ADC_NTC.elf: file format elf32-littlearm Sections: Idx Name Size VMA LMA File off Algn 0 .isr_vector 0000010c 08000000 08000000 00010000 2**0 CONTENTS, ALLOC, LOAD, READONLY, DATA 1 .text 00006138 08000110 08000110 00010110 2**3 CONTENTS, ALLOC, LOAD, READONLY, CODE 2 .rodata 0000040c 08006248 08006248 00016248 2**3 CONTENTS, ALLOC, LOAD, READONLY, DATA 3 .ARM.extab 00000000 08006654 08006654 000201dc 2**0 CONTENTS 4 .ARM 00000000 08006654 08006654 000201dc 2**0 CONTENTS 5 .preinit_array 00000000 08006654 08006654 000201dc 2**0 CONTENTS, ALLOC, LOAD, DATA 6 .init_array 00000004 08006654 08006654 00016654 2**2 CONTENTS, ALLOC, LOAD, DATA 7 .fini_array 00000004 08006658 08006658 00016658 2**2 CONTENTS, ALLOC, LOAD, DATA 8 .data 000001dc 20000000 0800665c 00020000 2**2 CONTENTS, ALLOC, LOAD, DATA 9 .bss 000000a8 200001dc 08006838 000201dc 2**2 ALLOC 10 ._user_heap_stack 00000604 20000284 08006838 00020284 2**0 ALLOC 11 .ARM.attributes 00000029 00000000 00000000 000201dc 2**0 CONTENTS, READONLY 12 .debug_info 0000726e 00000000 00000000 00020205 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 13 .debug_abbrev 00001b26 00000000 00000000 00027473 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 14 .debug_aranges 00000840 00000000 00000000 00028fa0 2**3 CONTENTS, READONLY, DEBUGGING, OCTETS 15 .debug_ranges 00000768 00000000 00000000 000297e0 2**3 CONTENTS, READONLY, DEBUGGING, OCTETS 16 .debug_macro 00018830 00000000 00000000 00029f48 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 17 .debug_line 00009d59 00000000 00000000 00042778 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 18 .debug_str 00088d0c 00000000 00000000 0004c4d1 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 19 .comment 00000050 00000000 00000000 000d51dd 2**0 CONTENTS, READONLY 20 .debug_frame 00003218 00000000 00000000 000d5230 2**2 CONTENTS, READONLY, DEBUGGING, OCTETS Disassembly of section .text: 08000110 <__do_global_dtors_aux>: 8000110: b510 push {r4, lr} 8000112: 4c05 ldr r4, [pc, #20] ; (8000128 <__do_global_dtors_aux+0x18>) 8000114: 7823 ldrb r3, [r4, #0] 8000116: b933 cbnz r3, 8000126 <__do_global_dtors_aux+0x16> 8000118: 4b04 ldr r3, [pc, #16] ; (800012c <__do_global_dtors_aux+0x1c>) 800011a: b113 cbz r3, 8000122 <__do_global_dtors_aux+0x12> 800011c: 4804 ldr r0, [pc, #16] ; (8000130 <__do_global_dtors_aux+0x20>) 800011e: f3af 8000 nop.w 8000122: 2301 movs r3, #1 8000124: 7023 strb r3, [r4, #0] 8000126: bd10 pop {r4, pc} 8000128: 200001dc .word 0x200001dc 800012c: 00000000 .word 0x00000000 8000130: 08006230 .word 0x08006230 08000134 : 8000134: b508 push {r3, lr} 8000136: 4b03 ldr r3, [pc, #12] ; (8000144 ) 8000138: b11b cbz r3, 8000142 800013a: 4903 ldr r1, [pc, #12] ; (8000148 ) 800013c: 4803 ldr r0, [pc, #12] ; (800014c ) 800013e: f3af 8000 nop.w 8000142: bd08 pop {r3, pc} 8000144: 00000000 .word 0x00000000 8000148: 200001e0 .word 0x200001e0 800014c: 08006230 .word 0x08006230 08000150 : 8000150: 4603 mov r3, r0 8000152: f813 2b01 ldrb.w r2, [r3], #1 8000156: 2a00 cmp r2, #0 8000158: d1fb bne.n 8000152 800015a: 1a18 subs r0, r3, r0 800015c: 3801 subs r0, #1 800015e: 4770 bx lr 08000160 <__aeabi_drsub>: 8000160: f081 4100 eor.w r1, r1, #2147483648 ; 0x80000000 8000164: e002 b.n 800016c <__adddf3> 8000166: bf00 nop 08000168 <__aeabi_dsub>: 8000168: f083 4300 eor.w r3, r3, #2147483648 ; 0x80000000 0800016c <__adddf3>: 800016c: b530 push {r4, r5, lr} 800016e: ea4f 0441 mov.w r4, r1, lsl #1 8000172: ea4f 0543 mov.w r5, r3, lsl #1 8000176: ea94 0f05 teq r4, r5 800017a: bf08 it eq 800017c: ea90 0f02 teqeq r0, r2 8000180: bf1f itttt ne 8000182: ea54 0c00 orrsne.w ip, r4, r0 8000186: ea55 0c02 orrsne.w ip, r5, r2 800018a: ea7f 5c64 mvnsne.w ip, r4, asr #21 800018e: ea7f 5c65 mvnsne.w ip, r5, asr #21 8000192: f000 80e2 beq.w 800035a <__adddf3+0x1ee> 8000196: ea4f 5454 mov.w r4, r4, lsr #21 800019a: ebd4 5555 rsbs r5, r4, r5, lsr #21 800019e: bfb8 it lt 80001a0: 426d neglt r5, r5 80001a2: dd0c ble.n 80001be <__adddf3+0x52> 80001a4: 442c add r4, r5 80001a6: ea80 0202 eor.w r2, r0, r2 80001aa: ea81 0303 eor.w r3, r1, r3 80001ae: ea82 0000 eor.w r0, r2, r0 80001b2: ea83 0101 eor.w r1, r3, r1 80001b6: ea80 0202 eor.w r2, r0, r2 80001ba: ea81 0303 eor.w r3, r1, r3 80001be: 2d36 cmp r5, #54 ; 0x36 80001c0: bf88 it hi 80001c2: bd30 pophi {r4, r5, pc} 80001c4: f011 4f00 tst.w r1, #2147483648 ; 0x80000000 80001c8: ea4f 3101 mov.w r1, r1, lsl #12 80001cc: f44f 1c80 mov.w ip, #1048576 ; 0x100000 80001d0: ea4c 3111 orr.w r1, ip, r1, lsr #12 80001d4: d002 beq.n 80001dc <__adddf3+0x70> 80001d6: 4240 negs r0, r0 80001d8: eb61 0141 sbc.w r1, r1, r1, lsl #1 80001dc: f013 4f00 tst.w r3, #2147483648 ; 0x80000000 80001e0: ea4f 3303 mov.w r3, r3, lsl #12 80001e4: ea4c 3313 orr.w r3, ip, r3, lsr #12 80001e8: d002 beq.n 80001f0 <__adddf3+0x84> 80001ea: 4252 negs r2, r2 80001ec: eb63 0343 sbc.w r3, r3, r3, lsl #1 80001f0: ea94 0f05 teq r4, r5 80001f4: f000 80a7 beq.w 8000346 <__adddf3+0x1da> 80001f8: f1a4 0401 sub.w r4, r4, #1 80001fc: f1d5 0e20 rsbs lr, r5, #32 8000200: db0d blt.n 800021e <__adddf3+0xb2> 8000202: fa02 fc0e lsl.w ip, r2, lr 8000206: fa22 f205 lsr.w r2, r2, r5 800020a: 1880 adds r0, r0, r2 800020c: f141 0100 adc.w r1, r1, #0 8000210: fa03 f20e lsl.w r2, r3, lr 8000214: 1880 adds r0, r0, r2 8000216: fa43 f305 asr.w r3, r3, r5 800021a: 4159 adcs r1, r3 800021c: e00e b.n 800023c <__adddf3+0xd0> 800021e: f1a5 0520 sub.w r5, r5, #32 8000222: f10e 0e20 add.w lr, lr, #32 8000226: 2a01 cmp r2, #1 8000228: fa03 fc0e lsl.w ip, r3, lr 800022c: bf28 it cs 800022e: f04c 0c02 orrcs.w ip, ip, #2 8000232: fa43 f305 asr.w r3, r3, r5 8000236: 18c0 adds r0, r0, r3 8000238: eb51 71e3 adcs.w r1, r1, r3, asr #31 800023c: f001 4500 and.w r5, r1, #2147483648 ; 0x80000000 8000240: d507 bpl.n 8000252 <__adddf3+0xe6> 8000242: f04f 0e00 mov.w lr, #0 8000246: f1dc 0c00 rsbs ip, ip, #0 800024a: eb7e 0000 sbcs.w r0, lr, r0 800024e: eb6e 0101 sbc.w r1, lr, r1 8000252: f5b1 1f80 cmp.w r1, #1048576 ; 0x100000 8000256: d31b bcc.n 8000290 <__adddf3+0x124> 8000258: f5b1 1f00 cmp.w r1, #2097152 ; 0x200000 800025c: d30c bcc.n 8000278 <__adddf3+0x10c> 800025e: 0849 lsrs r1, r1, #1 8000260: ea5f 0030 movs.w r0, r0, rrx 8000264: ea4f 0c3c mov.w ip, ip, rrx 8000268: f104 0401 add.w r4, r4, #1 800026c: ea4f 5244 mov.w r2, r4, lsl #21 8000270: f512 0f80 cmn.w r2, #4194304 ; 0x400000 8000274: f080 809a bcs.w 80003ac <__adddf3+0x240> 8000278: f1bc 4f00 cmp.w ip, #2147483648 ; 0x80000000 800027c: bf08 it eq 800027e: ea5f 0c50 movseq.w ip, r0, lsr #1 8000282: f150 0000 adcs.w r0, r0, #0 8000286: eb41 5104 adc.w r1, r1, r4, lsl #20 800028a: ea41 0105 orr.w r1, r1, r5 800028e: bd30 pop {r4, r5, pc} 8000290: ea5f 0c4c movs.w ip, ip, lsl #1 8000294: 4140 adcs r0, r0 8000296: eb41 0101 adc.w r1, r1, r1 800029a: 3c01 subs r4, #1 800029c: bf28 it cs 800029e: f5b1 1f80 cmpcs.w r1, #1048576 ; 0x100000 80002a2: d2e9 bcs.n 8000278 <__adddf3+0x10c> 80002a4: f091 0f00 teq r1, #0 80002a8: bf04 itt eq 80002aa: 4601 moveq r1, r0 80002ac: 2000 moveq r0, #0 80002ae: fab1 f381 clz r3, r1 80002b2: bf08 it eq 80002b4: 3320 addeq r3, #32 80002b6: f1a3 030b sub.w r3, r3, #11 80002ba: f1b3 0220 subs.w r2, r3, #32 80002be: da0c bge.n 80002da <__adddf3+0x16e> 80002c0: 320c adds r2, #12 80002c2: dd08 ble.n 80002d6 <__adddf3+0x16a> 80002c4: f102 0c14 add.w ip, r2, #20 80002c8: f1c2 020c rsb r2, r2, #12 80002cc: fa01 f00c lsl.w r0, r1, ip 80002d0: fa21 f102 lsr.w r1, r1, r2 80002d4: e00c b.n 80002f0 <__adddf3+0x184> 80002d6: f102 0214 add.w r2, r2, #20 80002da: bfd8 it le 80002dc: f1c2 0c20 rsble ip, r2, #32 80002e0: fa01 f102 lsl.w r1, r1, r2 80002e4: fa20 fc0c lsr.w ip, r0, ip 80002e8: bfdc itt le 80002ea: ea41 010c orrle.w r1, r1, ip 80002ee: 4090 lslle r0, r2 80002f0: 1ae4 subs r4, r4, r3 80002f2: bfa2 ittt ge 80002f4: eb01 5104 addge.w r1, r1, r4, lsl #20 80002f8: 4329 orrge r1, r5 80002fa: bd30 popge {r4, r5, pc} 80002fc: ea6f 0404 mvn.w r4, r4 8000300: 3c1f subs r4, #31 8000302: da1c bge.n 800033e <__adddf3+0x1d2> 8000304: 340c adds r4, #12 8000306: dc0e bgt.n 8000326 <__adddf3+0x1ba> 8000308: f104 0414 add.w r4, r4, #20 800030c: f1c4 0220 rsb r2, r4, #32 8000310: fa20 f004 lsr.w r0, r0, r4 8000314: fa01 f302 lsl.w r3, r1, r2 8000318: ea40 0003 orr.w r0, r0, r3 800031c: fa21 f304 lsr.w r3, r1, r4 8000320: ea45 0103 orr.w r1, r5, r3 8000324: bd30 pop {r4, r5, pc} 8000326: f1c4 040c rsb r4, r4, #12 800032a: f1c4 0220 rsb r2, r4, #32 800032e: fa20 f002 lsr.w r0, r0, r2 8000332: fa01 f304 lsl.w r3, r1, r4 8000336: ea40 0003 orr.w r0, r0, r3 800033a: 4629 mov r1, r5 800033c: bd30 pop {r4, r5, pc} 800033e: fa21 f004 lsr.w r0, r1, r4 8000342: 4629 mov r1, r5 8000344: bd30 pop {r4, r5, pc} 8000346: f094 0f00 teq r4, #0 800034a: f483 1380 eor.w r3, r3, #1048576 ; 0x100000 800034e: bf06 itte eq 8000350: f481 1180 eoreq.w r1, r1, #1048576 ; 0x100000 8000354: 3401 addeq r4, #1 8000356: 3d01 subne r5, #1 8000358: e74e b.n 80001f8 <__adddf3+0x8c> 800035a: ea7f 5c64 mvns.w ip, r4, asr #21 800035e: bf18 it ne 8000360: ea7f 5c65 mvnsne.w ip, r5, asr #21 8000364: d029 beq.n 80003ba <__adddf3+0x24e> 8000366: ea94 0f05 teq r4, r5 800036a: bf08 it eq 800036c: ea90 0f02 teqeq r0, r2 8000370: d005 beq.n 800037e <__adddf3+0x212> 8000372: ea54 0c00 orrs.w ip, r4, r0 8000376: bf04 itt eq 8000378: 4619 moveq r1, r3 800037a: 4610 moveq r0, r2 800037c: bd30 pop {r4, r5, pc} 800037e: ea91 0f03 teq r1, r3 8000382: bf1e ittt ne 8000384: 2100 movne r1, #0 8000386: 2000 movne r0, #0 8000388: bd30 popne {r4, r5, pc} 800038a: ea5f 5c54 movs.w ip, r4, lsr #21 800038e: d105 bne.n 800039c <__adddf3+0x230> 8000390: 0040 lsls r0, r0, #1 8000392: 4149 adcs r1, r1 8000394: bf28 it cs 8000396: f041 4100 orrcs.w r1, r1, #2147483648 ; 0x80000000 800039a: bd30 pop {r4, r5, pc} 800039c: f514 0480 adds.w r4, r4, #4194304 ; 0x400000 80003a0: bf3c itt cc 80003a2: f501 1180 addcc.w r1, r1, #1048576 ; 0x100000 80003a6: bd30 popcc {r4, r5, pc} 80003a8: f001 4500 and.w r5, r1, #2147483648 ; 0x80000000 80003ac: f045 41fe orr.w r1, r5, #2130706432 ; 0x7f000000 80003b0: f441 0170 orr.w r1, r1, #15728640 ; 0xf00000 80003b4: f04f 0000 mov.w r0, #0 80003b8: bd30 pop {r4, r5, pc} 80003ba: ea7f 5c64 mvns.w ip, r4, asr #21 80003be: bf1a itte ne 80003c0: 4619 movne r1, r3 80003c2: 4610 movne r0, r2 80003c4: ea7f 5c65 mvnseq.w ip, r5, asr #21 80003c8: bf1c itt ne 80003ca: 460b movne r3, r1 80003cc: 4602 movne r2, r0 80003ce: ea50 3401 orrs.w r4, r0, r1, lsl #12 80003d2: bf06 itte eq 80003d4: ea52 3503 orrseq.w r5, r2, r3, lsl #12 80003d8: ea91 0f03 teqeq r1, r3 80003dc: f441 2100 orrne.w r1, r1, #524288 ; 0x80000 80003e0: bd30 pop {r4, r5, pc} 80003e2: bf00 nop 080003e4 <__aeabi_ui2d>: 80003e4: f090 0f00 teq r0, #0 80003e8: bf04 itt eq 80003ea: 2100 moveq r1, #0 80003ec: 4770 bxeq lr 80003ee: b530 push {r4, r5, lr} 80003f0: f44f 6480 mov.w r4, #1024 ; 0x400 80003f4: f104 0432 add.w r4, r4, #50 ; 0x32 80003f8: f04f 0500 mov.w r5, #0 80003fc: f04f 0100 mov.w r1, #0 8000400: e750 b.n 80002a4 <__adddf3+0x138> 8000402: bf00 nop 08000404 <__aeabi_i2d>: 8000404: f090 0f00 teq r0, #0 8000408: bf04 itt eq 800040a: 2100 moveq r1, #0 800040c: 4770 bxeq lr 800040e: b530 push {r4, r5, lr} 8000410: f44f 6480 mov.w r4, #1024 ; 0x400 8000414: f104 0432 add.w r4, r4, #50 ; 0x32 8000418: f010 4500 ands.w r5, r0, #2147483648 ; 0x80000000 800041c: bf48 it mi 800041e: 4240 negmi r0, r0 8000420: f04f 0100 mov.w r1, #0 8000424: e73e b.n 80002a4 <__adddf3+0x138> 8000426: bf00 nop 08000428 <__aeabi_f2d>: 8000428: 0042 lsls r2, r0, #1 800042a: ea4f 01e2 mov.w r1, r2, asr #3 800042e: ea4f 0131 mov.w r1, r1, rrx 8000432: ea4f 7002 mov.w r0, r2, lsl #28 8000436: bf1f itttt ne 8000438: f012 437f andsne.w r3, r2, #4278190080 ; 0xff000000 800043c: f093 4f7f teqne r3, #4278190080 ; 0xff000000 8000440: f081 5160 eorne.w r1, r1, #939524096 ; 0x38000000 8000444: 4770 bxne lr 8000446: f032 427f bics.w r2, r2, #4278190080 ; 0xff000000 800044a: bf08 it eq 800044c: 4770 bxeq lr 800044e: f093 4f7f teq r3, #4278190080 ; 0xff000000 8000452: bf04 itt eq 8000454: f441 2100 orreq.w r1, r1, #524288 ; 0x80000 8000458: 4770 bxeq lr 800045a: b530 push {r4, r5, lr} 800045c: f44f 7460 mov.w r4, #896 ; 0x380 8000460: f001 4500 and.w r5, r1, #2147483648 ; 0x80000000 8000464: f021 4100 bic.w r1, r1, #2147483648 ; 0x80000000 8000468: e71c b.n 80002a4 <__adddf3+0x138> 800046a: bf00 nop 0800046c <__aeabi_ul2d>: 800046c: ea50 0201 orrs.w r2, r0, r1 8000470: bf08 it eq 8000472: 4770 bxeq lr 8000474: b530 push {r4, r5, lr} 8000476: f04f 0500 mov.w r5, #0 800047a: e00a b.n 8000492 <__aeabi_l2d+0x16> 0800047c <__aeabi_l2d>: 800047c: ea50 0201 orrs.w r2, r0, r1 8000480: bf08 it eq 8000482: 4770 bxeq lr 8000484: b530 push {r4, r5, lr} 8000486: f011 4500 ands.w r5, r1, #2147483648 ; 0x80000000 800048a: d502 bpl.n 8000492 <__aeabi_l2d+0x16> 800048c: 4240 negs r0, r0 800048e: eb61 0141 sbc.w r1, r1, r1, lsl #1 8000492: f44f 6480 mov.w r4, #1024 ; 0x400 8000496: f104 0432 add.w r4, r4, #50 ; 0x32 800049a: ea5f 5c91 movs.w ip, r1, lsr #22 800049e: f43f aed8 beq.w 8000252 <__adddf3+0xe6> 80004a2: f04f 0203 mov.w r2, #3 80004a6: ea5f 0cdc movs.w ip, ip, lsr #3 80004aa: bf18 it ne 80004ac: 3203 addne r2, #3 80004ae: ea5f 0cdc movs.w ip, ip, lsr #3 80004b2: bf18 it ne 80004b4: 3203 addne r2, #3 80004b6: eb02 02dc add.w r2, r2, ip, lsr #3 80004ba: f1c2 0320 rsb r3, r2, #32 80004be: fa00 fc03 lsl.w ip, r0, r3 80004c2: fa20 f002 lsr.w r0, r0, r2 80004c6: fa01 fe03 lsl.w lr, r1, r3 80004ca: ea40 000e orr.w r0, r0, lr 80004ce: fa21 f102 lsr.w r1, r1, r2 80004d2: 4414 add r4, r2 80004d4: e6bd b.n 8000252 <__adddf3+0xe6> 80004d6: bf00 nop 080004d8 <__aeabi_dmul>: 80004d8: b570 push {r4, r5, r6, lr} 80004da: f04f 0cff mov.w ip, #255 ; 0xff 80004de: f44c 6ce0 orr.w ip, ip, #1792 ; 0x700 80004e2: ea1c 5411 ands.w r4, ip, r1, lsr #20 80004e6: bf1d ittte ne 80004e8: ea1c 5513 andsne.w r5, ip, r3, lsr #20 80004ec: ea94 0f0c teqne r4, ip 80004f0: ea95 0f0c teqne r5, ip 80004f4: f000 f8de bleq 80006b4 <__aeabi_dmul+0x1dc> 80004f8: 442c add r4, r5 80004fa: ea81 0603 eor.w r6, r1, r3 80004fe: ea21 514c bic.w r1, r1, ip, lsl #21 8000502: ea23 534c bic.w r3, r3, ip, lsl #21 8000506: ea50 3501 orrs.w r5, r0, r1, lsl #12 800050a: bf18 it ne 800050c: ea52 3503 orrsne.w r5, r2, r3, lsl #12 8000510: f441 1180 orr.w r1, r1, #1048576 ; 0x100000 8000514: f443 1380 orr.w r3, r3, #1048576 ; 0x100000 8000518: d038 beq.n 800058c <__aeabi_dmul+0xb4> 800051a: fba0 ce02 umull ip, lr, r0, r2 800051e: f04f 0500 mov.w r5, #0 8000522: fbe1 e502 umlal lr, r5, r1, r2 8000526: f006 4200 and.w r2, r6, #2147483648 ; 0x80000000 800052a: fbe0 e503 umlal lr, r5, r0, r3 800052e: f04f 0600 mov.w r6, #0 8000532: fbe1 5603 umlal r5, r6, r1, r3 8000536: f09c 0f00 teq ip, #0 800053a: bf18 it ne 800053c: f04e 0e01 orrne.w lr, lr, #1 8000540: f1a4 04ff sub.w r4, r4, #255 ; 0xff 8000544: f5b6 7f00 cmp.w r6, #512 ; 0x200 8000548: f564 7440 sbc.w r4, r4, #768 ; 0x300 800054c: d204 bcs.n 8000558 <__aeabi_dmul+0x80> 800054e: ea5f 0e4e movs.w lr, lr, lsl #1 8000552: 416d adcs r5, r5 8000554: eb46 0606 adc.w r6, r6, r6 8000558: ea42 21c6 orr.w r1, r2, r6, lsl #11 800055c: ea41 5155 orr.w r1, r1, r5, lsr #21 8000560: ea4f 20c5 mov.w r0, r5, lsl #11 8000564: ea40 505e orr.w r0, r0, lr, lsr #21 8000568: ea4f 2ece mov.w lr, lr, lsl #11 800056c: f1b4 0cfd subs.w ip, r4, #253 ; 0xfd 8000570: bf88 it hi 8000572: f5bc 6fe0 cmphi.w ip, #1792 ; 0x700 8000576: d81e bhi.n 80005b6 <__aeabi_dmul+0xde> 8000578: f1be 4f00 cmp.w lr, #2147483648 ; 0x80000000 800057c: bf08 it eq 800057e: ea5f 0e50 movseq.w lr, r0, lsr #1 8000582: f150 0000 adcs.w r0, r0, #0 8000586: eb41 5104 adc.w r1, r1, r4, lsl #20 800058a: bd70 pop {r4, r5, r6, pc} 800058c: f006 4600 and.w r6, r6, #2147483648 ; 0x80000000 8000590: ea46 0101 orr.w r1, r6, r1 8000594: ea40 0002 orr.w r0, r0, r2 8000598: ea81 0103 eor.w r1, r1, r3 800059c: ebb4 045c subs.w r4, r4, ip, lsr #1 80005a0: bfc2 ittt gt 80005a2: ebd4 050c rsbsgt r5, r4, ip 80005a6: ea41 5104 orrgt.w r1, r1, r4, lsl #20 80005aa: bd70 popgt {r4, r5, r6, pc} 80005ac: f441 1180 orr.w r1, r1, #1048576 ; 0x100000 80005b0: f04f 0e00 mov.w lr, #0 80005b4: 3c01 subs r4, #1 80005b6: f300 80ab bgt.w 8000710 <__aeabi_dmul+0x238> 80005ba: f114 0f36 cmn.w r4, #54 ; 0x36 80005be: bfde ittt le 80005c0: 2000 movle r0, #0 80005c2: f001 4100 andle.w r1, r1, #2147483648 ; 0x80000000 80005c6: bd70 pople {r4, r5, r6, pc} 80005c8: f1c4 0400 rsb r4, r4, #0 80005cc: 3c20 subs r4, #32 80005ce: da35 bge.n 800063c <__aeabi_dmul+0x164> 80005d0: 340c adds r4, #12 80005d2: dc1b bgt.n 800060c <__aeabi_dmul+0x134> 80005d4: f104 0414 add.w r4, r4, #20 80005d8: f1c4 0520 rsb r5, r4, #32 80005dc: fa00 f305 lsl.w r3, r0, r5 80005e0: fa20 f004 lsr.w r0, r0, r4 80005e4: fa01 f205 lsl.w r2, r1, r5 80005e8: ea40 0002 orr.w r0, r0, r2 80005ec: f001 4200 and.w r2, r1, #2147483648 ; 0x80000000 80005f0: f021 4100 bic.w r1, r1, #2147483648 ; 0x80000000 80005f4: eb10 70d3 adds.w r0, r0, r3, lsr #31 80005f8: fa21 f604 lsr.w r6, r1, r4 80005fc: eb42 0106 adc.w r1, r2, r6 8000600: ea5e 0e43 orrs.w lr, lr, r3, lsl #1 8000604: bf08 it eq 8000606: ea20 70d3 biceq.w r0, r0, r3, lsr #31 800060a: bd70 pop {r4, r5, r6, pc} 800060c: f1c4 040c rsb r4, r4, #12 8000610: f1c4 0520 rsb r5, r4, #32 8000614: fa00 f304 lsl.w r3, r0, r4 8000618: fa20 f005 lsr.w r0, r0, r5 800061c: fa01 f204 lsl.w r2, r1, r4 8000620: ea40 0002 orr.w r0, r0, r2 8000624: f001 4100 and.w r1, r1, #2147483648 ; 0x80000000 8000628: eb10 70d3 adds.w r0, r0, r3, lsr #31 800062c: f141 0100 adc.w r1, r1, #0 8000630: ea5e 0e43 orrs.w lr, lr, r3, lsl #1 8000634: bf08 it eq 8000636: ea20 70d3 biceq.w r0, r0, r3, lsr #31 800063a: bd70 pop {r4, r5, r6, pc} 800063c: f1c4 0520 rsb r5, r4, #32 8000640: fa00 f205 lsl.w r2, r0, r5 8000644: ea4e 0e02 orr.w lr, lr, r2 8000648: fa20 f304 lsr.w r3, r0, r4 800064c: fa01 f205 lsl.w r2, r1, r5 8000650: ea43 0302 orr.w r3, r3, r2 8000654: fa21 f004 lsr.w r0, r1, r4 8000658: f001 4100 and.w r1, r1, #2147483648 ; 0x80000000 800065c: fa21 f204 lsr.w r2, r1, r4 8000660: ea20 0002 bic.w r0, r0, r2 8000664: eb00 70d3 add.w r0, r0, r3, lsr #31 8000668: ea5e 0e43 orrs.w lr, lr, r3, lsl #1 800066c: bf08 it eq 800066e: ea20 70d3 biceq.w r0, r0, r3, lsr #31 8000672: bd70 pop {r4, r5, r6, pc} 8000674: f094 0f00 teq r4, #0 8000678: d10f bne.n 800069a <__aeabi_dmul+0x1c2> 800067a: f001 4600 and.w r6, r1, #2147483648 ; 0x80000000 800067e: 0040 lsls r0, r0, #1 8000680: eb41 0101 adc.w r1, r1, r1 8000684: f411 1f80 tst.w r1, #1048576 ; 0x100000 8000688: bf08 it eq 800068a: 3c01 subeq r4, #1 800068c: d0f7 beq.n 800067e <__aeabi_dmul+0x1a6> 800068e: ea41 0106 orr.w r1, r1, r6 8000692: f095 0f00 teq r5, #0 8000696: bf18 it ne 8000698: 4770 bxne lr 800069a: f003 4600 and.w r6, r3, #2147483648 ; 0x80000000 800069e: 0052 lsls r2, r2, #1 80006a0: eb43 0303 adc.w r3, r3, r3 80006a4: f413 1f80 tst.w r3, #1048576 ; 0x100000 80006a8: bf08 it eq 80006aa: 3d01 subeq r5, #1 80006ac: d0f7 beq.n 800069e <__aeabi_dmul+0x1c6> 80006ae: ea43 0306 orr.w r3, r3, r6 80006b2: 4770 bx lr 80006b4: ea94 0f0c teq r4, ip 80006b8: ea0c 5513 and.w r5, ip, r3, lsr #20 80006bc: bf18 it ne 80006be: ea95 0f0c teqne r5, ip 80006c2: d00c beq.n 80006de <__aeabi_dmul+0x206> 80006c4: ea50 0641 orrs.w r6, r0, r1, lsl #1 80006c8: bf18 it ne 80006ca: ea52 0643 orrsne.w r6, r2, r3, lsl #1 80006ce: d1d1 bne.n 8000674 <__aeabi_dmul+0x19c> 80006d0: ea81 0103 eor.w r1, r1, r3 80006d4: f001 4100 and.w r1, r1, #2147483648 ; 0x80000000 80006d8: f04f 0000 mov.w r0, #0 80006dc: bd70 pop {r4, r5, r6, pc} 80006de: ea50 0641 orrs.w r6, r0, r1, lsl #1 80006e2: bf06 itte eq 80006e4: 4610 moveq r0, r2 80006e6: 4619 moveq r1, r3 80006e8: ea52 0643 orrsne.w r6, r2, r3, lsl #1 80006ec: d019 beq.n 8000722 <__aeabi_dmul+0x24a> 80006ee: ea94 0f0c teq r4, ip 80006f2: d102 bne.n 80006fa <__aeabi_dmul+0x222> 80006f4: ea50 3601 orrs.w r6, r0, r1, lsl #12 80006f8: d113 bne.n 8000722 <__aeabi_dmul+0x24a> 80006fa: ea95 0f0c teq r5, ip 80006fe: d105 bne.n 800070c <__aeabi_dmul+0x234> 8000700: ea52 3603 orrs.w r6, r2, r3, lsl #12 8000704: bf1c itt ne 8000706: 4610 movne r0, r2 8000708: 4619 movne r1, r3 800070a: d10a bne.n 8000722 <__aeabi_dmul+0x24a> 800070c: ea81 0103 eor.w r1, r1, r3 8000710: f001 4100 and.w r1, r1, #2147483648 ; 0x80000000 8000714: f041 41fe orr.w r1, r1, #2130706432 ; 0x7f000000 8000718: f441 0170 orr.w r1, r1, #15728640 ; 0xf00000 800071c: f04f 0000 mov.w r0, #0 8000720: bd70 pop {r4, r5, r6, pc} 8000722: f041 41fe orr.w r1, r1, #2130706432 ; 0x7f000000 8000726: f441 0178 orr.w r1, r1, #16252928 ; 0xf80000 800072a: bd70 pop {r4, r5, r6, pc} 0800072c <__aeabi_ddiv>: 800072c: b570 push {r4, r5, r6, lr} 800072e: f04f 0cff mov.w ip, #255 ; 0xff 8000732: f44c 6ce0 orr.w ip, ip, #1792 ; 0x700 8000736: ea1c 5411 ands.w r4, ip, r1, lsr #20 800073a: bf1d ittte ne 800073c: ea1c 5513 andsne.w r5, ip, r3, lsr #20 8000740: ea94 0f0c teqne r4, ip 8000744: ea95 0f0c teqne r5, ip 8000748: f000 f8a7 bleq 800089a <__aeabi_ddiv+0x16e> 800074c: eba4 0405 sub.w r4, r4, r5 8000750: ea81 0e03 eor.w lr, r1, r3 8000754: ea52 3503 orrs.w r5, r2, r3, lsl #12 8000758: ea4f 3101 mov.w r1, r1, lsl #12 800075c: f000 8088 beq.w 8000870 <__aeabi_ddiv+0x144> 8000760: ea4f 3303 mov.w r3, r3, lsl #12 8000764: f04f 5580 mov.w r5, #268435456 ; 0x10000000 8000768: ea45 1313 orr.w r3, r5, r3, lsr #4 800076c: ea43 6312 orr.w r3, r3, r2, lsr #24 8000770: ea4f 2202 mov.w r2, r2, lsl #8 8000774: ea45 1511 orr.w r5, r5, r1, lsr #4 8000778: ea45 6510 orr.w r5, r5, r0, lsr #24 800077c: ea4f 2600 mov.w r6, r0, lsl #8 8000780: f00e 4100 and.w r1, lr, #2147483648 ; 0x80000000 8000784: 429d cmp r5, r3 8000786: bf08 it eq 8000788: 4296 cmpeq r6, r2 800078a: f144 04fd adc.w r4, r4, #253 ; 0xfd 800078e: f504 7440 add.w r4, r4, #768 ; 0x300 8000792: d202 bcs.n 800079a <__aeabi_ddiv+0x6e> 8000794: 085b lsrs r3, r3, #1 8000796: ea4f 0232 mov.w r2, r2, rrx 800079a: 1ab6 subs r6, r6, r2 800079c: eb65 0503 sbc.w r5, r5, r3 80007a0: 085b lsrs r3, r3, #1 80007a2: ea4f 0232 mov.w r2, r2, rrx 80007a6: f44f 1080 mov.w r0, #1048576 ; 0x100000 80007aa: f44f 2c00 mov.w ip, #524288 ; 0x80000 80007ae: ebb6 0e02 subs.w lr, r6, r2 80007b2: eb75 0e03 sbcs.w lr, r5, r3 80007b6: bf22 ittt cs 80007b8: 1ab6 subcs r6, r6, r2 80007ba: 4675 movcs r5, lr 80007bc: ea40 000c orrcs.w r0, r0, ip 80007c0: 085b lsrs r3, r3, #1 80007c2: ea4f 0232 mov.w r2, r2, rrx 80007c6: ebb6 0e02 subs.w lr, r6, r2 80007ca: eb75 0e03 sbcs.w lr, r5, r3 80007ce: bf22 ittt cs 80007d0: 1ab6 subcs r6, r6, r2 80007d2: 4675 movcs r5, lr 80007d4: ea40 005c orrcs.w r0, r0, ip, lsr #1 80007d8: 085b lsrs r3, r3, #1 80007da: ea4f 0232 mov.w r2, r2, rrx 80007de: ebb6 0e02 subs.w lr, r6, r2 80007e2: eb75 0e03 sbcs.w lr, r5, r3 80007e6: bf22 ittt cs 80007e8: 1ab6 subcs r6, r6, r2 80007ea: 4675 movcs r5, lr 80007ec: ea40 009c orrcs.w r0, r0, ip, lsr #2 80007f0: 085b lsrs r3, r3, #1 80007f2: ea4f 0232 mov.w r2, r2, rrx 80007f6: ebb6 0e02 subs.w lr, r6, r2 80007fa: eb75 0e03 sbcs.w lr, r5, r3 80007fe: bf22 ittt cs 8000800: 1ab6 subcs r6, r6, r2 8000802: 4675 movcs r5, lr 8000804: ea40 00dc orrcs.w r0, r0, ip, lsr #3 8000808: ea55 0e06 orrs.w lr, r5, r6 800080c: d018 beq.n 8000840 <__aeabi_ddiv+0x114> 800080e: ea4f 1505 mov.w r5, r5, lsl #4 8000812: ea45 7516 orr.w r5, r5, r6, lsr #28 8000816: ea4f 1606 mov.w r6, r6, lsl #4 800081a: ea4f 03c3 mov.w r3, r3, lsl #3 800081e: ea43 7352 orr.w r3, r3, r2, lsr #29 8000822: ea4f 02c2 mov.w r2, r2, lsl #3 8000826: ea5f 1c1c movs.w ip, ip, lsr #4 800082a: d1c0 bne.n 80007ae <__aeabi_ddiv+0x82> 800082c: f411 1f80 tst.w r1, #1048576 ; 0x100000 8000830: d10b bne.n 800084a <__aeabi_ddiv+0x11e> 8000832: ea41 0100 orr.w r1, r1, r0 8000836: f04f 0000 mov.w r0, #0 800083a: f04f 4c00 mov.w ip, #2147483648 ; 0x80000000 800083e: e7b6 b.n 80007ae <__aeabi_ddiv+0x82> 8000840: f411 1f80 tst.w r1, #1048576 ; 0x100000 8000844: bf04 itt eq 8000846: 4301 orreq r1, r0 8000848: 2000 moveq r0, #0 800084a: f1b4 0cfd subs.w ip, r4, #253 ; 0xfd 800084e: bf88 it hi 8000850: f5bc 6fe0 cmphi.w ip, #1792 ; 0x700 8000854: f63f aeaf bhi.w 80005b6 <__aeabi_dmul+0xde> 8000858: ebb5 0c03 subs.w ip, r5, r3 800085c: bf04 itt eq 800085e: ebb6 0c02 subseq.w ip, r6, r2 8000862: ea5f 0c50 movseq.w ip, r0, lsr #1 8000866: f150 0000 adcs.w r0, r0, #0 800086a: eb41 5104 adc.w r1, r1, r4, lsl #20 800086e: bd70 pop {r4, r5, r6, pc} 8000870: f00e 4e00 and.w lr, lr, #2147483648 ; 0x80000000 8000874: ea4e 3111 orr.w r1, lr, r1, lsr #12 8000878: eb14 045c adds.w r4, r4, ip, lsr #1 800087c: bfc2 ittt gt 800087e: ebd4 050c rsbsgt r5, r4, ip 8000882: ea41 5104 orrgt.w r1, r1, r4, lsl #20 8000886: bd70 popgt {r4, r5, r6, pc} 8000888: f441 1180 orr.w r1, r1, #1048576 ; 0x100000 800088c: f04f 0e00 mov.w lr, #0 8000890: 3c01 subs r4, #1 8000892: e690 b.n 80005b6 <__aeabi_dmul+0xde> 8000894: ea45 0e06 orr.w lr, r5, r6 8000898: e68d b.n 80005b6 <__aeabi_dmul+0xde> 800089a: ea0c 5513 and.w r5, ip, r3, lsr #20 800089e: ea94 0f0c teq r4, ip 80008a2: bf08 it eq 80008a4: ea95 0f0c teqeq r5, ip 80008a8: f43f af3b beq.w 8000722 <__aeabi_dmul+0x24a> 80008ac: ea94 0f0c teq r4, ip 80008b0: d10a bne.n 80008c8 <__aeabi_ddiv+0x19c> 80008b2: ea50 3401 orrs.w r4, r0, r1, lsl #12 80008b6: f47f af34 bne.w 8000722 <__aeabi_dmul+0x24a> 80008ba: ea95 0f0c teq r5, ip 80008be: f47f af25 bne.w 800070c <__aeabi_dmul+0x234> 80008c2: 4610 mov r0, r2 80008c4: 4619 mov r1, r3 80008c6: e72c b.n 8000722 <__aeabi_dmul+0x24a> 80008c8: ea95 0f0c teq r5, ip 80008cc: d106 bne.n 80008dc <__aeabi_ddiv+0x1b0> 80008ce: ea52 3503 orrs.w r5, r2, r3, lsl #12 80008d2: f43f aefd beq.w 80006d0 <__aeabi_dmul+0x1f8> 80008d6: 4610 mov r0, r2 80008d8: 4619 mov r1, r3 80008da: e722 b.n 8000722 <__aeabi_dmul+0x24a> 80008dc: ea50 0641 orrs.w r6, r0, r1, lsl #1 80008e0: bf18 it ne 80008e2: ea52 0643 orrsne.w r6, r2, r3, lsl #1 80008e6: f47f aec5 bne.w 8000674 <__aeabi_dmul+0x19c> 80008ea: ea50 0441 orrs.w r4, r0, r1, lsl #1 80008ee: f47f af0d bne.w 800070c <__aeabi_dmul+0x234> 80008f2: ea52 0543 orrs.w r5, r2, r3, lsl #1 80008f6: f47f aeeb bne.w 80006d0 <__aeabi_dmul+0x1f8> 80008fa: e712 b.n 8000722 <__aeabi_dmul+0x24a> 080008fc <__gedf2>: 80008fc: f04f 3cff mov.w ip, #4294967295 8000900: e006 b.n 8000910 <__cmpdf2+0x4> 8000902: bf00 nop 08000904 <__ledf2>: 8000904: f04f 0c01 mov.w ip, #1 8000908: e002 b.n 8000910 <__cmpdf2+0x4> 800090a: bf00 nop 0800090c <__cmpdf2>: 800090c: f04f 0c01 mov.w ip, #1 8000910: f84d cd04 str.w ip, [sp, #-4]! 8000914: ea4f 0c41 mov.w ip, r1, lsl #1 8000918: ea7f 5c6c mvns.w ip, ip, asr #21 800091c: ea4f 0c43 mov.w ip, r3, lsl #1 8000920: bf18 it ne 8000922: ea7f 5c6c mvnsne.w ip, ip, asr #21 8000926: d01b beq.n 8000960 <__cmpdf2+0x54> 8000928: b001 add sp, #4 800092a: ea50 0c41 orrs.w ip, r0, r1, lsl #1 800092e: bf0c ite eq 8000930: ea52 0c43 orrseq.w ip, r2, r3, lsl #1 8000934: ea91 0f03 teqne r1, r3 8000938: bf02 ittt eq 800093a: ea90 0f02 teqeq r0, r2 800093e: 2000 moveq r0, #0 8000940: 4770 bxeq lr 8000942: f110 0f00 cmn.w r0, #0 8000946: ea91 0f03 teq r1, r3 800094a: bf58 it pl 800094c: 4299 cmppl r1, r3 800094e: bf08 it eq 8000950: 4290 cmpeq r0, r2 8000952: bf2c ite cs 8000954: 17d8 asrcs r0, r3, #31 8000956: ea6f 70e3 mvncc.w r0, r3, asr #31 800095a: f040 0001 orr.w r0, r0, #1 800095e: 4770 bx lr 8000960: ea4f 0c41 mov.w ip, r1, lsl #1 8000964: ea7f 5c6c mvns.w ip, ip, asr #21 8000968: d102 bne.n 8000970 <__cmpdf2+0x64> 800096a: ea50 3c01 orrs.w ip, r0, r1, lsl #12 800096e: d107 bne.n 8000980 <__cmpdf2+0x74> 8000970: ea4f 0c43 mov.w ip, r3, lsl #1 8000974: ea7f 5c6c mvns.w ip, ip, asr #21 8000978: d1d6 bne.n 8000928 <__cmpdf2+0x1c> 800097a: ea52 3c03 orrs.w ip, r2, r3, lsl #12 800097e: d0d3 beq.n 8000928 <__cmpdf2+0x1c> 8000980: f85d 0b04 ldr.w r0, [sp], #4 8000984: 4770 bx lr 8000986: bf00 nop 08000988 <__aeabi_cdrcmple>: 8000988: 4684 mov ip, r0 800098a: 4610 mov r0, r2 800098c: 4662 mov r2, ip 800098e: 468c mov ip, r1 8000990: 4619 mov r1, r3 8000992: 4663 mov r3, ip 8000994: e000 b.n 8000998 <__aeabi_cdcmpeq> 8000996: bf00 nop 08000998 <__aeabi_cdcmpeq>: 8000998: b501 push {r0, lr} 800099a: f7ff ffb7 bl 800090c <__cmpdf2> 800099e: 2800 cmp r0, #0 80009a0: bf48 it mi 80009a2: f110 0f00 cmnmi.w r0, #0 80009a6: bd01 pop {r0, pc} 080009a8 <__aeabi_dcmpeq>: 80009a8: f84d ed08 str.w lr, [sp, #-8]! 80009ac: f7ff fff4 bl 8000998 <__aeabi_cdcmpeq> 80009b0: bf0c ite eq 80009b2: 2001 moveq r0, #1 80009b4: 2000 movne r0, #0 80009b6: f85d fb08 ldr.w pc, [sp], #8 80009ba: bf00 nop 080009bc <__aeabi_dcmplt>: 80009bc: f84d ed08 str.w lr, [sp, #-8]! 80009c0: f7ff ffea bl 8000998 <__aeabi_cdcmpeq> 80009c4: bf34 ite cc 80009c6: 2001 movcc r0, #1 80009c8: 2000 movcs r0, #0 80009ca: f85d fb08 ldr.w pc, [sp], #8 80009ce: bf00 nop 080009d0 <__aeabi_dcmple>: 80009d0: f84d ed08 str.w lr, [sp, #-8]! 80009d4: f7ff ffe0 bl 8000998 <__aeabi_cdcmpeq> 80009d8: bf94 ite ls 80009da: 2001 movls r0, #1 80009dc: 2000 movhi r0, #0 80009de: f85d fb08 ldr.w pc, [sp], #8 80009e2: bf00 nop 080009e4 <__aeabi_dcmpge>: 80009e4: f84d ed08 str.w lr, [sp, #-8]! 80009e8: f7ff ffce bl 8000988 <__aeabi_cdrcmple> 80009ec: bf94 ite ls 80009ee: 2001 movls r0, #1 80009f0: 2000 movhi r0, #0 80009f2: f85d fb08 ldr.w pc, [sp], #8 80009f6: bf00 nop 080009f8 <__aeabi_dcmpgt>: 80009f8: f84d ed08 str.w lr, [sp, #-8]! 80009fc: f7ff ffc4 bl 8000988 <__aeabi_cdrcmple> 8000a00: bf34 ite cc 8000a02: 2001 movcc r0, #1 8000a04: 2000 movcs r0, #0 8000a06: f85d fb08 ldr.w pc, [sp], #8 8000a0a: bf00 nop 08000a0c <__aeabi_dcmpun>: 8000a0c: ea4f 0c41 mov.w ip, r1, lsl #1 8000a10: ea7f 5c6c mvns.w ip, ip, asr #21 8000a14: d102 bne.n 8000a1c <__aeabi_dcmpun+0x10> 8000a16: ea50 3c01 orrs.w ip, r0, r1, lsl #12 8000a1a: d10a bne.n 8000a32 <__aeabi_dcmpun+0x26> 8000a1c: ea4f 0c43 mov.w ip, r3, lsl #1 8000a20: ea7f 5c6c mvns.w ip, ip, asr #21 8000a24: d102 bne.n 8000a2c <__aeabi_dcmpun+0x20> 8000a26: ea52 3c03 orrs.w ip, r2, r3, lsl #12 8000a2a: d102 bne.n 8000a32 <__aeabi_dcmpun+0x26> 8000a2c: f04f 0000 mov.w r0, #0 8000a30: 4770 bx lr 8000a32: f04f 0001 mov.w r0, #1 8000a36: 4770 bx lr 08000a38 <__aeabi_d2iz>: 8000a38: ea4f 0241 mov.w r2, r1, lsl #1 8000a3c: f512 1200 adds.w r2, r2, #2097152 ; 0x200000 8000a40: d215 bcs.n 8000a6e <__aeabi_d2iz+0x36> 8000a42: d511 bpl.n 8000a68 <__aeabi_d2iz+0x30> 8000a44: f46f 7378 mvn.w r3, #992 ; 0x3e0 8000a48: ebb3 5262 subs.w r2, r3, r2, asr #21 8000a4c: d912 bls.n 8000a74 <__aeabi_d2iz+0x3c> 8000a4e: ea4f 23c1 mov.w r3, r1, lsl #11 8000a52: f043 4300 orr.w r3, r3, #2147483648 ; 0x80000000 8000a56: ea43 5350 orr.w r3, r3, r0, lsr #21 8000a5a: f011 4f00 tst.w r1, #2147483648 ; 0x80000000 8000a5e: fa23 f002 lsr.w r0, r3, r2 8000a62: bf18 it ne 8000a64: 4240 negne r0, r0 8000a66: 4770 bx lr 8000a68: f04f 0000 mov.w r0, #0 8000a6c: 4770 bx lr 8000a6e: ea50 3001 orrs.w r0, r0, r1, lsl #12 8000a72: d105 bne.n 8000a80 <__aeabi_d2iz+0x48> 8000a74: f011 4000 ands.w r0, r1, #2147483648 ; 0x80000000 8000a78: bf08 it eq 8000a7a: f06f 4000 mvneq.w r0, #2147483648 ; 0x80000000 8000a7e: 4770 bx lr 8000a80: f04f 0000 mov.w r0, #0 8000a84: 4770 bx lr 8000a86: bf00 nop 08000a88 <__aeabi_d2f>: 8000a88: ea4f 0241 mov.w r2, r1, lsl #1 8000a8c: f1b2 43e0 subs.w r3, r2, #1879048192 ; 0x70000000 8000a90: bf24 itt cs 8000a92: f5b3 1c00 subscs.w ip, r3, #2097152 ; 0x200000 8000a96: f1dc 5cfe rsbscs ip, ip, #532676608 ; 0x1fc00000 8000a9a: d90d bls.n 8000ab8 <__aeabi_d2f+0x30> 8000a9c: f001 4c00 and.w ip, r1, #2147483648 ; 0x80000000 8000aa0: ea4f 02c0 mov.w r2, r0, lsl #3 8000aa4: ea4c 7050 orr.w r0, ip, r0, lsr #29 8000aa8: f1b2 4f00 cmp.w r2, #2147483648 ; 0x80000000 8000aac: eb40 0083 adc.w r0, r0, r3, lsl #2 8000ab0: bf08 it eq 8000ab2: f020 0001 biceq.w r0, r0, #1 8000ab6: 4770 bx lr 8000ab8: f011 4f80 tst.w r1, #1073741824 ; 0x40000000 8000abc: d121 bne.n 8000b02 <__aeabi_d2f+0x7a> 8000abe: f113 7238 adds.w r2, r3, #48234496 ; 0x2e00000 8000ac2: bfbc itt lt 8000ac4: f001 4000 andlt.w r0, r1, #2147483648 ; 0x80000000 8000ac8: 4770 bxlt lr 8000aca: f441 1180 orr.w r1, r1, #1048576 ; 0x100000 8000ace: ea4f 5252 mov.w r2, r2, lsr #21 8000ad2: f1c2 0218 rsb r2, r2, #24 8000ad6: f1c2 0c20 rsb ip, r2, #32 8000ada: fa10 f30c lsls.w r3, r0, ip 8000ade: fa20 f002 lsr.w r0, r0, r2 8000ae2: bf18 it ne 8000ae4: f040 0001 orrne.w r0, r0, #1 8000ae8: ea4f 23c1 mov.w r3, r1, lsl #11 8000aec: ea4f 23d3 mov.w r3, r3, lsr #11 8000af0: fa03 fc0c lsl.w ip, r3, ip 8000af4: ea40 000c orr.w r0, r0, ip 8000af8: fa23 f302 lsr.w r3, r3, r2 8000afc: ea4f 0343 mov.w r3, r3, lsl #1 8000b00: e7cc b.n 8000a9c <__aeabi_d2f+0x14> 8000b02: ea7f 5362 mvns.w r3, r2, asr #21 8000b06: d107 bne.n 8000b18 <__aeabi_d2f+0x90> 8000b08: ea50 3301 orrs.w r3, r0, r1, lsl #12 8000b0c: bf1e ittt ne 8000b0e: f04f 40fe movne.w r0, #2130706432 ; 0x7f000000 8000b12: f440 0040 orrne.w r0, r0, #12582912 ; 0xc00000 8000b16: 4770 bxne lr 8000b18: f001 4000 and.w r0, r1, #2147483648 ; 0x80000000 8000b1c: f040 40fe orr.w r0, r0, #2130706432 ; 0x7f000000 8000b20: f440 0000 orr.w r0, r0, #8388608 ; 0x800000 8000b24: 4770 bx lr 8000b26: bf00 nop 08000b28 <__aeabi_frsub>: 8000b28: f080 4000 eor.w r0, r0, #2147483648 ; 0x80000000 8000b2c: e002 b.n 8000b34 <__addsf3> 8000b2e: bf00 nop 08000b30 <__aeabi_fsub>: 8000b30: f081 4100 eor.w r1, r1, #2147483648 ; 0x80000000 08000b34 <__addsf3>: 8000b34: 0042 lsls r2, r0, #1 8000b36: bf1f itttt ne 8000b38: ea5f 0341 movsne.w r3, r1, lsl #1 8000b3c: ea92 0f03 teqne r2, r3 8000b40: ea7f 6c22 mvnsne.w ip, r2, asr #24 8000b44: ea7f 6c23 mvnsne.w ip, r3, asr #24 8000b48: d06a beq.n 8000c20 <__addsf3+0xec> 8000b4a: ea4f 6212 mov.w r2, r2, lsr #24 8000b4e: ebd2 6313 rsbs r3, r2, r3, lsr #24 8000b52: bfc1 itttt gt 8000b54: 18d2 addgt r2, r2, r3 8000b56: 4041 eorgt r1, r0 8000b58: 4048 eorgt r0, r1 8000b5a: 4041 eorgt r1, r0 8000b5c: bfb8 it lt 8000b5e: 425b neglt r3, r3 8000b60: 2b19 cmp r3, #25 8000b62: bf88 it hi 8000b64: 4770 bxhi lr 8000b66: f010 4f00 tst.w r0, #2147483648 ; 0x80000000 8000b6a: f440 0000 orr.w r0, r0, #8388608 ; 0x800000 8000b6e: f020 407f bic.w r0, r0, #4278190080 ; 0xff000000 8000b72: bf18 it ne 8000b74: 4240 negne r0, r0 8000b76: f011 4f00 tst.w r1, #2147483648 ; 0x80000000 8000b7a: f441 0100 orr.w r1, r1, #8388608 ; 0x800000 8000b7e: f021 417f bic.w r1, r1, #4278190080 ; 0xff000000 8000b82: bf18 it ne 8000b84: 4249 negne r1, r1 8000b86: ea92 0f03 teq r2, r3 8000b8a: d03f beq.n 8000c0c <__addsf3+0xd8> 8000b8c: f1a2 0201 sub.w r2, r2, #1 8000b90: fa41 fc03 asr.w ip, r1, r3 8000b94: eb10 000c adds.w r0, r0, ip 8000b98: f1c3 0320 rsb r3, r3, #32 8000b9c: fa01 f103 lsl.w r1, r1, r3 8000ba0: f000 4300 and.w r3, r0, #2147483648 ; 0x80000000 8000ba4: d502 bpl.n 8000bac <__addsf3+0x78> 8000ba6: 4249 negs r1, r1 8000ba8: eb60 0040 sbc.w r0, r0, r0, lsl #1 8000bac: f5b0 0f00 cmp.w r0, #8388608 ; 0x800000 8000bb0: d313 bcc.n 8000bda <__addsf3+0xa6> 8000bb2: f1b0 7f80 cmp.w r0, #16777216 ; 0x1000000 8000bb6: d306 bcc.n 8000bc6 <__addsf3+0x92> 8000bb8: 0840 lsrs r0, r0, #1 8000bba: ea4f 0131 mov.w r1, r1, rrx 8000bbe: f102 0201 add.w r2, r2, #1 8000bc2: 2afe cmp r2, #254 ; 0xfe 8000bc4: d251 bcs.n 8000c6a <__addsf3+0x136> 8000bc6: f1b1 4f00 cmp.w r1, #2147483648 ; 0x80000000 8000bca: eb40 50c2 adc.w r0, r0, r2, lsl #23 8000bce: bf08 it eq 8000bd0: f020 0001 biceq.w r0, r0, #1 8000bd4: ea40 0003 orr.w r0, r0, r3 8000bd8: 4770 bx lr 8000bda: 0049 lsls r1, r1, #1 8000bdc: eb40 0000 adc.w r0, r0, r0 8000be0: 3a01 subs r2, #1 8000be2: bf28 it cs 8000be4: f5b0 0f00 cmpcs.w r0, #8388608 ; 0x800000 8000be8: d2ed bcs.n 8000bc6 <__addsf3+0x92> 8000bea: fab0 fc80 clz ip, r0 8000bee: f1ac 0c08 sub.w ip, ip, #8 8000bf2: ebb2 020c subs.w r2, r2, ip 8000bf6: fa00 f00c lsl.w r0, r0, ip 8000bfa: bfaa itet ge 8000bfc: eb00 50c2 addge.w r0, r0, r2, lsl #23 8000c00: 4252 neglt r2, r2 8000c02: 4318 orrge r0, r3 8000c04: bfbc itt lt 8000c06: 40d0 lsrlt r0, r2 8000c08: 4318 orrlt r0, r3 8000c0a: 4770 bx lr 8000c0c: f092 0f00 teq r2, #0 8000c10: f481 0100 eor.w r1, r1, #8388608 ; 0x800000 8000c14: bf06 itte eq 8000c16: f480 0000 eoreq.w r0, r0, #8388608 ; 0x800000 8000c1a: 3201 addeq r2, #1 8000c1c: 3b01 subne r3, #1 8000c1e: e7b5 b.n 8000b8c <__addsf3+0x58> 8000c20: ea4f 0341 mov.w r3, r1, lsl #1 8000c24: ea7f 6c22 mvns.w ip, r2, asr #24 8000c28: bf18 it ne 8000c2a: ea7f 6c23 mvnsne.w ip, r3, asr #24 8000c2e: d021 beq.n 8000c74 <__addsf3+0x140> 8000c30: ea92 0f03 teq r2, r3 8000c34: d004 beq.n 8000c40 <__addsf3+0x10c> 8000c36: f092 0f00 teq r2, #0 8000c3a: bf08 it eq 8000c3c: 4608 moveq r0, r1 8000c3e: 4770 bx lr 8000c40: ea90 0f01 teq r0, r1 8000c44: bf1c itt ne 8000c46: 2000 movne r0, #0 8000c48: 4770 bxne lr 8000c4a: f012 4f7f tst.w r2, #4278190080 ; 0xff000000 8000c4e: d104 bne.n 8000c5a <__addsf3+0x126> 8000c50: 0040 lsls r0, r0, #1 8000c52: bf28 it cs 8000c54: f040 4000 orrcs.w r0, r0, #2147483648 ; 0x80000000 8000c58: 4770 bx lr 8000c5a: f112 7200 adds.w r2, r2, #33554432 ; 0x2000000 8000c5e: bf3c itt cc 8000c60: f500 0000 addcc.w r0, r0, #8388608 ; 0x800000 8000c64: 4770 bxcc lr 8000c66: f000 4300 and.w r3, r0, #2147483648 ; 0x80000000 8000c6a: f043 40fe orr.w r0, r3, #2130706432 ; 0x7f000000 8000c6e: f440 0000 orr.w r0, r0, #8388608 ; 0x800000 8000c72: 4770 bx lr 8000c74: ea7f 6222 mvns.w r2, r2, asr #24 8000c78: bf16 itet ne 8000c7a: 4608 movne r0, r1 8000c7c: ea7f 6323 mvnseq.w r3, r3, asr #24 8000c80: 4601 movne r1, r0 8000c82: 0242 lsls r2, r0, #9 8000c84: bf06 itte eq 8000c86: ea5f 2341 movseq.w r3, r1, lsl #9 8000c8a: ea90 0f01 teqeq r0, r1 8000c8e: f440 0080 orrne.w r0, r0, #4194304 ; 0x400000 8000c92: 4770 bx lr 08000c94 <__aeabi_ui2f>: 8000c94: f04f 0300 mov.w r3, #0 8000c98: e004 b.n 8000ca4 <__aeabi_i2f+0x8> 8000c9a: bf00 nop 08000c9c <__aeabi_i2f>: 8000c9c: f010 4300 ands.w r3, r0, #2147483648 ; 0x80000000 8000ca0: bf48 it mi 8000ca2: 4240 negmi r0, r0 8000ca4: ea5f 0c00 movs.w ip, r0 8000ca8: bf08 it eq 8000caa: 4770 bxeq lr 8000cac: f043 4396 orr.w r3, r3, #1258291200 ; 0x4b000000 8000cb0: 4601 mov r1, r0 8000cb2: f04f 0000 mov.w r0, #0 8000cb6: e01c b.n 8000cf2 <__aeabi_l2f+0x2a> 08000cb8 <__aeabi_ul2f>: 8000cb8: ea50 0201 orrs.w r2, r0, r1 8000cbc: bf08 it eq 8000cbe: 4770 bxeq lr 8000cc0: f04f 0300 mov.w r3, #0 8000cc4: e00a b.n 8000cdc <__aeabi_l2f+0x14> 8000cc6: bf00 nop 08000cc8 <__aeabi_l2f>: 8000cc8: ea50 0201 orrs.w r2, r0, r1 8000ccc: bf08 it eq 8000cce: 4770 bxeq lr 8000cd0: f011 4300 ands.w r3, r1, #2147483648 ; 0x80000000 8000cd4: d502 bpl.n 8000cdc <__aeabi_l2f+0x14> 8000cd6: 4240 negs r0, r0 8000cd8: eb61 0141 sbc.w r1, r1, r1, lsl #1 8000cdc: ea5f 0c01 movs.w ip, r1 8000ce0: bf02 ittt eq 8000ce2: 4684 moveq ip, r0 8000ce4: 4601 moveq r1, r0 8000ce6: 2000 moveq r0, #0 8000ce8: f043 43b6 orr.w r3, r3, #1526726656 ; 0x5b000000 8000cec: bf08 it eq 8000cee: f1a3 5380 subeq.w r3, r3, #268435456 ; 0x10000000 8000cf2: f5a3 0300 sub.w r3, r3, #8388608 ; 0x800000 8000cf6: fabc f28c clz r2, ip 8000cfa: 3a08 subs r2, #8 8000cfc: eba3 53c2 sub.w r3, r3, r2, lsl #23 8000d00: db10 blt.n 8000d24 <__aeabi_l2f+0x5c> 8000d02: fa01 fc02 lsl.w ip, r1, r2 8000d06: 4463 add r3, ip 8000d08: fa00 fc02 lsl.w ip, r0, r2 8000d0c: f1c2 0220 rsb r2, r2, #32 8000d10: f1bc 4f00 cmp.w ip, #2147483648 ; 0x80000000 8000d14: fa20 f202 lsr.w r2, r0, r2 8000d18: eb43 0002 adc.w r0, r3, r2 8000d1c: bf08 it eq 8000d1e: f020 0001 biceq.w r0, r0, #1 8000d22: 4770 bx lr 8000d24: f102 0220 add.w r2, r2, #32 8000d28: fa01 fc02 lsl.w ip, r1, r2 8000d2c: f1c2 0220 rsb r2, r2, #32 8000d30: ea50 004c orrs.w r0, r0, ip, lsl #1 8000d34: fa21 f202 lsr.w r2, r1, r2 8000d38: eb43 0002 adc.w r0, r3, r2 8000d3c: bf08 it eq 8000d3e: ea20 70dc biceq.w r0, r0, ip, lsr #31 8000d42: 4770 bx lr 08000d44 <__aeabi_fmul>: 8000d44: f04f 0cff mov.w ip, #255 ; 0xff 8000d48: ea1c 52d0 ands.w r2, ip, r0, lsr #23 8000d4c: bf1e ittt ne 8000d4e: ea1c 53d1 andsne.w r3, ip, r1, lsr #23 8000d52: ea92 0f0c teqne r2, ip 8000d56: ea93 0f0c teqne r3, ip 8000d5a: d06f beq.n 8000e3c <__aeabi_fmul+0xf8> 8000d5c: 441a add r2, r3 8000d5e: ea80 0c01 eor.w ip, r0, r1 8000d62: 0240 lsls r0, r0, #9 8000d64: bf18 it ne 8000d66: ea5f 2141 movsne.w r1, r1, lsl #9 8000d6a: d01e beq.n 8000daa <__aeabi_fmul+0x66> 8000d6c: f04f 6300 mov.w r3, #134217728 ; 0x8000000 8000d70: ea43 1050 orr.w r0, r3, r0, lsr #5 8000d74: ea43 1151 orr.w r1, r3, r1, lsr #5 8000d78: fba0 3101 umull r3, r1, r0, r1 8000d7c: f00c 4000 and.w r0, ip, #2147483648 ; 0x80000000 8000d80: f5b1 0f00 cmp.w r1, #8388608 ; 0x800000 8000d84: bf3e ittt cc 8000d86: 0049 lslcc r1, r1, #1 8000d88: ea41 71d3 orrcc.w r1, r1, r3, lsr #31 8000d8c: 005b lslcc r3, r3, #1 8000d8e: ea40 0001 orr.w r0, r0, r1 8000d92: f162 027f sbc.w r2, r2, #127 ; 0x7f 8000d96: 2afd cmp r2, #253 ; 0xfd 8000d98: d81d bhi.n 8000dd6 <__aeabi_fmul+0x92> 8000d9a: f1b3 4f00 cmp.w r3, #2147483648 ; 0x80000000 8000d9e: eb40 50c2 adc.w r0, r0, r2, lsl #23 8000da2: bf08 it eq 8000da4: f020 0001 biceq.w r0, r0, #1 8000da8: 4770 bx lr 8000daa: f090 0f00 teq r0, #0 8000dae: f00c 4c00 and.w ip, ip, #2147483648 ; 0x80000000 8000db2: bf08 it eq 8000db4: 0249 lsleq r1, r1, #9 8000db6: ea4c 2050 orr.w r0, ip, r0, lsr #9 8000dba: ea40 2051 orr.w r0, r0, r1, lsr #9 8000dbe: 3a7f subs r2, #127 ; 0x7f 8000dc0: bfc2 ittt gt 8000dc2: f1d2 03ff rsbsgt r3, r2, #255 ; 0xff 8000dc6: ea40 50c2 orrgt.w r0, r0, r2, lsl #23 8000dca: 4770 bxgt lr 8000dcc: f440 0000 orr.w r0, r0, #8388608 ; 0x800000 8000dd0: f04f 0300 mov.w r3, #0 8000dd4: 3a01 subs r2, #1 8000dd6: dc5d bgt.n 8000e94 <__aeabi_fmul+0x150> 8000dd8: f112 0f19 cmn.w r2, #25 8000ddc: bfdc itt le 8000dde: f000 4000 andle.w r0, r0, #2147483648 ; 0x80000000 8000de2: 4770 bxle lr 8000de4: f1c2 0200 rsb r2, r2, #0 8000de8: 0041 lsls r1, r0, #1 8000dea: fa21 f102 lsr.w r1, r1, r2 8000dee: f1c2 0220 rsb r2, r2, #32 8000df2: fa00 fc02 lsl.w ip, r0, r2 8000df6: ea5f 0031 movs.w r0, r1, rrx 8000dfa: f140 0000 adc.w r0, r0, #0 8000dfe: ea53 034c orrs.w r3, r3, ip, lsl #1 8000e02: bf08 it eq 8000e04: ea20 70dc biceq.w r0, r0, ip, lsr #31 8000e08: 4770 bx lr 8000e0a: f092 0f00 teq r2, #0 8000e0e: f000 4c00 and.w ip, r0, #2147483648 ; 0x80000000 8000e12: bf02 ittt eq 8000e14: 0040 lsleq r0, r0, #1 8000e16: f410 0f00 tsteq.w r0, #8388608 ; 0x800000 8000e1a: 3a01 subeq r2, #1 8000e1c: d0f9 beq.n 8000e12 <__aeabi_fmul+0xce> 8000e1e: ea40 000c orr.w r0, r0, ip 8000e22: f093 0f00 teq r3, #0 8000e26: f001 4c00 and.w ip, r1, #2147483648 ; 0x80000000 8000e2a: bf02 ittt eq 8000e2c: 0049 lsleq r1, r1, #1 8000e2e: f411 0f00 tsteq.w r1, #8388608 ; 0x800000 8000e32: 3b01 subeq r3, #1 8000e34: d0f9 beq.n 8000e2a <__aeabi_fmul+0xe6> 8000e36: ea41 010c orr.w r1, r1, ip 8000e3a: e78f b.n 8000d5c <__aeabi_fmul+0x18> 8000e3c: ea0c 53d1 and.w r3, ip, r1, lsr #23 8000e40: ea92 0f0c teq r2, ip 8000e44: bf18 it ne 8000e46: ea93 0f0c teqne r3, ip 8000e4a: d00a beq.n 8000e62 <__aeabi_fmul+0x11e> 8000e4c: f030 4c00 bics.w ip, r0, #2147483648 ; 0x80000000 8000e50: bf18 it ne 8000e52: f031 4c00 bicsne.w ip, r1, #2147483648 ; 0x80000000 8000e56: d1d8 bne.n 8000e0a <__aeabi_fmul+0xc6> 8000e58: ea80 0001 eor.w r0, r0, r1 8000e5c: f000 4000 and.w r0, r0, #2147483648 ; 0x80000000 8000e60: 4770 bx lr 8000e62: f090 0f00 teq r0, #0 8000e66: bf17 itett ne 8000e68: f090 4f00 teqne r0, #2147483648 ; 0x80000000 8000e6c: 4608 moveq r0, r1 8000e6e: f091 0f00 teqne r1, #0 8000e72: f091 4f00 teqne r1, #2147483648 ; 0x80000000 8000e76: d014 beq.n 8000ea2 <__aeabi_fmul+0x15e> 8000e78: ea92 0f0c teq r2, ip 8000e7c: d101 bne.n 8000e82 <__aeabi_fmul+0x13e> 8000e7e: 0242 lsls r2, r0, #9 8000e80: d10f bne.n 8000ea2 <__aeabi_fmul+0x15e> 8000e82: ea93 0f0c teq r3, ip 8000e86: d103 bne.n 8000e90 <__aeabi_fmul+0x14c> 8000e88: 024b lsls r3, r1, #9 8000e8a: bf18 it ne 8000e8c: 4608 movne r0, r1 8000e8e: d108 bne.n 8000ea2 <__aeabi_fmul+0x15e> 8000e90: ea80 0001 eor.w r0, r0, r1 8000e94: f000 4000 and.w r0, r0, #2147483648 ; 0x80000000 8000e98: f040 40fe orr.w r0, r0, #2130706432 ; 0x7f000000 8000e9c: f440 0000 orr.w r0, r0, #8388608 ; 0x800000 8000ea0: 4770 bx lr 8000ea2: f040 40fe orr.w r0, r0, #2130706432 ; 0x7f000000 8000ea6: f440 0040 orr.w r0, r0, #12582912 ; 0xc00000 8000eaa: 4770 bx lr 08000eac <__aeabi_fdiv>: 8000eac: f04f 0cff mov.w ip, #255 ; 0xff 8000eb0: ea1c 52d0 ands.w r2, ip, r0, lsr #23 8000eb4: bf1e ittt ne 8000eb6: ea1c 53d1 andsne.w r3, ip, r1, lsr #23 8000eba: ea92 0f0c teqne r2, ip 8000ebe: ea93 0f0c teqne r3, ip 8000ec2: d069 beq.n 8000f98 <__aeabi_fdiv+0xec> 8000ec4: eba2 0203 sub.w r2, r2, r3 8000ec8: ea80 0c01 eor.w ip, r0, r1 8000ecc: 0249 lsls r1, r1, #9 8000ece: ea4f 2040 mov.w r0, r0, lsl #9 8000ed2: d037 beq.n 8000f44 <__aeabi_fdiv+0x98> 8000ed4: f04f 5380 mov.w r3, #268435456 ; 0x10000000 8000ed8: ea43 1111 orr.w r1, r3, r1, lsr #4 8000edc: ea43 1310 orr.w r3, r3, r0, lsr #4 8000ee0: f00c 4000 and.w r0, ip, #2147483648 ; 0x80000000 8000ee4: 428b cmp r3, r1 8000ee6: bf38 it cc 8000ee8: 005b lslcc r3, r3, #1 8000eea: f142 027d adc.w r2, r2, #125 ; 0x7d 8000eee: f44f 0c00 mov.w ip, #8388608 ; 0x800000 8000ef2: 428b cmp r3, r1 8000ef4: bf24 itt cs 8000ef6: 1a5b subcs r3, r3, r1 8000ef8: ea40 000c orrcs.w r0, r0, ip 8000efc: ebb3 0f51 cmp.w r3, r1, lsr #1 8000f00: bf24 itt cs 8000f02: eba3 0351 subcs.w r3, r3, r1, lsr #1 8000f06: ea40 005c orrcs.w r0, r0, ip, lsr #1 8000f0a: ebb3 0f91 cmp.w r3, r1, lsr #2 8000f0e: bf24 itt cs 8000f10: eba3 0391 subcs.w r3, r3, r1, lsr #2 8000f14: ea40 009c orrcs.w r0, r0, ip, lsr #2 8000f18: ebb3 0fd1 cmp.w r3, r1, lsr #3 8000f1c: bf24 itt cs 8000f1e: eba3 03d1 subcs.w r3, r3, r1, lsr #3 8000f22: ea40 00dc orrcs.w r0, r0, ip, lsr #3 8000f26: 011b lsls r3, r3, #4 8000f28: bf18 it ne 8000f2a: ea5f 1c1c movsne.w ip, ip, lsr #4 8000f2e: d1e0 bne.n 8000ef2 <__aeabi_fdiv+0x46> 8000f30: 2afd cmp r2, #253 ; 0xfd 8000f32: f63f af50 bhi.w 8000dd6 <__aeabi_fmul+0x92> 8000f36: 428b cmp r3, r1 8000f38: eb40 50c2 adc.w r0, r0, r2, lsl #23 8000f3c: bf08 it eq 8000f3e: f020 0001 biceq.w r0, r0, #1 8000f42: 4770 bx lr 8000f44: f00c 4c00 and.w ip, ip, #2147483648 ; 0x80000000 8000f48: ea4c 2050 orr.w r0, ip, r0, lsr #9 8000f4c: 327f adds r2, #127 ; 0x7f 8000f4e: bfc2 ittt gt 8000f50: f1d2 03ff rsbsgt r3, r2, #255 ; 0xff 8000f54: ea40 50c2 orrgt.w r0, r0, r2, lsl #23 8000f58: 4770 bxgt lr 8000f5a: f440 0000 orr.w r0, r0, #8388608 ; 0x800000 8000f5e: f04f 0300 mov.w r3, #0 8000f62: 3a01 subs r2, #1 8000f64: e737 b.n 8000dd6 <__aeabi_fmul+0x92> 8000f66: f092 0f00 teq r2, #0 8000f6a: f000 4c00 and.w ip, r0, #2147483648 ; 0x80000000 8000f6e: bf02 ittt eq 8000f70: 0040 lsleq r0, r0, #1 8000f72: f410 0f00 tsteq.w r0, #8388608 ; 0x800000 8000f76: 3a01 subeq r2, #1 8000f78: d0f9 beq.n 8000f6e <__aeabi_fdiv+0xc2> 8000f7a: ea40 000c orr.w r0, r0, ip 8000f7e: f093 0f00 teq r3, #0 8000f82: f001 4c00 and.w ip, r1, #2147483648 ; 0x80000000 8000f86: bf02 ittt eq 8000f88: 0049 lsleq r1, r1, #1 8000f8a: f411 0f00 tsteq.w r1, #8388608 ; 0x800000 8000f8e: 3b01 subeq r3, #1 8000f90: d0f9 beq.n 8000f86 <__aeabi_fdiv+0xda> 8000f92: ea41 010c orr.w r1, r1, ip 8000f96: e795 b.n 8000ec4 <__aeabi_fdiv+0x18> 8000f98: ea0c 53d1 and.w r3, ip, r1, lsr #23 8000f9c: ea92 0f0c teq r2, ip 8000fa0: d108 bne.n 8000fb4 <__aeabi_fdiv+0x108> 8000fa2: 0242 lsls r2, r0, #9 8000fa4: f47f af7d bne.w 8000ea2 <__aeabi_fmul+0x15e> 8000fa8: ea93 0f0c teq r3, ip 8000fac: f47f af70 bne.w 8000e90 <__aeabi_fmul+0x14c> 8000fb0: 4608 mov r0, r1 8000fb2: e776 b.n 8000ea2 <__aeabi_fmul+0x15e> 8000fb4: ea93 0f0c teq r3, ip 8000fb8: d104 bne.n 8000fc4 <__aeabi_fdiv+0x118> 8000fba: 024b lsls r3, r1, #9 8000fbc: f43f af4c beq.w 8000e58 <__aeabi_fmul+0x114> 8000fc0: 4608 mov r0, r1 8000fc2: e76e b.n 8000ea2 <__aeabi_fmul+0x15e> 8000fc4: f030 4c00 bics.w ip, r0, #2147483648 ; 0x80000000 8000fc8: bf18 it ne 8000fca: f031 4c00 bicsne.w ip, r1, #2147483648 ; 0x80000000 8000fce: d1ca bne.n 8000f66 <__aeabi_fdiv+0xba> 8000fd0: f030 4200 bics.w r2, r0, #2147483648 ; 0x80000000 8000fd4: f47f af5c bne.w 8000e90 <__aeabi_fmul+0x14c> 8000fd8: f031 4300 bics.w r3, r1, #2147483648 ; 0x80000000 8000fdc: f47f af3c bne.w 8000e58 <__aeabi_fmul+0x114> 8000fe0: e75f b.n 8000ea2 <__aeabi_fmul+0x15e> 8000fe2: bf00 nop 08000fe4 : ADC_HandleTypeDef hadc1; /* ADC1 init function */ void MX_ADC1_Init(void) { 8000fe4: b580 push {r7, lr} 8000fe6: b084 sub sp, #16 8000fe8: af00 add r7, sp, #0 /* USER CODE BEGIN ADC1_Init 0 */ /* USER CODE END ADC1_Init 0 */ ADC_ChannelConfTypeDef sConfig = {0}; 8000fea: 1d3b adds r3, r7, #4 8000fec: 2200 movs r2, #0 8000fee: 601a str r2, [r3, #0] 8000ff0: 605a str r2, [r3, #4] 8000ff2: 609a str r2, [r3, #8] /* USER CODE END ADC1_Init 1 */ /** Common config */ hadc1.Instance = ADC1; 8000ff4: 4b18 ldr r3, [pc, #96] ; (8001058 ) 8000ff6: 4a19 ldr r2, [pc, #100] ; (800105c ) 8000ff8: 601a str r2, [r3, #0] hadc1.Init.ScanConvMode = ADC_SCAN_DISABLE; 8000ffa: 4b17 ldr r3, [pc, #92] ; (8001058 ) 8000ffc: 2200 movs r2, #0 8000ffe: 609a str r2, [r3, #8] hadc1.Init.ContinuousConvMode = ENABLE; 8001000: 4b15 ldr r3, [pc, #84] ; (8001058 ) 8001002: 2201 movs r2, #1 8001004: 731a strb r2, [r3, #12] hadc1.Init.DiscontinuousConvMode = DISABLE; 8001006: 4b14 ldr r3, [pc, #80] ; (8001058 ) 8001008: 2200 movs r2, #0 800100a: 751a strb r2, [r3, #20] hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START; 800100c: 4b12 ldr r3, [pc, #72] ; (8001058 ) 800100e: f44f 2260 mov.w r2, #917504 ; 0xe0000 8001012: 61da str r2, [r3, #28] hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT; 8001014: 4b10 ldr r3, [pc, #64] ; (8001058 ) 8001016: 2200 movs r2, #0 8001018: 605a str r2, [r3, #4] hadc1.Init.NbrOfConversion = 1; 800101a: 4b0f ldr r3, [pc, #60] ; (8001058 ) 800101c: 2201 movs r2, #1 800101e: 611a str r2, [r3, #16] if (HAL_ADC_Init(&hadc1) != HAL_OK) 8001020: 480d ldr r0, [pc, #52] ; (8001058 ) 8001022: f000 fbf9 bl 8001818 8001026: 4603 mov r3, r0 8001028: 2b00 cmp r3, #0 800102a: d001 beq.n 8001030 { Error_Handler(); 800102c: f000 f9af bl 800138e } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_4; 8001030: 2304 movs r3, #4 8001032: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_1; 8001034: 2301 movs r3, #1 8001036: 60bb str r3, [r7, #8] sConfig.SamplingTime = ADC_SAMPLETIME_239CYCLES_5; 8001038: 2307 movs r3, #7 800103a: 60fb str r3, [r7, #12] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 800103c: 1d3b adds r3, r7, #4 800103e: 4619 mov r1, r3 8001040: 4805 ldr r0, [pc, #20] ; (8001058 ) 8001042: f000 fd7b bl 8001b3c 8001046: 4603 mov r3, r0 8001048: 2b00 cmp r3, #0 800104a: d001 beq.n 8001050 { Error_Handler(); 800104c: f000 f99f bl 800138e } /* USER CODE BEGIN ADC1_Init 2 */ /* USER CODE END ADC1_Init 2 */ } 8001050: bf00 nop 8001052: 3710 adds r7, #16 8001054: 46bd mov sp, r7 8001056: bd80 pop {r7, pc} 8001058: 200001f8 .word 0x200001f8 800105c: 40012400 .word 0x40012400 08001060 : void HAL_ADC_MspInit(ADC_HandleTypeDef* adcHandle) { 8001060: b580 push {r7, lr} 8001062: b088 sub sp, #32 8001064: af00 add r7, sp, #0 8001066: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8001068: f107 0310 add.w r3, r7, #16 800106c: 2200 movs r2, #0 800106e: 601a str r2, [r3, #0] 8001070: 605a str r2, [r3, #4] 8001072: 609a str r2, [r3, #8] 8001074: 60da str r2, [r3, #12] if(adcHandle->Instance==ADC1) 8001076: 687b ldr r3, [r7, #4] 8001078: 681b ldr r3, [r3, #0] 800107a: 4a14 ldr r2, [pc, #80] ; (80010cc ) 800107c: 4293 cmp r3, r2 800107e: d121 bne.n 80010c4 { /* USER CODE BEGIN ADC1_MspInit 0 */ /* USER CODE END ADC1_MspInit 0 */ /* ADC1 clock enable */ __HAL_RCC_ADC1_CLK_ENABLE(); 8001080: 4b13 ldr r3, [pc, #76] ; (80010d0 ) 8001082: 699b ldr r3, [r3, #24] 8001084: 4a12 ldr r2, [pc, #72] ; (80010d0 ) 8001086: f443 7300 orr.w r3, r3, #512 ; 0x200 800108a: 6193 str r3, [r2, #24] 800108c: 4b10 ldr r3, [pc, #64] ; (80010d0 ) 800108e: 699b ldr r3, [r3, #24] 8001090: f403 7300 and.w r3, r3, #512 ; 0x200 8001094: 60fb str r3, [r7, #12] 8001096: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOA_CLK_ENABLE(); 8001098: 4b0d ldr r3, [pc, #52] ; (80010d0 ) 800109a: 699b ldr r3, [r3, #24] 800109c: 4a0c ldr r2, [pc, #48] ; (80010d0 ) 800109e: f043 0304 orr.w r3, r3, #4 80010a2: 6193 str r3, [r2, #24] 80010a4: 4b0a ldr r3, [pc, #40] ; (80010d0 ) 80010a6: 699b ldr r3, [r3, #24] 80010a8: f003 0304 and.w r3, r3, #4 80010ac: 60bb str r3, [r7, #8] 80010ae: 68bb ldr r3, [r7, #8] /**ADC1 GPIO Configuration PA4 ------> ADC1_IN4 */ GPIO_InitStruct.Pin = GPIO_PIN_4; 80010b0: 2310 movs r3, #16 80010b2: 613b str r3, [r7, #16] GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 80010b4: 2303 movs r3, #3 80010b6: 617b str r3, [r7, #20] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 80010b8: f107 0310 add.w r3, r7, #16 80010bc: 4619 mov r1, r3 80010be: 4805 ldr r0, [pc, #20] ; (80010d4 ) 80010c0: f000 ffb4 bl 800202c /* USER CODE BEGIN ADC1_MspInit 1 */ /* USER CODE END ADC1_MspInit 1 */ } } 80010c4: bf00 nop 80010c6: 3720 adds r7, #32 80010c8: 46bd mov sp, r7 80010ca: bd80 pop {r7, pc} 80010cc: 40012400 .word 0x40012400 80010d0: 40021000 .word 0x40021000 80010d4: 40010800 .word 0x40010800 080010d8 : * Output * EVENT_OUT * EXTI */ void MX_GPIO_Init(void) { 80010d8: b480 push {r7} 80010da: b083 sub sp, #12 80010dc: af00 add r7, sp, #0 /* GPIO Ports Clock Enable */ __HAL_RCC_GPIOD_CLK_ENABLE(); 80010de: 4b0e ldr r3, [pc, #56] ; (8001118 ) 80010e0: 699b ldr r3, [r3, #24] 80010e2: 4a0d ldr r2, [pc, #52] ; (8001118 ) 80010e4: f043 0320 orr.w r3, r3, #32 80010e8: 6193 str r3, [r2, #24] 80010ea: 4b0b ldr r3, [pc, #44] ; (8001118 ) 80010ec: 699b ldr r3, [r3, #24] 80010ee: f003 0320 and.w r3, r3, #32 80010f2: 607b str r3, [r7, #4] 80010f4: 687b ldr r3, [r7, #4] __HAL_RCC_GPIOA_CLK_ENABLE(); 80010f6: 4b08 ldr r3, [pc, #32] ; (8001118 ) 80010f8: 699b ldr r3, [r3, #24] 80010fa: 4a07 ldr r2, [pc, #28] ; (8001118 ) 80010fc: f043 0304 orr.w r3, r3, #4 8001100: 6193 str r3, [r2, #24] 8001102: 4b05 ldr r3, [pc, #20] ; (8001118 ) 8001104: 699b ldr r3, [r3, #24] 8001106: f003 0304 and.w r3, r3, #4 800110a: 603b str r3, [r7, #0] 800110c: 683b ldr r3, [r7, #0] } 800110e: bf00 nop 8001110: 370c adds r7, #12 8001112: 46bd mov sp, r7 8001114: bc80 pop {r7} 8001116: 4770 bx lr 8001118: 40021000 .word 0x40021000 0800111c : /* USER CODE END PFP */ /* Private user code ---------------------------------------------------------*/ /* USER CODE BEGIN 0 */ //通过ADC电压计算NTC电阻值 float ADC2Resistance(uint32_t adc_value) { 800111c: b590 push {r4, r7, lr} 800111e: b083 sub sp, #12 8001120: af00 add r7, sp, #0 8001122: 6078 str r0, [r7, #4] return (adc_value / (4096.0f - adc_value)) * 10000.0f; 8001124: 6878 ldr r0, [r7, #4] 8001126: f7ff fdb5 bl 8000c94 <__aeabi_ui2f> 800112a: 4604 mov r4, r0 800112c: 6878 ldr r0, [r7, #4] 800112e: f7ff fdb1 bl 8000c94 <__aeabi_ui2f> 8001132: 4603 mov r3, r0 8001134: 4619 mov r1, r3 8001136: f04f 408b mov.w r0, #1166016512 ; 0x45800000 800113a: f7ff fcf9 bl 8000b30 <__aeabi_fsub> 800113e: 4603 mov r3, r0 8001140: 4619 mov r1, r3 8001142: 4620 mov r0, r4 8001144: f7ff feb2 bl 8000eac <__aeabi_fdiv> 8001148: 4603 mov r3, r0 800114a: 4904 ldr r1, [pc, #16] ; (800115c ) 800114c: 4618 mov r0, r3 800114e: f7ff fdf9 bl 8000d44 <__aeabi_fmul> 8001152: 4603 mov r3, r0 } 8001154: 4618 mov r0, r3 8001156: 370c adds r7, #12 8001158: 46bd mov sp, r7 800115a: bd90 pop {r4, r7, pc} 800115c: 461c4000 .word 0x461c4000 08001160 : //通过NTC电阻计算温度 float resistance2Temperature(float R1) { 8001160: b5b0 push {r4, r5, r7, lr} 8001162: b086 sub sp, #24 8001164: af00 add r7, sp, #0 8001166: 6078 str r0, [r7, #4] float B = 3950.0f; 8001168: 4b2f ldr r3, [pc, #188] ; (8001228 ) 800116a: 617b str r3, [r7, #20] float R2 = 10000.0f; 800116c: 4b2f ldr r3, [pc, #188] ; (800122c ) 800116e: 613b str r3, [r7, #16] float T2 = 25.0f; 8001170: 4b2f ldr r3, [pc, #188] ; (8001230 ) 8001172: 60fb str r3, [r7, #12] return (1.0 / ((1.0 / B) * log(R1 / R2) + (1.0 / (T2 + 273.15))) - 273.15); 8001174: 6978 ldr r0, [r7, #20] 8001176: f7ff f957 bl 8000428 <__aeabi_f2d> 800117a: 4602 mov r2, r0 800117c: 460b mov r3, r1 800117e: f04f 0000 mov.w r0, #0 8001182: 492c ldr r1, [pc, #176] ; (8001234 ) 8001184: f7ff fad2 bl 800072c <__aeabi_ddiv> 8001188: 4602 mov r2, r0 800118a: 460b mov r3, r1 800118c: 4614 mov r4, r2 800118e: 461d mov r5, r3 8001190: 6939 ldr r1, [r7, #16] 8001192: 6878 ldr r0, [r7, #4] 8001194: f7ff fe8a bl 8000eac <__aeabi_fdiv> 8001198: 4603 mov r3, r0 800119a: 4618 mov r0, r3 800119c: f7ff f944 bl 8000428 <__aeabi_f2d> 80011a0: 4602 mov r2, r0 80011a2: 460b mov r3, r1 80011a4: 4610 mov r0, r2 80011a6: 4619 mov r1, r3 80011a8: f004 fe56 bl 8005e58 80011ac: 4602 mov r2, r0 80011ae: 460b mov r3, r1 80011b0: 4620 mov r0, r4 80011b2: 4629 mov r1, r5 80011b4: f7ff f990 bl 80004d8 <__aeabi_dmul> 80011b8: 4602 mov r2, r0 80011ba: 460b mov r3, r1 80011bc: 4614 mov r4, r2 80011be: 461d mov r5, r3 80011c0: 68f8 ldr r0, [r7, #12] 80011c2: f7ff f931 bl 8000428 <__aeabi_f2d> 80011c6: a316 add r3, pc, #88 ; (adr r3, 8001220 ) 80011c8: e9d3 2300 ldrd r2, r3, [r3] 80011cc: f7fe ffce bl 800016c <__adddf3> 80011d0: 4602 mov r2, r0 80011d2: 460b mov r3, r1 80011d4: f04f 0000 mov.w r0, #0 80011d8: 4916 ldr r1, [pc, #88] ; (8001234 ) 80011da: f7ff faa7 bl 800072c <__aeabi_ddiv> 80011de: 4602 mov r2, r0 80011e0: 460b mov r3, r1 80011e2: 4620 mov r0, r4 80011e4: 4629 mov r1, r5 80011e6: f7fe ffc1 bl 800016c <__adddf3> 80011ea: 4602 mov r2, r0 80011ec: 460b mov r3, r1 80011ee: f04f 0000 mov.w r0, #0 80011f2: 4910 ldr r1, [pc, #64] ; (8001234 ) 80011f4: f7ff fa9a bl 800072c <__aeabi_ddiv> 80011f8: 4602 mov r2, r0 80011fa: 460b mov r3, r1 80011fc: 4610 mov r0, r2 80011fe: 4619 mov r1, r3 8001200: a307 add r3, pc, #28 ; (adr r3, 8001220 ) 8001202: e9d3 2300 ldrd r2, r3, [r3] 8001206: f7fe ffaf bl 8000168 <__aeabi_dsub> 800120a: 4602 mov r2, r0 800120c: 460b mov r3, r1 800120e: 4610 mov r0, r2 8001210: 4619 mov r1, r3 8001212: f7ff fc39 bl 8000a88 <__aeabi_d2f> 8001216: 4603 mov r3, r0 } 8001218: 4618 mov r0, r3 800121a: 3718 adds r7, #24 800121c: 46bd mov sp, r7 800121e: bdb0 pop {r4, r5, r7, pc} 8001220: 66666666 .word 0x66666666 8001224: 40711266 .word 0x40711266 8001228: 4576e000 .word 0x4576e000 800122c: 461c4000 .word 0x461c4000 8001230: 41c80000 .word 0x41c80000 8001234: 3ff00000 .word 0x3ff00000 08001238
: /** * @brief The application entry point. * @retval int */ int main(void) { 8001238: b580 push {r7, lr} 800123a: b08a sub sp, #40 ; 0x28 800123c: af00 add r7, sp, #0 /* USER CODE END 1 */ /* MCU Configuration--------------------------------------------------------*/ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ HAL_Init(); 800123e: f000 fa65 bl 800170c /* USER CODE BEGIN Init */ /* USER CODE END Init */ /* Configure the system clock */ SystemClock_Config(); 8001242: f000 f849 bl 80012d8 /* USER CODE BEGIN SysInit */ /* USER CODE END SysInit */ /* Initialize all configured peripherals */ MX_GPIO_Init(); 8001246: f7ff ff47 bl 80010d8 MX_ADC1_Init(); 800124a: f7ff fecb bl 8000fe4 MX_USART2_UART_Init(); 800124e: f000 f9c3 bl 80015d8 /* USER CODE END 2 */ /* Infinite loop */ /* USER CODE BEGIN WHILE */ char send_buf[30] = { 0 }; 8001252: 2300 movs r3, #0 8001254: 603b str r3, [r7, #0] 8001256: 1d3b adds r3, r7, #4 8001258: 2200 movs r2, #0 800125a: 601a str r2, [r3, #0] 800125c: 605a str r2, [r3, #4] 800125e: 609a str r2, [r3, #8] 8001260: 60da str r2, [r3, #12] 8001262: 611a str r2, [r3, #16] 8001264: 615a str r2, [r3, #20] 8001266: 831a strh r2, [r3, #24] float ntc_resistance = 0.0f; 8001268: f04f 0300 mov.w r3, #0 800126c: 627b str r3, [r7, #36] ; 0x24 float temperature = 0.0f; 800126e: f04f 0300 mov.w r3, #0 8001272: 623b str r3, [r7, #32] //打开ADC HAL_ADC_Start(&hadc1); 8001274: 4815 ldr r0, [pc, #84] ; (80012cc ) 8001276: f000 fba7 bl 80019c8 //等待ADC稳定 HAL_Delay(500); 800127a: f44f 70fa mov.w r0, #500 ; 0x1f4 800127e: f000 faa7 bl 80017d0 while (1) { ntc_resistance = ADC2Resistance(HAL_ADC_GetValue(&hadc1)); 8001282: 4812 ldr r0, [pc, #72] ; (80012cc ) 8001284: f000 fc4e bl 8001b24 8001288: 4603 mov r3, r0 800128a: 4618 mov r0, r3 800128c: f7ff ff46 bl 800111c 8001290: 6278 str r0, [r7, #36] ; 0x24 temperature = resistance2Temperature(ntc_resistance); 8001292: 6a78 ldr r0, [r7, #36] ; 0x24 8001294: f7ff ff64 bl 8001160 8001298: 6238 str r0, [r7, #32] sprintf(send_buf, "%.2f\r\n", temperature); 800129a: 6a38 ldr r0, [r7, #32] 800129c: f7ff f8c4 bl 8000428 <__aeabi_f2d> 80012a0: 4602 mov r2, r0 80012a2: 460b mov r3, r1 80012a4: 4638 mov r0, r7 80012a6: 490a ldr r1, [pc, #40] ; (80012d0 ) 80012a8: f002 fb5e bl 8003968 HAL_UART_Transmit(&huart2, (uint8_t*) send_buf, strlen(send_buf), 10); 80012ac: 463b mov r3, r7 80012ae: 4618 mov r0, r3 80012b0: f7fe ff4e bl 8000150 80012b4: 4603 mov r3, r0 80012b6: b29a uxth r2, r3 80012b8: 4639 mov r1, r7 80012ba: 230a movs r3, #10 80012bc: 4805 ldr r0, [pc, #20] ; (80012d4 ) 80012be: f001 fd56 bl 8002d6e HAL_Delay(100); 80012c2: 2064 movs r0, #100 ; 0x64 80012c4: f000 fa84 bl 80017d0 ntc_resistance = ADC2Resistance(HAL_ADC_GetValue(&hadc1)); 80012c8: e7db b.n 8001282 80012ca: bf00 nop 80012cc: 200001f8 .word 0x200001f8 80012d0: 08006248 .word 0x08006248 80012d4: 2000022c .word 0x2000022c 080012d8 : /** * @brief System Clock Configuration * @retval None */ void SystemClock_Config(void) { 80012d8: b580 push {r7, lr} 80012da: b094 sub sp, #80 ; 0x50 80012dc: af00 add r7, sp, #0 RCC_OscInitTypeDef RCC_OscInitStruct = { 0 }; 80012de: f107 0328 add.w r3, r7, #40 ; 0x28 80012e2: 2228 movs r2, #40 ; 0x28 80012e4: 2100 movs r1, #0 80012e6: 4618 mov r0, r3 80012e8: f001 fed6 bl 8003098 RCC_ClkInitTypeDef RCC_ClkInitStruct = { 0 }; 80012ec: f107 0314 add.w r3, r7, #20 80012f0: 2200 movs r2, #0 80012f2: 601a str r2, [r3, #0] 80012f4: 605a str r2, [r3, #4] 80012f6: 609a str r2, [r3, #8] 80012f8: 60da str r2, [r3, #12] 80012fa: 611a str r2, [r3, #16] RCC_PeriphCLKInitTypeDef PeriphClkInit = { 0 }; 80012fc: 1d3b adds r3, r7, #4 80012fe: 2200 movs r2, #0 8001300: 601a str r2, [r3, #0] 8001302: 605a str r2, [r3, #4] 8001304: 609a str r2, [r3, #8] 8001306: 60da str r2, [r3, #12] /** Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; 8001308: 2301 movs r3, #1 800130a: 62bb str r3, [r7, #40] ; 0x28 RCC_OscInitStruct.HSEState = RCC_HSE_ON; 800130c: f44f 3380 mov.w r3, #65536 ; 0x10000 8001310: 62fb str r3, [r7, #44] ; 0x2c RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV1; 8001312: 2300 movs r3, #0 8001314: 633b str r3, [r7, #48] ; 0x30 RCC_OscInitStruct.HSIState = RCC_HSI_ON; 8001316: 2301 movs r3, #1 8001318: 63bb str r3, [r7, #56] ; 0x38 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; 800131a: 2302 movs r3, #2 800131c: 647b str r3, [r7, #68] ; 0x44 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; 800131e: f44f 3380 mov.w r3, #65536 ; 0x10000 8001322: 64bb str r3, [r7, #72] ; 0x48 RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9; 8001324: f44f 13e0 mov.w r3, #1835008 ; 0x1c0000 8001328: 64fb str r3, [r7, #76] ; 0x4c if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { 800132a: f107 0328 add.w r3, r7, #40 ; 0x28 800132e: 4618 mov r0, r3 8001330: f001 f800 bl 8002334 8001334: 4603 mov r3, r0 8001336: 2b00 cmp r3, #0 8001338: d001 beq.n 800133e Error_Handler(); 800133a: f000 f828 bl 800138e } /** Initializes the CPU, AHB and APB buses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK 800133e: 230f movs r3, #15 8001340: 617b str r3, [r7, #20] | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; 8001342: 2302 movs r3, #2 8001344: 61bb str r3, [r7, #24] RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; 8001346: 2300 movs r3, #0 8001348: 61fb str r3, [r7, #28] RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; 800134a: f44f 6380 mov.w r3, #1024 ; 0x400 800134e: 623b str r3, [r7, #32] RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; 8001350: 2300 movs r3, #0 8001352: 627b str r3, [r7, #36] ; 0x24 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) { 8001354: f107 0314 add.w r3, r7, #20 8001358: 2102 movs r1, #2 800135a: 4618 mov r0, r3 800135c: f001 fa6c bl 8002838 8001360: 4603 mov r3, r0 8001362: 2b00 cmp r3, #0 8001364: d001 beq.n 800136a Error_Handler(); 8001366: f000 f812 bl 800138e } PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC; 800136a: 2302 movs r3, #2 800136c: 607b str r3, [r7, #4] PeriphClkInit.AdcClockSelection = RCC_ADCPCLK2_DIV6; 800136e: f44f 4300 mov.w r3, #32768 ; 0x8000 8001372: 60fb str r3, [r7, #12] if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) { 8001374: 1d3b adds r3, r7, #4 8001376: 4618 mov r0, r3 8001378: f001 fbf6 bl 8002b68 800137c: 4603 mov r3, r0 800137e: 2b00 cmp r3, #0 8001380: d001 beq.n 8001386 Error_Handler(); 8001382: f000 f804 bl 800138e } } 8001386: bf00 nop 8001388: 3750 adds r7, #80 ; 0x50 800138a: 46bd mov sp, r7 800138c: bd80 pop {r7, pc} 0800138e : /** * @brief This function is executed in case of error occurrence. * @retval None */ void Error_Handler(void) { 800138e: b480 push {r7} 8001390: af00 add r7, sp, #0 \details Disables IRQ interrupts by setting the I-bit in the CPSR. Can only be executed in Privileged modes. */ __STATIC_FORCEINLINE void __disable_irq(void) { __ASM volatile ("cpsid i" : : : "memory"); 8001392: b672 cpsid i } 8001394: bf00 nop /* USER CODE BEGIN Error_Handler_Debug */ /* User can add his own implementation to report the HAL error return state */ __disable_irq(); while (1) { 8001396: e7fe b.n 8001396 08001398 : /* USER CODE END 0 */ /** * Initializes the Global MSP. */ void HAL_MspInit(void) { 8001398: b480 push {r7} 800139a: b085 sub sp, #20 800139c: af00 add r7, sp, #0 /* USER CODE BEGIN MspInit 0 */ /* USER CODE END MspInit 0 */ __HAL_RCC_AFIO_CLK_ENABLE(); 800139e: 4b15 ldr r3, [pc, #84] ; (80013f4 ) 80013a0: 699b ldr r3, [r3, #24] 80013a2: 4a14 ldr r2, [pc, #80] ; (80013f4 ) 80013a4: f043 0301 orr.w r3, r3, #1 80013a8: 6193 str r3, [r2, #24] 80013aa: 4b12 ldr r3, [pc, #72] ; (80013f4 ) 80013ac: 699b ldr r3, [r3, #24] 80013ae: f003 0301 and.w r3, r3, #1 80013b2: 60bb str r3, [r7, #8] 80013b4: 68bb ldr r3, [r7, #8] __HAL_RCC_PWR_CLK_ENABLE(); 80013b6: 4b0f ldr r3, [pc, #60] ; (80013f4 ) 80013b8: 69db ldr r3, [r3, #28] 80013ba: 4a0e ldr r2, [pc, #56] ; (80013f4 ) 80013bc: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 80013c0: 61d3 str r3, [r2, #28] 80013c2: 4b0c ldr r3, [pc, #48] ; (80013f4 ) 80013c4: 69db ldr r3, [r3, #28] 80013c6: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 80013ca: 607b str r3, [r7, #4] 80013cc: 687b ldr r3, [r7, #4] /* System interrupt init*/ /** NOJTAG: JTAG-DP Disabled and SW-DP Enabled */ __HAL_AFIO_REMAP_SWJ_NOJTAG(); 80013ce: 4b0a ldr r3, [pc, #40] ; (80013f8 ) 80013d0: 685b ldr r3, [r3, #4] 80013d2: 60fb str r3, [r7, #12] 80013d4: 68fb ldr r3, [r7, #12] 80013d6: f023 63e0 bic.w r3, r3, #117440512 ; 0x7000000 80013da: 60fb str r3, [r7, #12] 80013dc: 68fb ldr r3, [r7, #12] 80013de: f043 7300 orr.w r3, r3, #33554432 ; 0x2000000 80013e2: 60fb str r3, [r7, #12] 80013e4: 4a04 ldr r2, [pc, #16] ; (80013f8 ) 80013e6: 68fb ldr r3, [r7, #12] 80013e8: 6053 str r3, [r2, #4] /* USER CODE BEGIN MspInit 1 */ /* USER CODE END MspInit 1 */ } 80013ea: bf00 nop 80013ec: 3714 adds r7, #20 80013ee: 46bd mov sp, r7 80013f0: bc80 pop {r7} 80013f2: 4770 bx lr 80013f4: 40021000 .word 0x40021000 80013f8: 40010000 .word 0x40010000 080013fc : /******************************************************************************/ /** * @brief This function handles Non maskable interrupt. */ void NMI_Handler(void) { 80013fc: b480 push {r7} 80013fe: af00 add r7, sp, #0 /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ /* USER CODE END NonMaskableInt_IRQn 0 */ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ while (1) 8001400: e7fe b.n 8001400 08001402 : /** * @brief This function handles Hard fault interrupt. */ void HardFault_Handler(void) { 8001402: b480 push {r7} 8001404: af00 add r7, sp, #0 /* USER CODE BEGIN HardFault_IRQn 0 */ /* USER CODE END HardFault_IRQn 0 */ while (1) 8001406: e7fe b.n 8001406 08001408 : /** * @brief This function handles Memory management fault. */ void MemManage_Handler(void) { 8001408: b480 push {r7} 800140a: af00 add r7, sp, #0 /* USER CODE BEGIN MemoryManagement_IRQn 0 */ /* USER CODE END MemoryManagement_IRQn 0 */ while (1) 800140c: e7fe b.n 800140c 0800140e : /** * @brief This function handles Prefetch fault, memory access fault. */ void BusFault_Handler(void) { 800140e: b480 push {r7} 8001410: af00 add r7, sp, #0 /* USER CODE BEGIN BusFault_IRQn 0 */ /* USER CODE END BusFault_IRQn 0 */ while (1) 8001412: e7fe b.n 8001412 08001414 : /** * @brief This function handles Undefined instruction or illegal state. */ void UsageFault_Handler(void) { 8001414: b480 push {r7} 8001416: af00 add r7, sp, #0 /* USER CODE BEGIN UsageFault_IRQn 0 */ /* USER CODE END UsageFault_IRQn 0 */ while (1) 8001418: e7fe b.n 8001418 0800141a : /** * @brief This function handles System service call via SWI instruction. */ void SVC_Handler(void) { 800141a: b480 push {r7} 800141c: af00 add r7, sp, #0 /* USER CODE END SVCall_IRQn 0 */ /* USER CODE BEGIN SVCall_IRQn 1 */ /* USER CODE END SVCall_IRQn 1 */ } 800141e: bf00 nop 8001420: 46bd mov sp, r7 8001422: bc80 pop {r7} 8001424: 4770 bx lr 08001426 : /** * @brief This function handles Debug monitor. */ void DebugMon_Handler(void) { 8001426: b480 push {r7} 8001428: af00 add r7, sp, #0 /* USER CODE END DebugMonitor_IRQn 0 */ /* USER CODE BEGIN DebugMonitor_IRQn 1 */ /* USER CODE END DebugMonitor_IRQn 1 */ } 800142a: bf00 nop 800142c: 46bd mov sp, r7 800142e: bc80 pop {r7} 8001430: 4770 bx lr 08001432 : /** * @brief This function handles Pendable request for system service. */ void PendSV_Handler(void) { 8001432: b480 push {r7} 8001434: af00 add r7, sp, #0 /* USER CODE END PendSV_IRQn 0 */ /* USER CODE BEGIN PendSV_IRQn 1 */ /* USER CODE END PendSV_IRQn 1 */ } 8001436: bf00 nop 8001438: 46bd mov sp, r7 800143a: bc80 pop {r7} 800143c: 4770 bx lr 0800143e : /** * @brief This function handles System tick timer. */ void SysTick_Handler(void) { 800143e: b580 push {r7, lr} 8001440: af00 add r7, sp, #0 /* USER CODE BEGIN SysTick_IRQn 0 */ /* USER CODE END SysTick_IRQn 0 */ HAL_IncTick(); 8001442: f000 f9a9 bl 8001798 /* USER CODE BEGIN SysTick_IRQn 1 */ /* USER CODE END SysTick_IRQn 1 */ } 8001446: bf00 nop 8001448: bd80 pop {r7, pc} 0800144a <_getpid>: void initialise_monitor_handles() { } int _getpid(void) { 800144a: b480 push {r7} 800144c: af00 add r7, sp, #0 return 1; 800144e: 2301 movs r3, #1 } 8001450: 4618 mov r0, r3 8001452: 46bd mov sp, r7 8001454: bc80 pop {r7} 8001456: 4770 bx lr 08001458 <_kill>: int _kill(int pid, int sig) { 8001458: b580 push {r7, lr} 800145a: b082 sub sp, #8 800145c: af00 add r7, sp, #0 800145e: 6078 str r0, [r7, #4] 8001460: 6039 str r1, [r7, #0] (void)pid; (void)sig; errno = EINVAL; 8001462: f001 fdef bl 8003044 <__errno> 8001466: 4603 mov r3, r0 8001468: 2216 movs r2, #22 800146a: 601a str r2, [r3, #0] return -1; 800146c: f04f 33ff mov.w r3, #4294967295 } 8001470: 4618 mov r0, r3 8001472: 3708 adds r7, #8 8001474: 46bd mov sp, r7 8001476: bd80 pop {r7, pc} 08001478 <_exit>: void _exit (int status) { 8001478: b580 push {r7, lr} 800147a: b082 sub sp, #8 800147c: af00 add r7, sp, #0 800147e: 6078 str r0, [r7, #4] _kill(status, -1); 8001480: f04f 31ff mov.w r1, #4294967295 8001484: 6878 ldr r0, [r7, #4] 8001486: f7ff ffe7 bl 8001458 <_kill> while (1) {} /* Make sure we hang here */ 800148a: e7fe b.n 800148a <_exit+0x12> 0800148c <_read>: } __attribute__((weak)) int _read(int file, char *ptr, int len) { 800148c: b580 push {r7, lr} 800148e: b086 sub sp, #24 8001490: af00 add r7, sp, #0 8001492: 60f8 str r0, [r7, #12] 8001494: 60b9 str r1, [r7, #8] 8001496: 607a str r2, [r7, #4] (void)file; int DataIdx; for (DataIdx = 0; DataIdx < len; DataIdx++) 8001498: 2300 movs r3, #0 800149a: 617b str r3, [r7, #20] 800149c: e00a b.n 80014b4 <_read+0x28> { *ptr++ = __io_getchar(); 800149e: f3af 8000 nop.w 80014a2: 4601 mov r1, r0 80014a4: 68bb ldr r3, [r7, #8] 80014a6: 1c5a adds r2, r3, #1 80014a8: 60ba str r2, [r7, #8] 80014aa: b2ca uxtb r2, r1 80014ac: 701a strb r2, [r3, #0] for (DataIdx = 0; DataIdx < len; DataIdx++) 80014ae: 697b ldr r3, [r7, #20] 80014b0: 3301 adds r3, #1 80014b2: 617b str r3, [r7, #20] 80014b4: 697a ldr r2, [r7, #20] 80014b6: 687b ldr r3, [r7, #4] 80014b8: 429a cmp r2, r3 80014ba: dbf0 blt.n 800149e <_read+0x12> } return len; 80014bc: 687b ldr r3, [r7, #4] } 80014be: 4618 mov r0, r3 80014c0: 3718 adds r7, #24 80014c2: 46bd mov sp, r7 80014c4: bd80 pop {r7, pc} 080014c6 <_write>: __attribute__((weak)) int _write(int file, char *ptr, int len) { 80014c6: b580 push {r7, lr} 80014c8: b086 sub sp, #24 80014ca: af00 add r7, sp, #0 80014cc: 60f8 str r0, [r7, #12] 80014ce: 60b9 str r1, [r7, #8] 80014d0: 607a str r2, [r7, #4] (void)file; int DataIdx; for (DataIdx = 0; DataIdx < len; DataIdx++) 80014d2: 2300 movs r3, #0 80014d4: 617b str r3, [r7, #20] 80014d6: e009 b.n 80014ec <_write+0x26> { __io_putchar(*ptr++); 80014d8: 68bb ldr r3, [r7, #8] 80014da: 1c5a adds r2, r3, #1 80014dc: 60ba str r2, [r7, #8] 80014de: 781b ldrb r3, [r3, #0] 80014e0: 4618 mov r0, r3 80014e2: f3af 8000 nop.w for (DataIdx = 0; DataIdx < len; DataIdx++) 80014e6: 697b ldr r3, [r7, #20] 80014e8: 3301 adds r3, #1 80014ea: 617b str r3, [r7, #20] 80014ec: 697a ldr r2, [r7, #20] 80014ee: 687b ldr r3, [r7, #4] 80014f0: 429a cmp r2, r3 80014f2: dbf1 blt.n 80014d8 <_write+0x12> } return len; 80014f4: 687b ldr r3, [r7, #4] } 80014f6: 4618 mov r0, r3 80014f8: 3718 adds r7, #24 80014fa: 46bd mov sp, r7 80014fc: bd80 pop {r7, pc} 080014fe <_close>: int _close(int file) { 80014fe: b480 push {r7} 8001500: b083 sub sp, #12 8001502: af00 add r7, sp, #0 8001504: 6078 str r0, [r7, #4] (void)file; return -1; 8001506: f04f 33ff mov.w r3, #4294967295 } 800150a: 4618 mov r0, r3 800150c: 370c adds r7, #12 800150e: 46bd mov sp, r7 8001510: bc80 pop {r7} 8001512: 4770 bx lr 08001514 <_fstat>: int _fstat(int file, struct stat *st) { 8001514: b480 push {r7} 8001516: b083 sub sp, #12 8001518: af00 add r7, sp, #0 800151a: 6078 str r0, [r7, #4] 800151c: 6039 str r1, [r7, #0] (void)file; st->st_mode = S_IFCHR; 800151e: 683b ldr r3, [r7, #0] 8001520: f44f 5200 mov.w r2, #8192 ; 0x2000 8001524: 605a str r2, [r3, #4] return 0; 8001526: 2300 movs r3, #0 } 8001528: 4618 mov r0, r3 800152a: 370c adds r7, #12 800152c: 46bd mov sp, r7 800152e: bc80 pop {r7} 8001530: 4770 bx lr 08001532 <_isatty>: int _isatty(int file) { 8001532: b480 push {r7} 8001534: b083 sub sp, #12 8001536: af00 add r7, sp, #0 8001538: 6078 str r0, [r7, #4] (void)file; return 1; 800153a: 2301 movs r3, #1 } 800153c: 4618 mov r0, r3 800153e: 370c adds r7, #12 8001540: 46bd mov sp, r7 8001542: bc80 pop {r7} 8001544: 4770 bx lr 08001546 <_lseek>: int _lseek(int file, int ptr, int dir) { 8001546: b480 push {r7} 8001548: b085 sub sp, #20 800154a: af00 add r7, sp, #0 800154c: 60f8 str r0, [r7, #12] 800154e: 60b9 str r1, [r7, #8] 8001550: 607a str r2, [r7, #4] (void)file; (void)ptr; (void)dir; return 0; 8001552: 2300 movs r3, #0 } 8001554: 4618 mov r0, r3 8001556: 3714 adds r7, #20 8001558: 46bd mov sp, r7 800155a: bc80 pop {r7} 800155c: 4770 bx lr ... 08001560 <_sbrk>: * * @param incr Memory size * @return Pointer to allocated memory */ void *_sbrk(ptrdiff_t incr) { 8001560: b580 push {r7, lr} 8001562: b086 sub sp, #24 8001564: af00 add r7, sp, #0 8001566: 6078 str r0, [r7, #4] extern uint8_t _end; /* Symbol defined in the linker script */ extern uint8_t _estack; /* Symbol defined in the linker script */ extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */ const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size; 8001568: 4a14 ldr r2, [pc, #80] ; (80015bc <_sbrk+0x5c>) 800156a: 4b15 ldr r3, [pc, #84] ; (80015c0 <_sbrk+0x60>) 800156c: 1ad3 subs r3, r2, r3 800156e: 617b str r3, [r7, #20] const uint8_t *max_heap = (uint8_t *)stack_limit; 8001570: 697b ldr r3, [r7, #20] 8001572: 613b str r3, [r7, #16] uint8_t *prev_heap_end; /* Initialize heap end at first call */ if (NULL == __sbrk_heap_end) 8001574: 4b13 ldr r3, [pc, #76] ; (80015c4 <_sbrk+0x64>) 8001576: 681b ldr r3, [r3, #0] 8001578: 2b00 cmp r3, #0 800157a: d102 bne.n 8001582 <_sbrk+0x22> { __sbrk_heap_end = &_end; 800157c: 4b11 ldr r3, [pc, #68] ; (80015c4 <_sbrk+0x64>) 800157e: 4a12 ldr r2, [pc, #72] ; (80015c8 <_sbrk+0x68>) 8001580: 601a str r2, [r3, #0] } /* Protect heap from growing into the reserved MSP stack */ if (__sbrk_heap_end + incr > max_heap) 8001582: 4b10 ldr r3, [pc, #64] ; (80015c4 <_sbrk+0x64>) 8001584: 681a ldr r2, [r3, #0] 8001586: 687b ldr r3, [r7, #4] 8001588: 4413 add r3, r2 800158a: 693a ldr r2, [r7, #16] 800158c: 429a cmp r2, r3 800158e: d207 bcs.n 80015a0 <_sbrk+0x40> { errno = ENOMEM; 8001590: f001 fd58 bl 8003044 <__errno> 8001594: 4603 mov r3, r0 8001596: 220c movs r2, #12 8001598: 601a str r2, [r3, #0] return (void *)-1; 800159a: f04f 33ff mov.w r3, #4294967295 800159e: e009 b.n 80015b4 <_sbrk+0x54> } prev_heap_end = __sbrk_heap_end; 80015a0: 4b08 ldr r3, [pc, #32] ; (80015c4 <_sbrk+0x64>) 80015a2: 681b ldr r3, [r3, #0] 80015a4: 60fb str r3, [r7, #12] __sbrk_heap_end += incr; 80015a6: 4b07 ldr r3, [pc, #28] ; (80015c4 <_sbrk+0x64>) 80015a8: 681a ldr r2, [r3, #0] 80015aa: 687b ldr r3, [r7, #4] 80015ac: 4413 add r3, r2 80015ae: 4a05 ldr r2, [pc, #20] ; (80015c4 <_sbrk+0x64>) 80015b0: 6013 str r3, [r2, #0] return (void *)prev_heap_end; 80015b2: 68fb ldr r3, [r7, #12] } 80015b4: 4618 mov r0, r3 80015b6: 3718 adds r7, #24 80015b8: 46bd mov sp, r7 80015ba: bd80 pop {r7, pc} 80015bc: 20005000 .word 0x20005000 80015c0: 00000400 .word 0x00000400 80015c4: 20000228 .word 0x20000228 80015c8: 20000288 .word 0x20000288 080015cc : * @note This function should be used only after reset. * @param None * @retval None */ void SystemInit (void) { 80015cc: b480 push {r7} 80015ce: af00 add r7, sp, #0 /* Configure the Vector Table location -------------------------------------*/ #if defined(USER_VECT_TAB_ADDRESS) SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ #endif /* USER_VECT_TAB_ADDRESS */ } 80015d0: bf00 nop 80015d2: 46bd mov sp, r7 80015d4: bc80 pop {r7} 80015d6: 4770 bx lr 080015d8 : UART_HandleTypeDef huart2; /* USART2 init function */ void MX_USART2_UART_Init(void) { 80015d8: b580 push {r7, lr} 80015da: af00 add r7, sp, #0 /* USER CODE END USART2_Init 0 */ /* USER CODE BEGIN USART2_Init 1 */ /* USER CODE END USART2_Init 1 */ huart2.Instance = USART2; 80015dc: 4b11 ldr r3, [pc, #68] ; (8001624 ) 80015de: 4a12 ldr r2, [pc, #72] ; (8001628 ) 80015e0: 601a str r2, [r3, #0] huart2.Init.BaudRate = 115200; 80015e2: 4b10 ldr r3, [pc, #64] ; (8001624 ) 80015e4: f44f 32e1 mov.w r2, #115200 ; 0x1c200 80015e8: 605a str r2, [r3, #4] huart2.Init.WordLength = UART_WORDLENGTH_8B; 80015ea: 4b0e ldr r3, [pc, #56] ; (8001624 ) 80015ec: 2200 movs r2, #0 80015ee: 609a str r2, [r3, #8] huart2.Init.StopBits = UART_STOPBITS_1; 80015f0: 4b0c ldr r3, [pc, #48] ; (8001624 ) 80015f2: 2200 movs r2, #0 80015f4: 60da str r2, [r3, #12] huart2.Init.Parity = UART_PARITY_NONE; 80015f6: 4b0b ldr r3, [pc, #44] ; (8001624 ) 80015f8: 2200 movs r2, #0 80015fa: 611a str r2, [r3, #16] huart2.Init.Mode = UART_MODE_TX_RX; 80015fc: 4b09 ldr r3, [pc, #36] ; (8001624 ) 80015fe: 220c movs r2, #12 8001600: 615a str r2, [r3, #20] huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE; 8001602: 4b08 ldr r3, [pc, #32] ; (8001624 ) 8001604: 2200 movs r2, #0 8001606: 619a str r2, [r3, #24] huart2.Init.OverSampling = UART_OVERSAMPLING_16; 8001608: 4b06 ldr r3, [pc, #24] ; (8001624 ) 800160a: 2200 movs r2, #0 800160c: 61da str r2, [r3, #28] if (HAL_UART_Init(&huart2) != HAL_OK) 800160e: 4805 ldr r0, [pc, #20] ; (8001624 ) 8001610: f001 fb60 bl 8002cd4 8001614: 4603 mov r3, r0 8001616: 2b00 cmp r3, #0 8001618: d001 beq.n 800161e { Error_Handler(); 800161a: f7ff feb8 bl 800138e } /* USER CODE BEGIN USART2_Init 2 */ /* USER CODE END USART2_Init 2 */ } 800161e: bf00 nop 8001620: bd80 pop {r7, pc} 8001622: bf00 nop 8001624: 2000022c .word 0x2000022c 8001628: 40004400 .word 0x40004400 0800162c : void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle) { 800162c: b580 push {r7, lr} 800162e: b088 sub sp, #32 8001630: af00 add r7, sp, #0 8001632: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8001634: f107 0310 add.w r3, r7, #16 8001638: 2200 movs r2, #0 800163a: 601a str r2, [r3, #0] 800163c: 605a str r2, [r3, #4] 800163e: 609a str r2, [r3, #8] 8001640: 60da str r2, [r3, #12] if(uartHandle->Instance==USART2) 8001642: 687b ldr r3, [r7, #4] 8001644: 681b ldr r3, [r3, #0] 8001646: 4a1b ldr r2, [pc, #108] ; (80016b4 ) 8001648: 4293 cmp r3, r2 800164a: d12f bne.n 80016ac { /* USER CODE BEGIN USART2_MspInit 0 */ /* USER CODE END USART2_MspInit 0 */ /* USART2 clock enable */ __HAL_RCC_USART2_CLK_ENABLE(); 800164c: 4b1a ldr r3, [pc, #104] ; (80016b8 ) 800164e: 69db ldr r3, [r3, #28] 8001650: 4a19 ldr r2, [pc, #100] ; (80016b8 ) 8001652: f443 3300 orr.w r3, r3, #131072 ; 0x20000 8001656: 61d3 str r3, [r2, #28] 8001658: 4b17 ldr r3, [pc, #92] ; (80016b8 ) 800165a: 69db ldr r3, [r3, #28] 800165c: f403 3300 and.w r3, r3, #131072 ; 0x20000 8001660: 60fb str r3, [r7, #12] 8001662: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOA_CLK_ENABLE(); 8001664: 4b14 ldr r3, [pc, #80] ; (80016b8 ) 8001666: 699b ldr r3, [r3, #24] 8001668: 4a13 ldr r2, [pc, #76] ; (80016b8 ) 800166a: f043 0304 orr.w r3, r3, #4 800166e: 6193 str r3, [r2, #24] 8001670: 4b11 ldr r3, [pc, #68] ; (80016b8 ) 8001672: 699b ldr r3, [r3, #24] 8001674: f003 0304 and.w r3, r3, #4 8001678: 60bb str r3, [r7, #8] 800167a: 68bb ldr r3, [r7, #8] /**USART2 GPIO Configuration PA2 ------> USART2_TX PA3 ------> USART2_RX */ GPIO_InitStruct.Pin = GPIO_PIN_2; 800167c: 2304 movs r3, #4 800167e: 613b str r3, [r7, #16] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8001680: 2302 movs r3, #2 8001682: 617b str r3, [r7, #20] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 8001684: 2303 movs r3, #3 8001686: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8001688: f107 0310 add.w r3, r7, #16 800168c: 4619 mov r1, r3 800168e: 480b ldr r0, [pc, #44] ; (80016bc ) 8001690: f000 fccc bl 800202c GPIO_InitStruct.Pin = GPIO_PIN_3; 8001694: 2308 movs r3, #8 8001696: 613b str r3, [r7, #16] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 8001698: 2300 movs r3, #0 800169a: 617b str r3, [r7, #20] GPIO_InitStruct.Pull = GPIO_NOPULL; 800169c: 2300 movs r3, #0 800169e: 61bb str r3, [r7, #24] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 80016a0: f107 0310 add.w r3, r7, #16 80016a4: 4619 mov r1, r3 80016a6: 4805 ldr r0, [pc, #20] ; (80016bc ) 80016a8: f000 fcc0 bl 800202c /* USER CODE BEGIN USART2_MspInit 1 */ /* USER CODE END USART2_MspInit 1 */ } } 80016ac: bf00 nop 80016ae: 3720 adds r7, #32 80016b0: 46bd mov sp, r7 80016b2: bd80 pop {r7, pc} 80016b4: 40004400 .word 0x40004400 80016b8: 40021000 .word 0x40021000 80016bc: 40010800 .word 0x40010800 080016c0 : .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata 80016c0: 480c ldr r0, [pc, #48] ; (80016f4 ) ldr r1, =_edata 80016c2: 490d ldr r1, [pc, #52] ; (80016f8 ) ldr r2, =_sidata 80016c4: 4a0d ldr r2, [pc, #52] ; (80016fc ) movs r3, #0 80016c6: 2300 movs r3, #0 b LoopCopyDataInit 80016c8: e002 b.n 80016d0 080016ca : CopyDataInit: ldr r4, [r2, r3] 80016ca: 58d4 ldr r4, [r2, r3] str r4, [r0, r3] 80016cc: 50c4 str r4, [r0, r3] adds r3, r3, #4 80016ce: 3304 adds r3, #4 080016d0 : LoopCopyDataInit: adds r4, r0, r3 80016d0: 18c4 adds r4, r0, r3 cmp r4, r1 80016d2: 428c cmp r4, r1 bcc CopyDataInit 80016d4: d3f9 bcc.n 80016ca /* Zero fill the bss segment. */ ldr r2, =_sbss 80016d6: 4a0a ldr r2, [pc, #40] ; (8001700 ) ldr r4, =_ebss 80016d8: 4c0a ldr r4, [pc, #40] ; (8001704 ) movs r3, #0 80016da: 2300 movs r3, #0 b LoopFillZerobss 80016dc: e001 b.n 80016e2 080016de : FillZerobss: str r3, [r2] 80016de: 6013 str r3, [r2, #0] adds r2, r2, #4 80016e0: 3204 adds r2, #4 080016e2 : LoopFillZerobss: cmp r2, r4 80016e2: 42a2 cmp r2, r4 bcc FillZerobss 80016e4: d3fb bcc.n 80016de /* Call the clock system intitialization function.*/ bl SystemInit 80016e6: f7ff ff71 bl 80015cc /* Call static constructors */ bl __libc_init_array 80016ea: f001 fcb1 bl 8003050 <__libc_init_array> /* Call the application's entry point.*/ bl main 80016ee: f7ff fda3 bl 8001238
bx lr 80016f2: 4770 bx lr ldr r0, =_sdata 80016f4: 20000000 .word 0x20000000 ldr r1, =_edata 80016f8: 200001dc .word 0x200001dc ldr r2, =_sidata 80016fc: 0800665c .word 0x0800665c ldr r2, =_sbss 8001700: 200001dc .word 0x200001dc ldr r4, =_ebss 8001704: 20000284 .word 0x20000284 08001708 : * @retval : None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop 8001708: e7fe b.n 8001708 ... 0800170c : * need to ensure that the SysTick time base is always set to 1 millisecond * to have correct HAL operation. * @retval HAL status */ HAL_StatusTypeDef HAL_Init(void) { 800170c: b580 push {r7, lr} 800170e: af00 add r7, sp, #0 defined(STM32F102x6) || defined(STM32F102xB) || \ defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || \ defined(STM32F105xC) || defined(STM32F107xC) /* Prefetch buffer is not available on value line devices */ __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); 8001710: 4b08 ldr r3, [pc, #32] ; (8001734 ) 8001712: 681b ldr r3, [r3, #0] 8001714: 4a07 ldr r2, [pc, #28] ; (8001734 ) 8001716: f043 0310 orr.w r3, r3, #16 800171a: 6013 str r3, [r2, #0] #endif #endif /* PREFETCH_ENABLE */ /* Set Interrupt Group Priority */ HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); 800171c: 2003 movs r0, #3 800171e: f000 fc51 bl 8001fc4 /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ HAL_InitTick(TICK_INT_PRIORITY); 8001722: 200f movs r0, #15 8001724: f000 f808 bl 8001738 /* Init the low level hardware */ HAL_MspInit(); 8001728: f7ff fe36 bl 8001398 /* Return function status */ return HAL_OK; 800172c: 2300 movs r3, #0 } 800172e: 4618 mov r0, r3 8001730: bd80 pop {r7, pc} 8001732: bf00 nop 8001734: 40022000 .word 0x40022000 08001738 : * implementation in user file. * @param TickPriority Tick interrupt priority. * @retval HAL status */ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { 8001738: b580 push {r7, lr} 800173a: b082 sub sp, #8 800173c: af00 add r7, sp, #0 800173e: 6078 str r0, [r7, #4] /* Configure the SysTick to have interrupt in 1ms time basis*/ if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U) 8001740: 4b12 ldr r3, [pc, #72] ; (800178c ) 8001742: 681a ldr r2, [r3, #0] 8001744: 4b12 ldr r3, [pc, #72] ; (8001790 ) 8001746: 781b ldrb r3, [r3, #0] 8001748: 4619 mov r1, r3 800174a: f44f 737a mov.w r3, #1000 ; 0x3e8 800174e: fbb3 f3f1 udiv r3, r3, r1 8001752: fbb2 f3f3 udiv r3, r2, r3 8001756: 4618 mov r0, r3 8001758: f000 fc5b bl 8002012 800175c: 4603 mov r3, r0 800175e: 2b00 cmp r3, #0 8001760: d001 beq.n 8001766 { return HAL_ERROR; 8001762: 2301 movs r3, #1 8001764: e00e b.n 8001784 } /* Configure the SysTick IRQ priority */ if (TickPriority < (1UL << __NVIC_PRIO_BITS)) 8001766: 687b ldr r3, [r7, #4] 8001768: 2b0f cmp r3, #15 800176a: d80a bhi.n 8001782 { HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); 800176c: 2200 movs r2, #0 800176e: 6879 ldr r1, [r7, #4] 8001770: f04f 30ff mov.w r0, #4294967295 8001774: f000 fc31 bl 8001fda uwTickPrio = TickPriority; 8001778: 4a06 ldr r2, [pc, #24] ; (8001794 ) 800177a: 687b ldr r3, [r7, #4] 800177c: 6013 str r3, [r2, #0] { return HAL_ERROR; } /* Return function status */ return HAL_OK; 800177e: 2300 movs r3, #0 8001780: e000 b.n 8001784 return HAL_ERROR; 8001782: 2301 movs r3, #1 } 8001784: 4618 mov r0, r3 8001786: 3708 adds r7, #8 8001788: 46bd mov sp, r7 800178a: bd80 pop {r7, pc} 800178c: 20000000 .word 0x20000000 8001790: 20000008 .word 0x20000008 8001794: 20000004 .word 0x20000004 08001798 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ __weak void HAL_IncTick(void) { 8001798: b480 push {r7} 800179a: af00 add r7, sp, #0 uwTick += uwTickFreq; 800179c: 4b05 ldr r3, [pc, #20] ; (80017b4 ) 800179e: 781b ldrb r3, [r3, #0] 80017a0: 461a mov r2, r3 80017a2: 4b05 ldr r3, [pc, #20] ; (80017b8 ) 80017a4: 681b ldr r3, [r3, #0] 80017a6: 4413 add r3, r2 80017a8: 4a03 ldr r2, [pc, #12] ; (80017b8 ) 80017aa: 6013 str r3, [r2, #0] } 80017ac: bf00 nop 80017ae: 46bd mov sp, r7 80017b0: bc80 pop {r7} 80017b2: 4770 bx lr 80017b4: 20000008 .word 0x20000008 80017b8: 20000270 .word 0x20000270 080017bc : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval tick value */ __weak uint32_t HAL_GetTick(void) { 80017bc: b480 push {r7} 80017be: af00 add r7, sp, #0 return uwTick; 80017c0: 4b02 ldr r3, [pc, #8] ; (80017cc ) 80017c2: 681b ldr r3, [r3, #0] } 80017c4: 4618 mov r0, r3 80017c6: 46bd mov sp, r7 80017c8: bc80 pop {r7} 80017ca: 4770 bx lr 80017cc: 20000270 .word 0x20000270 080017d0 : * implementations in user file. * @param Delay specifies the delay time length, in milliseconds. * @retval None */ __weak void HAL_Delay(uint32_t Delay) { 80017d0: b580 push {r7, lr} 80017d2: b084 sub sp, #16 80017d4: af00 add r7, sp, #0 80017d6: 6078 str r0, [r7, #4] uint32_t tickstart = HAL_GetTick(); 80017d8: f7ff fff0 bl 80017bc 80017dc: 60b8 str r0, [r7, #8] uint32_t wait = Delay; 80017de: 687b ldr r3, [r7, #4] 80017e0: 60fb str r3, [r7, #12] /* Add a freq to guarantee minimum wait */ if (wait < HAL_MAX_DELAY) 80017e2: 68fb ldr r3, [r7, #12] 80017e4: f1b3 3fff cmp.w r3, #4294967295 80017e8: d005 beq.n 80017f6 { wait += (uint32_t)(uwTickFreq); 80017ea: 4b0a ldr r3, [pc, #40] ; (8001814 ) 80017ec: 781b ldrb r3, [r3, #0] 80017ee: 461a mov r2, r3 80017f0: 68fb ldr r3, [r7, #12] 80017f2: 4413 add r3, r2 80017f4: 60fb str r3, [r7, #12] } while ((HAL_GetTick() - tickstart) < wait) 80017f6: bf00 nop 80017f8: f7ff ffe0 bl 80017bc 80017fc: 4602 mov r2, r0 80017fe: 68bb ldr r3, [r7, #8] 8001800: 1ad3 subs r3, r2, r3 8001802: 68fa ldr r2, [r7, #12] 8001804: 429a cmp r2, r3 8001806: d8f7 bhi.n 80017f8 { } } 8001808: bf00 nop 800180a: bf00 nop 800180c: 3710 adds r7, #16 800180e: 46bd mov sp, r7 8001810: bd80 pop {r7, pc} 8001812: bf00 nop 8001814: 20000008 .word 0x20000008 08001818 : * of structure "ADC_InitTypeDef". * @param hadc: ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) { 8001818: b580 push {r7, lr} 800181a: b086 sub sp, #24 800181c: af00 add r7, sp, #0 800181e: 6078 str r0, [r7, #4] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 8001820: 2300 movs r3, #0 8001822: 75fb strb r3, [r7, #23] uint32_t tmp_cr1 = 0U; 8001824: 2300 movs r3, #0 8001826: 613b str r3, [r7, #16] uint32_t tmp_cr2 = 0U; 8001828: 2300 movs r3, #0 800182a: 60bb str r3, [r7, #8] uint32_t tmp_sqr1 = 0U; 800182c: 2300 movs r3, #0 800182e: 60fb str r3, [r7, #12] /* Check ADC handle */ if(hadc == NULL) 8001830: 687b ldr r3, [r7, #4] 8001832: 2b00 cmp r3, #0 8001834: d101 bne.n 800183a { return HAL_ERROR; 8001836: 2301 movs r3, #1 8001838: e0be b.n 80019b8 assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign)); assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode)); assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); assert_param(IS_ADC_EXTTRIG(hadc->Init.ExternalTrigConv)); if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE) 800183a: 687b ldr r3, [r7, #4] 800183c: 689b ldr r3, [r3, #8] 800183e: 2b00 cmp r3, #0 /* Refer to header of this file for more details on clock enabling */ /* procedure. */ /* Actions performed only if ADC is coming from state reset: */ /* - Initialization of ADC MSP */ if (hadc->State == HAL_ADC_STATE_RESET) 8001840: 687b ldr r3, [r7, #4] 8001842: 6a9b ldr r3, [r3, #40] ; 0x28 8001844: 2b00 cmp r3, #0 8001846: d109 bne.n 800185c { /* Initialize ADC error code */ ADC_CLEAR_ERRORCODE(hadc); 8001848: 687b ldr r3, [r7, #4] 800184a: 2200 movs r2, #0 800184c: 62da str r2, [r3, #44] ; 0x2c /* Allocate lock resource and initialize it */ hadc->Lock = HAL_UNLOCKED; 800184e: 687b ldr r3, [r7, #4] 8001850: 2200 movs r2, #0 8001852: f883 2024 strb.w r2, [r3, #36] ; 0x24 /* Init the low level hardware */ hadc->MspInitCallback(hadc); #else /* Init the low level hardware */ HAL_ADC_MspInit(hadc); 8001856: 6878 ldr r0, [r7, #4] 8001858: f7ff fc02 bl 8001060 /* Stop potential conversion on going, on regular and injected groups */ /* Disable ADC peripheral */ /* Note: In case of ADC already enabled, precaution to not launch an */ /* unwanted conversion while modifying register CR2 by writing 1 to */ /* bit ADON. */ tmp_hal_status = ADC_ConversionStop_Disable(hadc); 800185c: 6878 ldr r0, [r7, #4] 800185e: f000 fabf bl 8001de0 8001862: 4603 mov r3, r0 8001864: 75fb strb r3, [r7, #23] /* Configuration of ADC parameters if previous preliminary actions are */ /* correctly completed. */ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) && 8001866: 687b ldr r3, [r7, #4] 8001868: 6a9b ldr r3, [r3, #40] ; 0x28 800186a: f003 0310 and.w r3, r3, #16 800186e: 2b00 cmp r3, #0 8001870: f040 8099 bne.w 80019a6 8001874: 7dfb ldrb r3, [r7, #23] 8001876: 2b00 cmp r3, #0 8001878: f040 8095 bne.w 80019a6 (tmp_hal_status == HAL_OK) ) { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, 800187c: 687b ldr r3, [r7, #4] 800187e: 6a9b ldr r3, [r3, #40] ; 0x28 8001880: f423 5388 bic.w r3, r3, #4352 ; 0x1100 8001884: f023 0302 bic.w r3, r3, #2 8001888: f043 0202 orr.w r2, r3, #2 800188c: 687b ldr r3, [r7, #4] 800188e: 629a str r2, [r3, #40] ; 0x28 /* - continuous conversion mode */ /* Note: External trigger polarity (ADC_CR2_EXTTRIG) is set into */ /* HAL_ADC_Start_xxx functions because if set in this function, */ /* a conversion on injected group would start a conversion also on */ /* regular group after ADC enabling. */ tmp_cr2 |= (hadc->Init.DataAlign | 8001890: 687b ldr r3, [r7, #4] 8001892: 685a ldr r2, [r3, #4] ADC_CFGR_EXTSEL(hadc, hadc->Init.ExternalTrigConv) | 8001894: 687b ldr r3, [r7, #4] 8001896: 69db ldr r3, [r3, #28] tmp_cr2 |= (hadc->Init.DataAlign | 8001898: 431a orrs r2, r3 ADC_CR2_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) ); 800189a: 687b ldr r3, [r7, #4] 800189c: 7b1b ldrb r3, [r3, #12] 800189e: 005b lsls r3, r3, #1 ADC_CFGR_EXTSEL(hadc, hadc->Init.ExternalTrigConv) | 80018a0: 4313 orrs r3, r2 tmp_cr2 |= (hadc->Init.DataAlign | 80018a2: 68ba ldr r2, [r7, #8] 80018a4: 4313 orrs r3, r2 80018a6: 60bb str r3, [r7, #8] /* Configuration of ADC: */ /* - scan mode */ /* - discontinuous mode disable/enable */ /* - discontinuous mode number of conversions */ tmp_cr1 |= (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode)); 80018a8: 687b ldr r3, [r7, #4] 80018aa: 689b ldr r3, [r3, #8] 80018ac: f5b3 7f80 cmp.w r3, #256 ; 0x100 80018b0: d003 beq.n 80018ba 80018b2: 687b ldr r3, [r7, #4] 80018b4: 689b ldr r3, [r3, #8] 80018b6: 2b01 cmp r3, #1 80018b8: d102 bne.n 80018c0 80018ba: f44f 7380 mov.w r3, #256 ; 0x100 80018be: e000 b.n 80018c2 80018c0: 2300 movs r3, #0 80018c2: 693a ldr r2, [r7, #16] 80018c4: 4313 orrs r3, r2 80018c6: 613b str r3, [r7, #16] /* Enable discontinuous mode only if continuous mode is disabled */ /* Note: If parameter "Init.ScanConvMode" is set to disable, parameter */ /* discontinuous is set anyway, but will have no effect on ADC HW. */ if (hadc->Init.DiscontinuousConvMode == ENABLE) 80018c8: 687b ldr r3, [r7, #4] 80018ca: 7d1b ldrb r3, [r3, #20] 80018cc: 2b01 cmp r3, #1 80018ce: d119 bne.n 8001904 { if (hadc->Init.ContinuousConvMode == DISABLE) 80018d0: 687b ldr r3, [r7, #4] 80018d2: 7b1b ldrb r3, [r3, #12] 80018d4: 2b00 cmp r3, #0 80018d6: d109 bne.n 80018ec { /* Enable the selected ADC regular discontinuous mode */ /* Set the number of channels to be converted in discontinuous mode */ SET_BIT(tmp_cr1, ADC_CR1_DISCEN | 80018d8: 687b ldr r3, [r7, #4] 80018da: 699b ldr r3, [r3, #24] 80018dc: 3b01 subs r3, #1 80018de: 035a lsls r2, r3, #13 80018e0: 693b ldr r3, [r7, #16] 80018e2: 4313 orrs r3, r2 80018e4: f443 6300 orr.w r3, r3, #2048 ; 0x800 80018e8: 613b str r3, [r7, #16] 80018ea: e00b b.n 8001904 { /* ADC regular group settings continuous and sequencer discontinuous*/ /* cannot be enabled simultaneously. */ /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 80018ec: 687b ldr r3, [r7, #4] 80018ee: 6a9b ldr r3, [r3, #40] ; 0x28 80018f0: f043 0220 orr.w r2, r3, #32 80018f4: 687b ldr r3, [r7, #4] 80018f6: 629a str r2, [r3, #40] ; 0x28 /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 80018f8: 687b ldr r3, [r7, #4] 80018fa: 6adb ldr r3, [r3, #44] ; 0x2c 80018fc: f043 0201 orr.w r2, r3, #1 8001900: 687b ldr r3, [r7, #4] 8001902: 62da str r2, [r3, #44] ; 0x2c } } /* Update ADC configuration register CR1 with previous settings */ MODIFY_REG(hadc->Instance->CR1, 8001904: 687b ldr r3, [r7, #4] 8001906: 681b ldr r3, [r3, #0] 8001908: 685b ldr r3, [r3, #4] 800190a: f423 4169 bic.w r1, r3, #59648 ; 0xe900 800190e: 687b ldr r3, [r7, #4] 8001910: 681b ldr r3, [r3, #0] 8001912: 693a ldr r2, [r7, #16] 8001914: 430a orrs r2, r1 8001916: 605a str r2, [r3, #4] ADC_CR1_DISCEN | ADC_CR1_DISCNUM , tmp_cr1 ); /* Update ADC configuration register CR2 with previous settings */ MODIFY_REG(hadc->Instance->CR2, 8001918: 687b ldr r3, [r7, #4] 800191a: 681b ldr r3, [r3, #0] 800191c: 689a ldr r2, [r3, #8] 800191e: 4b28 ldr r3, [pc, #160] ; (80019c0 ) 8001920: 4013 ands r3, r2 8001922: 687a ldr r2, [r7, #4] 8001924: 6812 ldr r2, [r2, #0] 8001926: 68b9 ldr r1, [r7, #8] 8001928: 430b orrs r3, r1 800192a: 6093 str r3, [r2, #8] /* Note: Scan mode is present by hardware on this device and, if */ /* disabled, discards automatically nb of conversions. Anyway, nb of */ /* conversions is forced to 0x00 for alignment over all STM32 devices. */ /* - if scan mode is enabled, regular channels sequence length is set to */ /* parameter "NbrOfConversion" */ if (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode) == ADC_SCAN_ENABLE) 800192c: 687b ldr r3, [r7, #4] 800192e: 689b ldr r3, [r3, #8] 8001930: f5b3 7f80 cmp.w r3, #256 ; 0x100 8001934: d003 beq.n 800193e 8001936: 687b ldr r3, [r7, #4] 8001938: 689b ldr r3, [r3, #8] 800193a: 2b01 cmp r3, #1 800193c: d104 bne.n 8001948 { tmp_sqr1 = ADC_SQR1_L_SHIFT(hadc->Init.NbrOfConversion); 800193e: 687b ldr r3, [r7, #4] 8001940: 691b ldr r3, [r3, #16] 8001942: 3b01 subs r3, #1 8001944: 051b lsls r3, r3, #20 8001946: 60fb str r3, [r7, #12] } MODIFY_REG(hadc->Instance->SQR1, 8001948: 687b ldr r3, [r7, #4] 800194a: 681b ldr r3, [r3, #0] 800194c: 6adb ldr r3, [r3, #44] ; 0x2c 800194e: f423 0170 bic.w r1, r3, #15728640 ; 0xf00000 8001952: 687b ldr r3, [r7, #4] 8001954: 681b ldr r3, [r3, #0] 8001956: 68fa ldr r2, [r7, #12] 8001958: 430a orrs r2, r1 800195a: 62da str r2, [r3, #44] ; 0x2c /* ensure of no potential problem of ADC core IP clocking. */ /* Check through register CR2 (excluding bits set in other functions: */ /* execution control bits (ADON, JSWSTART, SWSTART), regular group bits */ /* (DMA), injected group bits (JEXTTRIG and JEXTSEL), channel internal */ /* measurement path bit (TSVREFE). */ if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA | 800195c: 687b ldr r3, [r7, #4] 800195e: 681b ldr r3, [r3, #0] 8001960: 689a ldr r2, [r3, #8] 8001962: 4b18 ldr r3, [pc, #96] ; (80019c4 ) 8001964: 4013 ands r3, r2 8001966: 68ba ldr r2, [r7, #8] 8001968: 429a cmp r2, r3 800196a: d10b bne.n 8001984 ADC_CR2_JEXTTRIG | ADC_CR2_JEXTSEL | ADC_CR2_TSVREFE )) == tmp_cr2) { /* Set ADC error code to none */ ADC_CLEAR_ERRORCODE(hadc); 800196c: 687b ldr r3, [r7, #4] 800196e: 2200 movs r2, #0 8001970: 62da str r2, [r3, #44] ; 0x2c /* Set the ADC state */ ADC_STATE_CLR_SET(hadc->State, 8001972: 687b ldr r3, [r7, #4] 8001974: 6a9b ldr r3, [r3, #40] ; 0x28 8001976: f023 0303 bic.w r3, r3, #3 800197a: f043 0201 orr.w r2, r3, #1 800197e: 687b ldr r3, [r7, #4] 8001980: 629a str r2, [r3, #40] ; 0x28 if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA | 8001982: e018 b.n 80019b6 HAL_ADC_STATE_READY); } else { /* Update ADC state machine to error */ ADC_STATE_CLR_SET(hadc->State, 8001984: 687b ldr r3, [r7, #4] 8001986: 6a9b ldr r3, [r3, #40] ; 0x28 8001988: f023 0312 bic.w r3, r3, #18 800198c: f043 0210 orr.w r2, r3, #16 8001990: 687b ldr r3, [r7, #4] 8001992: 629a str r2, [r3, #40] ; 0x28 HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL); /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 8001994: 687b ldr r3, [r7, #4] 8001996: 6adb ldr r3, [r3, #44] ; 0x2c 8001998: f043 0201 orr.w r2, r3, #1 800199c: 687b ldr r3, [r7, #4] 800199e: 62da str r2, [r3, #44] ; 0x2c tmp_hal_status = HAL_ERROR; 80019a0: 2301 movs r3, #1 80019a2: 75fb strb r3, [r7, #23] if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA | 80019a4: e007 b.n 80019b6 } else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 80019a6: 687b ldr r3, [r7, #4] 80019a8: 6a9b ldr r3, [r3, #40] ; 0x28 80019aa: f043 0210 orr.w r2, r3, #16 80019ae: 687b ldr r3, [r7, #4] 80019b0: 629a str r2, [r3, #40] ; 0x28 tmp_hal_status = HAL_ERROR; 80019b2: 2301 movs r3, #1 80019b4: 75fb strb r3, [r7, #23] } /* Return function status */ return tmp_hal_status; 80019b6: 7dfb ldrb r3, [r7, #23] } 80019b8: 4618 mov r0, r3 80019ba: 3718 adds r7, #24 80019bc: 46bd mov sp, r7 80019be: bd80 pop {r7, pc} 80019c0: ffe1f7fd .word 0xffe1f7fd 80019c4: ff1f0efe .word 0xff1f0efe 080019c8 : * Interruptions enabled in this function: None. * @param hadc: ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc) { 80019c8: b580 push {r7, lr} 80019ca: b084 sub sp, #16 80019cc: af00 add r7, sp, #0 80019ce: 6078 str r0, [r7, #4] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 80019d0: 2300 movs r3, #0 80019d2: 73fb strb r3, [r7, #15] /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Process locked */ __HAL_LOCK(hadc); 80019d4: 687b ldr r3, [r7, #4] 80019d6: f893 3024 ldrb.w r3, [r3, #36] ; 0x24 80019da: 2b01 cmp r3, #1 80019dc: d101 bne.n 80019e2 80019de: 2302 movs r3, #2 80019e0: e098 b.n 8001b14 80019e2: 687b ldr r3, [r7, #4] 80019e4: 2201 movs r2, #1 80019e6: f883 2024 strb.w r2, [r3, #36] ; 0x24 /* Enable the ADC peripheral */ tmp_hal_status = ADC_Enable(hadc); 80019ea: 6878 ldr r0, [r7, #4] 80019ec: f000 f99e bl 8001d2c 80019f0: 4603 mov r3, r0 80019f2: 73fb strb r3, [r7, #15] /* Start conversion if ADC is effectively enabled */ if (tmp_hal_status == HAL_OK) 80019f4: 7bfb ldrb r3, [r7, #15] 80019f6: 2b00 cmp r3, #0 80019f8: f040 8087 bne.w 8001b0a { /* Set ADC state */ /* - Clear state bitfield related to regular group conversion results */ /* - Set state bitfield related to regular operation */ ADC_STATE_CLR_SET(hadc->State, 80019fc: 687b ldr r3, [r7, #4] 80019fe: 6a9b ldr r3, [r3, #40] ; 0x28 8001a00: f423 7340 bic.w r3, r3, #768 ; 0x300 8001a04: f023 0301 bic.w r3, r3, #1 8001a08: f443 7280 orr.w r2, r3, #256 ; 0x100 8001a0c: 687b ldr r3, [r7, #4] 8001a0e: 629a str r2, [r3, #40] ; 0x28 HAL_ADC_STATE_REG_BUSY); /* Set group injected state (from auto-injection) and multimode state */ /* for all cases of multimode: independent mode, multimode ADC master */ /* or multimode ADC slave (for devices with several ADCs): */ if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc)) 8001a10: 687b ldr r3, [r7, #4] 8001a12: 681b ldr r3, [r3, #0] 8001a14: 4a41 ldr r2, [pc, #260] ; (8001b1c ) 8001a16: 4293 cmp r3, r2 8001a18: d105 bne.n 8001a26 8001a1a: 4b41 ldr r3, [pc, #260] ; (8001b20 ) 8001a1c: 685b ldr r3, [r3, #4] 8001a1e: f403 2370 and.w r3, r3, #983040 ; 0xf0000 8001a22: 2b00 cmp r3, #0 8001a24: d115 bne.n 8001a52 { /* Set ADC state (ADC independent or master) */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); 8001a26: 687b ldr r3, [r7, #4] 8001a28: 6a9b ldr r3, [r3, #40] ; 0x28 8001a2a: f423 1280 bic.w r2, r3, #1048576 ; 0x100000 8001a2e: 687b ldr r3, [r7, #4] 8001a30: 629a str r2, [r3, #40] ; 0x28 /* If conversions on group regular are also triggering group injected, */ /* update ADC state. */ if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET) 8001a32: 687b ldr r3, [r7, #4] 8001a34: 681b ldr r3, [r3, #0] 8001a36: 685b ldr r3, [r3, #4] 8001a38: f403 6380 and.w r3, r3, #1024 ; 0x400 8001a3c: 2b00 cmp r3, #0 8001a3e: d026 beq.n 8001a8e { ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); 8001a40: 687b ldr r3, [r7, #4] 8001a42: 6a9b ldr r3, [r3, #40] ; 0x28 8001a44: f423 5340 bic.w r3, r3, #12288 ; 0x3000 8001a48: f443 5280 orr.w r2, r3, #4096 ; 0x1000 8001a4c: 687b ldr r3, [r7, #4] 8001a4e: 629a str r2, [r3, #40] ; 0x28 if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET) 8001a50: e01d b.n 8001a8e } } else { /* Set ADC state (ADC slave) */ SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); 8001a52: 687b ldr r3, [r7, #4] 8001a54: 6a9b ldr r3, [r3, #40] ; 0x28 8001a56: f443 1280 orr.w r2, r3, #1048576 ; 0x100000 8001a5a: 687b ldr r3, [r7, #4] 8001a5c: 629a str r2, [r3, #40] ; 0x28 /* If conversions on group regular are also triggering group injected, */ /* update ADC state. */ if (ADC_MULTIMODE_AUTO_INJECTED(hadc)) 8001a5e: 687b ldr r3, [r7, #4] 8001a60: 681b ldr r3, [r3, #0] 8001a62: 4a2f ldr r2, [pc, #188] ; (8001b20 ) 8001a64: 4293 cmp r3, r2 8001a66: d004 beq.n 8001a72 8001a68: 687b ldr r3, [r7, #4] 8001a6a: 681b ldr r3, [r3, #0] 8001a6c: 4a2b ldr r2, [pc, #172] ; (8001b1c ) 8001a6e: 4293 cmp r3, r2 8001a70: d10d bne.n 8001a8e 8001a72: 4b2b ldr r3, [pc, #172] ; (8001b20 ) 8001a74: 685b ldr r3, [r3, #4] 8001a76: f403 6380 and.w r3, r3, #1024 ; 0x400 8001a7a: 2b00 cmp r3, #0 8001a7c: d007 beq.n 8001a8e { ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); 8001a7e: 687b ldr r3, [r7, #4] 8001a80: 6a9b ldr r3, [r3, #40] ; 0x28 8001a82: f423 5340 bic.w r3, r3, #12288 ; 0x3000 8001a86: f443 5280 orr.w r2, r3, #4096 ; 0x1000 8001a8a: 687b ldr r3, [r7, #4] 8001a8c: 629a str r2, [r3, #40] ; 0x28 } } /* State machine update: Check if an injected conversion is ongoing */ if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) 8001a8e: 687b ldr r3, [r7, #4] 8001a90: 6a9b ldr r3, [r3, #40] ; 0x28 8001a92: f403 5380 and.w r3, r3, #4096 ; 0x1000 8001a96: 2b00 cmp r3, #0 8001a98: d006 beq.n 8001aa8 { /* Reset ADC error code fields related to conversions on group regular */ CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); 8001a9a: 687b ldr r3, [r7, #4] 8001a9c: 6adb ldr r3, [r3, #44] ; 0x2c 8001a9e: f023 0206 bic.w r2, r3, #6 8001aa2: 687b ldr r3, [r7, #4] 8001aa4: 62da str r2, [r3, #44] ; 0x2c 8001aa6: e002 b.n 8001aae } else { /* Reset ADC all error code fields */ ADC_CLEAR_ERRORCODE(hadc); 8001aa8: 687b ldr r3, [r7, #4] 8001aaa: 2200 movs r2, #0 8001aac: 62da str r2, [r3, #44] ; 0x2c } /* Process unlocked */ /* Unlock before starting ADC conversions: in case of potential */ /* interruption, to let the process to ADC IRQ Handler. */ __HAL_UNLOCK(hadc); 8001aae: 687b ldr r3, [r7, #4] 8001ab0: 2200 movs r2, #0 8001ab2: f883 2024 strb.w r2, [r3, #36] ; 0x24 /* Clear regular group conversion flag */ /* (To ensure of no unknown state from potential previous ADC operations) */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC); 8001ab6: 687b ldr r3, [r7, #4] 8001ab8: 681b ldr r3, [r3, #0] 8001aba: f06f 0202 mvn.w r2, #2 8001abe: 601a str r2, [r3, #0] /* - if ADC is slave, ADC is enabled only (conversion is not started). */ /* - if ADC is master, ADC is enabled and conversion is started. */ /* If ADC is master, ADC is enabled and conversion is started. */ /* Note: Alternate trigger for single conversion could be to force an */ /* additional set of bit ADON "hadc->Instance->CR2 |= ADC_CR2_ADON;"*/ if (ADC_IS_SOFTWARE_START_REGULAR(hadc) && 8001ac0: 687b ldr r3, [r7, #4] 8001ac2: 681b ldr r3, [r3, #0] 8001ac4: 689b ldr r3, [r3, #8] 8001ac6: f403 2360 and.w r3, r3, #917504 ; 0xe0000 8001aca: f5b3 2f60 cmp.w r3, #917504 ; 0xe0000 8001ace: d113 bne.n 8001af8 ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc) ) 8001ad0: 687b ldr r3, [r7, #4] 8001ad2: 681b ldr r3, [r3, #0] if (ADC_IS_SOFTWARE_START_REGULAR(hadc) && 8001ad4: 4a11 ldr r2, [pc, #68] ; (8001b1c ) 8001ad6: 4293 cmp r3, r2 8001ad8: d105 bne.n 8001ae6 ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc) ) 8001ada: 4b11 ldr r3, [pc, #68] ; (8001b20 ) 8001adc: 685b ldr r3, [r3, #4] 8001ade: f403 2370 and.w r3, r3, #983040 ; 0xf0000 if (ADC_IS_SOFTWARE_START_REGULAR(hadc) && 8001ae2: 2b00 cmp r3, #0 8001ae4: d108 bne.n 8001af8 { /* Start ADC conversion on regular group with SW start */ SET_BIT(hadc->Instance->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTTRIG)); 8001ae6: 687b ldr r3, [r7, #4] 8001ae8: 681b ldr r3, [r3, #0] 8001aea: 689a ldr r2, [r3, #8] 8001aec: 687b ldr r3, [r7, #4] 8001aee: 681b ldr r3, [r3, #0] 8001af0: f442 02a0 orr.w r2, r2, #5242880 ; 0x500000 8001af4: 609a str r2, [r3, #8] 8001af6: e00c b.n 8001b12 } else { /* Start ADC conversion on regular group with external trigger */ SET_BIT(hadc->Instance->CR2, ADC_CR2_EXTTRIG); 8001af8: 687b ldr r3, [r7, #4] 8001afa: 681b ldr r3, [r3, #0] 8001afc: 689a ldr r2, [r3, #8] 8001afe: 687b ldr r3, [r7, #4] 8001b00: 681b ldr r3, [r3, #0] 8001b02: f442 1280 orr.w r2, r2, #1048576 ; 0x100000 8001b06: 609a str r2, [r3, #8] 8001b08: e003 b.n 8001b12 } } else { /* Process unlocked */ __HAL_UNLOCK(hadc); 8001b0a: 687b ldr r3, [r7, #4] 8001b0c: 2200 movs r2, #0 8001b0e: f883 2024 strb.w r2, [r3, #36] ; 0x24 } /* Return function status */ return tmp_hal_status; 8001b12: 7bfb ldrb r3, [r7, #15] } 8001b14: 4618 mov r0, r3 8001b16: 3710 adds r7, #16 8001b18: 46bd mov sp, r7 8001b1a: bd80 pop {r7, pc} 8001b1c: 40012800 .word 0x40012800 8001b20: 40012400 .word 0x40012400 08001b24 : * or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_EOS). * @param hadc: ADC handle * @retval ADC group regular conversion data */ uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc) { 8001b24: b480 push {r7} 8001b26: b083 sub sp, #12 8001b28: af00 add r7, sp, #0 8001b2a: 6078 str r0, [r7, #4] /* Note: EOC flag is not cleared here by software because automatically */ /* cleared by hardware when reading register DR. */ /* Return ADC converted value */ return hadc->Instance->DR; 8001b2c: 687b ldr r3, [r7, #4] 8001b2e: 681b ldr r3, [r3, #0] 8001b30: 6cdb ldr r3, [r3, #76] ; 0x4c } 8001b32: 4618 mov r0, r3 8001b34: 370c adds r7, #12 8001b36: 46bd mov sp, r7 8001b38: bc80 pop {r7} 8001b3a: 4770 bx lr 08001b3c : * @param hadc: ADC handle * @param sConfig: Structure of ADC channel for regular group. * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig) { 8001b3c: b480 push {r7} 8001b3e: b085 sub sp, #20 8001b40: af00 add r7, sp, #0 8001b42: 6078 str r0, [r7, #4] 8001b44: 6039 str r1, [r7, #0] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 8001b46: 2300 movs r3, #0 8001b48: 73fb strb r3, [r7, #15] __IO uint32_t wait_loop_index = 0U; 8001b4a: 2300 movs r3, #0 8001b4c: 60bb str r3, [r7, #8] assert_param(IS_ADC_CHANNEL(sConfig->Channel)); assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank)); assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime)); /* Process locked */ __HAL_LOCK(hadc); 8001b4e: 687b ldr r3, [r7, #4] 8001b50: f893 3024 ldrb.w r3, [r3, #36] ; 0x24 8001b54: 2b01 cmp r3, #1 8001b56: d101 bne.n 8001b5c 8001b58: 2302 movs r3, #2 8001b5a: e0dc b.n 8001d16 8001b5c: 687b ldr r3, [r7, #4] 8001b5e: 2201 movs r2, #1 8001b60: f883 2024 strb.w r2, [r3, #36] ; 0x24 /* Regular sequence configuration */ /* For Rank 1 to 6 */ if (sConfig->Rank < 7U) 8001b64: 683b ldr r3, [r7, #0] 8001b66: 685b ldr r3, [r3, #4] 8001b68: 2b06 cmp r3, #6 8001b6a: d81c bhi.n 8001ba6 { MODIFY_REG(hadc->Instance->SQR3 , 8001b6c: 687b ldr r3, [r7, #4] 8001b6e: 681b ldr r3, [r3, #0] 8001b70: 6b59 ldr r1, [r3, #52] ; 0x34 8001b72: 683b ldr r3, [r7, #0] 8001b74: 685a ldr r2, [r3, #4] 8001b76: 4613 mov r3, r2 8001b78: 009b lsls r3, r3, #2 8001b7a: 4413 add r3, r2 8001b7c: 3b05 subs r3, #5 8001b7e: 221f movs r2, #31 8001b80: fa02 f303 lsl.w r3, r2, r3 8001b84: 43db mvns r3, r3 8001b86: 4019 ands r1, r3 8001b88: 683b ldr r3, [r7, #0] 8001b8a: 6818 ldr r0, [r3, #0] 8001b8c: 683b ldr r3, [r7, #0] 8001b8e: 685a ldr r2, [r3, #4] 8001b90: 4613 mov r3, r2 8001b92: 009b lsls r3, r3, #2 8001b94: 4413 add r3, r2 8001b96: 3b05 subs r3, #5 8001b98: fa00 f203 lsl.w r2, r0, r3 8001b9c: 687b ldr r3, [r7, #4] 8001b9e: 681b ldr r3, [r3, #0] 8001ba0: 430a orrs r2, r1 8001ba2: 635a str r2, [r3, #52] ; 0x34 8001ba4: e03c b.n 8001c20 ADC_SQR3_RK(ADC_SQR3_SQ1, sConfig->Rank) , ADC_SQR3_RK(sConfig->Channel, sConfig->Rank) ); } /* For Rank 7 to 12 */ else if (sConfig->Rank < 13U) 8001ba6: 683b ldr r3, [r7, #0] 8001ba8: 685b ldr r3, [r3, #4] 8001baa: 2b0c cmp r3, #12 8001bac: d81c bhi.n 8001be8 { MODIFY_REG(hadc->Instance->SQR2 , 8001bae: 687b ldr r3, [r7, #4] 8001bb0: 681b ldr r3, [r3, #0] 8001bb2: 6b19 ldr r1, [r3, #48] ; 0x30 8001bb4: 683b ldr r3, [r7, #0] 8001bb6: 685a ldr r2, [r3, #4] 8001bb8: 4613 mov r3, r2 8001bba: 009b lsls r3, r3, #2 8001bbc: 4413 add r3, r2 8001bbe: 3b23 subs r3, #35 ; 0x23 8001bc0: 221f movs r2, #31 8001bc2: fa02 f303 lsl.w r3, r2, r3 8001bc6: 43db mvns r3, r3 8001bc8: 4019 ands r1, r3 8001bca: 683b ldr r3, [r7, #0] 8001bcc: 6818 ldr r0, [r3, #0] 8001bce: 683b ldr r3, [r7, #0] 8001bd0: 685a ldr r2, [r3, #4] 8001bd2: 4613 mov r3, r2 8001bd4: 009b lsls r3, r3, #2 8001bd6: 4413 add r3, r2 8001bd8: 3b23 subs r3, #35 ; 0x23 8001bda: fa00 f203 lsl.w r2, r0, r3 8001bde: 687b ldr r3, [r7, #4] 8001be0: 681b ldr r3, [r3, #0] 8001be2: 430a orrs r2, r1 8001be4: 631a str r2, [r3, #48] ; 0x30 8001be6: e01b b.n 8001c20 ADC_SQR2_RK(sConfig->Channel, sConfig->Rank) ); } /* For Rank 13 to 16 */ else { MODIFY_REG(hadc->Instance->SQR1 , 8001be8: 687b ldr r3, [r7, #4] 8001bea: 681b ldr r3, [r3, #0] 8001bec: 6ad9 ldr r1, [r3, #44] ; 0x2c 8001bee: 683b ldr r3, [r7, #0] 8001bf0: 685a ldr r2, [r3, #4] 8001bf2: 4613 mov r3, r2 8001bf4: 009b lsls r3, r3, #2 8001bf6: 4413 add r3, r2 8001bf8: 3b41 subs r3, #65 ; 0x41 8001bfa: 221f movs r2, #31 8001bfc: fa02 f303 lsl.w r3, r2, r3 8001c00: 43db mvns r3, r3 8001c02: 4019 ands r1, r3 8001c04: 683b ldr r3, [r7, #0] 8001c06: 6818 ldr r0, [r3, #0] 8001c08: 683b ldr r3, [r7, #0] 8001c0a: 685a ldr r2, [r3, #4] 8001c0c: 4613 mov r3, r2 8001c0e: 009b lsls r3, r3, #2 8001c10: 4413 add r3, r2 8001c12: 3b41 subs r3, #65 ; 0x41 8001c14: fa00 f203 lsl.w r2, r0, r3 8001c18: 687b ldr r3, [r7, #4] 8001c1a: 681b ldr r3, [r3, #0] 8001c1c: 430a orrs r2, r1 8001c1e: 62da str r2, [r3, #44] ; 0x2c } /* Channel sampling time configuration */ /* For channels 10 to 17 */ if (sConfig->Channel >= ADC_CHANNEL_10) 8001c20: 683b ldr r3, [r7, #0] 8001c22: 681b ldr r3, [r3, #0] 8001c24: 2b09 cmp r3, #9 8001c26: d91c bls.n 8001c62 { MODIFY_REG(hadc->Instance->SMPR1 , 8001c28: 687b ldr r3, [r7, #4] 8001c2a: 681b ldr r3, [r3, #0] 8001c2c: 68d9 ldr r1, [r3, #12] 8001c2e: 683b ldr r3, [r7, #0] 8001c30: 681a ldr r2, [r3, #0] 8001c32: 4613 mov r3, r2 8001c34: 005b lsls r3, r3, #1 8001c36: 4413 add r3, r2 8001c38: 3b1e subs r3, #30 8001c3a: 2207 movs r2, #7 8001c3c: fa02 f303 lsl.w r3, r2, r3 8001c40: 43db mvns r3, r3 8001c42: 4019 ands r1, r3 8001c44: 683b ldr r3, [r7, #0] 8001c46: 6898 ldr r0, [r3, #8] 8001c48: 683b ldr r3, [r7, #0] 8001c4a: 681a ldr r2, [r3, #0] 8001c4c: 4613 mov r3, r2 8001c4e: 005b lsls r3, r3, #1 8001c50: 4413 add r3, r2 8001c52: 3b1e subs r3, #30 8001c54: fa00 f203 lsl.w r2, r0, r3 8001c58: 687b ldr r3, [r7, #4] 8001c5a: 681b ldr r3, [r3, #0] 8001c5c: 430a orrs r2, r1 8001c5e: 60da str r2, [r3, #12] 8001c60: e019 b.n 8001c96 ADC_SMPR1(ADC_SMPR1_SMP10, sConfig->Channel) , ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel) ); } else /* For channels 0 to 9 */ { MODIFY_REG(hadc->Instance->SMPR2 , 8001c62: 687b ldr r3, [r7, #4] 8001c64: 681b ldr r3, [r3, #0] 8001c66: 6919 ldr r1, [r3, #16] 8001c68: 683b ldr r3, [r7, #0] 8001c6a: 681a ldr r2, [r3, #0] 8001c6c: 4613 mov r3, r2 8001c6e: 005b lsls r3, r3, #1 8001c70: 4413 add r3, r2 8001c72: 2207 movs r2, #7 8001c74: fa02 f303 lsl.w r3, r2, r3 8001c78: 43db mvns r3, r3 8001c7a: 4019 ands r1, r3 8001c7c: 683b ldr r3, [r7, #0] 8001c7e: 6898 ldr r0, [r3, #8] 8001c80: 683b ldr r3, [r7, #0] 8001c82: 681a ldr r2, [r3, #0] 8001c84: 4613 mov r3, r2 8001c86: 005b lsls r3, r3, #1 8001c88: 4413 add r3, r2 8001c8a: fa00 f203 lsl.w r2, r0, r3 8001c8e: 687b ldr r3, [r7, #4] 8001c90: 681b ldr r3, [r3, #0] 8001c92: 430a orrs r2, r1 8001c94: 611a str r2, [r3, #16] ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel) ); } /* If ADC1 Channel_16 or Channel_17 is selected, enable Temperature sensor */ /* and VREFINT measurement path. */ if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) || 8001c96: 683b ldr r3, [r7, #0] 8001c98: 681b ldr r3, [r3, #0] 8001c9a: 2b10 cmp r3, #16 8001c9c: d003 beq.n 8001ca6 (sConfig->Channel == ADC_CHANNEL_VREFINT) ) 8001c9e: 683b ldr r3, [r7, #0] 8001ca0: 681b ldr r3, [r3, #0] if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) || 8001ca2: 2b11 cmp r3, #17 8001ca4: d132 bne.n 8001d0c { /* For STM32F1 devices with several ADC: Only ADC1 can access internal */ /* measurement channels (VrefInt/TempSensor). If these channels are */ /* intended to be set on other ADC instances, an error is reported. */ if (hadc->Instance == ADC1) 8001ca6: 687b ldr r3, [r7, #4] 8001ca8: 681b ldr r3, [r3, #0] 8001caa: 4a1d ldr r2, [pc, #116] ; (8001d20 ) 8001cac: 4293 cmp r3, r2 8001cae: d125 bne.n 8001cfc { if (READ_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE) == RESET) 8001cb0: 687b ldr r3, [r7, #4] 8001cb2: 681b ldr r3, [r3, #0] 8001cb4: 689b ldr r3, [r3, #8] 8001cb6: f403 0300 and.w r3, r3, #8388608 ; 0x800000 8001cba: 2b00 cmp r3, #0 8001cbc: d126 bne.n 8001d0c { SET_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE); 8001cbe: 687b ldr r3, [r7, #4] 8001cc0: 681b ldr r3, [r3, #0] 8001cc2: 689a ldr r2, [r3, #8] 8001cc4: 687b ldr r3, [r7, #4] 8001cc6: 681b ldr r3, [r3, #0] 8001cc8: f442 0200 orr.w r2, r2, #8388608 ; 0x800000 8001ccc: 609a str r2, [r3, #8] if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) 8001cce: 683b ldr r3, [r7, #0] 8001cd0: 681b ldr r3, [r3, #0] 8001cd2: 2b10 cmp r3, #16 8001cd4: d11a bne.n 8001d0c { /* Delay for temperature sensor stabilization time */ /* Compute number of CPU cycles to wait for */ wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U)); 8001cd6: 4b13 ldr r3, [pc, #76] ; (8001d24 ) 8001cd8: 681b ldr r3, [r3, #0] 8001cda: 4a13 ldr r2, [pc, #76] ; (8001d28 ) 8001cdc: fba2 2303 umull r2, r3, r2, r3 8001ce0: 0c9a lsrs r2, r3, #18 8001ce2: 4613 mov r3, r2 8001ce4: 009b lsls r3, r3, #2 8001ce6: 4413 add r3, r2 8001ce8: 005b lsls r3, r3, #1 8001cea: 60bb str r3, [r7, #8] while(wait_loop_index != 0U) 8001cec: e002 b.n 8001cf4 { wait_loop_index--; 8001cee: 68bb ldr r3, [r7, #8] 8001cf0: 3b01 subs r3, #1 8001cf2: 60bb str r3, [r7, #8] while(wait_loop_index != 0U) 8001cf4: 68bb ldr r3, [r7, #8] 8001cf6: 2b00 cmp r3, #0 8001cf8: d1f9 bne.n 8001cee 8001cfa: e007 b.n 8001d0c } } else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 8001cfc: 687b ldr r3, [r7, #4] 8001cfe: 6a9b ldr r3, [r3, #40] ; 0x28 8001d00: f043 0220 orr.w r2, r3, #32 8001d04: 687b ldr r3, [r7, #4] 8001d06: 629a str r2, [r3, #40] ; 0x28 tmp_hal_status = HAL_ERROR; 8001d08: 2301 movs r3, #1 8001d0a: 73fb strb r3, [r7, #15] } } /* Process unlocked */ __HAL_UNLOCK(hadc); 8001d0c: 687b ldr r3, [r7, #4] 8001d0e: 2200 movs r2, #0 8001d10: f883 2024 strb.w r2, [r3, #36] ; 0x24 /* Return function status */ return tmp_hal_status; 8001d14: 7bfb ldrb r3, [r7, #15] } 8001d16: 4618 mov r0, r3 8001d18: 3714 adds r7, #20 8001d1a: 46bd mov sp, r7 8001d1c: bc80 pop {r7} 8001d1e: 4770 bx lr 8001d20: 40012400 .word 0x40012400 8001d24: 20000000 .word 0x20000000 8001d28: 431bde83 .word 0x431bde83 08001d2c : * and voltage regulator must be enabled (done into HAL_ADC_Init()). * @param hadc: ADC handle * @retval HAL status. */ HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc) { 8001d2c: b580 push {r7, lr} 8001d2e: b084 sub sp, #16 8001d30: af00 add r7, sp, #0 8001d32: 6078 str r0, [r7, #4] uint32_t tickstart = 0U; 8001d34: 2300 movs r3, #0 8001d36: 60fb str r3, [r7, #12] __IO uint32_t wait_loop_index = 0U; 8001d38: 2300 movs r3, #0 8001d3a: 60bb str r3, [r7, #8] /* ADC enable and wait for ADC ready (in case of ADC is disabled or */ /* enabling phase not yet completed: flag ADC ready not yet set). */ /* Timeout implemented to not be stuck if ADC cannot be enabled (possible */ /* causes: ADC clock not running, ...). */ if (ADC_IS_ENABLE(hadc) == RESET) 8001d3c: 687b ldr r3, [r7, #4] 8001d3e: 681b ldr r3, [r3, #0] 8001d40: 689b ldr r3, [r3, #8] 8001d42: f003 0301 and.w r3, r3, #1 8001d46: 2b01 cmp r3, #1 8001d48: d040 beq.n 8001dcc { /* Enable the Peripheral */ __HAL_ADC_ENABLE(hadc); 8001d4a: 687b ldr r3, [r7, #4] 8001d4c: 681b ldr r3, [r3, #0] 8001d4e: 689a ldr r2, [r3, #8] 8001d50: 687b ldr r3, [r7, #4] 8001d52: 681b ldr r3, [r3, #0] 8001d54: f042 0201 orr.w r2, r2, #1 8001d58: 609a str r2, [r3, #8] /* Delay for ADC stabilization time */ /* Compute number of CPU cycles to wait for */ wait_loop_index = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U)); 8001d5a: 4b1f ldr r3, [pc, #124] ; (8001dd8 ) 8001d5c: 681b ldr r3, [r3, #0] 8001d5e: 4a1f ldr r2, [pc, #124] ; (8001ddc ) 8001d60: fba2 2303 umull r2, r3, r2, r3 8001d64: 0c9b lsrs r3, r3, #18 8001d66: 60bb str r3, [r7, #8] while(wait_loop_index != 0U) 8001d68: e002 b.n 8001d70 { wait_loop_index--; 8001d6a: 68bb ldr r3, [r7, #8] 8001d6c: 3b01 subs r3, #1 8001d6e: 60bb str r3, [r7, #8] while(wait_loop_index != 0U) 8001d70: 68bb ldr r3, [r7, #8] 8001d72: 2b00 cmp r3, #0 8001d74: d1f9 bne.n 8001d6a } /* Get tick count */ tickstart = HAL_GetTick(); 8001d76: f7ff fd21 bl 80017bc 8001d7a: 60f8 str r0, [r7, #12] /* Wait for ADC effectively enabled */ while(ADC_IS_ENABLE(hadc) == RESET) 8001d7c: e01f b.n 8001dbe { if((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT) 8001d7e: f7ff fd1d bl 80017bc 8001d82: 4602 mov r2, r0 8001d84: 68fb ldr r3, [r7, #12] 8001d86: 1ad3 subs r3, r2, r3 8001d88: 2b02 cmp r3, #2 8001d8a: d918 bls.n 8001dbe { /* New check to avoid false timeout detection in case of preemption */ if(ADC_IS_ENABLE(hadc) == RESET) 8001d8c: 687b ldr r3, [r7, #4] 8001d8e: 681b ldr r3, [r3, #0] 8001d90: 689b ldr r3, [r3, #8] 8001d92: f003 0301 and.w r3, r3, #1 8001d96: 2b01 cmp r3, #1 8001d98: d011 beq.n 8001dbe { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 8001d9a: 687b ldr r3, [r7, #4] 8001d9c: 6a9b ldr r3, [r3, #40] ; 0x28 8001d9e: f043 0210 orr.w r2, r3, #16 8001da2: 687b ldr r3, [r7, #4] 8001da4: 629a str r2, [r3, #40] ; 0x28 /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 8001da6: 687b ldr r3, [r7, #4] 8001da8: 6adb ldr r3, [r3, #44] ; 0x2c 8001daa: f043 0201 orr.w r2, r3, #1 8001dae: 687b ldr r3, [r7, #4] 8001db0: 62da str r2, [r3, #44] ; 0x2c /* Process unlocked */ __HAL_UNLOCK(hadc); 8001db2: 687b ldr r3, [r7, #4] 8001db4: 2200 movs r2, #0 8001db6: f883 2024 strb.w r2, [r3, #36] ; 0x24 return HAL_ERROR; 8001dba: 2301 movs r3, #1 8001dbc: e007 b.n 8001dce while(ADC_IS_ENABLE(hadc) == RESET) 8001dbe: 687b ldr r3, [r7, #4] 8001dc0: 681b ldr r3, [r3, #0] 8001dc2: 689b ldr r3, [r3, #8] 8001dc4: f003 0301 and.w r3, r3, #1 8001dc8: 2b01 cmp r3, #1 8001dca: d1d8 bne.n 8001d7e } } } /* Return HAL status */ return HAL_OK; 8001dcc: 2300 movs r3, #0 } 8001dce: 4618 mov r0, r3 8001dd0: 3710 adds r7, #16 8001dd2: 46bd mov sp, r7 8001dd4: bd80 pop {r7, pc} 8001dd6: bf00 nop 8001dd8: 20000000 .word 0x20000000 8001ddc: 431bde83 .word 0x431bde83 08001de0 : * stopped to disable the ADC. * @param hadc: ADC handle * @retval HAL status. */ HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef* hadc) { 8001de0: b580 push {r7, lr} 8001de2: b084 sub sp, #16 8001de4: af00 add r7, sp, #0 8001de6: 6078 str r0, [r7, #4] uint32_t tickstart = 0U; 8001de8: 2300 movs r3, #0 8001dea: 60fb str r3, [r7, #12] /* Verification if ADC is not already disabled */ if (ADC_IS_ENABLE(hadc) != RESET) 8001dec: 687b ldr r3, [r7, #4] 8001dee: 681b ldr r3, [r3, #0] 8001df0: 689b ldr r3, [r3, #8] 8001df2: f003 0301 and.w r3, r3, #1 8001df6: 2b01 cmp r3, #1 8001df8: d12e bne.n 8001e58 { /* Disable the ADC peripheral */ __HAL_ADC_DISABLE(hadc); 8001dfa: 687b ldr r3, [r7, #4] 8001dfc: 681b ldr r3, [r3, #0] 8001dfe: 689a ldr r2, [r3, #8] 8001e00: 687b ldr r3, [r7, #4] 8001e02: 681b ldr r3, [r3, #0] 8001e04: f022 0201 bic.w r2, r2, #1 8001e08: 609a str r2, [r3, #8] /* Get tick count */ tickstart = HAL_GetTick(); 8001e0a: f7ff fcd7 bl 80017bc 8001e0e: 60f8 str r0, [r7, #12] /* Wait for ADC effectively disabled */ while(ADC_IS_ENABLE(hadc) != RESET) 8001e10: e01b b.n 8001e4a { if((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT) 8001e12: f7ff fcd3 bl 80017bc 8001e16: 4602 mov r2, r0 8001e18: 68fb ldr r3, [r7, #12] 8001e1a: 1ad3 subs r3, r2, r3 8001e1c: 2b02 cmp r3, #2 8001e1e: d914 bls.n 8001e4a { /* New check to avoid false timeout detection in case of preemption */ if(ADC_IS_ENABLE(hadc) != RESET) 8001e20: 687b ldr r3, [r7, #4] 8001e22: 681b ldr r3, [r3, #0] 8001e24: 689b ldr r3, [r3, #8] 8001e26: f003 0301 and.w r3, r3, #1 8001e2a: 2b01 cmp r3, #1 8001e2c: d10d bne.n 8001e4a { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 8001e2e: 687b ldr r3, [r7, #4] 8001e30: 6a9b ldr r3, [r3, #40] ; 0x28 8001e32: f043 0210 orr.w r2, r3, #16 8001e36: 687b ldr r3, [r7, #4] 8001e38: 629a str r2, [r3, #40] ; 0x28 /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 8001e3a: 687b ldr r3, [r7, #4] 8001e3c: 6adb ldr r3, [r3, #44] ; 0x2c 8001e3e: f043 0201 orr.w r2, r3, #1 8001e42: 687b ldr r3, [r7, #4] 8001e44: 62da str r2, [r3, #44] ; 0x2c return HAL_ERROR; 8001e46: 2301 movs r3, #1 8001e48: e007 b.n 8001e5a while(ADC_IS_ENABLE(hadc) != RESET) 8001e4a: 687b ldr r3, [r7, #4] 8001e4c: 681b ldr r3, [r3, #0] 8001e4e: 689b ldr r3, [r3, #8] 8001e50: f003 0301 and.w r3, r3, #1 8001e54: 2b01 cmp r3, #1 8001e56: d0dc beq.n 8001e12 } } } /* Return HAL status */ return HAL_OK; 8001e58: 2300 movs r3, #0 } 8001e5a: 4618 mov r0, r3 8001e5c: 3710 adds r7, #16 8001e5e: 46bd mov sp, r7 8001e60: bd80 pop {r7, pc} ... 08001e64 <__NVIC_SetPriorityGrouping>: In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 8001e64: b480 push {r7} 8001e66: b085 sub sp, #20 8001e68: af00 add r7, sp, #0 8001e6a: 6078 str r0, [r7, #4] uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 8001e6c: 687b ldr r3, [r7, #4] 8001e6e: f003 0307 and.w r3, r3, #7 8001e72: 60fb str r3, [r7, #12] reg_value = SCB->AIRCR; /* read old register configuration */ 8001e74: 4b0c ldr r3, [pc, #48] ; (8001ea8 <__NVIC_SetPriorityGrouping+0x44>) 8001e76: 68db ldr r3, [r3, #12] 8001e78: 60bb str r3, [r7, #8] reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ 8001e7a: 68ba ldr r2, [r7, #8] 8001e7c: f64f 03ff movw r3, #63743 ; 0xf8ff 8001e80: 4013 ands r3, r2 8001e82: 60bb str r3, [r7, #8] reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ 8001e84: 68fb ldr r3, [r7, #12] 8001e86: 021a lsls r2, r3, #8 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 8001e88: 68bb ldr r3, [r7, #8] 8001e8a: 4313 orrs r3, r2 reg_value = (reg_value | 8001e8c: f043 63bf orr.w r3, r3, #100139008 ; 0x5f80000 8001e90: f443 3300 orr.w r3, r3, #131072 ; 0x20000 8001e94: 60bb str r3, [r7, #8] SCB->AIRCR = reg_value; 8001e96: 4a04 ldr r2, [pc, #16] ; (8001ea8 <__NVIC_SetPriorityGrouping+0x44>) 8001e98: 68bb ldr r3, [r7, #8] 8001e9a: 60d3 str r3, [r2, #12] } 8001e9c: bf00 nop 8001e9e: 3714 adds r7, #20 8001ea0: 46bd mov sp, r7 8001ea2: bc80 pop {r7} 8001ea4: 4770 bx lr 8001ea6: bf00 nop 8001ea8: e000ed00 .word 0xe000ed00 08001eac <__NVIC_GetPriorityGrouping>: \brief Get Priority Grouping \details Reads the priority grouping field from the NVIC Interrupt Controller. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) { 8001eac: b480 push {r7} 8001eae: af00 add r7, sp, #0 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); 8001eb0: 4b04 ldr r3, [pc, #16] ; (8001ec4 <__NVIC_GetPriorityGrouping+0x18>) 8001eb2: 68db ldr r3, [r3, #12] 8001eb4: 0a1b lsrs r3, r3, #8 8001eb6: f003 0307 and.w r3, r3, #7 } 8001eba: 4618 mov r0, r3 8001ebc: 46bd mov sp, r7 8001ebe: bc80 pop {r7} 8001ec0: 4770 bx lr 8001ec2: bf00 nop 8001ec4: e000ed00 .word 0xe000ed00 08001ec8 <__NVIC_SetPriority>: \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { 8001ec8: b480 push {r7} 8001eca: b083 sub sp, #12 8001ecc: af00 add r7, sp, #0 8001ece: 4603 mov r3, r0 8001ed0: 6039 str r1, [r7, #0] 8001ed2: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) 8001ed4: f997 3007 ldrsb.w r3, [r7, #7] 8001ed8: 2b00 cmp r3, #0 8001eda: db0a blt.n 8001ef2 <__NVIC_SetPriority+0x2a> { NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 8001edc: 683b ldr r3, [r7, #0] 8001ede: b2da uxtb r2, r3 8001ee0: 490c ldr r1, [pc, #48] ; (8001f14 <__NVIC_SetPriority+0x4c>) 8001ee2: f997 3007 ldrsb.w r3, [r7, #7] 8001ee6: 0112 lsls r2, r2, #4 8001ee8: b2d2 uxtb r2, r2 8001eea: 440b add r3, r1 8001eec: f883 2300 strb.w r2, [r3, #768] ; 0x300 } else { SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } 8001ef0: e00a b.n 8001f08 <__NVIC_SetPriority+0x40> SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 8001ef2: 683b ldr r3, [r7, #0] 8001ef4: b2da uxtb r2, r3 8001ef6: 4908 ldr r1, [pc, #32] ; (8001f18 <__NVIC_SetPriority+0x50>) 8001ef8: 79fb ldrb r3, [r7, #7] 8001efa: f003 030f and.w r3, r3, #15 8001efe: 3b04 subs r3, #4 8001f00: 0112 lsls r2, r2, #4 8001f02: b2d2 uxtb r2, r2 8001f04: 440b add r3, r1 8001f06: 761a strb r2, [r3, #24] } 8001f08: bf00 nop 8001f0a: 370c adds r7, #12 8001f0c: 46bd mov sp, r7 8001f0e: bc80 pop {r7} 8001f10: 4770 bx lr 8001f12: bf00 nop 8001f14: e000e100 .word 0xe000e100 8001f18: e000ed00 .word 0xe000ed00 08001f1c : \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { 8001f1c: b480 push {r7} 8001f1e: b089 sub sp, #36 ; 0x24 8001f20: af00 add r7, sp, #0 8001f22: 60f8 str r0, [r7, #12] 8001f24: 60b9 str r1, [r7, #8] 8001f26: 607a str r2, [r7, #4] uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 8001f28: 68fb ldr r3, [r7, #12] 8001f2a: f003 0307 and.w r3, r3, #7 8001f2e: 61fb str r3, [r7, #28] uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 8001f30: 69fb ldr r3, [r7, #28] 8001f32: f1c3 0307 rsb r3, r3, #7 8001f36: 2b04 cmp r3, #4 8001f38: bf28 it cs 8001f3a: 2304 movcs r3, #4 8001f3c: 61bb str r3, [r7, #24] SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 8001f3e: 69fb ldr r3, [r7, #28] 8001f40: 3304 adds r3, #4 8001f42: 2b06 cmp r3, #6 8001f44: d902 bls.n 8001f4c 8001f46: 69fb ldr r3, [r7, #28] 8001f48: 3b03 subs r3, #3 8001f4a: e000 b.n 8001f4e 8001f4c: 2300 movs r3, #0 8001f4e: 617b str r3, [r7, #20] return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 8001f50: f04f 32ff mov.w r2, #4294967295 8001f54: 69bb ldr r3, [r7, #24] 8001f56: fa02 f303 lsl.w r3, r2, r3 8001f5a: 43da mvns r2, r3 8001f5c: 68bb ldr r3, [r7, #8] 8001f5e: 401a ands r2, r3 8001f60: 697b ldr r3, [r7, #20] 8001f62: 409a lsls r2, r3 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) 8001f64: f04f 31ff mov.w r1, #4294967295 8001f68: 697b ldr r3, [r7, #20] 8001f6a: fa01 f303 lsl.w r3, r1, r3 8001f6e: 43d9 mvns r1, r3 8001f70: 687b ldr r3, [r7, #4] 8001f72: 400b ands r3, r1 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 8001f74: 4313 orrs r3, r2 ); } 8001f76: 4618 mov r0, r3 8001f78: 3724 adds r7, #36 ; 0x24 8001f7a: 46bd mov sp, r7 8001f7c: bc80 pop {r7} 8001f7e: 4770 bx lr 08001f80 : \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { 8001f80: b580 push {r7, lr} 8001f82: b082 sub sp, #8 8001f84: af00 add r7, sp, #0 8001f86: 6078 str r0, [r7, #4] if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) 8001f88: 687b ldr r3, [r7, #4] 8001f8a: 3b01 subs r3, #1 8001f8c: f1b3 7f80 cmp.w r3, #16777216 ; 0x1000000 8001f90: d301 bcc.n 8001f96 { return (1UL); /* Reload value impossible */ 8001f92: 2301 movs r3, #1 8001f94: e00f b.n 8001fb6 } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 8001f96: 4a0a ldr r2, [pc, #40] ; (8001fc0 ) 8001f98: 687b ldr r3, [r7, #4] 8001f9a: 3b01 subs r3, #1 8001f9c: 6053 str r3, [r2, #4] NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ 8001f9e: 210f movs r1, #15 8001fa0: f04f 30ff mov.w r0, #4294967295 8001fa4: f7ff ff90 bl 8001ec8 <__NVIC_SetPriority> SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ 8001fa8: 4b05 ldr r3, [pc, #20] ; (8001fc0 ) 8001faa: 2200 movs r2, #0 8001fac: 609a str r2, [r3, #8] SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 8001fae: 4b04 ldr r3, [pc, #16] ; (8001fc0 ) 8001fb0: 2207 movs r2, #7 8001fb2: 601a str r2, [r3, #0] SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ 8001fb4: 2300 movs r3, #0 } 8001fb6: 4618 mov r0, r3 8001fb8: 3708 adds r7, #8 8001fba: 46bd mov sp, r7 8001fbc: bd80 pop {r7, pc} 8001fbe: bf00 nop 8001fc0: e000e010 .word 0xe000e010 08001fc4 : * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. * The pending IRQ priority will be managed only by the subpriority. * @retval None */ void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 8001fc4: b580 push {r7, lr} 8001fc6: b082 sub sp, #8 8001fc8: af00 add r7, sp, #0 8001fca: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ NVIC_SetPriorityGrouping(PriorityGroup); 8001fcc: 6878 ldr r0, [r7, #4] 8001fce: f7ff ff49 bl 8001e64 <__NVIC_SetPriorityGrouping> } 8001fd2: bf00 nop 8001fd4: 3708 adds r7, #8 8001fd6: 46bd mov sp, r7 8001fd8: bd80 pop {r7, pc} 08001fda : * This parameter can be a value between 0 and 15 * A lower priority value indicates a higher priority. * @retval None */ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) { 8001fda: b580 push {r7, lr} 8001fdc: b086 sub sp, #24 8001fde: af00 add r7, sp, #0 8001fe0: 4603 mov r3, r0 8001fe2: 60b9 str r1, [r7, #8] 8001fe4: 607a str r2, [r7, #4] 8001fe6: 73fb strb r3, [r7, #15] uint32_t prioritygroup = 0x00U; 8001fe8: 2300 movs r3, #0 8001fea: 617b str r3, [r7, #20] /* Check the parameters */ assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); prioritygroup = NVIC_GetPriorityGrouping(); 8001fec: f7ff ff5e bl 8001eac <__NVIC_GetPriorityGrouping> 8001ff0: 6178 str r0, [r7, #20] NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); 8001ff2: 687a ldr r2, [r7, #4] 8001ff4: 68b9 ldr r1, [r7, #8] 8001ff6: 6978 ldr r0, [r7, #20] 8001ff8: f7ff ff90 bl 8001f1c 8001ffc: 4602 mov r2, r0 8001ffe: f997 300f ldrsb.w r3, [r7, #15] 8002002: 4611 mov r1, r2 8002004: 4618 mov r0, r3 8002006: f7ff ff5f bl 8001ec8 <__NVIC_SetPriority> } 800200a: bf00 nop 800200c: 3718 adds r7, #24 800200e: 46bd mov sp, r7 8002010: bd80 pop {r7, pc} 08002012 : * @param TicksNumb: Specifies the ticks Number of ticks between two interrupts. * @retval status: - 0 Function succeeded. * - 1 Function failed. */ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) { 8002012: b580 push {r7, lr} 8002014: b082 sub sp, #8 8002016: af00 add r7, sp, #0 8002018: 6078 str r0, [r7, #4] return SysTick_Config(TicksNumb); 800201a: 6878 ldr r0, [r7, #4] 800201c: f7ff ffb0 bl 8001f80 8002020: 4603 mov r3, r0 } 8002022: 4618 mov r0, r3 8002024: 3708 adds r7, #8 8002026: 46bd mov sp, r7 8002028: bd80 pop {r7, pc} ... 0800202c : * @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains * the configuration information for the specified GPIO peripheral. * @retval None */ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) { 800202c: b480 push {r7} 800202e: b08b sub sp, #44 ; 0x2c 8002030: af00 add r7, sp, #0 8002032: 6078 str r0, [r7, #4] 8002034: 6039 str r1, [r7, #0] uint32_t position = 0x00u; 8002036: 2300 movs r3, #0 8002038: 627b str r3, [r7, #36] ; 0x24 uint32_t ioposition; uint32_t iocurrent; uint32_t temp; uint32_t config = 0x00u; 800203a: 2300 movs r3, #0 800203c: 623b str r3, [r7, #32] assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); /* Configure the port pins */ while (((GPIO_Init->Pin) >> position) != 0x00u) 800203e: e169 b.n 8002314 { /* Get the IO position */ ioposition = (0x01uL << position); 8002040: 2201 movs r2, #1 8002042: 6a7b ldr r3, [r7, #36] ; 0x24 8002044: fa02 f303 lsl.w r3, r2, r3 8002048: 61fb str r3, [r7, #28] /* Get the current IO position */ iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition; 800204a: 683b ldr r3, [r7, #0] 800204c: 681b ldr r3, [r3, #0] 800204e: 69fa ldr r2, [r7, #28] 8002050: 4013 ands r3, r2 8002052: 61bb str r3, [r7, #24] if (iocurrent == ioposition) 8002054: 69ba ldr r2, [r7, #24] 8002056: 69fb ldr r3, [r7, #28] 8002058: 429a cmp r2, r3 800205a: f040 8158 bne.w 800230e { /* Check the Alternate function parameters */ assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); /* Based on the required mode, filling config variable with MODEy[1:0] and CNFy[3:2] corresponding bits */ switch (GPIO_Init->Mode) 800205e: 683b ldr r3, [r7, #0] 8002060: 685b ldr r3, [r3, #4] 8002062: 4a9a ldr r2, [pc, #616] ; (80022cc ) 8002064: 4293 cmp r3, r2 8002066: d05e beq.n 8002126 8002068: 4a98 ldr r2, [pc, #608] ; (80022cc ) 800206a: 4293 cmp r3, r2 800206c: d875 bhi.n 800215a 800206e: 4a98 ldr r2, [pc, #608] ; (80022d0 ) 8002070: 4293 cmp r3, r2 8002072: d058 beq.n 8002126 8002074: 4a96 ldr r2, [pc, #600] ; (80022d0 ) 8002076: 4293 cmp r3, r2 8002078: d86f bhi.n 800215a 800207a: 4a96 ldr r2, [pc, #600] ; (80022d4 ) 800207c: 4293 cmp r3, r2 800207e: d052 beq.n 8002126 8002080: 4a94 ldr r2, [pc, #592] ; (80022d4 ) 8002082: 4293 cmp r3, r2 8002084: d869 bhi.n 800215a 8002086: 4a94 ldr r2, [pc, #592] ; (80022d8 ) 8002088: 4293 cmp r3, r2 800208a: d04c beq.n 8002126 800208c: 4a92 ldr r2, [pc, #584] ; (80022d8 ) 800208e: 4293 cmp r3, r2 8002090: d863 bhi.n 800215a 8002092: 4a92 ldr r2, [pc, #584] ; (80022dc ) 8002094: 4293 cmp r3, r2 8002096: d046 beq.n 8002126 8002098: 4a90 ldr r2, [pc, #576] ; (80022dc ) 800209a: 4293 cmp r3, r2 800209c: d85d bhi.n 800215a 800209e: 2b12 cmp r3, #18 80020a0: d82a bhi.n 80020f8 80020a2: 2b12 cmp r3, #18 80020a4: d859 bhi.n 800215a 80020a6: a201 add r2, pc, #4 ; (adr r2, 80020ac ) 80020a8: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80020ac: 08002127 .word 0x08002127 80020b0: 08002101 .word 0x08002101 80020b4: 08002113 .word 0x08002113 80020b8: 08002155 .word 0x08002155 80020bc: 0800215b .word 0x0800215b 80020c0: 0800215b .word 0x0800215b 80020c4: 0800215b .word 0x0800215b 80020c8: 0800215b .word 0x0800215b 80020cc: 0800215b .word 0x0800215b 80020d0: 0800215b .word 0x0800215b 80020d4: 0800215b .word 0x0800215b 80020d8: 0800215b .word 0x0800215b 80020dc: 0800215b .word 0x0800215b 80020e0: 0800215b .word 0x0800215b 80020e4: 0800215b .word 0x0800215b 80020e8: 0800215b .word 0x0800215b 80020ec: 0800215b .word 0x0800215b 80020f0: 08002109 .word 0x08002109 80020f4: 0800211d .word 0x0800211d 80020f8: 4a79 ldr r2, [pc, #484] ; (80022e0 ) 80020fa: 4293 cmp r3, r2 80020fc: d013 beq.n 8002126 config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG; break; /* Parameters are checked with assert_param */ default: break; 80020fe: e02c b.n 800215a config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_PP; 8002100: 683b ldr r3, [r7, #0] 8002102: 68db ldr r3, [r3, #12] 8002104: 623b str r3, [r7, #32] break; 8002106: e029 b.n 800215c config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_OD; 8002108: 683b ldr r3, [r7, #0] 800210a: 68db ldr r3, [r3, #12] 800210c: 3304 adds r3, #4 800210e: 623b str r3, [r7, #32] break; 8002110: e024 b.n 800215c config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_PP; 8002112: 683b ldr r3, [r7, #0] 8002114: 68db ldr r3, [r3, #12] 8002116: 3308 adds r3, #8 8002118: 623b str r3, [r7, #32] break; 800211a: e01f b.n 800215c config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_OD; 800211c: 683b ldr r3, [r7, #0] 800211e: 68db ldr r3, [r3, #12] 8002120: 330c adds r3, #12 8002122: 623b str r3, [r7, #32] break; 8002124: e01a b.n 800215c if (GPIO_Init->Pull == GPIO_NOPULL) 8002126: 683b ldr r3, [r7, #0] 8002128: 689b ldr r3, [r3, #8] 800212a: 2b00 cmp r3, #0 800212c: d102 bne.n 8002134 config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_FLOATING; 800212e: 2304 movs r3, #4 8002130: 623b str r3, [r7, #32] break; 8002132: e013 b.n 800215c else if (GPIO_Init->Pull == GPIO_PULLUP) 8002134: 683b ldr r3, [r7, #0] 8002136: 689b ldr r3, [r3, #8] 8002138: 2b01 cmp r3, #1 800213a: d105 bne.n 8002148 config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD; 800213c: 2308 movs r3, #8 800213e: 623b str r3, [r7, #32] GPIOx->BSRR = ioposition; 8002140: 687b ldr r3, [r7, #4] 8002142: 69fa ldr r2, [r7, #28] 8002144: 611a str r2, [r3, #16] break; 8002146: e009 b.n 800215c config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD; 8002148: 2308 movs r3, #8 800214a: 623b str r3, [r7, #32] GPIOx->BRR = ioposition; 800214c: 687b ldr r3, [r7, #4] 800214e: 69fa ldr r2, [r7, #28] 8002150: 615a str r2, [r3, #20] break; 8002152: e003 b.n 800215c config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG; 8002154: 2300 movs r3, #0 8002156: 623b str r3, [r7, #32] break; 8002158: e000 b.n 800215c break; 800215a: bf00 nop } /* Check if the current bit belongs to first half or last half of the pin count number in order to address CRH or CRL register*/ configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL : &GPIOx->CRH; 800215c: 69bb ldr r3, [r7, #24] 800215e: 2bff cmp r3, #255 ; 0xff 8002160: d801 bhi.n 8002166 8002162: 687b ldr r3, [r7, #4] 8002164: e001 b.n 800216a 8002166: 687b ldr r3, [r7, #4] 8002168: 3304 adds r3, #4 800216a: 617b str r3, [r7, #20] registeroffset = (iocurrent < GPIO_PIN_8) ? (position << 2u) : ((position - 8u) << 2u); 800216c: 69bb ldr r3, [r7, #24] 800216e: 2bff cmp r3, #255 ; 0xff 8002170: d802 bhi.n 8002178 8002172: 6a7b ldr r3, [r7, #36] ; 0x24 8002174: 009b lsls r3, r3, #2 8002176: e002 b.n 800217e 8002178: 6a7b ldr r3, [r7, #36] ; 0x24 800217a: 3b08 subs r3, #8 800217c: 009b lsls r3, r3, #2 800217e: 613b str r3, [r7, #16] /* Apply the new configuration of the pin to the register */ MODIFY_REG((*configregister), ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset), (config << registeroffset)); 8002180: 697b ldr r3, [r7, #20] 8002182: 681a ldr r2, [r3, #0] 8002184: 210f movs r1, #15 8002186: 693b ldr r3, [r7, #16] 8002188: fa01 f303 lsl.w r3, r1, r3 800218c: 43db mvns r3, r3 800218e: 401a ands r2, r3 8002190: 6a39 ldr r1, [r7, #32] 8002192: 693b ldr r3, [r7, #16] 8002194: fa01 f303 lsl.w r3, r1, r3 8002198: 431a orrs r2, r3 800219a: 697b ldr r3, [r7, #20] 800219c: 601a str r2, [r3, #0] /*--------------------- EXTI Mode Configuration ------------------------*/ /* Configure the External Interrupt or event for the current IO */ if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE) 800219e: 683b ldr r3, [r7, #0] 80021a0: 685b ldr r3, [r3, #4] 80021a2: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 80021a6: 2b00 cmp r3, #0 80021a8: f000 80b1 beq.w 800230e { /* Enable AFIO Clock */ __HAL_RCC_AFIO_CLK_ENABLE(); 80021ac: 4b4d ldr r3, [pc, #308] ; (80022e4 ) 80021ae: 699b ldr r3, [r3, #24] 80021b0: 4a4c ldr r2, [pc, #304] ; (80022e4 ) 80021b2: f043 0301 orr.w r3, r3, #1 80021b6: 6193 str r3, [r2, #24] 80021b8: 4b4a ldr r3, [pc, #296] ; (80022e4 ) 80021ba: 699b ldr r3, [r3, #24] 80021bc: f003 0301 and.w r3, r3, #1 80021c0: 60bb str r3, [r7, #8] 80021c2: 68bb ldr r3, [r7, #8] temp = AFIO->EXTICR[position >> 2u]; 80021c4: 4a48 ldr r2, [pc, #288] ; (80022e8 ) 80021c6: 6a7b ldr r3, [r7, #36] ; 0x24 80021c8: 089b lsrs r3, r3, #2 80021ca: 3302 adds r3, #2 80021cc: f852 3023 ldr.w r3, [r2, r3, lsl #2] 80021d0: 60fb str r3, [r7, #12] CLEAR_BIT(temp, (0x0Fu) << (4u * (position & 0x03u))); 80021d2: 6a7b ldr r3, [r7, #36] ; 0x24 80021d4: f003 0303 and.w r3, r3, #3 80021d8: 009b lsls r3, r3, #2 80021da: 220f movs r2, #15 80021dc: fa02 f303 lsl.w r3, r2, r3 80021e0: 43db mvns r3, r3 80021e2: 68fa ldr r2, [r7, #12] 80021e4: 4013 ands r3, r2 80021e6: 60fb str r3, [r7, #12] SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4u * (position & 0x03u))); 80021e8: 687b ldr r3, [r7, #4] 80021ea: 4a40 ldr r2, [pc, #256] ; (80022ec ) 80021ec: 4293 cmp r3, r2 80021ee: d013 beq.n 8002218 80021f0: 687b ldr r3, [r7, #4] 80021f2: 4a3f ldr r2, [pc, #252] ; (80022f0 ) 80021f4: 4293 cmp r3, r2 80021f6: d00d beq.n 8002214 80021f8: 687b ldr r3, [r7, #4] 80021fa: 4a3e ldr r2, [pc, #248] ; (80022f4 ) 80021fc: 4293 cmp r3, r2 80021fe: d007 beq.n 8002210 8002200: 687b ldr r3, [r7, #4] 8002202: 4a3d ldr r2, [pc, #244] ; (80022f8 ) 8002204: 4293 cmp r3, r2 8002206: d101 bne.n 800220c 8002208: 2303 movs r3, #3 800220a: e006 b.n 800221a 800220c: 2304 movs r3, #4 800220e: e004 b.n 800221a 8002210: 2302 movs r3, #2 8002212: e002 b.n 800221a 8002214: 2301 movs r3, #1 8002216: e000 b.n 800221a 8002218: 2300 movs r3, #0 800221a: 6a7a ldr r2, [r7, #36] ; 0x24 800221c: f002 0203 and.w r2, r2, #3 8002220: 0092 lsls r2, r2, #2 8002222: 4093 lsls r3, r2 8002224: 68fa ldr r2, [r7, #12] 8002226: 4313 orrs r3, r2 8002228: 60fb str r3, [r7, #12] AFIO->EXTICR[position >> 2u] = temp; 800222a: 492f ldr r1, [pc, #188] ; (80022e8 ) 800222c: 6a7b ldr r3, [r7, #36] ; 0x24 800222e: 089b lsrs r3, r3, #2 8002230: 3302 adds r3, #2 8002232: 68fa ldr r2, [r7, #12] 8002234: f841 2023 str.w r2, [r1, r3, lsl #2] /* Configure the interrupt mask */ if ((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT) 8002238: 683b ldr r3, [r7, #0] 800223a: 685b ldr r3, [r3, #4] 800223c: f403 3380 and.w r3, r3, #65536 ; 0x10000 8002240: 2b00 cmp r3, #0 8002242: d006 beq.n 8002252 { SET_BIT(EXTI->IMR, iocurrent); 8002244: 4b2d ldr r3, [pc, #180] ; (80022fc ) 8002246: 681a ldr r2, [r3, #0] 8002248: 492c ldr r1, [pc, #176] ; (80022fc ) 800224a: 69bb ldr r3, [r7, #24] 800224c: 4313 orrs r3, r2 800224e: 600b str r3, [r1, #0] 8002250: e006 b.n 8002260 } else { CLEAR_BIT(EXTI->IMR, iocurrent); 8002252: 4b2a ldr r3, [pc, #168] ; (80022fc ) 8002254: 681a ldr r2, [r3, #0] 8002256: 69bb ldr r3, [r7, #24] 8002258: 43db mvns r3, r3 800225a: 4928 ldr r1, [pc, #160] ; (80022fc ) 800225c: 4013 ands r3, r2 800225e: 600b str r3, [r1, #0] } /* Configure the event mask */ if ((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT) 8002260: 683b ldr r3, [r7, #0] 8002262: 685b ldr r3, [r3, #4] 8002264: f403 3300 and.w r3, r3, #131072 ; 0x20000 8002268: 2b00 cmp r3, #0 800226a: d006 beq.n 800227a { SET_BIT(EXTI->EMR, iocurrent); 800226c: 4b23 ldr r3, [pc, #140] ; (80022fc ) 800226e: 685a ldr r2, [r3, #4] 8002270: 4922 ldr r1, [pc, #136] ; (80022fc ) 8002272: 69bb ldr r3, [r7, #24] 8002274: 4313 orrs r3, r2 8002276: 604b str r3, [r1, #4] 8002278: e006 b.n 8002288 } else { CLEAR_BIT(EXTI->EMR, iocurrent); 800227a: 4b20 ldr r3, [pc, #128] ; (80022fc ) 800227c: 685a ldr r2, [r3, #4] 800227e: 69bb ldr r3, [r7, #24] 8002280: 43db mvns r3, r3 8002282: 491e ldr r1, [pc, #120] ; (80022fc ) 8002284: 4013 ands r3, r2 8002286: 604b str r3, [r1, #4] } /* Enable or disable the rising trigger */ if ((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE) 8002288: 683b ldr r3, [r7, #0] 800228a: 685b ldr r3, [r3, #4] 800228c: f403 1380 and.w r3, r3, #1048576 ; 0x100000 8002290: 2b00 cmp r3, #0 8002292: d006 beq.n 80022a2 { SET_BIT(EXTI->RTSR, iocurrent); 8002294: 4b19 ldr r3, [pc, #100] ; (80022fc ) 8002296: 689a ldr r2, [r3, #8] 8002298: 4918 ldr r1, [pc, #96] ; (80022fc ) 800229a: 69bb ldr r3, [r7, #24] 800229c: 4313 orrs r3, r2 800229e: 608b str r3, [r1, #8] 80022a0: e006 b.n 80022b0 } else { CLEAR_BIT(EXTI->RTSR, iocurrent); 80022a2: 4b16 ldr r3, [pc, #88] ; (80022fc ) 80022a4: 689a ldr r2, [r3, #8] 80022a6: 69bb ldr r3, [r7, #24] 80022a8: 43db mvns r3, r3 80022aa: 4914 ldr r1, [pc, #80] ; (80022fc ) 80022ac: 4013 ands r3, r2 80022ae: 608b str r3, [r1, #8] } /* Enable or disable the falling trigger */ if ((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE) 80022b0: 683b ldr r3, [r7, #0] 80022b2: 685b ldr r3, [r3, #4] 80022b4: f403 1300 and.w r3, r3, #2097152 ; 0x200000 80022b8: 2b00 cmp r3, #0 80022ba: d021 beq.n 8002300 { SET_BIT(EXTI->FTSR, iocurrent); 80022bc: 4b0f ldr r3, [pc, #60] ; (80022fc ) 80022be: 68da ldr r2, [r3, #12] 80022c0: 490e ldr r1, [pc, #56] ; (80022fc ) 80022c2: 69bb ldr r3, [r7, #24] 80022c4: 4313 orrs r3, r2 80022c6: 60cb str r3, [r1, #12] 80022c8: e021 b.n 800230e 80022ca: bf00 nop 80022cc: 10320000 .word 0x10320000 80022d0: 10310000 .word 0x10310000 80022d4: 10220000 .word 0x10220000 80022d8: 10210000 .word 0x10210000 80022dc: 10120000 .word 0x10120000 80022e0: 10110000 .word 0x10110000 80022e4: 40021000 .word 0x40021000 80022e8: 40010000 .word 0x40010000 80022ec: 40010800 .word 0x40010800 80022f0: 40010c00 .word 0x40010c00 80022f4: 40011000 .word 0x40011000 80022f8: 40011400 .word 0x40011400 80022fc: 40010400 .word 0x40010400 } else { CLEAR_BIT(EXTI->FTSR, iocurrent); 8002300: 4b0b ldr r3, [pc, #44] ; (8002330 ) 8002302: 68da ldr r2, [r3, #12] 8002304: 69bb ldr r3, [r7, #24] 8002306: 43db mvns r3, r3 8002308: 4909 ldr r1, [pc, #36] ; (8002330 ) 800230a: 4013 ands r3, r2 800230c: 60cb str r3, [r1, #12] } } } position++; 800230e: 6a7b ldr r3, [r7, #36] ; 0x24 8002310: 3301 adds r3, #1 8002312: 627b str r3, [r7, #36] ; 0x24 while (((GPIO_Init->Pin) >> position) != 0x00u) 8002314: 683b ldr r3, [r7, #0] 8002316: 681a ldr r2, [r3, #0] 8002318: 6a7b ldr r3, [r7, #36] ; 0x24 800231a: fa22 f303 lsr.w r3, r2, r3 800231e: 2b00 cmp r3, #0 8002320: f47f ae8e bne.w 8002040 } } 8002324: bf00 nop 8002326: bf00 nop 8002328: 372c adds r7, #44 ; 0x2c 800232a: 46bd mov sp, r7 800232c: bc80 pop {r7} 800232e: 4770 bx lr 8002330: 40010400 .word 0x40010400 08002334 : * supported by this macro. User should request a transition to HSE Off * first and then HSE On or HSE Bypass. * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { 8002334: b580 push {r7, lr} 8002336: b086 sub sp, #24 8002338: af00 add r7, sp, #0 800233a: 6078 str r0, [r7, #4] uint32_t tickstart; uint32_t pll_config; /* Check Null pointer */ if (RCC_OscInitStruct == NULL) 800233c: 687b ldr r3, [r7, #4] 800233e: 2b00 cmp r3, #0 8002340: d101 bne.n 8002346 { return HAL_ERROR; 8002342: 2301 movs r3, #1 8002344: e272 b.n 800282c /* Check the parameters */ assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); /*------------------------------- HSE Configuration ------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) 8002346: 687b ldr r3, [r7, #4] 8002348: 681b ldr r3, [r3, #0] 800234a: f003 0301 and.w r3, r3, #1 800234e: 2b00 cmp r3, #0 8002350: f000 8087 beq.w 8002462 { /* Check the parameters */ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */ if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE) 8002354: 4b92 ldr r3, [pc, #584] ; (80025a0 ) 8002356: 685b ldr r3, [r3, #4] 8002358: f003 030c and.w r3, r3, #12 800235c: 2b04 cmp r3, #4 800235e: d00c beq.n 800237a || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE))) 8002360: 4b8f ldr r3, [pc, #572] ; (80025a0 ) 8002362: 685b ldr r3, [r3, #4] 8002364: f003 030c and.w r3, r3, #12 8002368: 2b08 cmp r3, #8 800236a: d112 bne.n 8002392 800236c: 4b8c ldr r3, [pc, #560] ; (80025a0 ) 800236e: 685b ldr r3, [r3, #4] 8002370: f403 3380 and.w r3, r3, #65536 ; 0x10000 8002374: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 8002378: d10b bne.n 8002392 { if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 800237a: 4b89 ldr r3, [pc, #548] ; (80025a0 ) 800237c: 681b ldr r3, [r3, #0] 800237e: f403 3300 and.w r3, r3, #131072 ; 0x20000 8002382: 2b00 cmp r3, #0 8002384: d06c beq.n 8002460 8002386: 687b ldr r3, [r7, #4] 8002388: 685b ldr r3, [r3, #4] 800238a: 2b00 cmp r3, #0 800238c: d168 bne.n 8002460 { return HAL_ERROR; 800238e: 2301 movs r3, #1 8002390: e24c b.n 800282c } } else { /* Set the new HSE configuration ---------------------------------------*/ __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); 8002392: 687b ldr r3, [r7, #4] 8002394: 685b ldr r3, [r3, #4] 8002396: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 800239a: d106 bne.n 80023aa 800239c: 4b80 ldr r3, [pc, #512] ; (80025a0 ) 800239e: 681b ldr r3, [r3, #0] 80023a0: 4a7f ldr r2, [pc, #508] ; (80025a0 ) 80023a2: f443 3380 orr.w r3, r3, #65536 ; 0x10000 80023a6: 6013 str r3, [r2, #0] 80023a8: e02e b.n 8002408 80023aa: 687b ldr r3, [r7, #4] 80023ac: 685b ldr r3, [r3, #4] 80023ae: 2b00 cmp r3, #0 80023b0: d10c bne.n 80023cc 80023b2: 4b7b ldr r3, [pc, #492] ; (80025a0 ) 80023b4: 681b ldr r3, [r3, #0] 80023b6: 4a7a ldr r2, [pc, #488] ; (80025a0 ) 80023b8: f423 3380 bic.w r3, r3, #65536 ; 0x10000 80023bc: 6013 str r3, [r2, #0] 80023be: 4b78 ldr r3, [pc, #480] ; (80025a0 ) 80023c0: 681b ldr r3, [r3, #0] 80023c2: 4a77 ldr r2, [pc, #476] ; (80025a0 ) 80023c4: f423 2380 bic.w r3, r3, #262144 ; 0x40000 80023c8: 6013 str r3, [r2, #0] 80023ca: e01d b.n 8002408 80023cc: 687b ldr r3, [r7, #4] 80023ce: 685b ldr r3, [r3, #4] 80023d0: f5b3 2fa0 cmp.w r3, #327680 ; 0x50000 80023d4: d10c bne.n 80023f0 80023d6: 4b72 ldr r3, [pc, #456] ; (80025a0 ) 80023d8: 681b ldr r3, [r3, #0] 80023da: 4a71 ldr r2, [pc, #452] ; (80025a0 ) 80023dc: f443 2380 orr.w r3, r3, #262144 ; 0x40000 80023e0: 6013 str r3, [r2, #0] 80023e2: 4b6f ldr r3, [pc, #444] ; (80025a0 ) 80023e4: 681b ldr r3, [r3, #0] 80023e6: 4a6e ldr r2, [pc, #440] ; (80025a0 ) 80023e8: f443 3380 orr.w r3, r3, #65536 ; 0x10000 80023ec: 6013 str r3, [r2, #0] 80023ee: e00b b.n 8002408 80023f0: 4b6b ldr r3, [pc, #428] ; (80025a0 ) 80023f2: 681b ldr r3, [r3, #0] 80023f4: 4a6a ldr r2, [pc, #424] ; (80025a0 ) 80023f6: f423 3380 bic.w r3, r3, #65536 ; 0x10000 80023fa: 6013 str r3, [r2, #0] 80023fc: 4b68 ldr r3, [pc, #416] ; (80025a0 ) 80023fe: 681b ldr r3, [r3, #0] 8002400: 4a67 ldr r2, [pc, #412] ; (80025a0 ) 8002402: f423 2380 bic.w r3, r3, #262144 ; 0x40000 8002406: 6013 str r3, [r2, #0] /* Check the HSE State */ if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF) 8002408: 687b ldr r3, [r7, #4] 800240a: 685b ldr r3, [r3, #4] 800240c: 2b00 cmp r3, #0 800240e: d013 beq.n 8002438 { /* Get Start Tick */ tickstart = HAL_GetTick(); 8002410: f7ff f9d4 bl 80017bc 8002414: 6138 str r0, [r7, #16] /* Wait till HSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 8002416: e008 b.n 800242a { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 8002418: f7ff f9d0 bl 80017bc 800241c: 4602 mov r2, r0 800241e: 693b ldr r3, [r7, #16] 8002420: 1ad3 subs r3, r2, r3 8002422: 2b64 cmp r3, #100 ; 0x64 8002424: d901 bls.n 800242a { return HAL_TIMEOUT; 8002426: 2303 movs r3, #3 8002428: e200 b.n 800282c while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 800242a: 4b5d ldr r3, [pc, #372] ; (80025a0 ) 800242c: 681b ldr r3, [r3, #0] 800242e: f403 3300 and.w r3, r3, #131072 ; 0x20000 8002432: 2b00 cmp r3, #0 8002434: d0f0 beq.n 8002418 8002436: e014 b.n 8002462 } } else { /* Get Start Tick */ tickstart = HAL_GetTick(); 8002438: f7ff f9c0 bl 80017bc 800243c: 6138 str r0, [r7, #16] /* Wait till HSE is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) 800243e: e008 b.n 8002452 { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 8002440: f7ff f9bc bl 80017bc 8002444: 4602 mov r2, r0 8002446: 693b ldr r3, [r7, #16] 8002448: 1ad3 subs r3, r2, r3 800244a: 2b64 cmp r3, #100 ; 0x64 800244c: d901 bls.n 8002452 { return HAL_TIMEOUT; 800244e: 2303 movs r3, #3 8002450: e1ec b.n 800282c while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) 8002452: 4b53 ldr r3, [pc, #332] ; (80025a0 ) 8002454: 681b ldr r3, [r3, #0] 8002456: f403 3300 and.w r3, r3, #131072 ; 0x20000 800245a: 2b00 cmp r3, #0 800245c: d1f0 bne.n 8002440 800245e: e000 b.n 8002462 if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 8002460: bf00 nop } } } } /*----------------------------- HSI Configuration --------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) 8002462: 687b ldr r3, [r7, #4] 8002464: 681b ldr r3, [r3, #0] 8002466: f003 0302 and.w r3, r3, #2 800246a: 2b00 cmp r3, #0 800246c: d063 beq.n 8002536 /* Check the parameters */ assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI) 800246e: 4b4c ldr r3, [pc, #304] ; (80025a0 ) 8002470: 685b ldr r3, [r3, #4] 8002472: f003 030c and.w r3, r3, #12 8002476: 2b00 cmp r3, #0 8002478: d00b beq.n 8002492 || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI_DIV2))) 800247a: 4b49 ldr r3, [pc, #292] ; (80025a0 ) 800247c: 685b ldr r3, [r3, #4] 800247e: f003 030c and.w r3, r3, #12 8002482: 2b08 cmp r3, #8 8002484: d11c bne.n 80024c0 8002486: 4b46 ldr r3, [pc, #280] ; (80025a0 ) 8002488: 685b ldr r3, [r3, #4] 800248a: f403 3380 and.w r3, r3, #65536 ; 0x10000 800248e: 2b00 cmp r3, #0 8002490: d116 bne.n 80024c0 { /* When HSI is used as system clock it will not disabled */ if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) 8002492: 4b43 ldr r3, [pc, #268] ; (80025a0 ) 8002494: 681b ldr r3, [r3, #0] 8002496: f003 0302 and.w r3, r3, #2 800249a: 2b00 cmp r3, #0 800249c: d005 beq.n 80024aa 800249e: 687b ldr r3, [r7, #4] 80024a0: 691b ldr r3, [r3, #16] 80024a2: 2b01 cmp r3, #1 80024a4: d001 beq.n 80024aa { return HAL_ERROR; 80024a6: 2301 movs r3, #1 80024a8: e1c0 b.n 800282c } /* Otherwise, just the calibration is allowed */ else { /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 80024aa: 4b3d ldr r3, [pc, #244] ; (80025a0 ) 80024ac: 681b ldr r3, [r3, #0] 80024ae: f023 02f8 bic.w r2, r3, #248 ; 0xf8 80024b2: 687b ldr r3, [r7, #4] 80024b4: 695b ldr r3, [r3, #20] 80024b6: 00db lsls r3, r3, #3 80024b8: 4939 ldr r1, [pc, #228] ; (80025a0 ) 80024ba: 4313 orrs r3, r2 80024bc: 600b str r3, [r1, #0] if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) 80024be: e03a b.n 8002536 } } else { /* Check the HSI State */ if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF) 80024c0: 687b ldr r3, [r7, #4] 80024c2: 691b ldr r3, [r3, #16] 80024c4: 2b00 cmp r3, #0 80024c6: d020 beq.n 800250a { /* Enable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_ENABLE(); 80024c8: 4b36 ldr r3, [pc, #216] ; (80025a4 ) 80024ca: 2201 movs r2, #1 80024cc: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 80024ce: f7ff f975 bl 80017bc 80024d2: 6138 str r0, [r7, #16] /* Wait till HSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 80024d4: e008 b.n 80024e8 { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 80024d6: f7ff f971 bl 80017bc 80024da: 4602 mov r2, r0 80024dc: 693b ldr r3, [r7, #16] 80024de: 1ad3 subs r3, r2, r3 80024e0: 2b02 cmp r3, #2 80024e2: d901 bls.n 80024e8 { return HAL_TIMEOUT; 80024e4: 2303 movs r3, #3 80024e6: e1a1 b.n 800282c while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 80024e8: 4b2d ldr r3, [pc, #180] ; (80025a0 ) 80024ea: 681b ldr r3, [r3, #0] 80024ec: f003 0302 and.w r3, r3, #2 80024f0: 2b00 cmp r3, #0 80024f2: d0f0 beq.n 80024d6 } } /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 80024f4: 4b2a ldr r3, [pc, #168] ; (80025a0 ) 80024f6: 681b ldr r3, [r3, #0] 80024f8: f023 02f8 bic.w r2, r3, #248 ; 0xf8 80024fc: 687b ldr r3, [r7, #4] 80024fe: 695b ldr r3, [r3, #20] 8002500: 00db lsls r3, r3, #3 8002502: 4927 ldr r1, [pc, #156] ; (80025a0 ) 8002504: 4313 orrs r3, r2 8002506: 600b str r3, [r1, #0] 8002508: e015 b.n 8002536 } else { /* Disable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_DISABLE(); 800250a: 4b26 ldr r3, [pc, #152] ; (80025a4 ) 800250c: 2200 movs r2, #0 800250e: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8002510: f7ff f954 bl 80017bc 8002514: 6138 str r0, [r7, #16] /* Wait till HSI is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) 8002516: e008 b.n 800252a { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 8002518: f7ff f950 bl 80017bc 800251c: 4602 mov r2, r0 800251e: 693b ldr r3, [r7, #16] 8002520: 1ad3 subs r3, r2, r3 8002522: 2b02 cmp r3, #2 8002524: d901 bls.n 800252a { return HAL_TIMEOUT; 8002526: 2303 movs r3, #3 8002528: e180 b.n 800282c while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) 800252a: 4b1d ldr r3, [pc, #116] ; (80025a0 ) 800252c: 681b ldr r3, [r3, #0] 800252e: f003 0302 and.w r3, r3, #2 8002532: 2b00 cmp r3, #0 8002534: d1f0 bne.n 8002518 } } } } /*------------------------------ LSI Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) 8002536: 687b ldr r3, [r7, #4] 8002538: 681b ldr r3, [r3, #0] 800253a: f003 0308 and.w r3, r3, #8 800253e: 2b00 cmp r3, #0 8002540: d03a beq.n 80025b8 { /* Check the parameters */ assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); /* Check the LSI State */ if (RCC_OscInitStruct->LSIState != RCC_LSI_OFF) 8002542: 687b ldr r3, [r7, #4] 8002544: 699b ldr r3, [r3, #24] 8002546: 2b00 cmp r3, #0 8002548: d019 beq.n 800257e { /* Enable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_ENABLE(); 800254a: 4b17 ldr r3, [pc, #92] ; (80025a8 ) 800254c: 2201 movs r2, #1 800254e: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8002550: f7ff f934 bl 80017bc 8002554: 6138 str r0, [r7, #16] /* Wait till LSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) 8002556: e008 b.n 800256a { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 8002558: f7ff f930 bl 80017bc 800255c: 4602 mov r2, r0 800255e: 693b ldr r3, [r7, #16] 8002560: 1ad3 subs r3, r2, r3 8002562: 2b02 cmp r3, #2 8002564: d901 bls.n 800256a { return HAL_TIMEOUT; 8002566: 2303 movs r3, #3 8002568: e160 b.n 800282c while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) 800256a: 4b0d ldr r3, [pc, #52] ; (80025a0 ) 800256c: 6a5b ldr r3, [r3, #36] ; 0x24 800256e: f003 0302 and.w r3, r3, #2 8002572: 2b00 cmp r3, #0 8002574: d0f0 beq.n 8002558 } } /* To have a fully stabilized clock in the specified range, a software delay of 1ms should be added.*/ RCC_Delay(1); 8002576: 2001 movs r0, #1 8002578: f000 fad8 bl 8002b2c 800257c: e01c b.n 80025b8 } else { /* Disable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_DISABLE(); 800257e: 4b0a ldr r3, [pc, #40] ; (80025a8 ) 8002580: 2200 movs r2, #0 8002582: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8002584: f7ff f91a bl 80017bc 8002588: 6138 str r0, [r7, #16] /* Wait till LSI is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) 800258a: e00f b.n 80025ac { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 800258c: f7ff f916 bl 80017bc 8002590: 4602 mov r2, r0 8002592: 693b ldr r3, [r7, #16] 8002594: 1ad3 subs r3, r2, r3 8002596: 2b02 cmp r3, #2 8002598: d908 bls.n 80025ac { return HAL_TIMEOUT; 800259a: 2303 movs r3, #3 800259c: e146 b.n 800282c 800259e: bf00 nop 80025a0: 40021000 .word 0x40021000 80025a4: 42420000 .word 0x42420000 80025a8: 42420480 .word 0x42420480 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) 80025ac: 4b92 ldr r3, [pc, #584] ; (80027f8 ) 80025ae: 6a5b ldr r3, [r3, #36] ; 0x24 80025b0: f003 0302 and.w r3, r3, #2 80025b4: 2b00 cmp r3, #0 80025b6: d1e9 bne.n 800258c } } } } /*------------------------------ LSE Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) 80025b8: 687b ldr r3, [r7, #4] 80025ba: 681b ldr r3, [r3, #0] 80025bc: f003 0304 and.w r3, r3, #4 80025c0: 2b00 cmp r3, #0 80025c2: f000 80a6 beq.w 8002712 { FlagStatus pwrclkchanged = RESET; 80025c6: 2300 movs r3, #0 80025c8: 75fb strb r3, [r7, #23] /* Check the parameters */ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); /* Update LSE configuration in Backup Domain control register */ /* Requires to enable write access to Backup Domain of necessary */ if (__HAL_RCC_PWR_IS_CLK_DISABLED()) 80025ca: 4b8b ldr r3, [pc, #556] ; (80027f8 ) 80025cc: 69db ldr r3, [r3, #28] 80025ce: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 80025d2: 2b00 cmp r3, #0 80025d4: d10d bne.n 80025f2 { __HAL_RCC_PWR_CLK_ENABLE(); 80025d6: 4b88 ldr r3, [pc, #544] ; (80027f8 ) 80025d8: 69db ldr r3, [r3, #28] 80025da: 4a87 ldr r2, [pc, #540] ; (80027f8 ) 80025dc: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 80025e0: 61d3 str r3, [r2, #28] 80025e2: 4b85 ldr r3, [pc, #532] ; (80027f8 ) 80025e4: 69db ldr r3, [r3, #28] 80025e6: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 80025ea: 60bb str r3, [r7, #8] 80025ec: 68bb ldr r3, [r7, #8] pwrclkchanged = SET; 80025ee: 2301 movs r3, #1 80025f0: 75fb strb r3, [r7, #23] } if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 80025f2: 4b82 ldr r3, [pc, #520] ; (80027fc ) 80025f4: 681b ldr r3, [r3, #0] 80025f6: f403 7380 and.w r3, r3, #256 ; 0x100 80025fa: 2b00 cmp r3, #0 80025fc: d118 bne.n 8002630 { /* Enable write access to Backup domain */ SET_BIT(PWR->CR, PWR_CR_DBP); 80025fe: 4b7f ldr r3, [pc, #508] ; (80027fc ) 8002600: 681b ldr r3, [r3, #0] 8002602: 4a7e ldr r2, [pc, #504] ; (80027fc ) 8002604: f443 7380 orr.w r3, r3, #256 ; 0x100 8002608: 6013 str r3, [r2, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 800260a: f7ff f8d7 bl 80017bc 800260e: 6138 str r0, [r7, #16] while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8002610: e008 b.n 8002624 { if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 8002612: f7ff f8d3 bl 80017bc 8002616: 4602 mov r2, r0 8002618: 693b ldr r3, [r7, #16] 800261a: 1ad3 subs r3, r2, r3 800261c: 2b64 cmp r3, #100 ; 0x64 800261e: d901 bls.n 8002624 { return HAL_TIMEOUT; 8002620: 2303 movs r3, #3 8002622: e103 b.n 800282c while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8002624: 4b75 ldr r3, [pc, #468] ; (80027fc ) 8002626: 681b ldr r3, [r3, #0] 8002628: f403 7380 and.w r3, r3, #256 ; 0x100 800262c: 2b00 cmp r3, #0 800262e: d0f0 beq.n 8002612 } } } /* Set the new LSE configuration -----------------------------------------*/ __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); 8002630: 687b ldr r3, [r7, #4] 8002632: 68db ldr r3, [r3, #12] 8002634: 2b01 cmp r3, #1 8002636: d106 bne.n 8002646 8002638: 4b6f ldr r3, [pc, #444] ; (80027f8 ) 800263a: 6a1b ldr r3, [r3, #32] 800263c: 4a6e ldr r2, [pc, #440] ; (80027f8 ) 800263e: f043 0301 orr.w r3, r3, #1 8002642: 6213 str r3, [r2, #32] 8002644: e02d b.n 80026a2 8002646: 687b ldr r3, [r7, #4] 8002648: 68db ldr r3, [r3, #12] 800264a: 2b00 cmp r3, #0 800264c: d10c bne.n 8002668 800264e: 4b6a ldr r3, [pc, #424] ; (80027f8 ) 8002650: 6a1b ldr r3, [r3, #32] 8002652: 4a69 ldr r2, [pc, #420] ; (80027f8 ) 8002654: f023 0301 bic.w r3, r3, #1 8002658: 6213 str r3, [r2, #32] 800265a: 4b67 ldr r3, [pc, #412] ; (80027f8 ) 800265c: 6a1b ldr r3, [r3, #32] 800265e: 4a66 ldr r2, [pc, #408] ; (80027f8 ) 8002660: f023 0304 bic.w r3, r3, #4 8002664: 6213 str r3, [r2, #32] 8002666: e01c b.n 80026a2 8002668: 687b ldr r3, [r7, #4] 800266a: 68db ldr r3, [r3, #12] 800266c: 2b05 cmp r3, #5 800266e: d10c bne.n 800268a 8002670: 4b61 ldr r3, [pc, #388] ; (80027f8 ) 8002672: 6a1b ldr r3, [r3, #32] 8002674: 4a60 ldr r2, [pc, #384] ; (80027f8 ) 8002676: f043 0304 orr.w r3, r3, #4 800267a: 6213 str r3, [r2, #32] 800267c: 4b5e ldr r3, [pc, #376] ; (80027f8 ) 800267e: 6a1b ldr r3, [r3, #32] 8002680: 4a5d ldr r2, [pc, #372] ; (80027f8 ) 8002682: f043 0301 orr.w r3, r3, #1 8002686: 6213 str r3, [r2, #32] 8002688: e00b b.n 80026a2 800268a: 4b5b ldr r3, [pc, #364] ; (80027f8 ) 800268c: 6a1b ldr r3, [r3, #32] 800268e: 4a5a ldr r2, [pc, #360] ; (80027f8 ) 8002690: f023 0301 bic.w r3, r3, #1 8002694: 6213 str r3, [r2, #32] 8002696: 4b58 ldr r3, [pc, #352] ; (80027f8 ) 8002698: 6a1b ldr r3, [r3, #32] 800269a: 4a57 ldr r2, [pc, #348] ; (80027f8 ) 800269c: f023 0304 bic.w r3, r3, #4 80026a0: 6213 str r3, [r2, #32] /* Check the LSE State */ if (RCC_OscInitStruct->LSEState != RCC_LSE_OFF) 80026a2: 687b ldr r3, [r7, #4] 80026a4: 68db ldr r3, [r3, #12] 80026a6: 2b00 cmp r3, #0 80026a8: d015 beq.n 80026d6 { /* Get Start Tick */ tickstart = HAL_GetTick(); 80026aa: f7ff f887 bl 80017bc 80026ae: 6138 str r0, [r7, #16] /* Wait till LSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 80026b0: e00a b.n 80026c8 { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 80026b2: f7ff f883 bl 80017bc 80026b6: 4602 mov r2, r0 80026b8: 693b ldr r3, [r7, #16] 80026ba: 1ad3 subs r3, r2, r3 80026bc: f241 3288 movw r2, #5000 ; 0x1388 80026c0: 4293 cmp r3, r2 80026c2: d901 bls.n 80026c8 { return HAL_TIMEOUT; 80026c4: 2303 movs r3, #3 80026c6: e0b1 b.n 800282c while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 80026c8: 4b4b ldr r3, [pc, #300] ; (80027f8 ) 80026ca: 6a1b ldr r3, [r3, #32] 80026cc: f003 0302 and.w r3, r3, #2 80026d0: 2b00 cmp r3, #0 80026d2: d0ee beq.n 80026b2 80026d4: e014 b.n 8002700 } } else { /* Get Start Tick */ tickstart = HAL_GetTick(); 80026d6: f7ff f871 bl 80017bc 80026da: 6138 str r0, [r7, #16] /* Wait till LSE is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) 80026dc: e00a b.n 80026f4 { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 80026de: f7ff f86d bl 80017bc 80026e2: 4602 mov r2, r0 80026e4: 693b ldr r3, [r7, #16] 80026e6: 1ad3 subs r3, r2, r3 80026e8: f241 3288 movw r2, #5000 ; 0x1388 80026ec: 4293 cmp r3, r2 80026ee: d901 bls.n 80026f4 { return HAL_TIMEOUT; 80026f0: 2303 movs r3, #3 80026f2: e09b b.n 800282c while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) 80026f4: 4b40 ldr r3, [pc, #256] ; (80027f8 ) 80026f6: 6a1b ldr r3, [r3, #32] 80026f8: f003 0302 and.w r3, r3, #2 80026fc: 2b00 cmp r3, #0 80026fe: d1ee bne.n 80026de } } } /* Require to disable power clock if necessary */ if (pwrclkchanged == SET) 8002700: 7dfb ldrb r3, [r7, #23] 8002702: 2b01 cmp r3, #1 8002704: d105 bne.n 8002712 { __HAL_RCC_PWR_CLK_DISABLE(); 8002706: 4b3c ldr r3, [pc, #240] ; (80027f8 ) 8002708: 69db ldr r3, [r3, #28] 800270a: 4a3b ldr r2, [pc, #236] ; (80027f8 ) 800270c: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000 8002710: 61d3 str r3, [r2, #28] #endif /* RCC_CR_PLL2ON */ /*-------------------------------- PLL Configuration -----------------------*/ /* Check the parameters */ assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) 8002712: 687b ldr r3, [r7, #4] 8002714: 69db ldr r3, [r3, #28] 8002716: 2b00 cmp r3, #0 8002718: f000 8087 beq.w 800282a { /* Check if the PLL is used as system clock or not */ if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) 800271c: 4b36 ldr r3, [pc, #216] ; (80027f8 ) 800271e: 685b ldr r3, [r3, #4] 8002720: f003 030c and.w r3, r3, #12 8002724: 2b08 cmp r3, #8 8002726: d061 beq.n 80027ec { if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) 8002728: 687b ldr r3, [r7, #4] 800272a: 69db ldr r3, [r3, #28] 800272c: 2b02 cmp r3, #2 800272e: d146 bne.n 80027be /* Check the parameters */ assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource)); assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL)); /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 8002730: 4b33 ldr r3, [pc, #204] ; (8002800 ) 8002732: 2200 movs r2, #0 8002734: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8002736: f7ff f841 bl 80017bc 800273a: 6138 str r0, [r7, #16] /* Wait till PLL is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 800273c: e008 b.n 8002750 { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 800273e: f7ff f83d bl 80017bc 8002742: 4602 mov r2, r0 8002744: 693b ldr r3, [r7, #16] 8002746: 1ad3 subs r3, r2, r3 8002748: 2b02 cmp r3, #2 800274a: d901 bls.n 8002750 { return HAL_TIMEOUT; 800274c: 2303 movs r3, #3 800274e: e06d b.n 800282c while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 8002750: 4b29 ldr r3, [pc, #164] ; (80027f8 ) 8002752: 681b ldr r3, [r3, #0] 8002754: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 8002758: 2b00 cmp r3, #0 800275a: d1f0 bne.n 800273e } } /* Configure the HSE prediv factor --------------------------------*/ /* It can be written only when the PLL is disabled. Not used in PLL source is different than HSE */ if (RCC_OscInitStruct->PLL.PLLSource == RCC_PLLSOURCE_HSE) 800275c: 687b ldr r3, [r7, #4] 800275e: 6a1b ldr r3, [r3, #32] 8002760: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 8002764: d108 bne.n 8002778 /* Set PREDIV1 source */ SET_BIT(RCC->CFGR2, RCC_OscInitStruct->Prediv1Source); #endif /* RCC_CFGR2_PREDIV1SRC */ /* Set PREDIV1 Value */ __HAL_RCC_HSE_PREDIV_CONFIG(RCC_OscInitStruct->HSEPredivValue); 8002766: 4b24 ldr r3, [pc, #144] ; (80027f8 ) 8002768: 685b ldr r3, [r3, #4] 800276a: f423 3200 bic.w r2, r3, #131072 ; 0x20000 800276e: 687b ldr r3, [r7, #4] 8002770: 689b ldr r3, [r3, #8] 8002772: 4921 ldr r1, [pc, #132] ; (80027f8 ) 8002774: 4313 orrs r3, r2 8002776: 604b str r3, [r1, #4] } /* Configure the main PLL clock source and multiplication factors. */ __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, 8002778: 4b1f ldr r3, [pc, #124] ; (80027f8 ) 800277a: 685b ldr r3, [r3, #4] 800277c: f423 1274 bic.w r2, r3, #3997696 ; 0x3d0000 8002780: 687b ldr r3, [r7, #4] 8002782: 6a19 ldr r1, [r3, #32] 8002784: 687b ldr r3, [r7, #4] 8002786: 6a5b ldr r3, [r3, #36] ; 0x24 8002788: 430b orrs r3, r1 800278a: 491b ldr r1, [pc, #108] ; (80027f8 ) 800278c: 4313 orrs r3, r2 800278e: 604b str r3, [r1, #4] RCC_OscInitStruct->PLL.PLLMUL); /* Enable the main PLL. */ __HAL_RCC_PLL_ENABLE(); 8002790: 4b1b ldr r3, [pc, #108] ; (8002800 ) 8002792: 2201 movs r2, #1 8002794: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8002796: f7ff f811 bl 80017bc 800279a: 6138 str r0, [r7, #16] /* Wait till PLL is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 800279c: e008 b.n 80027b0 { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 800279e: f7ff f80d bl 80017bc 80027a2: 4602 mov r2, r0 80027a4: 693b ldr r3, [r7, #16] 80027a6: 1ad3 subs r3, r2, r3 80027a8: 2b02 cmp r3, #2 80027aa: d901 bls.n 80027b0 { return HAL_TIMEOUT; 80027ac: 2303 movs r3, #3 80027ae: e03d b.n 800282c while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 80027b0: 4b11 ldr r3, [pc, #68] ; (80027f8 ) 80027b2: 681b ldr r3, [r3, #0] 80027b4: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 80027b8: 2b00 cmp r3, #0 80027ba: d0f0 beq.n 800279e 80027bc: e035 b.n 800282a } } else { /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 80027be: 4b10 ldr r3, [pc, #64] ; (8002800 ) 80027c0: 2200 movs r2, #0 80027c2: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 80027c4: f7fe fffa bl 80017bc 80027c8: 6138 str r0, [r7, #16] /* Wait till PLL is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 80027ca: e008 b.n 80027de { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 80027cc: f7fe fff6 bl 80017bc 80027d0: 4602 mov r2, r0 80027d2: 693b ldr r3, [r7, #16] 80027d4: 1ad3 subs r3, r2, r3 80027d6: 2b02 cmp r3, #2 80027d8: d901 bls.n 80027de { return HAL_TIMEOUT; 80027da: 2303 movs r3, #3 80027dc: e026 b.n 800282c while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 80027de: 4b06 ldr r3, [pc, #24] ; (80027f8 ) 80027e0: 681b ldr r3, [r3, #0] 80027e2: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 80027e6: 2b00 cmp r3, #0 80027e8: d1f0 bne.n 80027cc 80027ea: e01e b.n 800282a } } else { /* Check if there is a request to disable the PLL used as System clock source */ if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) 80027ec: 687b ldr r3, [r7, #4] 80027ee: 69db ldr r3, [r3, #28] 80027f0: 2b01 cmp r3, #1 80027f2: d107 bne.n 8002804 { return HAL_ERROR; 80027f4: 2301 movs r3, #1 80027f6: e019 b.n 800282c 80027f8: 40021000 .word 0x40021000 80027fc: 40007000 .word 0x40007000 8002800: 42420060 .word 0x42420060 } else { /* Do not return HAL_ERROR if request repeats the current configuration */ pll_config = RCC->CFGR; 8002804: 4b0b ldr r3, [pc, #44] ; (8002834 ) 8002806: 685b ldr r3, [r3, #4] 8002808: 60fb str r3, [r7, #12] if ((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 800280a: 68fb ldr r3, [r7, #12] 800280c: f403 3280 and.w r2, r3, #65536 ; 0x10000 8002810: 687b ldr r3, [r7, #4] 8002812: 6a1b ldr r3, [r3, #32] 8002814: 429a cmp r2, r3 8002816: d106 bne.n 8002826 (READ_BIT(pll_config, RCC_CFGR_PLLMULL) != RCC_OscInitStruct->PLL.PLLMUL)) 8002818: 68fb ldr r3, [r7, #12] 800281a: f403 1270 and.w r2, r3, #3932160 ; 0x3c0000 800281e: 687b ldr r3, [r7, #4] 8002820: 6a5b ldr r3, [r3, #36] ; 0x24 if ((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 8002822: 429a cmp r2, r3 8002824: d001 beq.n 800282a { return HAL_ERROR; 8002826: 2301 movs r3, #1 8002828: e000 b.n 800282c } } } } return HAL_OK; 800282a: 2300 movs r3, #0 } 800282c: 4618 mov r0, r3 800282e: 3718 adds r7, #24 8002830: 46bd mov sp, r7 8002832: bd80 pop {r7, pc} 8002834: 40021000 .word 0x40021000 08002838 : * You can use @ref HAL_RCC_GetClockConfig() function to know which clock is * currently used as system clock source. * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) { 8002838: b580 push {r7, lr} 800283a: b084 sub sp, #16 800283c: af00 add r7, sp, #0 800283e: 6078 str r0, [r7, #4] 8002840: 6039 str r1, [r7, #0] uint32_t tickstart; /* Check Null pointer */ if (RCC_ClkInitStruct == NULL) 8002842: 687b ldr r3, [r7, #4] 8002844: 2b00 cmp r3, #0 8002846: d101 bne.n 800284c { return HAL_ERROR; 8002848: 2301 movs r3, #1 800284a: e0d0 b.n 80029ee must be correctly programmed according to the frequency of the CPU clock (HCLK) of the device. */ #if defined(FLASH_ACR_LATENCY) /* Increasing the number of wait states because of higher CPU frequency */ if (FLatency > __HAL_FLASH_GET_LATENCY()) 800284c: 4b6a ldr r3, [pc, #424] ; (80029f8 ) 800284e: 681b ldr r3, [r3, #0] 8002850: f003 0307 and.w r3, r3, #7 8002854: 683a ldr r2, [r7, #0] 8002856: 429a cmp r2, r3 8002858: d910 bls.n 800287c { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 800285a: 4b67 ldr r3, [pc, #412] ; (80029f8 ) 800285c: 681b ldr r3, [r3, #0] 800285e: f023 0207 bic.w r2, r3, #7 8002862: 4965 ldr r1, [pc, #404] ; (80029f8 ) 8002864: 683b ldr r3, [r7, #0] 8002866: 4313 orrs r3, r2 8002868: 600b str r3, [r1, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if (__HAL_FLASH_GET_LATENCY() != FLatency) 800286a: 4b63 ldr r3, [pc, #396] ; (80029f8 ) 800286c: 681b ldr r3, [r3, #0] 800286e: f003 0307 and.w r3, r3, #7 8002872: 683a ldr r2, [r7, #0] 8002874: 429a cmp r2, r3 8002876: d001 beq.n 800287c { return HAL_ERROR; 8002878: 2301 movs r3, #1 800287a: e0b8 b.n 80029ee } } #endif /* FLASH_ACR_LATENCY */ /*-------------------------- HCLK Configuration --------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) 800287c: 687b ldr r3, [r7, #4] 800287e: 681b ldr r3, [r3, #0] 8002880: f003 0302 and.w r3, r3, #2 8002884: 2b00 cmp r3, #0 8002886: d020 beq.n 80028ca { /* Set the highest APBx dividers in order to ensure that we do not go through a non-spec phase whatever we decrease or increase HCLK. */ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 8002888: 687b ldr r3, [r7, #4] 800288a: 681b ldr r3, [r3, #0] 800288c: f003 0304 and.w r3, r3, #4 8002890: 2b00 cmp r3, #0 8002892: d005 beq.n 80028a0 { MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16); 8002894: 4b59 ldr r3, [pc, #356] ; (80029fc ) 8002896: 685b ldr r3, [r3, #4] 8002898: 4a58 ldr r2, [pc, #352] ; (80029fc ) 800289a: f443 63e0 orr.w r3, r3, #1792 ; 0x700 800289e: 6053 str r3, [r2, #4] } if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 80028a0: 687b ldr r3, [r7, #4] 80028a2: 681b ldr r3, [r3, #0] 80028a4: f003 0308 and.w r3, r3, #8 80028a8: 2b00 cmp r3, #0 80028aa: d005 beq.n 80028b8 { MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3)); 80028ac: 4b53 ldr r3, [pc, #332] ; (80029fc ) 80028ae: 685b ldr r3, [r3, #4] 80028b0: 4a52 ldr r2, [pc, #328] ; (80029fc ) 80028b2: f443 5360 orr.w r3, r3, #14336 ; 0x3800 80028b6: 6053 str r3, [r2, #4] } /* Set the new HCLK clock divider */ assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); 80028b8: 4b50 ldr r3, [pc, #320] ; (80029fc ) 80028ba: 685b ldr r3, [r3, #4] 80028bc: f023 02f0 bic.w r2, r3, #240 ; 0xf0 80028c0: 687b ldr r3, [r7, #4] 80028c2: 689b ldr r3, [r3, #8] 80028c4: 494d ldr r1, [pc, #308] ; (80029fc ) 80028c6: 4313 orrs r3, r2 80028c8: 604b str r3, [r1, #4] } /*------------------------- SYSCLK Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) 80028ca: 687b ldr r3, [r7, #4] 80028cc: 681b ldr r3, [r3, #0] 80028ce: f003 0301 and.w r3, r3, #1 80028d2: 2b00 cmp r3, #0 80028d4: d040 beq.n 8002958 { assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); /* HSE is selected as System Clock Source */ if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) 80028d6: 687b ldr r3, [r7, #4] 80028d8: 685b ldr r3, [r3, #4] 80028da: 2b01 cmp r3, #1 80028dc: d107 bne.n 80028ee { /* Check the HSE ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 80028de: 4b47 ldr r3, [pc, #284] ; (80029fc ) 80028e0: 681b ldr r3, [r3, #0] 80028e2: f403 3300 and.w r3, r3, #131072 ; 0x20000 80028e6: 2b00 cmp r3, #0 80028e8: d115 bne.n 8002916 { return HAL_ERROR; 80028ea: 2301 movs r3, #1 80028ec: e07f b.n 80029ee } } /* PLL is selected as System Clock Source */ else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) 80028ee: 687b ldr r3, [r7, #4] 80028f0: 685b ldr r3, [r3, #4] 80028f2: 2b02 cmp r3, #2 80028f4: d107 bne.n 8002906 { /* Check the PLL ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 80028f6: 4b41 ldr r3, [pc, #260] ; (80029fc ) 80028f8: 681b ldr r3, [r3, #0] 80028fa: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 80028fe: 2b00 cmp r3, #0 8002900: d109 bne.n 8002916 { return HAL_ERROR; 8002902: 2301 movs r3, #1 8002904: e073 b.n 80029ee } /* HSI is selected as System Clock Source */ else { /* Check the HSI ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 8002906: 4b3d ldr r3, [pc, #244] ; (80029fc ) 8002908: 681b ldr r3, [r3, #0] 800290a: f003 0302 and.w r3, r3, #2 800290e: 2b00 cmp r3, #0 8002910: d101 bne.n 8002916 { return HAL_ERROR; 8002912: 2301 movs r3, #1 8002914: e06b b.n 80029ee } } __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource); 8002916: 4b39 ldr r3, [pc, #228] ; (80029fc ) 8002918: 685b ldr r3, [r3, #4] 800291a: f023 0203 bic.w r2, r3, #3 800291e: 687b ldr r3, [r7, #4] 8002920: 685b ldr r3, [r3, #4] 8002922: 4936 ldr r1, [pc, #216] ; (80029fc ) 8002924: 4313 orrs r3, r2 8002926: 604b str r3, [r1, #4] /* Get Start Tick */ tickstart = HAL_GetTick(); 8002928: f7fe ff48 bl 80017bc 800292c: 60f8 str r0, [r7, #12] while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 800292e: e00a b.n 8002946 { if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) 8002930: f7fe ff44 bl 80017bc 8002934: 4602 mov r2, r0 8002936: 68fb ldr r3, [r7, #12] 8002938: 1ad3 subs r3, r2, r3 800293a: f241 3288 movw r2, #5000 ; 0x1388 800293e: 4293 cmp r3, r2 8002940: d901 bls.n 8002946 { return HAL_TIMEOUT; 8002942: 2303 movs r3, #3 8002944: e053 b.n 80029ee while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 8002946: 4b2d ldr r3, [pc, #180] ; (80029fc ) 8002948: 685b ldr r3, [r3, #4] 800294a: f003 020c and.w r2, r3, #12 800294e: 687b ldr r3, [r7, #4] 8002950: 685b ldr r3, [r3, #4] 8002952: 009b lsls r3, r3, #2 8002954: 429a cmp r2, r3 8002956: d1eb bne.n 8002930 } } #if defined(FLASH_ACR_LATENCY) /* Decreasing the number of wait states because of lower CPU frequency */ if (FLatency < __HAL_FLASH_GET_LATENCY()) 8002958: 4b27 ldr r3, [pc, #156] ; (80029f8 ) 800295a: 681b ldr r3, [r3, #0] 800295c: f003 0307 and.w r3, r3, #7 8002960: 683a ldr r2, [r7, #0] 8002962: 429a cmp r2, r3 8002964: d210 bcs.n 8002988 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 8002966: 4b24 ldr r3, [pc, #144] ; (80029f8 ) 8002968: 681b ldr r3, [r3, #0] 800296a: f023 0207 bic.w r2, r3, #7 800296e: 4922 ldr r1, [pc, #136] ; (80029f8 ) 8002970: 683b ldr r3, [r7, #0] 8002972: 4313 orrs r3, r2 8002974: 600b str r3, [r1, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if (__HAL_FLASH_GET_LATENCY() != FLatency) 8002976: 4b20 ldr r3, [pc, #128] ; (80029f8 ) 8002978: 681b ldr r3, [r3, #0] 800297a: f003 0307 and.w r3, r3, #7 800297e: 683a ldr r2, [r7, #0] 8002980: 429a cmp r2, r3 8002982: d001 beq.n 8002988 { return HAL_ERROR; 8002984: 2301 movs r3, #1 8002986: e032 b.n 80029ee } } #endif /* FLASH_ACR_LATENCY */ /*-------------------------- PCLK1 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 8002988: 687b ldr r3, [r7, #4] 800298a: 681b ldr r3, [r3, #0] 800298c: f003 0304 and.w r3, r3, #4 8002990: 2b00 cmp r3, #0 8002992: d008 beq.n 80029a6 { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider); 8002994: 4b19 ldr r3, [pc, #100] ; (80029fc ) 8002996: 685b ldr r3, [r3, #4] 8002998: f423 62e0 bic.w r2, r3, #1792 ; 0x700 800299c: 687b ldr r3, [r7, #4] 800299e: 68db ldr r3, [r3, #12] 80029a0: 4916 ldr r1, [pc, #88] ; (80029fc ) 80029a2: 4313 orrs r3, r2 80029a4: 604b str r3, [r1, #4] } /*-------------------------- PCLK2 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 80029a6: 687b ldr r3, [r7, #4] 80029a8: 681b ldr r3, [r3, #0] 80029aa: f003 0308 and.w r3, r3, #8 80029ae: 2b00 cmp r3, #0 80029b0: d009 beq.n 80029c6 { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3)); 80029b2: 4b12 ldr r3, [pc, #72] ; (80029fc ) 80029b4: 685b ldr r3, [r3, #4] 80029b6: f423 5260 bic.w r2, r3, #14336 ; 0x3800 80029ba: 687b ldr r3, [r7, #4] 80029bc: 691b ldr r3, [r3, #16] 80029be: 00db lsls r3, r3, #3 80029c0: 490e ldr r1, [pc, #56] ; (80029fc ) 80029c2: 4313 orrs r3, r2 80029c4: 604b str r3, [r1, #4] } /* Update the SystemCoreClock global variable */ SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]; 80029c6: f000 f821 bl 8002a0c 80029ca: 4602 mov r2, r0 80029cc: 4b0b ldr r3, [pc, #44] ; (80029fc ) 80029ce: 685b ldr r3, [r3, #4] 80029d0: 091b lsrs r3, r3, #4 80029d2: f003 030f and.w r3, r3, #15 80029d6: 490a ldr r1, [pc, #40] ; (8002a00 ) 80029d8: 5ccb ldrb r3, [r1, r3] 80029da: fa22 f303 lsr.w r3, r2, r3 80029de: 4a09 ldr r2, [pc, #36] ; (8002a04 ) 80029e0: 6013 str r3, [r2, #0] /* Configure the source of time base considering new system clocks settings*/ HAL_InitTick(uwTickPrio); 80029e2: 4b09 ldr r3, [pc, #36] ; (8002a08 ) 80029e4: 681b ldr r3, [r3, #0] 80029e6: 4618 mov r0, r3 80029e8: f7fe fea6 bl 8001738 return HAL_OK; 80029ec: 2300 movs r3, #0 } 80029ee: 4618 mov r0, r3 80029f0: 3710 adds r7, #16 80029f2: 46bd mov sp, r7 80029f4: bd80 pop {r7, pc} 80029f6: bf00 nop 80029f8: 40022000 .word 0x40022000 80029fc: 40021000 .word 0x40021000 8002a00: 08006260 .word 0x08006260 8002a04: 20000000 .word 0x20000000 8002a08: 20000004 .word 0x20000004 08002a0c : * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect. * * @retval SYSCLK frequency */ uint32_t HAL_RCC_GetSysClockFreq(void) { 8002a0c: b490 push {r4, r7} 8002a0e: b08a sub sp, #40 ; 0x28 8002a10: af00 add r7, sp, #0 #if defined(RCC_CFGR2_PREDIV1SRC) const uint8_t aPLLMULFactorTable[14] = {0, 0, 4, 5, 6, 7, 8, 9, 0, 0, 0, 0, 0, 13}; const uint8_t aPredivFactorTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}; #else const uint8_t aPLLMULFactorTable[16] = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16}; 8002a12: 4b29 ldr r3, [pc, #164] ; (8002ab8 ) 8002a14: 1d3c adds r4, r7, #4 8002a16: cb0f ldmia r3, {r0, r1, r2, r3} 8002a18: e884 000f stmia.w r4, {r0, r1, r2, r3} #if defined(RCC_CFGR2_PREDIV1) const uint8_t aPredivFactorTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}; #else const uint8_t aPredivFactorTable[2] = {1, 2}; 8002a1c: f240 2301 movw r3, #513 ; 0x201 8002a20: 803b strh r3, [r7, #0] #endif /*RCC_CFGR2_PREDIV1*/ #endif uint32_t tmpreg = 0U, prediv = 0U, pllclk = 0U, pllmul = 0U; 8002a22: 2300 movs r3, #0 8002a24: 61fb str r3, [r7, #28] 8002a26: 2300 movs r3, #0 8002a28: 61bb str r3, [r7, #24] 8002a2a: 2300 movs r3, #0 8002a2c: 627b str r3, [r7, #36] ; 0x24 8002a2e: 2300 movs r3, #0 8002a30: 617b str r3, [r7, #20] uint32_t sysclockfreq = 0U; 8002a32: 2300 movs r3, #0 8002a34: 623b str r3, [r7, #32] #if defined(RCC_CFGR2_PREDIV1SRC) uint32_t prediv2 = 0U, pll2mul = 0U; #endif /*RCC_CFGR2_PREDIV1SRC*/ tmpreg = RCC->CFGR; 8002a36: 4b21 ldr r3, [pc, #132] ; (8002abc ) 8002a38: 685b ldr r3, [r3, #4] 8002a3a: 61fb str r3, [r7, #28] /* Get SYSCLK source -------------------------------------------------------*/ switch (tmpreg & RCC_CFGR_SWS) 8002a3c: 69fb ldr r3, [r7, #28] 8002a3e: f003 030c and.w r3, r3, #12 8002a42: 2b04 cmp r3, #4 8002a44: d002 beq.n 8002a4c 8002a46: 2b08 cmp r3, #8 8002a48: d003 beq.n 8002a52 8002a4a: e02b b.n 8002aa4 { case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */ { sysclockfreq = HSE_VALUE; 8002a4c: 4b1c ldr r3, [pc, #112] ; (8002ac0 ) 8002a4e: 623b str r3, [r7, #32] break; 8002a50: e02b b.n 8002aaa } case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */ { pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos]; 8002a52: 69fb ldr r3, [r7, #28] 8002a54: 0c9b lsrs r3, r3, #18 8002a56: f003 030f and.w r3, r3, #15 8002a5a: 3328 adds r3, #40 ; 0x28 8002a5c: 443b add r3, r7 8002a5e: f813 3c24 ldrb.w r3, [r3, #-36] 8002a62: 617b str r3, [r7, #20] if ((tmpreg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2) 8002a64: 69fb ldr r3, [r7, #28] 8002a66: f403 3380 and.w r3, r3, #65536 ; 0x10000 8002a6a: 2b00 cmp r3, #0 8002a6c: d012 beq.n 8002a94 { #if defined(RCC_CFGR2_PREDIV1) prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> RCC_CFGR2_PREDIV1_Pos]; #else prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos]; 8002a6e: 4b13 ldr r3, [pc, #76] ; (8002abc ) 8002a70: 685b ldr r3, [r3, #4] 8002a72: 0c5b lsrs r3, r3, #17 8002a74: f003 0301 and.w r3, r3, #1 8002a78: 3328 adds r3, #40 ; 0x28 8002a7a: 443b add r3, r7 8002a7c: f813 3c28 ldrb.w r3, [r3, #-40] 8002a80: 61bb str r3, [r7, #24] { pllclk = pllclk / 2; } #else /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */ pllclk = (uint32_t)((HSE_VALUE * pllmul) / prediv); 8002a82: 697b ldr r3, [r7, #20] 8002a84: 4a0e ldr r2, [pc, #56] ; (8002ac0 ) 8002a86: fb03 f202 mul.w r2, r3, r2 8002a8a: 69bb ldr r3, [r7, #24] 8002a8c: fbb2 f3f3 udiv r3, r2, r3 8002a90: 627b str r3, [r7, #36] ; 0x24 8002a92: e004 b.n 8002a9e #endif /*RCC_CFGR2_PREDIV1SRC*/ } else { /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */ pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul); 8002a94: 697b ldr r3, [r7, #20] 8002a96: 4a0b ldr r2, [pc, #44] ; (8002ac4 ) 8002a98: fb02 f303 mul.w r3, r2, r3 8002a9c: 627b str r3, [r7, #36] ; 0x24 } sysclockfreq = pllclk; 8002a9e: 6a7b ldr r3, [r7, #36] ; 0x24 8002aa0: 623b str r3, [r7, #32] break; 8002aa2: e002 b.n 8002aaa } case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */ default: /* HSI used as system clock */ { sysclockfreq = HSI_VALUE; 8002aa4: 4b06 ldr r3, [pc, #24] ; (8002ac0 ) 8002aa6: 623b str r3, [r7, #32] break; 8002aa8: bf00 nop } } return sysclockfreq; 8002aaa: 6a3b ldr r3, [r7, #32] } 8002aac: 4618 mov r0, r3 8002aae: 3728 adds r7, #40 ; 0x28 8002ab0: 46bd mov sp, r7 8002ab2: bc90 pop {r4, r7} 8002ab4: 4770 bx lr 8002ab6: bf00 nop 8002ab8: 08006250 .word 0x08006250 8002abc: 40021000 .word 0x40021000 8002ac0: 007a1200 .word 0x007a1200 8002ac4: 003d0900 .word 0x003d0900 08002ac8 : * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency * and updated within this function * @retval HCLK frequency */ uint32_t HAL_RCC_GetHCLKFreq(void) { 8002ac8: b480 push {r7} 8002aca: af00 add r7, sp, #0 return SystemCoreClock; 8002acc: 4b02 ldr r3, [pc, #8] ; (8002ad8 ) 8002ace: 681b ldr r3, [r3, #0] } 8002ad0: 4618 mov r0, r3 8002ad2: 46bd mov sp, r7 8002ad4: bc80 pop {r7} 8002ad6: 4770 bx lr 8002ad8: 20000000 .word 0x20000000 08002adc : * @note Each time PCLK1 changes, this function must be called to update the * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK1 frequency */ uint32_t HAL_RCC_GetPCLK1Freq(void) { 8002adc: b580 push {r7, lr} 8002ade: af00 add r7, sp, #0 /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]); 8002ae0: f7ff fff2 bl 8002ac8 8002ae4: 4602 mov r2, r0 8002ae6: 4b05 ldr r3, [pc, #20] ; (8002afc ) 8002ae8: 685b ldr r3, [r3, #4] 8002aea: 0a1b lsrs r3, r3, #8 8002aec: f003 0307 and.w r3, r3, #7 8002af0: 4903 ldr r1, [pc, #12] ; (8002b00 ) 8002af2: 5ccb ldrb r3, [r1, r3] 8002af4: fa22 f303 lsr.w r3, r2, r3 } 8002af8: 4618 mov r0, r3 8002afa: bd80 pop {r7, pc} 8002afc: 40021000 .word 0x40021000 8002b00: 08006270 .word 0x08006270 08002b04 : * @note Each time PCLK2 changes, this function must be called to update the * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK2 frequency */ uint32_t HAL_RCC_GetPCLK2Freq(void) { 8002b04: b580 push {r7, lr} 8002b06: af00 add r7, sp, #0 /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]); 8002b08: f7ff ffde bl 8002ac8 8002b0c: 4602 mov r2, r0 8002b0e: 4b05 ldr r3, [pc, #20] ; (8002b24 ) 8002b10: 685b ldr r3, [r3, #4] 8002b12: 0adb lsrs r3, r3, #11 8002b14: f003 0307 and.w r3, r3, #7 8002b18: 4903 ldr r1, [pc, #12] ; (8002b28 ) 8002b1a: 5ccb ldrb r3, [r1, r3] 8002b1c: fa22 f303 lsr.w r3, r2, r3 } 8002b20: 4618 mov r0, r3 8002b22: bd80 pop {r7, pc} 8002b24: 40021000 .word 0x40021000 8002b28: 08006270 .word 0x08006270 08002b2c : * @brief This function provides delay (in milliseconds) based on CPU cycles method. * @param mdelay: specifies the delay time length, in milliseconds. * @retval None */ static void RCC_Delay(uint32_t mdelay) { 8002b2c: b480 push {r7} 8002b2e: b085 sub sp, #20 8002b30: af00 add r7, sp, #0 8002b32: 6078 str r0, [r7, #4] __IO uint32_t Delay = mdelay * (SystemCoreClock / 8U / 1000U); 8002b34: 4b0a ldr r3, [pc, #40] ; (8002b60 ) 8002b36: 681b ldr r3, [r3, #0] 8002b38: 4a0a ldr r2, [pc, #40] ; (8002b64 ) 8002b3a: fba2 2303 umull r2, r3, r2, r3 8002b3e: 0a5b lsrs r3, r3, #9 8002b40: 687a ldr r2, [r7, #4] 8002b42: fb02 f303 mul.w r3, r2, r3 8002b46: 60fb str r3, [r7, #12] do { __NOP(); 8002b48: bf00 nop } while (Delay --); 8002b4a: 68fb ldr r3, [r7, #12] 8002b4c: 1e5a subs r2, r3, #1 8002b4e: 60fa str r2, [r7, #12] 8002b50: 2b00 cmp r3, #0 8002b52: d1f9 bne.n 8002b48 } 8002b54: bf00 nop 8002b56: bf00 nop 8002b58: 3714 adds r7, #20 8002b5a: 46bd mov sp, r7 8002b5c: bc80 pop {r7} 8002b5e: 4770 bx lr 8002b60: 20000000 .word 0x20000000 8002b64: 10624dd3 .word 0x10624dd3 08002b68 : * manually disable it. * * @retval HAL status */ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) { 8002b68: b580 push {r7, lr} 8002b6a: b086 sub sp, #24 8002b6c: af00 add r7, sp, #0 8002b6e: 6078 str r0, [r7, #4] uint32_t tickstart = 0U, temp_reg = 0U; 8002b70: 2300 movs r3, #0 8002b72: 613b str r3, [r7, #16] 8002b74: 2300 movs r3, #0 8002b76: 60fb str r3, [r7, #12] /* Check the parameters */ assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); /*------------------------------- RTC/LCD Configuration ------------------------*/ if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) 8002b78: 687b ldr r3, [r7, #4] 8002b7a: 681b ldr r3, [r3, #0] 8002b7c: f003 0301 and.w r3, r3, #1 8002b80: 2b00 cmp r3, #0 8002b82: d07d beq.n 8002c80 { FlagStatus pwrclkchanged = RESET; 8002b84: 2300 movs r3, #0 8002b86: 75fb strb r3, [r7, #23] assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); /* As soon as function is called to change RTC clock source, activation of the power domain is done. */ /* Requires to enable write access to Backup Domain of necessary */ if (__HAL_RCC_PWR_IS_CLK_DISABLED()) 8002b88: 4b4f ldr r3, [pc, #316] ; (8002cc8 ) 8002b8a: 69db ldr r3, [r3, #28] 8002b8c: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 8002b90: 2b00 cmp r3, #0 8002b92: d10d bne.n 8002bb0 { __HAL_RCC_PWR_CLK_ENABLE(); 8002b94: 4b4c ldr r3, [pc, #304] ; (8002cc8 ) 8002b96: 69db ldr r3, [r3, #28] 8002b98: 4a4b ldr r2, [pc, #300] ; (8002cc8 ) 8002b9a: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 8002b9e: 61d3 str r3, [r2, #28] 8002ba0: 4b49 ldr r3, [pc, #292] ; (8002cc8 ) 8002ba2: 69db ldr r3, [r3, #28] 8002ba4: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 8002ba8: 60bb str r3, [r7, #8] 8002baa: 68bb ldr r3, [r7, #8] pwrclkchanged = SET; 8002bac: 2301 movs r3, #1 8002bae: 75fb strb r3, [r7, #23] } if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8002bb0: 4b46 ldr r3, [pc, #280] ; (8002ccc ) 8002bb2: 681b ldr r3, [r3, #0] 8002bb4: f403 7380 and.w r3, r3, #256 ; 0x100 8002bb8: 2b00 cmp r3, #0 8002bba: d118 bne.n 8002bee { /* Enable write access to Backup domain */ SET_BIT(PWR->CR, PWR_CR_DBP); 8002bbc: 4b43 ldr r3, [pc, #268] ; (8002ccc ) 8002bbe: 681b ldr r3, [r3, #0] 8002bc0: 4a42 ldr r2, [pc, #264] ; (8002ccc ) 8002bc2: f443 7380 orr.w r3, r3, #256 ; 0x100 8002bc6: 6013 str r3, [r2, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 8002bc8: f7fe fdf8 bl 80017bc 8002bcc: 6138 str r0, [r7, #16] while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8002bce: e008 b.n 8002be2 { if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 8002bd0: f7fe fdf4 bl 80017bc 8002bd4: 4602 mov r2, r0 8002bd6: 693b ldr r3, [r7, #16] 8002bd8: 1ad3 subs r3, r2, r3 8002bda: 2b64 cmp r3, #100 ; 0x64 8002bdc: d901 bls.n 8002be2 { return HAL_TIMEOUT; 8002bde: 2303 movs r3, #3 8002be0: e06d b.n 8002cbe while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8002be2: 4b3a ldr r3, [pc, #232] ; (8002ccc ) 8002be4: 681b ldr r3, [r3, #0] 8002be6: f403 7380 and.w r3, r3, #256 ; 0x100 8002bea: 2b00 cmp r3, #0 8002bec: d0f0 beq.n 8002bd0 } } } /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ temp_reg = (RCC->BDCR & RCC_BDCR_RTCSEL); 8002bee: 4b36 ldr r3, [pc, #216] ; (8002cc8 ) 8002bf0: 6a1b ldr r3, [r3, #32] 8002bf2: f403 7340 and.w r3, r3, #768 ; 0x300 8002bf6: 60fb str r3, [r7, #12] if ((temp_reg != 0x00000000U) && (temp_reg != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))) 8002bf8: 68fb ldr r3, [r7, #12] 8002bfa: 2b00 cmp r3, #0 8002bfc: d02e beq.n 8002c5c 8002bfe: 687b ldr r3, [r7, #4] 8002c00: 685b ldr r3, [r3, #4] 8002c02: f403 7340 and.w r3, r3, #768 ; 0x300 8002c06: 68fa ldr r2, [r7, #12] 8002c08: 429a cmp r2, r3 8002c0a: d027 beq.n 8002c5c { /* Store the content of BDCR register before the reset of Backup Domain */ temp_reg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); 8002c0c: 4b2e ldr r3, [pc, #184] ; (8002cc8 ) 8002c0e: 6a1b ldr r3, [r3, #32] 8002c10: f423 7340 bic.w r3, r3, #768 ; 0x300 8002c14: 60fb str r3, [r7, #12] /* RTC Clock selection can be changed only if the Backup Domain is reset */ __HAL_RCC_BACKUPRESET_FORCE(); 8002c16: 4b2e ldr r3, [pc, #184] ; (8002cd0 ) 8002c18: 2201 movs r2, #1 8002c1a: 601a str r2, [r3, #0] __HAL_RCC_BACKUPRESET_RELEASE(); 8002c1c: 4b2c ldr r3, [pc, #176] ; (8002cd0 ) 8002c1e: 2200 movs r2, #0 8002c20: 601a str r2, [r3, #0] /* Restore the Content of BDCR register */ RCC->BDCR = temp_reg; 8002c22: 4a29 ldr r2, [pc, #164] ; (8002cc8 ) 8002c24: 68fb ldr r3, [r7, #12] 8002c26: 6213 str r3, [r2, #32] /* Wait for LSERDY if LSE was enabled */ if (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSEON)) 8002c28: 68fb ldr r3, [r7, #12] 8002c2a: f003 0301 and.w r3, r3, #1 8002c2e: 2b00 cmp r3, #0 8002c30: d014 beq.n 8002c5c { /* Get Start Tick */ tickstart = HAL_GetTick(); 8002c32: f7fe fdc3 bl 80017bc 8002c36: 6138 str r0, [r7, #16] /* Wait till LSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 8002c38: e00a b.n 8002c50 { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 8002c3a: f7fe fdbf bl 80017bc 8002c3e: 4602 mov r2, r0 8002c40: 693b ldr r3, [r7, #16] 8002c42: 1ad3 subs r3, r2, r3 8002c44: f241 3288 movw r2, #5000 ; 0x1388 8002c48: 4293 cmp r3, r2 8002c4a: d901 bls.n 8002c50 { return HAL_TIMEOUT; 8002c4c: 2303 movs r3, #3 8002c4e: e036 b.n 8002cbe while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 8002c50: 4b1d ldr r3, [pc, #116] ; (8002cc8 ) 8002c52: 6a1b ldr r3, [r3, #32] 8002c54: f003 0302 and.w r3, r3, #2 8002c58: 2b00 cmp r3, #0 8002c5a: d0ee beq.n 8002c3a } } } } __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); 8002c5c: 4b1a ldr r3, [pc, #104] ; (8002cc8 ) 8002c5e: 6a1b ldr r3, [r3, #32] 8002c60: f423 7240 bic.w r2, r3, #768 ; 0x300 8002c64: 687b ldr r3, [r7, #4] 8002c66: 685b ldr r3, [r3, #4] 8002c68: 4917 ldr r1, [pc, #92] ; (8002cc8 ) 8002c6a: 4313 orrs r3, r2 8002c6c: 620b str r3, [r1, #32] /* Require to disable power clock if necessary */ if (pwrclkchanged == SET) 8002c6e: 7dfb ldrb r3, [r7, #23] 8002c70: 2b01 cmp r3, #1 8002c72: d105 bne.n 8002c80 { __HAL_RCC_PWR_CLK_DISABLE(); 8002c74: 4b14 ldr r3, [pc, #80] ; (8002cc8 ) 8002c76: 69db ldr r3, [r3, #28] 8002c78: 4a13 ldr r2, [pc, #76] ; (8002cc8 ) 8002c7a: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000 8002c7e: 61d3 str r3, [r2, #28] } } /*------------------------------ ADC clock Configuration ------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) 8002c80: 687b ldr r3, [r7, #4] 8002c82: 681b ldr r3, [r3, #0] 8002c84: f003 0302 and.w r3, r3, #2 8002c88: 2b00 cmp r3, #0 8002c8a: d008 beq.n 8002c9e { /* Check the parameters */ assert_param(IS_RCC_ADCPLLCLK_DIV(PeriphClkInit->AdcClockSelection)); /* Configure the ADC clock source */ __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection); 8002c8c: 4b0e ldr r3, [pc, #56] ; (8002cc8 ) 8002c8e: 685b ldr r3, [r3, #4] 8002c90: f423 4240 bic.w r2, r3, #49152 ; 0xc000 8002c94: 687b ldr r3, [r7, #4] 8002c96: 689b ldr r3, [r3, #8] 8002c98: 490b ldr r1, [pc, #44] ; (8002cc8 ) 8002c9a: 4313 orrs r3, r2 8002c9c: 604b str r3, [r1, #4] #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\ || defined(STM32F105xC) || defined(STM32F107xC) /*------------------------------ USB clock Configuration ------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) 8002c9e: 687b ldr r3, [r7, #4] 8002ca0: 681b ldr r3, [r3, #0] 8002ca2: f003 0310 and.w r3, r3, #16 8002ca6: 2b00 cmp r3, #0 8002ca8: d008 beq.n 8002cbc { /* Check the parameters */ assert_param(IS_RCC_USBPLLCLK_DIV(PeriphClkInit->UsbClockSelection)); /* Configure the USB clock source */ __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection); 8002caa: 4b07 ldr r3, [pc, #28] ; (8002cc8 ) 8002cac: 685b ldr r3, [r3, #4] 8002cae: f423 0280 bic.w r2, r3, #4194304 ; 0x400000 8002cb2: 687b ldr r3, [r7, #4] 8002cb4: 68db ldr r3, [r3, #12] 8002cb6: 4904 ldr r1, [pc, #16] ; (8002cc8 ) 8002cb8: 4313 orrs r3, r2 8002cba: 604b str r3, [r1, #4] } #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ return HAL_OK; 8002cbc: 2300 movs r3, #0 } 8002cbe: 4618 mov r0, r3 8002cc0: 3718 adds r7, #24 8002cc2: 46bd mov sp, r7 8002cc4: bd80 pop {r7, pc} 8002cc6: bf00 nop 8002cc8: 40021000 .word 0x40021000 8002ccc: 40007000 .word 0x40007000 8002cd0: 42420440 .word 0x42420440 08002cd4 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) { 8002cd4: b580 push {r7, lr} 8002cd6: b082 sub sp, #8 8002cd8: af00 add r7, sp, #0 8002cda: 6078 str r0, [r7, #4] /* Check the UART handle allocation */ if (huart == NULL) 8002cdc: 687b ldr r3, [r7, #4] 8002cde: 2b00 cmp r3, #0 8002ce0: d101 bne.n 8002ce6 { return HAL_ERROR; 8002ce2: 2301 movs r3, #1 8002ce4: e03f b.n 8002d66 assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength)); #if defined(USART_CR1_OVER8) assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling)); #endif /* USART_CR1_OVER8 */ if (huart->gState == HAL_UART_STATE_RESET) 8002ce6: 687b ldr r3, [r7, #4] 8002ce8: f893 303d ldrb.w r3, [r3, #61] ; 0x3d 8002cec: b2db uxtb r3, r3 8002cee: 2b00 cmp r3, #0 8002cf0: d106 bne.n 8002d00 { /* Allocate lock resource and initialize it */ huart->Lock = HAL_UNLOCKED; 8002cf2: 687b ldr r3, [r7, #4] 8002cf4: 2200 movs r2, #0 8002cf6: f883 203c strb.w r2, [r3, #60] ; 0x3c /* Init the low level hardware */ huart->MspInitCallback(huart); #else /* Init the low level hardware : GPIO, CLOCK */ HAL_UART_MspInit(huart); 8002cfa: 6878 ldr r0, [r7, #4] 8002cfc: f7fe fc96 bl 800162c #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } huart->gState = HAL_UART_STATE_BUSY; 8002d00: 687b ldr r3, [r7, #4] 8002d02: 2224 movs r2, #36 ; 0x24 8002d04: f883 203d strb.w r2, [r3, #61] ; 0x3d /* Disable the peripheral */ __HAL_UART_DISABLE(huart); 8002d08: 687b ldr r3, [r7, #4] 8002d0a: 681b ldr r3, [r3, #0] 8002d0c: 68da ldr r2, [r3, #12] 8002d0e: 687b ldr r3, [r7, #4] 8002d10: 681b ldr r3, [r3, #0] 8002d12: f422 5200 bic.w r2, r2, #8192 ; 0x2000 8002d16: 60da str r2, [r3, #12] /* Set the UART Communication parameters */ UART_SetConfig(huart); 8002d18: 6878 ldr r0, [r7, #4] 8002d1a: f000 f905 bl 8002f28 /* In asynchronous mode, the following bits must be kept cleared: - LINEN and CLKEN bits in the USART_CR2 register, - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/ CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); 8002d1e: 687b ldr r3, [r7, #4] 8002d20: 681b ldr r3, [r3, #0] 8002d22: 691a ldr r2, [r3, #16] 8002d24: 687b ldr r3, [r7, #4] 8002d26: 681b ldr r3, [r3, #0] 8002d28: f422 4290 bic.w r2, r2, #18432 ; 0x4800 8002d2c: 611a str r2, [r3, #16] CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); 8002d2e: 687b ldr r3, [r7, #4] 8002d30: 681b ldr r3, [r3, #0] 8002d32: 695a ldr r2, [r3, #20] 8002d34: 687b ldr r3, [r7, #4] 8002d36: 681b ldr r3, [r3, #0] 8002d38: f022 022a bic.w r2, r2, #42 ; 0x2a 8002d3c: 615a str r2, [r3, #20] /* Enable the peripheral */ __HAL_UART_ENABLE(huart); 8002d3e: 687b ldr r3, [r7, #4] 8002d40: 681b ldr r3, [r3, #0] 8002d42: 68da ldr r2, [r3, #12] 8002d44: 687b ldr r3, [r7, #4] 8002d46: 681b ldr r3, [r3, #0] 8002d48: f442 5200 orr.w r2, r2, #8192 ; 0x2000 8002d4c: 60da str r2, [r3, #12] /* Initialize the UART state */ huart->ErrorCode = HAL_UART_ERROR_NONE; 8002d4e: 687b ldr r3, [r7, #4] 8002d50: 2200 movs r2, #0 8002d52: 641a str r2, [r3, #64] ; 0x40 huart->gState = HAL_UART_STATE_READY; 8002d54: 687b ldr r3, [r7, #4] 8002d56: 2220 movs r2, #32 8002d58: f883 203d strb.w r2, [r3, #61] ; 0x3d huart->RxState = HAL_UART_STATE_READY; 8002d5c: 687b ldr r3, [r7, #4] 8002d5e: 2220 movs r2, #32 8002d60: f883 203e strb.w r2, [r3, #62] ; 0x3e return HAL_OK; 8002d64: 2300 movs r3, #0 } 8002d66: 4618 mov r0, r3 8002d68: 3708 adds r7, #8 8002d6a: 46bd mov sp, r7 8002d6c: bd80 pop {r7, pc} 08002d6e : * @param Size Amount of data elements (u8 or u16) to be sent * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout) { 8002d6e: b580 push {r7, lr} 8002d70: b08a sub sp, #40 ; 0x28 8002d72: af02 add r7, sp, #8 8002d74: 60f8 str r0, [r7, #12] 8002d76: 60b9 str r1, [r7, #8] 8002d78: 603b str r3, [r7, #0] 8002d7a: 4613 mov r3, r2 8002d7c: 80fb strh r3, [r7, #6] uint8_t *pdata8bits; uint16_t *pdata16bits; uint32_t tickstart = 0U; 8002d7e: 2300 movs r3, #0 8002d80: 617b str r3, [r7, #20] /* Check that a Tx process is not already ongoing */ if (huart->gState == HAL_UART_STATE_READY) 8002d82: 68fb ldr r3, [r7, #12] 8002d84: f893 303d ldrb.w r3, [r3, #61] ; 0x3d 8002d88: b2db uxtb r3, r3 8002d8a: 2b20 cmp r3, #32 8002d8c: d17c bne.n 8002e88 { if ((pData == NULL) || (Size == 0U)) 8002d8e: 68bb ldr r3, [r7, #8] 8002d90: 2b00 cmp r3, #0 8002d92: d002 beq.n 8002d9a 8002d94: 88fb ldrh r3, [r7, #6] 8002d96: 2b00 cmp r3, #0 8002d98: d101 bne.n 8002d9e { return HAL_ERROR; 8002d9a: 2301 movs r3, #1 8002d9c: e075 b.n 8002e8a } /* Process Locked */ __HAL_LOCK(huart); 8002d9e: 68fb ldr r3, [r7, #12] 8002da0: f893 303c ldrb.w r3, [r3, #60] ; 0x3c 8002da4: 2b01 cmp r3, #1 8002da6: d101 bne.n 8002dac 8002da8: 2302 movs r3, #2 8002daa: e06e b.n 8002e8a 8002dac: 68fb ldr r3, [r7, #12] 8002dae: 2201 movs r2, #1 8002db0: f883 203c strb.w r2, [r3, #60] ; 0x3c huart->ErrorCode = HAL_UART_ERROR_NONE; 8002db4: 68fb ldr r3, [r7, #12] 8002db6: 2200 movs r2, #0 8002db8: 641a str r2, [r3, #64] ; 0x40 huart->gState = HAL_UART_STATE_BUSY_TX; 8002dba: 68fb ldr r3, [r7, #12] 8002dbc: 2221 movs r2, #33 ; 0x21 8002dbe: f883 203d strb.w r2, [r3, #61] ; 0x3d /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); 8002dc2: f7fe fcfb bl 80017bc 8002dc6: 6178 str r0, [r7, #20] huart->TxXferSize = Size; 8002dc8: 68fb ldr r3, [r7, #12] 8002dca: 88fa ldrh r2, [r7, #6] 8002dcc: 849a strh r2, [r3, #36] ; 0x24 huart->TxXferCount = Size; 8002dce: 68fb ldr r3, [r7, #12] 8002dd0: 88fa ldrh r2, [r7, #6] 8002dd2: 84da strh r2, [r3, #38] ; 0x26 /* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) 8002dd4: 68fb ldr r3, [r7, #12] 8002dd6: 689b ldr r3, [r3, #8] 8002dd8: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 8002ddc: d108 bne.n 8002df0 8002dde: 68fb ldr r3, [r7, #12] 8002de0: 691b ldr r3, [r3, #16] 8002de2: 2b00 cmp r3, #0 8002de4: d104 bne.n 8002df0 { pdata8bits = NULL; 8002de6: 2300 movs r3, #0 8002de8: 61fb str r3, [r7, #28] pdata16bits = (uint16_t *) pData; 8002dea: 68bb ldr r3, [r7, #8] 8002dec: 61bb str r3, [r7, #24] 8002dee: e003 b.n 8002df8 } else { pdata8bits = pData; 8002df0: 68bb ldr r3, [r7, #8] 8002df2: 61fb str r3, [r7, #28] pdata16bits = NULL; 8002df4: 2300 movs r3, #0 8002df6: 61bb str r3, [r7, #24] } /* Process Unlocked */ __HAL_UNLOCK(huart); 8002df8: 68fb ldr r3, [r7, #12] 8002dfa: 2200 movs r2, #0 8002dfc: f883 203c strb.w r2, [r3, #60] ; 0x3c while (huart->TxXferCount > 0U) 8002e00: e02a b.n 8002e58 { if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) 8002e02: 683b ldr r3, [r7, #0] 8002e04: 9300 str r3, [sp, #0] 8002e06: 697b ldr r3, [r7, #20] 8002e08: 2200 movs r2, #0 8002e0a: 2180 movs r1, #128 ; 0x80 8002e0c: 68f8 ldr r0, [r7, #12] 8002e0e: f000 f840 bl 8002e92 8002e12: 4603 mov r3, r0 8002e14: 2b00 cmp r3, #0 8002e16: d001 beq.n 8002e1c { return HAL_TIMEOUT; 8002e18: 2303 movs r3, #3 8002e1a: e036 b.n 8002e8a } if (pdata8bits == NULL) 8002e1c: 69fb ldr r3, [r7, #28] 8002e1e: 2b00 cmp r3, #0 8002e20: d10b bne.n 8002e3a { huart->Instance->DR = (uint16_t)(*pdata16bits & 0x01FFU); 8002e22: 69bb ldr r3, [r7, #24] 8002e24: 881b ldrh r3, [r3, #0] 8002e26: 461a mov r2, r3 8002e28: 68fb ldr r3, [r7, #12] 8002e2a: 681b ldr r3, [r3, #0] 8002e2c: f3c2 0208 ubfx r2, r2, #0, #9 8002e30: 605a str r2, [r3, #4] pdata16bits++; 8002e32: 69bb ldr r3, [r7, #24] 8002e34: 3302 adds r3, #2 8002e36: 61bb str r3, [r7, #24] 8002e38: e007 b.n 8002e4a } else { huart->Instance->DR = (uint8_t)(*pdata8bits & 0xFFU); 8002e3a: 69fb ldr r3, [r7, #28] 8002e3c: 781a ldrb r2, [r3, #0] 8002e3e: 68fb ldr r3, [r7, #12] 8002e40: 681b ldr r3, [r3, #0] 8002e42: 605a str r2, [r3, #4] pdata8bits++; 8002e44: 69fb ldr r3, [r7, #28] 8002e46: 3301 adds r3, #1 8002e48: 61fb str r3, [r7, #28] } huart->TxXferCount--; 8002e4a: 68fb ldr r3, [r7, #12] 8002e4c: 8cdb ldrh r3, [r3, #38] ; 0x26 8002e4e: b29b uxth r3, r3 8002e50: 3b01 subs r3, #1 8002e52: b29a uxth r2, r3 8002e54: 68fb ldr r3, [r7, #12] 8002e56: 84da strh r2, [r3, #38] ; 0x26 while (huart->TxXferCount > 0U) 8002e58: 68fb ldr r3, [r7, #12] 8002e5a: 8cdb ldrh r3, [r3, #38] ; 0x26 8002e5c: b29b uxth r3, r3 8002e5e: 2b00 cmp r3, #0 8002e60: d1cf bne.n 8002e02 } if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) 8002e62: 683b ldr r3, [r7, #0] 8002e64: 9300 str r3, [sp, #0] 8002e66: 697b ldr r3, [r7, #20] 8002e68: 2200 movs r2, #0 8002e6a: 2140 movs r1, #64 ; 0x40 8002e6c: 68f8 ldr r0, [r7, #12] 8002e6e: f000 f810 bl 8002e92 8002e72: 4603 mov r3, r0 8002e74: 2b00 cmp r3, #0 8002e76: d001 beq.n 8002e7c { return HAL_TIMEOUT; 8002e78: 2303 movs r3, #3 8002e7a: e006 b.n 8002e8a } /* At end of Tx process, restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; 8002e7c: 68fb ldr r3, [r7, #12] 8002e7e: 2220 movs r2, #32 8002e80: f883 203d strb.w r2, [r3, #61] ; 0x3d return HAL_OK; 8002e84: 2300 movs r3, #0 8002e86: e000 b.n 8002e8a } else { return HAL_BUSY; 8002e88: 2302 movs r3, #2 } } 8002e8a: 4618 mov r0, r3 8002e8c: 3720 adds r7, #32 8002e8e: 46bd mov sp, r7 8002e90: bd80 pop {r7, pc} 08002e92 : * @param Tickstart Tick start value * @param Timeout Timeout duration * @retval HAL status */ static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout) { 8002e92: b580 push {r7, lr} 8002e94: b084 sub sp, #16 8002e96: af00 add r7, sp, #0 8002e98: 60f8 str r0, [r7, #12] 8002e9a: 60b9 str r1, [r7, #8] 8002e9c: 603b str r3, [r7, #0] 8002e9e: 4613 mov r3, r2 8002ea0: 71fb strb r3, [r7, #7] /* Wait until flag is set */ while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) 8002ea2: e02c b.n 8002efe { /* Check for the Timeout */ if (Timeout != HAL_MAX_DELAY) 8002ea4: 69bb ldr r3, [r7, #24] 8002ea6: f1b3 3fff cmp.w r3, #4294967295 8002eaa: d028 beq.n 8002efe { if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout)) 8002eac: 69bb ldr r3, [r7, #24] 8002eae: 2b00 cmp r3, #0 8002eb0: d007 beq.n 8002ec2 8002eb2: f7fe fc83 bl 80017bc 8002eb6: 4602 mov r2, r0 8002eb8: 683b ldr r3, [r7, #0] 8002eba: 1ad3 subs r3, r2, r3 8002ebc: 69ba ldr r2, [r7, #24] 8002ebe: 429a cmp r2, r3 8002ec0: d21d bcs.n 8002efe { /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE)); 8002ec2: 68fb ldr r3, [r7, #12] 8002ec4: 681b ldr r3, [r3, #0] 8002ec6: 68da ldr r2, [r3, #12] 8002ec8: 68fb ldr r3, [r7, #12] 8002eca: 681b ldr r3, [r3, #0] 8002ecc: f422 72d0 bic.w r2, r2, #416 ; 0x1a0 8002ed0: 60da str r2, [r3, #12] CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 8002ed2: 68fb ldr r3, [r7, #12] 8002ed4: 681b ldr r3, [r3, #0] 8002ed6: 695a ldr r2, [r3, #20] 8002ed8: 68fb ldr r3, [r7, #12] 8002eda: 681b ldr r3, [r3, #0] 8002edc: f022 0201 bic.w r2, r2, #1 8002ee0: 615a str r2, [r3, #20] huart->gState = HAL_UART_STATE_READY; 8002ee2: 68fb ldr r3, [r7, #12] 8002ee4: 2220 movs r2, #32 8002ee6: f883 203d strb.w r2, [r3, #61] ; 0x3d huart->RxState = HAL_UART_STATE_READY; 8002eea: 68fb ldr r3, [r7, #12] 8002eec: 2220 movs r2, #32 8002eee: f883 203e strb.w r2, [r3, #62] ; 0x3e /* Process Unlocked */ __HAL_UNLOCK(huart); 8002ef2: 68fb ldr r3, [r7, #12] 8002ef4: 2200 movs r2, #0 8002ef6: f883 203c strb.w r2, [r3, #60] ; 0x3c return HAL_TIMEOUT; 8002efa: 2303 movs r3, #3 8002efc: e00f b.n 8002f1e while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) 8002efe: 68fb ldr r3, [r7, #12] 8002f00: 681b ldr r3, [r3, #0] 8002f02: 681a ldr r2, [r3, #0] 8002f04: 68bb ldr r3, [r7, #8] 8002f06: 4013 ands r3, r2 8002f08: 68ba ldr r2, [r7, #8] 8002f0a: 429a cmp r2, r3 8002f0c: bf0c ite eq 8002f0e: 2301 moveq r3, #1 8002f10: 2300 movne r3, #0 8002f12: b2db uxtb r3, r3 8002f14: 461a mov r2, r3 8002f16: 79fb ldrb r3, [r7, #7] 8002f18: 429a cmp r2, r3 8002f1a: d0c3 beq.n 8002ea4 } } } return HAL_OK; 8002f1c: 2300 movs r3, #0 } 8002f1e: 4618 mov r0, r3 8002f20: 3710 adds r7, #16 8002f22: 46bd mov sp, r7 8002f24: bd80 pop {r7, pc} ... 08002f28 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ static void UART_SetConfig(UART_HandleTypeDef *huart) { 8002f28: b580 push {r7, lr} 8002f2a: b084 sub sp, #16 8002f2c: af00 add r7, sp, #0 8002f2e: 6078 str r0, [r7, #4] assert_param(IS_UART_MODE(huart->Init.Mode)); /*-------------------------- USART CR2 Configuration -----------------------*/ /* Configure the UART Stop Bits: Set STOP[13:12] bits according to huart->Init.StopBits value */ MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits); 8002f30: 687b ldr r3, [r7, #4] 8002f32: 681b ldr r3, [r3, #0] 8002f34: 691b ldr r3, [r3, #16] 8002f36: f423 5140 bic.w r1, r3, #12288 ; 0x3000 8002f3a: 687b ldr r3, [r7, #4] 8002f3c: 68da ldr r2, [r3, #12] 8002f3e: 687b ldr r3, [r7, #4] 8002f40: 681b ldr r3, [r3, #0] 8002f42: 430a orrs r2, r1 8002f44: 611a str r2, [r3, #16] tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling; MODIFY_REG(huart->Instance->CR1, (uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8), tmpreg); #else tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode; 8002f46: 687b ldr r3, [r7, #4] 8002f48: 689a ldr r2, [r3, #8] 8002f4a: 687b ldr r3, [r7, #4] 8002f4c: 691b ldr r3, [r3, #16] 8002f4e: 431a orrs r2, r3 8002f50: 687b ldr r3, [r7, #4] 8002f52: 695b ldr r3, [r3, #20] 8002f54: 4313 orrs r3, r2 8002f56: 60bb str r3, [r7, #8] MODIFY_REG(huart->Instance->CR1, 8002f58: 687b ldr r3, [r7, #4] 8002f5a: 681b ldr r3, [r3, #0] 8002f5c: 68db ldr r3, [r3, #12] 8002f5e: f423 53b0 bic.w r3, r3, #5632 ; 0x1600 8002f62: f023 030c bic.w r3, r3, #12 8002f66: 687a ldr r2, [r7, #4] 8002f68: 6812 ldr r2, [r2, #0] 8002f6a: 68b9 ldr r1, [r7, #8] 8002f6c: 430b orrs r3, r1 8002f6e: 60d3 str r3, [r2, #12] tmpreg); #endif /* USART_CR1_OVER8 */ /*-------------------------- USART CR3 Configuration -----------------------*/ /* Configure the UART HFC: Set CTSE and RTSE bits according to huart->Init.HwFlowCtl value */ MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE), huart->Init.HwFlowCtl); 8002f70: 687b ldr r3, [r7, #4] 8002f72: 681b ldr r3, [r3, #0] 8002f74: 695b ldr r3, [r3, #20] 8002f76: f423 7140 bic.w r1, r3, #768 ; 0x300 8002f7a: 687b ldr r3, [r7, #4] 8002f7c: 699a ldr r2, [r3, #24] 8002f7e: 687b ldr r3, [r7, #4] 8002f80: 681b ldr r3, [r3, #0] 8002f82: 430a orrs r2, r1 8002f84: 615a str r2, [r3, #20] if(huart->Instance == USART1) 8002f86: 687b ldr r3, [r7, #4] 8002f88: 681b ldr r3, [r3, #0] 8002f8a: 4a2c ldr r2, [pc, #176] ; (800303c ) 8002f8c: 4293 cmp r3, r2 8002f8e: d103 bne.n 8002f98 { pclk = HAL_RCC_GetPCLK2Freq(); 8002f90: f7ff fdb8 bl 8002b04 8002f94: 60f8 str r0, [r7, #12] 8002f96: e002 b.n 8002f9e } else { pclk = HAL_RCC_GetPCLK1Freq(); 8002f98: f7ff fda0 bl 8002adc 8002f9c: 60f8 str r0, [r7, #12] else { huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate); } #else huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate); 8002f9e: 68fa ldr r2, [r7, #12] 8002fa0: 4613 mov r3, r2 8002fa2: 009b lsls r3, r3, #2 8002fa4: 4413 add r3, r2 8002fa6: 009a lsls r2, r3, #2 8002fa8: 441a add r2, r3 8002faa: 687b ldr r3, [r7, #4] 8002fac: 685b ldr r3, [r3, #4] 8002fae: 009b lsls r3, r3, #2 8002fb0: fbb2 f3f3 udiv r3, r2, r3 8002fb4: 4a22 ldr r2, [pc, #136] ; (8003040 ) 8002fb6: fba2 2303 umull r2, r3, r2, r3 8002fba: 095b lsrs r3, r3, #5 8002fbc: 0119 lsls r1, r3, #4 8002fbe: 68fa ldr r2, [r7, #12] 8002fc0: 4613 mov r3, r2 8002fc2: 009b lsls r3, r3, #2 8002fc4: 4413 add r3, r2 8002fc6: 009a lsls r2, r3, #2 8002fc8: 441a add r2, r3 8002fca: 687b ldr r3, [r7, #4] 8002fcc: 685b ldr r3, [r3, #4] 8002fce: 009b lsls r3, r3, #2 8002fd0: fbb2 f2f3 udiv r2, r2, r3 8002fd4: 4b1a ldr r3, [pc, #104] ; (8003040 ) 8002fd6: fba3 0302 umull r0, r3, r3, r2 8002fda: 095b lsrs r3, r3, #5 8002fdc: 2064 movs r0, #100 ; 0x64 8002fde: fb00 f303 mul.w r3, r0, r3 8002fe2: 1ad3 subs r3, r2, r3 8002fe4: 011b lsls r3, r3, #4 8002fe6: 3332 adds r3, #50 ; 0x32 8002fe8: 4a15 ldr r2, [pc, #84] ; (8003040 ) 8002fea: fba2 2303 umull r2, r3, r2, r3 8002fee: 095b lsrs r3, r3, #5 8002ff0: f003 03f0 and.w r3, r3, #240 ; 0xf0 8002ff4: 4419 add r1, r3 8002ff6: 68fa ldr r2, [r7, #12] 8002ff8: 4613 mov r3, r2 8002ffa: 009b lsls r3, r3, #2 8002ffc: 4413 add r3, r2 8002ffe: 009a lsls r2, r3, #2 8003000: 441a add r2, r3 8003002: 687b ldr r3, [r7, #4] 8003004: 685b ldr r3, [r3, #4] 8003006: 009b lsls r3, r3, #2 8003008: fbb2 f2f3 udiv r2, r2, r3 800300c: 4b0c ldr r3, [pc, #48] ; (8003040 ) 800300e: fba3 0302 umull r0, r3, r3, r2 8003012: 095b lsrs r3, r3, #5 8003014: 2064 movs r0, #100 ; 0x64 8003016: fb00 f303 mul.w r3, r0, r3 800301a: 1ad3 subs r3, r2, r3 800301c: 011b lsls r3, r3, #4 800301e: 3332 adds r3, #50 ; 0x32 8003020: 4a07 ldr r2, [pc, #28] ; (8003040 ) 8003022: fba2 2303 umull r2, r3, r2, r3 8003026: 095b lsrs r3, r3, #5 8003028: f003 020f and.w r2, r3, #15 800302c: 687b ldr r3, [r7, #4] 800302e: 681b ldr r3, [r3, #0] 8003030: 440a add r2, r1 8003032: 609a str r2, [r3, #8] #endif /* USART_CR1_OVER8 */ } 8003034: bf00 nop 8003036: 3710 adds r7, #16 8003038: 46bd mov sp, r7 800303a: bd80 pop {r7, pc} 800303c: 40013800 .word 0x40013800 8003040: 51eb851f .word 0x51eb851f 08003044 <__errno>: 8003044: 4b01 ldr r3, [pc, #4] ; (800304c <__errno+0x8>) 8003046: 6818 ldr r0, [r3, #0] 8003048: 4770 bx lr 800304a: bf00 nop 800304c: 2000000c .word 0x2000000c 08003050 <__libc_init_array>: 8003050: b570 push {r4, r5, r6, lr} 8003052: 2600 movs r6, #0 8003054: 4d0c ldr r5, [pc, #48] ; (8003088 <__libc_init_array+0x38>) 8003056: 4c0d ldr r4, [pc, #52] ; (800308c <__libc_init_array+0x3c>) 8003058: 1b64 subs r4, r4, r5 800305a: 10a4 asrs r4, r4, #2 800305c: 42a6 cmp r6, r4 800305e: d109 bne.n 8003074 <__libc_init_array+0x24> 8003060: f003 f8e6 bl 8006230 <_init> 8003064: 2600 movs r6, #0 8003066: 4d0a ldr r5, [pc, #40] ; (8003090 <__libc_init_array+0x40>) 8003068: 4c0a ldr r4, [pc, #40] ; (8003094 <__libc_init_array+0x44>) 800306a: 1b64 subs r4, r4, r5 800306c: 10a4 asrs r4, r4, #2 800306e: 42a6 cmp r6, r4 8003070: d105 bne.n 800307e <__libc_init_array+0x2e> 8003072: bd70 pop {r4, r5, r6, pc} 8003074: f855 3b04 ldr.w r3, [r5], #4 8003078: 4798 blx r3 800307a: 3601 adds r6, #1 800307c: e7ee b.n 800305c <__libc_init_array+0xc> 800307e: f855 3b04 ldr.w r3, [r5], #4 8003082: 4798 blx r3 8003084: 3601 adds r6, #1 8003086: e7f2 b.n 800306e <__libc_init_array+0x1e> 8003088: 08006654 .word 0x08006654 800308c: 08006654 .word 0x08006654 8003090: 08006654 .word 0x08006654 8003094: 08006658 .word 0x08006658 08003098 : 8003098: 4603 mov r3, r0 800309a: 4402 add r2, r0 800309c: 4293 cmp r3, r2 800309e: d100 bne.n 80030a2 80030a0: 4770 bx lr 80030a2: f803 1b01 strb.w r1, [r3], #1 80030a6: e7f9 b.n 800309c 080030a8 <__cvt>: 80030a8: 2b00 cmp r3, #0 80030aa: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 80030ae: 461f mov r7, r3 80030b0: bfbb ittet lt 80030b2: f103 4300 addlt.w r3, r3, #2147483648 ; 0x80000000 80030b6: 461f movlt r7, r3 80030b8: 2300 movge r3, #0 80030ba: 232d movlt r3, #45 ; 0x2d 80030bc: b088 sub sp, #32 80030be: 4614 mov r4, r2 80030c0: 9a12 ldr r2, [sp, #72] ; 0x48 80030c2: 9d10 ldr r5, [sp, #64] ; 0x40 80030c4: 7013 strb r3, [r2, #0] 80030c6: 9b14 ldr r3, [sp, #80] ; 0x50 80030c8: f8dd a04c ldr.w sl, [sp, #76] ; 0x4c 80030cc: f023 0820 bic.w r8, r3, #32 80030d0: f1b8 0f46 cmp.w r8, #70 ; 0x46 80030d4: d005 beq.n 80030e2 <__cvt+0x3a> 80030d6: f1b8 0f45 cmp.w r8, #69 ; 0x45 80030da: d100 bne.n 80030de <__cvt+0x36> 80030dc: 3501 adds r5, #1 80030de: 2302 movs r3, #2 80030e0: e000 b.n 80030e4 <__cvt+0x3c> 80030e2: 2303 movs r3, #3 80030e4: aa07 add r2, sp, #28 80030e6: 9204 str r2, [sp, #16] 80030e8: aa06 add r2, sp, #24 80030ea: e9cd a202 strd sl, r2, [sp, #8] 80030ee: e9cd 3500 strd r3, r5, [sp] 80030f2: 4622 mov r2, r4 80030f4: 463b mov r3, r7 80030f6: f000 fce3 bl 8003ac0 <_dtoa_r> 80030fa: f1b8 0f47 cmp.w r8, #71 ; 0x47 80030fe: 4606 mov r6, r0 8003100: d102 bne.n 8003108 <__cvt+0x60> 8003102: 9b11 ldr r3, [sp, #68] ; 0x44 8003104: 07db lsls r3, r3, #31 8003106: d522 bpl.n 800314e <__cvt+0xa6> 8003108: f1b8 0f46 cmp.w r8, #70 ; 0x46 800310c: eb06 0905 add.w r9, r6, r5 8003110: d110 bne.n 8003134 <__cvt+0x8c> 8003112: 7833 ldrb r3, [r6, #0] 8003114: 2b30 cmp r3, #48 ; 0x30 8003116: d10a bne.n 800312e <__cvt+0x86> 8003118: 2200 movs r2, #0 800311a: 2300 movs r3, #0 800311c: 4620 mov r0, r4 800311e: 4639 mov r1, r7 8003120: f7fd fc42 bl 80009a8 <__aeabi_dcmpeq> 8003124: b918 cbnz r0, 800312e <__cvt+0x86> 8003126: f1c5 0501 rsb r5, r5, #1 800312a: f8ca 5000 str.w r5, [sl] 800312e: f8da 3000 ldr.w r3, [sl] 8003132: 4499 add r9, r3 8003134: 2200 movs r2, #0 8003136: 2300 movs r3, #0 8003138: 4620 mov r0, r4 800313a: 4639 mov r1, r7 800313c: f7fd fc34 bl 80009a8 <__aeabi_dcmpeq> 8003140: b108 cbz r0, 8003146 <__cvt+0x9e> 8003142: f8cd 901c str.w r9, [sp, #28] 8003146: 2230 movs r2, #48 ; 0x30 8003148: 9b07 ldr r3, [sp, #28] 800314a: 454b cmp r3, r9 800314c: d307 bcc.n 800315e <__cvt+0xb6> 800314e: 4630 mov r0, r6 8003150: 9b07 ldr r3, [sp, #28] 8003152: 9a15 ldr r2, [sp, #84] ; 0x54 8003154: 1b9b subs r3, r3, r6 8003156: 6013 str r3, [r2, #0] 8003158: b008 add sp, #32 800315a: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 800315e: 1c59 adds r1, r3, #1 8003160: 9107 str r1, [sp, #28] 8003162: 701a strb r2, [r3, #0] 8003164: e7f0 b.n 8003148 <__cvt+0xa0> 08003166 <__exponent>: 8003166: 4603 mov r3, r0 8003168: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr} 800316a: 2900 cmp r1, #0 800316c: f803 2b02 strb.w r2, [r3], #2 8003170: bfb6 itet lt 8003172: 222d movlt r2, #45 ; 0x2d 8003174: 222b movge r2, #43 ; 0x2b 8003176: 4249 neglt r1, r1 8003178: 2909 cmp r1, #9 800317a: 7042 strb r2, [r0, #1] 800317c: dd2b ble.n 80031d6 <__exponent+0x70> 800317e: f10d 0407 add.w r4, sp, #7 8003182: 46a4 mov ip, r4 8003184: 270a movs r7, #10 8003186: fb91 f6f7 sdiv r6, r1, r7 800318a: 460a mov r2, r1 800318c: 46a6 mov lr, r4 800318e: fb07 1516 mls r5, r7, r6, r1 8003192: 2a63 cmp r2, #99 ; 0x63 8003194: f105 0530 add.w r5, r5, #48 ; 0x30 8003198: 4631 mov r1, r6 800319a: f104 34ff add.w r4, r4, #4294967295 800319e: f80e 5c01 strb.w r5, [lr, #-1] 80031a2: dcf0 bgt.n 8003186 <__exponent+0x20> 80031a4: 3130 adds r1, #48 ; 0x30 80031a6: f1ae 0502 sub.w r5, lr, #2 80031aa: f804 1c01 strb.w r1, [r4, #-1] 80031ae: 4629 mov r1, r5 80031b0: 1c44 adds r4, r0, #1 80031b2: 4561 cmp r1, ip 80031b4: d30a bcc.n 80031cc <__exponent+0x66> 80031b6: f10d 0209 add.w r2, sp, #9 80031ba: eba2 020e sub.w r2, r2, lr 80031be: 4565 cmp r5, ip 80031c0: bf88 it hi 80031c2: 2200 movhi r2, #0 80031c4: 4413 add r3, r2 80031c6: 1a18 subs r0, r3, r0 80031c8: b003 add sp, #12 80031ca: bdf0 pop {r4, r5, r6, r7, pc} 80031cc: f811 2b01 ldrb.w r2, [r1], #1 80031d0: f804 2f01 strb.w r2, [r4, #1]! 80031d4: e7ed b.n 80031b2 <__exponent+0x4c> 80031d6: 2330 movs r3, #48 ; 0x30 80031d8: 3130 adds r1, #48 ; 0x30 80031da: 7083 strb r3, [r0, #2] 80031dc: 70c1 strb r1, [r0, #3] 80031de: 1d03 adds r3, r0, #4 80031e0: e7f1 b.n 80031c6 <__exponent+0x60> ... 080031e4 <_printf_float>: 80031e4: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 80031e8: b091 sub sp, #68 ; 0x44 80031ea: 460c mov r4, r1 80031ec: f8dd 8068 ldr.w r8, [sp, #104] ; 0x68 80031f0: 4616 mov r6, r2 80031f2: 461f mov r7, r3 80031f4: 4605 mov r5, r0 80031f6: f001 fa51 bl 800469c <_localeconv_r> 80031fa: 6803 ldr r3, [r0, #0] 80031fc: 4618 mov r0, r3 80031fe: 9309 str r3, [sp, #36] ; 0x24 8003200: f7fc ffa6 bl 8000150 8003204: 2300 movs r3, #0 8003206: 930e str r3, [sp, #56] ; 0x38 8003208: f8d8 3000 ldr.w r3, [r8] 800320c: 900a str r0, [sp, #40] ; 0x28 800320e: 3307 adds r3, #7 8003210: f023 0307 bic.w r3, r3, #7 8003214: f103 0208 add.w r2, r3, #8 8003218: f894 9018 ldrb.w r9, [r4, #24] 800321c: f8d4 b000 ldr.w fp, [r4] 8003220: f8c8 2000 str.w r2, [r8] 8003224: e9d3 2300 ldrd r2, r3, [r3] 8003228: e9c4 2312 strd r2, r3, [r4, #72] ; 0x48 800322c: e9d4 8a12 ldrd r8, sl, [r4, #72] ; 0x48 8003230: f02a 4300 bic.w r3, sl, #2147483648 ; 0x80000000 8003234: 930b str r3, [sp, #44] ; 0x2c 8003236: f04f 32ff mov.w r2, #4294967295 800323a: 4640 mov r0, r8 800323c: 4b9c ldr r3, [pc, #624] ; (80034b0 <_printf_float+0x2cc>) 800323e: 990b ldr r1, [sp, #44] ; 0x2c 8003240: f7fd fbe4 bl 8000a0c <__aeabi_dcmpun> 8003244: bb70 cbnz r0, 80032a4 <_printf_float+0xc0> 8003246: f04f 32ff mov.w r2, #4294967295 800324a: 4640 mov r0, r8 800324c: 4b98 ldr r3, [pc, #608] ; (80034b0 <_printf_float+0x2cc>) 800324e: 990b ldr r1, [sp, #44] ; 0x2c 8003250: f7fd fbbe bl 80009d0 <__aeabi_dcmple> 8003254: bb30 cbnz r0, 80032a4 <_printf_float+0xc0> 8003256: 2200 movs r2, #0 8003258: 2300 movs r3, #0 800325a: 4640 mov r0, r8 800325c: 4651 mov r1, sl 800325e: f7fd fbad bl 80009bc <__aeabi_dcmplt> 8003262: b110 cbz r0, 800326a <_printf_float+0x86> 8003264: 232d movs r3, #45 ; 0x2d 8003266: f884 3043 strb.w r3, [r4, #67] ; 0x43 800326a: 4b92 ldr r3, [pc, #584] ; (80034b4 <_printf_float+0x2d0>) 800326c: 4892 ldr r0, [pc, #584] ; (80034b8 <_printf_float+0x2d4>) 800326e: f1b9 0f47 cmp.w r9, #71 ; 0x47 8003272: bf94 ite ls 8003274: 4698 movls r8, r3 8003276: 4680 movhi r8, r0 8003278: 2303 movs r3, #3 800327a: f04f 0a00 mov.w sl, #0 800327e: 6123 str r3, [r4, #16] 8003280: f02b 0304 bic.w r3, fp, #4 8003284: 6023 str r3, [r4, #0] 8003286: 4633 mov r3, r6 8003288: 4621 mov r1, r4 800328a: 4628 mov r0, r5 800328c: 9700 str r7, [sp, #0] 800328e: aa0f add r2, sp, #60 ; 0x3c 8003290: f000 f9d4 bl 800363c <_printf_common> 8003294: 3001 adds r0, #1 8003296: f040 8090 bne.w 80033ba <_printf_float+0x1d6> 800329a: f04f 30ff mov.w r0, #4294967295 800329e: b011 add sp, #68 ; 0x44 80032a0: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 80032a4: 4642 mov r2, r8 80032a6: 4653 mov r3, sl 80032a8: 4640 mov r0, r8 80032aa: 4651 mov r1, sl 80032ac: f7fd fbae bl 8000a0c <__aeabi_dcmpun> 80032b0: b148 cbz r0, 80032c6 <_printf_float+0xe2> 80032b2: f1ba 0f00 cmp.w sl, #0 80032b6: bfb8 it lt 80032b8: 232d movlt r3, #45 ; 0x2d 80032ba: 4880 ldr r0, [pc, #512] ; (80034bc <_printf_float+0x2d8>) 80032bc: bfb8 it lt 80032be: f884 3043 strblt.w r3, [r4, #67] ; 0x43 80032c2: 4b7f ldr r3, [pc, #508] ; (80034c0 <_printf_float+0x2dc>) 80032c4: e7d3 b.n 800326e <_printf_float+0x8a> 80032c6: 6863 ldr r3, [r4, #4] 80032c8: f009 01df and.w r1, r9, #223 ; 0xdf 80032cc: 1c5a adds r2, r3, #1 80032ce: d142 bne.n 8003356 <_printf_float+0x172> 80032d0: 2306 movs r3, #6 80032d2: 6063 str r3, [r4, #4] 80032d4: 2200 movs r2, #0 80032d6: 9206 str r2, [sp, #24] 80032d8: aa0e add r2, sp, #56 ; 0x38 80032da: e9cd 9204 strd r9, r2, [sp, #16] 80032de: aa0d add r2, sp, #52 ; 0x34 80032e0: f44b 6380 orr.w r3, fp, #1024 ; 0x400 80032e4: 9203 str r2, [sp, #12] 80032e6: f10d 0233 add.w r2, sp, #51 ; 0x33 80032ea: e9cd 3201 strd r3, r2, [sp, #4] 80032ee: 6023 str r3, [r4, #0] 80032f0: 6863 ldr r3, [r4, #4] 80032f2: 4642 mov r2, r8 80032f4: 9300 str r3, [sp, #0] 80032f6: 4628 mov r0, r5 80032f8: 4653 mov r3, sl 80032fa: 910b str r1, [sp, #44] ; 0x2c 80032fc: f7ff fed4 bl 80030a8 <__cvt> 8003300: 990b ldr r1, [sp, #44] ; 0x2c 8003302: 4680 mov r8, r0 8003304: 2947 cmp r1, #71 ; 0x47 8003306: 990d ldr r1, [sp, #52] ; 0x34 8003308: d108 bne.n 800331c <_printf_float+0x138> 800330a: 1cc8 adds r0, r1, #3 800330c: db02 blt.n 8003314 <_printf_float+0x130> 800330e: 6863 ldr r3, [r4, #4] 8003310: 4299 cmp r1, r3 8003312: dd40 ble.n 8003396 <_printf_float+0x1b2> 8003314: f1a9 0902 sub.w r9, r9, #2 8003318: fa5f f989 uxtb.w r9, r9 800331c: f1b9 0f65 cmp.w r9, #101 ; 0x65 8003320: d81f bhi.n 8003362 <_printf_float+0x17e> 8003322: 464a mov r2, r9 8003324: 3901 subs r1, #1 8003326: f104 0050 add.w r0, r4, #80 ; 0x50 800332a: 910d str r1, [sp, #52] ; 0x34 800332c: f7ff ff1b bl 8003166 <__exponent> 8003330: 9a0e ldr r2, [sp, #56] ; 0x38 8003332: 4682 mov sl, r0 8003334: 1813 adds r3, r2, r0 8003336: 2a01 cmp r2, #1 8003338: 6123 str r3, [r4, #16] 800333a: dc02 bgt.n 8003342 <_printf_float+0x15e> 800333c: 6822 ldr r2, [r4, #0] 800333e: 07d2 lsls r2, r2, #31 8003340: d501 bpl.n 8003346 <_printf_float+0x162> 8003342: 3301 adds r3, #1 8003344: 6123 str r3, [r4, #16] 8003346: f89d 3033 ldrb.w r3, [sp, #51] ; 0x33 800334a: 2b00 cmp r3, #0 800334c: d09b beq.n 8003286 <_printf_float+0xa2> 800334e: 232d movs r3, #45 ; 0x2d 8003350: f884 3043 strb.w r3, [r4, #67] ; 0x43 8003354: e797 b.n 8003286 <_printf_float+0xa2> 8003356: 2947 cmp r1, #71 ; 0x47 8003358: d1bc bne.n 80032d4 <_printf_float+0xf0> 800335a: 2b00 cmp r3, #0 800335c: d1ba bne.n 80032d4 <_printf_float+0xf0> 800335e: 2301 movs r3, #1 8003360: e7b7 b.n 80032d2 <_printf_float+0xee> 8003362: f1b9 0f66 cmp.w r9, #102 ; 0x66 8003366: d118 bne.n 800339a <_printf_float+0x1b6> 8003368: 2900 cmp r1, #0 800336a: 6863 ldr r3, [r4, #4] 800336c: dd0b ble.n 8003386 <_printf_float+0x1a2> 800336e: 6121 str r1, [r4, #16] 8003370: b913 cbnz r3, 8003378 <_printf_float+0x194> 8003372: 6822 ldr r2, [r4, #0] 8003374: 07d0 lsls r0, r2, #31 8003376: d502 bpl.n 800337e <_printf_float+0x19a> 8003378: 3301 adds r3, #1 800337a: 440b add r3, r1 800337c: 6123 str r3, [r4, #16] 800337e: f04f 0a00 mov.w sl, #0 8003382: 65a1 str r1, [r4, #88] ; 0x58 8003384: e7df b.n 8003346 <_printf_float+0x162> 8003386: b913 cbnz r3, 800338e <_printf_float+0x1aa> 8003388: 6822 ldr r2, [r4, #0] 800338a: 07d2 lsls r2, r2, #31 800338c: d501 bpl.n 8003392 <_printf_float+0x1ae> 800338e: 3302 adds r3, #2 8003390: e7f4 b.n 800337c <_printf_float+0x198> 8003392: 2301 movs r3, #1 8003394: e7f2 b.n 800337c <_printf_float+0x198> 8003396: f04f 0967 mov.w r9, #103 ; 0x67 800339a: 9b0e ldr r3, [sp, #56] ; 0x38 800339c: 4299 cmp r1, r3 800339e: db05 blt.n 80033ac <_printf_float+0x1c8> 80033a0: 6823 ldr r3, [r4, #0] 80033a2: 6121 str r1, [r4, #16] 80033a4: 07d8 lsls r0, r3, #31 80033a6: d5ea bpl.n 800337e <_printf_float+0x19a> 80033a8: 1c4b adds r3, r1, #1 80033aa: e7e7 b.n 800337c <_printf_float+0x198> 80033ac: 2900 cmp r1, #0 80033ae: bfcc ite gt 80033b0: 2201 movgt r2, #1 80033b2: f1c1 0202 rsble r2, r1, #2 80033b6: 4413 add r3, r2 80033b8: e7e0 b.n 800337c <_printf_float+0x198> 80033ba: 6823 ldr r3, [r4, #0] 80033bc: 055a lsls r2, r3, #21 80033be: d407 bmi.n 80033d0 <_printf_float+0x1ec> 80033c0: 6923 ldr r3, [r4, #16] 80033c2: 4642 mov r2, r8 80033c4: 4631 mov r1, r6 80033c6: 4628 mov r0, r5 80033c8: 47b8 blx r7 80033ca: 3001 adds r0, #1 80033cc: d12b bne.n 8003426 <_printf_float+0x242> 80033ce: e764 b.n 800329a <_printf_float+0xb6> 80033d0: f1b9 0f65 cmp.w r9, #101 ; 0x65 80033d4: f240 80dd bls.w 8003592 <_printf_float+0x3ae> 80033d8: e9d4 0112 ldrd r0, r1, [r4, #72] ; 0x48 80033dc: 2200 movs r2, #0 80033de: 2300 movs r3, #0 80033e0: f7fd fae2 bl 80009a8 <__aeabi_dcmpeq> 80033e4: 2800 cmp r0, #0 80033e6: d033 beq.n 8003450 <_printf_float+0x26c> 80033e8: 2301 movs r3, #1 80033ea: 4631 mov r1, r6 80033ec: 4628 mov r0, r5 80033ee: 4a35 ldr r2, [pc, #212] ; (80034c4 <_printf_float+0x2e0>) 80033f0: 47b8 blx r7 80033f2: 3001 adds r0, #1 80033f4: f43f af51 beq.w 800329a <_printf_float+0xb6> 80033f8: e9dd 230d ldrd r2, r3, [sp, #52] ; 0x34 80033fc: 429a cmp r2, r3 80033fe: db02 blt.n 8003406 <_printf_float+0x222> 8003400: 6823 ldr r3, [r4, #0] 8003402: 07d8 lsls r0, r3, #31 8003404: d50f bpl.n 8003426 <_printf_float+0x242> 8003406: e9dd 2309 ldrd r2, r3, [sp, #36] ; 0x24 800340a: 4631 mov r1, r6 800340c: 4628 mov r0, r5 800340e: 47b8 blx r7 8003410: 3001 adds r0, #1 8003412: f43f af42 beq.w 800329a <_printf_float+0xb6> 8003416: f04f 0800 mov.w r8, #0 800341a: f104 091a add.w r9, r4, #26 800341e: 9b0e ldr r3, [sp, #56] ; 0x38 8003420: 3b01 subs r3, #1 8003422: 4543 cmp r3, r8 8003424: dc09 bgt.n 800343a <_printf_float+0x256> 8003426: 6823 ldr r3, [r4, #0] 8003428: 079b lsls r3, r3, #30 800342a: f100 8102 bmi.w 8003632 <_printf_float+0x44e> 800342e: 68e0 ldr r0, [r4, #12] 8003430: 9b0f ldr r3, [sp, #60] ; 0x3c 8003432: 4298 cmp r0, r3 8003434: bfb8 it lt 8003436: 4618 movlt r0, r3 8003438: e731 b.n 800329e <_printf_float+0xba> 800343a: 2301 movs r3, #1 800343c: 464a mov r2, r9 800343e: 4631 mov r1, r6 8003440: 4628 mov r0, r5 8003442: 47b8 blx r7 8003444: 3001 adds r0, #1 8003446: f43f af28 beq.w 800329a <_printf_float+0xb6> 800344a: f108 0801 add.w r8, r8, #1 800344e: e7e6 b.n 800341e <_printf_float+0x23a> 8003450: 9b0d ldr r3, [sp, #52] ; 0x34 8003452: 2b00 cmp r3, #0 8003454: dc38 bgt.n 80034c8 <_printf_float+0x2e4> 8003456: 2301 movs r3, #1 8003458: 4631 mov r1, r6 800345a: 4628 mov r0, r5 800345c: 4a19 ldr r2, [pc, #100] ; (80034c4 <_printf_float+0x2e0>) 800345e: 47b8 blx r7 8003460: 3001 adds r0, #1 8003462: f43f af1a beq.w 800329a <_printf_float+0xb6> 8003466: e9dd 230d ldrd r2, r3, [sp, #52] ; 0x34 800346a: 4313 orrs r3, r2 800346c: d102 bne.n 8003474 <_printf_float+0x290> 800346e: 6823 ldr r3, [r4, #0] 8003470: 07d9 lsls r1, r3, #31 8003472: d5d8 bpl.n 8003426 <_printf_float+0x242> 8003474: e9dd 2309 ldrd r2, r3, [sp, #36] ; 0x24 8003478: 4631 mov r1, r6 800347a: 4628 mov r0, r5 800347c: 47b8 blx r7 800347e: 3001 adds r0, #1 8003480: f43f af0b beq.w 800329a <_printf_float+0xb6> 8003484: f04f 0900 mov.w r9, #0 8003488: f104 0a1a add.w sl, r4, #26 800348c: 9b0d ldr r3, [sp, #52] ; 0x34 800348e: 425b negs r3, r3 8003490: 454b cmp r3, r9 8003492: dc01 bgt.n 8003498 <_printf_float+0x2b4> 8003494: 9b0e ldr r3, [sp, #56] ; 0x38 8003496: e794 b.n 80033c2 <_printf_float+0x1de> 8003498: 2301 movs r3, #1 800349a: 4652 mov r2, sl 800349c: 4631 mov r1, r6 800349e: 4628 mov r0, r5 80034a0: 47b8 blx r7 80034a2: 3001 adds r0, #1 80034a4: f43f aef9 beq.w 800329a <_printf_float+0xb6> 80034a8: f109 0901 add.w r9, r9, #1 80034ac: e7ee b.n 800348c <_printf_float+0x2a8> 80034ae: bf00 nop 80034b0: 7fefffff .word 0x7fefffff 80034b4: 0800627c .word 0x0800627c 80034b8: 08006280 .word 0x08006280 80034bc: 08006288 .word 0x08006288 80034c0: 08006284 .word 0x08006284 80034c4: 0800628c .word 0x0800628c 80034c8: 9a0e ldr r2, [sp, #56] ; 0x38 80034ca: 6da3 ldr r3, [r4, #88] ; 0x58 80034cc: 429a cmp r2, r3 80034ce: bfa8 it ge 80034d0: 461a movge r2, r3 80034d2: 2a00 cmp r2, #0 80034d4: 4691 mov r9, r2 80034d6: dc37 bgt.n 8003548 <_printf_float+0x364> 80034d8: f04f 0b00 mov.w fp, #0 80034dc: ea29 79e9 bic.w r9, r9, r9, asr #31 80034e0: f104 021a add.w r2, r4, #26 80034e4: f8d4 a058 ldr.w sl, [r4, #88] ; 0x58 80034e8: ebaa 0309 sub.w r3, sl, r9 80034ec: 455b cmp r3, fp 80034ee: dc33 bgt.n 8003558 <_printf_float+0x374> 80034f0: e9dd 230d ldrd r2, r3, [sp, #52] ; 0x34 80034f4: 429a cmp r2, r3 80034f6: db3b blt.n 8003570 <_printf_float+0x38c> 80034f8: 6823 ldr r3, [r4, #0] 80034fa: 07da lsls r2, r3, #31 80034fc: d438 bmi.n 8003570 <_printf_float+0x38c> 80034fe: 9b0e ldr r3, [sp, #56] ; 0x38 8003500: 990d ldr r1, [sp, #52] ; 0x34 8003502: eba3 020a sub.w r2, r3, sl 8003506: eba3 0901 sub.w r9, r3, r1 800350a: 4591 cmp r9, r2 800350c: bfa8 it ge 800350e: 4691 movge r9, r2 8003510: f1b9 0f00 cmp.w r9, #0 8003514: dc34 bgt.n 8003580 <_printf_float+0x39c> 8003516: f04f 0800 mov.w r8, #0 800351a: ea29 79e9 bic.w r9, r9, r9, asr #31 800351e: f104 0a1a add.w sl, r4, #26 8003522: e9dd 230d ldrd r2, r3, [sp, #52] ; 0x34 8003526: 1a9b subs r3, r3, r2 8003528: eba3 0309 sub.w r3, r3, r9 800352c: 4543 cmp r3, r8 800352e: f77f af7a ble.w 8003426 <_printf_float+0x242> 8003532: 2301 movs r3, #1 8003534: 4652 mov r2, sl 8003536: 4631 mov r1, r6 8003538: 4628 mov r0, r5 800353a: 47b8 blx r7 800353c: 3001 adds r0, #1 800353e: f43f aeac beq.w 800329a <_printf_float+0xb6> 8003542: f108 0801 add.w r8, r8, #1 8003546: e7ec b.n 8003522 <_printf_float+0x33e> 8003548: 4613 mov r3, r2 800354a: 4631 mov r1, r6 800354c: 4642 mov r2, r8 800354e: 4628 mov r0, r5 8003550: 47b8 blx r7 8003552: 3001 adds r0, #1 8003554: d1c0 bne.n 80034d8 <_printf_float+0x2f4> 8003556: e6a0 b.n 800329a <_printf_float+0xb6> 8003558: 2301 movs r3, #1 800355a: 4631 mov r1, r6 800355c: 4628 mov r0, r5 800355e: 920b str r2, [sp, #44] ; 0x2c 8003560: 47b8 blx r7 8003562: 3001 adds r0, #1 8003564: f43f ae99 beq.w 800329a <_printf_float+0xb6> 8003568: 9a0b ldr r2, [sp, #44] ; 0x2c 800356a: f10b 0b01 add.w fp, fp, #1 800356e: e7b9 b.n 80034e4 <_printf_float+0x300> 8003570: 4631 mov r1, r6 8003572: e9dd 2309 ldrd r2, r3, [sp, #36] ; 0x24 8003576: 4628 mov r0, r5 8003578: 47b8 blx r7 800357a: 3001 adds r0, #1 800357c: d1bf bne.n 80034fe <_printf_float+0x31a> 800357e: e68c b.n 800329a <_printf_float+0xb6> 8003580: 464b mov r3, r9 8003582: 4631 mov r1, r6 8003584: 4628 mov r0, r5 8003586: eb08 020a add.w r2, r8, sl 800358a: 47b8 blx r7 800358c: 3001 adds r0, #1 800358e: d1c2 bne.n 8003516 <_printf_float+0x332> 8003590: e683 b.n 800329a <_printf_float+0xb6> 8003592: 9a0e ldr r2, [sp, #56] ; 0x38 8003594: 2a01 cmp r2, #1 8003596: dc01 bgt.n 800359c <_printf_float+0x3b8> 8003598: 07db lsls r3, r3, #31 800359a: d537 bpl.n 800360c <_printf_float+0x428> 800359c: 2301 movs r3, #1 800359e: 4642 mov r2, r8 80035a0: 4631 mov r1, r6 80035a2: 4628 mov r0, r5 80035a4: 47b8 blx r7 80035a6: 3001 adds r0, #1 80035a8: f43f ae77 beq.w 800329a <_printf_float+0xb6> 80035ac: e9dd 2309 ldrd r2, r3, [sp, #36] ; 0x24 80035b0: 4631 mov r1, r6 80035b2: 4628 mov r0, r5 80035b4: 47b8 blx r7 80035b6: 3001 adds r0, #1 80035b8: f43f ae6f beq.w 800329a <_printf_float+0xb6> 80035bc: e9d4 0112 ldrd r0, r1, [r4, #72] ; 0x48 80035c0: 2200 movs r2, #0 80035c2: 2300 movs r3, #0 80035c4: f7fd f9f0 bl 80009a8 <__aeabi_dcmpeq> 80035c8: b9d8 cbnz r0, 8003602 <_printf_float+0x41e> 80035ca: 9b0e ldr r3, [sp, #56] ; 0x38 80035cc: f108 0201 add.w r2, r8, #1 80035d0: 3b01 subs r3, #1 80035d2: 4631 mov r1, r6 80035d4: 4628 mov r0, r5 80035d6: 47b8 blx r7 80035d8: 3001 adds r0, #1 80035da: d10e bne.n 80035fa <_printf_float+0x416> 80035dc: e65d b.n 800329a <_printf_float+0xb6> 80035de: 2301 movs r3, #1 80035e0: 464a mov r2, r9 80035e2: 4631 mov r1, r6 80035e4: 4628 mov r0, r5 80035e6: 47b8 blx r7 80035e8: 3001 adds r0, #1 80035ea: f43f ae56 beq.w 800329a <_printf_float+0xb6> 80035ee: f108 0801 add.w r8, r8, #1 80035f2: 9b0e ldr r3, [sp, #56] ; 0x38 80035f4: 3b01 subs r3, #1 80035f6: 4543 cmp r3, r8 80035f8: dcf1 bgt.n 80035de <_printf_float+0x3fa> 80035fa: 4653 mov r3, sl 80035fc: f104 0250 add.w r2, r4, #80 ; 0x50 8003600: e6e0 b.n 80033c4 <_printf_float+0x1e0> 8003602: f04f 0800 mov.w r8, #0 8003606: f104 091a add.w r9, r4, #26 800360a: e7f2 b.n 80035f2 <_printf_float+0x40e> 800360c: 2301 movs r3, #1 800360e: 4642 mov r2, r8 8003610: e7df b.n 80035d2 <_printf_float+0x3ee> 8003612: 2301 movs r3, #1 8003614: 464a mov r2, r9 8003616: 4631 mov r1, r6 8003618: 4628 mov r0, r5 800361a: 47b8 blx r7 800361c: 3001 adds r0, #1 800361e: f43f ae3c beq.w 800329a <_printf_float+0xb6> 8003622: f108 0801 add.w r8, r8, #1 8003626: 68e3 ldr r3, [r4, #12] 8003628: 990f ldr r1, [sp, #60] ; 0x3c 800362a: 1a5b subs r3, r3, r1 800362c: 4543 cmp r3, r8 800362e: dcf0 bgt.n 8003612 <_printf_float+0x42e> 8003630: e6fd b.n 800342e <_printf_float+0x24a> 8003632: f04f 0800 mov.w r8, #0 8003636: f104 0919 add.w r9, r4, #25 800363a: e7f4 b.n 8003626 <_printf_float+0x442> 0800363c <_printf_common>: 800363c: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 8003640: 4616 mov r6, r2 8003642: 4699 mov r9, r3 8003644: 688a ldr r2, [r1, #8] 8003646: 690b ldr r3, [r1, #16] 8003648: 4607 mov r7, r0 800364a: 4293 cmp r3, r2 800364c: bfb8 it lt 800364e: 4613 movlt r3, r2 8003650: 6033 str r3, [r6, #0] 8003652: f891 2043 ldrb.w r2, [r1, #67] ; 0x43 8003656: 460c mov r4, r1 8003658: f8dd 8020 ldr.w r8, [sp, #32] 800365c: b10a cbz r2, 8003662 <_printf_common+0x26> 800365e: 3301 adds r3, #1 8003660: 6033 str r3, [r6, #0] 8003662: 6823 ldr r3, [r4, #0] 8003664: 0699 lsls r1, r3, #26 8003666: bf42 ittt mi 8003668: 6833 ldrmi r3, [r6, #0] 800366a: 3302 addmi r3, #2 800366c: 6033 strmi r3, [r6, #0] 800366e: 6825 ldr r5, [r4, #0] 8003670: f015 0506 ands.w r5, r5, #6 8003674: d106 bne.n 8003684 <_printf_common+0x48> 8003676: f104 0a19 add.w sl, r4, #25 800367a: 68e3 ldr r3, [r4, #12] 800367c: 6832 ldr r2, [r6, #0] 800367e: 1a9b subs r3, r3, r2 8003680: 42ab cmp r3, r5 8003682: dc28 bgt.n 80036d6 <_printf_common+0x9a> 8003684: f894 2043 ldrb.w r2, [r4, #67] ; 0x43 8003688: 1e13 subs r3, r2, #0 800368a: 6822 ldr r2, [r4, #0] 800368c: bf18 it ne 800368e: 2301 movne r3, #1 8003690: 0692 lsls r2, r2, #26 8003692: d42d bmi.n 80036f0 <_printf_common+0xb4> 8003694: 4649 mov r1, r9 8003696: 4638 mov r0, r7 8003698: f104 0243 add.w r2, r4, #67 ; 0x43 800369c: 47c0 blx r8 800369e: 3001 adds r0, #1 80036a0: d020 beq.n 80036e4 <_printf_common+0xa8> 80036a2: 6823 ldr r3, [r4, #0] 80036a4: 68e5 ldr r5, [r4, #12] 80036a6: f003 0306 and.w r3, r3, #6 80036aa: 2b04 cmp r3, #4 80036ac: bf18 it ne 80036ae: 2500 movne r5, #0 80036b0: 6832 ldr r2, [r6, #0] 80036b2: f04f 0600 mov.w r6, #0 80036b6: 68a3 ldr r3, [r4, #8] 80036b8: bf08 it eq 80036ba: 1aad subeq r5, r5, r2 80036bc: 6922 ldr r2, [r4, #16] 80036be: bf08 it eq 80036c0: ea25 75e5 biceq.w r5, r5, r5, asr #31 80036c4: 4293 cmp r3, r2 80036c6: bfc4 itt gt 80036c8: 1a9b subgt r3, r3, r2 80036ca: 18ed addgt r5, r5, r3 80036cc: 341a adds r4, #26 80036ce: 42b5 cmp r5, r6 80036d0: d11a bne.n 8003708 <_printf_common+0xcc> 80036d2: 2000 movs r0, #0 80036d4: e008 b.n 80036e8 <_printf_common+0xac> 80036d6: 2301 movs r3, #1 80036d8: 4652 mov r2, sl 80036da: 4649 mov r1, r9 80036dc: 4638 mov r0, r7 80036de: 47c0 blx r8 80036e0: 3001 adds r0, #1 80036e2: d103 bne.n 80036ec <_printf_common+0xb0> 80036e4: f04f 30ff mov.w r0, #4294967295 80036e8: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 80036ec: 3501 adds r5, #1 80036ee: e7c4 b.n 800367a <_printf_common+0x3e> 80036f0: 2030 movs r0, #48 ; 0x30 80036f2: 18e1 adds r1, r4, r3 80036f4: f881 0043 strb.w r0, [r1, #67] ; 0x43 80036f8: 1c5a adds r2, r3, #1 80036fa: f894 1045 ldrb.w r1, [r4, #69] ; 0x45 80036fe: 4422 add r2, r4 8003700: 3302 adds r3, #2 8003702: f882 1043 strb.w r1, [r2, #67] ; 0x43 8003706: e7c5 b.n 8003694 <_printf_common+0x58> 8003708: 2301 movs r3, #1 800370a: 4622 mov r2, r4 800370c: 4649 mov r1, r9 800370e: 4638 mov r0, r7 8003710: 47c0 blx r8 8003712: 3001 adds r0, #1 8003714: d0e6 beq.n 80036e4 <_printf_common+0xa8> 8003716: 3601 adds r6, #1 8003718: e7d9 b.n 80036ce <_printf_common+0x92> ... 0800371c <_printf_i>: 800371c: e92d 47ff stmdb sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, lr} 8003720: 7e0f ldrb r7, [r1, #24] 8003722: 4691 mov r9, r2 8003724: 2f78 cmp r7, #120 ; 0x78 8003726: 4680 mov r8, r0 8003728: 460c mov r4, r1 800372a: 469a mov sl, r3 800372c: 9d0c ldr r5, [sp, #48] ; 0x30 800372e: f101 0243 add.w r2, r1, #67 ; 0x43 8003732: d807 bhi.n 8003744 <_printf_i+0x28> 8003734: 2f62 cmp r7, #98 ; 0x62 8003736: d80a bhi.n 800374e <_printf_i+0x32> 8003738: 2f00 cmp r7, #0 800373a: f000 80d9 beq.w 80038f0 <_printf_i+0x1d4> 800373e: 2f58 cmp r7, #88 ; 0x58 8003740: f000 80a4 beq.w 800388c <_printf_i+0x170> 8003744: f104 0542 add.w r5, r4, #66 ; 0x42 8003748: f884 7042 strb.w r7, [r4, #66] ; 0x42 800374c: e03a b.n 80037c4 <_printf_i+0xa8> 800374e: f1a7 0363 sub.w r3, r7, #99 ; 0x63 8003752: 2b15 cmp r3, #21 8003754: d8f6 bhi.n 8003744 <_printf_i+0x28> 8003756: a101 add r1, pc, #4 ; (adr r1, 800375c <_printf_i+0x40>) 8003758: f851 f023 ldr.w pc, [r1, r3, lsl #2] 800375c: 080037b5 .word 0x080037b5 8003760: 080037c9 .word 0x080037c9 8003764: 08003745 .word 0x08003745 8003768: 08003745 .word 0x08003745 800376c: 08003745 .word 0x08003745 8003770: 08003745 .word 0x08003745 8003774: 080037c9 .word 0x080037c9 8003778: 08003745 .word 0x08003745 800377c: 08003745 .word 0x08003745 8003780: 08003745 .word 0x08003745 8003784: 08003745 .word 0x08003745 8003788: 080038d7 .word 0x080038d7 800378c: 080037f9 .word 0x080037f9 8003790: 080038b9 .word 0x080038b9 8003794: 08003745 .word 0x08003745 8003798: 08003745 .word 0x08003745 800379c: 080038f9 .word 0x080038f9 80037a0: 08003745 .word 0x08003745 80037a4: 080037f9 .word 0x080037f9 80037a8: 08003745 .word 0x08003745 80037ac: 08003745 .word 0x08003745 80037b0: 080038c1 .word 0x080038c1 80037b4: 682b ldr r3, [r5, #0] 80037b6: 1d1a adds r2, r3, #4 80037b8: 681b ldr r3, [r3, #0] 80037ba: 602a str r2, [r5, #0] 80037bc: f104 0542 add.w r5, r4, #66 ; 0x42 80037c0: f884 3042 strb.w r3, [r4, #66] ; 0x42 80037c4: 2301 movs r3, #1 80037c6: e0a4 b.n 8003912 <_printf_i+0x1f6> 80037c8: 6820 ldr r0, [r4, #0] 80037ca: 6829 ldr r1, [r5, #0] 80037cc: 0606 lsls r6, r0, #24 80037ce: f101 0304 add.w r3, r1, #4 80037d2: d50a bpl.n 80037ea <_printf_i+0xce> 80037d4: 680e ldr r6, [r1, #0] 80037d6: 602b str r3, [r5, #0] 80037d8: 2e00 cmp r6, #0 80037da: da03 bge.n 80037e4 <_printf_i+0xc8> 80037dc: 232d movs r3, #45 ; 0x2d 80037de: 4276 negs r6, r6 80037e0: f884 3043 strb.w r3, [r4, #67] ; 0x43 80037e4: 230a movs r3, #10 80037e6: 485e ldr r0, [pc, #376] ; (8003960 <_printf_i+0x244>) 80037e8: e019 b.n 800381e <_printf_i+0x102> 80037ea: 680e ldr r6, [r1, #0] 80037ec: f010 0f40 tst.w r0, #64 ; 0x40 80037f0: 602b str r3, [r5, #0] 80037f2: bf18 it ne 80037f4: b236 sxthne r6, r6 80037f6: e7ef b.n 80037d8 <_printf_i+0xbc> 80037f8: 682b ldr r3, [r5, #0] 80037fa: 6820 ldr r0, [r4, #0] 80037fc: 1d19 adds r1, r3, #4 80037fe: 6029 str r1, [r5, #0] 8003800: 0601 lsls r1, r0, #24 8003802: d501 bpl.n 8003808 <_printf_i+0xec> 8003804: 681e ldr r6, [r3, #0] 8003806: e002 b.n 800380e <_printf_i+0xf2> 8003808: 0646 lsls r6, r0, #25 800380a: d5fb bpl.n 8003804 <_printf_i+0xe8> 800380c: 881e ldrh r6, [r3, #0] 800380e: 2f6f cmp r7, #111 ; 0x6f 8003810: bf0c ite eq 8003812: 2308 moveq r3, #8 8003814: 230a movne r3, #10 8003816: 4852 ldr r0, [pc, #328] ; (8003960 <_printf_i+0x244>) 8003818: 2100 movs r1, #0 800381a: f884 1043 strb.w r1, [r4, #67] ; 0x43 800381e: 6865 ldr r5, [r4, #4] 8003820: 2d00 cmp r5, #0 8003822: bfa8 it ge 8003824: 6821 ldrge r1, [r4, #0] 8003826: 60a5 str r5, [r4, #8] 8003828: bfa4 itt ge 800382a: f021 0104 bicge.w r1, r1, #4 800382e: 6021 strge r1, [r4, #0] 8003830: b90e cbnz r6, 8003836 <_printf_i+0x11a> 8003832: 2d00 cmp r5, #0 8003834: d04d beq.n 80038d2 <_printf_i+0x1b6> 8003836: 4615 mov r5, r2 8003838: fbb6 f1f3 udiv r1, r6, r3 800383c: fb03 6711 mls r7, r3, r1, r6 8003840: 5dc7 ldrb r7, [r0, r7] 8003842: f805 7d01 strb.w r7, [r5, #-1]! 8003846: 4637 mov r7, r6 8003848: 42bb cmp r3, r7 800384a: 460e mov r6, r1 800384c: d9f4 bls.n 8003838 <_printf_i+0x11c> 800384e: 2b08 cmp r3, #8 8003850: d10b bne.n 800386a <_printf_i+0x14e> 8003852: 6823 ldr r3, [r4, #0] 8003854: 07de lsls r6, r3, #31 8003856: d508 bpl.n 800386a <_printf_i+0x14e> 8003858: 6923 ldr r3, [r4, #16] 800385a: 6861 ldr r1, [r4, #4] 800385c: 4299 cmp r1, r3 800385e: bfde ittt le 8003860: 2330 movle r3, #48 ; 0x30 8003862: f805 3c01 strble.w r3, [r5, #-1] 8003866: f105 35ff addle.w r5, r5, #4294967295 800386a: 1b52 subs r2, r2, r5 800386c: 6122 str r2, [r4, #16] 800386e: 464b mov r3, r9 8003870: 4621 mov r1, r4 8003872: 4640 mov r0, r8 8003874: f8cd a000 str.w sl, [sp] 8003878: aa03 add r2, sp, #12 800387a: f7ff fedf bl 800363c <_printf_common> 800387e: 3001 adds r0, #1 8003880: d14c bne.n 800391c <_printf_i+0x200> 8003882: f04f 30ff mov.w r0, #4294967295 8003886: b004 add sp, #16 8003888: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 800388c: 4834 ldr r0, [pc, #208] ; (8003960 <_printf_i+0x244>) 800388e: f881 7045 strb.w r7, [r1, #69] ; 0x45 8003892: 6829 ldr r1, [r5, #0] 8003894: 6823 ldr r3, [r4, #0] 8003896: f851 6b04 ldr.w r6, [r1], #4 800389a: 6029 str r1, [r5, #0] 800389c: 061d lsls r5, r3, #24 800389e: d514 bpl.n 80038ca <_printf_i+0x1ae> 80038a0: 07df lsls r7, r3, #31 80038a2: bf44 itt mi 80038a4: f043 0320 orrmi.w r3, r3, #32 80038a8: 6023 strmi r3, [r4, #0] 80038aa: b91e cbnz r6, 80038b4 <_printf_i+0x198> 80038ac: 6823 ldr r3, [r4, #0] 80038ae: f023 0320 bic.w r3, r3, #32 80038b2: 6023 str r3, [r4, #0] 80038b4: 2310 movs r3, #16 80038b6: e7af b.n 8003818 <_printf_i+0xfc> 80038b8: 6823 ldr r3, [r4, #0] 80038ba: f043 0320 orr.w r3, r3, #32 80038be: 6023 str r3, [r4, #0] 80038c0: 2378 movs r3, #120 ; 0x78 80038c2: 4828 ldr r0, [pc, #160] ; (8003964 <_printf_i+0x248>) 80038c4: f884 3045 strb.w r3, [r4, #69] ; 0x45 80038c8: e7e3 b.n 8003892 <_printf_i+0x176> 80038ca: 0659 lsls r1, r3, #25 80038cc: bf48 it mi 80038ce: b2b6 uxthmi r6, r6 80038d0: e7e6 b.n 80038a0 <_printf_i+0x184> 80038d2: 4615 mov r5, r2 80038d4: e7bb b.n 800384e <_printf_i+0x132> 80038d6: 682b ldr r3, [r5, #0] 80038d8: 6826 ldr r6, [r4, #0] 80038da: 1d18 adds r0, r3, #4 80038dc: 6961 ldr r1, [r4, #20] 80038de: 6028 str r0, [r5, #0] 80038e0: 0635 lsls r5, r6, #24 80038e2: 681b ldr r3, [r3, #0] 80038e4: d501 bpl.n 80038ea <_printf_i+0x1ce> 80038e6: 6019 str r1, [r3, #0] 80038e8: e002 b.n 80038f0 <_printf_i+0x1d4> 80038ea: 0670 lsls r0, r6, #25 80038ec: d5fb bpl.n 80038e6 <_printf_i+0x1ca> 80038ee: 8019 strh r1, [r3, #0] 80038f0: 2300 movs r3, #0 80038f2: 4615 mov r5, r2 80038f4: 6123 str r3, [r4, #16] 80038f6: e7ba b.n 800386e <_printf_i+0x152> 80038f8: 682b ldr r3, [r5, #0] 80038fa: 2100 movs r1, #0 80038fc: 1d1a adds r2, r3, #4 80038fe: 602a str r2, [r5, #0] 8003900: 681d ldr r5, [r3, #0] 8003902: 6862 ldr r2, [r4, #4] 8003904: 4628 mov r0, r5 8003906: f000 fed5 bl 80046b4 800390a: b108 cbz r0, 8003910 <_printf_i+0x1f4> 800390c: 1b40 subs r0, r0, r5 800390e: 6060 str r0, [r4, #4] 8003910: 6863 ldr r3, [r4, #4] 8003912: 6123 str r3, [r4, #16] 8003914: 2300 movs r3, #0 8003916: f884 3043 strb.w r3, [r4, #67] ; 0x43 800391a: e7a8 b.n 800386e <_printf_i+0x152> 800391c: 462a mov r2, r5 800391e: 4649 mov r1, r9 8003920: 4640 mov r0, r8 8003922: 6923 ldr r3, [r4, #16] 8003924: 47d0 blx sl 8003926: 3001 adds r0, #1 8003928: d0ab beq.n 8003882 <_printf_i+0x166> 800392a: 6823 ldr r3, [r4, #0] 800392c: 079b lsls r3, r3, #30 800392e: d413 bmi.n 8003958 <_printf_i+0x23c> 8003930: 68e0 ldr r0, [r4, #12] 8003932: 9b03 ldr r3, [sp, #12] 8003934: 4298 cmp r0, r3 8003936: bfb8 it lt 8003938: 4618 movlt r0, r3 800393a: e7a4 b.n 8003886 <_printf_i+0x16a> 800393c: 2301 movs r3, #1 800393e: 4632 mov r2, r6 8003940: 4649 mov r1, r9 8003942: 4640 mov r0, r8 8003944: 47d0 blx sl 8003946: 3001 adds r0, #1 8003948: d09b beq.n 8003882 <_printf_i+0x166> 800394a: 3501 adds r5, #1 800394c: 68e3 ldr r3, [r4, #12] 800394e: 9903 ldr r1, [sp, #12] 8003950: 1a5b subs r3, r3, r1 8003952: 42ab cmp r3, r5 8003954: dcf2 bgt.n 800393c <_printf_i+0x220> 8003956: e7eb b.n 8003930 <_printf_i+0x214> 8003958: 2500 movs r5, #0 800395a: f104 0619 add.w r6, r4, #25 800395e: e7f5 b.n 800394c <_printf_i+0x230> 8003960: 0800628e .word 0x0800628e 8003964: 0800629f .word 0x0800629f 08003968 : 8003968: b40e push {r1, r2, r3} 800396a: f06f 4100 mvn.w r1, #2147483648 ; 0x80000000 800396e: b500 push {lr} 8003970: b09c sub sp, #112 ; 0x70 8003972: ab1d add r3, sp, #116 ; 0x74 8003974: 9002 str r0, [sp, #8] 8003976: 9006 str r0, [sp, #24] 8003978: 9107 str r1, [sp, #28] 800397a: 9104 str r1, [sp, #16] 800397c: 4808 ldr r0, [pc, #32] ; (80039a0 ) 800397e: 4909 ldr r1, [pc, #36] ; (80039a4 ) 8003980: f853 2b04 ldr.w r2, [r3], #4 8003984: 9105 str r1, [sp, #20] 8003986: 6800 ldr r0, [r0, #0] 8003988: a902 add r1, sp, #8 800398a: 9301 str r3, [sp, #4] 800398c: f001 fb7c bl 8005088 <_svfiprintf_r> 8003990: 2200 movs r2, #0 8003992: 9b02 ldr r3, [sp, #8] 8003994: 701a strb r2, [r3, #0] 8003996: b01c add sp, #112 ; 0x70 8003998: f85d eb04 ldr.w lr, [sp], #4 800399c: b003 add sp, #12 800399e: 4770 bx lr 80039a0: 2000000c .word 0x2000000c 80039a4: ffff0208 .word 0xffff0208 080039a8 : 80039a8: e92d 4ff7 stmdb sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr} 80039ac: 6903 ldr r3, [r0, #16] 80039ae: 690c ldr r4, [r1, #16] 80039b0: 4607 mov r7, r0 80039b2: 42a3 cmp r3, r4 80039b4: f2c0 8082 blt.w 8003abc 80039b8: 3c01 subs r4, #1 80039ba: f100 0514 add.w r5, r0, #20 80039be: f101 0814 add.w r8, r1, #20 80039c2: eb05 0384 add.w r3, r5, r4, lsl #2 80039c6: 9301 str r3, [sp, #4] 80039c8: f858 3024 ldr.w r3, [r8, r4, lsl #2] 80039cc: f855 2024 ldr.w r2, [r5, r4, lsl #2] 80039d0: 3301 adds r3, #1 80039d2: 429a cmp r2, r3 80039d4: fbb2 f6f3 udiv r6, r2, r3 80039d8: ea4f 0b84 mov.w fp, r4, lsl #2 80039dc: eb08 0984 add.w r9, r8, r4, lsl #2 80039e0: d331 bcc.n 8003a46 80039e2: f04f 0e00 mov.w lr, #0 80039e6: 4640 mov r0, r8 80039e8: 46ac mov ip, r5 80039ea: 46f2 mov sl, lr 80039ec: f850 2b04 ldr.w r2, [r0], #4 80039f0: b293 uxth r3, r2 80039f2: fb06 e303 mla r3, r6, r3, lr 80039f6: 0c12 lsrs r2, r2, #16 80039f8: ea4f 4e13 mov.w lr, r3, lsr #16 80039fc: b29b uxth r3, r3 80039fe: fb06 e202 mla r2, r6, r2, lr 8003a02: ebaa 0303 sub.w r3, sl, r3 8003a06: f8dc a000 ldr.w sl, [ip] 8003a0a: ea4f 4e12 mov.w lr, r2, lsr #16 8003a0e: fa1f fa8a uxth.w sl, sl 8003a12: 4453 add r3, sl 8003a14: f8dc a000 ldr.w sl, [ip] 8003a18: b292 uxth r2, r2 8003a1a: ebc2 421a rsb r2, r2, sl, lsr #16 8003a1e: eb02 4223 add.w r2, r2, r3, asr #16 8003a22: b29b uxth r3, r3 8003a24: ea43 4302 orr.w r3, r3, r2, lsl #16 8003a28: 4581 cmp r9, r0 8003a2a: ea4f 4a22 mov.w sl, r2, asr #16 8003a2e: f84c 3b04 str.w r3, [ip], #4 8003a32: d2db bcs.n 80039ec 8003a34: f855 300b ldr.w r3, [r5, fp] 8003a38: b92b cbnz r3, 8003a46 8003a3a: 9b01 ldr r3, [sp, #4] 8003a3c: 3b04 subs r3, #4 8003a3e: 429d cmp r5, r3 8003a40: 461a mov r2, r3 8003a42: d32f bcc.n 8003aa4 8003a44: 613c str r4, [r7, #16] 8003a46: 4638 mov r0, r7 8003a48: f001 f8ce bl 8004be8 <__mcmp> 8003a4c: 2800 cmp r0, #0 8003a4e: db25 blt.n 8003a9c 8003a50: 4628 mov r0, r5 8003a52: f04f 0c00 mov.w ip, #0 8003a56: 3601 adds r6, #1 8003a58: f858 1b04 ldr.w r1, [r8], #4 8003a5c: f8d0 e000 ldr.w lr, [r0] 8003a60: b28b uxth r3, r1 8003a62: ebac 0303 sub.w r3, ip, r3 8003a66: fa1f f28e uxth.w r2, lr 8003a6a: 4413 add r3, r2 8003a6c: 0c0a lsrs r2, r1, #16 8003a6e: ebc2 421e rsb r2, r2, lr, lsr #16 8003a72: eb02 4223 add.w r2, r2, r3, asr #16 8003a76: b29b uxth r3, r3 8003a78: ea43 4302 orr.w r3, r3, r2, lsl #16 8003a7c: 45c1 cmp r9, r8 8003a7e: ea4f 4c22 mov.w ip, r2, asr #16 8003a82: f840 3b04 str.w r3, [r0], #4 8003a86: d2e7 bcs.n 8003a58 8003a88: f855 2024 ldr.w r2, [r5, r4, lsl #2] 8003a8c: eb05 0384 add.w r3, r5, r4, lsl #2 8003a90: b922 cbnz r2, 8003a9c 8003a92: 3b04 subs r3, #4 8003a94: 429d cmp r5, r3 8003a96: 461a mov r2, r3 8003a98: d30a bcc.n 8003ab0 8003a9a: 613c str r4, [r7, #16] 8003a9c: 4630 mov r0, r6 8003a9e: b003 add sp, #12 8003aa0: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 8003aa4: 6812 ldr r2, [r2, #0] 8003aa6: 3b04 subs r3, #4 8003aa8: 2a00 cmp r2, #0 8003aaa: d1cb bne.n 8003a44 8003aac: 3c01 subs r4, #1 8003aae: e7c6 b.n 8003a3e 8003ab0: 6812 ldr r2, [r2, #0] 8003ab2: 3b04 subs r3, #4 8003ab4: 2a00 cmp r2, #0 8003ab6: d1f0 bne.n 8003a9a 8003ab8: 3c01 subs r4, #1 8003aba: e7eb b.n 8003a94 8003abc: 2000 movs r0, #0 8003abe: e7ee b.n 8003a9e 08003ac0 <_dtoa_r>: 8003ac0: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 8003ac4: 4616 mov r6, r2 8003ac6: 461f mov r7, r3 8003ac8: 6a44 ldr r4, [r0, #36] ; 0x24 8003aca: b099 sub sp, #100 ; 0x64 8003acc: 4605 mov r5, r0 8003ace: e9cd 6704 strd r6, r7, [sp, #16] 8003ad2: f8dd 8094 ldr.w r8, [sp, #148] ; 0x94 8003ad6: b974 cbnz r4, 8003af6 <_dtoa_r+0x36> 8003ad8: 2010 movs r0, #16 8003ada: f000 fde3 bl 80046a4 8003ade: 4602 mov r2, r0 8003ae0: 6268 str r0, [r5, #36] ; 0x24 8003ae2: b920 cbnz r0, 8003aee <_dtoa_r+0x2e> 8003ae4: 21ea movs r1, #234 ; 0xea 8003ae6: 4ba8 ldr r3, [pc, #672] ; (8003d88 <_dtoa_r+0x2c8>) 8003ae8: 48a8 ldr r0, [pc, #672] ; (8003d8c <_dtoa_r+0x2cc>) 8003aea: f001 fbdd bl 80052a8 <__assert_func> 8003aee: e9c0 4401 strd r4, r4, [r0, #4] 8003af2: 6004 str r4, [r0, #0] 8003af4: 60c4 str r4, [r0, #12] 8003af6: 6a6b ldr r3, [r5, #36] ; 0x24 8003af8: 6819 ldr r1, [r3, #0] 8003afa: b151 cbz r1, 8003b12 <_dtoa_r+0x52> 8003afc: 685a ldr r2, [r3, #4] 8003afe: 2301 movs r3, #1 8003b00: 4093 lsls r3, r2 8003b02: 604a str r2, [r1, #4] 8003b04: 608b str r3, [r1, #8] 8003b06: 4628 mov r0, r5 8003b08: f000 fe30 bl 800476c <_Bfree> 8003b0c: 2200 movs r2, #0 8003b0e: 6a6b ldr r3, [r5, #36] ; 0x24 8003b10: 601a str r2, [r3, #0] 8003b12: 1e3b subs r3, r7, #0 8003b14: bfaf iteee ge 8003b16: 2300 movge r3, #0 8003b18: 2201 movlt r2, #1 8003b1a: f023 4300 biclt.w r3, r3, #2147483648 ; 0x80000000 8003b1e: 9305 strlt r3, [sp, #20] 8003b20: bfa8 it ge 8003b22: f8c8 3000 strge.w r3, [r8] 8003b26: f8dd 9014 ldr.w r9, [sp, #20] 8003b2a: 4b99 ldr r3, [pc, #612] ; (8003d90 <_dtoa_r+0x2d0>) 8003b2c: bfb8 it lt 8003b2e: f8c8 2000 strlt.w r2, [r8] 8003b32: ea33 0309 bics.w r3, r3, r9 8003b36: d119 bne.n 8003b6c <_dtoa_r+0xac> 8003b38: f242 730f movw r3, #9999 ; 0x270f 8003b3c: 9a24 ldr r2, [sp, #144] ; 0x90 8003b3e: 6013 str r3, [r2, #0] 8003b40: f3c9 0313 ubfx r3, r9, #0, #20 8003b44: 4333 orrs r3, r6 8003b46: f000 857f beq.w 8004648 <_dtoa_r+0xb88> 8003b4a: 9b26 ldr r3, [sp, #152] ; 0x98 8003b4c: b953 cbnz r3, 8003b64 <_dtoa_r+0xa4> 8003b4e: 4b91 ldr r3, [pc, #580] ; (8003d94 <_dtoa_r+0x2d4>) 8003b50: e022 b.n 8003b98 <_dtoa_r+0xd8> 8003b52: 4b91 ldr r3, [pc, #580] ; (8003d98 <_dtoa_r+0x2d8>) 8003b54: 9303 str r3, [sp, #12] 8003b56: 3308 adds r3, #8 8003b58: 9a26 ldr r2, [sp, #152] ; 0x98 8003b5a: 6013 str r3, [r2, #0] 8003b5c: 9803 ldr r0, [sp, #12] 8003b5e: b019 add sp, #100 ; 0x64 8003b60: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 8003b64: 4b8b ldr r3, [pc, #556] ; (8003d94 <_dtoa_r+0x2d4>) 8003b66: 9303 str r3, [sp, #12] 8003b68: 3303 adds r3, #3 8003b6a: e7f5 b.n 8003b58 <_dtoa_r+0x98> 8003b6c: e9dd 3404 ldrd r3, r4, [sp, #16] 8003b70: e9cd 340c strd r3, r4, [sp, #48] ; 0x30 8003b74: e9dd 010c ldrd r0, r1, [sp, #48] ; 0x30 8003b78: 2200 movs r2, #0 8003b7a: 2300 movs r3, #0 8003b7c: f7fc ff14 bl 80009a8 <__aeabi_dcmpeq> 8003b80: 4680 mov r8, r0 8003b82: b158 cbz r0, 8003b9c <_dtoa_r+0xdc> 8003b84: 2301 movs r3, #1 8003b86: 9a24 ldr r2, [sp, #144] ; 0x90 8003b88: 6013 str r3, [r2, #0] 8003b8a: 9b26 ldr r3, [sp, #152] ; 0x98 8003b8c: 2b00 cmp r3, #0 8003b8e: f000 8558 beq.w 8004642 <_dtoa_r+0xb82> 8003b92: 4882 ldr r0, [pc, #520] ; (8003d9c <_dtoa_r+0x2dc>) 8003b94: 6018 str r0, [r3, #0] 8003b96: 1e43 subs r3, r0, #1 8003b98: 9303 str r3, [sp, #12] 8003b9a: e7df b.n 8003b5c <_dtoa_r+0x9c> 8003b9c: ab16 add r3, sp, #88 ; 0x58 8003b9e: 9301 str r3, [sp, #4] 8003ba0: ab17 add r3, sp, #92 ; 0x5c 8003ba2: 9300 str r3, [sp, #0] 8003ba4: 4628 mov r0, r5 8003ba6: e9dd 230c ldrd r2, r3, [sp, #48] ; 0x30 8003baa: f001 f8c5 bl 8004d38 <__d2b> 8003bae: f3c9 540a ubfx r4, r9, #20, #11 8003bb2: 4683 mov fp, r0 8003bb4: 2c00 cmp r4, #0 8003bb6: d07f beq.n 8003cb8 <_dtoa_r+0x1f8> 8003bb8: e9dd 010c ldrd r0, r1, [sp, #48] ; 0x30 8003bbc: 9b0d ldr r3, [sp, #52] ; 0x34 8003bbe: f2a4 34ff subw r4, r4, #1023 ; 0x3ff 8003bc2: f3c3 0313 ubfx r3, r3, #0, #20 8003bc6: f043 517f orr.w r1, r3, #1069547520 ; 0x3fc00000 8003bca: f441 1140 orr.w r1, r1, #3145728 ; 0x300000 8003bce: f8cd 804c str.w r8, [sp, #76] ; 0x4c 8003bd2: 2200 movs r2, #0 8003bd4: 4b72 ldr r3, [pc, #456] ; (8003da0 <_dtoa_r+0x2e0>) 8003bd6: f7fc fac7 bl 8000168 <__aeabi_dsub> 8003bda: a365 add r3, pc, #404 ; (adr r3, 8003d70 <_dtoa_r+0x2b0>) 8003bdc: e9d3 2300 ldrd r2, r3, [r3] 8003be0: f7fc fc7a bl 80004d8 <__aeabi_dmul> 8003be4: a364 add r3, pc, #400 ; (adr r3, 8003d78 <_dtoa_r+0x2b8>) 8003be6: e9d3 2300 ldrd r2, r3, [r3] 8003bea: f7fc fabf bl 800016c <__adddf3> 8003bee: 4606 mov r6, r0 8003bf0: 4620 mov r0, r4 8003bf2: 460f mov r7, r1 8003bf4: f7fc fc06 bl 8000404 <__aeabi_i2d> 8003bf8: a361 add r3, pc, #388 ; (adr r3, 8003d80 <_dtoa_r+0x2c0>) 8003bfa: e9d3 2300 ldrd r2, r3, [r3] 8003bfe: f7fc fc6b bl 80004d8 <__aeabi_dmul> 8003c02: 4602 mov r2, r0 8003c04: 460b mov r3, r1 8003c06: 4630 mov r0, r6 8003c08: 4639 mov r1, r7 8003c0a: f7fc faaf bl 800016c <__adddf3> 8003c0e: 4606 mov r6, r0 8003c10: 460f mov r7, r1 8003c12: f7fc ff11 bl 8000a38 <__aeabi_d2iz> 8003c16: 2200 movs r2, #0 8003c18: 4682 mov sl, r0 8003c1a: 2300 movs r3, #0 8003c1c: 4630 mov r0, r6 8003c1e: 4639 mov r1, r7 8003c20: f7fc fecc bl 80009bc <__aeabi_dcmplt> 8003c24: b148 cbz r0, 8003c3a <_dtoa_r+0x17a> 8003c26: 4650 mov r0, sl 8003c28: f7fc fbec bl 8000404 <__aeabi_i2d> 8003c2c: 4632 mov r2, r6 8003c2e: 463b mov r3, r7 8003c30: f7fc feba bl 80009a8 <__aeabi_dcmpeq> 8003c34: b908 cbnz r0, 8003c3a <_dtoa_r+0x17a> 8003c36: f10a 3aff add.w sl, sl, #4294967295 8003c3a: f1ba 0f16 cmp.w sl, #22 8003c3e: d858 bhi.n 8003cf2 <_dtoa_r+0x232> 8003c40: e9dd 010c ldrd r0, r1, [sp, #48] ; 0x30 8003c44: 4b57 ldr r3, [pc, #348] ; (8003da4 <_dtoa_r+0x2e4>) 8003c46: eb03 03ca add.w r3, r3, sl, lsl #3 8003c4a: e9d3 2300 ldrd r2, r3, [r3] 8003c4e: f7fc feb5 bl 80009bc <__aeabi_dcmplt> 8003c52: 2800 cmp r0, #0 8003c54: d04f beq.n 8003cf6 <_dtoa_r+0x236> 8003c56: 2300 movs r3, #0 8003c58: f10a 3aff add.w sl, sl, #4294967295 8003c5c: 930f str r3, [sp, #60] ; 0x3c 8003c5e: 9b16 ldr r3, [sp, #88] ; 0x58 8003c60: 1b1c subs r4, r3, r4 8003c62: 1e63 subs r3, r4, #1 8003c64: 9309 str r3, [sp, #36] ; 0x24 8003c66: bf49 itett mi 8003c68: f1c4 0301 rsbmi r3, r4, #1 8003c6c: 2300 movpl r3, #0 8003c6e: 9306 strmi r3, [sp, #24] 8003c70: 2300 movmi r3, #0 8003c72: bf54 ite pl 8003c74: 9306 strpl r3, [sp, #24] 8003c76: 9309 strmi r3, [sp, #36] ; 0x24 8003c78: f1ba 0f00 cmp.w sl, #0 8003c7c: db3d blt.n 8003cfa <_dtoa_r+0x23a> 8003c7e: 9b09 ldr r3, [sp, #36] ; 0x24 8003c80: f8cd a038 str.w sl, [sp, #56] ; 0x38 8003c84: 4453 add r3, sl 8003c86: 9309 str r3, [sp, #36] ; 0x24 8003c88: 2300 movs r3, #0 8003c8a: 930a str r3, [sp, #40] ; 0x28 8003c8c: 9b22 ldr r3, [sp, #136] ; 0x88 8003c8e: 2b09 cmp r3, #9 8003c90: f200 808c bhi.w 8003dac <_dtoa_r+0x2ec> 8003c94: 2b05 cmp r3, #5 8003c96: bfc4 itt gt 8003c98: 3b04 subgt r3, #4 8003c9a: 9322 strgt r3, [sp, #136] ; 0x88 8003c9c: 9b22 ldr r3, [sp, #136] ; 0x88 8003c9e: bfc8 it gt 8003ca0: 2400 movgt r4, #0 8003ca2: f1a3 0302 sub.w r3, r3, #2 8003ca6: bfd8 it le 8003ca8: 2401 movle r4, #1 8003caa: 2b03 cmp r3, #3 8003cac: f200 808a bhi.w 8003dc4 <_dtoa_r+0x304> 8003cb0: e8df f003 tbb [pc, r3] 8003cb4: 5b4d4f2d .word 0x5b4d4f2d 8003cb8: e9dd 4316 ldrd r4, r3, [sp, #88] ; 0x58 8003cbc: 441c add r4, r3 8003cbe: f204 4332 addw r3, r4, #1074 ; 0x432 8003cc2: 2b20 cmp r3, #32 8003cc4: bfc3 ittte gt 8003cc6: f1c3 0340 rsbgt r3, r3, #64 ; 0x40 8003cca: f204 4012 addwgt r0, r4, #1042 ; 0x412 8003cce: fa09 f303 lslgt.w r3, r9, r3 8003cd2: f1c3 0320 rsble r3, r3, #32 8003cd6: bfc6 itte gt 8003cd8: fa26 f000 lsrgt.w r0, r6, r0 8003cdc: 4318 orrgt r0, r3 8003cde: fa06 f003 lslle.w r0, r6, r3 8003ce2: f7fc fb7f bl 80003e4 <__aeabi_ui2d> 8003ce6: 2301 movs r3, #1 8003ce8: f1a1 71f8 sub.w r1, r1, #32505856 ; 0x1f00000 8003cec: 3c01 subs r4, #1 8003cee: 9313 str r3, [sp, #76] ; 0x4c 8003cf0: e76f b.n 8003bd2 <_dtoa_r+0x112> 8003cf2: 2301 movs r3, #1 8003cf4: e7b2 b.n 8003c5c <_dtoa_r+0x19c> 8003cf6: 900f str r0, [sp, #60] ; 0x3c 8003cf8: e7b1 b.n 8003c5e <_dtoa_r+0x19e> 8003cfa: 9b06 ldr r3, [sp, #24] 8003cfc: eba3 030a sub.w r3, r3, sl 8003d00: 9306 str r3, [sp, #24] 8003d02: f1ca 0300 rsb r3, sl, #0 8003d06: 930a str r3, [sp, #40] ; 0x28 8003d08: 2300 movs r3, #0 8003d0a: 930e str r3, [sp, #56] ; 0x38 8003d0c: e7be b.n 8003c8c <_dtoa_r+0x1cc> 8003d0e: 2300 movs r3, #0 8003d10: 930b str r3, [sp, #44] ; 0x2c 8003d12: 9b23 ldr r3, [sp, #140] ; 0x8c 8003d14: 2b00 cmp r3, #0 8003d16: dc58 bgt.n 8003dca <_dtoa_r+0x30a> 8003d18: f04f 0901 mov.w r9, #1 8003d1c: 464b mov r3, r9 8003d1e: f8cd 9020 str.w r9, [sp, #32] 8003d22: f8cd 908c str.w r9, [sp, #140] ; 0x8c 8003d26: 2200 movs r2, #0 8003d28: 6a68 ldr r0, [r5, #36] ; 0x24 8003d2a: 6042 str r2, [r0, #4] 8003d2c: 2204 movs r2, #4 8003d2e: f102 0614 add.w r6, r2, #20 8003d32: 429e cmp r6, r3 8003d34: 6841 ldr r1, [r0, #4] 8003d36: d94e bls.n 8003dd6 <_dtoa_r+0x316> 8003d38: 4628 mov r0, r5 8003d3a: f000 fcd7 bl 80046ec <_Balloc> 8003d3e: 9003 str r0, [sp, #12] 8003d40: 2800 cmp r0, #0 8003d42: d14c bne.n 8003dde <_dtoa_r+0x31e> 8003d44: 4602 mov r2, r0 8003d46: f44f 71d5 mov.w r1, #426 ; 0x1aa 8003d4a: 4b17 ldr r3, [pc, #92] ; (8003da8 <_dtoa_r+0x2e8>) 8003d4c: e6cc b.n 8003ae8 <_dtoa_r+0x28> 8003d4e: 2301 movs r3, #1 8003d50: e7de b.n 8003d10 <_dtoa_r+0x250> 8003d52: 2300 movs r3, #0 8003d54: 930b str r3, [sp, #44] ; 0x2c 8003d56: 9b23 ldr r3, [sp, #140] ; 0x8c 8003d58: eb0a 0903 add.w r9, sl, r3 8003d5c: f109 0301 add.w r3, r9, #1 8003d60: 2b01 cmp r3, #1 8003d62: 9308 str r3, [sp, #32] 8003d64: bfb8 it lt 8003d66: 2301 movlt r3, #1 8003d68: e7dd b.n 8003d26 <_dtoa_r+0x266> 8003d6a: 2301 movs r3, #1 8003d6c: e7f2 b.n 8003d54 <_dtoa_r+0x294> 8003d6e: bf00 nop 8003d70: 636f4361 .word 0x636f4361 8003d74: 3fd287a7 .word 0x3fd287a7 8003d78: 8b60c8b3 .word 0x8b60c8b3 8003d7c: 3fc68a28 .word 0x3fc68a28 8003d80: 509f79fb .word 0x509f79fb 8003d84: 3fd34413 .word 0x3fd34413 8003d88: 080062bd .word 0x080062bd 8003d8c: 080062d4 .word 0x080062d4 8003d90: 7ff00000 .word 0x7ff00000 8003d94: 080062b9 .word 0x080062b9 8003d98: 080062b0 .word 0x080062b0 8003d9c: 0800628d .word 0x0800628d 8003da0: 3ff80000 .word 0x3ff80000 8003da4: 080063c8 .word 0x080063c8 8003da8: 0800632f .word 0x0800632f 8003dac: 2401 movs r4, #1 8003dae: 2300 movs r3, #0 8003db0: 940b str r4, [sp, #44] ; 0x2c 8003db2: 9322 str r3, [sp, #136] ; 0x88 8003db4: f04f 39ff mov.w r9, #4294967295 8003db8: 2200 movs r2, #0 8003dba: 2312 movs r3, #18 8003dbc: f8cd 9020 str.w r9, [sp, #32] 8003dc0: 9223 str r2, [sp, #140] ; 0x8c 8003dc2: e7b0 b.n 8003d26 <_dtoa_r+0x266> 8003dc4: 2301 movs r3, #1 8003dc6: 930b str r3, [sp, #44] ; 0x2c 8003dc8: e7f4 b.n 8003db4 <_dtoa_r+0x2f4> 8003dca: f8dd 908c ldr.w r9, [sp, #140] ; 0x8c 8003dce: 464b mov r3, r9 8003dd0: f8cd 9020 str.w r9, [sp, #32] 8003dd4: e7a7 b.n 8003d26 <_dtoa_r+0x266> 8003dd6: 3101 adds r1, #1 8003dd8: 6041 str r1, [r0, #4] 8003dda: 0052 lsls r2, r2, #1 8003ddc: e7a7 b.n 8003d2e <_dtoa_r+0x26e> 8003dde: 6a6b ldr r3, [r5, #36] ; 0x24 8003de0: 9a03 ldr r2, [sp, #12] 8003de2: 601a str r2, [r3, #0] 8003de4: 9b08 ldr r3, [sp, #32] 8003de6: 2b0e cmp r3, #14 8003de8: f200 80a8 bhi.w 8003f3c <_dtoa_r+0x47c> 8003dec: 2c00 cmp r4, #0 8003dee: f000 80a5 beq.w 8003f3c <_dtoa_r+0x47c> 8003df2: f1ba 0f00 cmp.w sl, #0 8003df6: dd34 ble.n 8003e62 <_dtoa_r+0x3a2> 8003df8: 4a9a ldr r2, [pc, #616] ; (8004064 <_dtoa_r+0x5a4>) 8003dfa: f00a 030f and.w r3, sl, #15 8003dfe: eb02 03c3 add.w r3, r2, r3, lsl #3 8003e02: f41a 7f80 tst.w sl, #256 ; 0x100 8003e06: e9d3 3400 ldrd r3, r4, [r3] 8003e0a: e9cd 3410 strd r3, r4, [sp, #64] ; 0x40 8003e0e: ea4f 142a mov.w r4, sl, asr #4 8003e12: d016 beq.n 8003e42 <_dtoa_r+0x382> 8003e14: e9dd 010c ldrd r0, r1, [sp, #48] ; 0x30 8003e18: 4b93 ldr r3, [pc, #588] ; (8004068 <_dtoa_r+0x5a8>) 8003e1a: 2703 movs r7, #3 8003e1c: e9d3 2308 ldrd r2, r3, [r3, #32] 8003e20: f7fc fc84 bl 800072c <__aeabi_ddiv> 8003e24: e9cd 0104 strd r0, r1, [sp, #16] 8003e28: f004 040f and.w r4, r4, #15 8003e2c: 4e8e ldr r6, [pc, #568] ; (8004068 <_dtoa_r+0x5a8>) 8003e2e: b954 cbnz r4, 8003e46 <_dtoa_r+0x386> 8003e30: e9dd 2310 ldrd r2, r3, [sp, #64] ; 0x40 8003e34: e9dd 0104 ldrd r0, r1, [sp, #16] 8003e38: f7fc fc78 bl 800072c <__aeabi_ddiv> 8003e3c: e9cd 0104 strd r0, r1, [sp, #16] 8003e40: e029 b.n 8003e96 <_dtoa_r+0x3d6> 8003e42: 2702 movs r7, #2 8003e44: e7f2 b.n 8003e2c <_dtoa_r+0x36c> 8003e46: 07e1 lsls r1, r4, #31 8003e48: d508 bpl.n 8003e5c <_dtoa_r+0x39c> 8003e4a: e9dd 0110 ldrd r0, r1, [sp, #64] ; 0x40 8003e4e: e9d6 2300 ldrd r2, r3, [r6] 8003e52: f7fc fb41 bl 80004d8 <__aeabi_dmul> 8003e56: e9cd 0110 strd r0, r1, [sp, #64] ; 0x40 8003e5a: 3701 adds r7, #1 8003e5c: 1064 asrs r4, r4, #1 8003e5e: 3608 adds r6, #8 8003e60: e7e5 b.n 8003e2e <_dtoa_r+0x36e> 8003e62: f000 80a5 beq.w 8003fb0 <_dtoa_r+0x4f0> 8003e66: e9dd 010c ldrd r0, r1, [sp, #48] ; 0x30 8003e6a: f1ca 0400 rsb r4, sl, #0 8003e6e: 4b7d ldr r3, [pc, #500] ; (8004064 <_dtoa_r+0x5a4>) 8003e70: f004 020f and.w r2, r4, #15 8003e74: eb03 03c2 add.w r3, r3, r2, lsl #3 8003e78: e9d3 2300 ldrd r2, r3, [r3] 8003e7c: f7fc fb2c bl 80004d8 <__aeabi_dmul> 8003e80: 2702 movs r7, #2 8003e82: 2300 movs r3, #0 8003e84: e9cd 0104 strd r0, r1, [sp, #16] 8003e88: 4e77 ldr r6, [pc, #476] ; (8004068 <_dtoa_r+0x5a8>) 8003e8a: 1124 asrs r4, r4, #4 8003e8c: 2c00 cmp r4, #0 8003e8e: f040 8084 bne.w 8003f9a <_dtoa_r+0x4da> 8003e92: 2b00 cmp r3, #0 8003e94: d1d2 bne.n 8003e3c <_dtoa_r+0x37c> 8003e96: 9b0f ldr r3, [sp, #60] ; 0x3c 8003e98: 2b00 cmp r3, #0 8003e9a: f000 808b beq.w 8003fb4 <_dtoa_r+0x4f4> 8003e9e: e9dd 3404 ldrd r3, r4, [sp, #16] 8003ea2: e9cd 3410 strd r3, r4, [sp, #64] ; 0x40 8003ea6: e9dd 0110 ldrd r0, r1, [sp, #64] ; 0x40 8003eaa: 2200 movs r2, #0 8003eac: 4b6f ldr r3, [pc, #444] ; (800406c <_dtoa_r+0x5ac>) 8003eae: f7fc fd85 bl 80009bc <__aeabi_dcmplt> 8003eb2: 2800 cmp r0, #0 8003eb4: d07e beq.n 8003fb4 <_dtoa_r+0x4f4> 8003eb6: 9b08 ldr r3, [sp, #32] 8003eb8: 2b00 cmp r3, #0 8003eba: d07b beq.n 8003fb4 <_dtoa_r+0x4f4> 8003ebc: f1b9 0f00 cmp.w r9, #0 8003ec0: dd38 ble.n 8003f34 <_dtoa_r+0x474> 8003ec2: e9dd 0110 ldrd r0, r1, [sp, #64] ; 0x40 8003ec6: 2200 movs r2, #0 8003ec8: 4b69 ldr r3, [pc, #420] ; (8004070 <_dtoa_r+0x5b0>) 8003eca: f7fc fb05 bl 80004d8 <__aeabi_dmul> 8003ece: 464c mov r4, r9 8003ed0: e9cd 0104 strd r0, r1, [sp, #16] 8003ed4: f10a 38ff add.w r8, sl, #4294967295 8003ed8: 3701 adds r7, #1 8003eda: 4638 mov r0, r7 8003edc: f7fc fa92 bl 8000404 <__aeabi_i2d> 8003ee0: e9dd 2304 ldrd r2, r3, [sp, #16] 8003ee4: f7fc faf8 bl 80004d8 <__aeabi_dmul> 8003ee8: 2200 movs r2, #0 8003eea: 4b62 ldr r3, [pc, #392] ; (8004074 <_dtoa_r+0x5b4>) 8003eec: f7fc f93e bl 800016c <__adddf3> 8003ef0: f1a1 7650 sub.w r6, r1, #54525952 ; 0x3400000 8003ef4: e9cd 0110 strd r0, r1, [sp, #64] ; 0x40 8003ef8: 9611 str r6, [sp, #68] ; 0x44 8003efa: 2c00 cmp r4, #0 8003efc: d15d bne.n 8003fba <_dtoa_r+0x4fa> 8003efe: e9dd 0104 ldrd r0, r1, [sp, #16] 8003f02: 2200 movs r2, #0 8003f04: 4b5c ldr r3, [pc, #368] ; (8004078 <_dtoa_r+0x5b8>) 8003f06: f7fc f92f bl 8000168 <__aeabi_dsub> 8003f0a: 4602 mov r2, r0 8003f0c: 460b mov r3, r1 8003f0e: e9cd 2304 strd r2, r3, [sp, #16] 8003f12: 4633 mov r3, r6 8003f14: 9a10 ldr r2, [sp, #64] ; 0x40 8003f16: f7fc fd6f bl 80009f8 <__aeabi_dcmpgt> 8003f1a: 2800 cmp r0, #0 8003f1c: f040 829c bne.w 8004458 <_dtoa_r+0x998> 8003f20: e9dd 0104 ldrd r0, r1, [sp, #16] 8003f24: 9a10 ldr r2, [sp, #64] ; 0x40 8003f26: f106 4300 add.w r3, r6, #2147483648 ; 0x80000000 8003f2a: f7fc fd47 bl 80009bc <__aeabi_dcmplt> 8003f2e: 2800 cmp r0, #0 8003f30: f040 8290 bne.w 8004454 <_dtoa_r+0x994> 8003f34: e9dd 340c ldrd r3, r4, [sp, #48] ; 0x30 8003f38: e9cd 3404 strd r3, r4, [sp, #16] 8003f3c: 9b17 ldr r3, [sp, #92] ; 0x5c 8003f3e: 2b00 cmp r3, #0 8003f40: f2c0 8152 blt.w 80041e8 <_dtoa_r+0x728> 8003f44: f1ba 0f0e cmp.w sl, #14 8003f48: f300 814e bgt.w 80041e8 <_dtoa_r+0x728> 8003f4c: 4b45 ldr r3, [pc, #276] ; (8004064 <_dtoa_r+0x5a4>) 8003f4e: eb03 03ca add.w r3, r3, sl, lsl #3 8003f52: e9d3 3400 ldrd r3, r4, [r3] 8003f56: e9cd 3406 strd r3, r4, [sp, #24] 8003f5a: 9b23 ldr r3, [sp, #140] ; 0x8c 8003f5c: 2b00 cmp r3, #0 8003f5e: f280 80db bge.w 8004118 <_dtoa_r+0x658> 8003f62: 9b08 ldr r3, [sp, #32] 8003f64: 2b00 cmp r3, #0 8003f66: f300 80d7 bgt.w 8004118 <_dtoa_r+0x658> 8003f6a: f040 8272 bne.w 8004452 <_dtoa_r+0x992> 8003f6e: e9dd 0106 ldrd r0, r1, [sp, #24] 8003f72: 2200 movs r2, #0 8003f74: 4b40 ldr r3, [pc, #256] ; (8004078 <_dtoa_r+0x5b8>) 8003f76: f7fc faaf bl 80004d8 <__aeabi_dmul> 8003f7a: e9dd 2304 ldrd r2, r3, [sp, #16] 8003f7e: f7fc fd31 bl 80009e4 <__aeabi_dcmpge> 8003f82: 9c08 ldr r4, [sp, #32] 8003f84: 4626 mov r6, r4 8003f86: 2800 cmp r0, #0 8003f88: f040 8248 bne.w 800441c <_dtoa_r+0x95c> 8003f8c: 2331 movs r3, #49 ; 0x31 8003f8e: 9f03 ldr r7, [sp, #12] 8003f90: f10a 0a01 add.w sl, sl, #1 8003f94: f807 3b01 strb.w r3, [r7], #1 8003f98: e244 b.n 8004424 <_dtoa_r+0x964> 8003f9a: 07e2 lsls r2, r4, #31 8003f9c: d505 bpl.n 8003faa <_dtoa_r+0x4ea> 8003f9e: e9d6 2300 ldrd r2, r3, [r6] 8003fa2: f7fc fa99 bl 80004d8 <__aeabi_dmul> 8003fa6: 2301 movs r3, #1 8003fa8: 3701 adds r7, #1 8003faa: 1064 asrs r4, r4, #1 8003fac: 3608 adds r6, #8 8003fae: e76d b.n 8003e8c <_dtoa_r+0x3cc> 8003fb0: 2702 movs r7, #2 8003fb2: e770 b.n 8003e96 <_dtoa_r+0x3d6> 8003fb4: 46d0 mov r8, sl 8003fb6: 9c08 ldr r4, [sp, #32] 8003fb8: e78f b.n 8003eda <_dtoa_r+0x41a> 8003fba: 9903 ldr r1, [sp, #12] 8003fbc: 4b29 ldr r3, [pc, #164] ; (8004064 <_dtoa_r+0x5a4>) 8003fbe: 4421 add r1, r4 8003fc0: 9112 str r1, [sp, #72] ; 0x48 8003fc2: 990b ldr r1, [sp, #44] ; 0x2c 8003fc4: eb03 03c4 add.w r3, r3, r4, lsl #3 8003fc8: e9dd 6710 ldrd r6, r7, [sp, #64] ; 0x40 8003fcc: e953 2302 ldrd r2, r3, [r3, #-8] 8003fd0: 2900 cmp r1, #0 8003fd2: d055 beq.n 8004080 <_dtoa_r+0x5c0> 8003fd4: 2000 movs r0, #0 8003fd6: 4929 ldr r1, [pc, #164] ; (800407c <_dtoa_r+0x5bc>) 8003fd8: f7fc fba8 bl 800072c <__aeabi_ddiv> 8003fdc: 463b mov r3, r7 8003fde: 4632 mov r2, r6 8003fe0: f7fc f8c2 bl 8000168 <__aeabi_dsub> 8003fe4: e9cd 0110 strd r0, r1, [sp, #64] ; 0x40 8003fe8: 9f03 ldr r7, [sp, #12] 8003fea: e9dd 0104 ldrd r0, r1, [sp, #16] 8003fee: f7fc fd23 bl 8000a38 <__aeabi_d2iz> 8003ff2: 4604 mov r4, r0 8003ff4: f7fc fa06 bl 8000404 <__aeabi_i2d> 8003ff8: 4602 mov r2, r0 8003ffa: 460b mov r3, r1 8003ffc: e9dd 0104 ldrd r0, r1, [sp, #16] 8004000: f7fc f8b2 bl 8000168 <__aeabi_dsub> 8004004: 4602 mov r2, r0 8004006: 460b mov r3, r1 8004008: 3430 adds r4, #48 ; 0x30 800400a: e9cd 2304 strd r2, r3, [sp, #16] 800400e: e9dd 2310 ldrd r2, r3, [sp, #64] ; 0x40 8004012: f807 4b01 strb.w r4, [r7], #1 8004016: f7fc fcd1 bl 80009bc <__aeabi_dcmplt> 800401a: 2800 cmp r0, #0 800401c: d174 bne.n 8004108 <_dtoa_r+0x648> 800401e: e9dd 2304 ldrd r2, r3, [sp, #16] 8004022: 2000 movs r0, #0 8004024: 4911 ldr r1, [pc, #68] ; (800406c <_dtoa_r+0x5ac>) 8004026: f7fc f89f bl 8000168 <__aeabi_dsub> 800402a: e9dd 2310 ldrd r2, r3, [sp, #64] ; 0x40 800402e: f7fc fcc5 bl 80009bc <__aeabi_dcmplt> 8004032: 2800 cmp r0, #0 8004034: f040 80b7 bne.w 80041a6 <_dtoa_r+0x6e6> 8004038: 9b12 ldr r3, [sp, #72] ; 0x48 800403a: 429f cmp r7, r3 800403c: f43f af7a beq.w 8003f34 <_dtoa_r+0x474> 8004040: e9dd 0110 ldrd r0, r1, [sp, #64] ; 0x40 8004044: 2200 movs r2, #0 8004046: 4b0a ldr r3, [pc, #40] ; (8004070 <_dtoa_r+0x5b0>) 8004048: f7fc fa46 bl 80004d8 <__aeabi_dmul> 800404c: 2200 movs r2, #0 800404e: e9cd 0110 strd r0, r1, [sp, #64] ; 0x40 8004052: e9dd 0104 ldrd r0, r1, [sp, #16] 8004056: 4b06 ldr r3, [pc, #24] ; (8004070 <_dtoa_r+0x5b0>) 8004058: f7fc fa3e bl 80004d8 <__aeabi_dmul> 800405c: e9cd 0104 strd r0, r1, [sp, #16] 8004060: e7c3 b.n 8003fea <_dtoa_r+0x52a> 8004062: bf00 nop 8004064: 080063c8 .word 0x080063c8 8004068: 080063a0 .word 0x080063a0 800406c: 3ff00000 .word 0x3ff00000 8004070: 40240000 .word 0x40240000 8004074: 401c0000 .word 0x401c0000 8004078: 40140000 .word 0x40140000 800407c: 3fe00000 .word 0x3fe00000 8004080: 4630 mov r0, r6 8004082: 4639 mov r1, r7 8004084: f7fc fa28 bl 80004d8 <__aeabi_dmul> 8004088: 9b12 ldr r3, [sp, #72] ; 0x48 800408a: e9cd 0110 strd r0, r1, [sp, #64] ; 0x40 800408e: 9c03 ldr r4, [sp, #12] 8004090: 9314 str r3, [sp, #80] ; 0x50 8004092: e9dd 0104 ldrd r0, r1, [sp, #16] 8004096: f7fc fccf bl 8000a38 <__aeabi_d2iz> 800409a: 9015 str r0, [sp, #84] ; 0x54 800409c: f7fc f9b2 bl 8000404 <__aeabi_i2d> 80040a0: 4602 mov r2, r0 80040a2: 460b mov r3, r1 80040a4: e9dd 0104 ldrd r0, r1, [sp, #16] 80040a8: f7fc f85e bl 8000168 <__aeabi_dsub> 80040ac: 9b15 ldr r3, [sp, #84] ; 0x54 80040ae: 4606 mov r6, r0 80040b0: 3330 adds r3, #48 ; 0x30 80040b2: f804 3b01 strb.w r3, [r4], #1 80040b6: 9b12 ldr r3, [sp, #72] ; 0x48 80040b8: 460f mov r7, r1 80040ba: 429c cmp r4, r3 80040bc: f04f 0200 mov.w r2, #0 80040c0: d124 bne.n 800410c <_dtoa_r+0x64c> 80040c2: e9dd 0110 ldrd r0, r1, [sp, #64] ; 0x40 80040c6: 4bb0 ldr r3, [pc, #704] ; (8004388 <_dtoa_r+0x8c8>) 80040c8: f7fc f850 bl 800016c <__adddf3> 80040cc: 4602 mov r2, r0 80040ce: 460b mov r3, r1 80040d0: 4630 mov r0, r6 80040d2: 4639 mov r1, r7 80040d4: f7fc fc90 bl 80009f8 <__aeabi_dcmpgt> 80040d8: 2800 cmp r0, #0 80040da: d163 bne.n 80041a4 <_dtoa_r+0x6e4> 80040dc: e9dd 2310 ldrd r2, r3, [sp, #64] ; 0x40 80040e0: 2000 movs r0, #0 80040e2: 49a9 ldr r1, [pc, #676] ; (8004388 <_dtoa_r+0x8c8>) 80040e4: f7fc f840 bl 8000168 <__aeabi_dsub> 80040e8: 4602 mov r2, r0 80040ea: 460b mov r3, r1 80040ec: 4630 mov r0, r6 80040ee: 4639 mov r1, r7 80040f0: f7fc fc64 bl 80009bc <__aeabi_dcmplt> 80040f4: 2800 cmp r0, #0 80040f6: f43f af1d beq.w 8003f34 <_dtoa_r+0x474> 80040fa: 9f14 ldr r7, [sp, #80] ; 0x50 80040fc: 1e7b subs r3, r7, #1 80040fe: 9314 str r3, [sp, #80] ; 0x50 8004100: f817 3c01 ldrb.w r3, [r7, #-1] 8004104: 2b30 cmp r3, #48 ; 0x30 8004106: d0f8 beq.n 80040fa <_dtoa_r+0x63a> 8004108: 46c2 mov sl, r8 800410a: e03b b.n 8004184 <_dtoa_r+0x6c4> 800410c: 4b9f ldr r3, [pc, #636] ; (800438c <_dtoa_r+0x8cc>) 800410e: f7fc f9e3 bl 80004d8 <__aeabi_dmul> 8004112: e9cd 0104 strd r0, r1, [sp, #16] 8004116: e7bc b.n 8004092 <_dtoa_r+0x5d2> 8004118: 9f03 ldr r7, [sp, #12] 800411a: e9dd 8904 ldrd r8, r9, [sp, #16] 800411e: e9dd 2306 ldrd r2, r3, [sp, #24] 8004122: 4640 mov r0, r8 8004124: 4649 mov r1, r9 8004126: f7fc fb01 bl 800072c <__aeabi_ddiv> 800412a: f7fc fc85 bl 8000a38 <__aeabi_d2iz> 800412e: 4604 mov r4, r0 8004130: f7fc f968 bl 8000404 <__aeabi_i2d> 8004134: e9dd 2306 ldrd r2, r3, [sp, #24] 8004138: f7fc f9ce bl 80004d8 <__aeabi_dmul> 800413c: 4602 mov r2, r0 800413e: 460b mov r3, r1 8004140: 4640 mov r0, r8 8004142: 4649 mov r1, r9 8004144: f7fc f810 bl 8000168 <__aeabi_dsub> 8004148: f104 0630 add.w r6, r4, #48 ; 0x30 800414c: f807 6b01 strb.w r6, [r7], #1 8004150: 9e03 ldr r6, [sp, #12] 8004152: f8dd c020 ldr.w ip, [sp, #32] 8004156: 1bbe subs r6, r7, r6 8004158: 45b4 cmp ip, r6 800415a: 4602 mov r2, r0 800415c: 460b mov r3, r1 800415e: d136 bne.n 80041ce <_dtoa_r+0x70e> 8004160: f7fc f804 bl 800016c <__adddf3> 8004164: e9dd 2306 ldrd r2, r3, [sp, #24] 8004168: 4680 mov r8, r0 800416a: 4689 mov r9, r1 800416c: f7fc fc44 bl 80009f8 <__aeabi_dcmpgt> 8004170: bb58 cbnz r0, 80041ca <_dtoa_r+0x70a> 8004172: e9dd 2306 ldrd r2, r3, [sp, #24] 8004176: 4640 mov r0, r8 8004178: 4649 mov r1, r9 800417a: f7fc fc15 bl 80009a8 <__aeabi_dcmpeq> 800417e: b108 cbz r0, 8004184 <_dtoa_r+0x6c4> 8004180: 07e1 lsls r1, r4, #31 8004182: d422 bmi.n 80041ca <_dtoa_r+0x70a> 8004184: 4628 mov r0, r5 8004186: 4659 mov r1, fp 8004188: f000 faf0 bl 800476c <_Bfree> 800418c: 2300 movs r3, #0 800418e: 703b strb r3, [r7, #0] 8004190: 9b24 ldr r3, [sp, #144] ; 0x90 8004192: f10a 0001 add.w r0, sl, #1 8004196: 6018 str r0, [r3, #0] 8004198: 9b26 ldr r3, [sp, #152] ; 0x98 800419a: 2b00 cmp r3, #0 800419c: f43f acde beq.w 8003b5c <_dtoa_r+0x9c> 80041a0: 601f str r7, [r3, #0] 80041a2: e4db b.n 8003b5c <_dtoa_r+0x9c> 80041a4: 4627 mov r7, r4 80041a6: 463b mov r3, r7 80041a8: 461f mov r7, r3 80041aa: f813 2d01 ldrb.w r2, [r3, #-1]! 80041ae: 2a39 cmp r2, #57 ; 0x39 80041b0: d107 bne.n 80041c2 <_dtoa_r+0x702> 80041b2: 9a03 ldr r2, [sp, #12] 80041b4: 429a cmp r2, r3 80041b6: d1f7 bne.n 80041a8 <_dtoa_r+0x6e8> 80041b8: 2230 movs r2, #48 ; 0x30 80041ba: 9903 ldr r1, [sp, #12] 80041bc: f108 0801 add.w r8, r8, #1 80041c0: 700a strb r2, [r1, #0] 80041c2: 781a ldrb r2, [r3, #0] 80041c4: 3201 adds r2, #1 80041c6: 701a strb r2, [r3, #0] 80041c8: e79e b.n 8004108 <_dtoa_r+0x648> 80041ca: 46d0 mov r8, sl 80041cc: e7eb b.n 80041a6 <_dtoa_r+0x6e6> 80041ce: 2200 movs r2, #0 80041d0: 4b6e ldr r3, [pc, #440] ; (800438c <_dtoa_r+0x8cc>) 80041d2: f7fc f981 bl 80004d8 <__aeabi_dmul> 80041d6: 2200 movs r2, #0 80041d8: 2300 movs r3, #0 80041da: 4680 mov r8, r0 80041dc: 4689 mov r9, r1 80041de: f7fc fbe3 bl 80009a8 <__aeabi_dcmpeq> 80041e2: 2800 cmp r0, #0 80041e4: d09b beq.n 800411e <_dtoa_r+0x65e> 80041e6: e7cd b.n 8004184 <_dtoa_r+0x6c4> 80041e8: 9a0b ldr r2, [sp, #44] ; 0x2c 80041ea: 2a00 cmp r2, #0 80041ec: f000 80d0 beq.w 8004390 <_dtoa_r+0x8d0> 80041f0: 9a22 ldr r2, [sp, #136] ; 0x88 80041f2: 2a01 cmp r2, #1 80041f4: f300 80ae bgt.w 8004354 <_dtoa_r+0x894> 80041f8: 9a13 ldr r2, [sp, #76] ; 0x4c 80041fa: 2a00 cmp r2, #0 80041fc: f000 80a6 beq.w 800434c <_dtoa_r+0x88c> 8004200: f203 4333 addw r3, r3, #1075 ; 0x433 8004204: 9c0a ldr r4, [sp, #40] ; 0x28 8004206: 9f06 ldr r7, [sp, #24] 8004208: 9a06 ldr r2, [sp, #24] 800420a: 2101 movs r1, #1 800420c: 441a add r2, r3 800420e: 9206 str r2, [sp, #24] 8004210: 9a09 ldr r2, [sp, #36] ; 0x24 8004212: 4628 mov r0, r5 8004214: 441a add r2, r3 8004216: 9209 str r2, [sp, #36] ; 0x24 8004218: f000 fb5e bl 80048d8 <__i2b> 800421c: 4606 mov r6, r0 800421e: 2f00 cmp r7, #0 8004220: dd0c ble.n 800423c <_dtoa_r+0x77c> 8004222: 9b09 ldr r3, [sp, #36] ; 0x24 8004224: 2b00 cmp r3, #0 8004226: dd09 ble.n 800423c <_dtoa_r+0x77c> 8004228: 42bb cmp r3, r7 800422a: bfa8 it ge 800422c: 463b movge r3, r7 800422e: 9a06 ldr r2, [sp, #24] 8004230: 1aff subs r7, r7, r3 8004232: 1ad2 subs r2, r2, r3 8004234: 9206 str r2, [sp, #24] 8004236: 9a09 ldr r2, [sp, #36] ; 0x24 8004238: 1ad3 subs r3, r2, r3 800423a: 9309 str r3, [sp, #36] ; 0x24 800423c: 9b0a ldr r3, [sp, #40] ; 0x28 800423e: b1f3 cbz r3, 800427e <_dtoa_r+0x7be> 8004240: 9b0b ldr r3, [sp, #44] ; 0x2c 8004242: 2b00 cmp r3, #0 8004244: f000 80a8 beq.w 8004398 <_dtoa_r+0x8d8> 8004248: 2c00 cmp r4, #0 800424a: dd10 ble.n 800426e <_dtoa_r+0x7ae> 800424c: 4631 mov r1, r6 800424e: 4622 mov r2, r4 8004250: 4628 mov r0, r5 8004252: f000 fbff bl 8004a54 <__pow5mult> 8004256: 465a mov r2, fp 8004258: 4601 mov r1, r0 800425a: 4606 mov r6, r0 800425c: 4628 mov r0, r5 800425e: f000 fb51 bl 8004904 <__multiply> 8004262: 4680 mov r8, r0 8004264: 4659 mov r1, fp 8004266: 4628 mov r0, r5 8004268: f000 fa80 bl 800476c <_Bfree> 800426c: 46c3 mov fp, r8 800426e: 9b0a ldr r3, [sp, #40] ; 0x28 8004270: 1b1a subs r2, r3, r4 8004272: d004 beq.n 800427e <_dtoa_r+0x7be> 8004274: 4659 mov r1, fp 8004276: 4628 mov r0, r5 8004278: f000 fbec bl 8004a54 <__pow5mult> 800427c: 4683 mov fp, r0 800427e: 2101 movs r1, #1 8004280: 4628 mov r0, r5 8004282: f000 fb29 bl 80048d8 <__i2b> 8004286: 9b0e ldr r3, [sp, #56] ; 0x38 8004288: 4604 mov r4, r0 800428a: 2b00 cmp r3, #0 800428c: f340 8086 ble.w 800439c <_dtoa_r+0x8dc> 8004290: 461a mov r2, r3 8004292: 4601 mov r1, r0 8004294: 4628 mov r0, r5 8004296: f000 fbdd bl 8004a54 <__pow5mult> 800429a: 9b22 ldr r3, [sp, #136] ; 0x88 800429c: 4604 mov r4, r0 800429e: 2b01 cmp r3, #1 80042a0: dd7f ble.n 80043a2 <_dtoa_r+0x8e2> 80042a2: f04f 0800 mov.w r8, #0 80042a6: 6923 ldr r3, [r4, #16] 80042a8: eb04 0383 add.w r3, r4, r3, lsl #2 80042ac: 6918 ldr r0, [r3, #16] 80042ae: f000 fac5 bl 800483c <__hi0bits> 80042b2: f1c0 0020 rsb r0, r0, #32 80042b6: 9b09 ldr r3, [sp, #36] ; 0x24 80042b8: 4418 add r0, r3 80042ba: f010 001f ands.w r0, r0, #31 80042be: f000 8092 beq.w 80043e6 <_dtoa_r+0x926> 80042c2: f1c0 0320 rsb r3, r0, #32 80042c6: 2b04 cmp r3, #4 80042c8: f340 808a ble.w 80043e0 <_dtoa_r+0x920> 80042cc: f1c0 001c rsb r0, r0, #28 80042d0: 9b06 ldr r3, [sp, #24] 80042d2: 4407 add r7, r0 80042d4: 4403 add r3, r0 80042d6: 9306 str r3, [sp, #24] 80042d8: 9b09 ldr r3, [sp, #36] ; 0x24 80042da: 4403 add r3, r0 80042dc: 9309 str r3, [sp, #36] ; 0x24 80042de: 9b06 ldr r3, [sp, #24] 80042e0: 2b00 cmp r3, #0 80042e2: dd05 ble.n 80042f0 <_dtoa_r+0x830> 80042e4: 4659 mov r1, fp 80042e6: 461a mov r2, r3 80042e8: 4628 mov r0, r5 80042ea: f000 fc0d bl 8004b08 <__lshift> 80042ee: 4683 mov fp, r0 80042f0: 9b09 ldr r3, [sp, #36] ; 0x24 80042f2: 2b00 cmp r3, #0 80042f4: dd05 ble.n 8004302 <_dtoa_r+0x842> 80042f6: 4621 mov r1, r4 80042f8: 461a mov r2, r3 80042fa: 4628 mov r0, r5 80042fc: f000 fc04 bl 8004b08 <__lshift> 8004300: 4604 mov r4, r0 8004302: 9b0f ldr r3, [sp, #60] ; 0x3c 8004304: 2b00 cmp r3, #0 8004306: d070 beq.n 80043ea <_dtoa_r+0x92a> 8004308: 4621 mov r1, r4 800430a: 4658 mov r0, fp 800430c: f000 fc6c bl 8004be8 <__mcmp> 8004310: 2800 cmp r0, #0 8004312: da6a bge.n 80043ea <_dtoa_r+0x92a> 8004314: 2300 movs r3, #0 8004316: 4659 mov r1, fp 8004318: 220a movs r2, #10 800431a: 4628 mov r0, r5 800431c: f000 fa48 bl 80047b0 <__multadd> 8004320: 9b0b ldr r3, [sp, #44] ; 0x2c 8004322: 4683 mov fp, r0 8004324: f10a 3aff add.w sl, sl, #4294967295 8004328: 2b00 cmp r3, #0 800432a: f000 8194 beq.w 8004656 <_dtoa_r+0xb96> 800432e: 4631 mov r1, r6 8004330: 2300 movs r3, #0 8004332: 220a movs r2, #10 8004334: 4628 mov r0, r5 8004336: f000 fa3b bl 80047b0 <__multadd> 800433a: f1b9 0f00 cmp.w r9, #0 800433e: 4606 mov r6, r0 8004340: f300 8093 bgt.w 800446a <_dtoa_r+0x9aa> 8004344: 9b22 ldr r3, [sp, #136] ; 0x88 8004346: 2b02 cmp r3, #2 8004348: dc57 bgt.n 80043fa <_dtoa_r+0x93a> 800434a: e08e b.n 800446a <_dtoa_r+0x9aa> 800434c: 9b16 ldr r3, [sp, #88] ; 0x58 800434e: f1c3 0336 rsb r3, r3, #54 ; 0x36 8004352: e757 b.n 8004204 <_dtoa_r+0x744> 8004354: 9b08 ldr r3, [sp, #32] 8004356: 1e5c subs r4, r3, #1 8004358: 9b0a ldr r3, [sp, #40] ; 0x28 800435a: 42a3 cmp r3, r4 800435c: bfb7 itett lt 800435e: 9b0a ldrlt r3, [sp, #40] ; 0x28 8004360: 1b1c subge r4, r3, r4 8004362: 1ae2 sublt r2, r4, r3 8004364: 9b0e ldrlt r3, [sp, #56] ; 0x38 8004366: bfbe ittt lt 8004368: 940a strlt r4, [sp, #40] ; 0x28 800436a: 189b addlt r3, r3, r2 800436c: 930e strlt r3, [sp, #56] ; 0x38 800436e: 9b08 ldr r3, [sp, #32] 8004370: bfb8 it lt 8004372: 2400 movlt r4, #0 8004374: 2b00 cmp r3, #0 8004376: bfbb ittet lt 8004378: 9b06 ldrlt r3, [sp, #24] 800437a: 9a08 ldrlt r2, [sp, #32] 800437c: 9f06 ldrge r7, [sp, #24] 800437e: 1a9f sublt r7, r3, r2 8004380: bfac ite ge 8004382: 9b08 ldrge r3, [sp, #32] 8004384: 2300 movlt r3, #0 8004386: e73f b.n 8004208 <_dtoa_r+0x748> 8004388: 3fe00000 .word 0x3fe00000 800438c: 40240000 .word 0x40240000 8004390: 9c0a ldr r4, [sp, #40] ; 0x28 8004392: 9f06 ldr r7, [sp, #24] 8004394: 9e0b ldr r6, [sp, #44] ; 0x2c 8004396: e742 b.n 800421e <_dtoa_r+0x75e> 8004398: 9a0a ldr r2, [sp, #40] ; 0x28 800439a: e76b b.n 8004274 <_dtoa_r+0x7b4> 800439c: 9b22 ldr r3, [sp, #136] ; 0x88 800439e: 2b01 cmp r3, #1 80043a0: dc19 bgt.n 80043d6 <_dtoa_r+0x916> 80043a2: 9b04 ldr r3, [sp, #16] 80043a4: b9bb cbnz r3, 80043d6 <_dtoa_r+0x916> 80043a6: 9b05 ldr r3, [sp, #20] 80043a8: f3c3 0313 ubfx r3, r3, #0, #20 80043ac: b99b cbnz r3, 80043d6 <_dtoa_r+0x916> 80043ae: 9b05 ldr r3, [sp, #20] 80043b0: f023 4300 bic.w r3, r3, #2147483648 ; 0x80000000 80043b4: 0d1b lsrs r3, r3, #20 80043b6: 051b lsls r3, r3, #20 80043b8: b183 cbz r3, 80043dc <_dtoa_r+0x91c> 80043ba: f04f 0801 mov.w r8, #1 80043be: 9b06 ldr r3, [sp, #24] 80043c0: 3301 adds r3, #1 80043c2: 9306 str r3, [sp, #24] 80043c4: 9b09 ldr r3, [sp, #36] ; 0x24 80043c6: 3301 adds r3, #1 80043c8: 9309 str r3, [sp, #36] ; 0x24 80043ca: 9b0e ldr r3, [sp, #56] ; 0x38 80043cc: 2b00 cmp r3, #0 80043ce: f47f af6a bne.w 80042a6 <_dtoa_r+0x7e6> 80043d2: 2001 movs r0, #1 80043d4: e76f b.n 80042b6 <_dtoa_r+0x7f6> 80043d6: f04f 0800 mov.w r8, #0 80043da: e7f6 b.n 80043ca <_dtoa_r+0x90a> 80043dc: 4698 mov r8, r3 80043de: e7f4 b.n 80043ca <_dtoa_r+0x90a> 80043e0: f43f af7d beq.w 80042de <_dtoa_r+0x81e> 80043e4: 4618 mov r0, r3 80043e6: 301c adds r0, #28 80043e8: e772 b.n 80042d0 <_dtoa_r+0x810> 80043ea: 9b08 ldr r3, [sp, #32] 80043ec: 2b00 cmp r3, #0 80043ee: dc36 bgt.n 800445e <_dtoa_r+0x99e> 80043f0: 9b22 ldr r3, [sp, #136] ; 0x88 80043f2: 2b02 cmp r3, #2 80043f4: dd33 ble.n 800445e <_dtoa_r+0x99e> 80043f6: f8dd 9020 ldr.w r9, [sp, #32] 80043fa: f1b9 0f00 cmp.w r9, #0 80043fe: d10d bne.n 800441c <_dtoa_r+0x95c> 8004400: 4621 mov r1, r4 8004402: 464b mov r3, r9 8004404: 2205 movs r2, #5 8004406: 4628 mov r0, r5 8004408: f000 f9d2 bl 80047b0 <__multadd> 800440c: 4601 mov r1, r0 800440e: 4604 mov r4, r0 8004410: 4658 mov r0, fp 8004412: f000 fbe9 bl 8004be8 <__mcmp> 8004416: 2800 cmp r0, #0 8004418: f73f adb8 bgt.w 8003f8c <_dtoa_r+0x4cc> 800441c: 9b23 ldr r3, [sp, #140] ; 0x8c 800441e: 9f03 ldr r7, [sp, #12] 8004420: ea6f 0a03 mvn.w sl, r3 8004424: f04f 0800 mov.w r8, #0 8004428: 4621 mov r1, r4 800442a: 4628 mov r0, r5 800442c: f000 f99e bl 800476c <_Bfree> 8004430: 2e00 cmp r6, #0 8004432: f43f aea7 beq.w 8004184 <_dtoa_r+0x6c4> 8004436: f1b8 0f00 cmp.w r8, #0 800443a: d005 beq.n 8004448 <_dtoa_r+0x988> 800443c: 45b0 cmp r8, r6 800443e: d003 beq.n 8004448 <_dtoa_r+0x988> 8004440: 4641 mov r1, r8 8004442: 4628 mov r0, r5 8004444: f000 f992 bl 800476c <_Bfree> 8004448: 4631 mov r1, r6 800444a: 4628 mov r0, r5 800444c: f000 f98e bl 800476c <_Bfree> 8004450: e698 b.n 8004184 <_dtoa_r+0x6c4> 8004452: 2400 movs r4, #0 8004454: 4626 mov r6, r4 8004456: e7e1 b.n 800441c <_dtoa_r+0x95c> 8004458: 46c2 mov sl, r8 800445a: 4626 mov r6, r4 800445c: e596 b.n 8003f8c <_dtoa_r+0x4cc> 800445e: 9b0b ldr r3, [sp, #44] ; 0x2c 8004460: f8dd 9020 ldr.w r9, [sp, #32] 8004464: 2b00 cmp r3, #0 8004466: f000 80fd beq.w 8004664 <_dtoa_r+0xba4> 800446a: 2f00 cmp r7, #0 800446c: dd05 ble.n 800447a <_dtoa_r+0x9ba> 800446e: 4631 mov r1, r6 8004470: 463a mov r2, r7 8004472: 4628 mov r0, r5 8004474: f000 fb48 bl 8004b08 <__lshift> 8004478: 4606 mov r6, r0 800447a: f1b8 0f00 cmp.w r8, #0 800447e: d05c beq.n 800453a <_dtoa_r+0xa7a> 8004480: 4628 mov r0, r5 8004482: 6871 ldr r1, [r6, #4] 8004484: f000 f932 bl 80046ec <_Balloc> 8004488: 4607 mov r7, r0 800448a: b928 cbnz r0, 8004498 <_dtoa_r+0x9d8> 800448c: 4602 mov r2, r0 800448e: f240 21ea movw r1, #746 ; 0x2ea 8004492: 4b7f ldr r3, [pc, #508] ; (8004690 <_dtoa_r+0xbd0>) 8004494: f7ff bb28 b.w 8003ae8 <_dtoa_r+0x28> 8004498: 6932 ldr r2, [r6, #16] 800449a: f106 010c add.w r1, r6, #12 800449e: 3202 adds r2, #2 80044a0: 0092 lsls r2, r2, #2 80044a2: 300c adds r0, #12 80044a4: f000 f914 bl 80046d0 80044a8: 2201 movs r2, #1 80044aa: 4639 mov r1, r7 80044ac: 4628 mov r0, r5 80044ae: f000 fb2b bl 8004b08 <__lshift> 80044b2: 46b0 mov r8, r6 80044b4: 4606 mov r6, r0 80044b6: 9b03 ldr r3, [sp, #12] 80044b8: 3301 adds r3, #1 80044ba: 9308 str r3, [sp, #32] 80044bc: 9b03 ldr r3, [sp, #12] 80044be: 444b add r3, r9 80044c0: 930a str r3, [sp, #40] ; 0x28 80044c2: 9b04 ldr r3, [sp, #16] 80044c4: f003 0301 and.w r3, r3, #1 80044c8: 9309 str r3, [sp, #36] ; 0x24 80044ca: 9b08 ldr r3, [sp, #32] 80044cc: 4621 mov r1, r4 80044ce: 3b01 subs r3, #1 80044d0: 4658 mov r0, fp 80044d2: 9304 str r3, [sp, #16] 80044d4: f7ff fa68 bl 80039a8 80044d8: 4603 mov r3, r0 80044da: 4641 mov r1, r8 80044dc: 3330 adds r3, #48 ; 0x30 80044de: 9006 str r0, [sp, #24] 80044e0: 4658 mov r0, fp 80044e2: 930b str r3, [sp, #44] ; 0x2c 80044e4: f000 fb80 bl 8004be8 <__mcmp> 80044e8: 4632 mov r2, r6 80044ea: 4681 mov r9, r0 80044ec: 4621 mov r1, r4 80044ee: 4628 mov r0, r5 80044f0: f000 fb96 bl 8004c20 <__mdiff> 80044f4: 68c2 ldr r2, [r0, #12] 80044f6: 4607 mov r7, r0 80044f8: 9b0b ldr r3, [sp, #44] ; 0x2c 80044fa: bb02 cbnz r2, 800453e <_dtoa_r+0xa7e> 80044fc: 4601 mov r1, r0 80044fe: 4658 mov r0, fp 8004500: f000 fb72 bl 8004be8 <__mcmp> 8004504: 4602 mov r2, r0 8004506: 9b0b ldr r3, [sp, #44] ; 0x2c 8004508: 4639 mov r1, r7 800450a: 4628 mov r0, r5 800450c: e9cd 320b strd r3, r2, [sp, #44] ; 0x2c 8004510: f000 f92c bl 800476c <_Bfree> 8004514: 9b22 ldr r3, [sp, #136] ; 0x88 8004516: 9a0c ldr r2, [sp, #48] ; 0x30 8004518: 9f08 ldr r7, [sp, #32] 800451a: ea43 0102 orr.w r1, r3, r2 800451e: 9b09 ldr r3, [sp, #36] ; 0x24 8004520: 430b orrs r3, r1 8004522: 9b0b ldr r3, [sp, #44] ; 0x2c 8004524: d10d bne.n 8004542 <_dtoa_r+0xa82> 8004526: 2b39 cmp r3, #57 ; 0x39 8004528: d029 beq.n 800457e <_dtoa_r+0xabe> 800452a: f1b9 0f00 cmp.w r9, #0 800452e: dd01 ble.n 8004534 <_dtoa_r+0xa74> 8004530: 9b06 ldr r3, [sp, #24] 8004532: 3331 adds r3, #49 ; 0x31 8004534: 9a04 ldr r2, [sp, #16] 8004536: 7013 strb r3, [r2, #0] 8004538: e776 b.n 8004428 <_dtoa_r+0x968> 800453a: 4630 mov r0, r6 800453c: e7b9 b.n 80044b2 <_dtoa_r+0x9f2> 800453e: 2201 movs r2, #1 8004540: e7e2 b.n 8004508 <_dtoa_r+0xa48> 8004542: f1b9 0f00 cmp.w r9, #0 8004546: db06 blt.n 8004556 <_dtoa_r+0xa96> 8004548: 9922 ldr r1, [sp, #136] ; 0x88 800454a: ea41 0909 orr.w r9, r1, r9 800454e: 9909 ldr r1, [sp, #36] ; 0x24 8004550: ea59 0101 orrs.w r1, r9, r1 8004554: d120 bne.n 8004598 <_dtoa_r+0xad8> 8004556: 2a00 cmp r2, #0 8004558: ddec ble.n 8004534 <_dtoa_r+0xa74> 800455a: 4659 mov r1, fp 800455c: 2201 movs r2, #1 800455e: 4628 mov r0, r5 8004560: 9308 str r3, [sp, #32] 8004562: f000 fad1 bl 8004b08 <__lshift> 8004566: 4621 mov r1, r4 8004568: 4683 mov fp, r0 800456a: f000 fb3d bl 8004be8 <__mcmp> 800456e: 2800 cmp r0, #0 8004570: 9b08 ldr r3, [sp, #32] 8004572: dc02 bgt.n 800457a <_dtoa_r+0xaba> 8004574: d1de bne.n 8004534 <_dtoa_r+0xa74> 8004576: 07da lsls r2, r3, #31 8004578: d5dc bpl.n 8004534 <_dtoa_r+0xa74> 800457a: 2b39 cmp r3, #57 ; 0x39 800457c: d1d8 bne.n 8004530 <_dtoa_r+0xa70> 800457e: 2339 movs r3, #57 ; 0x39 8004580: 9a04 ldr r2, [sp, #16] 8004582: 7013 strb r3, [r2, #0] 8004584: 463b mov r3, r7 8004586: 461f mov r7, r3 8004588: f817 2c01 ldrb.w r2, [r7, #-1] 800458c: 3b01 subs r3, #1 800458e: 2a39 cmp r2, #57 ; 0x39 8004590: d050 beq.n 8004634 <_dtoa_r+0xb74> 8004592: 3201 adds r2, #1 8004594: 701a strb r2, [r3, #0] 8004596: e747 b.n 8004428 <_dtoa_r+0x968> 8004598: 2a00 cmp r2, #0 800459a: dd03 ble.n 80045a4 <_dtoa_r+0xae4> 800459c: 2b39 cmp r3, #57 ; 0x39 800459e: d0ee beq.n 800457e <_dtoa_r+0xabe> 80045a0: 3301 adds r3, #1 80045a2: e7c7 b.n 8004534 <_dtoa_r+0xa74> 80045a4: 9a08 ldr r2, [sp, #32] 80045a6: 990a ldr r1, [sp, #40] ; 0x28 80045a8: f802 3c01 strb.w r3, [r2, #-1] 80045ac: 428a cmp r2, r1 80045ae: d02a beq.n 8004606 <_dtoa_r+0xb46> 80045b0: 4659 mov r1, fp 80045b2: 2300 movs r3, #0 80045b4: 220a movs r2, #10 80045b6: 4628 mov r0, r5 80045b8: f000 f8fa bl 80047b0 <__multadd> 80045bc: 45b0 cmp r8, r6 80045be: 4683 mov fp, r0 80045c0: f04f 0300 mov.w r3, #0 80045c4: f04f 020a mov.w r2, #10 80045c8: 4641 mov r1, r8 80045ca: 4628 mov r0, r5 80045cc: d107 bne.n 80045de <_dtoa_r+0xb1e> 80045ce: f000 f8ef bl 80047b0 <__multadd> 80045d2: 4680 mov r8, r0 80045d4: 4606 mov r6, r0 80045d6: 9b08 ldr r3, [sp, #32] 80045d8: 3301 adds r3, #1 80045da: 9308 str r3, [sp, #32] 80045dc: e775 b.n 80044ca <_dtoa_r+0xa0a> 80045de: f000 f8e7 bl 80047b0 <__multadd> 80045e2: 4631 mov r1, r6 80045e4: 4680 mov r8, r0 80045e6: 2300 movs r3, #0 80045e8: 220a movs r2, #10 80045ea: 4628 mov r0, r5 80045ec: f000 f8e0 bl 80047b0 <__multadd> 80045f0: 4606 mov r6, r0 80045f2: e7f0 b.n 80045d6 <_dtoa_r+0xb16> 80045f4: f1b9 0f00 cmp.w r9, #0 80045f8: bfcc ite gt 80045fa: 464f movgt r7, r9 80045fc: 2701 movle r7, #1 80045fe: f04f 0800 mov.w r8, #0 8004602: 9a03 ldr r2, [sp, #12] 8004604: 4417 add r7, r2 8004606: 4659 mov r1, fp 8004608: 2201 movs r2, #1 800460a: 4628 mov r0, r5 800460c: 9308 str r3, [sp, #32] 800460e: f000 fa7b bl 8004b08 <__lshift> 8004612: 4621 mov r1, r4 8004614: 4683 mov fp, r0 8004616: f000 fae7 bl 8004be8 <__mcmp> 800461a: 2800 cmp r0, #0 800461c: dcb2 bgt.n 8004584 <_dtoa_r+0xac4> 800461e: d102 bne.n 8004626 <_dtoa_r+0xb66> 8004620: 9b08 ldr r3, [sp, #32] 8004622: 07db lsls r3, r3, #31 8004624: d4ae bmi.n 8004584 <_dtoa_r+0xac4> 8004626: 463b mov r3, r7 8004628: 461f mov r7, r3 800462a: f813 2d01 ldrb.w r2, [r3, #-1]! 800462e: 2a30 cmp r2, #48 ; 0x30 8004630: d0fa beq.n 8004628 <_dtoa_r+0xb68> 8004632: e6f9 b.n 8004428 <_dtoa_r+0x968> 8004634: 9a03 ldr r2, [sp, #12] 8004636: 429a cmp r2, r3 8004638: d1a5 bne.n 8004586 <_dtoa_r+0xac6> 800463a: 2331 movs r3, #49 ; 0x31 800463c: f10a 0a01 add.w sl, sl, #1 8004640: e779 b.n 8004536 <_dtoa_r+0xa76> 8004642: 4b14 ldr r3, [pc, #80] ; (8004694 <_dtoa_r+0xbd4>) 8004644: f7ff baa8 b.w 8003b98 <_dtoa_r+0xd8> 8004648: 9b26 ldr r3, [sp, #152] ; 0x98 800464a: 2b00 cmp r3, #0 800464c: f47f aa81 bne.w 8003b52 <_dtoa_r+0x92> 8004650: 4b11 ldr r3, [pc, #68] ; (8004698 <_dtoa_r+0xbd8>) 8004652: f7ff baa1 b.w 8003b98 <_dtoa_r+0xd8> 8004656: f1b9 0f00 cmp.w r9, #0 800465a: dc03 bgt.n 8004664 <_dtoa_r+0xba4> 800465c: 9b22 ldr r3, [sp, #136] ; 0x88 800465e: 2b02 cmp r3, #2 8004660: f73f aecb bgt.w 80043fa <_dtoa_r+0x93a> 8004664: 9f03 ldr r7, [sp, #12] 8004666: 4621 mov r1, r4 8004668: 4658 mov r0, fp 800466a: f7ff f99d bl 80039a8 800466e: 9a03 ldr r2, [sp, #12] 8004670: f100 0330 add.w r3, r0, #48 ; 0x30 8004674: f807 3b01 strb.w r3, [r7], #1 8004678: 1aba subs r2, r7, r2 800467a: 4591 cmp r9, r2 800467c: ddba ble.n 80045f4 <_dtoa_r+0xb34> 800467e: 4659 mov r1, fp 8004680: 2300 movs r3, #0 8004682: 220a movs r2, #10 8004684: 4628 mov r0, r5 8004686: f000 f893 bl 80047b0 <__multadd> 800468a: 4683 mov fp, r0 800468c: e7eb b.n 8004666 <_dtoa_r+0xba6> 800468e: bf00 nop 8004690: 0800632f .word 0x0800632f 8004694: 0800628c .word 0x0800628c 8004698: 080062b0 .word 0x080062b0 0800469c <_localeconv_r>: 800469c: 4800 ldr r0, [pc, #0] ; (80046a0 <_localeconv_r+0x4>) 800469e: 4770 bx lr 80046a0: 20000160 .word 0x20000160 080046a4 : 80046a4: 4b02 ldr r3, [pc, #8] ; (80046b0 ) 80046a6: 4601 mov r1, r0 80046a8: 6818 ldr r0, [r3, #0] 80046aa: f000 bc1d b.w 8004ee8 <_malloc_r> 80046ae: bf00 nop 80046b0: 2000000c .word 0x2000000c 080046b4 : 80046b4: 4603 mov r3, r0 80046b6: b510 push {r4, lr} 80046b8: b2c9 uxtb r1, r1 80046ba: 4402 add r2, r0 80046bc: 4293 cmp r3, r2 80046be: 4618 mov r0, r3 80046c0: d101 bne.n 80046c6 80046c2: 2000 movs r0, #0 80046c4: e003 b.n 80046ce 80046c6: 7804 ldrb r4, [r0, #0] 80046c8: 3301 adds r3, #1 80046ca: 428c cmp r4, r1 80046cc: d1f6 bne.n 80046bc 80046ce: bd10 pop {r4, pc} 080046d0 : 80046d0: 440a add r2, r1 80046d2: 4291 cmp r1, r2 80046d4: f100 33ff add.w r3, r0, #4294967295 80046d8: d100 bne.n 80046dc 80046da: 4770 bx lr 80046dc: b510 push {r4, lr} 80046de: f811 4b01 ldrb.w r4, [r1], #1 80046e2: 4291 cmp r1, r2 80046e4: f803 4f01 strb.w r4, [r3, #1]! 80046e8: d1f9 bne.n 80046de 80046ea: bd10 pop {r4, pc} 080046ec <_Balloc>: 80046ec: b570 push {r4, r5, r6, lr} 80046ee: 6a46 ldr r6, [r0, #36] ; 0x24 80046f0: 4604 mov r4, r0 80046f2: 460d mov r5, r1 80046f4: b976 cbnz r6, 8004714 <_Balloc+0x28> 80046f6: 2010 movs r0, #16 80046f8: f7ff ffd4 bl 80046a4 80046fc: 4602 mov r2, r0 80046fe: 6260 str r0, [r4, #36] ; 0x24 8004700: b920 cbnz r0, 800470c <_Balloc+0x20> 8004702: 2166 movs r1, #102 ; 0x66 8004704: 4b17 ldr r3, [pc, #92] ; (8004764 <_Balloc+0x78>) 8004706: 4818 ldr r0, [pc, #96] ; (8004768 <_Balloc+0x7c>) 8004708: f000 fdce bl 80052a8 <__assert_func> 800470c: e9c0 6601 strd r6, r6, [r0, #4] 8004710: 6006 str r6, [r0, #0] 8004712: 60c6 str r6, [r0, #12] 8004714: 6a66 ldr r6, [r4, #36] ; 0x24 8004716: 68f3 ldr r3, [r6, #12] 8004718: b183 cbz r3, 800473c <_Balloc+0x50> 800471a: 6a63 ldr r3, [r4, #36] ; 0x24 800471c: 68db ldr r3, [r3, #12] 800471e: f853 0025 ldr.w r0, [r3, r5, lsl #2] 8004722: b9b8 cbnz r0, 8004754 <_Balloc+0x68> 8004724: 2101 movs r1, #1 8004726: fa01 f605 lsl.w r6, r1, r5 800472a: 1d72 adds r2, r6, #5 800472c: 4620 mov r0, r4 800472e: 0092 lsls r2, r2, #2 8004730: f000 fb5e bl 8004df0 <_calloc_r> 8004734: b160 cbz r0, 8004750 <_Balloc+0x64> 8004736: e9c0 5601 strd r5, r6, [r0, #4] 800473a: e00e b.n 800475a <_Balloc+0x6e> 800473c: 2221 movs r2, #33 ; 0x21 800473e: 2104 movs r1, #4 8004740: 4620 mov r0, r4 8004742: f000 fb55 bl 8004df0 <_calloc_r> 8004746: 6a63 ldr r3, [r4, #36] ; 0x24 8004748: 60f0 str r0, [r6, #12] 800474a: 68db ldr r3, [r3, #12] 800474c: 2b00 cmp r3, #0 800474e: d1e4 bne.n 800471a <_Balloc+0x2e> 8004750: 2000 movs r0, #0 8004752: bd70 pop {r4, r5, r6, pc} 8004754: 6802 ldr r2, [r0, #0] 8004756: f843 2025 str.w r2, [r3, r5, lsl #2] 800475a: 2300 movs r3, #0 800475c: e9c0 3303 strd r3, r3, [r0, #12] 8004760: e7f7 b.n 8004752 <_Balloc+0x66> 8004762: bf00 nop 8004764: 080062bd .word 0x080062bd 8004768: 08006340 .word 0x08006340 0800476c <_Bfree>: 800476c: b570 push {r4, r5, r6, lr} 800476e: 6a46 ldr r6, [r0, #36] ; 0x24 8004770: 4605 mov r5, r0 8004772: 460c mov r4, r1 8004774: b976 cbnz r6, 8004794 <_Bfree+0x28> 8004776: 2010 movs r0, #16 8004778: f7ff ff94 bl 80046a4 800477c: 4602 mov r2, r0 800477e: 6268 str r0, [r5, #36] ; 0x24 8004780: b920 cbnz r0, 800478c <_Bfree+0x20> 8004782: 218a movs r1, #138 ; 0x8a 8004784: 4b08 ldr r3, [pc, #32] ; (80047a8 <_Bfree+0x3c>) 8004786: 4809 ldr r0, [pc, #36] ; (80047ac <_Bfree+0x40>) 8004788: f000 fd8e bl 80052a8 <__assert_func> 800478c: e9c0 6601 strd r6, r6, [r0, #4] 8004790: 6006 str r6, [r0, #0] 8004792: 60c6 str r6, [r0, #12] 8004794: b13c cbz r4, 80047a6 <_Bfree+0x3a> 8004796: 6a6b ldr r3, [r5, #36] ; 0x24 8004798: 6862 ldr r2, [r4, #4] 800479a: 68db ldr r3, [r3, #12] 800479c: f853 1022 ldr.w r1, [r3, r2, lsl #2] 80047a0: 6021 str r1, [r4, #0] 80047a2: f843 4022 str.w r4, [r3, r2, lsl #2] 80047a6: bd70 pop {r4, r5, r6, pc} 80047a8: 080062bd .word 0x080062bd 80047ac: 08006340 .word 0x08006340 080047b0 <__multadd>: 80047b0: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} 80047b4: 4607 mov r7, r0 80047b6: 460c mov r4, r1 80047b8: 461e mov r6, r3 80047ba: 2000 movs r0, #0 80047bc: 690d ldr r5, [r1, #16] 80047be: f101 0c14 add.w ip, r1, #20 80047c2: f8dc 3000 ldr.w r3, [ip] 80047c6: 3001 adds r0, #1 80047c8: b299 uxth r1, r3 80047ca: fb02 6101 mla r1, r2, r1, r6 80047ce: 0c1e lsrs r6, r3, #16 80047d0: 0c0b lsrs r3, r1, #16 80047d2: fb02 3306 mla r3, r2, r6, r3 80047d6: b289 uxth r1, r1 80047d8: eb01 4103 add.w r1, r1, r3, lsl #16 80047dc: 4285 cmp r5, r0 80047de: ea4f 4613 mov.w r6, r3, lsr #16 80047e2: f84c 1b04 str.w r1, [ip], #4 80047e6: dcec bgt.n 80047c2 <__multadd+0x12> 80047e8: b30e cbz r6, 800482e <__multadd+0x7e> 80047ea: 68a3 ldr r3, [r4, #8] 80047ec: 42ab cmp r3, r5 80047ee: dc19 bgt.n 8004824 <__multadd+0x74> 80047f0: 6861 ldr r1, [r4, #4] 80047f2: 4638 mov r0, r7 80047f4: 3101 adds r1, #1 80047f6: f7ff ff79 bl 80046ec <_Balloc> 80047fa: 4680 mov r8, r0 80047fc: b928 cbnz r0, 800480a <__multadd+0x5a> 80047fe: 4602 mov r2, r0 8004800: 21b5 movs r1, #181 ; 0xb5 8004802: 4b0c ldr r3, [pc, #48] ; (8004834 <__multadd+0x84>) 8004804: 480c ldr r0, [pc, #48] ; (8004838 <__multadd+0x88>) 8004806: f000 fd4f bl 80052a8 <__assert_func> 800480a: 6922 ldr r2, [r4, #16] 800480c: f104 010c add.w r1, r4, #12 8004810: 3202 adds r2, #2 8004812: 0092 lsls r2, r2, #2 8004814: 300c adds r0, #12 8004816: f7ff ff5b bl 80046d0 800481a: 4621 mov r1, r4 800481c: 4638 mov r0, r7 800481e: f7ff ffa5 bl 800476c <_Bfree> 8004822: 4644 mov r4, r8 8004824: eb04 0385 add.w r3, r4, r5, lsl #2 8004828: 3501 adds r5, #1 800482a: 615e str r6, [r3, #20] 800482c: 6125 str r5, [r4, #16] 800482e: 4620 mov r0, r4 8004830: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} 8004834: 0800632f .word 0x0800632f 8004838: 08006340 .word 0x08006340 0800483c <__hi0bits>: 800483c: 0c02 lsrs r2, r0, #16 800483e: 0412 lsls r2, r2, #16 8004840: 4603 mov r3, r0 8004842: b9ca cbnz r2, 8004878 <__hi0bits+0x3c> 8004844: 0403 lsls r3, r0, #16 8004846: 2010 movs r0, #16 8004848: f013 4f7f tst.w r3, #4278190080 ; 0xff000000 800484c: bf04 itt eq 800484e: 021b lsleq r3, r3, #8 8004850: 3008 addeq r0, #8 8004852: f013 4f70 tst.w r3, #4026531840 ; 0xf0000000 8004856: bf04 itt eq 8004858: 011b lsleq r3, r3, #4 800485a: 3004 addeq r0, #4 800485c: f013 4f40 tst.w r3, #3221225472 ; 0xc0000000 8004860: bf04 itt eq 8004862: 009b lsleq r3, r3, #2 8004864: 3002 addeq r0, #2 8004866: 2b00 cmp r3, #0 8004868: db05 blt.n 8004876 <__hi0bits+0x3a> 800486a: f013 4f80 tst.w r3, #1073741824 ; 0x40000000 800486e: f100 0001 add.w r0, r0, #1 8004872: bf08 it eq 8004874: 2020 moveq r0, #32 8004876: 4770 bx lr 8004878: 2000 movs r0, #0 800487a: e7e5 b.n 8004848 <__hi0bits+0xc> 0800487c <__lo0bits>: 800487c: 6803 ldr r3, [r0, #0] 800487e: 4602 mov r2, r0 8004880: f013 0007 ands.w r0, r3, #7 8004884: d00b beq.n 800489e <__lo0bits+0x22> 8004886: 07d9 lsls r1, r3, #31 8004888: d421 bmi.n 80048ce <__lo0bits+0x52> 800488a: 0798 lsls r0, r3, #30 800488c: bf49 itett mi 800488e: 085b lsrmi r3, r3, #1 8004890: 089b lsrpl r3, r3, #2 8004892: 2001 movmi r0, #1 8004894: 6013 strmi r3, [r2, #0] 8004896: bf5c itt pl 8004898: 2002 movpl r0, #2 800489a: 6013 strpl r3, [r2, #0] 800489c: 4770 bx lr 800489e: b299 uxth r1, r3 80048a0: b909 cbnz r1, 80048a6 <__lo0bits+0x2a> 80048a2: 2010 movs r0, #16 80048a4: 0c1b lsrs r3, r3, #16 80048a6: b2d9 uxtb r1, r3 80048a8: b909 cbnz r1, 80048ae <__lo0bits+0x32> 80048aa: 3008 adds r0, #8 80048ac: 0a1b lsrs r3, r3, #8 80048ae: 0719 lsls r1, r3, #28 80048b0: bf04 itt eq 80048b2: 091b lsreq r3, r3, #4 80048b4: 3004 addeq r0, #4 80048b6: 0799 lsls r1, r3, #30 80048b8: bf04 itt eq 80048ba: 089b lsreq r3, r3, #2 80048bc: 3002 addeq r0, #2 80048be: 07d9 lsls r1, r3, #31 80048c0: d403 bmi.n 80048ca <__lo0bits+0x4e> 80048c2: 085b lsrs r3, r3, #1 80048c4: f100 0001 add.w r0, r0, #1 80048c8: d003 beq.n 80048d2 <__lo0bits+0x56> 80048ca: 6013 str r3, [r2, #0] 80048cc: 4770 bx lr 80048ce: 2000 movs r0, #0 80048d0: 4770 bx lr 80048d2: 2020 movs r0, #32 80048d4: 4770 bx lr ... 080048d8 <__i2b>: 80048d8: b510 push {r4, lr} 80048da: 460c mov r4, r1 80048dc: 2101 movs r1, #1 80048de: f7ff ff05 bl 80046ec <_Balloc> 80048e2: 4602 mov r2, r0 80048e4: b928 cbnz r0, 80048f2 <__i2b+0x1a> 80048e6: f44f 71a0 mov.w r1, #320 ; 0x140 80048ea: 4b04 ldr r3, [pc, #16] ; (80048fc <__i2b+0x24>) 80048ec: 4804 ldr r0, [pc, #16] ; (8004900 <__i2b+0x28>) 80048ee: f000 fcdb bl 80052a8 <__assert_func> 80048f2: 2301 movs r3, #1 80048f4: 6144 str r4, [r0, #20] 80048f6: 6103 str r3, [r0, #16] 80048f8: bd10 pop {r4, pc} 80048fa: bf00 nop 80048fc: 0800632f .word 0x0800632f 8004900: 08006340 .word 0x08006340 08004904 <__multiply>: 8004904: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 8004908: 4691 mov r9, r2 800490a: 690a ldr r2, [r1, #16] 800490c: f8d9 3010 ldr.w r3, [r9, #16] 8004910: 460c mov r4, r1 8004912: 429a cmp r2, r3 8004914: bfbe ittt lt 8004916: 460b movlt r3, r1 8004918: 464c movlt r4, r9 800491a: 4699 movlt r9, r3 800491c: 6927 ldr r7, [r4, #16] 800491e: f8d9 a010 ldr.w sl, [r9, #16] 8004922: 68a3 ldr r3, [r4, #8] 8004924: 6861 ldr r1, [r4, #4] 8004926: eb07 060a add.w r6, r7, sl 800492a: 42b3 cmp r3, r6 800492c: b085 sub sp, #20 800492e: bfb8 it lt 8004930: 3101 addlt r1, #1 8004932: f7ff fedb bl 80046ec <_Balloc> 8004936: b930 cbnz r0, 8004946 <__multiply+0x42> 8004938: 4602 mov r2, r0 800493a: f240 115d movw r1, #349 ; 0x15d 800493e: 4b43 ldr r3, [pc, #268] ; (8004a4c <__multiply+0x148>) 8004940: 4843 ldr r0, [pc, #268] ; (8004a50 <__multiply+0x14c>) 8004942: f000 fcb1 bl 80052a8 <__assert_func> 8004946: f100 0514 add.w r5, r0, #20 800494a: 462b mov r3, r5 800494c: 2200 movs r2, #0 800494e: eb05 0886 add.w r8, r5, r6, lsl #2 8004952: 4543 cmp r3, r8 8004954: d321 bcc.n 800499a <__multiply+0x96> 8004956: f104 0314 add.w r3, r4, #20 800495a: eb03 0787 add.w r7, r3, r7, lsl #2 800495e: f109 0314 add.w r3, r9, #20 8004962: eb03 028a add.w r2, r3, sl, lsl #2 8004966: 9202 str r2, [sp, #8] 8004968: 1b3a subs r2, r7, r4 800496a: 3a15 subs r2, #21 800496c: f022 0203 bic.w r2, r2, #3 8004970: 3204 adds r2, #4 8004972: f104 0115 add.w r1, r4, #21 8004976: 428f cmp r7, r1 8004978: bf38 it cc 800497a: 2204 movcc r2, #4 800497c: 9201 str r2, [sp, #4] 800497e: 9a02 ldr r2, [sp, #8] 8004980: 9303 str r3, [sp, #12] 8004982: 429a cmp r2, r3 8004984: d80c bhi.n 80049a0 <__multiply+0x9c> 8004986: 2e00 cmp r6, #0 8004988: dd03 ble.n 8004992 <__multiply+0x8e> 800498a: f858 3d04 ldr.w r3, [r8, #-4]! 800498e: 2b00 cmp r3, #0 8004990: d059 beq.n 8004a46 <__multiply+0x142> 8004992: 6106 str r6, [r0, #16] 8004994: b005 add sp, #20 8004996: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 800499a: f843 2b04 str.w r2, [r3], #4 800499e: e7d8 b.n 8004952 <__multiply+0x4e> 80049a0: f8b3 a000 ldrh.w sl, [r3] 80049a4: f1ba 0f00 cmp.w sl, #0 80049a8: d023 beq.n 80049f2 <__multiply+0xee> 80049aa: 46a9 mov r9, r5 80049ac: f04f 0c00 mov.w ip, #0 80049b0: f104 0e14 add.w lr, r4, #20 80049b4: f85e 2b04 ldr.w r2, [lr], #4 80049b8: f8d9 1000 ldr.w r1, [r9] 80049bc: fa1f fb82 uxth.w fp, r2 80049c0: b289 uxth r1, r1 80049c2: fb0a 110b mla r1, sl, fp, r1 80049c6: 4461 add r1, ip 80049c8: f8d9 c000 ldr.w ip, [r9] 80049cc: 0c12 lsrs r2, r2, #16 80049ce: ea4f 4c1c mov.w ip, ip, lsr #16 80049d2: fb0a c202 mla r2, sl, r2, ip 80049d6: eb02 4211 add.w r2, r2, r1, lsr #16 80049da: b289 uxth r1, r1 80049dc: ea41 4102 orr.w r1, r1, r2, lsl #16 80049e0: 4577 cmp r7, lr 80049e2: ea4f 4c12 mov.w ip, r2, lsr #16 80049e6: f849 1b04 str.w r1, [r9], #4 80049ea: d8e3 bhi.n 80049b4 <__multiply+0xb0> 80049ec: 9a01 ldr r2, [sp, #4] 80049ee: f845 c002 str.w ip, [r5, r2] 80049f2: 9a03 ldr r2, [sp, #12] 80049f4: 3304 adds r3, #4 80049f6: f8b2 9002 ldrh.w r9, [r2, #2] 80049fa: f1b9 0f00 cmp.w r9, #0 80049fe: d020 beq.n 8004a42 <__multiply+0x13e> 8004a00: 46ae mov lr, r5 8004a02: f04f 0a00 mov.w sl, #0 8004a06: 6829 ldr r1, [r5, #0] 8004a08: f104 0c14 add.w ip, r4, #20 8004a0c: f8bc b000 ldrh.w fp, [ip] 8004a10: f8be 2002 ldrh.w r2, [lr, #2] 8004a14: b289 uxth r1, r1 8004a16: fb09 220b mla r2, r9, fp, r2 8004a1a: 4492 add sl, r2 8004a1c: ea41 410a orr.w r1, r1, sl, lsl #16 8004a20: f84e 1b04 str.w r1, [lr], #4 8004a24: f85c 2b04 ldr.w r2, [ip], #4 8004a28: f8be 1000 ldrh.w r1, [lr] 8004a2c: 0c12 lsrs r2, r2, #16 8004a2e: fb09 1102 mla r1, r9, r2, r1 8004a32: 4567 cmp r7, ip 8004a34: eb01 411a add.w r1, r1, sl, lsr #16 8004a38: ea4f 4a11 mov.w sl, r1, lsr #16 8004a3c: d8e6 bhi.n 8004a0c <__multiply+0x108> 8004a3e: 9a01 ldr r2, [sp, #4] 8004a40: 50a9 str r1, [r5, r2] 8004a42: 3504 adds r5, #4 8004a44: e79b b.n 800497e <__multiply+0x7a> 8004a46: 3e01 subs r6, #1 8004a48: e79d b.n 8004986 <__multiply+0x82> 8004a4a: bf00 nop 8004a4c: 0800632f .word 0x0800632f 8004a50: 08006340 .word 0x08006340 08004a54 <__pow5mult>: 8004a54: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} 8004a58: 4615 mov r5, r2 8004a5a: f012 0203 ands.w r2, r2, #3 8004a5e: 4606 mov r6, r0 8004a60: 460f mov r7, r1 8004a62: d007 beq.n 8004a74 <__pow5mult+0x20> 8004a64: 4c25 ldr r4, [pc, #148] ; (8004afc <__pow5mult+0xa8>) 8004a66: 3a01 subs r2, #1 8004a68: 2300 movs r3, #0 8004a6a: f854 2022 ldr.w r2, [r4, r2, lsl #2] 8004a6e: f7ff fe9f bl 80047b0 <__multadd> 8004a72: 4607 mov r7, r0 8004a74: 10ad asrs r5, r5, #2 8004a76: d03d beq.n 8004af4 <__pow5mult+0xa0> 8004a78: 6a74 ldr r4, [r6, #36] ; 0x24 8004a7a: b97c cbnz r4, 8004a9c <__pow5mult+0x48> 8004a7c: 2010 movs r0, #16 8004a7e: f7ff fe11 bl 80046a4 8004a82: 4602 mov r2, r0 8004a84: 6270 str r0, [r6, #36] ; 0x24 8004a86: b928 cbnz r0, 8004a94 <__pow5mult+0x40> 8004a88: f44f 71d7 mov.w r1, #430 ; 0x1ae 8004a8c: 4b1c ldr r3, [pc, #112] ; (8004b00 <__pow5mult+0xac>) 8004a8e: 481d ldr r0, [pc, #116] ; (8004b04 <__pow5mult+0xb0>) 8004a90: f000 fc0a bl 80052a8 <__assert_func> 8004a94: e9c0 4401 strd r4, r4, [r0, #4] 8004a98: 6004 str r4, [r0, #0] 8004a9a: 60c4 str r4, [r0, #12] 8004a9c: f8d6 8024 ldr.w r8, [r6, #36] ; 0x24 8004aa0: f8d8 4008 ldr.w r4, [r8, #8] 8004aa4: b94c cbnz r4, 8004aba <__pow5mult+0x66> 8004aa6: f240 2171 movw r1, #625 ; 0x271 8004aaa: 4630 mov r0, r6 8004aac: f7ff ff14 bl 80048d8 <__i2b> 8004ab0: 2300 movs r3, #0 8004ab2: 4604 mov r4, r0 8004ab4: f8c8 0008 str.w r0, [r8, #8] 8004ab8: 6003 str r3, [r0, #0] 8004aba: f04f 0900 mov.w r9, #0 8004abe: 07eb lsls r3, r5, #31 8004ac0: d50a bpl.n 8004ad8 <__pow5mult+0x84> 8004ac2: 4639 mov r1, r7 8004ac4: 4622 mov r2, r4 8004ac6: 4630 mov r0, r6 8004ac8: f7ff ff1c bl 8004904 <__multiply> 8004acc: 4680 mov r8, r0 8004ace: 4639 mov r1, r7 8004ad0: 4630 mov r0, r6 8004ad2: f7ff fe4b bl 800476c <_Bfree> 8004ad6: 4647 mov r7, r8 8004ad8: 106d asrs r5, r5, #1 8004ada: d00b beq.n 8004af4 <__pow5mult+0xa0> 8004adc: 6820 ldr r0, [r4, #0] 8004ade: b938 cbnz r0, 8004af0 <__pow5mult+0x9c> 8004ae0: 4622 mov r2, r4 8004ae2: 4621 mov r1, r4 8004ae4: 4630 mov r0, r6 8004ae6: f7ff ff0d bl 8004904 <__multiply> 8004aea: 6020 str r0, [r4, #0] 8004aec: f8c0 9000 str.w r9, [r0] 8004af0: 4604 mov r4, r0 8004af2: e7e4 b.n 8004abe <__pow5mult+0x6a> 8004af4: 4638 mov r0, r7 8004af6: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} 8004afa: bf00 nop 8004afc: 08006490 .word 0x08006490 8004b00: 080062bd .word 0x080062bd 8004b04: 08006340 .word 0x08006340 08004b08 <__lshift>: 8004b08: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 8004b0c: 460c mov r4, r1 8004b0e: 4607 mov r7, r0 8004b10: 4691 mov r9, r2 8004b12: 6923 ldr r3, [r4, #16] 8004b14: 6849 ldr r1, [r1, #4] 8004b16: eb03 1862 add.w r8, r3, r2, asr #5 8004b1a: 68a3 ldr r3, [r4, #8] 8004b1c: ea4f 1a62 mov.w sl, r2, asr #5 8004b20: f108 0601 add.w r6, r8, #1 8004b24: 42b3 cmp r3, r6 8004b26: db0b blt.n 8004b40 <__lshift+0x38> 8004b28: 4638 mov r0, r7 8004b2a: f7ff fddf bl 80046ec <_Balloc> 8004b2e: 4605 mov r5, r0 8004b30: b948 cbnz r0, 8004b46 <__lshift+0x3e> 8004b32: 4602 mov r2, r0 8004b34: f240 11d9 movw r1, #473 ; 0x1d9 8004b38: 4b29 ldr r3, [pc, #164] ; (8004be0 <__lshift+0xd8>) 8004b3a: 482a ldr r0, [pc, #168] ; (8004be4 <__lshift+0xdc>) 8004b3c: f000 fbb4 bl 80052a8 <__assert_func> 8004b40: 3101 adds r1, #1 8004b42: 005b lsls r3, r3, #1 8004b44: e7ee b.n 8004b24 <__lshift+0x1c> 8004b46: 2300 movs r3, #0 8004b48: f100 0114 add.w r1, r0, #20 8004b4c: f100 0210 add.w r2, r0, #16 8004b50: 4618 mov r0, r3 8004b52: 4553 cmp r3, sl 8004b54: db37 blt.n 8004bc6 <__lshift+0xbe> 8004b56: 6920 ldr r0, [r4, #16] 8004b58: ea2a 7aea bic.w sl, sl, sl, asr #31 8004b5c: f104 0314 add.w r3, r4, #20 8004b60: f019 091f ands.w r9, r9, #31 8004b64: eb01 018a add.w r1, r1, sl, lsl #2 8004b68: eb03 0080 add.w r0, r3, r0, lsl #2 8004b6c: d02f beq.n 8004bce <__lshift+0xc6> 8004b6e: 468a mov sl, r1 8004b70: f04f 0c00 mov.w ip, #0 8004b74: f1c9 0e20 rsb lr, r9, #32 8004b78: 681a ldr r2, [r3, #0] 8004b7a: fa02 f209 lsl.w r2, r2, r9 8004b7e: ea42 020c orr.w r2, r2, ip 8004b82: f84a 2b04 str.w r2, [sl], #4 8004b86: f853 2b04 ldr.w r2, [r3], #4 8004b8a: 4298 cmp r0, r3 8004b8c: fa22 fc0e lsr.w ip, r2, lr 8004b90: d8f2 bhi.n 8004b78 <__lshift+0x70> 8004b92: 1b03 subs r3, r0, r4 8004b94: 3b15 subs r3, #21 8004b96: f023 0303 bic.w r3, r3, #3 8004b9a: 3304 adds r3, #4 8004b9c: f104 0215 add.w r2, r4, #21 8004ba0: 4290 cmp r0, r2 8004ba2: bf38 it cc 8004ba4: 2304 movcc r3, #4 8004ba6: f841 c003 str.w ip, [r1, r3] 8004baa: f1bc 0f00 cmp.w ip, #0 8004bae: d001 beq.n 8004bb4 <__lshift+0xac> 8004bb0: f108 0602 add.w r6, r8, #2 8004bb4: 3e01 subs r6, #1 8004bb6: 4638 mov r0, r7 8004bb8: 4621 mov r1, r4 8004bba: 612e str r6, [r5, #16] 8004bbc: f7ff fdd6 bl 800476c <_Bfree> 8004bc0: 4628 mov r0, r5 8004bc2: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 8004bc6: f842 0f04 str.w r0, [r2, #4]! 8004bca: 3301 adds r3, #1 8004bcc: e7c1 b.n 8004b52 <__lshift+0x4a> 8004bce: 3904 subs r1, #4 8004bd0: f853 2b04 ldr.w r2, [r3], #4 8004bd4: 4298 cmp r0, r3 8004bd6: f841 2f04 str.w r2, [r1, #4]! 8004bda: d8f9 bhi.n 8004bd0 <__lshift+0xc8> 8004bdc: e7ea b.n 8004bb4 <__lshift+0xac> 8004bde: bf00 nop 8004be0: 0800632f .word 0x0800632f 8004be4: 08006340 .word 0x08006340 08004be8 <__mcmp>: 8004be8: 4603 mov r3, r0 8004bea: 690a ldr r2, [r1, #16] 8004bec: 6900 ldr r0, [r0, #16] 8004bee: b530 push {r4, r5, lr} 8004bf0: 1a80 subs r0, r0, r2 8004bf2: d10d bne.n 8004c10 <__mcmp+0x28> 8004bf4: 3314 adds r3, #20 8004bf6: 3114 adds r1, #20 8004bf8: eb03 0482 add.w r4, r3, r2, lsl #2 8004bfc: eb01 0182 add.w r1, r1, r2, lsl #2 8004c00: f854 5d04 ldr.w r5, [r4, #-4]! 8004c04: f851 2d04 ldr.w r2, [r1, #-4]! 8004c08: 4295 cmp r5, r2 8004c0a: d002 beq.n 8004c12 <__mcmp+0x2a> 8004c0c: d304 bcc.n 8004c18 <__mcmp+0x30> 8004c0e: 2001 movs r0, #1 8004c10: bd30 pop {r4, r5, pc} 8004c12: 42a3 cmp r3, r4 8004c14: d3f4 bcc.n 8004c00 <__mcmp+0x18> 8004c16: e7fb b.n 8004c10 <__mcmp+0x28> 8004c18: f04f 30ff mov.w r0, #4294967295 8004c1c: e7f8 b.n 8004c10 <__mcmp+0x28> ... 08004c20 <__mdiff>: 8004c20: e92d 4ff8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr} 8004c24: 460d mov r5, r1 8004c26: 4607 mov r7, r0 8004c28: 4611 mov r1, r2 8004c2a: 4628 mov r0, r5 8004c2c: 4614 mov r4, r2 8004c2e: f7ff ffdb bl 8004be8 <__mcmp> 8004c32: 1e06 subs r6, r0, #0 8004c34: d111 bne.n 8004c5a <__mdiff+0x3a> 8004c36: 4631 mov r1, r6 8004c38: 4638 mov r0, r7 8004c3a: f7ff fd57 bl 80046ec <_Balloc> 8004c3e: 4602 mov r2, r0 8004c40: b928 cbnz r0, 8004c4e <__mdiff+0x2e> 8004c42: f240 2132 movw r1, #562 ; 0x232 8004c46: 4b3a ldr r3, [pc, #232] ; (8004d30 <__mdiff+0x110>) 8004c48: 483a ldr r0, [pc, #232] ; (8004d34 <__mdiff+0x114>) 8004c4a: f000 fb2d bl 80052a8 <__assert_func> 8004c4e: 2301 movs r3, #1 8004c50: e9c0 3604 strd r3, r6, [r0, #16] 8004c54: 4610 mov r0, r2 8004c56: e8bd 8ff8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, pc} 8004c5a: bfa4 itt ge 8004c5c: 4623 movge r3, r4 8004c5e: 462c movge r4, r5 8004c60: 4638 mov r0, r7 8004c62: 6861 ldr r1, [r4, #4] 8004c64: bfa6 itte ge 8004c66: 461d movge r5, r3 8004c68: 2600 movge r6, #0 8004c6a: 2601 movlt r6, #1 8004c6c: f7ff fd3e bl 80046ec <_Balloc> 8004c70: 4602 mov r2, r0 8004c72: b918 cbnz r0, 8004c7c <__mdiff+0x5c> 8004c74: f44f 7110 mov.w r1, #576 ; 0x240 8004c78: 4b2d ldr r3, [pc, #180] ; (8004d30 <__mdiff+0x110>) 8004c7a: e7e5 b.n 8004c48 <__mdiff+0x28> 8004c7c: f102 0814 add.w r8, r2, #20 8004c80: 46c2 mov sl, r8 8004c82: f04f 0c00 mov.w ip, #0 8004c86: 6927 ldr r7, [r4, #16] 8004c88: 60c6 str r6, [r0, #12] 8004c8a: 692e ldr r6, [r5, #16] 8004c8c: f104 0014 add.w r0, r4, #20 8004c90: f105 0914 add.w r9, r5, #20 8004c94: eb00 0e87 add.w lr, r0, r7, lsl #2 8004c98: eb09 0686 add.w r6, r9, r6, lsl #2 8004c9c: 3410 adds r4, #16 8004c9e: f854 bf04 ldr.w fp, [r4, #4]! 8004ca2: f859 3b04 ldr.w r3, [r9], #4 8004ca6: fa1f f18b uxth.w r1, fp 8004caa: 448c add ip, r1 8004cac: b299 uxth r1, r3 8004cae: 0c1b lsrs r3, r3, #16 8004cb0: ebac 0101 sub.w r1, ip, r1 8004cb4: ebc3 431b rsb r3, r3, fp, lsr #16 8004cb8: eb03 4321 add.w r3, r3, r1, asr #16 8004cbc: b289 uxth r1, r1 8004cbe: ea4f 4c23 mov.w ip, r3, asr #16 8004cc2: 454e cmp r6, r9 8004cc4: ea41 4303 orr.w r3, r1, r3, lsl #16 8004cc8: f84a 3b04 str.w r3, [sl], #4 8004ccc: d8e7 bhi.n 8004c9e <__mdiff+0x7e> 8004cce: 1b73 subs r3, r6, r5 8004cd0: 3b15 subs r3, #21 8004cd2: f023 0303 bic.w r3, r3, #3 8004cd6: 3515 adds r5, #21 8004cd8: 3304 adds r3, #4 8004cda: 42ae cmp r6, r5 8004cdc: bf38 it cc 8004cde: 2304 movcc r3, #4 8004ce0: 4418 add r0, r3 8004ce2: 4443 add r3, r8 8004ce4: 461e mov r6, r3 8004ce6: 4605 mov r5, r0 8004ce8: 4575 cmp r5, lr 8004cea: d30e bcc.n 8004d0a <__mdiff+0xea> 8004cec: f10e 0103 add.w r1, lr, #3 8004cf0: 1a09 subs r1, r1, r0 8004cf2: f021 0103 bic.w r1, r1, #3 8004cf6: 3803 subs r0, #3 8004cf8: 4586 cmp lr, r0 8004cfa: bf38 it cc 8004cfc: 2100 movcc r1, #0 8004cfe: 4419 add r1, r3 8004d00: f851 3d04 ldr.w r3, [r1, #-4]! 8004d04: b18b cbz r3, 8004d2a <__mdiff+0x10a> 8004d06: 6117 str r7, [r2, #16] 8004d08: e7a4 b.n 8004c54 <__mdiff+0x34> 8004d0a: f855 8b04 ldr.w r8, [r5], #4 8004d0e: fa1f f188 uxth.w r1, r8 8004d12: 4461 add r1, ip 8004d14: 140c asrs r4, r1, #16 8004d16: eb04 4418 add.w r4, r4, r8, lsr #16 8004d1a: b289 uxth r1, r1 8004d1c: ea41 4104 orr.w r1, r1, r4, lsl #16 8004d20: ea4f 4c24 mov.w ip, r4, asr #16 8004d24: f846 1b04 str.w r1, [r6], #4 8004d28: e7de b.n 8004ce8 <__mdiff+0xc8> 8004d2a: 3f01 subs r7, #1 8004d2c: e7e8 b.n 8004d00 <__mdiff+0xe0> 8004d2e: bf00 nop 8004d30: 0800632f .word 0x0800632f 8004d34: 08006340 .word 0x08006340 08004d38 <__d2b>: 8004d38: e92d 41f3 stmdb sp!, {r0, r1, r4, r5, r6, r7, r8, lr} 8004d3c: 2101 movs r1, #1 8004d3e: e9dd 7608 ldrd r7, r6, [sp, #32] 8004d42: 4690 mov r8, r2 8004d44: 461d mov r5, r3 8004d46: f7ff fcd1 bl 80046ec <_Balloc> 8004d4a: 4604 mov r4, r0 8004d4c: b930 cbnz r0, 8004d5c <__d2b+0x24> 8004d4e: 4602 mov r2, r0 8004d50: f240 310a movw r1, #778 ; 0x30a 8004d54: 4b24 ldr r3, [pc, #144] ; (8004de8 <__d2b+0xb0>) 8004d56: 4825 ldr r0, [pc, #148] ; (8004dec <__d2b+0xb4>) 8004d58: f000 faa6 bl 80052a8 <__assert_func> 8004d5c: f3c5 0313 ubfx r3, r5, #0, #20 8004d60: f3c5 550a ubfx r5, r5, #20, #11 8004d64: bb2d cbnz r5, 8004db2 <__d2b+0x7a> 8004d66: 9301 str r3, [sp, #4] 8004d68: f1b8 0300 subs.w r3, r8, #0 8004d6c: d026 beq.n 8004dbc <__d2b+0x84> 8004d6e: 4668 mov r0, sp 8004d70: 9300 str r3, [sp, #0] 8004d72: f7ff fd83 bl 800487c <__lo0bits> 8004d76: 9900 ldr r1, [sp, #0] 8004d78: b1f0 cbz r0, 8004db8 <__d2b+0x80> 8004d7a: 9a01 ldr r2, [sp, #4] 8004d7c: f1c0 0320 rsb r3, r0, #32 8004d80: fa02 f303 lsl.w r3, r2, r3 8004d84: 430b orrs r3, r1 8004d86: 40c2 lsrs r2, r0 8004d88: 6163 str r3, [r4, #20] 8004d8a: 9201 str r2, [sp, #4] 8004d8c: 9b01 ldr r3, [sp, #4] 8004d8e: 2b00 cmp r3, #0 8004d90: bf14 ite ne 8004d92: 2102 movne r1, #2 8004d94: 2101 moveq r1, #1 8004d96: 61a3 str r3, [r4, #24] 8004d98: 6121 str r1, [r4, #16] 8004d9a: b1c5 cbz r5, 8004dce <__d2b+0x96> 8004d9c: f2a5 4533 subw r5, r5, #1075 ; 0x433 8004da0: 4405 add r5, r0 8004da2: f1c0 0035 rsb r0, r0, #53 ; 0x35 8004da6: 603d str r5, [r7, #0] 8004da8: 6030 str r0, [r6, #0] 8004daa: 4620 mov r0, r4 8004dac: b002 add sp, #8 8004dae: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} 8004db2: f443 1380 orr.w r3, r3, #1048576 ; 0x100000 8004db6: e7d6 b.n 8004d66 <__d2b+0x2e> 8004db8: 6161 str r1, [r4, #20] 8004dba: e7e7 b.n 8004d8c <__d2b+0x54> 8004dbc: a801 add r0, sp, #4 8004dbe: f7ff fd5d bl 800487c <__lo0bits> 8004dc2: 2101 movs r1, #1 8004dc4: 9b01 ldr r3, [sp, #4] 8004dc6: 6121 str r1, [r4, #16] 8004dc8: 6163 str r3, [r4, #20] 8004dca: 3020 adds r0, #32 8004dcc: e7e5 b.n 8004d9a <__d2b+0x62> 8004dce: eb04 0381 add.w r3, r4, r1, lsl #2 8004dd2: f2a0 4032 subw r0, r0, #1074 ; 0x432 8004dd6: 6038 str r0, [r7, #0] 8004dd8: 6918 ldr r0, [r3, #16] 8004dda: f7ff fd2f bl 800483c <__hi0bits> 8004dde: ebc0 1141 rsb r1, r0, r1, lsl #5 8004de2: 6031 str r1, [r6, #0] 8004de4: e7e1 b.n 8004daa <__d2b+0x72> 8004de6: bf00 nop 8004de8: 0800632f .word 0x0800632f 8004dec: 08006340 .word 0x08006340 08004df0 <_calloc_r>: 8004df0: b570 push {r4, r5, r6, lr} 8004df2: fba1 5402 umull r5, r4, r1, r2 8004df6: b934 cbnz r4, 8004e06 <_calloc_r+0x16> 8004df8: 4629 mov r1, r5 8004dfa: f000 f875 bl 8004ee8 <_malloc_r> 8004dfe: 4606 mov r6, r0 8004e00: b928 cbnz r0, 8004e0e <_calloc_r+0x1e> 8004e02: 4630 mov r0, r6 8004e04: bd70 pop {r4, r5, r6, pc} 8004e06: 220c movs r2, #12 8004e08: 2600 movs r6, #0 8004e0a: 6002 str r2, [r0, #0] 8004e0c: e7f9 b.n 8004e02 <_calloc_r+0x12> 8004e0e: 462a mov r2, r5 8004e10: 4621 mov r1, r4 8004e12: f7fe f941 bl 8003098 8004e16: e7f4 b.n 8004e02 <_calloc_r+0x12> 08004e18 <_free_r>: 8004e18: b538 push {r3, r4, r5, lr} 8004e1a: 4605 mov r5, r0 8004e1c: 2900 cmp r1, #0 8004e1e: d040 beq.n 8004ea2 <_free_r+0x8a> 8004e20: f851 3c04 ldr.w r3, [r1, #-4] 8004e24: 1f0c subs r4, r1, #4 8004e26: 2b00 cmp r3, #0 8004e28: bfb8 it lt 8004e2a: 18e4 addlt r4, r4, r3 8004e2c: f000 fa98 bl 8005360 <__malloc_lock> 8004e30: 4a1c ldr r2, [pc, #112] ; (8004ea4 <_free_r+0x8c>) 8004e32: 6813 ldr r3, [r2, #0] 8004e34: b933 cbnz r3, 8004e44 <_free_r+0x2c> 8004e36: 6063 str r3, [r4, #4] 8004e38: 6014 str r4, [r2, #0] 8004e3a: 4628 mov r0, r5 8004e3c: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} 8004e40: f000 ba94 b.w 800536c <__malloc_unlock> 8004e44: 42a3 cmp r3, r4 8004e46: d908 bls.n 8004e5a <_free_r+0x42> 8004e48: 6820 ldr r0, [r4, #0] 8004e4a: 1821 adds r1, r4, r0 8004e4c: 428b cmp r3, r1 8004e4e: bf01 itttt eq 8004e50: 6819 ldreq r1, [r3, #0] 8004e52: 685b ldreq r3, [r3, #4] 8004e54: 1809 addeq r1, r1, r0 8004e56: 6021 streq r1, [r4, #0] 8004e58: e7ed b.n 8004e36 <_free_r+0x1e> 8004e5a: 461a mov r2, r3 8004e5c: 685b ldr r3, [r3, #4] 8004e5e: b10b cbz r3, 8004e64 <_free_r+0x4c> 8004e60: 42a3 cmp r3, r4 8004e62: d9fa bls.n 8004e5a <_free_r+0x42> 8004e64: 6811 ldr r1, [r2, #0] 8004e66: 1850 adds r0, r2, r1 8004e68: 42a0 cmp r0, r4 8004e6a: d10b bne.n 8004e84 <_free_r+0x6c> 8004e6c: 6820 ldr r0, [r4, #0] 8004e6e: 4401 add r1, r0 8004e70: 1850 adds r0, r2, r1 8004e72: 4283 cmp r3, r0 8004e74: 6011 str r1, [r2, #0] 8004e76: d1e0 bne.n 8004e3a <_free_r+0x22> 8004e78: 6818 ldr r0, [r3, #0] 8004e7a: 685b ldr r3, [r3, #4] 8004e7c: 4401 add r1, r0 8004e7e: 6011 str r1, [r2, #0] 8004e80: 6053 str r3, [r2, #4] 8004e82: e7da b.n 8004e3a <_free_r+0x22> 8004e84: d902 bls.n 8004e8c <_free_r+0x74> 8004e86: 230c movs r3, #12 8004e88: 602b str r3, [r5, #0] 8004e8a: e7d6 b.n 8004e3a <_free_r+0x22> 8004e8c: 6820 ldr r0, [r4, #0] 8004e8e: 1821 adds r1, r4, r0 8004e90: 428b cmp r3, r1 8004e92: bf01 itttt eq 8004e94: 6819 ldreq r1, [r3, #0] 8004e96: 685b ldreq r3, [r3, #4] 8004e98: 1809 addeq r1, r1, r0 8004e9a: 6021 streq r1, [r4, #0] 8004e9c: 6063 str r3, [r4, #4] 8004e9e: 6054 str r4, [r2, #4] 8004ea0: e7cb b.n 8004e3a <_free_r+0x22> 8004ea2: bd38 pop {r3, r4, r5, pc} 8004ea4: 20000274 .word 0x20000274 08004ea8 : 8004ea8: b570 push {r4, r5, r6, lr} 8004eaa: 4e0e ldr r6, [pc, #56] ; (8004ee4 ) 8004eac: 460c mov r4, r1 8004eae: 6831 ldr r1, [r6, #0] 8004eb0: 4605 mov r5, r0 8004eb2: b911 cbnz r1, 8004eba 8004eb4: f000 f9e8 bl 8005288 <_sbrk_r> 8004eb8: 6030 str r0, [r6, #0] 8004eba: 4621 mov r1, r4 8004ebc: 4628 mov r0, r5 8004ebe: f000 f9e3 bl 8005288 <_sbrk_r> 8004ec2: 1c43 adds r3, r0, #1 8004ec4: d00a beq.n 8004edc 8004ec6: 1cc4 adds r4, r0, #3 8004ec8: f024 0403 bic.w r4, r4, #3 8004ecc: 42a0 cmp r0, r4 8004ece: d007 beq.n 8004ee0 8004ed0: 1a21 subs r1, r4, r0 8004ed2: 4628 mov r0, r5 8004ed4: f000 f9d8 bl 8005288 <_sbrk_r> 8004ed8: 3001 adds r0, #1 8004eda: d101 bne.n 8004ee0 8004edc: f04f 34ff mov.w r4, #4294967295 8004ee0: 4620 mov r0, r4 8004ee2: bd70 pop {r4, r5, r6, pc} 8004ee4: 20000278 .word 0x20000278 08004ee8 <_malloc_r>: 8004ee8: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} 8004eec: 1ccd adds r5, r1, #3 8004eee: f025 0503 bic.w r5, r5, #3 8004ef2: 3508 adds r5, #8 8004ef4: 2d0c cmp r5, #12 8004ef6: bf38 it cc 8004ef8: 250c movcc r5, #12 8004efa: 2d00 cmp r5, #0 8004efc: 4607 mov r7, r0 8004efe: db01 blt.n 8004f04 <_malloc_r+0x1c> 8004f00: 42a9 cmp r1, r5 8004f02: d905 bls.n 8004f10 <_malloc_r+0x28> 8004f04: 230c movs r3, #12 8004f06: 2600 movs r6, #0 8004f08: 603b str r3, [r7, #0] 8004f0a: 4630 mov r0, r6 8004f0c: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} 8004f10: 4e2e ldr r6, [pc, #184] ; (8004fcc <_malloc_r+0xe4>) 8004f12: f000 fa25 bl 8005360 <__malloc_lock> 8004f16: 6833 ldr r3, [r6, #0] 8004f18: 461c mov r4, r3 8004f1a: bb34 cbnz r4, 8004f6a <_malloc_r+0x82> 8004f1c: 4629 mov r1, r5 8004f1e: 4638 mov r0, r7 8004f20: f7ff ffc2 bl 8004ea8 8004f24: 1c43 adds r3, r0, #1 8004f26: 4604 mov r4, r0 8004f28: d14d bne.n 8004fc6 <_malloc_r+0xde> 8004f2a: 6834 ldr r4, [r6, #0] 8004f2c: 4626 mov r6, r4 8004f2e: 2e00 cmp r6, #0 8004f30: d140 bne.n 8004fb4 <_malloc_r+0xcc> 8004f32: 6823 ldr r3, [r4, #0] 8004f34: 4631 mov r1, r6 8004f36: 4638 mov r0, r7 8004f38: eb04 0803 add.w r8, r4, r3 8004f3c: f000 f9a4 bl 8005288 <_sbrk_r> 8004f40: 4580 cmp r8, r0 8004f42: d13a bne.n 8004fba <_malloc_r+0xd2> 8004f44: 6821 ldr r1, [r4, #0] 8004f46: 3503 adds r5, #3 8004f48: 1a6d subs r5, r5, r1 8004f4a: f025 0503 bic.w r5, r5, #3 8004f4e: 3508 adds r5, #8 8004f50: 2d0c cmp r5, #12 8004f52: bf38 it cc 8004f54: 250c movcc r5, #12 8004f56: 4638 mov r0, r7 8004f58: 4629 mov r1, r5 8004f5a: f7ff ffa5 bl 8004ea8 8004f5e: 3001 adds r0, #1 8004f60: d02b beq.n 8004fba <_malloc_r+0xd2> 8004f62: 6823 ldr r3, [r4, #0] 8004f64: 442b add r3, r5 8004f66: 6023 str r3, [r4, #0] 8004f68: e00e b.n 8004f88 <_malloc_r+0xa0> 8004f6a: 6822 ldr r2, [r4, #0] 8004f6c: 1b52 subs r2, r2, r5 8004f6e: d41e bmi.n 8004fae <_malloc_r+0xc6> 8004f70: 2a0b cmp r2, #11 8004f72: d916 bls.n 8004fa2 <_malloc_r+0xba> 8004f74: 1961 adds r1, r4, r5 8004f76: 42a3 cmp r3, r4 8004f78: 6025 str r5, [r4, #0] 8004f7a: bf18 it ne 8004f7c: 6059 strne r1, [r3, #4] 8004f7e: 6863 ldr r3, [r4, #4] 8004f80: bf08 it eq 8004f82: 6031 streq r1, [r6, #0] 8004f84: 5162 str r2, [r4, r5] 8004f86: 604b str r3, [r1, #4] 8004f88: 4638 mov r0, r7 8004f8a: f104 060b add.w r6, r4, #11 8004f8e: f000 f9ed bl 800536c <__malloc_unlock> 8004f92: f026 0607 bic.w r6, r6, #7 8004f96: 1d23 adds r3, r4, #4 8004f98: 1af2 subs r2, r6, r3 8004f9a: d0b6 beq.n 8004f0a <_malloc_r+0x22> 8004f9c: 1b9b subs r3, r3, r6 8004f9e: 50a3 str r3, [r4, r2] 8004fa0: e7b3 b.n 8004f0a <_malloc_r+0x22> 8004fa2: 6862 ldr r2, [r4, #4] 8004fa4: 42a3 cmp r3, r4 8004fa6: bf0c ite eq 8004fa8: 6032 streq r2, [r6, #0] 8004faa: 605a strne r2, [r3, #4] 8004fac: e7ec b.n 8004f88 <_malloc_r+0xa0> 8004fae: 4623 mov r3, r4 8004fb0: 6864 ldr r4, [r4, #4] 8004fb2: e7b2 b.n 8004f1a <_malloc_r+0x32> 8004fb4: 4634 mov r4, r6 8004fb6: 6876 ldr r6, [r6, #4] 8004fb8: e7b9 b.n 8004f2e <_malloc_r+0x46> 8004fba: 230c movs r3, #12 8004fbc: 4638 mov r0, r7 8004fbe: 603b str r3, [r7, #0] 8004fc0: f000 f9d4 bl 800536c <__malloc_unlock> 8004fc4: e7a1 b.n 8004f0a <_malloc_r+0x22> 8004fc6: 6025 str r5, [r4, #0] 8004fc8: e7de b.n 8004f88 <_malloc_r+0xa0> 8004fca: bf00 nop 8004fcc: 20000274 .word 0x20000274 08004fd0 <__ssputs_r>: 8004fd0: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 8004fd4: 688e ldr r6, [r1, #8] 8004fd6: 4682 mov sl, r0 8004fd8: 429e cmp r6, r3 8004fda: 460c mov r4, r1 8004fdc: 4690 mov r8, r2 8004fde: 461f mov r7, r3 8004fe0: d838 bhi.n 8005054 <__ssputs_r+0x84> 8004fe2: 898a ldrh r2, [r1, #12] 8004fe4: f412 6f90 tst.w r2, #1152 ; 0x480 8004fe8: d032 beq.n 8005050 <__ssputs_r+0x80> 8004fea: 6825 ldr r5, [r4, #0] 8004fec: 6909 ldr r1, [r1, #16] 8004fee: 3301 adds r3, #1 8004ff0: eba5 0901 sub.w r9, r5, r1 8004ff4: 6965 ldr r5, [r4, #20] 8004ff6: 444b add r3, r9 8004ff8: eb05 0545 add.w r5, r5, r5, lsl #1 8004ffc: eb05 75d5 add.w r5, r5, r5, lsr #31 8005000: 106d asrs r5, r5, #1 8005002: 429d cmp r5, r3 8005004: bf38 it cc 8005006: 461d movcc r5, r3 8005008: 0553 lsls r3, r2, #21 800500a: d531 bpl.n 8005070 <__ssputs_r+0xa0> 800500c: 4629 mov r1, r5 800500e: f7ff ff6b bl 8004ee8 <_malloc_r> 8005012: 4606 mov r6, r0 8005014: b950 cbnz r0, 800502c <__ssputs_r+0x5c> 8005016: 230c movs r3, #12 8005018: f04f 30ff mov.w r0, #4294967295 800501c: f8ca 3000 str.w r3, [sl] 8005020: 89a3 ldrh r3, [r4, #12] 8005022: f043 0340 orr.w r3, r3, #64 ; 0x40 8005026: 81a3 strh r3, [r4, #12] 8005028: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 800502c: 464a mov r2, r9 800502e: 6921 ldr r1, [r4, #16] 8005030: f7ff fb4e bl 80046d0 8005034: 89a3 ldrh r3, [r4, #12] 8005036: f423 6390 bic.w r3, r3, #1152 ; 0x480 800503a: f043 0380 orr.w r3, r3, #128 ; 0x80 800503e: 81a3 strh r3, [r4, #12] 8005040: 6126 str r6, [r4, #16] 8005042: 444e add r6, r9 8005044: 6026 str r6, [r4, #0] 8005046: 463e mov r6, r7 8005048: 6165 str r5, [r4, #20] 800504a: eba5 0509 sub.w r5, r5, r9 800504e: 60a5 str r5, [r4, #8] 8005050: 42be cmp r6, r7 8005052: d900 bls.n 8005056 <__ssputs_r+0x86> 8005054: 463e mov r6, r7 8005056: 4632 mov r2, r6 8005058: 4641 mov r1, r8 800505a: 6820 ldr r0, [r4, #0] 800505c: f000 f966 bl 800532c 8005060: 68a3 ldr r3, [r4, #8] 8005062: 2000 movs r0, #0 8005064: 1b9b subs r3, r3, r6 8005066: 60a3 str r3, [r4, #8] 8005068: 6823 ldr r3, [r4, #0] 800506a: 4433 add r3, r6 800506c: 6023 str r3, [r4, #0] 800506e: e7db b.n 8005028 <__ssputs_r+0x58> 8005070: 462a mov r2, r5 8005072: f000 f981 bl 8005378 <_realloc_r> 8005076: 4606 mov r6, r0 8005078: 2800 cmp r0, #0 800507a: d1e1 bne.n 8005040 <__ssputs_r+0x70> 800507c: 4650 mov r0, sl 800507e: 6921 ldr r1, [r4, #16] 8005080: f7ff feca bl 8004e18 <_free_r> 8005084: e7c7 b.n 8005016 <__ssputs_r+0x46> ... 08005088 <_svfiprintf_r>: 8005088: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 800508c: 4698 mov r8, r3 800508e: 898b ldrh r3, [r1, #12] 8005090: 4607 mov r7, r0 8005092: 061b lsls r3, r3, #24 8005094: 460d mov r5, r1 8005096: 4614 mov r4, r2 8005098: b09d sub sp, #116 ; 0x74 800509a: d50e bpl.n 80050ba <_svfiprintf_r+0x32> 800509c: 690b ldr r3, [r1, #16] 800509e: b963 cbnz r3, 80050ba <_svfiprintf_r+0x32> 80050a0: 2140 movs r1, #64 ; 0x40 80050a2: f7ff ff21 bl 8004ee8 <_malloc_r> 80050a6: 6028 str r0, [r5, #0] 80050a8: 6128 str r0, [r5, #16] 80050aa: b920 cbnz r0, 80050b6 <_svfiprintf_r+0x2e> 80050ac: 230c movs r3, #12 80050ae: 603b str r3, [r7, #0] 80050b0: f04f 30ff mov.w r0, #4294967295 80050b4: e0d1 b.n 800525a <_svfiprintf_r+0x1d2> 80050b6: 2340 movs r3, #64 ; 0x40 80050b8: 616b str r3, [r5, #20] 80050ba: 2300 movs r3, #0 80050bc: 9309 str r3, [sp, #36] ; 0x24 80050be: 2320 movs r3, #32 80050c0: f88d 3029 strb.w r3, [sp, #41] ; 0x29 80050c4: 2330 movs r3, #48 ; 0x30 80050c6: f04f 0901 mov.w r9, #1 80050ca: f8cd 800c str.w r8, [sp, #12] 80050ce: f8df 81a4 ldr.w r8, [pc, #420] ; 8005274 <_svfiprintf_r+0x1ec> 80050d2: f88d 302a strb.w r3, [sp, #42] ; 0x2a 80050d6: 4623 mov r3, r4 80050d8: 469a mov sl, r3 80050da: f813 2b01 ldrb.w r2, [r3], #1 80050de: b10a cbz r2, 80050e4 <_svfiprintf_r+0x5c> 80050e0: 2a25 cmp r2, #37 ; 0x25 80050e2: d1f9 bne.n 80050d8 <_svfiprintf_r+0x50> 80050e4: ebba 0b04 subs.w fp, sl, r4 80050e8: d00b beq.n 8005102 <_svfiprintf_r+0x7a> 80050ea: 465b mov r3, fp 80050ec: 4622 mov r2, r4 80050ee: 4629 mov r1, r5 80050f0: 4638 mov r0, r7 80050f2: f7ff ff6d bl 8004fd0 <__ssputs_r> 80050f6: 3001 adds r0, #1 80050f8: f000 80aa beq.w 8005250 <_svfiprintf_r+0x1c8> 80050fc: 9a09 ldr r2, [sp, #36] ; 0x24 80050fe: 445a add r2, fp 8005100: 9209 str r2, [sp, #36] ; 0x24 8005102: f89a 3000 ldrb.w r3, [sl] 8005106: 2b00 cmp r3, #0 8005108: f000 80a2 beq.w 8005250 <_svfiprintf_r+0x1c8> 800510c: 2300 movs r3, #0 800510e: f04f 32ff mov.w r2, #4294967295 8005112: e9cd 2305 strd r2, r3, [sp, #20] 8005116: f10a 0a01 add.w sl, sl, #1 800511a: 9304 str r3, [sp, #16] 800511c: 9307 str r3, [sp, #28] 800511e: f88d 3053 strb.w r3, [sp, #83] ; 0x53 8005122: 931a str r3, [sp, #104] ; 0x68 8005124: 4654 mov r4, sl 8005126: 2205 movs r2, #5 8005128: f814 1b01 ldrb.w r1, [r4], #1 800512c: 4851 ldr r0, [pc, #324] ; (8005274 <_svfiprintf_r+0x1ec>) 800512e: f7ff fac1 bl 80046b4 8005132: 9a04 ldr r2, [sp, #16] 8005134: b9d8 cbnz r0, 800516e <_svfiprintf_r+0xe6> 8005136: 06d0 lsls r0, r2, #27 8005138: bf44 itt mi 800513a: 2320 movmi r3, #32 800513c: f88d 3053 strbmi.w r3, [sp, #83] ; 0x53 8005140: 0711 lsls r1, r2, #28 8005142: bf44 itt mi 8005144: 232b movmi r3, #43 ; 0x2b 8005146: f88d 3053 strbmi.w r3, [sp, #83] ; 0x53 800514a: f89a 3000 ldrb.w r3, [sl] 800514e: 2b2a cmp r3, #42 ; 0x2a 8005150: d015 beq.n 800517e <_svfiprintf_r+0xf6> 8005152: 4654 mov r4, sl 8005154: 2000 movs r0, #0 8005156: f04f 0c0a mov.w ip, #10 800515a: 9a07 ldr r2, [sp, #28] 800515c: 4621 mov r1, r4 800515e: f811 3b01 ldrb.w r3, [r1], #1 8005162: 3b30 subs r3, #48 ; 0x30 8005164: 2b09 cmp r3, #9 8005166: d94e bls.n 8005206 <_svfiprintf_r+0x17e> 8005168: b1b0 cbz r0, 8005198 <_svfiprintf_r+0x110> 800516a: 9207 str r2, [sp, #28] 800516c: e014 b.n 8005198 <_svfiprintf_r+0x110> 800516e: eba0 0308 sub.w r3, r0, r8 8005172: fa09 f303 lsl.w r3, r9, r3 8005176: 4313 orrs r3, r2 8005178: 46a2 mov sl, r4 800517a: 9304 str r3, [sp, #16] 800517c: e7d2 b.n 8005124 <_svfiprintf_r+0x9c> 800517e: 9b03 ldr r3, [sp, #12] 8005180: 1d19 adds r1, r3, #4 8005182: 681b ldr r3, [r3, #0] 8005184: 9103 str r1, [sp, #12] 8005186: 2b00 cmp r3, #0 8005188: bfbb ittet lt 800518a: 425b neglt r3, r3 800518c: f042 0202 orrlt.w r2, r2, #2 8005190: 9307 strge r3, [sp, #28] 8005192: 9307 strlt r3, [sp, #28] 8005194: bfb8 it lt 8005196: 9204 strlt r2, [sp, #16] 8005198: 7823 ldrb r3, [r4, #0] 800519a: 2b2e cmp r3, #46 ; 0x2e 800519c: d10c bne.n 80051b8 <_svfiprintf_r+0x130> 800519e: 7863 ldrb r3, [r4, #1] 80051a0: 2b2a cmp r3, #42 ; 0x2a 80051a2: d135 bne.n 8005210 <_svfiprintf_r+0x188> 80051a4: 9b03 ldr r3, [sp, #12] 80051a6: 3402 adds r4, #2 80051a8: 1d1a adds r2, r3, #4 80051aa: 681b ldr r3, [r3, #0] 80051ac: 9203 str r2, [sp, #12] 80051ae: 2b00 cmp r3, #0 80051b0: bfb8 it lt 80051b2: f04f 33ff movlt.w r3, #4294967295 80051b6: 9305 str r3, [sp, #20] 80051b8: f8df a0bc ldr.w sl, [pc, #188] ; 8005278 <_svfiprintf_r+0x1f0> 80051bc: 2203 movs r2, #3 80051be: 4650 mov r0, sl 80051c0: 7821 ldrb r1, [r4, #0] 80051c2: f7ff fa77 bl 80046b4 80051c6: b140 cbz r0, 80051da <_svfiprintf_r+0x152> 80051c8: 2340 movs r3, #64 ; 0x40 80051ca: eba0 000a sub.w r0, r0, sl 80051ce: fa03 f000 lsl.w r0, r3, r0 80051d2: 9b04 ldr r3, [sp, #16] 80051d4: 3401 adds r4, #1 80051d6: 4303 orrs r3, r0 80051d8: 9304 str r3, [sp, #16] 80051da: f814 1b01 ldrb.w r1, [r4], #1 80051de: 2206 movs r2, #6 80051e0: 4826 ldr r0, [pc, #152] ; (800527c <_svfiprintf_r+0x1f4>) 80051e2: f88d 1028 strb.w r1, [sp, #40] ; 0x28 80051e6: f7ff fa65 bl 80046b4 80051ea: 2800 cmp r0, #0 80051ec: d038 beq.n 8005260 <_svfiprintf_r+0x1d8> 80051ee: 4b24 ldr r3, [pc, #144] ; (8005280 <_svfiprintf_r+0x1f8>) 80051f0: bb1b cbnz r3, 800523a <_svfiprintf_r+0x1b2> 80051f2: 9b03 ldr r3, [sp, #12] 80051f4: 3307 adds r3, #7 80051f6: f023 0307 bic.w r3, r3, #7 80051fa: 3308 adds r3, #8 80051fc: 9303 str r3, [sp, #12] 80051fe: 9b09 ldr r3, [sp, #36] ; 0x24 8005200: 4433 add r3, r6 8005202: 9309 str r3, [sp, #36] ; 0x24 8005204: e767 b.n 80050d6 <_svfiprintf_r+0x4e> 8005206: 460c mov r4, r1 8005208: 2001 movs r0, #1 800520a: fb0c 3202 mla r2, ip, r2, r3 800520e: e7a5 b.n 800515c <_svfiprintf_r+0xd4> 8005210: 2300 movs r3, #0 8005212: f04f 0c0a mov.w ip, #10 8005216: 4619 mov r1, r3 8005218: 3401 adds r4, #1 800521a: 9305 str r3, [sp, #20] 800521c: 4620 mov r0, r4 800521e: f810 2b01 ldrb.w r2, [r0], #1 8005222: 3a30 subs r2, #48 ; 0x30 8005224: 2a09 cmp r2, #9 8005226: d903 bls.n 8005230 <_svfiprintf_r+0x1a8> 8005228: 2b00 cmp r3, #0 800522a: d0c5 beq.n 80051b8 <_svfiprintf_r+0x130> 800522c: 9105 str r1, [sp, #20] 800522e: e7c3 b.n 80051b8 <_svfiprintf_r+0x130> 8005230: 4604 mov r4, r0 8005232: 2301 movs r3, #1 8005234: fb0c 2101 mla r1, ip, r1, r2 8005238: e7f0 b.n 800521c <_svfiprintf_r+0x194> 800523a: ab03 add r3, sp, #12 800523c: 9300 str r3, [sp, #0] 800523e: 462a mov r2, r5 8005240: 4638 mov r0, r7 8005242: 4b10 ldr r3, [pc, #64] ; (8005284 <_svfiprintf_r+0x1fc>) 8005244: a904 add r1, sp, #16 8005246: f7fd ffcd bl 80031e4 <_printf_float> 800524a: 1c42 adds r2, r0, #1 800524c: 4606 mov r6, r0 800524e: d1d6 bne.n 80051fe <_svfiprintf_r+0x176> 8005250: 89ab ldrh r3, [r5, #12] 8005252: 065b lsls r3, r3, #25 8005254: f53f af2c bmi.w 80050b0 <_svfiprintf_r+0x28> 8005258: 9809 ldr r0, [sp, #36] ; 0x24 800525a: b01d add sp, #116 ; 0x74 800525c: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 8005260: ab03 add r3, sp, #12 8005262: 9300 str r3, [sp, #0] 8005264: 462a mov r2, r5 8005266: 4638 mov r0, r7 8005268: 4b06 ldr r3, [pc, #24] ; (8005284 <_svfiprintf_r+0x1fc>) 800526a: a904 add r1, sp, #16 800526c: f7fe fa56 bl 800371c <_printf_i> 8005270: e7eb b.n 800524a <_svfiprintf_r+0x1c2> 8005272: bf00 nop 8005274: 0800649c .word 0x0800649c 8005278: 080064a2 .word 0x080064a2 800527c: 080064a6 .word 0x080064a6 8005280: 080031e5 .word 0x080031e5 8005284: 08004fd1 .word 0x08004fd1 08005288 <_sbrk_r>: 8005288: b538 push {r3, r4, r5, lr} 800528a: 2300 movs r3, #0 800528c: 4d05 ldr r5, [pc, #20] ; (80052a4 <_sbrk_r+0x1c>) 800528e: 4604 mov r4, r0 8005290: 4608 mov r0, r1 8005292: 602b str r3, [r5, #0] 8005294: f7fc f964 bl 8001560 <_sbrk> 8005298: 1c43 adds r3, r0, #1 800529a: d102 bne.n 80052a2 <_sbrk_r+0x1a> 800529c: 682b ldr r3, [r5, #0] 800529e: b103 cbz r3, 80052a2 <_sbrk_r+0x1a> 80052a0: 6023 str r3, [r4, #0] 80052a2: bd38 pop {r3, r4, r5, pc} 80052a4: 2000027c .word 0x2000027c 080052a8 <__assert_func>: 80052a8: b51f push {r0, r1, r2, r3, r4, lr} 80052aa: 4614 mov r4, r2 80052ac: 461a mov r2, r3 80052ae: 4b09 ldr r3, [pc, #36] ; (80052d4 <__assert_func+0x2c>) 80052b0: 4605 mov r5, r0 80052b2: 681b ldr r3, [r3, #0] 80052b4: 68d8 ldr r0, [r3, #12] 80052b6: b14c cbz r4, 80052cc <__assert_func+0x24> 80052b8: 4b07 ldr r3, [pc, #28] ; (80052d8 <__assert_func+0x30>) 80052ba: e9cd 3401 strd r3, r4, [sp, #4] 80052be: 9100 str r1, [sp, #0] 80052c0: 462b mov r3, r5 80052c2: 4906 ldr r1, [pc, #24] ; (80052dc <__assert_func+0x34>) 80052c4: f000 f80e bl 80052e4 80052c8: f000 faaa bl 8005820 80052cc: 4b04 ldr r3, [pc, #16] ; (80052e0 <__assert_func+0x38>) 80052ce: 461c mov r4, r3 80052d0: e7f3 b.n 80052ba <__assert_func+0x12> 80052d2: bf00 nop 80052d4: 2000000c .word 0x2000000c 80052d8: 080064ad .word 0x080064ad 80052dc: 080064ba .word 0x080064ba 80052e0: 080064e8 .word 0x080064e8 080052e4 : 80052e4: b40e push {r1, r2, r3} 80052e6: b503 push {r0, r1, lr} 80052e8: 4601 mov r1, r0 80052ea: ab03 add r3, sp, #12 80052ec: 4805 ldr r0, [pc, #20] ; (8005304 ) 80052ee: f853 2b04 ldr.w r2, [r3], #4 80052f2: 6800 ldr r0, [r0, #0] 80052f4: 9301 str r3, [sp, #4] 80052f6: f000 f895 bl 8005424 <_vfiprintf_r> 80052fa: b002 add sp, #8 80052fc: f85d eb04 ldr.w lr, [sp], #4 8005300: b003 add sp, #12 8005302: 4770 bx lr 8005304: 2000000c .word 0x2000000c 08005308 <__ascii_mbtowc>: 8005308: b082 sub sp, #8 800530a: b901 cbnz r1, 800530e <__ascii_mbtowc+0x6> 800530c: a901 add r1, sp, #4 800530e: b142 cbz r2, 8005322 <__ascii_mbtowc+0x1a> 8005310: b14b cbz r3, 8005326 <__ascii_mbtowc+0x1e> 8005312: 7813 ldrb r3, [r2, #0] 8005314: 600b str r3, [r1, #0] 8005316: 7812 ldrb r2, [r2, #0] 8005318: 1e10 subs r0, r2, #0 800531a: bf18 it ne 800531c: 2001 movne r0, #1 800531e: b002 add sp, #8 8005320: 4770 bx lr 8005322: 4610 mov r0, r2 8005324: e7fb b.n 800531e <__ascii_mbtowc+0x16> 8005326: f06f 0001 mvn.w r0, #1 800532a: e7f8 b.n 800531e <__ascii_mbtowc+0x16> 0800532c : 800532c: 4288 cmp r0, r1 800532e: b510 push {r4, lr} 8005330: eb01 0402 add.w r4, r1, r2 8005334: d902 bls.n 800533c 8005336: 4284 cmp r4, r0 8005338: 4623 mov r3, r4 800533a: d807 bhi.n 800534c 800533c: 1e43 subs r3, r0, #1 800533e: 42a1 cmp r1, r4 8005340: d008 beq.n 8005354 8005342: f811 2b01 ldrb.w r2, [r1], #1 8005346: f803 2f01 strb.w r2, [r3, #1]! 800534a: e7f8 b.n 800533e 800534c: 4601 mov r1, r0 800534e: 4402 add r2, r0 8005350: 428a cmp r2, r1 8005352: d100 bne.n 8005356 8005354: bd10 pop {r4, pc} 8005356: f813 4d01 ldrb.w r4, [r3, #-1]! 800535a: f802 4d01 strb.w r4, [r2, #-1]! 800535e: e7f7 b.n 8005350 08005360 <__malloc_lock>: 8005360: 4801 ldr r0, [pc, #4] ; (8005368 <__malloc_lock+0x8>) 8005362: f000 bc19 b.w 8005b98 <__retarget_lock_acquire_recursive> 8005366: bf00 nop 8005368: 20000280 .word 0x20000280 0800536c <__malloc_unlock>: 800536c: 4801 ldr r0, [pc, #4] ; (8005374 <__malloc_unlock+0x8>) 800536e: f000 bc14 b.w 8005b9a <__retarget_lock_release_recursive> 8005372: bf00 nop 8005374: 20000280 .word 0x20000280 08005378 <_realloc_r>: 8005378: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} 800537c: 4680 mov r8, r0 800537e: 4614 mov r4, r2 8005380: 460e mov r6, r1 8005382: b921 cbnz r1, 800538e <_realloc_r+0x16> 8005384: 4611 mov r1, r2 8005386: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} 800538a: f7ff bdad b.w 8004ee8 <_malloc_r> 800538e: b92a cbnz r2, 800539c <_realloc_r+0x24> 8005390: f7ff fd42 bl 8004e18 <_free_r> 8005394: 4625 mov r5, r4 8005396: 4628 mov r0, r5 8005398: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} 800539c: f000 fc64 bl 8005c68 <_malloc_usable_size_r> 80053a0: 4284 cmp r4, r0 80053a2: 4607 mov r7, r0 80053a4: d802 bhi.n 80053ac <_realloc_r+0x34> 80053a6: ebb4 0f50 cmp.w r4, r0, lsr #1 80053aa: d812 bhi.n 80053d2 <_realloc_r+0x5a> 80053ac: 4621 mov r1, r4 80053ae: 4640 mov r0, r8 80053b0: f7ff fd9a bl 8004ee8 <_malloc_r> 80053b4: 4605 mov r5, r0 80053b6: 2800 cmp r0, #0 80053b8: d0ed beq.n 8005396 <_realloc_r+0x1e> 80053ba: 42bc cmp r4, r7 80053bc: 4622 mov r2, r4 80053be: 4631 mov r1, r6 80053c0: bf28 it cs 80053c2: 463a movcs r2, r7 80053c4: f7ff f984 bl 80046d0 80053c8: 4631 mov r1, r6 80053ca: 4640 mov r0, r8 80053cc: f7ff fd24 bl 8004e18 <_free_r> 80053d0: e7e1 b.n 8005396 <_realloc_r+0x1e> 80053d2: 4635 mov r5, r6 80053d4: e7df b.n 8005396 <_realloc_r+0x1e> 080053d6 <__sfputc_r>: 80053d6: 6893 ldr r3, [r2, #8] 80053d8: b410 push {r4} 80053da: 3b01 subs r3, #1 80053dc: 2b00 cmp r3, #0 80053de: 6093 str r3, [r2, #8] 80053e0: da07 bge.n 80053f2 <__sfputc_r+0x1c> 80053e2: 6994 ldr r4, [r2, #24] 80053e4: 42a3 cmp r3, r4 80053e6: db01 blt.n 80053ec <__sfputc_r+0x16> 80053e8: 290a cmp r1, #10 80053ea: d102 bne.n 80053f2 <__sfputc_r+0x1c> 80053ec: bc10 pop {r4} 80053ee: f000 b949 b.w 8005684 <__swbuf_r> 80053f2: 6813 ldr r3, [r2, #0] 80053f4: 1c58 adds r0, r3, #1 80053f6: 6010 str r0, [r2, #0] 80053f8: 7019 strb r1, [r3, #0] 80053fa: 4608 mov r0, r1 80053fc: bc10 pop {r4} 80053fe: 4770 bx lr 08005400 <__sfputs_r>: 8005400: b5f8 push {r3, r4, r5, r6, r7, lr} 8005402: 4606 mov r6, r0 8005404: 460f mov r7, r1 8005406: 4614 mov r4, r2 8005408: 18d5 adds r5, r2, r3 800540a: 42ac cmp r4, r5 800540c: d101 bne.n 8005412 <__sfputs_r+0x12> 800540e: 2000 movs r0, #0 8005410: e007 b.n 8005422 <__sfputs_r+0x22> 8005412: 463a mov r2, r7 8005414: 4630 mov r0, r6 8005416: f814 1b01 ldrb.w r1, [r4], #1 800541a: f7ff ffdc bl 80053d6 <__sfputc_r> 800541e: 1c43 adds r3, r0, #1 8005420: d1f3 bne.n 800540a <__sfputs_r+0xa> 8005422: bdf8 pop {r3, r4, r5, r6, r7, pc} 08005424 <_vfiprintf_r>: 8005424: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 8005428: 460d mov r5, r1 800542a: 4614 mov r4, r2 800542c: 4698 mov r8, r3 800542e: 4606 mov r6, r0 8005430: b09d sub sp, #116 ; 0x74 8005432: b118 cbz r0, 800543c <_vfiprintf_r+0x18> 8005434: 6983 ldr r3, [r0, #24] 8005436: b90b cbnz r3, 800543c <_vfiprintf_r+0x18> 8005438: f000 fb10 bl 8005a5c <__sinit> 800543c: 4b89 ldr r3, [pc, #548] ; (8005664 <_vfiprintf_r+0x240>) 800543e: 429d cmp r5, r3 8005440: d11b bne.n 800547a <_vfiprintf_r+0x56> 8005442: 6875 ldr r5, [r6, #4] 8005444: 6e6b ldr r3, [r5, #100] ; 0x64 8005446: 07d9 lsls r1, r3, #31 8005448: d405 bmi.n 8005456 <_vfiprintf_r+0x32> 800544a: 89ab ldrh r3, [r5, #12] 800544c: 059a lsls r2, r3, #22 800544e: d402 bmi.n 8005456 <_vfiprintf_r+0x32> 8005450: 6da8 ldr r0, [r5, #88] ; 0x58 8005452: f000 fba1 bl 8005b98 <__retarget_lock_acquire_recursive> 8005456: 89ab ldrh r3, [r5, #12] 8005458: 071b lsls r3, r3, #28 800545a: d501 bpl.n 8005460 <_vfiprintf_r+0x3c> 800545c: 692b ldr r3, [r5, #16] 800545e: b9eb cbnz r3, 800549c <_vfiprintf_r+0x78> 8005460: 4629 mov r1, r5 8005462: 4630 mov r0, r6 8005464: f000 f96e bl 8005744 <__swsetup_r> 8005468: b1c0 cbz r0, 800549c <_vfiprintf_r+0x78> 800546a: 6e6b ldr r3, [r5, #100] ; 0x64 800546c: 07dc lsls r4, r3, #31 800546e: d50e bpl.n 800548e <_vfiprintf_r+0x6a> 8005470: f04f 30ff mov.w r0, #4294967295 8005474: b01d add sp, #116 ; 0x74 8005476: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 800547a: 4b7b ldr r3, [pc, #492] ; (8005668 <_vfiprintf_r+0x244>) 800547c: 429d cmp r5, r3 800547e: d101 bne.n 8005484 <_vfiprintf_r+0x60> 8005480: 68b5 ldr r5, [r6, #8] 8005482: e7df b.n 8005444 <_vfiprintf_r+0x20> 8005484: 4b79 ldr r3, [pc, #484] ; (800566c <_vfiprintf_r+0x248>) 8005486: 429d cmp r5, r3 8005488: bf08 it eq 800548a: 68f5 ldreq r5, [r6, #12] 800548c: e7da b.n 8005444 <_vfiprintf_r+0x20> 800548e: 89ab ldrh r3, [r5, #12] 8005490: 0598 lsls r0, r3, #22 8005492: d4ed bmi.n 8005470 <_vfiprintf_r+0x4c> 8005494: 6da8 ldr r0, [r5, #88] ; 0x58 8005496: f000 fb80 bl 8005b9a <__retarget_lock_release_recursive> 800549a: e7e9 b.n 8005470 <_vfiprintf_r+0x4c> 800549c: 2300 movs r3, #0 800549e: 9309 str r3, [sp, #36] ; 0x24 80054a0: 2320 movs r3, #32 80054a2: f88d 3029 strb.w r3, [sp, #41] ; 0x29 80054a6: 2330 movs r3, #48 ; 0x30 80054a8: f04f 0901 mov.w r9, #1 80054ac: f8cd 800c str.w r8, [sp, #12] 80054b0: f8df 81bc ldr.w r8, [pc, #444] ; 8005670 <_vfiprintf_r+0x24c> 80054b4: f88d 302a strb.w r3, [sp, #42] ; 0x2a 80054b8: 4623 mov r3, r4 80054ba: 469a mov sl, r3 80054bc: f813 2b01 ldrb.w r2, [r3], #1 80054c0: b10a cbz r2, 80054c6 <_vfiprintf_r+0xa2> 80054c2: 2a25 cmp r2, #37 ; 0x25 80054c4: d1f9 bne.n 80054ba <_vfiprintf_r+0x96> 80054c6: ebba 0b04 subs.w fp, sl, r4 80054ca: d00b beq.n 80054e4 <_vfiprintf_r+0xc0> 80054cc: 465b mov r3, fp 80054ce: 4622 mov r2, r4 80054d0: 4629 mov r1, r5 80054d2: 4630 mov r0, r6 80054d4: f7ff ff94 bl 8005400 <__sfputs_r> 80054d8: 3001 adds r0, #1 80054da: f000 80aa beq.w 8005632 <_vfiprintf_r+0x20e> 80054de: 9a09 ldr r2, [sp, #36] ; 0x24 80054e0: 445a add r2, fp 80054e2: 9209 str r2, [sp, #36] ; 0x24 80054e4: f89a 3000 ldrb.w r3, [sl] 80054e8: 2b00 cmp r3, #0 80054ea: f000 80a2 beq.w 8005632 <_vfiprintf_r+0x20e> 80054ee: 2300 movs r3, #0 80054f0: f04f 32ff mov.w r2, #4294967295 80054f4: e9cd 2305 strd r2, r3, [sp, #20] 80054f8: f10a 0a01 add.w sl, sl, #1 80054fc: 9304 str r3, [sp, #16] 80054fe: 9307 str r3, [sp, #28] 8005500: f88d 3053 strb.w r3, [sp, #83] ; 0x53 8005504: 931a str r3, [sp, #104] ; 0x68 8005506: 4654 mov r4, sl 8005508: 2205 movs r2, #5 800550a: f814 1b01 ldrb.w r1, [r4], #1 800550e: 4858 ldr r0, [pc, #352] ; (8005670 <_vfiprintf_r+0x24c>) 8005510: f7ff f8d0 bl 80046b4 8005514: 9a04 ldr r2, [sp, #16] 8005516: b9d8 cbnz r0, 8005550 <_vfiprintf_r+0x12c> 8005518: 06d1 lsls r1, r2, #27 800551a: bf44 itt mi 800551c: 2320 movmi r3, #32 800551e: f88d 3053 strbmi.w r3, [sp, #83] ; 0x53 8005522: 0713 lsls r3, r2, #28 8005524: bf44 itt mi 8005526: 232b movmi r3, #43 ; 0x2b 8005528: f88d 3053 strbmi.w r3, [sp, #83] ; 0x53 800552c: f89a 3000 ldrb.w r3, [sl] 8005530: 2b2a cmp r3, #42 ; 0x2a 8005532: d015 beq.n 8005560 <_vfiprintf_r+0x13c> 8005534: 4654 mov r4, sl 8005536: 2000 movs r0, #0 8005538: f04f 0c0a mov.w ip, #10 800553c: 9a07 ldr r2, [sp, #28] 800553e: 4621 mov r1, r4 8005540: f811 3b01 ldrb.w r3, [r1], #1 8005544: 3b30 subs r3, #48 ; 0x30 8005546: 2b09 cmp r3, #9 8005548: d94e bls.n 80055e8 <_vfiprintf_r+0x1c4> 800554a: b1b0 cbz r0, 800557a <_vfiprintf_r+0x156> 800554c: 9207 str r2, [sp, #28] 800554e: e014 b.n 800557a <_vfiprintf_r+0x156> 8005550: eba0 0308 sub.w r3, r0, r8 8005554: fa09 f303 lsl.w r3, r9, r3 8005558: 4313 orrs r3, r2 800555a: 46a2 mov sl, r4 800555c: 9304 str r3, [sp, #16] 800555e: e7d2 b.n 8005506 <_vfiprintf_r+0xe2> 8005560: 9b03 ldr r3, [sp, #12] 8005562: 1d19 adds r1, r3, #4 8005564: 681b ldr r3, [r3, #0] 8005566: 9103 str r1, [sp, #12] 8005568: 2b00 cmp r3, #0 800556a: bfbb ittet lt 800556c: 425b neglt r3, r3 800556e: f042 0202 orrlt.w r2, r2, #2 8005572: 9307 strge r3, [sp, #28] 8005574: 9307 strlt r3, [sp, #28] 8005576: bfb8 it lt 8005578: 9204 strlt r2, [sp, #16] 800557a: 7823 ldrb r3, [r4, #0] 800557c: 2b2e cmp r3, #46 ; 0x2e 800557e: d10c bne.n 800559a <_vfiprintf_r+0x176> 8005580: 7863 ldrb r3, [r4, #1] 8005582: 2b2a cmp r3, #42 ; 0x2a 8005584: d135 bne.n 80055f2 <_vfiprintf_r+0x1ce> 8005586: 9b03 ldr r3, [sp, #12] 8005588: 3402 adds r4, #2 800558a: 1d1a adds r2, r3, #4 800558c: 681b ldr r3, [r3, #0] 800558e: 9203 str r2, [sp, #12] 8005590: 2b00 cmp r3, #0 8005592: bfb8 it lt 8005594: f04f 33ff movlt.w r3, #4294967295 8005598: 9305 str r3, [sp, #20] 800559a: f8df a0d8 ldr.w sl, [pc, #216] ; 8005674 <_vfiprintf_r+0x250> 800559e: 2203 movs r2, #3 80055a0: 4650 mov r0, sl 80055a2: 7821 ldrb r1, [r4, #0] 80055a4: f7ff f886 bl 80046b4 80055a8: b140 cbz r0, 80055bc <_vfiprintf_r+0x198> 80055aa: 2340 movs r3, #64 ; 0x40 80055ac: eba0 000a sub.w r0, r0, sl 80055b0: fa03 f000 lsl.w r0, r3, r0 80055b4: 9b04 ldr r3, [sp, #16] 80055b6: 3401 adds r4, #1 80055b8: 4303 orrs r3, r0 80055ba: 9304 str r3, [sp, #16] 80055bc: f814 1b01 ldrb.w r1, [r4], #1 80055c0: 2206 movs r2, #6 80055c2: 482d ldr r0, [pc, #180] ; (8005678 <_vfiprintf_r+0x254>) 80055c4: f88d 1028 strb.w r1, [sp, #40] ; 0x28 80055c8: f7ff f874 bl 80046b4 80055cc: 2800 cmp r0, #0 80055ce: d03f beq.n 8005650 <_vfiprintf_r+0x22c> 80055d0: 4b2a ldr r3, [pc, #168] ; (800567c <_vfiprintf_r+0x258>) 80055d2: bb1b cbnz r3, 800561c <_vfiprintf_r+0x1f8> 80055d4: 9b03 ldr r3, [sp, #12] 80055d6: 3307 adds r3, #7 80055d8: f023 0307 bic.w r3, r3, #7 80055dc: 3308 adds r3, #8 80055de: 9303 str r3, [sp, #12] 80055e0: 9b09 ldr r3, [sp, #36] ; 0x24 80055e2: 443b add r3, r7 80055e4: 9309 str r3, [sp, #36] ; 0x24 80055e6: e767 b.n 80054b8 <_vfiprintf_r+0x94> 80055e8: 460c mov r4, r1 80055ea: 2001 movs r0, #1 80055ec: fb0c 3202 mla r2, ip, r2, r3 80055f0: e7a5 b.n 800553e <_vfiprintf_r+0x11a> 80055f2: 2300 movs r3, #0 80055f4: f04f 0c0a mov.w ip, #10 80055f8: 4619 mov r1, r3 80055fa: 3401 adds r4, #1 80055fc: 9305 str r3, [sp, #20] 80055fe: 4620 mov r0, r4 8005600: f810 2b01 ldrb.w r2, [r0], #1 8005604: 3a30 subs r2, #48 ; 0x30 8005606: 2a09 cmp r2, #9 8005608: d903 bls.n 8005612 <_vfiprintf_r+0x1ee> 800560a: 2b00 cmp r3, #0 800560c: d0c5 beq.n 800559a <_vfiprintf_r+0x176> 800560e: 9105 str r1, [sp, #20] 8005610: e7c3 b.n 800559a <_vfiprintf_r+0x176> 8005612: 4604 mov r4, r0 8005614: 2301 movs r3, #1 8005616: fb0c 2101 mla r1, ip, r1, r2 800561a: e7f0 b.n 80055fe <_vfiprintf_r+0x1da> 800561c: ab03 add r3, sp, #12 800561e: 9300 str r3, [sp, #0] 8005620: 462a mov r2, r5 8005622: 4630 mov r0, r6 8005624: 4b16 ldr r3, [pc, #88] ; (8005680 <_vfiprintf_r+0x25c>) 8005626: a904 add r1, sp, #16 8005628: f7fd fddc bl 80031e4 <_printf_float> 800562c: 4607 mov r7, r0 800562e: 1c78 adds r0, r7, #1 8005630: d1d6 bne.n 80055e0 <_vfiprintf_r+0x1bc> 8005632: 6e6b ldr r3, [r5, #100] ; 0x64 8005634: 07d9 lsls r1, r3, #31 8005636: d405 bmi.n 8005644 <_vfiprintf_r+0x220> 8005638: 89ab ldrh r3, [r5, #12] 800563a: 059a lsls r2, r3, #22 800563c: d402 bmi.n 8005644 <_vfiprintf_r+0x220> 800563e: 6da8 ldr r0, [r5, #88] ; 0x58 8005640: f000 faab bl 8005b9a <__retarget_lock_release_recursive> 8005644: 89ab ldrh r3, [r5, #12] 8005646: 065b lsls r3, r3, #25 8005648: f53f af12 bmi.w 8005470 <_vfiprintf_r+0x4c> 800564c: 9809 ldr r0, [sp, #36] ; 0x24 800564e: e711 b.n 8005474 <_vfiprintf_r+0x50> 8005650: ab03 add r3, sp, #12 8005652: 9300 str r3, [sp, #0] 8005654: 462a mov r2, r5 8005656: 4630 mov r0, r6 8005658: 4b09 ldr r3, [pc, #36] ; (8005680 <_vfiprintf_r+0x25c>) 800565a: a904 add r1, sp, #16 800565c: f7fe f85e bl 800371c <_printf_i> 8005660: e7e4 b.n 800562c <_vfiprintf_r+0x208> 8005662: bf00 nop 8005664: 08006614 .word 0x08006614 8005668: 08006634 .word 0x08006634 800566c: 080065f4 .word 0x080065f4 8005670: 0800649c .word 0x0800649c 8005674: 080064a2 .word 0x080064a2 8005678: 080064a6 .word 0x080064a6 800567c: 080031e5 .word 0x080031e5 8005680: 08005401 .word 0x08005401 08005684 <__swbuf_r>: 8005684: b5f8 push {r3, r4, r5, r6, r7, lr} 8005686: 460e mov r6, r1 8005688: 4614 mov r4, r2 800568a: 4605 mov r5, r0 800568c: b118 cbz r0, 8005696 <__swbuf_r+0x12> 800568e: 6983 ldr r3, [r0, #24] 8005690: b90b cbnz r3, 8005696 <__swbuf_r+0x12> 8005692: f000 f9e3 bl 8005a5c <__sinit> 8005696: 4b21 ldr r3, [pc, #132] ; (800571c <__swbuf_r+0x98>) 8005698: 429c cmp r4, r3 800569a: d12b bne.n 80056f4 <__swbuf_r+0x70> 800569c: 686c ldr r4, [r5, #4] 800569e: 69a3 ldr r3, [r4, #24] 80056a0: 60a3 str r3, [r4, #8] 80056a2: 89a3 ldrh r3, [r4, #12] 80056a4: 071a lsls r2, r3, #28 80056a6: d52f bpl.n 8005708 <__swbuf_r+0x84> 80056a8: 6923 ldr r3, [r4, #16] 80056aa: b36b cbz r3, 8005708 <__swbuf_r+0x84> 80056ac: 6923 ldr r3, [r4, #16] 80056ae: 6820 ldr r0, [r4, #0] 80056b0: b2f6 uxtb r6, r6 80056b2: 1ac0 subs r0, r0, r3 80056b4: 6963 ldr r3, [r4, #20] 80056b6: 4637 mov r7, r6 80056b8: 4283 cmp r3, r0 80056ba: dc04 bgt.n 80056c6 <__swbuf_r+0x42> 80056bc: 4621 mov r1, r4 80056be: 4628 mov r0, r5 80056c0: f000 f938 bl 8005934 <_fflush_r> 80056c4: bb30 cbnz r0, 8005714 <__swbuf_r+0x90> 80056c6: 68a3 ldr r3, [r4, #8] 80056c8: 3001 adds r0, #1 80056ca: 3b01 subs r3, #1 80056cc: 60a3 str r3, [r4, #8] 80056ce: 6823 ldr r3, [r4, #0] 80056d0: 1c5a adds r2, r3, #1 80056d2: 6022 str r2, [r4, #0] 80056d4: 701e strb r6, [r3, #0] 80056d6: 6963 ldr r3, [r4, #20] 80056d8: 4283 cmp r3, r0 80056da: d004 beq.n 80056e6 <__swbuf_r+0x62> 80056dc: 89a3 ldrh r3, [r4, #12] 80056de: 07db lsls r3, r3, #31 80056e0: d506 bpl.n 80056f0 <__swbuf_r+0x6c> 80056e2: 2e0a cmp r6, #10 80056e4: d104 bne.n 80056f0 <__swbuf_r+0x6c> 80056e6: 4621 mov r1, r4 80056e8: 4628 mov r0, r5 80056ea: f000 f923 bl 8005934 <_fflush_r> 80056ee: b988 cbnz r0, 8005714 <__swbuf_r+0x90> 80056f0: 4638 mov r0, r7 80056f2: bdf8 pop {r3, r4, r5, r6, r7, pc} 80056f4: 4b0a ldr r3, [pc, #40] ; (8005720 <__swbuf_r+0x9c>) 80056f6: 429c cmp r4, r3 80056f8: d101 bne.n 80056fe <__swbuf_r+0x7a> 80056fa: 68ac ldr r4, [r5, #8] 80056fc: e7cf b.n 800569e <__swbuf_r+0x1a> 80056fe: 4b09 ldr r3, [pc, #36] ; (8005724 <__swbuf_r+0xa0>) 8005700: 429c cmp r4, r3 8005702: bf08 it eq 8005704: 68ec ldreq r4, [r5, #12] 8005706: e7ca b.n 800569e <__swbuf_r+0x1a> 8005708: 4621 mov r1, r4 800570a: 4628 mov r0, r5 800570c: f000 f81a bl 8005744 <__swsetup_r> 8005710: 2800 cmp r0, #0 8005712: d0cb beq.n 80056ac <__swbuf_r+0x28> 8005714: f04f 37ff mov.w r7, #4294967295 8005718: e7ea b.n 80056f0 <__swbuf_r+0x6c> 800571a: bf00 nop 800571c: 08006614 .word 0x08006614 8005720: 08006634 .word 0x08006634 8005724: 080065f4 .word 0x080065f4 08005728 <__ascii_wctomb>: 8005728: 4603 mov r3, r0 800572a: 4608 mov r0, r1 800572c: b141 cbz r1, 8005740 <__ascii_wctomb+0x18> 800572e: 2aff cmp r2, #255 ; 0xff 8005730: d904 bls.n 800573c <__ascii_wctomb+0x14> 8005732: 228a movs r2, #138 ; 0x8a 8005734: f04f 30ff mov.w r0, #4294967295 8005738: 601a str r2, [r3, #0] 800573a: 4770 bx lr 800573c: 2001 movs r0, #1 800573e: 700a strb r2, [r1, #0] 8005740: 4770 bx lr ... 08005744 <__swsetup_r>: 8005744: 4b32 ldr r3, [pc, #200] ; (8005810 <__swsetup_r+0xcc>) 8005746: b570 push {r4, r5, r6, lr} 8005748: 681d ldr r5, [r3, #0] 800574a: 4606 mov r6, r0 800574c: 460c mov r4, r1 800574e: b125 cbz r5, 800575a <__swsetup_r+0x16> 8005750: 69ab ldr r3, [r5, #24] 8005752: b913 cbnz r3, 800575a <__swsetup_r+0x16> 8005754: 4628 mov r0, r5 8005756: f000 f981 bl 8005a5c <__sinit> 800575a: 4b2e ldr r3, [pc, #184] ; (8005814 <__swsetup_r+0xd0>) 800575c: 429c cmp r4, r3 800575e: d10f bne.n 8005780 <__swsetup_r+0x3c> 8005760: 686c ldr r4, [r5, #4] 8005762: 89a3 ldrh r3, [r4, #12] 8005764: f9b4 200c ldrsh.w r2, [r4, #12] 8005768: 0719 lsls r1, r3, #28 800576a: d42c bmi.n 80057c6 <__swsetup_r+0x82> 800576c: 06dd lsls r5, r3, #27 800576e: d411 bmi.n 8005794 <__swsetup_r+0x50> 8005770: 2309 movs r3, #9 8005772: 6033 str r3, [r6, #0] 8005774: f042 0340 orr.w r3, r2, #64 ; 0x40 8005778: f04f 30ff mov.w r0, #4294967295 800577c: 81a3 strh r3, [r4, #12] 800577e: e03e b.n 80057fe <__swsetup_r+0xba> 8005780: 4b25 ldr r3, [pc, #148] ; (8005818 <__swsetup_r+0xd4>) 8005782: 429c cmp r4, r3 8005784: d101 bne.n 800578a <__swsetup_r+0x46> 8005786: 68ac ldr r4, [r5, #8] 8005788: e7eb b.n 8005762 <__swsetup_r+0x1e> 800578a: 4b24 ldr r3, [pc, #144] ; (800581c <__swsetup_r+0xd8>) 800578c: 429c cmp r4, r3 800578e: bf08 it eq 8005790: 68ec ldreq r4, [r5, #12] 8005792: e7e6 b.n 8005762 <__swsetup_r+0x1e> 8005794: 0758 lsls r0, r3, #29 8005796: d512 bpl.n 80057be <__swsetup_r+0x7a> 8005798: 6b61 ldr r1, [r4, #52] ; 0x34 800579a: b141 cbz r1, 80057ae <__swsetup_r+0x6a> 800579c: f104 0344 add.w r3, r4, #68 ; 0x44 80057a0: 4299 cmp r1, r3 80057a2: d002 beq.n 80057aa <__swsetup_r+0x66> 80057a4: 4630 mov r0, r6 80057a6: f7ff fb37 bl 8004e18 <_free_r> 80057aa: 2300 movs r3, #0 80057ac: 6363 str r3, [r4, #52] ; 0x34 80057ae: 89a3 ldrh r3, [r4, #12] 80057b0: f023 0324 bic.w r3, r3, #36 ; 0x24 80057b4: 81a3 strh r3, [r4, #12] 80057b6: 2300 movs r3, #0 80057b8: 6063 str r3, [r4, #4] 80057ba: 6923 ldr r3, [r4, #16] 80057bc: 6023 str r3, [r4, #0] 80057be: 89a3 ldrh r3, [r4, #12] 80057c0: f043 0308 orr.w r3, r3, #8 80057c4: 81a3 strh r3, [r4, #12] 80057c6: 6923 ldr r3, [r4, #16] 80057c8: b94b cbnz r3, 80057de <__swsetup_r+0x9a> 80057ca: 89a3 ldrh r3, [r4, #12] 80057cc: f403 7320 and.w r3, r3, #640 ; 0x280 80057d0: f5b3 7f00 cmp.w r3, #512 ; 0x200 80057d4: d003 beq.n 80057de <__swsetup_r+0x9a> 80057d6: 4621 mov r1, r4 80057d8: 4630 mov r0, r6 80057da: f000 fa05 bl 8005be8 <__smakebuf_r> 80057de: 89a0 ldrh r0, [r4, #12] 80057e0: f9b4 200c ldrsh.w r2, [r4, #12] 80057e4: f010 0301 ands.w r3, r0, #1 80057e8: d00a beq.n 8005800 <__swsetup_r+0xbc> 80057ea: 2300 movs r3, #0 80057ec: 60a3 str r3, [r4, #8] 80057ee: 6963 ldr r3, [r4, #20] 80057f0: 425b negs r3, r3 80057f2: 61a3 str r3, [r4, #24] 80057f4: 6923 ldr r3, [r4, #16] 80057f6: b943 cbnz r3, 800580a <__swsetup_r+0xc6> 80057f8: f010 0080 ands.w r0, r0, #128 ; 0x80 80057fc: d1ba bne.n 8005774 <__swsetup_r+0x30> 80057fe: bd70 pop {r4, r5, r6, pc} 8005800: 0781 lsls r1, r0, #30 8005802: bf58 it pl 8005804: 6963 ldrpl r3, [r4, #20] 8005806: 60a3 str r3, [r4, #8] 8005808: e7f4 b.n 80057f4 <__swsetup_r+0xb0> 800580a: 2000 movs r0, #0 800580c: e7f7 b.n 80057fe <__swsetup_r+0xba> 800580e: bf00 nop 8005810: 2000000c .word 0x2000000c 8005814: 08006614 .word 0x08006614 8005818: 08006634 .word 0x08006634 800581c: 080065f4 .word 0x080065f4 08005820 : 8005820: 2006 movs r0, #6 8005822: b508 push {r3, lr} 8005824: f000 fa50 bl 8005cc8 8005828: 2001 movs r0, #1 800582a: f7fb fe25 bl 8001478 <_exit> ... 08005830 <__sflush_r>: 8005830: 898a ldrh r2, [r1, #12] 8005832: b5f8 push {r3, r4, r5, r6, r7, lr} 8005834: 4605 mov r5, r0 8005836: 0710 lsls r0, r2, #28 8005838: 460c mov r4, r1 800583a: d457 bmi.n 80058ec <__sflush_r+0xbc> 800583c: 684b ldr r3, [r1, #4] 800583e: 2b00 cmp r3, #0 8005840: dc04 bgt.n 800584c <__sflush_r+0x1c> 8005842: 6c0b ldr r3, [r1, #64] ; 0x40 8005844: 2b00 cmp r3, #0 8005846: dc01 bgt.n 800584c <__sflush_r+0x1c> 8005848: 2000 movs r0, #0 800584a: bdf8 pop {r3, r4, r5, r6, r7, pc} 800584c: 6ae6 ldr r6, [r4, #44] ; 0x2c 800584e: 2e00 cmp r6, #0 8005850: d0fa beq.n 8005848 <__sflush_r+0x18> 8005852: 2300 movs r3, #0 8005854: f412 5280 ands.w r2, r2, #4096 ; 0x1000 8005858: 682f ldr r7, [r5, #0] 800585a: 602b str r3, [r5, #0] 800585c: d032 beq.n 80058c4 <__sflush_r+0x94> 800585e: 6d60 ldr r0, [r4, #84] ; 0x54 8005860: 89a3 ldrh r3, [r4, #12] 8005862: 075a lsls r2, r3, #29 8005864: d505 bpl.n 8005872 <__sflush_r+0x42> 8005866: 6863 ldr r3, [r4, #4] 8005868: 1ac0 subs r0, r0, r3 800586a: 6b63 ldr r3, [r4, #52] ; 0x34 800586c: b10b cbz r3, 8005872 <__sflush_r+0x42> 800586e: 6c23 ldr r3, [r4, #64] ; 0x40 8005870: 1ac0 subs r0, r0, r3 8005872: 2300 movs r3, #0 8005874: 4602 mov r2, r0 8005876: 6ae6 ldr r6, [r4, #44] ; 0x2c 8005878: 4628 mov r0, r5 800587a: 6a21 ldr r1, [r4, #32] 800587c: 47b0 blx r6 800587e: 1c43 adds r3, r0, #1 8005880: 89a3 ldrh r3, [r4, #12] 8005882: d106 bne.n 8005892 <__sflush_r+0x62> 8005884: 6829 ldr r1, [r5, #0] 8005886: 291d cmp r1, #29 8005888: d82c bhi.n 80058e4 <__sflush_r+0xb4> 800588a: 4a29 ldr r2, [pc, #164] ; (8005930 <__sflush_r+0x100>) 800588c: 40ca lsrs r2, r1 800588e: 07d6 lsls r6, r2, #31 8005890: d528 bpl.n 80058e4 <__sflush_r+0xb4> 8005892: 2200 movs r2, #0 8005894: 6062 str r2, [r4, #4] 8005896: 6922 ldr r2, [r4, #16] 8005898: 04d9 lsls r1, r3, #19 800589a: 6022 str r2, [r4, #0] 800589c: d504 bpl.n 80058a8 <__sflush_r+0x78> 800589e: 1c42 adds r2, r0, #1 80058a0: d101 bne.n 80058a6 <__sflush_r+0x76> 80058a2: 682b ldr r3, [r5, #0] 80058a4: b903 cbnz r3, 80058a8 <__sflush_r+0x78> 80058a6: 6560 str r0, [r4, #84] ; 0x54 80058a8: 6b61 ldr r1, [r4, #52] ; 0x34 80058aa: 602f str r7, [r5, #0] 80058ac: 2900 cmp r1, #0 80058ae: d0cb beq.n 8005848 <__sflush_r+0x18> 80058b0: f104 0344 add.w r3, r4, #68 ; 0x44 80058b4: 4299 cmp r1, r3 80058b6: d002 beq.n 80058be <__sflush_r+0x8e> 80058b8: 4628 mov r0, r5 80058ba: f7ff faad bl 8004e18 <_free_r> 80058be: 2000 movs r0, #0 80058c0: 6360 str r0, [r4, #52] ; 0x34 80058c2: e7c2 b.n 800584a <__sflush_r+0x1a> 80058c4: 6a21 ldr r1, [r4, #32] 80058c6: 2301 movs r3, #1 80058c8: 4628 mov r0, r5 80058ca: 47b0 blx r6 80058cc: 1c41 adds r1, r0, #1 80058ce: d1c7 bne.n 8005860 <__sflush_r+0x30> 80058d0: 682b ldr r3, [r5, #0] 80058d2: 2b00 cmp r3, #0 80058d4: d0c4 beq.n 8005860 <__sflush_r+0x30> 80058d6: 2b1d cmp r3, #29 80058d8: d001 beq.n 80058de <__sflush_r+0xae> 80058da: 2b16 cmp r3, #22 80058dc: d101 bne.n 80058e2 <__sflush_r+0xb2> 80058de: 602f str r7, [r5, #0] 80058e0: e7b2 b.n 8005848 <__sflush_r+0x18> 80058e2: 89a3 ldrh r3, [r4, #12] 80058e4: f043 0340 orr.w r3, r3, #64 ; 0x40 80058e8: 81a3 strh r3, [r4, #12] 80058ea: e7ae b.n 800584a <__sflush_r+0x1a> 80058ec: 690f ldr r7, [r1, #16] 80058ee: 2f00 cmp r7, #0 80058f0: d0aa beq.n 8005848 <__sflush_r+0x18> 80058f2: 0793 lsls r3, r2, #30 80058f4: bf18 it ne 80058f6: 2300 movne r3, #0 80058f8: 680e ldr r6, [r1, #0] 80058fa: bf08 it eq 80058fc: 694b ldreq r3, [r1, #20] 80058fe: 1bf6 subs r6, r6, r7 8005900: 600f str r7, [r1, #0] 8005902: 608b str r3, [r1, #8] 8005904: 2e00 cmp r6, #0 8005906: dd9f ble.n 8005848 <__sflush_r+0x18> 8005908: 4633 mov r3, r6 800590a: 463a mov r2, r7 800590c: 4628 mov r0, r5 800590e: 6a21 ldr r1, [r4, #32] 8005910: f8d4 c028 ldr.w ip, [r4, #40] ; 0x28 8005914: 47e0 blx ip 8005916: 2800 cmp r0, #0 8005918: dc06 bgt.n 8005928 <__sflush_r+0xf8> 800591a: 89a3 ldrh r3, [r4, #12] 800591c: f04f 30ff mov.w r0, #4294967295 8005920: f043 0340 orr.w r3, r3, #64 ; 0x40 8005924: 81a3 strh r3, [r4, #12] 8005926: e790 b.n 800584a <__sflush_r+0x1a> 8005928: 4407 add r7, r0 800592a: 1a36 subs r6, r6, r0 800592c: e7ea b.n 8005904 <__sflush_r+0xd4> 800592e: bf00 nop 8005930: 20400001 .word 0x20400001 08005934 <_fflush_r>: 8005934: b538 push {r3, r4, r5, lr} 8005936: 690b ldr r3, [r1, #16] 8005938: 4605 mov r5, r0 800593a: 460c mov r4, r1 800593c: b913 cbnz r3, 8005944 <_fflush_r+0x10> 800593e: 2500 movs r5, #0 8005940: 4628 mov r0, r5 8005942: bd38 pop {r3, r4, r5, pc} 8005944: b118 cbz r0, 800594e <_fflush_r+0x1a> 8005946: 6983 ldr r3, [r0, #24] 8005948: b90b cbnz r3, 800594e <_fflush_r+0x1a> 800594a: f000 f887 bl 8005a5c <__sinit> 800594e: 4b14 ldr r3, [pc, #80] ; (80059a0 <_fflush_r+0x6c>) 8005950: 429c cmp r4, r3 8005952: d11b bne.n 800598c <_fflush_r+0x58> 8005954: 686c ldr r4, [r5, #4] 8005956: f9b4 300c ldrsh.w r3, [r4, #12] 800595a: 2b00 cmp r3, #0 800595c: d0ef beq.n 800593e <_fflush_r+0xa> 800595e: 6e62 ldr r2, [r4, #100] ; 0x64 8005960: 07d0 lsls r0, r2, #31 8005962: d404 bmi.n 800596e <_fflush_r+0x3a> 8005964: 0599 lsls r1, r3, #22 8005966: d402 bmi.n 800596e <_fflush_r+0x3a> 8005968: 6da0 ldr r0, [r4, #88] ; 0x58 800596a: f000 f915 bl 8005b98 <__retarget_lock_acquire_recursive> 800596e: 4628 mov r0, r5 8005970: 4621 mov r1, r4 8005972: f7ff ff5d bl 8005830 <__sflush_r> 8005976: 6e63 ldr r3, [r4, #100] ; 0x64 8005978: 4605 mov r5, r0 800597a: 07da lsls r2, r3, #31 800597c: d4e0 bmi.n 8005940 <_fflush_r+0xc> 800597e: 89a3 ldrh r3, [r4, #12] 8005980: 059b lsls r3, r3, #22 8005982: d4dd bmi.n 8005940 <_fflush_r+0xc> 8005984: 6da0 ldr r0, [r4, #88] ; 0x58 8005986: f000 f908 bl 8005b9a <__retarget_lock_release_recursive> 800598a: e7d9 b.n 8005940 <_fflush_r+0xc> 800598c: 4b05 ldr r3, [pc, #20] ; (80059a4 <_fflush_r+0x70>) 800598e: 429c cmp r4, r3 8005990: d101 bne.n 8005996 <_fflush_r+0x62> 8005992: 68ac ldr r4, [r5, #8] 8005994: e7df b.n 8005956 <_fflush_r+0x22> 8005996: 4b04 ldr r3, [pc, #16] ; (80059a8 <_fflush_r+0x74>) 8005998: 429c cmp r4, r3 800599a: bf08 it eq 800599c: 68ec ldreq r4, [r5, #12] 800599e: e7da b.n 8005956 <_fflush_r+0x22> 80059a0: 08006614 .word 0x08006614 80059a4: 08006634 .word 0x08006634 80059a8: 080065f4 .word 0x080065f4 080059ac : 80059ac: 2300 movs r3, #0 80059ae: b510 push {r4, lr} 80059b0: 4604 mov r4, r0 80059b2: e9c0 3300 strd r3, r3, [r0] 80059b6: e9c0 3304 strd r3, r3, [r0, #16] 80059ba: 6083 str r3, [r0, #8] 80059bc: 8181 strh r1, [r0, #12] 80059be: 6643 str r3, [r0, #100] ; 0x64 80059c0: 81c2 strh r2, [r0, #14] 80059c2: 6183 str r3, [r0, #24] 80059c4: 4619 mov r1, r3 80059c6: 2208 movs r2, #8 80059c8: 305c adds r0, #92 ; 0x5c 80059ca: f7fd fb65 bl 8003098 80059ce: 4b05 ldr r3, [pc, #20] ; (80059e4 ) 80059d0: 6224 str r4, [r4, #32] 80059d2: 6263 str r3, [r4, #36] ; 0x24 80059d4: 4b04 ldr r3, [pc, #16] ; (80059e8 ) 80059d6: 62a3 str r3, [r4, #40] ; 0x28 80059d8: 4b04 ldr r3, [pc, #16] ; (80059ec ) 80059da: 62e3 str r3, [r4, #44] ; 0x2c 80059dc: 4b04 ldr r3, [pc, #16] ; (80059f0 ) 80059de: 6323 str r3, [r4, #48] ; 0x30 80059e0: bd10 pop {r4, pc} 80059e2: bf00 nop 80059e4: 08005d01 .word 0x08005d01 80059e8: 08005d23 .word 0x08005d23 80059ec: 08005d5b .word 0x08005d5b 80059f0: 08005d7f .word 0x08005d7f 080059f4 <_cleanup_r>: 80059f4: 4901 ldr r1, [pc, #4] ; (80059fc <_cleanup_r+0x8>) 80059f6: f000 b8af b.w 8005b58 <_fwalk_reent> 80059fa: bf00 nop 80059fc: 08005935 .word 0x08005935 08005a00 <__sfmoreglue>: 8005a00: 2268 movs r2, #104 ; 0x68 8005a02: b570 push {r4, r5, r6, lr} 8005a04: 1e4d subs r5, r1, #1 8005a06: 4355 muls r5, r2 8005a08: 460e mov r6, r1 8005a0a: f105 0174 add.w r1, r5, #116 ; 0x74 8005a0e: f7ff fa6b bl 8004ee8 <_malloc_r> 8005a12: 4604 mov r4, r0 8005a14: b140 cbz r0, 8005a28 <__sfmoreglue+0x28> 8005a16: 2100 movs r1, #0 8005a18: e9c0 1600 strd r1, r6, [r0] 8005a1c: 300c adds r0, #12 8005a1e: 60a0 str r0, [r4, #8] 8005a20: f105 0268 add.w r2, r5, #104 ; 0x68 8005a24: f7fd fb38 bl 8003098 8005a28: 4620 mov r0, r4 8005a2a: bd70 pop {r4, r5, r6, pc} 08005a2c <__sfp_lock_acquire>: 8005a2c: 4801 ldr r0, [pc, #4] ; (8005a34 <__sfp_lock_acquire+0x8>) 8005a2e: f000 b8b3 b.w 8005b98 <__retarget_lock_acquire_recursive> 8005a32: bf00 nop 8005a34: 20000281 .word 0x20000281 08005a38 <__sfp_lock_release>: 8005a38: 4801 ldr r0, [pc, #4] ; (8005a40 <__sfp_lock_release+0x8>) 8005a3a: f000 b8ae b.w 8005b9a <__retarget_lock_release_recursive> 8005a3e: bf00 nop 8005a40: 20000281 .word 0x20000281 08005a44 <__sinit_lock_acquire>: 8005a44: 4801 ldr r0, [pc, #4] ; (8005a4c <__sinit_lock_acquire+0x8>) 8005a46: f000 b8a7 b.w 8005b98 <__retarget_lock_acquire_recursive> 8005a4a: bf00 nop 8005a4c: 20000282 .word 0x20000282 08005a50 <__sinit_lock_release>: 8005a50: 4801 ldr r0, [pc, #4] ; (8005a58 <__sinit_lock_release+0x8>) 8005a52: f000 b8a2 b.w 8005b9a <__retarget_lock_release_recursive> 8005a56: bf00 nop 8005a58: 20000282 .word 0x20000282 08005a5c <__sinit>: 8005a5c: b510 push {r4, lr} 8005a5e: 4604 mov r4, r0 8005a60: f7ff fff0 bl 8005a44 <__sinit_lock_acquire> 8005a64: 69a3 ldr r3, [r4, #24] 8005a66: b11b cbz r3, 8005a70 <__sinit+0x14> 8005a68: e8bd 4010 ldmia.w sp!, {r4, lr} 8005a6c: f7ff bff0 b.w 8005a50 <__sinit_lock_release> 8005a70: e9c4 3312 strd r3, r3, [r4, #72] ; 0x48 8005a74: 6523 str r3, [r4, #80] ; 0x50 8005a76: 4b13 ldr r3, [pc, #76] ; (8005ac4 <__sinit+0x68>) 8005a78: 4a13 ldr r2, [pc, #76] ; (8005ac8 <__sinit+0x6c>) 8005a7a: 681b ldr r3, [r3, #0] 8005a7c: 62a2 str r2, [r4, #40] ; 0x28 8005a7e: 42a3 cmp r3, r4 8005a80: bf08 it eq 8005a82: 2301 moveq r3, #1 8005a84: 4620 mov r0, r4 8005a86: bf08 it eq 8005a88: 61a3 streq r3, [r4, #24] 8005a8a: f000 f81f bl 8005acc <__sfp> 8005a8e: 6060 str r0, [r4, #4] 8005a90: 4620 mov r0, r4 8005a92: f000 f81b bl 8005acc <__sfp> 8005a96: 60a0 str r0, [r4, #8] 8005a98: 4620 mov r0, r4 8005a9a: f000 f817 bl 8005acc <__sfp> 8005a9e: 2200 movs r2, #0 8005aa0: 2104 movs r1, #4 8005aa2: 60e0 str r0, [r4, #12] 8005aa4: 6860 ldr r0, [r4, #4] 8005aa6: f7ff ff81 bl 80059ac 8005aaa: 2201 movs r2, #1 8005aac: 2109 movs r1, #9 8005aae: 68a0 ldr r0, [r4, #8] 8005ab0: f7ff ff7c bl 80059ac 8005ab4: 2202 movs r2, #2 8005ab6: 2112 movs r1, #18 8005ab8: 68e0 ldr r0, [r4, #12] 8005aba: f7ff ff77 bl 80059ac 8005abe: 2301 movs r3, #1 8005ac0: 61a3 str r3, [r4, #24] 8005ac2: e7d1 b.n 8005a68 <__sinit+0xc> 8005ac4: 08006278 .word 0x08006278 8005ac8: 080059f5 .word 0x080059f5 08005acc <__sfp>: 8005acc: b5f8 push {r3, r4, r5, r6, r7, lr} 8005ace: 4607 mov r7, r0 8005ad0: f7ff ffac bl 8005a2c <__sfp_lock_acquire> 8005ad4: 4b1e ldr r3, [pc, #120] ; (8005b50 <__sfp+0x84>) 8005ad6: 681e ldr r6, [r3, #0] 8005ad8: 69b3 ldr r3, [r6, #24] 8005ada: b913 cbnz r3, 8005ae2 <__sfp+0x16> 8005adc: 4630 mov r0, r6 8005ade: f7ff ffbd bl 8005a5c <__sinit> 8005ae2: 3648 adds r6, #72 ; 0x48 8005ae4: e9d6 3401 ldrd r3, r4, [r6, #4] 8005ae8: 3b01 subs r3, #1 8005aea: d503 bpl.n 8005af4 <__sfp+0x28> 8005aec: 6833 ldr r3, [r6, #0] 8005aee: b30b cbz r3, 8005b34 <__sfp+0x68> 8005af0: 6836 ldr r6, [r6, #0] 8005af2: e7f7 b.n 8005ae4 <__sfp+0x18> 8005af4: f9b4 500c ldrsh.w r5, [r4, #12] 8005af8: b9d5 cbnz r5, 8005b30 <__sfp+0x64> 8005afa: 4b16 ldr r3, [pc, #88] ; (8005b54 <__sfp+0x88>) 8005afc: f104 0058 add.w r0, r4, #88 ; 0x58 8005b00: 60e3 str r3, [r4, #12] 8005b02: 6665 str r5, [r4, #100] ; 0x64 8005b04: f000 f847 bl 8005b96 <__retarget_lock_init_recursive> 8005b08: f7ff ff96 bl 8005a38 <__sfp_lock_release> 8005b0c: 2208 movs r2, #8 8005b0e: 4629 mov r1, r5 8005b10: e9c4 5501 strd r5, r5, [r4, #4] 8005b14: e9c4 5504 strd r5, r5, [r4, #16] 8005b18: 6025 str r5, [r4, #0] 8005b1a: 61a5 str r5, [r4, #24] 8005b1c: f104 005c add.w r0, r4, #92 ; 0x5c 8005b20: f7fd faba bl 8003098 8005b24: e9c4 550d strd r5, r5, [r4, #52] ; 0x34 8005b28: e9c4 5512 strd r5, r5, [r4, #72] ; 0x48 8005b2c: 4620 mov r0, r4 8005b2e: bdf8 pop {r3, r4, r5, r6, r7, pc} 8005b30: 3468 adds r4, #104 ; 0x68 8005b32: e7d9 b.n 8005ae8 <__sfp+0x1c> 8005b34: 2104 movs r1, #4 8005b36: 4638 mov r0, r7 8005b38: f7ff ff62 bl 8005a00 <__sfmoreglue> 8005b3c: 4604 mov r4, r0 8005b3e: 6030 str r0, [r6, #0] 8005b40: 2800 cmp r0, #0 8005b42: d1d5 bne.n 8005af0 <__sfp+0x24> 8005b44: f7ff ff78 bl 8005a38 <__sfp_lock_release> 8005b48: 230c movs r3, #12 8005b4a: 603b str r3, [r7, #0] 8005b4c: e7ee b.n 8005b2c <__sfp+0x60> 8005b4e: bf00 nop 8005b50: 08006278 .word 0x08006278 8005b54: ffff0001 .word 0xffff0001 08005b58 <_fwalk_reent>: 8005b58: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} 8005b5c: 4606 mov r6, r0 8005b5e: 4688 mov r8, r1 8005b60: 2700 movs r7, #0 8005b62: f100 0448 add.w r4, r0, #72 ; 0x48 8005b66: e9d4 9501 ldrd r9, r5, [r4, #4] 8005b6a: f1b9 0901 subs.w r9, r9, #1 8005b6e: d505 bpl.n 8005b7c <_fwalk_reent+0x24> 8005b70: 6824 ldr r4, [r4, #0] 8005b72: 2c00 cmp r4, #0 8005b74: d1f7 bne.n 8005b66 <_fwalk_reent+0xe> 8005b76: 4638 mov r0, r7 8005b78: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} 8005b7c: 89ab ldrh r3, [r5, #12] 8005b7e: 2b01 cmp r3, #1 8005b80: d907 bls.n 8005b92 <_fwalk_reent+0x3a> 8005b82: f9b5 300e ldrsh.w r3, [r5, #14] 8005b86: 3301 adds r3, #1 8005b88: d003 beq.n 8005b92 <_fwalk_reent+0x3a> 8005b8a: 4629 mov r1, r5 8005b8c: 4630 mov r0, r6 8005b8e: 47c0 blx r8 8005b90: 4307 orrs r7, r0 8005b92: 3568 adds r5, #104 ; 0x68 8005b94: e7e9 b.n 8005b6a <_fwalk_reent+0x12> 08005b96 <__retarget_lock_init_recursive>: 8005b96: 4770 bx lr 08005b98 <__retarget_lock_acquire_recursive>: 8005b98: 4770 bx lr 08005b9a <__retarget_lock_release_recursive>: 8005b9a: 4770 bx lr 08005b9c <__swhatbuf_r>: 8005b9c: b570 push {r4, r5, r6, lr} 8005b9e: 460e mov r6, r1 8005ba0: f9b1 100e ldrsh.w r1, [r1, #14] 8005ba4: 4614 mov r4, r2 8005ba6: 2900 cmp r1, #0 8005ba8: 461d mov r5, r3 8005baa: b096 sub sp, #88 ; 0x58 8005bac: da08 bge.n 8005bc0 <__swhatbuf_r+0x24> 8005bae: 2200 movs r2, #0 8005bb0: f9b6 300c ldrsh.w r3, [r6, #12] 8005bb4: 602a str r2, [r5, #0] 8005bb6: 061a lsls r2, r3, #24 8005bb8: d410 bmi.n 8005bdc <__swhatbuf_r+0x40> 8005bba: f44f 6380 mov.w r3, #1024 ; 0x400 8005bbe: e00e b.n 8005bde <__swhatbuf_r+0x42> 8005bc0: 466a mov r2, sp 8005bc2: f000 f903 bl 8005dcc <_fstat_r> 8005bc6: 2800 cmp r0, #0 8005bc8: dbf1 blt.n 8005bae <__swhatbuf_r+0x12> 8005bca: 9a01 ldr r2, [sp, #4] 8005bcc: f402 4270 and.w r2, r2, #61440 ; 0xf000 8005bd0: f5a2 5300 sub.w r3, r2, #8192 ; 0x2000 8005bd4: 425a negs r2, r3 8005bd6: 415a adcs r2, r3 8005bd8: 602a str r2, [r5, #0] 8005bda: e7ee b.n 8005bba <__swhatbuf_r+0x1e> 8005bdc: 2340 movs r3, #64 ; 0x40 8005bde: 2000 movs r0, #0 8005be0: 6023 str r3, [r4, #0] 8005be2: b016 add sp, #88 ; 0x58 8005be4: bd70 pop {r4, r5, r6, pc} ... 08005be8 <__smakebuf_r>: 8005be8: 898b ldrh r3, [r1, #12] 8005bea: b573 push {r0, r1, r4, r5, r6, lr} 8005bec: 079d lsls r5, r3, #30 8005bee: 4606 mov r6, r0 8005bf0: 460c mov r4, r1 8005bf2: d507 bpl.n 8005c04 <__smakebuf_r+0x1c> 8005bf4: f104 0347 add.w r3, r4, #71 ; 0x47 8005bf8: 6023 str r3, [r4, #0] 8005bfa: 6123 str r3, [r4, #16] 8005bfc: 2301 movs r3, #1 8005bfe: 6163 str r3, [r4, #20] 8005c00: b002 add sp, #8 8005c02: bd70 pop {r4, r5, r6, pc} 8005c04: 466a mov r2, sp 8005c06: ab01 add r3, sp, #4 8005c08: f7ff ffc8 bl 8005b9c <__swhatbuf_r> 8005c0c: 9900 ldr r1, [sp, #0] 8005c0e: 4605 mov r5, r0 8005c10: 4630 mov r0, r6 8005c12: f7ff f969 bl 8004ee8 <_malloc_r> 8005c16: b948 cbnz r0, 8005c2c <__smakebuf_r+0x44> 8005c18: f9b4 300c ldrsh.w r3, [r4, #12] 8005c1c: 059a lsls r2, r3, #22 8005c1e: d4ef bmi.n 8005c00 <__smakebuf_r+0x18> 8005c20: f023 0303 bic.w r3, r3, #3 8005c24: f043 0302 orr.w r3, r3, #2 8005c28: 81a3 strh r3, [r4, #12] 8005c2a: e7e3 b.n 8005bf4 <__smakebuf_r+0xc> 8005c2c: 4b0d ldr r3, [pc, #52] ; (8005c64 <__smakebuf_r+0x7c>) 8005c2e: 62b3 str r3, [r6, #40] ; 0x28 8005c30: 89a3 ldrh r3, [r4, #12] 8005c32: 6020 str r0, [r4, #0] 8005c34: f043 0380 orr.w r3, r3, #128 ; 0x80 8005c38: 81a3 strh r3, [r4, #12] 8005c3a: 9b00 ldr r3, [sp, #0] 8005c3c: 6120 str r0, [r4, #16] 8005c3e: 6163 str r3, [r4, #20] 8005c40: 9b01 ldr r3, [sp, #4] 8005c42: b15b cbz r3, 8005c5c <__smakebuf_r+0x74> 8005c44: 4630 mov r0, r6 8005c46: f9b4 100e ldrsh.w r1, [r4, #14] 8005c4a: f000 f8d1 bl 8005df0 <_isatty_r> 8005c4e: b128 cbz r0, 8005c5c <__smakebuf_r+0x74> 8005c50: 89a3 ldrh r3, [r4, #12] 8005c52: f023 0303 bic.w r3, r3, #3 8005c56: f043 0301 orr.w r3, r3, #1 8005c5a: 81a3 strh r3, [r4, #12] 8005c5c: 89a0 ldrh r0, [r4, #12] 8005c5e: 4305 orrs r5, r0 8005c60: 81a5 strh r5, [r4, #12] 8005c62: e7cd b.n 8005c00 <__smakebuf_r+0x18> 8005c64: 080059f5 .word 0x080059f5 08005c68 <_malloc_usable_size_r>: 8005c68: f851 3c04 ldr.w r3, [r1, #-4] 8005c6c: 1f18 subs r0, r3, #4 8005c6e: 2b00 cmp r3, #0 8005c70: bfbc itt lt 8005c72: 580b ldrlt r3, [r1, r0] 8005c74: 18c0 addlt r0, r0, r3 8005c76: 4770 bx lr 08005c78 <_raise_r>: 8005c78: 291f cmp r1, #31 8005c7a: b538 push {r3, r4, r5, lr} 8005c7c: 4604 mov r4, r0 8005c7e: 460d mov r5, r1 8005c80: d904 bls.n 8005c8c <_raise_r+0x14> 8005c82: 2316 movs r3, #22 8005c84: 6003 str r3, [r0, #0] 8005c86: f04f 30ff mov.w r0, #4294967295 8005c8a: bd38 pop {r3, r4, r5, pc} 8005c8c: 6c42 ldr r2, [r0, #68] ; 0x44 8005c8e: b112 cbz r2, 8005c96 <_raise_r+0x1e> 8005c90: f852 3021 ldr.w r3, [r2, r1, lsl #2] 8005c94: b94b cbnz r3, 8005caa <_raise_r+0x32> 8005c96: 4620 mov r0, r4 8005c98: f000 f830 bl 8005cfc <_getpid_r> 8005c9c: 462a mov r2, r5 8005c9e: 4601 mov r1, r0 8005ca0: 4620 mov r0, r4 8005ca2: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} 8005ca6: f000 b817 b.w 8005cd8 <_kill_r> 8005caa: 2b01 cmp r3, #1 8005cac: d00a beq.n 8005cc4 <_raise_r+0x4c> 8005cae: 1c59 adds r1, r3, #1 8005cb0: d103 bne.n 8005cba <_raise_r+0x42> 8005cb2: 2316 movs r3, #22 8005cb4: 6003 str r3, [r0, #0] 8005cb6: 2001 movs r0, #1 8005cb8: e7e7 b.n 8005c8a <_raise_r+0x12> 8005cba: 2400 movs r4, #0 8005cbc: 4628 mov r0, r5 8005cbe: f842 4025 str.w r4, [r2, r5, lsl #2] 8005cc2: 4798 blx r3 8005cc4: 2000 movs r0, #0 8005cc6: e7e0 b.n 8005c8a <_raise_r+0x12> 08005cc8 : 8005cc8: 4b02 ldr r3, [pc, #8] ; (8005cd4 ) 8005cca: 4601 mov r1, r0 8005ccc: 6818 ldr r0, [r3, #0] 8005cce: f7ff bfd3 b.w 8005c78 <_raise_r> 8005cd2: bf00 nop 8005cd4: 2000000c .word 0x2000000c 08005cd8 <_kill_r>: 8005cd8: b538 push {r3, r4, r5, lr} 8005cda: 2300 movs r3, #0 8005cdc: 4d06 ldr r5, [pc, #24] ; (8005cf8 <_kill_r+0x20>) 8005cde: 4604 mov r4, r0 8005ce0: 4608 mov r0, r1 8005ce2: 4611 mov r1, r2 8005ce4: 602b str r3, [r5, #0] 8005ce6: f7fb fbb7 bl 8001458 <_kill> 8005cea: 1c43 adds r3, r0, #1 8005cec: d102 bne.n 8005cf4 <_kill_r+0x1c> 8005cee: 682b ldr r3, [r5, #0] 8005cf0: b103 cbz r3, 8005cf4 <_kill_r+0x1c> 8005cf2: 6023 str r3, [r4, #0] 8005cf4: bd38 pop {r3, r4, r5, pc} 8005cf6: bf00 nop 8005cf8: 2000027c .word 0x2000027c 08005cfc <_getpid_r>: 8005cfc: f7fb bba5 b.w 800144a <_getpid> 08005d00 <__sread>: 8005d00: b510 push {r4, lr} 8005d02: 460c mov r4, r1 8005d04: f9b1 100e ldrsh.w r1, [r1, #14] 8005d08: f000 f894 bl 8005e34 <_read_r> 8005d0c: 2800 cmp r0, #0 8005d0e: bfab itete ge 8005d10: 6d63 ldrge r3, [r4, #84] ; 0x54 8005d12: 89a3 ldrhlt r3, [r4, #12] 8005d14: 181b addge r3, r3, r0 8005d16: f423 5380 biclt.w r3, r3, #4096 ; 0x1000 8005d1a: bfac ite ge 8005d1c: 6563 strge r3, [r4, #84] ; 0x54 8005d1e: 81a3 strhlt r3, [r4, #12] 8005d20: bd10 pop {r4, pc} 08005d22 <__swrite>: 8005d22: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} 8005d26: 461f mov r7, r3 8005d28: 898b ldrh r3, [r1, #12] 8005d2a: 4605 mov r5, r0 8005d2c: 05db lsls r3, r3, #23 8005d2e: 460c mov r4, r1 8005d30: 4616 mov r6, r2 8005d32: d505 bpl.n 8005d40 <__swrite+0x1e> 8005d34: 2302 movs r3, #2 8005d36: 2200 movs r2, #0 8005d38: f9b1 100e ldrsh.w r1, [r1, #14] 8005d3c: f000 f868 bl 8005e10 <_lseek_r> 8005d40: 89a3 ldrh r3, [r4, #12] 8005d42: 4632 mov r2, r6 8005d44: f423 5380 bic.w r3, r3, #4096 ; 0x1000 8005d48: 81a3 strh r3, [r4, #12] 8005d4a: 4628 mov r0, r5 8005d4c: 463b mov r3, r7 8005d4e: f9b4 100e ldrsh.w r1, [r4, #14] 8005d52: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} 8005d56: f000 b817 b.w 8005d88 <_write_r> 08005d5a <__sseek>: 8005d5a: b510 push {r4, lr} 8005d5c: 460c mov r4, r1 8005d5e: f9b1 100e ldrsh.w r1, [r1, #14] 8005d62: f000 f855 bl 8005e10 <_lseek_r> 8005d66: 1c43 adds r3, r0, #1 8005d68: 89a3 ldrh r3, [r4, #12] 8005d6a: bf15 itete ne 8005d6c: 6560 strne r0, [r4, #84] ; 0x54 8005d6e: f423 5380 biceq.w r3, r3, #4096 ; 0x1000 8005d72: f443 5380 orrne.w r3, r3, #4096 ; 0x1000 8005d76: 81a3 strheq r3, [r4, #12] 8005d78: bf18 it ne 8005d7a: 81a3 strhne r3, [r4, #12] 8005d7c: bd10 pop {r4, pc} 08005d7e <__sclose>: 8005d7e: f9b1 100e ldrsh.w r1, [r1, #14] 8005d82: f000 b813 b.w 8005dac <_close_r> ... 08005d88 <_write_r>: 8005d88: b538 push {r3, r4, r5, lr} 8005d8a: 4604 mov r4, r0 8005d8c: 4608 mov r0, r1 8005d8e: 4611 mov r1, r2 8005d90: 2200 movs r2, #0 8005d92: 4d05 ldr r5, [pc, #20] ; (8005da8 <_write_r+0x20>) 8005d94: 602a str r2, [r5, #0] 8005d96: 461a mov r2, r3 8005d98: f7fb fb95 bl 80014c6 <_write> 8005d9c: 1c43 adds r3, r0, #1 8005d9e: d102 bne.n 8005da6 <_write_r+0x1e> 8005da0: 682b ldr r3, [r5, #0] 8005da2: b103 cbz r3, 8005da6 <_write_r+0x1e> 8005da4: 6023 str r3, [r4, #0] 8005da6: bd38 pop {r3, r4, r5, pc} 8005da8: 2000027c .word 0x2000027c 08005dac <_close_r>: 8005dac: b538 push {r3, r4, r5, lr} 8005dae: 2300 movs r3, #0 8005db0: 4d05 ldr r5, [pc, #20] ; (8005dc8 <_close_r+0x1c>) 8005db2: 4604 mov r4, r0 8005db4: 4608 mov r0, r1 8005db6: 602b str r3, [r5, #0] 8005db8: f7fb fba1 bl 80014fe <_close> 8005dbc: 1c43 adds r3, r0, #1 8005dbe: d102 bne.n 8005dc6 <_close_r+0x1a> 8005dc0: 682b ldr r3, [r5, #0] 8005dc2: b103 cbz r3, 8005dc6 <_close_r+0x1a> 8005dc4: 6023 str r3, [r4, #0] 8005dc6: bd38 pop {r3, r4, r5, pc} 8005dc8: 2000027c .word 0x2000027c 08005dcc <_fstat_r>: 8005dcc: b538 push {r3, r4, r5, lr} 8005dce: 2300 movs r3, #0 8005dd0: 4d06 ldr r5, [pc, #24] ; (8005dec <_fstat_r+0x20>) 8005dd2: 4604 mov r4, r0 8005dd4: 4608 mov r0, r1 8005dd6: 4611 mov r1, r2 8005dd8: 602b str r3, [r5, #0] 8005dda: f7fb fb9b bl 8001514 <_fstat> 8005dde: 1c43 adds r3, r0, #1 8005de0: d102 bne.n 8005de8 <_fstat_r+0x1c> 8005de2: 682b ldr r3, [r5, #0] 8005de4: b103 cbz r3, 8005de8 <_fstat_r+0x1c> 8005de6: 6023 str r3, [r4, #0] 8005de8: bd38 pop {r3, r4, r5, pc} 8005dea: bf00 nop 8005dec: 2000027c .word 0x2000027c 08005df0 <_isatty_r>: 8005df0: b538 push {r3, r4, r5, lr} 8005df2: 2300 movs r3, #0 8005df4: 4d05 ldr r5, [pc, #20] ; (8005e0c <_isatty_r+0x1c>) 8005df6: 4604 mov r4, r0 8005df8: 4608 mov r0, r1 8005dfa: 602b str r3, [r5, #0] 8005dfc: f7fb fb99 bl 8001532 <_isatty> 8005e00: 1c43 adds r3, r0, #1 8005e02: d102 bne.n 8005e0a <_isatty_r+0x1a> 8005e04: 682b ldr r3, [r5, #0] 8005e06: b103 cbz r3, 8005e0a <_isatty_r+0x1a> 8005e08: 6023 str r3, [r4, #0] 8005e0a: bd38 pop {r3, r4, r5, pc} 8005e0c: 2000027c .word 0x2000027c 08005e10 <_lseek_r>: 8005e10: b538 push {r3, r4, r5, lr} 8005e12: 4604 mov r4, r0 8005e14: 4608 mov r0, r1 8005e16: 4611 mov r1, r2 8005e18: 2200 movs r2, #0 8005e1a: 4d05 ldr r5, [pc, #20] ; (8005e30 <_lseek_r+0x20>) 8005e1c: 602a str r2, [r5, #0] 8005e1e: 461a mov r2, r3 8005e20: f7fb fb91 bl 8001546 <_lseek> 8005e24: 1c43 adds r3, r0, #1 8005e26: d102 bne.n 8005e2e <_lseek_r+0x1e> 8005e28: 682b ldr r3, [r5, #0] 8005e2a: b103 cbz r3, 8005e2e <_lseek_r+0x1e> 8005e2c: 6023 str r3, [r4, #0] 8005e2e: bd38 pop {r3, r4, r5, pc} 8005e30: 2000027c .word 0x2000027c 08005e34 <_read_r>: 8005e34: b538 push {r3, r4, r5, lr} 8005e36: 4604 mov r4, r0 8005e38: 4608 mov r0, r1 8005e3a: 4611 mov r1, r2 8005e3c: 2200 movs r2, #0 8005e3e: 4d05 ldr r5, [pc, #20] ; (8005e54 <_read_r+0x20>) 8005e40: 602a str r2, [r5, #0] 8005e42: 461a mov r2, r3 8005e44: f7fb fb22 bl 800148c <_read> 8005e48: 1c43 adds r3, r0, #1 8005e4a: d102 bne.n 8005e52 <_read_r+0x1e> 8005e4c: 682b ldr r3, [r5, #0] 8005e4e: b103 cbz r3, 8005e52 <_read_r+0x1e> 8005e50: 6023 str r3, [r4, #0] 8005e52: bd38 pop {r3, r4, r5, pc} 8005e54: 2000027c .word 0x2000027c 08005e58 : 8005e58: b5f8 push {r3, r4, r5, r6, r7, lr} 8005e5a: 4604 mov r4, r0 8005e5c: 460d mov r5, r1 8005e5e: f000 f82f bl 8005ec0 <__ieee754_log> 8005e62: 4622 mov r2, r4 8005e64: 4606 mov r6, r0 8005e66: 460f mov r7, r1 8005e68: 462b mov r3, r5 8005e6a: 4620 mov r0, r4 8005e6c: 4629 mov r1, r5 8005e6e: f7fa fdcd bl 8000a0c <__aeabi_dcmpun> 8005e72: b998 cbnz r0, 8005e9c 8005e74: 2200 movs r2, #0 8005e76: 2300 movs r3, #0 8005e78: 4620 mov r0, r4 8005e7a: 4629 mov r1, r5 8005e7c: f7fa fdbc bl 80009f8 <__aeabi_dcmpgt> 8005e80: b960 cbnz r0, 8005e9c 8005e82: 2200 movs r2, #0 8005e84: 2300 movs r3, #0 8005e86: 4620 mov r0, r4 8005e88: 4629 mov r1, r5 8005e8a: f7fa fd8d bl 80009a8 <__aeabi_dcmpeq> 8005e8e: b140 cbz r0, 8005ea2 8005e90: f7fd f8d8 bl 8003044 <__errno> 8005e94: 2322 movs r3, #34 ; 0x22 8005e96: 2600 movs r6, #0 8005e98: 4f06 ldr r7, [pc, #24] ; (8005eb4 ) 8005e9a: 6003 str r3, [r0, #0] 8005e9c: 4630 mov r0, r6 8005e9e: 4639 mov r1, r7 8005ea0: bdf8 pop {r3, r4, r5, r6, r7, pc} 8005ea2: f7fd f8cf bl 8003044 <__errno> 8005ea6: 2321 movs r3, #33 ; 0x21 8005ea8: 6003 str r3, [r0, #0] 8005eaa: 4803 ldr r0, [pc, #12] ; (8005eb8 ) 8005eac: e8bd 40f8 ldmia.w sp!, {r3, r4, r5, r6, r7, lr} 8005eb0: f000 b9b8 b.w 8006224 8005eb4: fff00000 .word 0xfff00000 8005eb8: 080064e8 .word 0x080064e8 8005ebc: 00000000 .word 0x00000000 08005ec0 <__ieee754_log>: 8005ec0: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 8005ec4: f5b1 1f80 cmp.w r1, #1048576 ; 0x100000 8005ec8: 4602 mov r2, r0 8005eca: 460b mov r3, r1 8005ecc: 460d mov r5, r1 8005ece: b087 sub sp, #28 8005ed0: da24 bge.n 8005f1c <__ieee754_log+0x5c> 8005ed2: f021 4400 bic.w r4, r1, #2147483648 ; 0x80000000 8005ed6: 4304 orrs r4, r0 8005ed8: d108 bne.n 8005eec <__ieee754_log+0x2c> 8005eda: 2200 movs r2, #0 8005edc: 2300 movs r3, #0 8005ede: 2000 movs r0, #0 8005ee0: 49cb ldr r1, [pc, #812] ; (8006210 <__ieee754_log+0x350>) 8005ee2: f7fa fc23 bl 800072c <__aeabi_ddiv> 8005ee6: b007 add sp, #28 8005ee8: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 8005eec: 2900 cmp r1, #0 8005eee: da04 bge.n 8005efa <__ieee754_log+0x3a> 8005ef0: f7fa f93a bl 8000168 <__aeabi_dsub> 8005ef4: 2200 movs r2, #0 8005ef6: 2300 movs r3, #0 8005ef8: e7f3 b.n 8005ee2 <__ieee754_log+0x22> 8005efa: 2200 movs r2, #0 8005efc: 4bc5 ldr r3, [pc, #788] ; (8006214 <__ieee754_log+0x354>) 8005efe: f7fa faeb bl 80004d8 <__aeabi_dmul> 8005f02: f06f 0635 mvn.w r6, #53 ; 0x35 8005f06: 4602 mov r2, r0 8005f08: 460b mov r3, r1 8005f0a: 460d mov r5, r1 8005f0c: 49c2 ldr r1, [pc, #776] ; (8006218 <__ieee754_log+0x358>) 8005f0e: 428d cmp r5, r1 8005f10: dd06 ble.n 8005f20 <__ieee754_log+0x60> 8005f12: 4610 mov r0, r2 8005f14: 4619 mov r1, r3 8005f16: f7fa f929 bl 800016c <__adddf3> 8005f1a: e7e4 b.n 8005ee6 <__ieee754_log+0x26> 8005f1c: 2600 movs r6, #0 8005f1e: e7f5 b.n 8005f0c <__ieee754_log+0x4c> 8005f20: 152c asrs r4, r5, #20 8005f22: f3c5 0513 ubfx r5, r5, #0, #20 8005f26: f505 2115 add.w r1, r5, #610304 ; 0x95000 8005f2a: f2a4 34ff subw r4, r4, #1023 ; 0x3ff 8005f2e: f601 7164 addw r1, r1, #3940 ; 0xf64 8005f32: 4426 add r6, r4 8005f34: f401 1480 and.w r4, r1, #1048576 ; 0x100000 8005f38: f084 517f eor.w r1, r4, #1069547520 ; 0x3fc00000 8005f3c: f481 1140 eor.w r1, r1, #3145728 ; 0x300000 8005f40: ea41 0305 orr.w r3, r1, r5 8005f44: 4610 mov r0, r2 8005f46: 4619 mov r1, r3 8005f48: 2200 movs r2, #0 8005f4a: 4bb4 ldr r3, [pc, #720] ; (800621c <__ieee754_log+0x35c>) 8005f4c: f7fa f90c bl 8000168 <__aeabi_dsub> 8005f50: 1cab adds r3, r5, #2 8005f52: f3c3 0313 ubfx r3, r3, #0, #20 8005f56: 2b02 cmp r3, #2 8005f58: 4682 mov sl, r0 8005f5a: 468b mov fp, r1 8005f5c: f04f 0200 mov.w r2, #0 8005f60: eb06 5414 add.w r4, r6, r4, lsr #20 8005f64: dc53 bgt.n 800600e <__ieee754_log+0x14e> 8005f66: 2300 movs r3, #0 8005f68: f7fa fd1e bl 80009a8 <__aeabi_dcmpeq> 8005f6c: b1d0 cbz r0, 8005fa4 <__ieee754_log+0xe4> 8005f6e: 2c00 cmp r4, #0 8005f70: f000 8122 beq.w 80061b8 <__ieee754_log+0x2f8> 8005f74: 4620 mov r0, r4 8005f76: f7fa fa45 bl 8000404 <__aeabi_i2d> 8005f7a: a391 add r3, pc, #580 ; (adr r3, 80061c0 <__ieee754_log+0x300>) 8005f7c: e9d3 2300 ldrd r2, r3, [r3] 8005f80: 4606 mov r6, r0 8005f82: 460f mov r7, r1 8005f84: f7fa faa8 bl 80004d8 <__aeabi_dmul> 8005f88: a38f add r3, pc, #572 ; (adr r3, 80061c8 <__ieee754_log+0x308>) 8005f8a: e9d3 2300 ldrd r2, r3, [r3] 8005f8e: 4604 mov r4, r0 8005f90: 460d mov r5, r1 8005f92: 4630 mov r0, r6 8005f94: 4639 mov r1, r7 8005f96: f7fa fa9f bl 80004d8 <__aeabi_dmul> 8005f9a: 4602 mov r2, r0 8005f9c: 460b mov r3, r1 8005f9e: 4620 mov r0, r4 8005fa0: 4629 mov r1, r5 8005fa2: e7b8 b.n 8005f16 <__ieee754_log+0x56> 8005fa4: a38a add r3, pc, #552 ; (adr r3, 80061d0 <__ieee754_log+0x310>) 8005fa6: e9d3 2300 ldrd r2, r3, [r3] 8005faa: 4650 mov r0, sl 8005fac: 4659 mov r1, fp 8005fae: f7fa fa93 bl 80004d8 <__aeabi_dmul> 8005fb2: 4602 mov r2, r0 8005fb4: 460b mov r3, r1 8005fb6: 2000 movs r0, #0 8005fb8: 4999 ldr r1, [pc, #612] ; (8006220 <__ieee754_log+0x360>) 8005fba: f7fa f8d5 bl 8000168 <__aeabi_dsub> 8005fbe: 4652 mov r2, sl 8005fc0: 4606 mov r6, r0 8005fc2: 460f mov r7, r1 8005fc4: 465b mov r3, fp 8005fc6: 4650 mov r0, sl 8005fc8: 4659 mov r1, fp 8005fca: f7fa fa85 bl 80004d8 <__aeabi_dmul> 8005fce: 4602 mov r2, r0 8005fd0: 460b mov r3, r1 8005fd2: 4630 mov r0, r6 8005fd4: 4639 mov r1, r7 8005fd6: f7fa fa7f bl 80004d8 <__aeabi_dmul> 8005fda: 4606 mov r6, r0 8005fdc: 460f mov r7, r1 8005fde: b914 cbnz r4, 8005fe6 <__ieee754_log+0x126> 8005fe0: 4632 mov r2, r6 8005fe2: 463b mov r3, r7 8005fe4: e0a2 b.n 800612c <__ieee754_log+0x26c> 8005fe6: 4620 mov r0, r4 8005fe8: f7fa fa0c bl 8000404 <__aeabi_i2d> 8005fec: a374 add r3, pc, #464 ; (adr r3, 80061c0 <__ieee754_log+0x300>) 8005fee: e9d3 2300 ldrd r2, r3, [r3] 8005ff2: 4680 mov r8, r0 8005ff4: 4689 mov r9, r1 8005ff6: f7fa fa6f bl 80004d8 <__aeabi_dmul> 8005ffa: a373 add r3, pc, #460 ; (adr r3, 80061c8 <__ieee754_log+0x308>) 8005ffc: e9d3 2300 ldrd r2, r3, [r3] 8006000: 4604 mov r4, r0 8006002: 460d mov r5, r1 8006004: 4640 mov r0, r8 8006006: 4649 mov r1, r9 8006008: f7fa fa66 bl 80004d8 <__aeabi_dmul> 800600c: e0a7 b.n 800615e <__ieee754_log+0x29e> 800600e: f04f 4380 mov.w r3, #1073741824 ; 0x40000000 8006012: f7fa f8ab bl 800016c <__adddf3> 8006016: 4602 mov r2, r0 8006018: 460b mov r3, r1 800601a: 4650 mov r0, sl 800601c: 4659 mov r1, fp 800601e: f7fa fb85 bl 800072c <__aeabi_ddiv> 8006022: e9cd 0100 strd r0, r1, [sp] 8006026: 4620 mov r0, r4 8006028: f7fa f9ec bl 8000404 <__aeabi_i2d> 800602c: e9dd 2300 ldrd r2, r3, [sp] 8006030: e9cd 0102 strd r0, r1, [sp, #8] 8006034: 4610 mov r0, r2 8006036: 4619 mov r1, r3 8006038: f7fa fa4e bl 80004d8 <__aeabi_dmul> 800603c: f5a5 23c2 sub.w r3, r5, #397312 ; 0x61000 8006040: f2a3 437a subw r3, r3, #1146 ; 0x47a 8006044: 4602 mov r2, r0 8006046: 9305 str r3, [sp, #20] 8006048: 460b mov r3, r1 800604a: 4606 mov r6, r0 800604c: 460f mov r7, r1 800604e: f7fa fa43 bl 80004d8 <__aeabi_dmul> 8006052: a361 add r3, pc, #388 ; (adr r3, 80061d8 <__ieee754_log+0x318>) 8006054: e9d3 2300 ldrd r2, r3, [r3] 8006058: 4680 mov r8, r0 800605a: 4689 mov r9, r1 800605c: f7fa fa3c bl 80004d8 <__aeabi_dmul> 8006060: a35f add r3, pc, #380 ; (adr r3, 80061e0 <__ieee754_log+0x320>) 8006062: e9d3 2300 ldrd r2, r3, [r3] 8006066: f7fa f881 bl 800016c <__adddf3> 800606a: 4642 mov r2, r8 800606c: 464b mov r3, r9 800606e: f7fa fa33 bl 80004d8 <__aeabi_dmul> 8006072: a35d add r3, pc, #372 ; (adr r3, 80061e8 <__ieee754_log+0x328>) 8006074: e9d3 2300 ldrd r2, r3, [r3] 8006078: f7fa f878 bl 800016c <__adddf3> 800607c: 4642 mov r2, r8 800607e: 464b mov r3, r9 8006080: f7fa fa2a bl 80004d8 <__aeabi_dmul> 8006084: a35a add r3, pc, #360 ; (adr r3, 80061f0 <__ieee754_log+0x330>) 8006086: e9d3 2300 ldrd r2, r3, [r3] 800608a: f7fa f86f bl 800016c <__adddf3> 800608e: 4632 mov r2, r6 8006090: 463b mov r3, r7 8006092: f7fa fa21 bl 80004d8 <__aeabi_dmul> 8006096: a358 add r3, pc, #352 ; (adr r3, 80061f8 <__ieee754_log+0x338>) 8006098: e9d3 2300 ldrd r2, r3, [r3] 800609c: 4606 mov r6, r0 800609e: 460f mov r7, r1 80060a0: 4640 mov r0, r8 80060a2: 4649 mov r1, r9 80060a4: f7fa fa18 bl 80004d8 <__aeabi_dmul> 80060a8: a355 add r3, pc, #340 ; (adr r3, 8006200 <__ieee754_log+0x340>) 80060aa: e9d3 2300 ldrd r2, r3, [r3] 80060ae: f7fa f85d bl 800016c <__adddf3> 80060b2: 4642 mov r2, r8 80060b4: 464b mov r3, r9 80060b6: f7fa fa0f bl 80004d8 <__aeabi_dmul> 80060ba: a353 add r3, pc, #332 ; (adr r3, 8006208 <__ieee754_log+0x348>) 80060bc: e9d3 2300 ldrd r2, r3, [r3] 80060c0: f7fa f854 bl 800016c <__adddf3> 80060c4: 4642 mov r2, r8 80060c6: 464b mov r3, r9 80060c8: f7fa fa06 bl 80004d8 <__aeabi_dmul> 80060cc: 460b mov r3, r1 80060ce: 4602 mov r2, r0 80060d0: 4639 mov r1, r7 80060d2: 4630 mov r0, r6 80060d4: f7fa f84a bl 800016c <__adddf3> 80060d8: f5c5 25d7 rsb r5, r5, #440320 ; 0x6b800 80060dc: 9b05 ldr r3, [sp, #20] 80060de: 3551 adds r5, #81 ; 0x51 80060e0: 431d orrs r5, r3 80060e2: 2d00 cmp r5, #0 80060e4: 4680 mov r8, r0 80060e6: 4689 mov r9, r1 80060e8: dd48 ble.n 800617c <__ieee754_log+0x2bc> 80060ea: 2200 movs r2, #0 80060ec: 4b4c ldr r3, [pc, #304] ; (8006220 <__ieee754_log+0x360>) 80060ee: 4650 mov r0, sl 80060f0: 4659 mov r1, fp 80060f2: f7fa f9f1 bl 80004d8 <__aeabi_dmul> 80060f6: 4652 mov r2, sl 80060f8: 465b mov r3, fp 80060fa: f7fa f9ed bl 80004d8 <__aeabi_dmul> 80060fe: 4602 mov r2, r0 8006100: 460b mov r3, r1 8006102: 4606 mov r6, r0 8006104: 460f mov r7, r1 8006106: 4640 mov r0, r8 8006108: 4649 mov r1, r9 800610a: f7fa f82f bl 800016c <__adddf3> 800610e: e9dd 2300 ldrd r2, r3, [sp] 8006112: f7fa f9e1 bl 80004d8 <__aeabi_dmul> 8006116: 4680 mov r8, r0 8006118: 4689 mov r9, r1 800611a: b964 cbnz r4, 8006136 <__ieee754_log+0x276> 800611c: 4602 mov r2, r0 800611e: 460b mov r3, r1 8006120: 4630 mov r0, r6 8006122: 4639 mov r1, r7 8006124: f7fa f820 bl 8000168 <__aeabi_dsub> 8006128: 4602 mov r2, r0 800612a: 460b mov r3, r1 800612c: 4650 mov r0, sl 800612e: 4659 mov r1, fp 8006130: f7fa f81a bl 8000168 <__aeabi_dsub> 8006134: e6d7 b.n 8005ee6 <__ieee754_log+0x26> 8006136: a322 add r3, pc, #136 ; (adr r3, 80061c0 <__ieee754_log+0x300>) 8006138: e9d3 2300 ldrd r2, r3, [r3] 800613c: e9dd 0102 ldrd r0, r1, [sp, #8] 8006140: f7fa f9ca bl 80004d8 <__aeabi_dmul> 8006144: a320 add r3, pc, #128 ; (adr r3, 80061c8 <__ieee754_log+0x308>) 8006146: e9d3 2300 ldrd r2, r3, [r3] 800614a: 4604 mov r4, r0 800614c: 460d mov r5, r1 800614e: e9dd 0102 ldrd r0, r1, [sp, #8] 8006152: f7fa f9c1 bl 80004d8 <__aeabi_dmul> 8006156: 4642 mov r2, r8 8006158: 464b mov r3, r9 800615a: f7fa f807 bl 800016c <__adddf3> 800615e: 4602 mov r2, r0 8006160: 460b mov r3, r1 8006162: 4630 mov r0, r6 8006164: 4639 mov r1, r7 8006166: f7f9 ffff bl 8000168 <__aeabi_dsub> 800616a: 4652 mov r2, sl 800616c: 465b mov r3, fp 800616e: f7f9 fffb bl 8000168 <__aeabi_dsub> 8006172: 4602 mov r2, r0 8006174: 460b mov r3, r1 8006176: 4620 mov r0, r4 8006178: 4629 mov r1, r5 800617a: e7d9 b.n 8006130 <__ieee754_log+0x270> 800617c: 4602 mov r2, r0 800617e: 460b mov r3, r1 8006180: 4650 mov r0, sl 8006182: 4659 mov r1, fp 8006184: f7f9 fff0 bl 8000168 <__aeabi_dsub> 8006188: e9dd 2300 ldrd r2, r3, [sp] 800618c: f7fa f9a4 bl 80004d8 <__aeabi_dmul> 8006190: 4606 mov r6, r0 8006192: 460f mov r7, r1 8006194: 2c00 cmp r4, #0 8006196: f43f af23 beq.w 8005fe0 <__ieee754_log+0x120> 800619a: a309 add r3, pc, #36 ; (adr r3, 80061c0 <__ieee754_log+0x300>) 800619c: e9d3 2300 ldrd r2, r3, [r3] 80061a0: e9dd 0102 ldrd r0, r1, [sp, #8] 80061a4: f7fa f998 bl 80004d8 <__aeabi_dmul> 80061a8: a307 add r3, pc, #28 ; (adr r3, 80061c8 <__ieee754_log+0x308>) 80061aa: e9d3 2300 ldrd r2, r3, [r3] 80061ae: 4604 mov r4, r0 80061b0: 460d mov r5, r1 80061b2: e9dd 0102 ldrd r0, r1, [sp, #8] 80061b6: e727 b.n 8006008 <__ieee754_log+0x148> 80061b8: 2000 movs r0, #0 80061ba: 2100 movs r1, #0 80061bc: e693 b.n 8005ee6 <__ieee754_log+0x26> 80061be: bf00 nop 80061c0: fee00000 .word 0xfee00000 80061c4: 3fe62e42 .word 0x3fe62e42 80061c8: 35793c76 .word 0x35793c76 80061cc: 3dea39ef .word 0x3dea39ef 80061d0: 55555555 .word 0x55555555 80061d4: 3fd55555 .word 0x3fd55555 80061d8: df3e5244 .word 0xdf3e5244 80061dc: 3fc2f112 .word 0x3fc2f112 80061e0: 96cb03de .word 0x96cb03de 80061e4: 3fc74664 .word 0x3fc74664 80061e8: 94229359 .word 0x94229359 80061ec: 3fd24924 .word 0x3fd24924 80061f0: 55555593 .word 0x55555593 80061f4: 3fe55555 .word 0x3fe55555 80061f8: d078c69f .word 0xd078c69f 80061fc: 3fc39a09 .word 0x3fc39a09 8006200: 1d8e78af .word 0x1d8e78af 8006204: 3fcc71c5 .word 0x3fcc71c5 8006208: 9997fa04 .word 0x9997fa04 800620c: 3fd99999 .word 0x3fd99999 8006210: c3500000 .word 0xc3500000 8006214: 43500000 .word 0x43500000 8006218: 7fefffff .word 0x7fefffff 800621c: 3ff00000 .word 0x3ff00000 8006220: 3fe00000 .word 0x3fe00000 08006224 : 8006224: 2000 movs r0, #0 8006226: 4901 ldr r1, [pc, #4] ; (800622c ) 8006228: 4770 bx lr 800622a: bf00 nop 800622c: 7ff80000 .word 0x7ff80000 08006230 <_init>: 8006230: b5f8 push {r3, r4, r5, r6, r7, lr} 8006232: bf00 nop 8006234: bcf8 pop {r3, r4, r5, r6, r7} 8006236: bc08 pop {r3} 8006238: 469e mov lr, r3 800623a: 4770 bx lr 0800623c <_fini>: 800623c: b5f8 push {r3, r4, r5, r6, r7, lr} 800623e: bf00 nop 8006240: bcf8 pop {r3, r4, r5, r6, r7} 8006242: bc08 pop {r3} 8006244: 469e mov lr, r3 8006246: 4770 bx lr