GPIO_Relay.elf: file format elf32-littlearm Sections: Idx Name Size VMA LMA File off Algn 0 .isr_vector 0000010c 08000000 08000000 00010000 2**0 CONTENTS, ALLOC, LOAD, READONLY, DATA 1 .text 000011ac 0800010c 0800010c 0001010c 2**2 CONTENTS, ALLOC, LOAD, READONLY, CODE 2 .rodata 00000020 080012b8 080012b8 000112b8 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 3 .ARM.extab 00000000 080012d8 080012d8 0002000c 2**0 CONTENTS 4 .ARM 00000000 080012d8 080012d8 0002000c 2**0 CONTENTS 5 .preinit_array 00000000 080012d8 080012d8 0002000c 2**0 CONTENTS, ALLOC, LOAD, DATA 6 .init_array 00000004 080012d8 080012d8 000112d8 2**2 CONTENTS, ALLOC, LOAD, DATA 7 .fini_array 00000004 080012dc 080012dc 000112dc 2**2 CONTENTS, ALLOC, LOAD, DATA 8 .data 0000000c 20000000 080012e0 00020000 2**2 CONTENTS, ALLOC, LOAD, DATA 9 .bss 00000020 2000000c 080012ec 0002000c 2**2 ALLOC 10 ._user_heap_stack 00000604 2000002c 080012ec 0002002c 2**0 ALLOC 11 .ARM.attributes 00000029 00000000 00000000 0002000c 2**0 CONTENTS, READONLY 12 .debug_info 00002cf6 00000000 00000000 00020035 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 13 .debug_abbrev 00000eea 00000000 00000000 00022d2b 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 14 .debug_aranges 000003e8 00000000 00000000 00023c18 2**3 CONTENTS, READONLY, DEBUGGING, OCTETS 15 .debug_ranges 00000350 00000000 00000000 00024000 2**3 CONTENTS, READONLY, DEBUGGING, OCTETS 16 .debug_macro 00015a95 00000000 00000000 00024350 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 17 .debug_line 00004b6e 00000000 00000000 00039de5 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 18 .debug_str 0007b9fb 00000000 00000000 0003e953 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 19 .comment 00000050 00000000 00000000 000ba34e 2**0 CONTENTS, READONLY 20 .debug_frame 00000d40 00000000 00000000 000ba3a0 2**2 CONTENTS, READONLY, DEBUGGING, OCTETS Disassembly of section .text: 0800010c <__do_global_dtors_aux>: 800010c: b510 push {r4, lr} 800010e: 4c05 ldr r4, [pc, #20] ; (8000124 <__do_global_dtors_aux+0x18>) 8000110: 7823 ldrb r3, [r4, #0] 8000112: b933 cbnz r3, 8000122 <__do_global_dtors_aux+0x16> 8000114: 4b04 ldr r3, [pc, #16] ; (8000128 <__do_global_dtors_aux+0x1c>) 8000116: b113 cbz r3, 800011e <__do_global_dtors_aux+0x12> 8000118: 4804 ldr r0, [pc, #16] ; (800012c <__do_global_dtors_aux+0x20>) 800011a: f3af 8000 nop.w 800011e: 2301 movs r3, #1 8000120: 7023 strb r3, [r4, #0] 8000122: bd10 pop {r4, pc} 8000124: 2000000c .word 0x2000000c 8000128: 00000000 .word 0x00000000 800012c: 080012a0 .word 0x080012a0 08000130 : 8000130: b508 push {r3, lr} 8000132: 4b03 ldr r3, [pc, #12] ; (8000140 ) 8000134: b11b cbz r3, 800013e 8000136: 4903 ldr r1, [pc, #12] ; (8000144 ) 8000138: 4803 ldr r0, [pc, #12] ; (8000148 ) 800013a: f3af 8000 nop.w 800013e: bd08 pop {r3, pc} 8000140: 00000000 .word 0x00000000 8000144: 20000010 .word 0x20000010 8000148: 080012a0 .word 0x080012a0 0800014c : * Output * EVENT_OUT * EXTI */ void MX_GPIO_Init(void) { 800014c: b580 push {r7, lr} 800014e: b086 sub sp, #24 8000150: af00 add r7, sp, #0 GPIO_InitTypeDef GPIO_InitStruct = {0}; 8000152: f107 0308 add.w r3, r7, #8 8000156: 2200 movs r2, #0 8000158: 601a str r2, [r3, #0] 800015a: 605a str r2, [r3, #4] 800015c: 609a str r2, [r3, #8] 800015e: 60da str r2, [r3, #12] /* GPIO Ports Clock Enable */ __HAL_RCC_GPIOA_CLK_ENABLE(); 8000160: 4b27 ldr r3, [pc, #156] ; (8000200 ) 8000162: 699b ldr r3, [r3, #24] 8000164: 4a26 ldr r2, [pc, #152] ; (8000200 ) 8000166: f043 0304 orr.w r3, r3, #4 800016a: 6193 str r3, [r2, #24] 800016c: 4b24 ldr r3, [pc, #144] ; (8000200 ) 800016e: 699b ldr r3, [r3, #24] 8000170: f003 0304 and.w r3, r3, #4 8000174: 607b str r3, [r7, #4] 8000176: 687b ldr r3, [r7, #4] __HAL_RCC_GPIOB_CLK_ENABLE(); 8000178: 4b21 ldr r3, [pc, #132] ; (8000200 ) 800017a: 699b ldr r3, [r3, #24] 800017c: 4a20 ldr r2, [pc, #128] ; (8000200 ) 800017e: f043 0308 orr.w r3, r3, #8 8000182: 6193 str r3, [r2, #24] 8000184: 4b1e ldr r3, [pc, #120] ; (8000200 ) 8000186: 699b ldr r3, [r3, #24] 8000188: f003 0308 and.w r3, r3, #8 800018c: 603b str r3, [r7, #0] 800018e: 683b ldr r3, [r7, #0] /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GREEN_GPIO_Port, GREEN_Pin, GPIO_PIN_RESET); 8000190: 2200 movs r2, #0 8000192: 2180 movs r1, #128 ; 0x80 8000194: 481b ldr r0, [pc, #108] ; (8000204 ) 8000196: f000 fc3e bl 8000a16 /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOB, RED_Pin|RELAY_Pin, GPIO_PIN_RESET); 800019a: 2200 movs r2, #0 800019c: 2121 movs r1, #33 ; 0x21 800019e: 481a ldr r0, [pc, #104] ; (8000208 ) 80001a0: f000 fc39 bl 8000a16 /*Configure GPIO pin : PtPin */ GPIO_InitStruct.Pin = GREEN_Pin; 80001a4: 2380 movs r3, #128 ; 0x80 80001a6: 60bb str r3, [r7, #8] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 80001a8: 2301 movs r3, #1 80001aa: 60fb str r3, [r7, #12] GPIO_InitStruct.Pull = GPIO_NOPULL; 80001ac: 2300 movs r3, #0 80001ae: 613b str r3, [r7, #16] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 80001b0: 2302 movs r3, #2 80001b2: 617b str r3, [r7, #20] HAL_GPIO_Init(GREEN_GPIO_Port, &GPIO_InitStruct); 80001b4: f107 0308 add.w r3, r7, #8 80001b8: 4619 mov r1, r3 80001ba: 4812 ldr r0, [pc, #72] ; (8000204 ) 80001bc: f000 fa90 bl 80006e0 /*Configure GPIO pins : PBPin PBPin */ GPIO_InitStruct.Pin = RED_Pin|RELAY_Pin; 80001c0: 2321 movs r3, #33 ; 0x21 80001c2: 60bb str r3, [r7, #8] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 80001c4: 2301 movs r3, #1 80001c6: 60fb str r3, [r7, #12] GPIO_InitStruct.Pull = GPIO_NOPULL; 80001c8: 2300 movs r3, #0 80001ca: 613b str r3, [r7, #16] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 80001cc: 2302 movs r3, #2 80001ce: 617b str r3, [r7, #20] HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 80001d0: f107 0308 add.w r3, r7, #8 80001d4: 4619 mov r1, r3 80001d6: 480c ldr r0, [pc, #48] ; (8000208 ) 80001d8: f000 fa82 bl 80006e0 /*Configure GPIO pin : PtPin */ GPIO_InitStruct.Pin = KEY1_Pin; 80001dc: f44f 5380 mov.w r3, #4096 ; 0x1000 80001e0: 60bb str r3, [r7, #8] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 80001e2: 2300 movs r3, #0 80001e4: 60fb str r3, [r7, #12] GPIO_InitStruct.Pull = GPIO_NOPULL; 80001e6: 2300 movs r3, #0 80001e8: 613b str r3, [r7, #16] HAL_GPIO_Init(KEY1_GPIO_Port, &GPIO_InitStruct); 80001ea: f107 0308 add.w r3, r7, #8 80001ee: 4619 mov r1, r3 80001f0: 4805 ldr r0, [pc, #20] ; (8000208 ) 80001f2: f000 fa75 bl 80006e0 } 80001f6: bf00 nop 80001f8: 3718 adds r7, #24 80001fa: 46bd mov sp, r7 80001fc: bd80 pop {r7, pc} 80001fe: bf00 nop 8000200: 40021000 .word 0x40021000 8000204: 40010800 .word 0x40010800 8000208: 40010c00 .word 0x40010c00 0800020c
: /** * @brief The application entry point. * @retval int */ int main(void) { 800020c: b580 push {r7, lr} 800020e: af00 add r7, sp, #0 /* USER CODE END 1 */ /* MCU Configuration--------------------------------------------------------*/ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ HAL_Init(); 8000210: f000 f8fc bl 800040c /* USER CODE BEGIN Init */ /* USER CODE END Init */ /* Configure the system clock */ SystemClock_Config(); 8000214: f000 f834 bl 8000280 /* USER CODE BEGIN SysInit */ /* USER CODE END SysInit */ /* Initialize all configured peripherals */ MX_GPIO_Init(); 8000218: f7ff ff98 bl 800014c /* USER CODE END 2 */ /* Infinite loop */ /* USER CODE BEGIN WHILE */ HAL_GPIO_WritePin(RED_GPIO_Port, RED_Pin, 1); 800021c: 2201 movs r2, #1 800021e: 2101 movs r1, #1 8000220: 4815 ldr r0, [pc, #84] ; (8000278 ) 8000222: f000 fbf8 bl 8000a16 while (1) { if (!HAL_GPIO_ReadPin(KEY1_GPIO_Port, KEY1_Pin)) { 8000226: f44f 5180 mov.w r1, #4096 ; 0x1000 800022a: 4813 ldr r0, [pc, #76] ; (8000278 ) 800022c: f000 fbdc bl 80009e8 8000230: 4603 mov r3, r0 8000232: 2b00 cmp r3, #0 8000234: d1f7 bne.n 8000226 HAL_Delay(50); 8000236: 2032 movs r0, #50 ; 0x32 8000238: f000 f94a bl 80004d0 if (!HAL_GPIO_ReadPin(KEY1_GPIO_Port, KEY1_Pin)) { 800023c: f44f 5180 mov.w r1, #4096 ; 0x1000 8000240: 480d ldr r0, [pc, #52] ; (8000278 ) 8000242: f000 fbd1 bl 80009e8 8000246: 4603 mov r3, r0 8000248: 2b00 cmp r3, #0 800024a: d1ec bne.n 8000226 HAL_GPIO_TogglePin(RELAY_GPIO_Port, RELAY_Pin); 800024c: 2120 movs r1, #32 800024e: 480a ldr r0, [pc, #40] ; (8000278 ) 8000250: f000 fbf9 bl 8000a46 HAL_GPIO_TogglePin(RED_GPIO_Port, RED_Pin); 8000254: 2101 movs r1, #1 8000256: 4808 ldr r0, [pc, #32] ; (8000278 ) 8000258: f000 fbf5 bl 8000a46 HAL_GPIO_TogglePin(GREEN_GPIO_Port, GREEN_Pin); 800025c: 2180 movs r1, #128 ; 0x80 800025e: 4807 ldr r0, [pc, #28] ; (800027c ) 8000260: f000 fbf1 bl 8000a46 while (!HAL_GPIO_ReadPin(KEY1_GPIO_Port, KEY1_Pin)) { 8000264: bf00 nop 8000266: f44f 5180 mov.w r1, #4096 ; 0x1000 800026a: 4803 ldr r0, [pc, #12] ; (8000278 ) 800026c: f000 fbbc bl 80009e8 8000270: 4603 mov r3, r0 8000272: 2b00 cmp r3, #0 8000274: d0f7 beq.n 8000266 if (!HAL_GPIO_ReadPin(KEY1_GPIO_Port, KEY1_Pin)) { 8000276: e7d6 b.n 8000226 8000278: 40010c00 .word 0x40010c00 800027c: 40010800 .word 0x40010800 08000280 : /** * @brief System Clock Configuration * @retval None */ void SystemClock_Config(void) { 8000280: b580 push {r7, lr} 8000282: b090 sub sp, #64 ; 0x40 8000284: af00 add r7, sp, #0 RCC_OscInitTypeDef RCC_OscInitStruct = { 0 }; 8000286: f107 0318 add.w r3, r7, #24 800028a: 2228 movs r2, #40 ; 0x28 800028c: 2100 movs r1, #0 800028e: 4618 mov r0, r3 8000290: f000 fffe bl 8001290 RCC_ClkInitTypeDef RCC_ClkInitStruct = { 0 }; 8000294: 1d3b adds r3, r7, #4 8000296: 2200 movs r2, #0 8000298: 601a str r2, [r3, #0] 800029a: 605a str r2, [r3, #4] 800029c: 609a str r2, [r3, #8] 800029e: 60da str r2, [r3, #12] 80002a0: 611a str r2, [r3, #16] /** Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; 80002a2: 2302 movs r3, #2 80002a4: 61bb str r3, [r7, #24] RCC_OscInitStruct.HSIState = RCC_HSI_ON; 80002a6: 2301 movs r3, #1 80002a8: 62bb str r3, [r7, #40] ; 0x28 RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; 80002aa: 2310 movs r3, #16 80002ac: 62fb str r3, [r7, #44] ; 0x2c RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; 80002ae: 2300 movs r3, #0 80002b0: 637b str r3, [r7, #52] ; 0x34 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { 80002b2: f107 0318 add.w r3, r7, #24 80002b6: 4618 mov r0, r3 80002b8: f000 fbde bl 8000a78 80002bc: 4603 mov r3, r0 80002be: 2b00 cmp r3, #0 80002c0: d001 beq.n 80002c6 Error_Handler(); 80002c2: f000 f818 bl 80002f6 } /** Initializes the CPU, AHB and APB buses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK 80002c6: 230f movs r3, #15 80002c8: 607b str r3, [r7, #4] | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI; 80002ca: 2300 movs r3, #0 80002cc: 60bb str r3, [r7, #8] RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; 80002ce: 2300 movs r3, #0 80002d0: 60fb str r3, [r7, #12] RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; 80002d2: 2300 movs r3, #0 80002d4: 613b str r3, [r7, #16] RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; 80002d6: 2300 movs r3, #0 80002d8: 617b str r3, [r7, #20] if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK) { 80002da: 1d3b adds r3, r7, #4 80002dc: 2100 movs r1, #0 80002de: 4618 mov r0, r3 80002e0: f000 fe4c bl 8000f7c 80002e4: 4603 mov r3, r0 80002e6: 2b00 cmp r3, #0 80002e8: d001 beq.n 80002ee Error_Handler(); 80002ea: f000 f804 bl 80002f6 } } 80002ee: bf00 nop 80002f0: 3740 adds r7, #64 ; 0x40 80002f2: 46bd mov sp, r7 80002f4: bd80 pop {r7, pc} 080002f6 : /** * @brief This function is executed in case of error occurrence. * @retval None */ void Error_Handler(void) { 80002f6: b480 push {r7} 80002f8: af00 add r7, sp, #0 \details Disables IRQ interrupts by setting the I-bit in the CPSR. Can only be executed in Privileged modes. */ __STATIC_FORCEINLINE void __disable_irq(void) { __ASM volatile ("cpsid i" : : : "memory"); 80002fa: b672 cpsid i } 80002fc: bf00 nop /* USER CODE BEGIN Error_Handler_Debug */ /* User can add his own implementation to report the HAL error return state */ __disable_irq(); while (1) { 80002fe: e7fe b.n 80002fe 08000300 : /* USER CODE END 0 */ /** * Initializes the Global MSP. */ void HAL_MspInit(void) { 8000300: b480 push {r7} 8000302: b085 sub sp, #20 8000304: af00 add r7, sp, #0 /* USER CODE BEGIN MspInit 0 */ /* USER CODE END MspInit 0 */ __HAL_RCC_AFIO_CLK_ENABLE(); 8000306: 4b15 ldr r3, [pc, #84] ; (800035c ) 8000308: 699b ldr r3, [r3, #24] 800030a: 4a14 ldr r2, [pc, #80] ; (800035c ) 800030c: f043 0301 orr.w r3, r3, #1 8000310: 6193 str r3, [r2, #24] 8000312: 4b12 ldr r3, [pc, #72] ; (800035c ) 8000314: 699b ldr r3, [r3, #24] 8000316: f003 0301 and.w r3, r3, #1 800031a: 60bb str r3, [r7, #8] 800031c: 68bb ldr r3, [r7, #8] __HAL_RCC_PWR_CLK_ENABLE(); 800031e: 4b0f ldr r3, [pc, #60] ; (800035c ) 8000320: 69db ldr r3, [r3, #28] 8000322: 4a0e ldr r2, [pc, #56] ; (800035c ) 8000324: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 8000328: 61d3 str r3, [r2, #28] 800032a: 4b0c ldr r3, [pc, #48] ; (800035c ) 800032c: 69db ldr r3, [r3, #28] 800032e: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 8000332: 607b str r3, [r7, #4] 8000334: 687b ldr r3, [r7, #4] /* System interrupt init*/ /** NOJTAG: JTAG-DP Disabled and SW-DP Enabled */ __HAL_AFIO_REMAP_SWJ_NOJTAG(); 8000336: 4b0a ldr r3, [pc, #40] ; (8000360 ) 8000338: 685b ldr r3, [r3, #4] 800033a: 60fb str r3, [r7, #12] 800033c: 68fb ldr r3, [r7, #12] 800033e: f023 63e0 bic.w r3, r3, #117440512 ; 0x7000000 8000342: 60fb str r3, [r7, #12] 8000344: 68fb ldr r3, [r7, #12] 8000346: f043 7300 orr.w r3, r3, #33554432 ; 0x2000000 800034a: 60fb str r3, [r7, #12] 800034c: 4a04 ldr r2, [pc, #16] ; (8000360 ) 800034e: 68fb ldr r3, [r7, #12] 8000350: 6053 str r3, [r2, #4] /* USER CODE BEGIN MspInit 1 */ /* USER CODE END MspInit 1 */ } 8000352: bf00 nop 8000354: 3714 adds r7, #20 8000356: 46bd mov sp, r7 8000358: bc80 pop {r7} 800035a: 4770 bx lr 800035c: 40021000 .word 0x40021000 8000360: 40010000 .word 0x40010000 08000364 : /******************************************************************************/ /** * @brief This function handles Non maskable interrupt. */ void NMI_Handler(void) { 8000364: b480 push {r7} 8000366: af00 add r7, sp, #0 /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ /* USER CODE END NonMaskableInt_IRQn 0 */ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ while (1) 8000368: e7fe b.n 8000368 0800036a : /** * @brief This function handles Hard fault interrupt. */ void HardFault_Handler(void) { 800036a: b480 push {r7} 800036c: af00 add r7, sp, #0 /* USER CODE BEGIN HardFault_IRQn 0 */ /* USER CODE END HardFault_IRQn 0 */ while (1) 800036e: e7fe b.n 800036e 08000370 : /** * @brief This function handles Memory management fault. */ void MemManage_Handler(void) { 8000370: b480 push {r7} 8000372: af00 add r7, sp, #0 /* USER CODE BEGIN MemoryManagement_IRQn 0 */ /* USER CODE END MemoryManagement_IRQn 0 */ while (1) 8000374: e7fe b.n 8000374 08000376 : /** * @brief This function handles Prefetch fault, memory access fault. */ void BusFault_Handler(void) { 8000376: b480 push {r7} 8000378: af00 add r7, sp, #0 /* USER CODE BEGIN BusFault_IRQn 0 */ /* USER CODE END BusFault_IRQn 0 */ while (1) 800037a: e7fe b.n 800037a 0800037c : /** * @brief This function handles Undefined instruction or illegal state. */ void UsageFault_Handler(void) { 800037c: b480 push {r7} 800037e: af00 add r7, sp, #0 /* USER CODE BEGIN UsageFault_IRQn 0 */ /* USER CODE END UsageFault_IRQn 0 */ while (1) 8000380: e7fe b.n 8000380 08000382 : /** * @brief This function handles System service call via SWI instruction. */ void SVC_Handler(void) { 8000382: b480 push {r7} 8000384: af00 add r7, sp, #0 /* USER CODE END SVCall_IRQn 0 */ /* USER CODE BEGIN SVCall_IRQn 1 */ /* USER CODE END SVCall_IRQn 1 */ } 8000386: bf00 nop 8000388: 46bd mov sp, r7 800038a: bc80 pop {r7} 800038c: 4770 bx lr 0800038e : /** * @brief This function handles Debug monitor. */ void DebugMon_Handler(void) { 800038e: b480 push {r7} 8000390: af00 add r7, sp, #0 /* USER CODE END DebugMonitor_IRQn 0 */ /* USER CODE BEGIN DebugMonitor_IRQn 1 */ /* USER CODE END DebugMonitor_IRQn 1 */ } 8000392: bf00 nop 8000394: 46bd mov sp, r7 8000396: bc80 pop {r7} 8000398: 4770 bx lr 0800039a : /** * @brief This function handles Pendable request for system service. */ void PendSV_Handler(void) { 800039a: b480 push {r7} 800039c: af00 add r7, sp, #0 /* USER CODE END PendSV_IRQn 0 */ /* USER CODE BEGIN PendSV_IRQn 1 */ /* USER CODE END PendSV_IRQn 1 */ } 800039e: bf00 nop 80003a0: 46bd mov sp, r7 80003a2: bc80 pop {r7} 80003a4: 4770 bx lr 080003a6 : /** * @brief This function handles System tick timer. */ void SysTick_Handler(void) { 80003a6: b580 push {r7, lr} 80003a8: af00 add r7, sp, #0 /* USER CODE BEGIN SysTick_IRQn 0 */ /* USER CODE END SysTick_IRQn 0 */ HAL_IncTick(); 80003aa: f000 f875 bl 8000498 /* USER CODE BEGIN SysTick_IRQn 1 */ /* USER CODE END SysTick_IRQn 1 */ } 80003ae: bf00 nop 80003b0: bd80 pop {r7, pc} 080003b2 : * @note This function should be used only after reset. * @param None * @retval None */ void SystemInit (void) { 80003b2: b480 push {r7} 80003b4: af00 add r7, sp, #0 /* Configure the Vector Table location -------------------------------------*/ #if defined(USER_VECT_TAB_ADDRESS) SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ #endif /* USER_VECT_TAB_ADDRESS */ } 80003b6: bf00 nop 80003b8: 46bd mov sp, r7 80003ba: bc80 pop {r7} 80003bc: 4770 bx lr ... 080003c0 : .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata 80003c0: 480c ldr r0, [pc, #48] ; (80003f4 ) ldr r1, =_edata 80003c2: 490d ldr r1, [pc, #52] ; (80003f8 ) ldr r2, =_sidata 80003c4: 4a0d ldr r2, [pc, #52] ; (80003fc ) movs r3, #0 80003c6: 2300 movs r3, #0 b LoopCopyDataInit 80003c8: e002 b.n 80003d0 080003ca : CopyDataInit: ldr r4, [r2, r3] 80003ca: 58d4 ldr r4, [r2, r3] str r4, [r0, r3] 80003cc: 50c4 str r4, [r0, r3] adds r3, r3, #4 80003ce: 3304 adds r3, #4 080003d0 : LoopCopyDataInit: adds r4, r0, r3 80003d0: 18c4 adds r4, r0, r3 cmp r4, r1 80003d2: 428c cmp r4, r1 bcc CopyDataInit 80003d4: d3f9 bcc.n 80003ca /* Zero fill the bss segment. */ ldr r2, =_sbss 80003d6: 4a0a ldr r2, [pc, #40] ; (8000400 ) ldr r4, =_ebss 80003d8: 4c0a ldr r4, [pc, #40] ; (8000404 ) movs r3, #0 80003da: 2300 movs r3, #0 b LoopFillZerobss 80003dc: e001 b.n 80003e2 080003de : FillZerobss: str r3, [r2] 80003de: 6013 str r3, [r2, #0] adds r2, r2, #4 80003e0: 3204 adds r2, #4 080003e2 : LoopFillZerobss: cmp r2, r4 80003e2: 42a2 cmp r2, r4 bcc FillZerobss 80003e4: d3fb bcc.n 80003de /* Call the clock system intitialization function.*/ bl SystemInit 80003e6: f7ff ffe4 bl 80003b2 /* Call static constructors */ bl __libc_init_array 80003ea: f000 ff2d bl 8001248 <__libc_init_array> /* Call the application's entry point.*/ bl main 80003ee: f7ff ff0d bl 800020c
bx lr 80003f2: 4770 bx lr ldr r0, =_sdata 80003f4: 20000000 .word 0x20000000 ldr r1, =_edata 80003f8: 2000000c .word 0x2000000c ldr r2, =_sidata 80003fc: 080012e0 .word 0x080012e0 ldr r2, =_sbss 8000400: 2000000c .word 0x2000000c ldr r4, =_ebss 8000404: 2000002c .word 0x2000002c 08000408 : * @retval : None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop 8000408: e7fe b.n 8000408 ... 0800040c : * need to ensure that the SysTick time base is always set to 1 millisecond * to have correct HAL operation. * @retval HAL status */ HAL_StatusTypeDef HAL_Init(void) { 800040c: b580 push {r7, lr} 800040e: af00 add r7, sp, #0 defined(STM32F102x6) || defined(STM32F102xB) || \ defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || \ defined(STM32F105xC) || defined(STM32F107xC) /* Prefetch buffer is not available on value line devices */ __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); 8000410: 4b08 ldr r3, [pc, #32] ; (8000434 ) 8000412: 681b ldr r3, [r3, #0] 8000414: 4a07 ldr r2, [pc, #28] ; (8000434 ) 8000416: f043 0310 orr.w r3, r3, #16 800041a: 6013 str r3, [r2, #0] #endif #endif /* PREFETCH_ENABLE */ /* Set Interrupt Group Priority */ HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); 800041c: 2003 movs r0, #3 800041e: f000 f92b bl 8000678 /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ HAL_InitTick(TICK_INT_PRIORITY); 8000422: 200f movs r0, #15 8000424: f000 f808 bl 8000438 /* Init the low level hardware */ HAL_MspInit(); 8000428: f7ff ff6a bl 8000300 /* Return function status */ return HAL_OK; 800042c: 2300 movs r3, #0 } 800042e: 4618 mov r0, r3 8000430: bd80 pop {r7, pc} 8000432: bf00 nop 8000434: 40022000 .word 0x40022000 08000438 : * implementation in user file. * @param TickPriority Tick interrupt priority. * @retval HAL status */ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { 8000438: b580 push {r7, lr} 800043a: b082 sub sp, #8 800043c: af00 add r7, sp, #0 800043e: 6078 str r0, [r7, #4] /* Configure the SysTick to have interrupt in 1ms time basis*/ if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U) 8000440: 4b12 ldr r3, [pc, #72] ; (800048c ) 8000442: 681a ldr r2, [r3, #0] 8000444: 4b12 ldr r3, [pc, #72] ; (8000490 ) 8000446: 781b ldrb r3, [r3, #0] 8000448: 4619 mov r1, r3 800044a: f44f 737a mov.w r3, #1000 ; 0x3e8 800044e: fbb3 f3f1 udiv r3, r3, r1 8000452: fbb2 f3f3 udiv r3, r2, r3 8000456: 4618 mov r0, r3 8000458: f000 f935 bl 80006c6 800045c: 4603 mov r3, r0 800045e: 2b00 cmp r3, #0 8000460: d001 beq.n 8000466 { return HAL_ERROR; 8000462: 2301 movs r3, #1 8000464: e00e b.n 8000484 } /* Configure the SysTick IRQ priority */ if (TickPriority < (1UL << __NVIC_PRIO_BITS)) 8000466: 687b ldr r3, [r7, #4] 8000468: 2b0f cmp r3, #15 800046a: d80a bhi.n 8000482 { HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); 800046c: 2200 movs r2, #0 800046e: 6879 ldr r1, [r7, #4] 8000470: f04f 30ff mov.w r0, #4294967295 8000474: f000 f90b bl 800068e uwTickPrio = TickPriority; 8000478: 4a06 ldr r2, [pc, #24] ; (8000494 ) 800047a: 687b ldr r3, [r7, #4] 800047c: 6013 str r3, [r2, #0] { return HAL_ERROR; } /* Return function status */ return HAL_OK; 800047e: 2300 movs r3, #0 8000480: e000 b.n 8000484 return HAL_ERROR; 8000482: 2301 movs r3, #1 } 8000484: 4618 mov r0, r3 8000486: 3708 adds r7, #8 8000488: 46bd mov sp, r7 800048a: bd80 pop {r7, pc} 800048c: 20000000 .word 0x20000000 8000490: 20000008 .word 0x20000008 8000494: 20000004 .word 0x20000004 08000498 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ __weak void HAL_IncTick(void) { 8000498: b480 push {r7} 800049a: af00 add r7, sp, #0 uwTick += uwTickFreq; 800049c: 4b05 ldr r3, [pc, #20] ; (80004b4 ) 800049e: 781b ldrb r3, [r3, #0] 80004a0: 461a mov r2, r3 80004a2: 4b05 ldr r3, [pc, #20] ; (80004b8 ) 80004a4: 681b ldr r3, [r3, #0] 80004a6: 4413 add r3, r2 80004a8: 4a03 ldr r2, [pc, #12] ; (80004b8 ) 80004aa: 6013 str r3, [r2, #0] } 80004ac: bf00 nop 80004ae: 46bd mov sp, r7 80004b0: bc80 pop {r7} 80004b2: 4770 bx lr 80004b4: 20000008 .word 0x20000008 80004b8: 20000028 .word 0x20000028 080004bc : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval tick value */ __weak uint32_t HAL_GetTick(void) { 80004bc: b480 push {r7} 80004be: af00 add r7, sp, #0 return uwTick; 80004c0: 4b02 ldr r3, [pc, #8] ; (80004cc ) 80004c2: 681b ldr r3, [r3, #0] } 80004c4: 4618 mov r0, r3 80004c6: 46bd mov sp, r7 80004c8: bc80 pop {r7} 80004ca: 4770 bx lr 80004cc: 20000028 .word 0x20000028 080004d0 : * implementations in user file. * @param Delay specifies the delay time length, in milliseconds. * @retval None */ __weak void HAL_Delay(uint32_t Delay) { 80004d0: b580 push {r7, lr} 80004d2: b084 sub sp, #16 80004d4: af00 add r7, sp, #0 80004d6: 6078 str r0, [r7, #4] uint32_t tickstart = HAL_GetTick(); 80004d8: f7ff fff0 bl 80004bc 80004dc: 60b8 str r0, [r7, #8] uint32_t wait = Delay; 80004de: 687b ldr r3, [r7, #4] 80004e0: 60fb str r3, [r7, #12] /* Add a freq to guarantee minimum wait */ if (wait < HAL_MAX_DELAY) 80004e2: 68fb ldr r3, [r7, #12] 80004e4: f1b3 3fff cmp.w r3, #4294967295 80004e8: d005 beq.n 80004f6 { wait += (uint32_t)(uwTickFreq); 80004ea: 4b0a ldr r3, [pc, #40] ; (8000514 ) 80004ec: 781b ldrb r3, [r3, #0] 80004ee: 461a mov r2, r3 80004f0: 68fb ldr r3, [r7, #12] 80004f2: 4413 add r3, r2 80004f4: 60fb str r3, [r7, #12] } while ((HAL_GetTick() - tickstart) < wait) 80004f6: bf00 nop 80004f8: f7ff ffe0 bl 80004bc 80004fc: 4602 mov r2, r0 80004fe: 68bb ldr r3, [r7, #8] 8000500: 1ad3 subs r3, r2, r3 8000502: 68fa ldr r2, [r7, #12] 8000504: 429a cmp r2, r3 8000506: d8f7 bhi.n 80004f8 { } } 8000508: bf00 nop 800050a: bf00 nop 800050c: 3710 adds r7, #16 800050e: 46bd mov sp, r7 8000510: bd80 pop {r7, pc} 8000512: bf00 nop 8000514: 20000008 .word 0x20000008 08000518 <__NVIC_SetPriorityGrouping>: In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 8000518: b480 push {r7} 800051a: b085 sub sp, #20 800051c: af00 add r7, sp, #0 800051e: 6078 str r0, [r7, #4] uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 8000520: 687b ldr r3, [r7, #4] 8000522: f003 0307 and.w r3, r3, #7 8000526: 60fb str r3, [r7, #12] reg_value = SCB->AIRCR; /* read old register configuration */ 8000528: 4b0c ldr r3, [pc, #48] ; (800055c <__NVIC_SetPriorityGrouping+0x44>) 800052a: 68db ldr r3, [r3, #12] 800052c: 60bb str r3, [r7, #8] reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ 800052e: 68ba ldr r2, [r7, #8] 8000530: f64f 03ff movw r3, #63743 ; 0xf8ff 8000534: 4013 ands r3, r2 8000536: 60bb str r3, [r7, #8] reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ 8000538: 68fb ldr r3, [r7, #12] 800053a: 021a lsls r2, r3, #8 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 800053c: 68bb ldr r3, [r7, #8] 800053e: 4313 orrs r3, r2 reg_value = (reg_value | 8000540: f043 63bf orr.w r3, r3, #100139008 ; 0x5f80000 8000544: f443 3300 orr.w r3, r3, #131072 ; 0x20000 8000548: 60bb str r3, [r7, #8] SCB->AIRCR = reg_value; 800054a: 4a04 ldr r2, [pc, #16] ; (800055c <__NVIC_SetPriorityGrouping+0x44>) 800054c: 68bb ldr r3, [r7, #8] 800054e: 60d3 str r3, [r2, #12] } 8000550: bf00 nop 8000552: 3714 adds r7, #20 8000554: 46bd mov sp, r7 8000556: bc80 pop {r7} 8000558: 4770 bx lr 800055a: bf00 nop 800055c: e000ed00 .word 0xe000ed00 08000560 <__NVIC_GetPriorityGrouping>: \brief Get Priority Grouping \details Reads the priority grouping field from the NVIC Interrupt Controller. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) { 8000560: b480 push {r7} 8000562: af00 add r7, sp, #0 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); 8000564: 4b04 ldr r3, [pc, #16] ; (8000578 <__NVIC_GetPriorityGrouping+0x18>) 8000566: 68db ldr r3, [r3, #12] 8000568: 0a1b lsrs r3, r3, #8 800056a: f003 0307 and.w r3, r3, #7 } 800056e: 4618 mov r0, r3 8000570: 46bd mov sp, r7 8000572: bc80 pop {r7} 8000574: 4770 bx lr 8000576: bf00 nop 8000578: e000ed00 .word 0xe000ed00 0800057c <__NVIC_SetPriority>: \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { 800057c: b480 push {r7} 800057e: b083 sub sp, #12 8000580: af00 add r7, sp, #0 8000582: 4603 mov r3, r0 8000584: 6039 str r1, [r7, #0] 8000586: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) 8000588: f997 3007 ldrsb.w r3, [r7, #7] 800058c: 2b00 cmp r3, #0 800058e: db0a blt.n 80005a6 <__NVIC_SetPriority+0x2a> { NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 8000590: 683b ldr r3, [r7, #0] 8000592: b2da uxtb r2, r3 8000594: 490c ldr r1, [pc, #48] ; (80005c8 <__NVIC_SetPriority+0x4c>) 8000596: f997 3007 ldrsb.w r3, [r7, #7] 800059a: 0112 lsls r2, r2, #4 800059c: b2d2 uxtb r2, r2 800059e: 440b add r3, r1 80005a0: f883 2300 strb.w r2, [r3, #768] ; 0x300 } else { SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } 80005a4: e00a b.n 80005bc <__NVIC_SetPriority+0x40> SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 80005a6: 683b ldr r3, [r7, #0] 80005a8: b2da uxtb r2, r3 80005aa: 4908 ldr r1, [pc, #32] ; (80005cc <__NVIC_SetPriority+0x50>) 80005ac: 79fb ldrb r3, [r7, #7] 80005ae: f003 030f and.w r3, r3, #15 80005b2: 3b04 subs r3, #4 80005b4: 0112 lsls r2, r2, #4 80005b6: b2d2 uxtb r2, r2 80005b8: 440b add r3, r1 80005ba: 761a strb r2, [r3, #24] } 80005bc: bf00 nop 80005be: 370c adds r7, #12 80005c0: 46bd mov sp, r7 80005c2: bc80 pop {r7} 80005c4: 4770 bx lr 80005c6: bf00 nop 80005c8: e000e100 .word 0xe000e100 80005cc: e000ed00 .word 0xe000ed00 080005d0 : \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { 80005d0: b480 push {r7} 80005d2: b089 sub sp, #36 ; 0x24 80005d4: af00 add r7, sp, #0 80005d6: 60f8 str r0, [r7, #12] 80005d8: 60b9 str r1, [r7, #8] 80005da: 607a str r2, [r7, #4] uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 80005dc: 68fb ldr r3, [r7, #12] 80005de: f003 0307 and.w r3, r3, #7 80005e2: 61fb str r3, [r7, #28] uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 80005e4: 69fb ldr r3, [r7, #28] 80005e6: f1c3 0307 rsb r3, r3, #7 80005ea: 2b04 cmp r3, #4 80005ec: bf28 it cs 80005ee: 2304 movcs r3, #4 80005f0: 61bb str r3, [r7, #24] SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 80005f2: 69fb ldr r3, [r7, #28] 80005f4: 3304 adds r3, #4 80005f6: 2b06 cmp r3, #6 80005f8: d902 bls.n 8000600 80005fa: 69fb ldr r3, [r7, #28] 80005fc: 3b03 subs r3, #3 80005fe: e000 b.n 8000602 8000600: 2300 movs r3, #0 8000602: 617b str r3, [r7, #20] return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 8000604: f04f 32ff mov.w r2, #4294967295 8000608: 69bb ldr r3, [r7, #24] 800060a: fa02 f303 lsl.w r3, r2, r3 800060e: 43da mvns r2, r3 8000610: 68bb ldr r3, [r7, #8] 8000612: 401a ands r2, r3 8000614: 697b ldr r3, [r7, #20] 8000616: 409a lsls r2, r3 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) 8000618: f04f 31ff mov.w r1, #4294967295 800061c: 697b ldr r3, [r7, #20] 800061e: fa01 f303 lsl.w r3, r1, r3 8000622: 43d9 mvns r1, r3 8000624: 687b ldr r3, [r7, #4] 8000626: 400b ands r3, r1 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 8000628: 4313 orrs r3, r2 ); } 800062a: 4618 mov r0, r3 800062c: 3724 adds r7, #36 ; 0x24 800062e: 46bd mov sp, r7 8000630: bc80 pop {r7} 8000632: 4770 bx lr 08000634 : \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { 8000634: b580 push {r7, lr} 8000636: b082 sub sp, #8 8000638: af00 add r7, sp, #0 800063a: 6078 str r0, [r7, #4] if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) 800063c: 687b ldr r3, [r7, #4] 800063e: 3b01 subs r3, #1 8000640: f1b3 7f80 cmp.w r3, #16777216 ; 0x1000000 8000644: d301 bcc.n 800064a { return (1UL); /* Reload value impossible */ 8000646: 2301 movs r3, #1 8000648: e00f b.n 800066a } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 800064a: 4a0a ldr r2, [pc, #40] ; (8000674 ) 800064c: 687b ldr r3, [r7, #4] 800064e: 3b01 subs r3, #1 8000650: 6053 str r3, [r2, #4] NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ 8000652: 210f movs r1, #15 8000654: f04f 30ff mov.w r0, #4294967295 8000658: f7ff ff90 bl 800057c <__NVIC_SetPriority> SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ 800065c: 4b05 ldr r3, [pc, #20] ; (8000674 ) 800065e: 2200 movs r2, #0 8000660: 609a str r2, [r3, #8] SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 8000662: 4b04 ldr r3, [pc, #16] ; (8000674 ) 8000664: 2207 movs r2, #7 8000666: 601a str r2, [r3, #0] SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ 8000668: 2300 movs r3, #0 } 800066a: 4618 mov r0, r3 800066c: 3708 adds r7, #8 800066e: 46bd mov sp, r7 8000670: bd80 pop {r7, pc} 8000672: bf00 nop 8000674: e000e010 .word 0xe000e010 08000678 : * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. * The pending IRQ priority will be managed only by the subpriority. * @retval None */ void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 8000678: b580 push {r7, lr} 800067a: b082 sub sp, #8 800067c: af00 add r7, sp, #0 800067e: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ NVIC_SetPriorityGrouping(PriorityGroup); 8000680: 6878 ldr r0, [r7, #4] 8000682: f7ff ff49 bl 8000518 <__NVIC_SetPriorityGrouping> } 8000686: bf00 nop 8000688: 3708 adds r7, #8 800068a: 46bd mov sp, r7 800068c: bd80 pop {r7, pc} 0800068e : * This parameter can be a value between 0 and 15 * A lower priority value indicates a higher priority. * @retval None */ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) { 800068e: b580 push {r7, lr} 8000690: b086 sub sp, #24 8000692: af00 add r7, sp, #0 8000694: 4603 mov r3, r0 8000696: 60b9 str r1, [r7, #8] 8000698: 607a str r2, [r7, #4] 800069a: 73fb strb r3, [r7, #15] uint32_t prioritygroup = 0x00U; 800069c: 2300 movs r3, #0 800069e: 617b str r3, [r7, #20] /* Check the parameters */ assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); prioritygroup = NVIC_GetPriorityGrouping(); 80006a0: f7ff ff5e bl 8000560 <__NVIC_GetPriorityGrouping> 80006a4: 6178 str r0, [r7, #20] NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); 80006a6: 687a ldr r2, [r7, #4] 80006a8: 68b9 ldr r1, [r7, #8] 80006aa: 6978 ldr r0, [r7, #20] 80006ac: f7ff ff90 bl 80005d0 80006b0: 4602 mov r2, r0 80006b2: f997 300f ldrsb.w r3, [r7, #15] 80006b6: 4611 mov r1, r2 80006b8: 4618 mov r0, r3 80006ba: f7ff ff5f bl 800057c <__NVIC_SetPriority> } 80006be: bf00 nop 80006c0: 3718 adds r7, #24 80006c2: 46bd mov sp, r7 80006c4: bd80 pop {r7, pc} 080006c6 : * @param TicksNumb: Specifies the ticks Number of ticks between two interrupts. * @retval status: - 0 Function succeeded. * - 1 Function failed. */ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) { 80006c6: b580 push {r7, lr} 80006c8: b082 sub sp, #8 80006ca: af00 add r7, sp, #0 80006cc: 6078 str r0, [r7, #4] return SysTick_Config(TicksNumb); 80006ce: 6878 ldr r0, [r7, #4] 80006d0: f7ff ffb0 bl 8000634 80006d4: 4603 mov r3, r0 } 80006d6: 4618 mov r0, r3 80006d8: 3708 adds r7, #8 80006da: 46bd mov sp, r7 80006dc: bd80 pop {r7, pc} ... 080006e0 : * @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains * the configuration information for the specified GPIO peripheral. * @retval None */ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) { 80006e0: b480 push {r7} 80006e2: b08b sub sp, #44 ; 0x2c 80006e4: af00 add r7, sp, #0 80006e6: 6078 str r0, [r7, #4] 80006e8: 6039 str r1, [r7, #0] uint32_t position = 0x00u; 80006ea: 2300 movs r3, #0 80006ec: 627b str r3, [r7, #36] ; 0x24 uint32_t ioposition; uint32_t iocurrent; uint32_t temp; uint32_t config = 0x00u; 80006ee: 2300 movs r3, #0 80006f0: 623b str r3, [r7, #32] assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); /* Configure the port pins */ while (((GPIO_Init->Pin) >> position) != 0x00u) 80006f2: e169 b.n 80009c8 { /* Get the IO position */ ioposition = (0x01uL << position); 80006f4: 2201 movs r2, #1 80006f6: 6a7b ldr r3, [r7, #36] ; 0x24 80006f8: fa02 f303 lsl.w r3, r2, r3 80006fc: 61fb str r3, [r7, #28] /* Get the current IO position */ iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition; 80006fe: 683b ldr r3, [r7, #0] 8000700: 681b ldr r3, [r3, #0] 8000702: 69fa ldr r2, [r7, #28] 8000704: 4013 ands r3, r2 8000706: 61bb str r3, [r7, #24] if (iocurrent == ioposition) 8000708: 69ba ldr r2, [r7, #24] 800070a: 69fb ldr r3, [r7, #28] 800070c: 429a cmp r2, r3 800070e: f040 8158 bne.w 80009c2 { /* Check the Alternate function parameters */ assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); /* Based on the required mode, filling config variable with MODEy[1:0] and CNFy[3:2] corresponding bits */ switch (GPIO_Init->Mode) 8000712: 683b ldr r3, [r7, #0] 8000714: 685b ldr r3, [r3, #4] 8000716: 4a9a ldr r2, [pc, #616] ; (8000980 ) 8000718: 4293 cmp r3, r2 800071a: d05e beq.n 80007da 800071c: 4a98 ldr r2, [pc, #608] ; (8000980 ) 800071e: 4293 cmp r3, r2 8000720: d875 bhi.n 800080e 8000722: 4a98 ldr r2, [pc, #608] ; (8000984 ) 8000724: 4293 cmp r3, r2 8000726: d058 beq.n 80007da 8000728: 4a96 ldr r2, [pc, #600] ; (8000984 ) 800072a: 4293 cmp r3, r2 800072c: d86f bhi.n 800080e 800072e: 4a96 ldr r2, [pc, #600] ; (8000988 ) 8000730: 4293 cmp r3, r2 8000732: d052 beq.n 80007da 8000734: 4a94 ldr r2, [pc, #592] ; (8000988 ) 8000736: 4293 cmp r3, r2 8000738: d869 bhi.n 800080e 800073a: 4a94 ldr r2, [pc, #592] ; (800098c ) 800073c: 4293 cmp r3, r2 800073e: d04c beq.n 80007da 8000740: 4a92 ldr r2, [pc, #584] ; (800098c ) 8000742: 4293 cmp r3, r2 8000744: d863 bhi.n 800080e 8000746: 4a92 ldr r2, [pc, #584] ; (8000990 ) 8000748: 4293 cmp r3, r2 800074a: d046 beq.n 80007da 800074c: 4a90 ldr r2, [pc, #576] ; (8000990 ) 800074e: 4293 cmp r3, r2 8000750: d85d bhi.n 800080e 8000752: 2b12 cmp r3, #18 8000754: d82a bhi.n 80007ac 8000756: 2b12 cmp r3, #18 8000758: d859 bhi.n 800080e 800075a: a201 add r2, pc, #4 ; (adr r2, 8000760 ) 800075c: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8000760: 080007db .word 0x080007db 8000764: 080007b5 .word 0x080007b5 8000768: 080007c7 .word 0x080007c7 800076c: 08000809 .word 0x08000809 8000770: 0800080f .word 0x0800080f 8000774: 0800080f .word 0x0800080f 8000778: 0800080f .word 0x0800080f 800077c: 0800080f .word 0x0800080f 8000780: 0800080f .word 0x0800080f 8000784: 0800080f .word 0x0800080f 8000788: 0800080f .word 0x0800080f 800078c: 0800080f .word 0x0800080f 8000790: 0800080f .word 0x0800080f 8000794: 0800080f .word 0x0800080f 8000798: 0800080f .word 0x0800080f 800079c: 0800080f .word 0x0800080f 80007a0: 0800080f .word 0x0800080f 80007a4: 080007bd .word 0x080007bd 80007a8: 080007d1 .word 0x080007d1 80007ac: 4a79 ldr r2, [pc, #484] ; (8000994 ) 80007ae: 4293 cmp r3, r2 80007b0: d013 beq.n 80007da config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG; break; /* Parameters are checked with assert_param */ default: break; 80007b2: e02c b.n 800080e config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_PP; 80007b4: 683b ldr r3, [r7, #0] 80007b6: 68db ldr r3, [r3, #12] 80007b8: 623b str r3, [r7, #32] break; 80007ba: e029 b.n 8000810 config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_OD; 80007bc: 683b ldr r3, [r7, #0] 80007be: 68db ldr r3, [r3, #12] 80007c0: 3304 adds r3, #4 80007c2: 623b str r3, [r7, #32] break; 80007c4: e024 b.n 8000810 config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_PP; 80007c6: 683b ldr r3, [r7, #0] 80007c8: 68db ldr r3, [r3, #12] 80007ca: 3308 adds r3, #8 80007cc: 623b str r3, [r7, #32] break; 80007ce: e01f b.n 8000810 config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_OD; 80007d0: 683b ldr r3, [r7, #0] 80007d2: 68db ldr r3, [r3, #12] 80007d4: 330c adds r3, #12 80007d6: 623b str r3, [r7, #32] break; 80007d8: e01a b.n 8000810 if (GPIO_Init->Pull == GPIO_NOPULL) 80007da: 683b ldr r3, [r7, #0] 80007dc: 689b ldr r3, [r3, #8] 80007de: 2b00 cmp r3, #0 80007e0: d102 bne.n 80007e8 config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_FLOATING; 80007e2: 2304 movs r3, #4 80007e4: 623b str r3, [r7, #32] break; 80007e6: e013 b.n 8000810 else if (GPIO_Init->Pull == GPIO_PULLUP) 80007e8: 683b ldr r3, [r7, #0] 80007ea: 689b ldr r3, [r3, #8] 80007ec: 2b01 cmp r3, #1 80007ee: d105 bne.n 80007fc config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD; 80007f0: 2308 movs r3, #8 80007f2: 623b str r3, [r7, #32] GPIOx->BSRR = ioposition; 80007f4: 687b ldr r3, [r7, #4] 80007f6: 69fa ldr r2, [r7, #28] 80007f8: 611a str r2, [r3, #16] break; 80007fa: e009 b.n 8000810 config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD; 80007fc: 2308 movs r3, #8 80007fe: 623b str r3, [r7, #32] GPIOx->BRR = ioposition; 8000800: 687b ldr r3, [r7, #4] 8000802: 69fa ldr r2, [r7, #28] 8000804: 615a str r2, [r3, #20] break; 8000806: e003 b.n 8000810 config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG; 8000808: 2300 movs r3, #0 800080a: 623b str r3, [r7, #32] break; 800080c: e000 b.n 8000810 break; 800080e: bf00 nop } /* Check if the current bit belongs to first half or last half of the pin count number in order to address CRH or CRL register*/ configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL : &GPIOx->CRH; 8000810: 69bb ldr r3, [r7, #24] 8000812: 2bff cmp r3, #255 ; 0xff 8000814: d801 bhi.n 800081a 8000816: 687b ldr r3, [r7, #4] 8000818: e001 b.n 800081e 800081a: 687b ldr r3, [r7, #4] 800081c: 3304 adds r3, #4 800081e: 617b str r3, [r7, #20] registeroffset = (iocurrent < GPIO_PIN_8) ? (position << 2u) : ((position - 8u) << 2u); 8000820: 69bb ldr r3, [r7, #24] 8000822: 2bff cmp r3, #255 ; 0xff 8000824: d802 bhi.n 800082c 8000826: 6a7b ldr r3, [r7, #36] ; 0x24 8000828: 009b lsls r3, r3, #2 800082a: e002 b.n 8000832 800082c: 6a7b ldr r3, [r7, #36] ; 0x24 800082e: 3b08 subs r3, #8 8000830: 009b lsls r3, r3, #2 8000832: 613b str r3, [r7, #16] /* Apply the new configuration of the pin to the register */ MODIFY_REG((*configregister), ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset), (config << registeroffset)); 8000834: 697b ldr r3, [r7, #20] 8000836: 681a ldr r2, [r3, #0] 8000838: 210f movs r1, #15 800083a: 693b ldr r3, [r7, #16] 800083c: fa01 f303 lsl.w r3, r1, r3 8000840: 43db mvns r3, r3 8000842: 401a ands r2, r3 8000844: 6a39 ldr r1, [r7, #32] 8000846: 693b ldr r3, [r7, #16] 8000848: fa01 f303 lsl.w r3, r1, r3 800084c: 431a orrs r2, r3 800084e: 697b ldr r3, [r7, #20] 8000850: 601a str r2, [r3, #0] /*--------------------- EXTI Mode Configuration ------------------------*/ /* Configure the External Interrupt or event for the current IO */ if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE) 8000852: 683b ldr r3, [r7, #0] 8000854: 685b ldr r3, [r3, #4] 8000856: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 800085a: 2b00 cmp r3, #0 800085c: f000 80b1 beq.w 80009c2 { /* Enable AFIO Clock */ __HAL_RCC_AFIO_CLK_ENABLE(); 8000860: 4b4d ldr r3, [pc, #308] ; (8000998 ) 8000862: 699b ldr r3, [r3, #24] 8000864: 4a4c ldr r2, [pc, #304] ; (8000998 ) 8000866: f043 0301 orr.w r3, r3, #1 800086a: 6193 str r3, [r2, #24] 800086c: 4b4a ldr r3, [pc, #296] ; (8000998 ) 800086e: 699b ldr r3, [r3, #24] 8000870: f003 0301 and.w r3, r3, #1 8000874: 60bb str r3, [r7, #8] 8000876: 68bb ldr r3, [r7, #8] temp = AFIO->EXTICR[position >> 2u]; 8000878: 4a48 ldr r2, [pc, #288] ; (800099c ) 800087a: 6a7b ldr r3, [r7, #36] ; 0x24 800087c: 089b lsrs r3, r3, #2 800087e: 3302 adds r3, #2 8000880: f852 3023 ldr.w r3, [r2, r3, lsl #2] 8000884: 60fb str r3, [r7, #12] CLEAR_BIT(temp, (0x0Fu) << (4u * (position & 0x03u))); 8000886: 6a7b ldr r3, [r7, #36] ; 0x24 8000888: f003 0303 and.w r3, r3, #3 800088c: 009b lsls r3, r3, #2 800088e: 220f movs r2, #15 8000890: fa02 f303 lsl.w r3, r2, r3 8000894: 43db mvns r3, r3 8000896: 68fa ldr r2, [r7, #12] 8000898: 4013 ands r3, r2 800089a: 60fb str r3, [r7, #12] SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4u * (position & 0x03u))); 800089c: 687b ldr r3, [r7, #4] 800089e: 4a40 ldr r2, [pc, #256] ; (80009a0 ) 80008a0: 4293 cmp r3, r2 80008a2: d013 beq.n 80008cc 80008a4: 687b ldr r3, [r7, #4] 80008a6: 4a3f ldr r2, [pc, #252] ; (80009a4 ) 80008a8: 4293 cmp r3, r2 80008aa: d00d beq.n 80008c8 80008ac: 687b ldr r3, [r7, #4] 80008ae: 4a3e ldr r2, [pc, #248] ; (80009a8 ) 80008b0: 4293 cmp r3, r2 80008b2: d007 beq.n 80008c4 80008b4: 687b ldr r3, [r7, #4] 80008b6: 4a3d ldr r2, [pc, #244] ; (80009ac ) 80008b8: 4293 cmp r3, r2 80008ba: d101 bne.n 80008c0 80008bc: 2303 movs r3, #3 80008be: e006 b.n 80008ce 80008c0: 2304 movs r3, #4 80008c2: e004 b.n 80008ce 80008c4: 2302 movs r3, #2 80008c6: e002 b.n 80008ce 80008c8: 2301 movs r3, #1 80008ca: e000 b.n 80008ce 80008cc: 2300 movs r3, #0 80008ce: 6a7a ldr r2, [r7, #36] ; 0x24 80008d0: f002 0203 and.w r2, r2, #3 80008d4: 0092 lsls r2, r2, #2 80008d6: 4093 lsls r3, r2 80008d8: 68fa ldr r2, [r7, #12] 80008da: 4313 orrs r3, r2 80008dc: 60fb str r3, [r7, #12] AFIO->EXTICR[position >> 2u] = temp; 80008de: 492f ldr r1, [pc, #188] ; (800099c ) 80008e0: 6a7b ldr r3, [r7, #36] ; 0x24 80008e2: 089b lsrs r3, r3, #2 80008e4: 3302 adds r3, #2 80008e6: 68fa ldr r2, [r7, #12] 80008e8: f841 2023 str.w r2, [r1, r3, lsl #2] /* Configure the interrupt mask */ if ((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT) 80008ec: 683b ldr r3, [r7, #0] 80008ee: 685b ldr r3, [r3, #4] 80008f0: f403 3380 and.w r3, r3, #65536 ; 0x10000 80008f4: 2b00 cmp r3, #0 80008f6: d006 beq.n 8000906 { SET_BIT(EXTI->IMR, iocurrent); 80008f8: 4b2d ldr r3, [pc, #180] ; (80009b0 ) 80008fa: 681a ldr r2, [r3, #0] 80008fc: 492c ldr r1, [pc, #176] ; (80009b0 ) 80008fe: 69bb ldr r3, [r7, #24] 8000900: 4313 orrs r3, r2 8000902: 600b str r3, [r1, #0] 8000904: e006 b.n 8000914 } else { CLEAR_BIT(EXTI->IMR, iocurrent); 8000906: 4b2a ldr r3, [pc, #168] ; (80009b0 ) 8000908: 681a ldr r2, [r3, #0] 800090a: 69bb ldr r3, [r7, #24] 800090c: 43db mvns r3, r3 800090e: 4928 ldr r1, [pc, #160] ; (80009b0 ) 8000910: 4013 ands r3, r2 8000912: 600b str r3, [r1, #0] } /* Configure the event mask */ if ((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT) 8000914: 683b ldr r3, [r7, #0] 8000916: 685b ldr r3, [r3, #4] 8000918: f403 3300 and.w r3, r3, #131072 ; 0x20000 800091c: 2b00 cmp r3, #0 800091e: d006 beq.n 800092e { SET_BIT(EXTI->EMR, iocurrent); 8000920: 4b23 ldr r3, [pc, #140] ; (80009b0 ) 8000922: 685a ldr r2, [r3, #4] 8000924: 4922 ldr r1, [pc, #136] ; (80009b0 ) 8000926: 69bb ldr r3, [r7, #24] 8000928: 4313 orrs r3, r2 800092a: 604b str r3, [r1, #4] 800092c: e006 b.n 800093c } else { CLEAR_BIT(EXTI->EMR, iocurrent); 800092e: 4b20 ldr r3, [pc, #128] ; (80009b0 ) 8000930: 685a ldr r2, [r3, #4] 8000932: 69bb ldr r3, [r7, #24] 8000934: 43db mvns r3, r3 8000936: 491e ldr r1, [pc, #120] ; (80009b0 ) 8000938: 4013 ands r3, r2 800093a: 604b str r3, [r1, #4] } /* Enable or disable the rising trigger */ if ((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE) 800093c: 683b ldr r3, [r7, #0] 800093e: 685b ldr r3, [r3, #4] 8000940: f403 1380 and.w r3, r3, #1048576 ; 0x100000 8000944: 2b00 cmp r3, #0 8000946: d006 beq.n 8000956 { SET_BIT(EXTI->RTSR, iocurrent); 8000948: 4b19 ldr r3, [pc, #100] ; (80009b0 ) 800094a: 689a ldr r2, [r3, #8] 800094c: 4918 ldr r1, [pc, #96] ; (80009b0 ) 800094e: 69bb ldr r3, [r7, #24] 8000950: 4313 orrs r3, r2 8000952: 608b str r3, [r1, #8] 8000954: e006 b.n 8000964 } else { CLEAR_BIT(EXTI->RTSR, iocurrent); 8000956: 4b16 ldr r3, [pc, #88] ; (80009b0 ) 8000958: 689a ldr r2, [r3, #8] 800095a: 69bb ldr r3, [r7, #24] 800095c: 43db mvns r3, r3 800095e: 4914 ldr r1, [pc, #80] ; (80009b0 ) 8000960: 4013 ands r3, r2 8000962: 608b str r3, [r1, #8] } /* Enable or disable the falling trigger */ if ((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE) 8000964: 683b ldr r3, [r7, #0] 8000966: 685b ldr r3, [r3, #4] 8000968: f403 1300 and.w r3, r3, #2097152 ; 0x200000 800096c: 2b00 cmp r3, #0 800096e: d021 beq.n 80009b4 { SET_BIT(EXTI->FTSR, iocurrent); 8000970: 4b0f ldr r3, [pc, #60] ; (80009b0 ) 8000972: 68da ldr r2, [r3, #12] 8000974: 490e ldr r1, [pc, #56] ; (80009b0 ) 8000976: 69bb ldr r3, [r7, #24] 8000978: 4313 orrs r3, r2 800097a: 60cb str r3, [r1, #12] 800097c: e021 b.n 80009c2 800097e: bf00 nop 8000980: 10320000 .word 0x10320000 8000984: 10310000 .word 0x10310000 8000988: 10220000 .word 0x10220000 800098c: 10210000 .word 0x10210000 8000990: 10120000 .word 0x10120000 8000994: 10110000 .word 0x10110000 8000998: 40021000 .word 0x40021000 800099c: 40010000 .word 0x40010000 80009a0: 40010800 .word 0x40010800 80009a4: 40010c00 .word 0x40010c00 80009a8: 40011000 .word 0x40011000 80009ac: 40011400 .word 0x40011400 80009b0: 40010400 .word 0x40010400 } else { CLEAR_BIT(EXTI->FTSR, iocurrent); 80009b4: 4b0b ldr r3, [pc, #44] ; (80009e4 ) 80009b6: 68da ldr r2, [r3, #12] 80009b8: 69bb ldr r3, [r7, #24] 80009ba: 43db mvns r3, r3 80009bc: 4909 ldr r1, [pc, #36] ; (80009e4 ) 80009be: 4013 ands r3, r2 80009c0: 60cb str r3, [r1, #12] } } } position++; 80009c2: 6a7b ldr r3, [r7, #36] ; 0x24 80009c4: 3301 adds r3, #1 80009c6: 627b str r3, [r7, #36] ; 0x24 while (((GPIO_Init->Pin) >> position) != 0x00u) 80009c8: 683b ldr r3, [r7, #0] 80009ca: 681a ldr r2, [r3, #0] 80009cc: 6a7b ldr r3, [r7, #36] ; 0x24 80009ce: fa22 f303 lsr.w r3, r2, r3 80009d2: 2b00 cmp r3, #0 80009d4: f47f ae8e bne.w 80006f4 } } 80009d8: bf00 nop 80009da: bf00 nop 80009dc: 372c adds r7, #44 ; 0x2c 80009de: 46bd mov sp, r7 80009e0: bc80 pop {r7} 80009e2: 4770 bx lr 80009e4: 40010400 .word 0x40010400 080009e8 : * @param GPIO_Pin: specifies the port bit to read. * This parameter can be GPIO_PIN_x where x can be (0..15). * @retval The input port pin value. */ GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) { 80009e8: b480 push {r7} 80009ea: b085 sub sp, #20 80009ec: af00 add r7, sp, #0 80009ee: 6078 str r0, [r7, #4] 80009f0: 460b mov r3, r1 80009f2: 807b strh r3, [r7, #2] GPIO_PinState bitstatus; /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET) 80009f4: 687b ldr r3, [r7, #4] 80009f6: 689a ldr r2, [r3, #8] 80009f8: 887b ldrh r3, [r7, #2] 80009fa: 4013 ands r3, r2 80009fc: 2b00 cmp r3, #0 80009fe: d002 beq.n 8000a06 { bitstatus = GPIO_PIN_SET; 8000a00: 2301 movs r3, #1 8000a02: 73fb strb r3, [r7, #15] 8000a04: e001 b.n 8000a0a } else { bitstatus = GPIO_PIN_RESET; 8000a06: 2300 movs r3, #0 8000a08: 73fb strb r3, [r7, #15] } return bitstatus; 8000a0a: 7bfb ldrb r3, [r7, #15] } 8000a0c: 4618 mov r0, r3 8000a0e: 3714 adds r7, #20 8000a10: 46bd mov sp, r7 8000a12: bc80 pop {r7} 8000a14: 4770 bx lr 08000a16 : * @arg GPIO_PIN_RESET: to clear the port pin * @arg GPIO_PIN_SET: to set the port pin * @retval None */ void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) { 8000a16: b480 push {r7} 8000a18: b083 sub sp, #12 8000a1a: af00 add r7, sp, #0 8000a1c: 6078 str r0, [r7, #4] 8000a1e: 460b mov r3, r1 8000a20: 807b strh r3, [r7, #2] 8000a22: 4613 mov r3, r2 8000a24: 707b strb r3, [r7, #1] /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); assert_param(IS_GPIO_PIN_ACTION(PinState)); if (PinState != GPIO_PIN_RESET) 8000a26: 787b ldrb r3, [r7, #1] 8000a28: 2b00 cmp r3, #0 8000a2a: d003 beq.n 8000a34 { GPIOx->BSRR = GPIO_Pin; 8000a2c: 887a ldrh r2, [r7, #2] 8000a2e: 687b ldr r3, [r7, #4] 8000a30: 611a str r2, [r3, #16] } else { GPIOx->BSRR = (uint32_t)GPIO_Pin << 16u; } } 8000a32: e003 b.n 8000a3c GPIOx->BSRR = (uint32_t)GPIO_Pin << 16u; 8000a34: 887b ldrh r3, [r7, #2] 8000a36: 041a lsls r2, r3, #16 8000a38: 687b ldr r3, [r7, #4] 8000a3a: 611a str r2, [r3, #16] } 8000a3c: bf00 nop 8000a3e: 370c adds r7, #12 8000a40: 46bd mov sp, r7 8000a42: bc80 pop {r7} 8000a44: 4770 bx lr 08000a46 : * @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral * @param GPIO_Pin: Specifies the pins to be toggled. * @retval None */ void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) { 8000a46: b480 push {r7} 8000a48: b085 sub sp, #20 8000a4a: af00 add r7, sp, #0 8000a4c: 6078 str r0, [r7, #4] 8000a4e: 460b mov r3, r1 8000a50: 807b strh r3, [r7, #2] /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); /* get current Ouput Data Register value */ odr = GPIOx->ODR; 8000a52: 687b ldr r3, [r7, #4] 8000a54: 68db ldr r3, [r3, #12] 8000a56: 60fb str r3, [r7, #12] /* Set selected pins that were at low level, and reset ones that were high */ GPIOx->BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin); 8000a58: 887a ldrh r2, [r7, #2] 8000a5a: 68fb ldr r3, [r7, #12] 8000a5c: 4013 ands r3, r2 8000a5e: 041a lsls r2, r3, #16 8000a60: 68fb ldr r3, [r7, #12] 8000a62: 43d9 mvns r1, r3 8000a64: 887b ldrh r3, [r7, #2] 8000a66: 400b ands r3, r1 8000a68: 431a orrs r2, r3 8000a6a: 687b ldr r3, [r7, #4] 8000a6c: 611a str r2, [r3, #16] } 8000a6e: bf00 nop 8000a70: 3714 adds r7, #20 8000a72: 46bd mov sp, r7 8000a74: bc80 pop {r7} 8000a76: 4770 bx lr 08000a78 : * supported by this macro. User should request a transition to HSE Off * first and then HSE On or HSE Bypass. * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { 8000a78: b580 push {r7, lr} 8000a7a: b086 sub sp, #24 8000a7c: af00 add r7, sp, #0 8000a7e: 6078 str r0, [r7, #4] uint32_t tickstart; uint32_t pll_config; /* Check Null pointer */ if (RCC_OscInitStruct == NULL) 8000a80: 687b ldr r3, [r7, #4] 8000a82: 2b00 cmp r3, #0 8000a84: d101 bne.n 8000a8a { return HAL_ERROR; 8000a86: 2301 movs r3, #1 8000a88: e272 b.n 8000f70 /* Check the parameters */ assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); /*------------------------------- HSE Configuration ------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) 8000a8a: 687b ldr r3, [r7, #4] 8000a8c: 681b ldr r3, [r3, #0] 8000a8e: f003 0301 and.w r3, r3, #1 8000a92: 2b00 cmp r3, #0 8000a94: f000 8087 beq.w 8000ba6 { /* Check the parameters */ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */ if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE) 8000a98: 4b92 ldr r3, [pc, #584] ; (8000ce4 ) 8000a9a: 685b ldr r3, [r3, #4] 8000a9c: f003 030c and.w r3, r3, #12 8000aa0: 2b04 cmp r3, #4 8000aa2: d00c beq.n 8000abe || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE))) 8000aa4: 4b8f ldr r3, [pc, #572] ; (8000ce4 ) 8000aa6: 685b ldr r3, [r3, #4] 8000aa8: f003 030c and.w r3, r3, #12 8000aac: 2b08 cmp r3, #8 8000aae: d112 bne.n 8000ad6 8000ab0: 4b8c ldr r3, [pc, #560] ; (8000ce4 ) 8000ab2: 685b ldr r3, [r3, #4] 8000ab4: f403 3380 and.w r3, r3, #65536 ; 0x10000 8000ab8: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 8000abc: d10b bne.n 8000ad6 { if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 8000abe: 4b89 ldr r3, [pc, #548] ; (8000ce4 ) 8000ac0: 681b ldr r3, [r3, #0] 8000ac2: f403 3300 and.w r3, r3, #131072 ; 0x20000 8000ac6: 2b00 cmp r3, #0 8000ac8: d06c beq.n 8000ba4 8000aca: 687b ldr r3, [r7, #4] 8000acc: 685b ldr r3, [r3, #4] 8000ace: 2b00 cmp r3, #0 8000ad0: d168 bne.n 8000ba4 { return HAL_ERROR; 8000ad2: 2301 movs r3, #1 8000ad4: e24c b.n 8000f70 } } else { /* Set the new HSE configuration ---------------------------------------*/ __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); 8000ad6: 687b ldr r3, [r7, #4] 8000ad8: 685b ldr r3, [r3, #4] 8000ada: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 8000ade: d106 bne.n 8000aee 8000ae0: 4b80 ldr r3, [pc, #512] ; (8000ce4 ) 8000ae2: 681b ldr r3, [r3, #0] 8000ae4: 4a7f ldr r2, [pc, #508] ; (8000ce4 ) 8000ae6: f443 3380 orr.w r3, r3, #65536 ; 0x10000 8000aea: 6013 str r3, [r2, #0] 8000aec: e02e b.n 8000b4c 8000aee: 687b ldr r3, [r7, #4] 8000af0: 685b ldr r3, [r3, #4] 8000af2: 2b00 cmp r3, #0 8000af4: d10c bne.n 8000b10 8000af6: 4b7b ldr r3, [pc, #492] ; (8000ce4 ) 8000af8: 681b ldr r3, [r3, #0] 8000afa: 4a7a ldr r2, [pc, #488] ; (8000ce4 ) 8000afc: f423 3380 bic.w r3, r3, #65536 ; 0x10000 8000b00: 6013 str r3, [r2, #0] 8000b02: 4b78 ldr r3, [pc, #480] ; (8000ce4 ) 8000b04: 681b ldr r3, [r3, #0] 8000b06: 4a77 ldr r2, [pc, #476] ; (8000ce4 ) 8000b08: f423 2380 bic.w r3, r3, #262144 ; 0x40000 8000b0c: 6013 str r3, [r2, #0] 8000b0e: e01d b.n 8000b4c 8000b10: 687b ldr r3, [r7, #4] 8000b12: 685b ldr r3, [r3, #4] 8000b14: f5b3 2fa0 cmp.w r3, #327680 ; 0x50000 8000b18: d10c bne.n 8000b34 8000b1a: 4b72 ldr r3, [pc, #456] ; (8000ce4 ) 8000b1c: 681b ldr r3, [r3, #0] 8000b1e: 4a71 ldr r2, [pc, #452] ; (8000ce4 ) 8000b20: f443 2380 orr.w r3, r3, #262144 ; 0x40000 8000b24: 6013 str r3, [r2, #0] 8000b26: 4b6f ldr r3, [pc, #444] ; (8000ce4 ) 8000b28: 681b ldr r3, [r3, #0] 8000b2a: 4a6e ldr r2, [pc, #440] ; (8000ce4 ) 8000b2c: f443 3380 orr.w r3, r3, #65536 ; 0x10000 8000b30: 6013 str r3, [r2, #0] 8000b32: e00b b.n 8000b4c 8000b34: 4b6b ldr r3, [pc, #428] ; (8000ce4 ) 8000b36: 681b ldr r3, [r3, #0] 8000b38: 4a6a ldr r2, [pc, #424] ; (8000ce4 ) 8000b3a: f423 3380 bic.w r3, r3, #65536 ; 0x10000 8000b3e: 6013 str r3, [r2, #0] 8000b40: 4b68 ldr r3, [pc, #416] ; (8000ce4 ) 8000b42: 681b ldr r3, [r3, #0] 8000b44: 4a67 ldr r2, [pc, #412] ; (8000ce4 ) 8000b46: f423 2380 bic.w r3, r3, #262144 ; 0x40000 8000b4a: 6013 str r3, [r2, #0] /* Check the HSE State */ if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF) 8000b4c: 687b ldr r3, [r7, #4] 8000b4e: 685b ldr r3, [r3, #4] 8000b50: 2b00 cmp r3, #0 8000b52: d013 beq.n 8000b7c { /* Get Start Tick */ tickstart = HAL_GetTick(); 8000b54: f7ff fcb2 bl 80004bc 8000b58: 6138 str r0, [r7, #16] /* Wait till HSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 8000b5a: e008 b.n 8000b6e { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 8000b5c: f7ff fcae bl 80004bc 8000b60: 4602 mov r2, r0 8000b62: 693b ldr r3, [r7, #16] 8000b64: 1ad3 subs r3, r2, r3 8000b66: 2b64 cmp r3, #100 ; 0x64 8000b68: d901 bls.n 8000b6e { return HAL_TIMEOUT; 8000b6a: 2303 movs r3, #3 8000b6c: e200 b.n 8000f70 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 8000b6e: 4b5d ldr r3, [pc, #372] ; (8000ce4 ) 8000b70: 681b ldr r3, [r3, #0] 8000b72: f403 3300 and.w r3, r3, #131072 ; 0x20000 8000b76: 2b00 cmp r3, #0 8000b78: d0f0 beq.n 8000b5c 8000b7a: e014 b.n 8000ba6 } } else { /* Get Start Tick */ tickstart = HAL_GetTick(); 8000b7c: f7ff fc9e bl 80004bc 8000b80: 6138 str r0, [r7, #16] /* Wait till HSE is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) 8000b82: e008 b.n 8000b96 { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 8000b84: f7ff fc9a bl 80004bc 8000b88: 4602 mov r2, r0 8000b8a: 693b ldr r3, [r7, #16] 8000b8c: 1ad3 subs r3, r2, r3 8000b8e: 2b64 cmp r3, #100 ; 0x64 8000b90: d901 bls.n 8000b96 { return HAL_TIMEOUT; 8000b92: 2303 movs r3, #3 8000b94: e1ec b.n 8000f70 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) 8000b96: 4b53 ldr r3, [pc, #332] ; (8000ce4 ) 8000b98: 681b ldr r3, [r3, #0] 8000b9a: f403 3300 and.w r3, r3, #131072 ; 0x20000 8000b9e: 2b00 cmp r3, #0 8000ba0: d1f0 bne.n 8000b84 8000ba2: e000 b.n 8000ba6 if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 8000ba4: bf00 nop } } } } /*----------------------------- HSI Configuration --------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) 8000ba6: 687b ldr r3, [r7, #4] 8000ba8: 681b ldr r3, [r3, #0] 8000baa: f003 0302 and.w r3, r3, #2 8000bae: 2b00 cmp r3, #0 8000bb0: d063 beq.n 8000c7a /* Check the parameters */ assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI) 8000bb2: 4b4c ldr r3, [pc, #304] ; (8000ce4 ) 8000bb4: 685b ldr r3, [r3, #4] 8000bb6: f003 030c and.w r3, r3, #12 8000bba: 2b00 cmp r3, #0 8000bbc: d00b beq.n 8000bd6 || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI_DIV2))) 8000bbe: 4b49 ldr r3, [pc, #292] ; (8000ce4 ) 8000bc0: 685b ldr r3, [r3, #4] 8000bc2: f003 030c and.w r3, r3, #12 8000bc6: 2b08 cmp r3, #8 8000bc8: d11c bne.n 8000c04 8000bca: 4b46 ldr r3, [pc, #280] ; (8000ce4 ) 8000bcc: 685b ldr r3, [r3, #4] 8000bce: f403 3380 and.w r3, r3, #65536 ; 0x10000 8000bd2: 2b00 cmp r3, #0 8000bd4: d116 bne.n 8000c04 { /* When HSI is used as system clock it will not disabled */ if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) 8000bd6: 4b43 ldr r3, [pc, #268] ; (8000ce4 ) 8000bd8: 681b ldr r3, [r3, #0] 8000bda: f003 0302 and.w r3, r3, #2 8000bde: 2b00 cmp r3, #0 8000be0: d005 beq.n 8000bee 8000be2: 687b ldr r3, [r7, #4] 8000be4: 691b ldr r3, [r3, #16] 8000be6: 2b01 cmp r3, #1 8000be8: d001 beq.n 8000bee { return HAL_ERROR; 8000bea: 2301 movs r3, #1 8000bec: e1c0 b.n 8000f70 } /* Otherwise, just the calibration is allowed */ else { /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 8000bee: 4b3d ldr r3, [pc, #244] ; (8000ce4 ) 8000bf0: 681b ldr r3, [r3, #0] 8000bf2: f023 02f8 bic.w r2, r3, #248 ; 0xf8 8000bf6: 687b ldr r3, [r7, #4] 8000bf8: 695b ldr r3, [r3, #20] 8000bfa: 00db lsls r3, r3, #3 8000bfc: 4939 ldr r1, [pc, #228] ; (8000ce4 ) 8000bfe: 4313 orrs r3, r2 8000c00: 600b str r3, [r1, #0] if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) 8000c02: e03a b.n 8000c7a } } else { /* Check the HSI State */ if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF) 8000c04: 687b ldr r3, [r7, #4] 8000c06: 691b ldr r3, [r3, #16] 8000c08: 2b00 cmp r3, #0 8000c0a: d020 beq.n 8000c4e { /* Enable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_ENABLE(); 8000c0c: 4b36 ldr r3, [pc, #216] ; (8000ce8 ) 8000c0e: 2201 movs r2, #1 8000c10: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8000c12: f7ff fc53 bl 80004bc 8000c16: 6138 str r0, [r7, #16] /* Wait till HSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 8000c18: e008 b.n 8000c2c { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 8000c1a: f7ff fc4f bl 80004bc 8000c1e: 4602 mov r2, r0 8000c20: 693b ldr r3, [r7, #16] 8000c22: 1ad3 subs r3, r2, r3 8000c24: 2b02 cmp r3, #2 8000c26: d901 bls.n 8000c2c { return HAL_TIMEOUT; 8000c28: 2303 movs r3, #3 8000c2a: e1a1 b.n 8000f70 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 8000c2c: 4b2d ldr r3, [pc, #180] ; (8000ce4 ) 8000c2e: 681b ldr r3, [r3, #0] 8000c30: f003 0302 and.w r3, r3, #2 8000c34: 2b00 cmp r3, #0 8000c36: d0f0 beq.n 8000c1a } } /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 8000c38: 4b2a ldr r3, [pc, #168] ; (8000ce4 ) 8000c3a: 681b ldr r3, [r3, #0] 8000c3c: f023 02f8 bic.w r2, r3, #248 ; 0xf8 8000c40: 687b ldr r3, [r7, #4] 8000c42: 695b ldr r3, [r3, #20] 8000c44: 00db lsls r3, r3, #3 8000c46: 4927 ldr r1, [pc, #156] ; (8000ce4 ) 8000c48: 4313 orrs r3, r2 8000c4a: 600b str r3, [r1, #0] 8000c4c: e015 b.n 8000c7a } else { /* Disable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_DISABLE(); 8000c4e: 4b26 ldr r3, [pc, #152] ; (8000ce8 ) 8000c50: 2200 movs r2, #0 8000c52: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8000c54: f7ff fc32 bl 80004bc 8000c58: 6138 str r0, [r7, #16] /* Wait till HSI is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) 8000c5a: e008 b.n 8000c6e { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 8000c5c: f7ff fc2e bl 80004bc 8000c60: 4602 mov r2, r0 8000c62: 693b ldr r3, [r7, #16] 8000c64: 1ad3 subs r3, r2, r3 8000c66: 2b02 cmp r3, #2 8000c68: d901 bls.n 8000c6e { return HAL_TIMEOUT; 8000c6a: 2303 movs r3, #3 8000c6c: e180 b.n 8000f70 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) 8000c6e: 4b1d ldr r3, [pc, #116] ; (8000ce4 ) 8000c70: 681b ldr r3, [r3, #0] 8000c72: f003 0302 and.w r3, r3, #2 8000c76: 2b00 cmp r3, #0 8000c78: d1f0 bne.n 8000c5c } } } } /*------------------------------ LSI Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) 8000c7a: 687b ldr r3, [r7, #4] 8000c7c: 681b ldr r3, [r3, #0] 8000c7e: f003 0308 and.w r3, r3, #8 8000c82: 2b00 cmp r3, #0 8000c84: d03a beq.n 8000cfc { /* Check the parameters */ assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); /* Check the LSI State */ if (RCC_OscInitStruct->LSIState != RCC_LSI_OFF) 8000c86: 687b ldr r3, [r7, #4] 8000c88: 699b ldr r3, [r3, #24] 8000c8a: 2b00 cmp r3, #0 8000c8c: d019 beq.n 8000cc2 { /* Enable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_ENABLE(); 8000c8e: 4b17 ldr r3, [pc, #92] ; (8000cec ) 8000c90: 2201 movs r2, #1 8000c92: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8000c94: f7ff fc12 bl 80004bc 8000c98: 6138 str r0, [r7, #16] /* Wait till LSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) 8000c9a: e008 b.n 8000cae { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 8000c9c: f7ff fc0e bl 80004bc 8000ca0: 4602 mov r2, r0 8000ca2: 693b ldr r3, [r7, #16] 8000ca4: 1ad3 subs r3, r2, r3 8000ca6: 2b02 cmp r3, #2 8000ca8: d901 bls.n 8000cae { return HAL_TIMEOUT; 8000caa: 2303 movs r3, #3 8000cac: e160 b.n 8000f70 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) 8000cae: 4b0d ldr r3, [pc, #52] ; (8000ce4 ) 8000cb0: 6a5b ldr r3, [r3, #36] ; 0x24 8000cb2: f003 0302 and.w r3, r3, #2 8000cb6: 2b00 cmp r3, #0 8000cb8: d0f0 beq.n 8000c9c } } /* To have a fully stabilized clock in the specified range, a software delay of 1ms should be added.*/ RCC_Delay(1); 8000cba: 2001 movs r0, #1 8000cbc: f000 faa6 bl 800120c 8000cc0: e01c b.n 8000cfc } else { /* Disable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_DISABLE(); 8000cc2: 4b0a ldr r3, [pc, #40] ; (8000cec ) 8000cc4: 2200 movs r2, #0 8000cc6: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8000cc8: f7ff fbf8 bl 80004bc 8000ccc: 6138 str r0, [r7, #16] /* Wait till LSI is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) 8000cce: e00f b.n 8000cf0 { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 8000cd0: f7ff fbf4 bl 80004bc 8000cd4: 4602 mov r2, r0 8000cd6: 693b ldr r3, [r7, #16] 8000cd8: 1ad3 subs r3, r2, r3 8000cda: 2b02 cmp r3, #2 8000cdc: d908 bls.n 8000cf0 { return HAL_TIMEOUT; 8000cde: 2303 movs r3, #3 8000ce0: e146 b.n 8000f70 8000ce2: bf00 nop 8000ce4: 40021000 .word 0x40021000 8000ce8: 42420000 .word 0x42420000 8000cec: 42420480 .word 0x42420480 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) 8000cf0: 4b92 ldr r3, [pc, #584] ; (8000f3c ) 8000cf2: 6a5b ldr r3, [r3, #36] ; 0x24 8000cf4: f003 0302 and.w r3, r3, #2 8000cf8: 2b00 cmp r3, #0 8000cfa: d1e9 bne.n 8000cd0 } } } } /*------------------------------ LSE Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) 8000cfc: 687b ldr r3, [r7, #4] 8000cfe: 681b ldr r3, [r3, #0] 8000d00: f003 0304 and.w r3, r3, #4 8000d04: 2b00 cmp r3, #0 8000d06: f000 80a6 beq.w 8000e56 { FlagStatus pwrclkchanged = RESET; 8000d0a: 2300 movs r3, #0 8000d0c: 75fb strb r3, [r7, #23] /* Check the parameters */ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); /* Update LSE configuration in Backup Domain control register */ /* Requires to enable write access to Backup Domain of necessary */ if (__HAL_RCC_PWR_IS_CLK_DISABLED()) 8000d0e: 4b8b ldr r3, [pc, #556] ; (8000f3c ) 8000d10: 69db ldr r3, [r3, #28] 8000d12: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 8000d16: 2b00 cmp r3, #0 8000d18: d10d bne.n 8000d36 { __HAL_RCC_PWR_CLK_ENABLE(); 8000d1a: 4b88 ldr r3, [pc, #544] ; (8000f3c ) 8000d1c: 69db ldr r3, [r3, #28] 8000d1e: 4a87 ldr r2, [pc, #540] ; (8000f3c ) 8000d20: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 8000d24: 61d3 str r3, [r2, #28] 8000d26: 4b85 ldr r3, [pc, #532] ; (8000f3c ) 8000d28: 69db ldr r3, [r3, #28] 8000d2a: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 8000d2e: 60bb str r3, [r7, #8] 8000d30: 68bb ldr r3, [r7, #8] pwrclkchanged = SET; 8000d32: 2301 movs r3, #1 8000d34: 75fb strb r3, [r7, #23] } if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8000d36: 4b82 ldr r3, [pc, #520] ; (8000f40 ) 8000d38: 681b ldr r3, [r3, #0] 8000d3a: f403 7380 and.w r3, r3, #256 ; 0x100 8000d3e: 2b00 cmp r3, #0 8000d40: d118 bne.n 8000d74 { /* Enable write access to Backup domain */ SET_BIT(PWR->CR, PWR_CR_DBP); 8000d42: 4b7f ldr r3, [pc, #508] ; (8000f40 ) 8000d44: 681b ldr r3, [r3, #0] 8000d46: 4a7e ldr r2, [pc, #504] ; (8000f40 ) 8000d48: f443 7380 orr.w r3, r3, #256 ; 0x100 8000d4c: 6013 str r3, [r2, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 8000d4e: f7ff fbb5 bl 80004bc 8000d52: 6138 str r0, [r7, #16] while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8000d54: e008 b.n 8000d68 { if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 8000d56: f7ff fbb1 bl 80004bc 8000d5a: 4602 mov r2, r0 8000d5c: 693b ldr r3, [r7, #16] 8000d5e: 1ad3 subs r3, r2, r3 8000d60: 2b64 cmp r3, #100 ; 0x64 8000d62: d901 bls.n 8000d68 { return HAL_TIMEOUT; 8000d64: 2303 movs r3, #3 8000d66: e103 b.n 8000f70 while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8000d68: 4b75 ldr r3, [pc, #468] ; (8000f40 ) 8000d6a: 681b ldr r3, [r3, #0] 8000d6c: f403 7380 and.w r3, r3, #256 ; 0x100 8000d70: 2b00 cmp r3, #0 8000d72: d0f0 beq.n 8000d56 } } } /* Set the new LSE configuration -----------------------------------------*/ __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); 8000d74: 687b ldr r3, [r7, #4] 8000d76: 68db ldr r3, [r3, #12] 8000d78: 2b01 cmp r3, #1 8000d7a: d106 bne.n 8000d8a 8000d7c: 4b6f ldr r3, [pc, #444] ; (8000f3c ) 8000d7e: 6a1b ldr r3, [r3, #32] 8000d80: 4a6e ldr r2, [pc, #440] ; (8000f3c ) 8000d82: f043 0301 orr.w r3, r3, #1 8000d86: 6213 str r3, [r2, #32] 8000d88: e02d b.n 8000de6 8000d8a: 687b ldr r3, [r7, #4] 8000d8c: 68db ldr r3, [r3, #12] 8000d8e: 2b00 cmp r3, #0 8000d90: d10c bne.n 8000dac 8000d92: 4b6a ldr r3, [pc, #424] ; (8000f3c ) 8000d94: 6a1b ldr r3, [r3, #32] 8000d96: 4a69 ldr r2, [pc, #420] ; (8000f3c ) 8000d98: f023 0301 bic.w r3, r3, #1 8000d9c: 6213 str r3, [r2, #32] 8000d9e: 4b67 ldr r3, [pc, #412] ; (8000f3c ) 8000da0: 6a1b ldr r3, [r3, #32] 8000da2: 4a66 ldr r2, [pc, #408] ; (8000f3c ) 8000da4: f023 0304 bic.w r3, r3, #4 8000da8: 6213 str r3, [r2, #32] 8000daa: e01c b.n 8000de6 8000dac: 687b ldr r3, [r7, #4] 8000dae: 68db ldr r3, [r3, #12] 8000db0: 2b05 cmp r3, #5 8000db2: d10c bne.n 8000dce 8000db4: 4b61 ldr r3, [pc, #388] ; (8000f3c ) 8000db6: 6a1b ldr r3, [r3, #32] 8000db8: 4a60 ldr r2, [pc, #384] ; (8000f3c ) 8000dba: f043 0304 orr.w r3, r3, #4 8000dbe: 6213 str r3, [r2, #32] 8000dc0: 4b5e ldr r3, [pc, #376] ; (8000f3c ) 8000dc2: 6a1b ldr r3, [r3, #32] 8000dc4: 4a5d ldr r2, [pc, #372] ; (8000f3c ) 8000dc6: f043 0301 orr.w r3, r3, #1 8000dca: 6213 str r3, [r2, #32] 8000dcc: e00b b.n 8000de6 8000dce: 4b5b ldr r3, [pc, #364] ; (8000f3c ) 8000dd0: 6a1b ldr r3, [r3, #32] 8000dd2: 4a5a ldr r2, [pc, #360] ; (8000f3c ) 8000dd4: f023 0301 bic.w r3, r3, #1 8000dd8: 6213 str r3, [r2, #32] 8000dda: 4b58 ldr r3, [pc, #352] ; (8000f3c ) 8000ddc: 6a1b ldr r3, [r3, #32] 8000dde: 4a57 ldr r2, [pc, #348] ; (8000f3c ) 8000de0: f023 0304 bic.w r3, r3, #4 8000de4: 6213 str r3, [r2, #32] /* Check the LSE State */ if (RCC_OscInitStruct->LSEState != RCC_LSE_OFF) 8000de6: 687b ldr r3, [r7, #4] 8000de8: 68db ldr r3, [r3, #12] 8000dea: 2b00 cmp r3, #0 8000dec: d015 beq.n 8000e1a { /* Get Start Tick */ tickstart = HAL_GetTick(); 8000dee: f7ff fb65 bl 80004bc 8000df2: 6138 str r0, [r7, #16] /* Wait till LSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 8000df4: e00a b.n 8000e0c { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 8000df6: f7ff fb61 bl 80004bc 8000dfa: 4602 mov r2, r0 8000dfc: 693b ldr r3, [r7, #16] 8000dfe: 1ad3 subs r3, r2, r3 8000e00: f241 3288 movw r2, #5000 ; 0x1388 8000e04: 4293 cmp r3, r2 8000e06: d901 bls.n 8000e0c { return HAL_TIMEOUT; 8000e08: 2303 movs r3, #3 8000e0a: e0b1 b.n 8000f70 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 8000e0c: 4b4b ldr r3, [pc, #300] ; (8000f3c ) 8000e0e: 6a1b ldr r3, [r3, #32] 8000e10: f003 0302 and.w r3, r3, #2 8000e14: 2b00 cmp r3, #0 8000e16: d0ee beq.n 8000df6 8000e18: e014 b.n 8000e44 } } else { /* Get Start Tick */ tickstart = HAL_GetTick(); 8000e1a: f7ff fb4f bl 80004bc 8000e1e: 6138 str r0, [r7, #16] /* Wait till LSE is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) 8000e20: e00a b.n 8000e38 { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 8000e22: f7ff fb4b bl 80004bc 8000e26: 4602 mov r2, r0 8000e28: 693b ldr r3, [r7, #16] 8000e2a: 1ad3 subs r3, r2, r3 8000e2c: f241 3288 movw r2, #5000 ; 0x1388 8000e30: 4293 cmp r3, r2 8000e32: d901 bls.n 8000e38 { return HAL_TIMEOUT; 8000e34: 2303 movs r3, #3 8000e36: e09b b.n 8000f70 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) 8000e38: 4b40 ldr r3, [pc, #256] ; (8000f3c ) 8000e3a: 6a1b ldr r3, [r3, #32] 8000e3c: f003 0302 and.w r3, r3, #2 8000e40: 2b00 cmp r3, #0 8000e42: d1ee bne.n 8000e22 } } } /* Require to disable power clock if necessary */ if (pwrclkchanged == SET) 8000e44: 7dfb ldrb r3, [r7, #23] 8000e46: 2b01 cmp r3, #1 8000e48: d105 bne.n 8000e56 { __HAL_RCC_PWR_CLK_DISABLE(); 8000e4a: 4b3c ldr r3, [pc, #240] ; (8000f3c ) 8000e4c: 69db ldr r3, [r3, #28] 8000e4e: 4a3b ldr r2, [pc, #236] ; (8000f3c ) 8000e50: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000 8000e54: 61d3 str r3, [r2, #28] #endif /* RCC_CR_PLL2ON */ /*-------------------------------- PLL Configuration -----------------------*/ /* Check the parameters */ assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) 8000e56: 687b ldr r3, [r7, #4] 8000e58: 69db ldr r3, [r3, #28] 8000e5a: 2b00 cmp r3, #0 8000e5c: f000 8087 beq.w 8000f6e { /* Check if the PLL is used as system clock or not */ if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) 8000e60: 4b36 ldr r3, [pc, #216] ; (8000f3c ) 8000e62: 685b ldr r3, [r3, #4] 8000e64: f003 030c and.w r3, r3, #12 8000e68: 2b08 cmp r3, #8 8000e6a: d061 beq.n 8000f30 { if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) 8000e6c: 687b ldr r3, [r7, #4] 8000e6e: 69db ldr r3, [r3, #28] 8000e70: 2b02 cmp r3, #2 8000e72: d146 bne.n 8000f02 /* Check the parameters */ assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource)); assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL)); /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 8000e74: 4b33 ldr r3, [pc, #204] ; (8000f44 ) 8000e76: 2200 movs r2, #0 8000e78: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8000e7a: f7ff fb1f bl 80004bc 8000e7e: 6138 str r0, [r7, #16] /* Wait till PLL is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 8000e80: e008 b.n 8000e94 { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 8000e82: f7ff fb1b bl 80004bc 8000e86: 4602 mov r2, r0 8000e88: 693b ldr r3, [r7, #16] 8000e8a: 1ad3 subs r3, r2, r3 8000e8c: 2b02 cmp r3, #2 8000e8e: d901 bls.n 8000e94 { return HAL_TIMEOUT; 8000e90: 2303 movs r3, #3 8000e92: e06d b.n 8000f70 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 8000e94: 4b29 ldr r3, [pc, #164] ; (8000f3c ) 8000e96: 681b ldr r3, [r3, #0] 8000e98: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 8000e9c: 2b00 cmp r3, #0 8000e9e: d1f0 bne.n 8000e82 } } /* Configure the HSE prediv factor --------------------------------*/ /* It can be written only when the PLL is disabled. Not used in PLL source is different than HSE */ if (RCC_OscInitStruct->PLL.PLLSource == RCC_PLLSOURCE_HSE) 8000ea0: 687b ldr r3, [r7, #4] 8000ea2: 6a1b ldr r3, [r3, #32] 8000ea4: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 8000ea8: d108 bne.n 8000ebc /* Set PREDIV1 source */ SET_BIT(RCC->CFGR2, RCC_OscInitStruct->Prediv1Source); #endif /* RCC_CFGR2_PREDIV1SRC */ /* Set PREDIV1 Value */ __HAL_RCC_HSE_PREDIV_CONFIG(RCC_OscInitStruct->HSEPredivValue); 8000eaa: 4b24 ldr r3, [pc, #144] ; (8000f3c ) 8000eac: 685b ldr r3, [r3, #4] 8000eae: f423 3200 bic.w r2, r3, #131072 ; 0x20000 8000eb2: 687b ldr r3, [r7, #4] 8000eb4: 689b ldr r3, [r3, #8] 8000eb6: 4921 ldr r1, [pc, #132] ; (8000f3c ) 8000eb8: 4313 orrs r3, r2 8000eba: 604b str r3, [r1, #4] } /* Configure the main PLL clock source and multiplication factors. */ __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, 8000ebc: 4b1f ldr r3, [pc, #124] ; (8000f3c ) 8000ebe: 685b ldr r3, [r3, #4] 8000ec0: f423 1274 bic.w r2, r3, #3997696 ; 0x3d0000 8000ec4: 687b ldr r3, [r7, #4] 8000ec6: 6a19 ldr r1, [r3, #32] 8000ec8: 687b ldr r3, [r7, #4] 8000eca: 6a5b ldr r3, [r3, #36] ; 0x24 8000ecc: 430b orrs r3, r1 8000ece: 491b ldr r1, [pc, #108] ; (8000f3c ) 8000ed0: 4313 orrs r3, r2 8000ed2: 604b str r3, [r1, #4] RCC_OscInitStruct->PLL.PLLMUL); /* Enable the main PLL. */ __HAL_RCC_PLL_ENABLE(); 8000ed4: 4b1b ldr r3, [pc, #108] ; (8000f44 ) 8000ed6: 2201 movs r2, #1 8000ed8: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8000eda: f7ff faef bl 80004bc 8000ede: 6138 str r0, [r7, #16] /* Wait till PLL is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 8000ee0: e008 b.n 8000ef4 { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 8000ee2: f7ff faeb bl 80004bc 8000ee6: 4602 mov r2, r0 8000ee8: 693b ldr r3, [r7, #16] 8000eea: 1ad3 subs r3, r2, r3 8000eec: 2b02 cmp r3, #2 8000eee: d901 bls.n 8000ef4 { return HAL_TIMEOUT; 8000ef0: 2303 movs r3, #3 8000ef2: e03d b.n 8000f70 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 8000ef4: 4b11 ldr r3, [pc, #68] ; (8000f3c ) 8000ef6: 681b ldr r3, [r3, #0] 8000ef8: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 8000efc: 2b00 cmp r3, #0 8000efe: d0f0 beq.n 8000ee2 8000f00: e035 b.n 8000f6e } } else { /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 8000f02: 4b10 ldr r3, [pc, #64] ; (8000f44 ) 8000f04: 2200 movs r2, #0 8000f06: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8000f08: f7ff fad8 bl 80004bc 8000f0c: 6138 str r0, [r7, #16] /* Wait till PLL is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 8000f0e: e008 b.n 8000f22 { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 8000f10: f7ff fad4 bl 80004bc 8000f14: 4602 mov r2, r0 8000f16: 693b ldr r3, [r7, #16] 8000f18: 1ad3 subs r3, r2, r3 8000f1a: 2b02 cmp r3, #2 8000f1c: d901 bls.n 8000f22 { return HAL_TIMEOUT; 8000f1e: 2303 movs r3, #3 8000f20: e026 b.n 8000f70 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 8000f22: 4b06 ldr r3, [pc, #24] ; (8000f3c ) 8000f24: 681b ldr r3, [r3, #0] 8000f26: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 8000f2a: 2b00 cmp r3, #0 8000f2c: d1f0 bne.n 8000f10 8000f2e: e01e b.n 8000f6e } } else { /* Check if there is a request to disable the PLL used as System clock source */ if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) 8000f30: 687b ldr r3, [r7, #4] 8000f32: 69db ldr r3, [r3, #28] 8000f34: 2b01 cmp r3, #1 8000f36: d107 bne.n 8000f48 { return HAL_ERROR; 8000f38: 2301 movs r3, #1 8000f3a: e019 b.n 8000f70 8000f3c: 40021000 .word 0x40021000 8000f40: 40007000 .word 0x40007000 8000f44: 42420060 .word 0x42420060 } else { /* Do not return HAL_ERROR if request repeats the current configuration */ pll_config = RCC->CFGR; 8000f48: 4b0b ldr r3, [pc, #44] ; (8000f78 ) 8000f4a: 685b ldr r3, [r3, #4] 8000f4c: 60fb str r3, [r7, #12] if ((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 8000f4e: 68fb ldr r3, [r7, #12] 8000f50: f403 3280 and.w r2, r3, #65536 ; 0x10000 8000f54: 687b ldr r3, [r7, #4] 8000f56: 6a1b ldr r3, [r3, #32] 8000f58: 429a cmp r2, r3 8000f5a: d106 bne.n 8000f6a (READ_BIT(pll_config, RCC_CFGR_PLLMULL) != RCC_OscInitStruct->PLL.PLLMUL)) 8000f5c: 68fb ldr r3, [r7, #12] 8000f5e: f403 1270 and.w r2, r3, #3932160 ; 0x3c0000 8000f62: 687b ldr r3, [r7, #4] 8000f64: 6a5b ldr r3, [r3, #36] ; 0x24 if ((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 8000f66: 429a cmp r2, r3 8000f68: d001 beq.n 8000f6e { return HAL_ERROR; 8000f6a: 2301 movs r3, #1 8000f6c: e000 b.n 8000f70 } } } } return HAL_OK; 8000f6e: 2300 movs r3, #0 } 8000f70: 4618 mov r0, r3 8000f72: 3718 adds r7, #24 8000f74: 46bd mov sp, r7 8000f76: bd80 pop {r7, pc} 8000f78: 40021000 .word 0x40021000 08000f7c : * You can use @ref HAL_RCC_GetClockConfig() function to know which clock is * currently used as system clock source. * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) { 8000f7c: b580 push {r7, lr} 8000f7e: b084 sub sp, #16 8000f80: af00 add r7, sp, #0 8000f82: 6078 str r0, [r7, #4] 8000f84: 6039 str r1, [r7, #0] uint32_t tickstart; /* Check Null pointer */ if (RCC_ClkInitStruct == NULL) 8000f86: 687b ldr r3, [r7, #4] 8000f88: 2b00 cmp r3, #0 8000f8a: d101 bne.n 8000f90 { return HAL_ERROR; 8000f8c: 2301 movs r3, #1 8000f8e: e0d0 b.n 8001132 must be correctly programmed according to the frequency of the CPU clock (HCLK) of the device. */ #if defined(FLASH_ACR_LATENCY) /* Increasing the number of wait states because of higher CPU frequency */ if (FLatency > __HAL_FLASH_GET_LATENCY()) 8000f90: 4b6a ldr r3, [pc, #424] ; (800113c ) 8000f92: 681b ldr r3, [r3, #0] 8000f94: f003 0307 and.w r3, r3, #7 8000f98: 683a ldr r2, [r7, #0] 8000f9a: 429a cmp r2, r3 8000f9c: d910 bls.n 8000fc0 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 8000f9e: 4b67 ldr r3, [pc, #412] ; (800113c ) 8000fa0: 681b ldr r3, [r3, #0] 8000fa2: f023 0207 bic.w r2, r3, #7 8000fa6: 4965 ldr r1, [pc, #404] ; (800113c ) 8000fa8: 683b ldr r3, [r7, #0] 8000faa: 4313 orrs r3, r2 8000fac: 600b str r3, [r1, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if (__HAL_FLASH_GET_LATENCY() != FLatency) 8000fae: 4b63 ldr r3, [pc, #396] ; (800113c ) 8000fb0: 681b ldr r3, [r3, #0] 8000fb2: f003 0307 and.w r3, r3, #7 8000fb6: 683a ldr r2, [r7, #0] 8000fb8: 429a cmp r2, r3 8000fba: d001 beq.n 8000fc0 { return HAL_ERROR; 8000fbc: 2301 movs r3, #1 8000fbe: e0b8 b.n 8001132 } } #endif /* FLASH_ACR_LATENCY */ /*-------------------------- HCLK Configuration --------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) 8000fc0: 687b ldr r3, [r7, #4] 8000fc2: 681b ldr r3, [r3, #0] 8000fc4: f003 0302 and.w r3, r3, #2 8000fc8: 2b00 cmp r3, #0 8000fca: d020 beq.n 800100e { /* Set the highest APBx dividers in order to ensure that we do not go through a non-spec phase whatever we decrease or increase HCLK. */ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 8000fcc: 687b ldr r3, [r7, #4] 8000fce: 681b ldr r3, [r3, #0] 8000fd0: f003 0304 and.w r3, r3, #4 8000fd4: 2b00 cmp r3, #0 8000fd6: d005 beq.n 8000fe4 { MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16); 8000fd8: 4b59 ldr r3, [pc, #356] ; (8001140 ) 8000fda: 685b ldr r3, [r3, #4] 8000fdc: 4a58 ldr r2, [pc, #352] ; (8001140 ) 8000fde: f443 63e0 orr.w r3, r3, #1792 ; 0x700 8000fe2: 6053 str r3, [r2, #4] } if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 8000fe4: 687b ldr r3, [r7, #4] 8000fe6: 681b ldr r3, [r3, #0] 8000fe8: f003 0308 and.w r3, r3, #8 8000fec: 2b00 cmp r3, #0 8000fee: d005 beq.n 8000ffc { MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3)); 8000ff0: 4b53 ldr r3, [pc, #332] ; (8001140 ) 8000ff2: 685b ldr r3, [r3, #4] 8000ff4: 4a52 ldr r2, [pc, #328] ; (8001140 ) 8000ff6: f443 5360 orr.w r3, r3, #14336 ; 0x3800 8000ffa: 6053 str r3, [r2, #4] } /* Set the new HCLK clock divider */ assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); 8000ffc: 4b50 ldr r3, [pc, #320] ; (8001140 ) 8000ffe: 685b ldr r3, [r3, #4] 8001000: f023 02f0 bic.w r2, r3, #240 ; 0xf0 8001004: 687b ldr r3, [r7, #4] 8001006: 689b ldr r3, [r3, #8] 8001008: 494d ldr r1, [pc, #308] ; (8001140 ) 800100a: 4313 orrs r3, r2 800100c: 604b str r3, [r1, #4] } /*------------------------- SYSCLK Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) 800100e: 687b ldr r3, [r7, #4] 8001010: 681b ldr r3, [r3, #0] 8001012: f003 0301 and.w r3, r3, #1 8001016: 2b00 cmp r3, #0 8001018: d040 beq.n 800109c { assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); /* HSE is selected as System Clock Source */ if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) 800101a: 687b ldr r3, [r7, #4] 800101c: 685b ldr r3, [r3, #4] 800101e: 2b01 cmp r3, #1 8001020: d107 bne.n 8001032 { /* Check the HSE ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 8001022: 4b47 ldr r3, [pc, #284] ; (8001140 ) 8001024: 681b ldr r3, [r3, #0] 8001026: f403 3300 and.w r3, r3, #131072 ; 0x20000 800102a: 2b00 cmp r3, #0 800102c: d115 bne.n 800105a { return HAL_ERROR; 800102e: 2301 movs r3, #1 8001030: e07f b.n 8001132 } } /* PLL is selected as System Clock Source */ else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) 8001032: 687b ldr r3, [r7, #4] 8001034: 685b ldr r3, [r3, #4] 8001036: 2b02 cmp r3, #2 8001038: d107 bne.n 800104a { /* Check the PLL ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 800103a: 4b41 ldr r3, [pc, #260] ; (8001140 ) 800103c: 681b ldr r3, [r3, #0] 800103e: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 8001042: 2b00 cmp r3, #0 8001044: d109 bne.n 800105a { return HAL_ERROR; 8001046: 2301 movs r3, #1 8001048: e073 b.n 8001132 } /* HSI is selected as System Clock Source */ else { /* Check the HSI ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 800104a: 4b3d ldr r3, [pc, #244] ; (8001140 ) 800104c: 681b ldr r3, [r3, #0] 800104e: f003 0302 and.w r3, r3, #2 8001052: 2b00 cmp r3, #0 8001054: d101 bne.n 800105a { return HAL_ERROR; 8001056: 2301 movs r3, #1 8001058: e06b b.n 8001132 } } __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource); 800105a: 4b39 ldr r3, [pc, #228] ; (8001140 ) 800105c: 685b ldr r3, [r3, #4] 800105e: f023 0203 bic.w r2, r3, #3 8001062: 687b ldr r3, [r7, #4] 8001064: 685b ldr r3, [r3, #4] 8001066: 4936 ldr r1, [pc, #216] ; (8001140 ) 8001068: 4313 orrs r3, r2 800106a: 604b str r3, [r1, #4] /* Get Start Tick */ tickstart = HAL_GetTick(); 800106c: f7ff fa26 bl 80004bc 8001070: 60f8 str r0, [r7, #12] while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 8001072: e00a b.n 800108a { if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) 8001074: f7ff fa22 bl 80004bc 8001078: 4602 mov r2, r0 800107a: 68fb ldr r3, [r7, #12] 800107c: 1ad3 subs r3, r2, r3 800107e: f241 3288 movw r2, #5000 ; 0x1388 8001082: 4293 cmp r3, r2 8001084: d901 bls.n 800108a { return HAL_TIMEOUT; 8001086: 2303 movs r3, #3 8001088: e053 b.n 8001132 while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 800108a: 4b2d ldr r3, [pc, #180] ; (8001140 ) 800108c: 685b ldr r3, [r3, #4] 800108e: f003 020c and.w r2, r3, #12 8001092: 687b ldr r3, [r7, #4] 8001094: 685b ldr r3, [r3, #4] 8001096: 009b lsls r3, r3, #2 8001098: 429a cmp r2, r3 800109a: d1eb bne.n 8001074 } } #if defined(FLASH_ACR_LATENCY) /* Decreasing the number of wait states because of lower CPU frequency */ if (FLatency < __HAL_FLASH_GET_LATENCY()) 800109c: 4b27 ldr r3, [pc, #156] ; (800113c ) 800109e: 681b ldr r3, [r3, #0] 80010a0: f003 0307 and.w r3, r3, #7 80010a4: 683a ldr r2, [r7, #0] 80010a6: 429a cmp r2, r3 80010a8: d210 bcs.n 80010cc { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 80010aa: 4b24 ldr r3, [pc, #144] ; (800113c ) 80010ac: 681b ldr r3, [r3, #0] 80010ae: f023 0207 bic.w r2, r3, #7 80010b2: 4922 ldr r1, [pc, #136] ; (800113c ) 80010b4: 683b ldr r3, [r7, #0] 80010b6: 4313 orrs r3, r2 80010b8: 600b str r3, [r1, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if (__HAL_FLASH_GET_LATENCY() != FLatency) 80010ba: 4b20 ldr r3, [pc, #128] ; (800113c ) 80010bc: 681b ldr r3, [r3, #0] 80010be: f003 0307 and.w r3, r3, #7 80010c2: 683a ldr r2, [r7, #0] 80010c4: 429a cmp r2, r3 80010c6: d001 beq.n 80010cc { return HAL_ERROR; 80010c8: 2301 movs r3, #1 80010ca: e032 b.n 8001132 } } #endif /* FLASH_ACR_LATENCY */ /*-------------------------- PCLK1 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 80010cc: 687b ldr r3, [r7, #4] 80010ce: 681b ldr r3, [r3, #0] 80010d0: f003 0304 and.w r3, r3, #4 80010d4: 2b00 cmp r3, #0 80010d6: d008 beq.n 80010ea { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider); 80010d8: 4b19 ldr r3, [pc, #100] ; (8001140 ) 80010da: 685b ldr r3, [r3, #4] 80010dc: f423 62e0 bic.w r2, r3, #1792 ; 0x700 80010e0: 687b ldr r3, [r7, #4] 80010e2: 68db ldr r3, [r3, #12] 80010e4: 4916 ldr r1, [pc, #88] ; (8001140 ) 80010e6: 4313 orrs r3, r2 80010e8: 604b str r3, [r1, #4] } /*-------------------------- PCLK2 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 80010ea: 687b ldr r3, [r7, #4] 80010ec: 681b ldr r3, [r3, #0] 80010ee: f003 0308 and.w r3, r3, #8 80010f2: 2b00 cmp r3, #0 80010f4: d009 beq.n 800110a { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3)); 80010f6: 4b12 ldr r3, [pc, #72] ; (8001140 ) 80010f8: 685b ldr r3, [r3, #4] 80010fa: f423 5260 bic.w r2, r3, #14336 ; 0x3800 80010fe: 687b ldr r3, [r7, #4] 8001100: 691b ldr r3, [r3, #16] 8001102: 00db lsls r3, r3, #3 8001104: 490e ldr r1, [pc, #56] ; (8001140 ) 8001106: 4313 orrs r3, r2 8001108: 604b str r3, [r1, #4] } /* Update the SystemCoreClock global variable */ SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]; 800110a: f000 f821 bl 8001150 800110e: 4602 mov r2, r0 8001110: 4b0b ldr r3, [pc, #44] ; (8001140 ) 8001112: 685b ldr r3, [r3, #4] 8001114: 091b lsrs r3, r3, #4 8001116: f003 030f and.w r3, r3, #15 800111a: 490a ldr r1, [pc, #40] ; (8001144 ) 800111c: 5ccb ldrb r3, [r1, r3] 800111e: fa22 f303 lsr.w r3, r2, r3 8001122: 4a09 ldr r2, [pc, #36] ; (8001148 ) 8001124: 6013 str r3, [r2, #0] /* Configure the source of time base considering new system clocks settings*/ HAL_InitTick(uwTickPrio); 8001126: 4b09 ldr r3, [pc, #36] ; (800114c ) 8001128: 681b ldr r3, [r3, #0] 800112a: 4618 mov r0, r3 800112c: f7ff f984 bl 8000438 return HAL_OK; 8001130: 2300 movs r3, #0 } 8001132: 4618 mov r0, r3 8001134: 3710 adds r7, #16 8001136: 46bd mov sp, r7 8001138: bd80 pop {r7, pc} 800113a: bf00 nop 800113c: 40022000 .word 0x40022000 8001140: 40021000 .word 0x40021000 8001144: 080012c8 .word 0x080012c8 8001148: 20000000 .word 0x20000000 800114c: 20000004 .word 0x20000004 08001150 : * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect. * * @retval SYSCLK frequency */ uint32_t HAL_RCC_GetSysClockFreq(void) { 8001150: b490 push {r4, r7} 8001152: b08a sub sp, #40 ; 0x28 8001154: af00 add r7, sp, #0 #if defined(RCC_CFGR2_PREDIV1SRC) const uint8_t aPLLMULFactorTable[14] = {0, 0, 4, 5, 6, 7, 8, 9, 0, 0, 0, 0, 0, 13}; const uint8_t aPredivFactorTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}; #else const uint8_t aPLLMULFactorTable[16] = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16}; 8001156: 4b29 ldr r3, [pc, #164] ; (80011fc ) 8001158: 1d3c adds r4, r7, #4 800115a: cb0f ldmia r3, {r0, r1, r2, r3} 800115c: e884 000f stmia.w r4, {r0, r1, r2, r3} #if defined(RCC_CFGR2_PREDIV1) const uint8_t aPredivFactorTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}; #else const uint8_t aPredivFactorTable[2] = {1, 2}; 8001160: f240 2301 movw r3, #513 ; 0x201 8001164: 803b strh r3, [r7, #0] #endif /*RCC_CFGR2_PREDIV1*/ #endif uint32_t tmpreg = 0U, prediv = 0U, pllclk = 0U, pllmul = 0U; 8001166: 2300 movs r3, #0 8001168: 61fb str r3, [r7, #28] 800116a: 2300 movs r3, #0 800116c: 61bb str r3, [r7, #24] 800116e: 2300 movs r3, #0 8001170: 627b str r3, [r7, #36] ; 0x24 8001172: 2300 movs r3, #0 8001174: 617b str r3, [r7, #20] uint32_t sysclockfreq = 0U; 8001176: 2300 movs r3, #0 8001178: 623b str r3, [r7, #32] #if defined(RCC_CFGR2_PREDIV1SRC) uint32_t prediv2 = 0U, pll2mul = 0U; #endif /*RCC_CFGR2_PREDIV1SRC*/ tmpreg = RCC->CFGR; 800117a: 4b21 ldr r3, [pc, #132] ; (8001200 ) 800117c: 685b ldr r3, [r3, #4] 800117e: 61fb str r3, [r7, #28] /* Get SYSCLK source -------------------------------------------------------*/ switch (tmpreg & RCC_CFGR_SWS) 8001180: 69fb ldr r3, [r7, #28] 8001182: f003 030c and.w r3, r3, #12 8001186: 2b04 cmp r3, #4 8001188: d002 beq.n 8001190 800118a: 2b08 cmp r3, #8 800118c: d003 beq.n 8001196 800118e: e02b b.n 80011e8 { case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */ { sysclockfreq = HSE_VALUE; 8001190: 4b1c ldr r3, [pc, #112] ; (8001204 ) 8001192: 623b str r3, [r7, #32] break; 8001194: e02b b.n 80011ee } case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */ { pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos]; 8001196: 69fb ldr r3, [r7, #28] 8001198: 0c9b lsrs r3, r3, #18 800119a: f003 030f and.w r3, r3, #15 800119e: 3328 adds r3, #40 ; 0x28 80011a0: 443b add r3, r7 80011a2: f813 3c24 ldrb.w r3, [r3, #-36] 80011a6: 617b str r3, [r7, #20] if ((tmpreg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2) 80011a8: 69fb ldr r3, [r7, #28] 80011aa: f403 3380 and.w r3, r3, #65536 ; 0x10000 80011ae: 2b00 cmp r3, #0 80011b0: d012 beq.n 80011d8 { #if defined(RCC_CFGR2_PREDIV1) prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> RCC_CFGR2_PREDIV1_Pos]; #else prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos]; 80011b2: 4b13 ldr r3, [pc, #76] ; (8001200 ) 80011b4: 685b ldr r3, [r3, #4] 80011b6: 0c5b lsrs r3, r3, #17 80011b8: f003 0301 and.w r3, r3, #1 80011bc: 3328 adds r3, #40 ; 0x28 80011be: 443b add r3, r7 80011c0: f813 3c28 ldrb.w r3, [r3, #-40] 80011c4: 61bb str r3, [r7, #24] { pllclk = pllclk / 2; } #else /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */ pllclk = (uint32_t)((HSE_VALUE * pllmul) / prediv); 80011c6: 697b ldr r3, [r7, #20] 80011c8: 4a0e ldr r2, [pc, #56] ; (8001204 ) 80011ca: fb03 f202 mul.w r2, r3, r2 80011ce: 69bb ldr r3, [r7, #24] 80011d0: fbb2 f3f3 udiv r3, r2, r3 80011d4: 627b str r3, [r7, #36] ; 0x24 80011d6: e004 b.n 80011e2 #endif /*RCC_CFGR2_PREDIV1SRC*/ } else { /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */ pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul); 80011d8: 697b ldr r3, [r7, #20] 80011da: 4a0b ldr r2, [pc, #44] ; (8001208 ) 80011dc: fb02 f303 mul.w r3, r2, r3 80011e0: 627b str r3, [r7, #36] ; 0x24 } sysclockfreq = pllclk; 80011e2: 6a7b ldr r3, [r7, #36] ; 0x24 80011e4: 623b str r3, [r7, #32] break; 80011e6: e002 b.n 80011ee } case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */ default: /* HSI used as system clock */ { sysclockfreq = HSI_VALUE; 80011e8: 4b06 ldr r3, [pc, #24] ; (8001204 ) 80011ea: 623b str r3, [r7, #32] break; 80011ec: bf00 nop } } return sysclockfreq; 80011ee: 6a3b ldr r3, [r7, #32] } 80011f0: 4618 mov r0, r3 80011f2: 3728 adds r7, #40 ; 0x28 80011f4: 46bd mov sp, r7 80011f6: bc90 pop {r4, r7} 80011f8: 4770 bx lr 80011fa: bf00 nop 80011fc: 080012b8 .word 0x080012b8 8001200: 40021000 .word 0x40021000 8001204: 007a1200 .word 0x007a1200 8001208: 003d0900 .word 0x003d0900 0800120c : * @brief This function provides delay (in milliseconds) based on CPU cycles method. * @param mdelay: specifies the delay time length, in milliseconds. * @retval None */ static void RCC_Delay(uint32_t mdelay) { 800120c: b480 push {r7} 800120e: b085 sub sp, #20 8001210: af00 add r7, sp, #0 8001212: 6078 str r0, [r7, #4] __IO uint32_t Delay = mdelay * (SystemCoreClock / 8U / 1000U); 8001214: 4b0a ldr r3, [pc, #40] ; (8001240 ) 8001216: 681b ldr r3, [r3, #0] 8001218: 4a0a ldr r2, [pc, #40] ; (8001244 ) 800121a: fba2 2303 umull r2, r3, r2, r3 800121e: 0a5b lsrs r3, r3, #9 8001220: 687a ldr r2, [r7, #4] 8001222: fb02 f303 mul.w r3, r2, r3 8001226: 60fb str r3, [r7, #12] do { __NOP(); 8001228: bf00 nop } while (Delay --); 800122a: 68fb ldr r3, [r7, #12] 800122c: 1e5a subs r2, r3, #1 800122e: 60fa str r2, [r7, #12] 8001230: 2b00 cmp r3, #0 8001232: d1f9 bne.n 8001228 } 8001234: bf00 nop 8001236: bf00 nop 8001238: 3714 adds r7, #20 800123a: 46bd mov sp, r7 800123c: bc80 pop {r7} 800123e: 4770 bx lr 8001240: 20000000 .word 0x20000000 8001244: 10624dd3 .word 0x10624dd3 08001248 <__libc_init_array>: 8001248: b570 push {r4, r5, r6, lr} 800124a: 2600 movs r6, #0 800124c: 4d0c ldr r5, [pc, #48] ; (8001280 <__libc_init_array+0x38>) 800124e: 4c0d ldr r4, [pc, #52] ; (8001284 <__libc_init_array+0x3c>) 8001250: 1b64 subs r4, r4, r5 8001252: 10a4 asrs r4, r4, #2 8001254: 42a6 cmp r6, r4 8001256: d109 bne.n 800126c <__libc_init_array+0x24> 8001258: f000 f822 bl 80012a0 <_init> 800125c: 2600 movs r6, #0 800125e: 4d0a ldr r5, [pc, #40] ; (8001288 <__libc_init_array+0x40>) 8001260: 4c0a ldr r4, [pc, #40] ; (800128c <__libc_init_array+0x44>) 8001262: 1b64 subs r4, r4, r5 8001264: 10a4 asrs r4, r4, #2 8001266: 42a6 cmp r6, r4 8001268: d105 bne.n 8001276 <__libc_init_array+0x2e> 800126a: bd70 pop {r4, r5, r6, pc} 800126c: f855 3b04 ldr.w r3, [r5], #4 8001270: 4798 blx r3 8001272: 3601 adds r6, #1 8001274: e7ee b.n 8001254 <__libc_init_array+0xc> 8001276: f855 3b04 ldr.w r3, [r5], #4 800127a: 4798 blx r3 800127c: 3601 adds r6, #1 800127e: e7f2 b.n 8001266 <__libc_init_array+0x1e> 8001280: 080012d8 .word 0x080012d8 8001284: 080012d8 .word 0x080012d8 8001288: 080012d8 .word 0x080012d8 800128c: 080012dc .word 0x080012dc 08001290 : 8001290: 4603 mov r3, r0 8001292: 4402 add r2, r0 8001294: 4293 cmp r3, r2 8001296: d100 bne.n 800129a 8001298: 4770 bx lr 800129a: f803 1b01 strb.w r1, [r3], #1 800129e: e7f9 b.n 8001294 080012a0 <_init>: 80012a0: b5f8 push {r3, r4, r5, r6, r7, lr} 80012a2: bf00 nop 80012a4: bcf8 pop {r3, r4, r5, r6, r7} 80012a6: bc08 pop {r3} 80012a8: 469e mov lr, r3 80012aa: 4770 bx lr 080012ac <_fini>: 80012ac: b5f8 push {r3, r4, r5, r6, r7, lr} 80012ae: bf00 nop 80012b0: bcf8 pop {r3, r4, r5, r6, r7} 80012b2: bc08 pop {r3} 80012b4: 469e mov lr, r3 80012b6: 4770 bx lr