: /** * @brief The application entry point. * @retval int */ int main(void) { 80001a0: b580 push {r7, lr} 80001a2: b090 sub sp, #64 ; 0x40 80001a4: af02 add r7, sp, #8 /* USER CODE END 1 */ /* MCU Configuration--------------------------------------------------------*/ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ HAL_Init(); 80001a6: f000 fa2d bl 8000604 /* USER CODE BEGIN Init */ /* USER CODE END Init */ /* Configure the system clock */ SystemClock_Config(); 80001aa: f000 f859 bl 8000260 /* USER CODE BEGIN SysInit */ /* USER CODE END SysInit */ /* Initialize all configured peripherals */ MX_GPIO_Init(); 80001ae: f7ff ffd5 bl 800015c MX_RTC_Init(); 80001b2: f000 f8ad bl 8000310 MX_USART2_UART_Init(); 80001b6: f000 f98b bl 80004d0 /* USER CODE END 2 */ /* Infinite loop */ /* USER CODE BEGIN WHILE */ uint8_t buf[50] = { 0 }; 80001ba: 2300 movs r3, #0 80001bc: 607b str r3, [r7, #4] 80001be: f107 0308 add.w r3, r7, #8 80001c2: 222e movs r2, #46 ; 0x2e 80001c4: 2100 movs r1, #0 80001c6: 4618 mov r0, r3 80001c8: f002 f87a bl 80022c0 RTC_TimeTypeDef currentTime; //存放获取到的时间 while (1) { HAL_RTC_GetTime(&hrtc, ¤tTime, RTC_FORMAT_BCD); //读取当前时间 80001cc: 463b mov r3, r7 80001ce: 2201 movs r2, #1 80001d0: 4619 mov r1, r3 80001d2: 4820 ldr r0, [pc, #128] ; (8000254 ) 80001d4: f001 fb36 bl 8001844 //打印时间 //注意：HAL_RTC_GetTime得到的是BCD码的格式，需�?/16*10+%16转换�?10进制数字 sprintf((char*) buf, "%02d:%02d:%02d\r\n", currentTime.Hours / 16 * 10 + currentTime.Hours % 16, 80001d8: 783b ldrb r3, [r7, #0] 80001da: 091b lsrs r3, r3, #4 80001dc: b2db uxtb r3, r3 80001de: 461a mov r2, r3 80001e0: 4613 mov r3, r2 80001e2: 009b lsls r3, r3, #2 80001e4: 4413 add r3, r2 80001e6: 005b lsls r3, r3, #1 80001e8: 461a mov r2, r3 80001ea: 783b ldrb r3, [r7, #0] 80001ec: f003 030f and.w r3, r3, #15 sprintf((char*) buf, "%02d:%02d:%02d\r\n", 80001f0: 441a add r2, r3 currentTime.Minutes / 16 * 10 + currentTime.Minutes % 16, 80001f2: 787b ldrb r3, [r7, #1] 80001f4: 091b lsrs r3, r3, #4 80001f6: b2db uxtb r3, r3 80001f8: 4619 mov r1, r3 80001fa: 460b mov r3, r1 80001fc: 009b lsls r3, r3, #2 80001fe: 440b add r3, r1 8000200: 005b lsls r3, r3, #1 8000202: 4619 mov r1, r3 8000204: 787b ldrb r3, [r7, #1] 8000206: f003 030f and.w r3, r3, #15 sprintf((char*) buf, "%02d:%02d:%02d\r\n", 800020a: 4419 add r1, r3 currentTime.Seconds / 16 * 10 + currentTime.Seconds % 16); 800020c: 78bb ldrb r3, [r7, #2] 800020e: 091b lsrs r3, r3, #4 8000210: b2db uxtb r3, r3 8000212: 4618 mov r0, r3 8000214: 4603 mov r3, r0 8000216: 009b lsls r3, r3, #2 8000218: 4403 add r3, r0 800021a: 005b lsls r3, r3, #1 800021c: 4618 mov r0, r3 800021e: 78bb ldrb r3, [r7, #2] 8000220: f003 030f and.w r3, r3, #15 sprintf((char*) buf, "%02d:%02d:%02d\r\n", 8000224: 4403 add r3, r0 8000226: 1d38 adds r0, r7, #4 8000228: 9300 str r3, [sp, #0] 800022a: 460b mov r3, r1 800022c: 490a ldr r1, [pc, #40] ; (8000258 ) 800022e: f002 f84f bl 80022d0 HAL_UART_Transmit(&huart2, buf, strlen((const char*) buf), 10); //串口输出 8000232: 1d3b adds r3, r7, #4 8000234: 4618 mov r0, r3 8000236: f7ff ff89 bl 800014c 800023a: 4603 mov r3, r0 800023c: b29a uxth r2, r3 800023e: 1d39 adds r1, r7, #4 8000240: 230a movs r3, #10 8000242: 4806 ldr r0, [pc, #24] ; (800025c ) 8000244: f001 fea7 bl 8001f96 HAL_Delay(1000); 8000248: f44f 707a mov.w r0, #1000 ; 0x3e8 800024c: f000 fa3c bl 80006c8 HAL_RTC_GetTime(&hrtc, ¤tTime, RTC_FORMAT_BCD); //读取当前时间 8000250: e7bc b.n 80001cc 8000252: bf00 nop 8000254: 2000008c .word 0x2000008c 8000258: 08002bdc .word 0x08002bdc 800025c: 200000a4 .word 0x200000a4 08000260 : /** * @brief System Clock Configuration * @retval None */ void SystemClock_Config(void) { 8000260: b580 push {r7, lr} 8000262: b094 sub sp, #80 ; 0x50 8000264: af00 add r7, sp, #0 RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 8000266: f107 0328 add.w r3, r7, #40 ; 0x28 800026a: 2228 movs r2, #40 ; 0x28 800026c: 2100 movs r1, #0 800026e: 4618 mov r0, r3 8000270: f002 f826 bl 80022c0 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 8000274: f107 0314 add.w r3, r7, #20 8000278: 2200 movs r2, #0 800027a: 601a str r2, [r3, #0] 800027c: 605a str r2, [r3, #4] 800027e: 609a str r2, [r3, #8] 8000280: 60da str r2, [r3, #12] 8000282: 611a str r2, [r3, #16] RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; 8000284: 1d3b adds r3, r7, #4 8000286: 2200 movs r2, #0 8000288: 601a str r2, [r3, #0] 800028a: 605a str r2, [r3, #4] 800028c: 609a str r2, [r3, #8] 800028e: 60da str r2, [r3, #12] /** Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI|RCC_OSCILLATORTYPE_LSE; 8000290: 2306 movs r3, #6 8000292: 62bb str r3, [r7, #40] ; 0x28 RCC_OscInitStruct.LSEState = RCC_LSE_ON; 8000294: 2301 movs r3, #1 8000296: 637b str r3, [r7, #52] ; 0x34 RCC_OscInitStruct.HSIState = RCC_HSI_ON; 8000298: 2301 movs r3, #1 800029a: 63bb str r3, [r7, #56] ; 0x38 RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; 800029c: 2310 movs r3, #16 800029e: 63fb str r3, [r7, #60] ; 0x3c RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; 80002a0: 2300 movs r3, #0 80002a2: 647b str r3, [r7, #68] ; 0x44 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 80002a4: f107 0328 add.w r3, r7, #40 ; 0x28 80002a8: 4618 mov r0, r3 80002aa: f000 fca5 bl 8000bf8 80002ae: 4603 mov r3, r0 80002b0: 2b00 cmp r3, #0 80002b2: d001 beq.n 80002b8 { Error_Handler(); 80002b4: f000 f827 bl 8000306 } /** Initializes the CPU, AHB and APB buses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK 80002b8: 230f movs r3, #15 80002ba: 617b str r3, [r7, #20] |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI; 80002bc: 2300 movs r3, #0 80002be: 61bb str r3, [r7, #24] RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; 80002c0: 2300 movs r3, #0 80002c2: 61fb str r3, [r7, #28] RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; 80002c4: 2300 movs r3, #0 80002c6: 623b str r3, [r7, #32] RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; 80002c8: 2300 movs r3, #0 80002ca: 627b str r3, [r7, #36] ; 0x24 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK) 80002cc: f107 0314 add.w r3, r7, #20 80002d0: 2100 movs r1, #0 80002d2: 4618 mov r0, r3 80002d4: f000 ff12 bl 80010fc 80002d8: 4603 mov r3, r0 80002da: 2b00 cmp r3, #0 80002dc: d001 beq.n 80002e2 { Error_Handler(); 80002de: f000 f812 bl 8000306 } PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_RTC; 80002e2: 2301 movs r3, #1 80002e4: 607b str r3, [r7, #4] PeriphClkInit.RTCClockSelection = RCC_RTCCLKSOURCE_LSE; 80002e6: f44f 7380 mov.w r3, #256 ; 0x100 80002ea: 60bb str r3, [r7, #8] if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) 80002ec: 1d3b adds r3, r7, #4 80002ee: 4618 mov r0, r3 80002f0: f001 f89c bl 800142c 80002f4: 4603 mov r3, r0 80002f6: 2b00 cmp r3, #0 80002f8: d001 beq.n 80002fe { Error_Handler(); 80002fa: f000 f804 bl 8000306 } } 80002fe: bf00 nop 8000300: 3750 adds r7, #80 ; 0x50 8000302: 46bd mov sp, r7 8000304: bd80 pop {r7, pc} 08000306 : /** * @brief This function is executed in case of error occurrence. * @retval None */ void Error_Handler(void) { 8000306: b480 push {r7} 8000308: af00 add r7, sp, #0 \details Disables IRQ interrupts by setting the I-bit in the CPSR. Can only be executed in Privileged modes. */ __STATIC_FORCEINLINE void __disable_irq(void) { __ASM volatile ("cpsid i" : : : "memory"); 800030a: b672 cpsid i } 800030c: bf00 nop /* USER CODE BEGIN Error_Handler_Debug */ /* User can add his own implementation to report the HAL error return state */ __disable_irq(); while (1) { 800030e: e7fe b.n 800030e 08000310 : /* USER CODE END 0 */ RTC_HandleTypeDef hrtc; /* RTC init function */ void MX_RTC_Init(void) { 8000310: b580 push {r7, lr} 8000312: b082 sub sp, #8 8000314: af00 add r7, sp, #0 /* USER CODE BEGIN RTC_Init 0 */ /* USER CODE END RTC_Init 0 */ RTC_TimeTypeDef sTime = { 0 }; 8000316: 1d3b adds r3, r7, #4 8000318: 2100 movs r1, #0 800031a: 460a mov r2, r1 800031c: 801a strh r2, [r3, #0] 800031e: 460a mov r2, r1 8000320: 709a strb r2, [r3, #2] RTC_DateTypeDef DateToUpdate = { 0 }; 8000322: 2300 movs r3, #0 8000324: 603b str r3, [r7, #0] /* USER CODE END RTC_Init 1 */ /** Initialize RTC Only */ hrtc.Instance = RTC; 8000326: 4b0b ldr r3, [pc, #44] ; (8000354 ) 8000328: 4a0b ldr r2, [pc, #44] ; (8000358 ) 800032a: 601a str r2, [r3, #0] hrtc.Init.AsynchPrediv = RTC_AUTO_1_SECOND; 800032c: 4b09 ldr r3, [pc, #36] ; (8000354 ) 800032e: f04f 32ff mov.w r2, #4294967295 8000332: 605a str r2, [r3, #4] hrtc.Init.OutPut = RTC_OUTPUTSOURCE_ALARM; 8000334: 4b07 ldr r3, [pc, #28] ; (8000354 ) 8000336: f44f 7280 mov.w r2, #256 ; 0x100 800033a: 609a str r2, [r3, #8] if (HAL_RTC_Init(&hrtc) != HAL_OK) { 800033c: 4805 ldr r0, [pc, #20] ; (8000354 ) 800033e: f001 f9eb bl 8001718 8000342: 4603 mov r3, r0 8000344: 2b00 cmp r3, #0 8000346: d001 beq.n 800034c Error_Handler(); 8000348: f7ff ffdd bl 8000306 } /* USER CODE BEGIN RTC_Init 2 */ /* USER CODE END RTC_Init 2 */ } 800034c: 3708 adds r7, #8 800034e: 46bd mov sp, r7 8000350: bd80 pop {r7, pc} 8000352: bf00 nop 8000354: 2000008c .word 0x2000008c 8000358: 40002800 .word 0x40002800 0800035c : void HAL_RTC_MspInit(RTC_HandleTypeDef *rtcHandle) { 800035c: b580 push {r7, lr} 800035e: b084 sub sp, #16 8000360: af00 add r7, sp, #0 8000362: 6078 str r0, [r7, #4] if (rtcHandle->Instance == RTC) { 8000364: 687b ldr r3, [r7, #4] 8000366: 681b ldr r3, [r3, #0] 8000368: 4a0b ldr r2, [pc, #44] ; (8000398 ) 800036a: 4293 cmp r3, r2 800036c: d110 bne.n 8000390 /* USER CODE BEGIN RTC_MspInit 0 */ /* USER CODE END RTC_MspInit 0 */ HAL_PWR_EnableBkUpAccess(); 800036e: f000 fc37 bl 8000be0 /* Enable BKP CLK enable for backup registers */ __HAL_RCC_BKP_CLK_ENABLE(); 8000372: 4b0a ldr r3, [pc, #40] ; (800039c ) 8000374: 69db ldr r3, [r3, #28] 8000376: 4a09 ldr r2, [pc, #36] ; (800039c ) 8000378: f043 6300 orr.w r3, r3, #134217728 ; 0x8000000 800037c: 61d3 str r3, [r2, #28] 800037e: 4b07 ldr r3, [pc, #28] ; (800039c ) 8000380: 69db ldr r3, [r3, #28] 8000382: f003 6300 and.w r3, r3, #134217728 ; 0x8000000 8000386: 60fb str r3, [r7, #12] 8000388: 68fb ldr r3, [r7, #12] /* RTC clock enable */ __HAL_RCC_RTC_ENABLE(); 800038a: 4b05 ldr r3, [pc, #20] ; (80003a0 ) 800038c: 2201 movs r2, #1 800038e: 601a str r2, [r3, #0] /* USER CODE BEGIN RTC_MspInit 1 */ /* USER CODE END RTC_MspInit 1 */ } } 8000390: bf00 nop 8000392: 3710 adds r7, #16 8000394: 46bd mov sp, r7 8000396: bd80 pop {r7, pc} 8000398: 40002800 .word 0x40002800 800039c: 40021000 .word 0x40021000 80003a0: 4242043c .word 0x4242043c 080003a4 : /* USER CODE END 0 */ /** * Initializes the Global MSP. */ void HAL_MspInit(void) { 80003a4: b480 push {r7} 80003a6: b085 sub sp, #20 80003a8: af00 add r7, sp, #0 /* USER CODE BEGIN MspInit 0 */ /* USER CODE END MspInit 0 */ __HAL_RCC_AFIO_CLK_ENABLE(); 80003aa: 4b15 ldr r3, [pc, #84] ; (8000400 ) 80003ac: 699b ldr r3, [r3, #24] 80003ae: 4a14 ldr r2, [pc, #80] ; (8000400 ) 80003b0: f043 0301 orr.w r3, r3, #1 80003b4: 6193 str r3, [r2, #24] 80003b6: 4b12 ldr r3, [pc, #72] ; (8000400 ) 80003b8: 699b ldr r3, [r3, #24] 80003ba: f003 0301 and.w r3, r3, #1 80003be: 60bb str r3, [r7, #8] 80003c0: 68bb ldr r3, [r7, #8] __HAL_RCC_PWR_CLK_ENABLE(); 80003c2: 4b0f ldr r3, [pc, #60] ; (8000400 ) 80003c4: 69db ldr r3, [r3, #28] 80003c6: 4a0e ldr r2, [pc, #56] ; (8000400 ) 80003c8: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 80003cc: 61d3 str r3, [r2, #28] 80003ce: 4b0c ldr r3, [pc, #48] ; (8000400 ) 80003d0: 69db ldr r3, [r3, #28] 80003d2: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 80003d6: 607b str r3, [r7, #4] 80003d8: 687b ldr r3, [r7, #4] /* System interrupt init*/ /** NOJTAG: JTAG-DP Disabled and SW-DP Enabled */ __HAL_AFIO_REMAP_SWJ_NOJTAG(); 80003da: 4b0a ldr r3, [pc, #40] ; (8000404 ) 80003dc: 685b ldr r3, [r3, #4] 80003de: 60fb str r3, [r7, #12] 80003e0: 68fb ldr r3, [r7, #12] 80003e2: f023 63e0 bic.w r3, r3, #117440512 ; 0x7000000 80003e6: 60fb str r3, [r7, #12] 80003e8: 68fb ldr r3, [r7, #12] 80003ea: f043 7300 orr.w r3, r3, #33554432 ; 0x2000000 80003ee: 60fb str r3, [r7, #12] 80003f0: 4a04 ldr r2, [pc, #16] ; (8000404 ) 80003f2: 68fb ldr r3, [r7, #12] 80003f4: 6053 str r3, [r2, #4] /* USER CODE BEGIN MspInit 1 */ /* USER CODE END MspInit 1 */ } 80003f6: bf00 nop 80003f8: 3714 adds r7, #20 80003fa: 46bd mov sp, r7 80003fc: bc80 pop {r7} 80003fe: 4770 bx lr 8000400: 40021000 .word 0x40021000 8000404: 40010000 .word 0x40010000 08000408 : /******************************************************************************/ /** * @brief This function handles Non maskable interrupt. */ void NMI_Handler(void) { 8000408: b480 push {r7} 800040a: af00 add r7, sp, #0 /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ /* USER CODE END NonMaskableInt_IRQn 0 */ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ while (1) 800040c: e7fe b.n 800040c 0800040e : /** * @brief This function handles Hard fault interrupt. */ void HardFault_Handler(void) { 800040e: b480 push {r7} 8000410: af00 add r7, sp, #0 /* USER CODE BEGIN HardFault_IRQn 0 */ /* USER CODE END HardFault_IRQn 0 */ while (1) 8000412: e7fe b.n 8000412 08000414 : /** * @brief This function handles Memory management fault. */ void MemManage_Handler(void) { 8000414: b480 push {r7} 8000416: af00 add r7, sp, #0 /* USER CODE BEGIN MemoryManagement_IRQn 0 */ /* USER CODE END MemoryManagement_IRQn 0 */ while (1) 8000418: e7fe b.n 8000418 0800041a : /** * @brief This function handles Prefetch fault, memory access fault. */ void BusFault_Handler(void) { 800041a: b480 push {r7} 800041c: af00 add r7, sp, #0 /* USER CODE BEGIN BusFault_IRQn 0 */ /* USER CODE END BusFault_IRQn 0 */ while (1) 800041e: e7fe b.n 800041e 08000420 : /** * @brief This function handles Undefined instruction or illegal state. */ void UsageFault_Handler(void) { 8000420: b480 push {r7} 8000422: af00 add r7, sp, #0 /* USER CODE BEGIN UsageFault_IRQn 0 */ /* USER CODE END UsageFault_IRQn 0 */ while (1) 8000424: e7fe b.n 8000424 08000426 : /** * @brief This function handles System service call via SWI instruction. */ void SVC_Handler(void) { 8000426: b480 push {r7} 8000428: af00 add r7, sp, #0 /* USER CODE END SVCall_IRQn 0 */ /* USER CODE BEGIN SVCall_IRQn 1 */ /* USER CODE END SVCall_IRQn 1 */ } 800042a: bf00 nop 800042c: 46bd mov sp, r7 800042e: bc80 pop {r7} 8000430: 4770 bx lr 08000432 : /** * @brief This function handles Debug monitor. */ void DebugMon_Handler(void) { 8000432: b480 push {r7} 8000434: af00 add r7, sp, #0 /* USER CODE END DebugMonitor_IRQn 0 */ /* USER CODE BEGIN DebugMonitor_IRQn 1 */ /* USER CODE END DebugMonitor_IRQn 1 */ } 8000436: bf00 nop 8000438: 46bd mov sp, r7 800043a: bc80 pop {r7} 800043c: 4770 bx lr 0800043e : /** * @brief This function handles Pendable request for system service. */ void PendSV_Handler(void) { 800043e: b480 push {r7} 8000440: af00 add r7, sp, #0 /* USER CODE END PendSV_IRQn 0 */ /* USER CODE BEGIN PendSV_IRQn 1 */ /* USER CODE END PendSV_IRQn 1 */ } 8000442: bf00 nop 8000444: 46bd mov sp, r7 8000446: bc80 pop {r7} 8000448: 4770 bx lr 0800044a : /** * @brief This function handles System tick timer. */ void SysTick_Handler(void) { 800044a: b580 push {r7, lr} 800044c: af00 add r7, sp, #0 /* USER CODE BEGIN SysTick_IRQn 0 */ /* USER CODE END SysTick_IRQn 0 */ HAL_IncTick(); 800044e: f000 f91f bl 8000690 /* USER CODE BEGIN SysTick_IRQn 1 */ /* USER CODE END SysTick_IRQn 1 */ } 8000452: bf00 nop 8000454: bd80 pop {r7, pc} ... 08000458 <_sbrk>: * * @param incr Memory size * @return Pointer to allocated memory */ void *_sbrk(ptrdiff_t incr) { 8000458: b580 push {r7, lr} 800045a: b086 sub sp, #24 800045c: af00 add r7, sp, #0 800045e: 6078 str r0, [r7, #4] extern uint8_t _end; /* Symbol defined in the linker script */ extern uint8_t _estack; /* Symbol defined in the linker script */ extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */ const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size; 8000460: 4a14 ldr r2, [pc, #80] ; (80004b4 <_sbrk+0x5c>) 8000462: 4b15 ldr r3, [pc, #84] ; (80004b8 <_sbrk+0x60>) 8000464: 1ad3 subs r3, r2, r3 8000466: 617b str r3, [r7, #20] const uint8_t *max_heap = (uint8_t *)stack_limit; 8000468: 697b ldr r3, [r7, #20] 800046a: 613b str r3, [r7, #16] uint8_t *prev_heap_end; /* Initialize heap end at first call */ if (NULL == __sbrk_heap_end) 800046c: 4b13 ldr r3, [pc, #76] ; (80004bc <_sbrk+0x64>) 800046e: 681b ldr r3, [r3, #0] 8000470: 2b00 cmp r3, #0 8000472: d102 bne.n 800047a <_sbrk+0x22> { __sbrk_heap_end = &_end; 8000474: 4b11 ldr r3, [pc, #68] ; (80004bc <_sbrk+0x64>) 8000476: 4a12 ldr r2, [pc, #72] ; (80004c0 <_sbrk+0x68>) 8000478: 601a str r2, [r3, #0] } /* Protect heap from growing into the reserved MSP stack */ if (__sbrk_heap_end + incr > max_heap) 800047a: 4b10 ldr r3, [pc, #64] ; (80004bc <_sbrk+0x64>) 800047c: 681a ldr r2, [r3, #0] 800047e: 687b ldr r3, [r7, #4] 8000480: 4413 add r3, r2 8000482: 693a ldr r2, [r7, #16] 8000484: 429a cmp r2, r3 8000486: d207 bcs.n 8000498 <_sbrk+0x40> { errno = ENOMEM; 8000488: f001 fef0 bl 800226c <__errno> 800048c: 4603 mov r3, r0 800048e: 220c movs r2, #12 8000490: 601a str r2, [r3, #0] return (void *)-1; 8000492: f04f 33ff mov.w r3, #4294967295 8000496: e009 b.n 80004ac <_sbrk+0x54> } prev_heap_end = __sbrk_heap_end; 8000498: 4b08 ldr r3, [pc, #32] ; (80004bc <_sbrk+0x64>) 800049a: 681b ldr r3, [r3, #0] 800049c: 60fb str r3, [r7, #12] __sbrk_heap_end += incr; 800049e: 4b07 ldr r3, [pc, #28] ; (80004bc <_sbrk+0x64>) 80004a0: 681a ldr r2, [r3, #0] 80004a2: 687b ldr r3, [r7, #4] 80004a4: 4413 add r3, r2 80004a6: 4a05 ldr r2, [pc, #20] ; (80004bc <_sbrk+0x64>) 80004a8: 6013 str r3, [r2, #0] return (void *)prev_heap_end; 80004aa: 68fb ldr r3, [r7, #12] } 80004ac: 4618 mov r0, r3 80004ae: 3718 adds r7, #24 80004b0: 46bd mov sp, r7 80004b2: bd80 pop {r7, pc} 80004b4: 20005000 .word 0x20005000 80004b8: 00000400 .word 0x00000400 80004bc: 200000a0 .word 0x200000a0 80004c0: 20000100 .word 0x20000100 080004c4 : * @note This function should be used only after reset. * @param None * @retval None */ void SystemInit (void) { 80004c4: b480 push {r7} 80004c6: af00 add r7, sp, #0 /* Configure the Vector Table location -------------------------------------*/ #if defined(USER_VECT_TAB_ADDRESS) SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ #endif /* USER_VECT_TAB_ADDRESS */ } 80004c8: bf00 nop 80004ca: 46bd mov sp, r7 80004cc: bc80 pop {r7} 80004ce: 4770 bx lr 080004d0 : UART_HandleTypeDef huart2; /* USART2 init function */ void MX_USART2_UART_Init(void) { 80004d0: b580 push {r7, lr} 80004d2: af00 add r7, sp, #0 /* USER CODE END USART2_Init 0 */ /* USER CODE BEGIN USART2_Init 1 */ /* USER CODE END USART2_Init 1 */ huart2.Instance = USART2; 80004d4: 4b11 ldr r3, [pc, #68] ; (800051c ) 80004d6: 4a12 ldr r2, [pc, #72] ; (8000520 ) 80004d8: 601a str r2, [r3, #0] huart2.Init.BaudRate = 115200; 80004da: 4b10 ldr r3, [pc, #64] ; (800051c ) 80004dc: f44f 32e1 mov.w r2, #115200 ; 0x1c200 80004e0: 605a str r2, [r3, #4] huart2.Init.WordLength = UART_WORDLENGTH_8B; 80004e2: 4b0e ldr r3, [pc, #56] ; (800051c ) 80004e4: 2200 movs r2, #0 80004e6: 609a str r2, [r3, #8] huart2.Init.StopBits = UART_STOPBITS_1; 80004e8: 4b0c ldr r3, [pc, #48] ; (800051c ) 80004ea: 2200 movs r2, #0 80004ec: 60da str r2, [r3, #12] huart2.Init.Parity = UART_PARITY_NONE; 80004ee: 4b0b ldr r3, [pc, #44] ; (800051c ) 80004f0: 2200 movs r2, #0 80004f2: 611a str r2, [r3, #16] huart2.Init.Mode = UART_MODE_TX_RX; 80004f4: 4b09 ldr r3, [pc, #36] ; (800051c ) 80004f6: 220c movs r2, #12 80004f8: 615a str r2, [r3, #20] huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE; 80004fa: 4b08 ldr r3, [pc, #32] ; (800051c ) 80004fc: 2200 movs r2, #0 80004fe: 619a str r2, [r3, #24] huart2.Init.OverSampling = UART_OVERSAMPLING_16; 8000500: 4b06 ldr r3, [pc, #24] ; (800051c ) 8000502: 2200 movs r2, #0 8000504: 61da str r2, [r3, #28] if (HAL_UART_Init(&huart2) != HAL_OK) 8000506: 4805 ldr r0, [pc, #20] ; (800051c ) 8000508: f001 fcf8 bl 8001efc 800050c: 4603 mov r3, r0 800050e: 2b00 cmp r3, #0 8000510: d001 beq.n 8000516 { Error_Handler(); 8000512: f7ff fef8 bl 8000306 } /* USER CODE BEGIN USART2_Init 2 */ /* USER CODE END USART2_Init 2 */ } 8000516: bf00 nop 8000518: bd80 pop {r7, pc} 800051a: bf00 nop 800051c: 200000a4 .word 0x200000a4 8000520: 40004400 .word 0x40004400 08000524 : void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle) { 8000524: b580 push {r7, lr} 8000526: b088 sub sp, #32 8000528: af00 add r7, sp, #0 800052a: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 800052c: f107 0310 add.w r3, r7, #16 8000530: 2200 movs r2, #0 8000532: 601a str r2, [r3, #0] 8000534: 605a str r2, [r3, #4] 8000536: 609a str r2, [r3, #8] 8000538: 60da str r2, [r3, #12] if(uartHandle->Instance==USART2) 800053a: 687b ldr r3, [r7, #4] 800053c: 681b ldr r3, [r3, #0] 800053e: 4a1b ldr r2, [pc, #108] ; (80005ac ) 8000540: 4293 cmp r3, r2 8000542: d12f bne.n 80005a4 { /* USER CODE BEGIN USART2_MspInit 0 */ /* USER CODE END USART2_MspInit 0 */ /* USART2 clock enable */ __HAL_RCC_USART2_CLK_ENABLE(); 8000544: 4b1a ldr r3, [pc, #104] ; (80005b0 ) 8000546: 69db ldr r3, [r3, #28] 8000548: 4a19 ldr r2, [pc, #100] ; (80005b0 ) 800054a: f443 3300 orr.w r3, r3, #131072 ; 0x20000 800054e: 61d3 str r3, [r2, #28] 8000550: 4b17 ldr r3, [pc, #92] ; (80005b0 ) 8000552: 69db ldr r3, [r3, #28] 8000554: f403 3300 and.w r3, r3, #131072 ; 0x20000 8000558: 60fb str r3, [r7, #12] 800055a: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOA_CLK_ENABLE(); 800055c: 4b14 ldr r3, [pc, #80] ; (80005b0 ) 800055e: 699b ldr r3, [r3, #24] 8000560: 4a13 ldr r2, [pc, #76] ; (80005b0 ) 8000562: f043 0304 orr.w r3, r3, #4 8000566: 6193 str r3, [r2, #24] 8000568: 4b11 ldr r3, [pc, #68] ; (80005b0 ) 800056a: 699b ldr r3, [r3, #24] 800056c: f003 0304 and.w r3, r3, #4 8000570: 60bb str r3, [r7, #8] 8000572: 68bb ldr r3, [r7, #8] /**USART2 GPIO Configuration PA2 ------> USART2_TX PA3 ------> USART2_RX */ GPIO_InitStruct.Pin = GPIO_PIN_2; 8000574: 2304 movs r3, #4 8000576: 613b str r3, [r7, #16] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8000578: 2302 movs r3, #2 800057a: 617b str r3, [r7, #20] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 800057c: 2303 movs r3, #3 800057e: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8000580: f107 0310 add.w r3, r7, #16 8000584: 4619 mov r1, r3 8000586: 480b ldr r0, [pc, #44] ; (80005b4 ) 8000588: f000 f9a6 bl 80008d8 GPIO_InitStruct.Pin = GPIO_PIN_3; 800058c: 2308 movs r3, #8 800058e: 613b str r3, [r7, #16] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 8000590: 2300 movs r3, #0 8000592: 617b str r3, [r7, #20] GPIO_InitStruct.Pull = GPIO_NOPULL; 8000594: 2300 movs r3, #0 8000596: 61bb str r3, [r7, #24] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8000598: f107 0310 add.w r3, r7, #16 800059c: 4619 mov r1, r3 800059e: 4805 ldr r0, [pc, #20] ; (80005b4 ) 80005a0: f000 f99a bl 80008d8 /* USER CODE BEGIN USART2_MspInit 1 */ /* USER CODE END USART2_MspInit 1 */ } } 80005a4: bf00 nop 80005a6: 3720 adds r7, #32 80005a8: 46bd mov sp, r7 80005aa: bd80 pop {r7, pc} 80005ac: 40004400 .word 0x40004400 80005b0: 40021000 .word 0x40021000 80005b4: 40010800 .word 0x40010800 080005b8 : .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata 80005b8: 480c ldr r0, [pc, #48] ; (80005ec ) ldr r1, =_edata 80005ba: 490d ldr r1, [pc, #52] ; (80005f0 ) ldr r2, =_sidata 80005bc: 4a0d ldr r2, [pc, #52] ; (80005f4 ) movs r3, #0 80005be: 2300 movs r3, #0 b LoopCopyDataInit 80005c0: e002 b.n 80005c8 080005c2 : CopyDataInit: ldr r4, [r2, r3] 80005c2: 58d4 ldr r4, [r2, r3] str r4, [r0, r3] 80005c4: 50c4 str r4, [r0, r3] adds r3, r3, #4 80005c6: 3304 adds r3, #4 080005c8 : LoopCopyDataInit: adds r4, r0, r3 80005c8: 18c4 adds r4, r0, r3 cmp r4, r1 80005ca: 428c cmp r4, r1 bcc CopyDataInit 80005cc: d3f9 bcc.n 80005c2 /* Zero fill the bss segment. */ ldr r2, =_sbss 80005ce: 4a0a ldr r2, [pc, #40] ; (80005f8 ) ldr r4, =_ebss 80005d0: 4c0a ldr r4, [pc, #40] ; (80005fc ) movs r3, #0 80005d2: 2300 movs r3, #0 b LoopFillZerobss 80005d4: e001 b.n 80005da 080005d6 : FillZerobss: str r3, [r2] 80005d6: 6013 str r3, [r2, #0] adds r2, r2, #4 80005d8: 3204 adds r2, #4 080005da : LoopFillZerobss: cmp r2, r4 80005da: 42a2 cmp r2, r4 bcc FillZerobss 80005dc: d3fb bcc.n 80005d6 /* Call the clock system intitialization function.*/ bl SystemInit 80005de: f7ff ff71 bl 80004c4 /* Call static constructors */ bl __libc_init_array 80005e2: f001 fe49 bl 8002278 <__libc_init_array> /* Call the application's entry point.*/ bl main 80005e6: f7ff fddb bl 80001a0

bx lr 80005ea: 4770 bx lr ldr r0, =_sdata 80005ec: 20000000 .word 0x20000000 ldr r1, =_edata 80005f0: 20000070 .word 0x20000070 ldr r2, =_sidata 80005f4: 08002c64 .word 0x08002c64 ldr r2, =_sbss 80005f8: 20000070 .word 0x20000070 ldr r4, =_ebss 80005fc: 200000fc .word 0x200000fc 08000600 : * @retval : None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop 8000600: e7fe b.n 8000600 ... 08000604 : * need to ensure that the SysTick time base is always set to 1 millisecond * to have correct HAL operation. * @retval HAL status */ HAL_StatusTypeDef HAL_Init(void) { 8000604: b580 push {r7, lr} 8000606: af00 add r7, sp, #0 defined(STM32F102x6) || defined(STM32F102xB) || \ defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || \ defined(STM32F105xC) || defined(STM32F107xC) /* Prefetch buffer is not available on value line devices */ __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); 8000608: 4b08 ldr r3, [pc, #32] ; (800062c ) 800060a: 681b ldr r3, [r3, #0] 800060c: 4a07 ldr r2, [pc, #28] ; (800062c ) 800060e: f043 0310 orr.w r3, r3, #16 8000612: 6013 str r3, [r2, #0] #endif #endif /* PREFETCH_ENABLE */ /* Set Interrupt Group Priority */ HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); 8000614: 2003 movs r0, #3 8000616: f000 f92b bl 8000870 /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ HAL_InitTick(TICK_INT_PRIORITY); 800061a: 200f movs r0, #15 800061c: f000 f808 bl 8000630 /* Init the low level hardware */ HAL_MspInit(); 8000620: f7ff fec0 bl 80003a4 /* Return function status */ return HAL_OK; 8000624: 2300 movs r3, #0 } 8000626: 4618 mov r0, r3 8000628: bd80 pop {r7, pc} 800062a: bf00 nop 800062c: 40022000 .word 0x40022000 08000630 : * implementation in user file. * @param TickPriority Tick interrupt priority. * @retval HAL status */ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { 8000630: b580 push {r7, lr} 8000632: b082 sub sp, #8 8000634: af00 add r7, sp, #0 8000636: 6078 str r0, [r7, #4] /* Configure the SysTick to have interrupt in 1ms time basis*/ if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U) 8000638: 4b12 ldr r3, [pc, #72] ; (8000684 ) 800063a: 681a ldr r2, [r3, #0] 800063c: 4b12 ldr r3, [pc, #72] ; (8000688 ) 800063e: 781b ldrb r3, [r3, #0] 8000640: 4619 mov r1, r3 8000642: f44f 737a mov.w r3, #1000 ; 0x3e8 8000646: fbb3 f3f1 udiv r3, r3, r1 800064a: fbb2 f3f3 udiv r3, r2, r3 800064e: 4618 mov r0, r3 8000650: f000 f935 bl 80008be 8000654: 4603 mov r3, r0 8000656: 2b00 cmp r3, #0 8000658: d001 beq.n 800065e { return HAL_ERROR; 800065a: 2301 movs r3, #1 800065c: e00e b.n 800067c } /* Configure the SysTick IRQ priority */ if (TickPriority < (1UL << __NVIC_PRIO_BITS)) 800065e: 687b ldr r3, [r7, #4] 8000660: 2b0f cmp r3, #15 8000662: d80a bhi.n 800067a { HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); 8000664: 2200 movs r2, #0 8000666: 6879 ldr r1, [r7, #4] 8000668: f04f 30ff mov.w r0, #4294967295 800066c: f000 f90b bl 8000886 uwTickPrio = TickPriority; 8000670: 4a06 ldr r2, [pc, #24] ; (800068c ) 8000672: 687b ldr r3, [r7, #4] 8000674: 6013 str r3, [r2, #0] { return HAL_ERROR; } /* Return function status */ return HAL_OK; 8000676: 2300 movs r3, #0 8000678: e000 b.n 800067c return HAL_ERROR; 800067a: 2301 movs r3, #1 } 800067c: 4618 mov r0, r3 800067e: 3708 adds r7, #8 8000680: 46bd mov sp, r7 8000682: bd80 pop {r7, pc} 8000684: 20000000 .word 0x20000000 8000688: 20000008 .word 0x20000008 800068c: 20000004 .word 0x20000004 08000690 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ __weak void HAL_IncTick(void) { 8000690: b480 push {r7} 8000692: af00 add r7, sp, #0 uwTick += uwTickFreq; 8000694: 4b05 ldr r3, [pc, #20] ; (80006ac ) 8000696: 781b ldrb r3, [r3, #0] 8000698: 461a mov r2, r3 800069a: 4b05 ldr r3, [pc, #20] ; (80006b0 ) 800069c: 681b ldr r3, [r3, #0] 800069e: 4413 add r3, r2 80006a0: 4a03 ldr r2, [pc, #12] ; (80006b0 ) 80006a2: 6013 str r3, [r2, #0] } 80006a4: bf00 nop 80006a6: 46bd mov sp, r7 80006a8: bc80 pop {r7} 80006aa: 4770 bx lr 80006ac: 20000008 .word 0x20000008 80006b0: 200000e8 .word 0x200000e8 080006b4 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval tick value */ __weak uint32_t HAL_GetTick(void) { 80006b4: b480 push {r7} 80006b6: af00 add r7, sp, #0 return uwTick; 80006b8: 4b02 ldr r3, [pc, #8] ; (80006c4 ) 80006ba: 681b ldr r3, [r3, #0] } 80006bc: 4618 mov r0, r3 80006be: 46bd mov sp, r7 80006c0: bc80 pop {r7} 80006c2: 4770 bx lr 80006c4: 200000e8 .word 0x200000e8 080006c8 : * implementations in user file. * @param Delay specifies the delay time length, in milliseconds. * @retval None */ __weak void HAL_Delay(uint32_t Delay) { 80006c8: b580 push {r7, lr} 80006ca: b084 sub sp, #16 80006cc: af00 add r7, sp, #0 80006ce: 6078 str r0, [r7, #4] uint32_t tickstart = HAL_GetTick(); 80006d0: f7ff fff0 bl 80006b4 80006d4: 60b8 str r0, [r7, #8] uint32_t wait = Delay; 80006d6: 687b ldr r3, [r7, #4] 80006d8: 60fb str r3, [r7, #12] /* Add a freq to guarantee minimum wait */ if (wait < HAL_MAX_DELAY) 80006da: 68fb ldr r3, [r7, #12] 80006dc: f1b3 3fff cmp.w r3, #4294967295 80006e0: d005 beq.n 80006ee { wait += (uint32_t)(uwTickFreq); 80006e2: 4b0a ldr r3, [pc, #40] ; (800070c ) 80006e4: 781b ldrb r3, [r3, #0] 80006e6: 461a mov r2, r3 80006e8: 68fb ldr r3, [r7, #12] 80006ea: 4413 add r3, r2 80006ec: 60fb str r3, [r7, #12] } while ((HAL_GetTick() - tickstart) < wait) 80006ee: bf00 nop 80006f0: f7ff ffe0 bl 80006b4 80006f4: 4602 mov r2, r0 80006f6: 68bb ldr r3, [r7, #8] 80006f8: 1ad3 subs r3, r2, r3 80006fa: 68fa ldr r2, [r7, #12] 80006fc: 429a cmp r2, r3 80006fe: d8f7 bhi.n 80006f0 { } } 8000700: bf00 nop 8000702: bf00 nop 8000704: 3710 adds r7, #16 8000706: 46bd mov sp, r7 8000708: bd80 pop {r7, pc} 800070a: bf00 nop 800070c: 20000008 .word 0x20000008 08000710 <__NVIC_SetPriorityGrouping>: In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 8000710: b480 push {r7} 8000712: b085 sub sp, #20 8000714: af00 add r7, sp, #0 8000716: 6078 str r0, [r7, #4] uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 8000718: 687b ldr r3, [r7, #4] 800071a: f003 0307 and.w r3, r3, #7 800071e: 60fb str r3, [r7, #12] reg_value = SCB->AIRCR; /* read old register configuration */ 8000720: 4b0c ldr r3, [pc, #48] ; (8000754 <__NVIC_SetPriorityGrouping+0x44>) 8000722: 68db ldr r3, [r3, #12] 8000724: 60bb str r3, [r7, #8] reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ 8000726: 68ba ldr r2, [r7, #8] 8000728: f64f 03ff movw r3, #63743 ; 0xf8ff 800072c: 4013 ands r3, r2 800072e: 60bb str r3, [r7, #8] reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ 8000730: 68fb ldr r3, [r7, #12] 8000732: 021a lsls r2, r3, #8 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 8000734: 68bb ldr r3, [r7, #8] 8000736: 4313 orrs r3, r2 reg_value = (reg_value | 8000738: f043 63bf orr.w r3, r3, #100139008 ; 0x5f80000 800073c: f443 3300 orr.w r3, r3, #131072 ; 0x20000 8000740: 60bb str r3, [r7, #8] SCB->AIRCR = reg_value; 8000742: 4a04 ldr r2, [pc, #16] ; (8000754 <__NVIC_SetPriorityGrouping+0x44>) 8000744: 68bb ldr r3, [r7, #8] 8000746: 60d3 str r3, [r2, #12] } 8000748: bf00 nop 800074a: 3714 adds r7, #20 800074c: 46bd mov sp, r7 800074e: bc80 pop {r7} 8000750: 4770 bx lr 8000752: bf00 nop 8000754: e000ed00 .word 0xe000ed00 08000758 <__NVIC_GetPriorityGrouping>: \brief Get Priority Grouping \details Reads the priority grouping field from the NVIC Interrupt Controller. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) { 8000758: b480 push {r7} 800075a: af00 add r7, sp, #0 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); 800075c: 4b04 ldr r3, [pc, #16] ; (8000770 <__NVIC_GetPriorityGrouping+0x18>) 800075e: 68db ldr r3, [r3, #12] 8000760: 0a1b lsrs r3, r3, #8 8000762: f003 0307 and.w r3, r3, #7 } 8000766: 4618 mov r0, r3 8000768: 46bd mov sp, r7 800076a: bc80 pop {r7} 800076c: 4770 bx lr 800076e: bf00 nop 8000770: e000ed00 .word 0xe000ed00 08000774 <__NVIC_SetPriority>: \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { 8000774: b480 push {r7} 8000776: b083 sub sp, #12 8000778: af00 add r7, sp, #0 800077a: 4603 mov r3, r0 800077c: 6039 str r1, [r7, #0] 800077e: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) 8000780: f997 3007 ldrsb.w r3, [r7, #7] 8000784: 2b00 cmp r3, #0 8000786: db0a blt.n 800079e <__NVIC_SetPriority+0x2a> { NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 8000788: 683b ldr r3, [r7, #0] 800078a: b2da uxtb r2, r3 800078c: 490c ldr r1, [pc, #48] ; (80007c0 <__NVIC_SetPriority+0x4c>) 800078e: f997 3007 ldrsb.w r3, [r7, #7] 8000792: 0112 lsls r2, r2, #4 8000794: b2d2 uxtb r2, r2 8000796: 440b add r3, r1 8000798: f883 2300 strb.w r2, [r3, #768] ; 0x300 } else { SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } 800079c: e00a b.n 80007b4 <__NVIC_SetPriority+0x40> SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 800079e: 683b ldr r3, [r7, #0] 80007a0: b2da uxtb r2, r3 80007a2: 4908 ldr r1, [pc, #32] ; (80007c4 <__NVIC_SetPriority+0x50>) 80007a4: 79fb ldrb r3, [r7, #7] 80007a6: f003 030f and.w r3, r3, #15 80007aa: 3b04 subs r3, #4 80007ac: 0112 lsls r2, r2, #4 80007ae: b2d2 uxtb r2, r2 80007b0: 440b add r3, r1 80007b2: 761a strb r2, [r3, #24] } 80007b4: bf00 nop 80007b6: 370c adds r7, #12 80007b8: 46bd mov sp, r7 80007ba: bc80 pop {r7} 80007bc: 4770 bx lr 80007be: bf00 nop 80007c0: e000e100 .word 0xe000e100 80007c4: e000ed00 .word 0xe000ed00 080007c8 : \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { 80007c8: b480 push {r7} 80007ca: b089 sub sp, #36 ; 0x24 80007cc: af00 add r7, sp, #0 80007ce: 60f8 str r0, [r7, #12] 80007d0: 60b9 str r1, [r7, #8] 80007d2: 607a str r2, [r7, #4] uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 80007d4: 68fb ldr r3, [r7, #12] 80007d6: f003 0307 and.w r3, r3, #7 80007da: 61fb str r3, [r7, #28] uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 80007dc: 69fb ldr r3, [r7, #28] 80007de: f1c3 0307 rsb r3, r3, #7 80007e2: 2b04 cmp r3, #4 80007e4: bf28 it cs 80007e6: 2304 movcs r3, #4 80007e8: 61bb str r3, [r7, #24] SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 80007ea: 69fb ldr r3, [r7, #28] 80007ec: 3304 adds r3, #4 80007ee: 2b06 cmp r3, #6 80007f0: d902 bls.n 80007f8 80007f2: 69fb ldr r3, [r7, #28] 80007f4: 3b03 subs r3, #3 80007f6: e000 b.n 80007fa 80007f8: 2300 movs r3, #0 80007fa: 617b str r3, [r7, #20] return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 80007fc: f04f 32ff mov.w r2, #4294967295 8000800: 69bb ldr r3, [r7, #24] 8000802: fa02 f303 lsl.w r3, r2, r3 8000806: 43da mvns r2, r3 8000808: 68bb ldr r3, [r7, #8] 800080a: 401a ands r2, r3 800080c: 697b ldr r3, [r7, #20] 800080e: 409a lsls r2, r3 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) 8000810: f04f 31ff mov.w r1, #4294967295 8000814: 697b ldr r3, [r7, #20] 8000816: fa01 f303 lsl.w r3, r1, r3 800081a: 43d9 mvns r1, r3 800081c: 687b ldr r3, [r7, #4] 800081e: 400b ands r3, r1 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 8000820: 4313 orrs r3, r2 ); } 8000822: 4618 mov r0, r3 8000824: 3724 adds r7, #36 ; 0x24 8000826: 46bd mov sp, r7 8000828: bc80 pop {r7} 800082a: 4770 bx lr 0800082c : \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { 800082c: b580 push {r7, lr} 800082e: b082 sub sp, #8 8000830: af00 add r7, sp, #0 8000832: 6078 str r0, [r7, #4] if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) 8000834: 687b ldr r3, [r7, #4] 8000836: 3b01 subs r3, #1 8000838: f1b3 7f80 cmp.w r3, #16777216 ; 0x1000000 800083c: d301 bcc.n 8000842 { return (1UL); /* Reload value impossible */ 800083e: 2301 movs r3, #1 8000840: e00f b.n 8000862 } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 8000842: 4a0a ldr r2, [pc, #40] ; (800086c ) 8000844: 687b ldr r3, [r7, #4] 8000846: 3b01 subs r3, #1 8000848: 6053 str r3, [r2, #4] NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ 800084a: 210f movs r1, #15 800084c: f04f 30ff mov.w r0, #4294967295 8000850: f7ff ff90 bl 8000774 <__NVIC_SetPriority> SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ 8000854: 4b05 ldr r3, [pc, #20] ; (800086c ) 8000856: 2200 movs r2, #0 8000858: 609a str r2, [r3, #8] SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 800085a: 4b04 ldr r3, [pc, #16] ; (800086c ) 800085c: 2207 movs r2, #7 800085e: 601a str r2, [r3, #0] SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ 8000860: 2300 movs r3, #0 } 8000862: 4618 mov r0, r3 8000864: 3708 adds r7, #8 8000866: 46bd mov sp, r7 8000868: bd80 pop {r7, pc} 800086a: bf00 nop 800086c: e000e010 .word 0xe000e010 08000870 : * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. * The pending IRQ priority will be managed only by the subpriority. * @retval None */ void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 8000870: b580 push {r7, lr} 8000872: b082 sub sp, #8 8000874: af00 add r7, sp, #0 8000876: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ NVIC_SetPriorityGrouping(PriorityGroup); 8000878: 6878 ldr r0, [r7, #4] 800087a: f7ff ff49 bl 8000710 <__NVIC_SetPriorityGrouping> } 800087e: bf00 nop 8000880: 3708 adds r7, #8 8000882: 46bd mov sp, r7 8000884: bd80 pop {r7, pc} 08000886 : * This parameter can be a value between 0 and 15 * A lower priority value indicates a higher priority. * @retval None */ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) { 8000886: b580 push {r7, lr} 8000888: b086 sub sp, #24 800088a: af00 add r7, sp, #0 800088c: 4603 mov r3, r0 800088e: 60b9 str r1, [r7, #8] 8000890: 607a str r2, [r7, #4] 8000892: 73fb strb r3, [r7, #15] uint32_t prioritygroup = 0x00U; 8000894: 2300 movs r3, #0 8000896: 617b str r3, [r7, #20] /* Check the parameters */ assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); prioritygroup = NVIC_GetPriorityGrouping(); 8000898: f7ff ff5e bl 8000758 <__NVIC_GetPriorityGrouping> 800089c: 6178 str r0, [r7, #20] NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); 800089e: 687a ldr r2, [r7, #4] 80008a0: 68b9 ldr r1, [r7, #8] 80008a2: 6978 ldr r0, [r7, #20] 80008a4: f7ff ff90 bl 80007c8 80008a8: 4602 mov r2, r0 80008aa: f997 300f ldrsb.w r3, [r7, #15] 80008ae: 4611 mov r1, r2 80008b0: 4618 mov r0, r3 80008b2: f7ff ff5f bl 8000774 <__NVIC_SetPriority> } 80008b6: bf00 nop 80008b8: 3718 adds r7, #24 80008ba: 46bd mov sp, r7 80008bc: bd80 pop {r7, pc} 080008be : * @param TicksNumb: Specifies the ticks Number of ticks between two interrupts. * @retval status: - 0 Function succeeded. * - 1 Function failed. */ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) { 80008be: b580 push {r7, lr} 80008c0: b082 sub sp, #8 80008c2: af00 add r7, sp, #0 80008c4: 6078 str r0, [r7, #4] return SysTick_Config(TicksNumb); 80008c6: 6878 ldr r0, [r7, #4] 80008c8: f7ff ffb0 bl 800082c 80008cc: 4603 mov r3, r0 } 80008ce: 4618 mov r0, r3 80008d0: 3708 adds r7, #8 80008d2: 46bd mov sp, r7 80008d4: bd80 pop {r7, pc} ... 080008d8 : * @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains * the configuration information for the specified GPIO peripheral. * @retval None */ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) { 80008d8: b480 push {r7} 80008da: b08b sub sp, #44 ; 0x2c 80008dc: af00 add r7, sp, #0 80008de: 6078 str r0, [r7, #4] 80008e0: 6039 str r1, [r7, #0] uint32_t position = 0x00u; 80008e2: 2300 movs r3, #0 80008e4: 627b str r3, [r7, #36] ; 0x24 uint32_t ioposition; uint32_t iocurrent; uint32_t temp; uint32_t config = 0x00u; 80008e6: 2300 movs r3, #0 80008e8: 623b str r3, [r7, #32] assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); /* Configure the port pins */ while (((GPIO_Init->Pin) >> position) != 0x00u) 80008ea: e169 b.n 8000bc0 { /* Get the IO position */ ioposition = (0x01uL << position); 80008ec: 2201 movs r2, #1 80008ee: 6a7b ldr r3, [r7, #36] ; 0x24 80008f0: fa02 f303 lsl.w r3, r2, r3 80008f4: 61fb str r3, [r7, #28] /* Get the current IO position */ iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition; 80008f6: 683b ldr r3, [r7, #0] 80008f8: 681b ldr r3, [r3, #0] 80008fa: 69fa ldr r2, [r7, #28] 80008fc: 4013 ands r3, r2 80008fe: 61bb str r3, [r7, #24] if (iocurrent == ioposition) 8000900: 69ba ldr r2, [r7, #24] 8000902: 69fb ldr r3, [r7, #28] 8000904: 429a cmp r2, r3 8000906: f040 8158 bne.w 8000bba { /* Check the Alternate function parameters */ assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); /* Based on the required mode, filling config variable with MODEy[1:0] and CNFy[3:2] corresponding bits */ switch (GPIO_Init->Mode) 800090a: 683b ldr r3, [r7, #0] 800090c: 685b ldr r3, [r3, #4] 800090e: 4a9a ldr r2, [pc, #616] ; (8000b78 ) 8000910: 4293 cmp r3, r2 8000912: d05e beq.n 80009d2 8000914: 4a98 ldr r2, [pc, #608] ; (8000b78 ) 8000916: 4293 cmp r3, r2 8000918: d875 bhi.n 8000a06 800091a: 4a98 ldr r2, [pc, #608] ; (8000b7c ) 800091c: 4293 cmp r3, r2 800091e: d058 beq.n 80009d2 8000920: 4a96 ldr r2, [pc, #600] ; (8000b7c ) 8000922: 4293 cmp r3, r2 8000924: d86f bhi.n 8000a06 8000926: 4a96 ldr r2, [pc, #600] ; (8000b80 ) 8000928: 4293 cmp r3, r2 800092a: d052 beq.n 80009d2 800092c: 4a94 ldr r2, [pc, #592] ; (8000b80 ) 800092e: 4293 cmp r3, r2 8000930: d869 bhi.n 8000a06 8000932: 4a94 ldr r2, [pc, #592] ; (8000b84 ) 8000934: 4293 cmp r3, r2 8000936: d04c beq.n 80009d2 8000938: 4a92 ldr r2, [pc, #584] ; (8000b84 ) 800093a: 4293 cmp r3, r2 800093c: d863 bhi.n 8000a06 800093e: 4a92 ldr r2, [pc, #584] ; (8000b88 ) 8000940: 4293 cmp r3, r2 8000942: d046 beq.n 80009d2 8000944: 4a90 ldr r2, [pc, #576] ; (8000b88 ) 8000946: 4293 cmp r3, r2 8000948: d85d bhi.n 8000a06 800094a: 2b12 cmp r3, #18 800094c: d82a bhi.n 80009a4 800094e: 2b12 cmp r3, #18 8000950: d859 bhi.n 8000a06 8000952: a201 add r2, pc, #4 ; (adr r2, 8000958 ) 8000954: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8000958: 080009d3 .word 0x080009d3 800095c: 080009ad .word 0x080009ad 8000960: 080009bf .word 0x080009bf 8000964: 08000a01 .word 0x08000a01 8000968: 08000a07 .word 0x08000a07 800096c: 08000a07 .word 0x08000a07 8000970: 08000a07 .word 0x08000a07 8000974: 08000a07 .word 0x08000a07 8000978: 08000a07 .word 0x08000a07 800097c: 08000a07 .word 0x08000a07 8000980: 08000a07 .word 0x08000a07 8000984: 08000a07 .word 0x08000a07 8000988: 08000a07 .word 0x08000a07 800098c: 08000a07 .word 0x08000a07 8000990: 08000a07 .word 0x08000a07 8000994: 08000a07 .word 0x08000a07 8000998: 08000a07 .word 0x08000a07 800099c: 080009b5 .word 0x080009b5 80009a0: 080009c9 .word 0x080009c9 80009a4: 4a79 ldr r2, [pc, #484] ; (8000b8c ) 80009a6: 4293 cmp r3, r2 80009a8: d013 beq.n 80009d2 config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG; break; /* Parameters are checked with assert_param */ default: break; 80009aa: e02c b.n 8000a06 config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_PP; 80009ac: 683b ldr r3, [r7, #0] 80009ae: 68db ldr r3, [r3, #12] 80009b0: 623b str r3, [r7, #32] break; 80009b2: e029 b.n 8000a08 config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_OD; 80009b4: 683b ldr r3, [r7, #0] 80009b6: 68db ldr r3, [r3, #12] 80009b8: 3304 adds r3, #4 80009ba: 623b str r3, [r7, #32] break; 80009bc: e024 b.n 8000a08 config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_PP; 80009be: 683b ldr r3, [r7, #0] 80009c0: 68db ldr r3, [r3, #12] 80009c2: 3308 adds r3, #8 80009c4: 623b str r3, [r7, #32] break; 80009c6: e01f b.n 8000a08 config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_OD; 80009c8: 683b ldr r3, [r7, #0] 80009ca: 68db ldr r3, [r3, #12] 80009cc: 330c adds r3, #12 80009ce: 623b str r3, [r7, #32] break; 80009d0: e01a b.n 8000a08 if (GPIO_Init->Pull == GPIO_NOPULL) 80009d2: 683b ldr r3, [r7, #0] 80009d4: 689b ldr r3, [r3, #8] 80009d6: 2b00 cmp r3, #0 80009d8: d102 bne.n 80009e0 config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_FLOATING; 80009da: 2304 movs r3, #4 80009dc: 623b str r3, [r7, #32] break; 80009de: e013 b.n 8000a08 else if (GPIO_Init->Pull == GPIO_PULLUP) 80009e0: 683b ldr r3, [r7, #0] 80009e2: 689b ldr r3, [r3, #8] 80009e4: 2b01 cmp r3, #1 80009e6: d105 bne.n 80009f4 config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD; 80009e8: 2308 movs r3, #8 80009ea: 623b str r3, [r7, #32] GPIOx->BSRR = ioposition; 80009ec: 687b ldr r3, [r7, #4] 80009ee: 69fa ldr r2, [r7, #28] 80009f0: 611a str r2, [r3, #16] break; 80009f2: e009 b.n 8000a08 config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD; 80009f4: 2308 movs r3, #8 80009f6: 623b str r3, [r7, #32] GPIOx->BRR = ioposition; 80009f8: 687b ldr r3, [r7, #4] 80009fa: 69fa ldr r2, [r7, #28] 80009fc: 615a str r2, [r3, #20] break; 80009fe: e003 b.n 8000a08 config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG; 8000a00: 2300 movs r3, #0 8000a02: 623b str r3, [r7, #32] break; 8000a04: e000 b.n 8000a08 break; 8000a06: bf00 nop } /* Check if the current bit belongs to first half or last half of the pin count number in order to address CRH or CRL register*/ configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL : &GPIOx->CRH; 8000a08: 69bb ldr r3, [r7, #24] 8000a0a: 2bff cmp r3, #255 ; 0xff 8000a0c: d801 bhi.n 8000a12 8000a0e: 687b ldr r3, [r7, #4] 8000a10: e001 b.n 8000a16 8000a12: 687b ldr r3, [r7, #4] 8000a14: 3304 adds r3, #4 8000a16: 617b str r3, [r7, #20] registeroffset = (iocurrent < GPIO_PIN_8) ? (position << 2u) : ((position - 8u) << 2u); 8000a18: 69bb ldr r3, [r7, #24] 8000a1a: 2bff cmp r3, #255 ; 0xff 8000a1c: d802 bhi.n 8000a24 8000a1e: 6a7b ldr r3, [r7, #36] ; 0x24 8000a20: 009b lsls r3, r3, #2 8000a22: e002 b.n 8000a2a 8000a24: 6a7b ldr r3, [r7, #36] ; 0x24 8000a26: 3b08 subs r3, #8 8000a28: 009b lsls r3, r3, #2 8000a2a: 613b str r3, [r7, #16] /* Apply the new configuration of the pin to the register */ MODIFY_REG((*configregister), ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset), (config << registeroffset)); 8000a2c: 697b ldr r3, [r7, #20] 8000a2e: 681a ldr r2, [r3, #0] 8000a30: 210f movs r1, #15 8000a32: 693b ldr r3, [r7, #16] 8000a34: fa01 f303 lsl.w r3, r1, r3 8000a38: 43db mvns r3, r3 8000a3a: 401a ands r2, r3 8000a3c: 6a39 ldr r1, [r7, #32] 8000a3e: 693b ldr r3, [r7, #16] 8000a40: fa01 f303 lsl.w r3, r1, r3 8000a44: 431a orrs r2, r3 8000a46: 697b ldr r3, [r7, #20] 8000a48: 601a str r2, [r3, #0] /*--------------------- EXTI Mode Configuration ------------------------*/ /* Configure the External Interrupt or event for the current IO */ if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE) 8000a4a: 683b ldr r3, [r7, #0] 8000a4c: 685b ldr r3, [r3, #4] 8000a4e: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 8000a52: 2b00 cmp r3, #0 8000a54: f000 80b1 beq.w 8000bba { /* Enable AFIO Clock */ __HAL_RCC_AFIO_CLK_ENABLE(); 8000a58: 4b4d ldr r3, [pc, #308] ; (8000b90 ) 8000a5a: 699b ldr r3, [r3, #24] 8000a5c: 4a4c ldr r2, [pc, #304] ; (8000b90 ) 8000a5e: f043 0301 orr.w r3, r3, #1 8000a62: 6193 str r3, [r2, #24] 8000a64: 4b4a ldr r3, [pc, #296] ; (8000b90 ) 8000a66: 699b ldr r3, [r3, #24] 8000a68: f003 0301 and.w r3, r3, #1 8000a6c: 60bb str r3, [r7, #8] 8000a6e: 68bb ldr r3, [r7, #8] temp = AFIO->EXTICR[position >> 2u]; 8000a70: 4a48 ldr r2, [pc, #288] ; (8000b94 ) 8000a72: 6a7b ldr r3, [r7, #36] ; 0x24 8000a74: 089b lsrs r3, r3, #2 8000a76: 3302 adds r3, #2 8000a78: f852 3023 ldr.w r3, [r2, r3, lsl #2] 8000a7c: 60fb str r3, [r7, #12] CLEAR_BIT(temp, (0x0Fu) << (4u * (position & 0x03u))); 8000a7e: 6a7b ldr r3, [r7, #36] ; 0x24 8000a80: f003 0303 and.w r3, r3, #3 8000a84: 009b lsls r3, r3, #2 8000a86: 220f movs r2, #15 8000a88: fa02 f303 lsl.w r3, r2, r3 8000a8c: 43db mvns r3, r3 8000a8e: 68fa ldr r2, [r7, #12] 8000a90: 4013 ands r3, r2 8000a92: 60fb str r3, [r7, #12] SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4u * (position & 0x03u))); 8000a94: 687b ldr r3, [r7, #4] 8000a96: 4a40 ldr r2, [pc, #256] ; (8000b98 ) 8000a98: 4293 cmp r3, r2 8000a9a: d013 beq.n 8000ac4 8000a9c: 687b ldr r3, [r7, #4] 8000a9e: 4a3f ldr r2, [pc, #252] ; (8000b9c ) 8000aa0: 4293 cmp r3, r2 8000aa2: d00d beq.n 8000ac0 8000aa4: 687b ldr r3, [r7, #4] 8000aa6: 4a3e ldr r2, [pc, #248] ; (8000ba0 ) 8000aa8: 4293 cmp r3, r2 8000aaa: d007 beq.n 8000abc 8000aac: 687b ldr r3, [r7, #4] 8000aae: 4a3d ldr r2, [pc, #244] ; (8000ba4 ) 8000ab0: 4293 cmp r3, r2 8000ab2: d101 bne.n 8000ab8 8000ab4: 2303 movs r3, #3 8000ab6: e006 b.n 8000ac6 8000ab8: 2304 movs r3, #4 8000aba: e004 b.n 8000ac6 8000abc: 2302 movs r3, #2 8000abe: e002 b.n 8000ac6 8000ac0: 2301 movs r3, #1 8000ac2: e000 b.n 8000ac6 8000ac4: 2300 movs r3, #0 8000ac6: 6a7a ldr r2, [r7, #36] ; 0x24 8000ac8: f002 0203 and.w r2, r2, #3 8000acc: 0092 lsls r2, r2, #2 8000ace: 4093 lsls r3, r2 8000ad0: 68fa ldr r2, [r7, #12] 8000ad2: 4313 orrs r3, r2 8000ad4: 60fb str r3, [r7, #12] AFIO->EXTICR[position >> 2u] = temp; 8000ad6: 492f ldr r1, [pc, #188] ; (8000b94 ) 8000ad8: 6a7b ldr r3, [r7, #36] ; 0x24 8000ada: 089b lsrs r3, r3, #2 8000adc: 3302 adds r3, #2 8000ade: 68fa ldr r2, [r7, #12] 8000ae0: f841 2023 str.w r2, [r1, r3, lsl #2] /* Configure the interrupt mask */ if ((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT) 8000ae4: 683b ldr r3, [r7, #0] 8000ae6: 685b ldr r3, [r3, #4] 8000ae8: f403 3380 and.w r3, r3, #65536 ; 0x10000 8000aec: 2b00 cmp r3, #0 8000aee: d006 beq.n 8000afe { SET_BIT(EXTI->IMR, iocurrent); 8000af0: 4b2d ldr r3, [pc, #180] ; (8000ba8 ) 8000af2: 681a ldr r2, [r3, #0] 8000af4: 492c ldr r1, [pc, #176] ; (8000ba8 ) 8000af6: 69bb ldr r3, [r7, #24] 8000af8: 4313 orrs r3, r2 8000afa: 600b str r3, [r1, #0] 8000afc: e006 b.n 8000b0c } else { CLEAR_BIT(EXTI->IMR, iocurrent); 8000afe: 4b2a ldr r3, [pc, #168] ; (8000ba8 ) 8000b00: 681a ldr r2, [r3, #0] 8000b02: 69bb ldr r3, [r7, #24] 8000b04: 43db mvns r3, r3 8000b06: 4928 ldr r1, [pc, #160] ; (8000ba8 ) 8000b08: 4013 ands r3, r2 8000b0a: 600b str r3, [r1, #0] } /* Configure the event mask */ if ((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT) 8000b0c: 683b ldr r3, [r7, #0] 8000b0e: 685b ldr r3, [r3, #4] 8000b10: f403 3300 and.w r3, r3, #131072 ; 0x20000 8000b14: 2b00 cmp r3, #0 8000b16: d006 beq.n 8000b26 { SET_BIT(EXTI->EMR, iocurrent); 8000b18: 4b23 ldr r3, [pc, #140] ; (8000ba8 ) 8000b1a: 685a ldr r2, [r3, #4] 8000b1c: 4922 ldr r1, [pc, #136] ; (8000ba8 ) 8000b1e: 69bb ldr r3, [r7, #24] 8000b20: 4313 orrs r3, r2 8000b22: 604b str r3, [r1, #4] 8000b24: e006 b.n 8000b34 } else { CLEAR_BIT(EXTI->EMR, iocurrent); 8000b26: 4b20 ldr r3, [pc, #128] ; (8000ba8 ) 8000b28: 685a ldr r2, [r3, #4] 8000b2a: 69bb ldr r3, [r7, #24] 8000b2c: 43db mvns r3, r3 8000b2e: 491e ldr r1, [pc, #120] ; (8000ba8 ) 8000b30: 4013 ands r3, r2 8000b32: 604b str r3, [r1, #4] } /* Enable or disable the rising trigger */ if ((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE) 8000b34: 683b ldr r3, [r7, #0] 8000b36: 685b ldr r3, [r3, #4] 8000b38: f403 1380 and.w r3, r3, #1048576 ; 0x100000 8000b3c: 2b00 cmp r3, #0 8000b3e: d006 beq.n 8000b4e { SET_BIT(EXTI->RTSR, iocurrent); 8000b40: 4b19 ldr r3, [pc, #100] ; (8000ba8 ) 8000b42: 689a ldr r2, [r3, #8] 8000b44: 4918 ldr r1, [pc, #96] ; (8000ba8 ) 8000b46: 69bb ldr r3, [r7, #24] 8000b48: 4313 orrs r3, r2 8000b4a: 608b str r3, [r1, #8] 8000b4c: e006 b.n 8000b5c } else { CLEAR_BIT(EXTI->RTSR, iocurrent); 8000b4e: 4b16 ldr r3, [pc, #88] ; (8000ba8 ) 8000b50: 689a ldr r2, [r3, #8] 8000b52: 69bb ldr r3, [r7, #24] 8000b54: 43db mvns r3, r3 8000b56: 4914 ldr r1, [pc, #80] ; (8000ba8 ) 8000b58: 4013 ands r3, r2 8000b5a: 608b str r3, [r1, #8] } /* Enable or disable the falling trigger */ if ((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE) 8000b5c: 683b ldr r3, [r7, #0] 8000b5e: 685b ldr r3, [r3, #4] 8000b60: f403 1300 and.w r3, r3, #2097152 ; 0x200000 8000b64: 2b00 cmp r3, #0 8000b66: d021 beq.n 8000bac { SET_BIT(EXTI->FTSR, iocurrent); 8000b68: 4b0f ldr r3, [pc, #60] ; (8000ba8 ) 8000b6a: 68da ldr r2, [r3, #12] 8000b6c: 490e ldr r1, [pc, #56] ; (8000ba8 ) 8000b6e: 69bb ldr r3, [r7, #24] 8000b70: 4313 orrs r3, r2 8000b72: 60cb str r3, [r1, #12] 8000b74: e021 b.n 8000bba 8000b76: bf00 nop 8000b78: 10320000 .word 0x10320000 8000b7c: 10310000 .word 0x10310000 8000b80: 10220000 .word 0x10220000 8000b84: 10210000 .word 0x10210000 8000b88: 10120000 .word 0x10120000 8000b8c: 10110000 .word 0x10110000 8000b90: 40021000 .word 0x40021000 8000b94: 40010000 .word 0x40010000 8000b98: 40010800 .word 0x40010800 8000b9c: 40010c00 .word 0x40010c00 8000ba0: 40011000 .word 0x40011000 8000ba4: 40011400 .word 0x40011400 8000ba8: 40010400 .word 0x40010400 } else { CLEAR_BIT(EXTI->FTSR, iocurrent); 8000bac: 4b0b ldr r3, [pc, #44] ; (8000bdc ) 8000bae: 68da ldr r2, [r3, #12] 8000bb0: 69bb ldr r3, [r7, #24] 8000bb2: 43db mvns r3, r3 8000bb4: 4909 ldr r1, [pc, #36] ; (8000bdc ) 8000bb6: 4013 ands r3, r2 8000bb8: 60cb str r3, [r1, #12] } } } position++; 8000bba: 6a7b ldr r3, [r7, #36] ; 0x24 8000bbc: 3301 adds r3, #1 8000bbe: 627b str r3, [r7, #36] ; 0x24 while (((GPIO_Init->Pin) >> position) != 0x00u) 8000bc0: 683b ldr r3, [r7, #0] 8000bc2: 681a ldr r2, [r3, #0] 8000bc4: 6a7b ldr r3, [r7, #36] ; 0x24 8000bc6: fa22 f303 lsr.w r3, r2, r3 8000bca: 2b00 cmp r3, #0 8000bcc: f47f ae8e bne.w 80008ec } } 8000bd0: bf00 nop 8000bd2: bf00 nop 8000bd4: 372c adds r7, #44 ; 0x2c 8000bd6: 46bd mov sp, r7 8000bd8: bc80 pop {r7} 8000bda: 4770 bx lr 8000bdc: 40010400 .word 0x40010400 08000be0 : * @note If the HSE divided by 128 is used as the RTC clock, the * Backup Domain Access should be kept enabled. * @retval None */ void HAL_PWR_EnableBkUpAccess(void) { 8000be0: b480 push {r7} 8000be2: af00 add r7, sp, #0 /* Enable access to RTC and backup registers */ *(__IO uint32_t *) CR_DBP_BB = (uint32_t)ENABLE; 8000be4: 4b03 ldr r3, [pc, #12] ; (8000bf4 ) 8000be6: 2201 movs r2, #1 8000be8: 601a str r2, [r3, #0] } 8000bea: bf00 nop 8000bec: 46bd mov sp, r7 8000bee: bc80 pop {r7} 8000bf0: 4770 bx lr 8000bf2: bf00 nop 8000bf4: 420e0020 .word 0x420e0020 08000bf8 : * supported by this macro. User should request a transition to HSE Off * first and then HSE On or HSE Bypass. * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { 8000bf8: b580 push {r7, lr} 8000bfa: b086 sub sp, #24 8000bfc: af00 add r7, sp, #0 8000bfe: 6078 str r0, [r7, #4] uint32_t tickstart; uint32_t pll_config; /* Check Null pointer */ if (RCC_OscInitStruct == NULL) 8000c00: 687b ldr r3, [r7, #4] 8000c02: 2b00 cmp r3, #0 8000c04: d101 bne.n 8000c0a { return HAL_ERROR; 8000c06: 2301 movs r3, #1 8000c08: e272 b.n 80010f0 /* Check the parameters */ assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); /*------------------------------- HSE Configuration ------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) 8000c0a: 687b ldr r3, [r7, #4] 8000c0c: 681b ldr r3, [r3, #0] 8000c0e: f003 0301 and.w r3, r3, #1 8000c12: 2b00 cmp r3, #0 8000c14: f000 8087 beq.w 8000d26 { /* Check the parameters */ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */ if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE) 8000c18: 4b92 ldr r3, [pc, #584] ; (8000e64 ) 8000c1a: 685b ldr r3, [r3, #4] 8000c1c: f003 030c and.w r3, r3, #12 8000c20: 2b04 cmp r3, #4 8000c22: d00c beq.n 8000c3e || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE))) 8000c24: 4b8f ldr r3, [pc, #572] ; (8000e64 ) 8000c26: 685b ldr r3, [r3, #4] 8000c28: f003 030c and.w r3, r3, #12 8000c2c: 2b08 cmp r3, #8 8000c2e: d112 bne.n 8000c56 8000c30: 4b8c ldr r3, [pc, #560] ; (8000e64 ) 8000c32: 685b ldr r3, [r3, #4] 8000c34: f403 3380 and.w r3, r3, #65536 ; 0x10000 8000c38: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 8000c3c: d10b bne.n 8000c56 { if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 8000c3e: 4b89 ldr r3, [pc, #548] ; (8000e64 ) 8000c40: 681b ldr r3, [r3, #0] 8000c42: f403 3300 and.w r3, r3, #131072 ; 0x20000 8000c46: 2b00 cmp r3, #0 8000c48: d06c beq.n 8000d24 8000c4a: 687b ldr r3, [r7, #4] 8000c4c: 685b ldr r3, [r3, #4] 8000c4e: 2b00 cmp r3, #0 8000c50: d168 bne.n 8000d24 { return HAL_ERROR; 8000c52: 2301 movs r3, #1 8000c54: e24c b.n 80010f0 } } else { /* Set the new HSE configuration ---------------------------------------*/ __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); 8000c56: 687b ldr r3, [r7, #4] 8000c58: 685b ldr r3, [r3, #4] 8000c5a: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 8000c5e: d106 bne.n 8000c6e 8000c60: 4b80 ldr r3, [pc, #512] ; (8000e64 ) 8000c62: 681b ldr r3, [r3, #0] 8000c64: 4a7f ldr r2, [pc, #508] ; (8000e64 ) 8000c66: f443 3380 orr.w r3, r3, #65536 ; 0x10000 8000c6a: 6013 str r3, [r2, #0] 8000c6c: e02e b.n 8000ccc 8000c6e: 687b ldr r3, [r7, #4] 8000c70: 685b ldr r3, [r3, #4] 8000c72: 2b00 cmp r3, #0 8000c74: d10c bne.n 8000c90 8000c76: 4b7b ldr r3, [pc, #492] ; (8000e64 ) 8000c78: 681b ldr r3, [r3, #0] 8000c7a: 4a7a ldr r2, [pc, #488] ; (8000e64 ) 8000c7c: f423 3380 bic.w r3, r3, #65536 ; 0x10000 8000c80: 6013 str r3, [r2, #0] 8000c82: 4b78 ldr r3, [pc, #480] ; (8000e64 ) 8000c84: 681b ldr r3, [r3, #0] 8000c86: 4a77 ldr r2, [pc, #476] ; (8000e64 ) 8000c88: f423 2380 bic.w r3, r3, #262144 ; 0x40000 8000c8c: 6013 str r3, [r2, #0] 8000c8e: e01d b.n 8000ccc 8000c90: 687b ldr r3, [r7, #4] 8000c92: 685b ldr r3, [r3, #4] 8000c94: f5b3 2fa0 cmp.w r3, #327680 ; 0x50000 8000c98: d10c bne.n 8000cb4 8000c9a: 4b72 ldr r3, [pc, #456] ; (8000e64 ) 8000c9c: 681b ldr r3, [r3, #0] 8000c9e: 4a71 ldr r2, [pc, #452] ; (8000e64 ) 8000ca0: f443 2380 orr.w r3, r3, #262144 ; 0x40000 8000ca4: 6013 str r3, [r2, #0] 8000ca6: 4b6f ldr r3, [pc, #444] ; (8000e64 ) 8000ca8: 681b ldr r3, [r3, #0] 8000caa: 4a6e ldr r2, [pc, #440] ; (8000e64 ) 8000cac: f443 3380 orr.w r3, r3, #65536 ; 0x10000 8000cb0: 6013 str r3, [r2, #0] 8000cb2: e00b b.n 8000ccc 8000cb4: 4b6b ldr r3, [pc, #428] ; (8000e64 ) 8000cb6: 681b ldr r3, [r3, #0] 8000cb8: 4a6a ldr r2, [pc, #424] ; (8000e64 ) 8000cba: f423 3380 bic.w r3, r3, #65536 ; 0x10000 8000cbe: 6013 str r3, [r2, #0] 8000cc0: 4b68 ldr r3, [pc, #416] ; (8000e64 ) 8000cc2: 681b ldr r3, [r3, #0] 8000cc4: 4a67 ldr r2, [pc, #412] ; (8000e64 ) 8000cc6: f423 2380 bic.w r3, r3, #262144 ; 0x40000 8000cca: 6013 str r3, [r2, #0] /* Check the HSE State */ if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF) 8000ccc: 687b ldr r3, [r7, #4] 8000cce: 685b ldr r3, [r3, #4] 8000cd0: 2b00 cmp r3, #0 8000cd2: d013 beq.n 8000cfc { /* Get Start Tick */ tickstart = HAL_GetTick(); 8000cd4: f7ff fcee bl 80006b4 8000cd8: 6138 str r0, [r7, #16] /* Wait till HSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 8000cda: e008 b.n 8000cee { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 8000cdc: f7ff fcea bl 80006b4 8000ce0: 4602 mov r2, r0 8000ce2: 693b ldr r3, [r7, #16] 8000ce4: 1ad3 subs r3, r2, r3 8000ce6: 2b64 cmp r3, #100 ; 0x64 8000ce8: d901 bls.n 8000cee { return HAL_TIMEOUT; 8000cea: 2303 movs r3, #3 8000cec: e200 b.n 80010f0 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 8000cee: 4b5d ldr r3, [pc, #372] ; (8000e64 ) 8000cf0: 681b ldr r3, [r3, #0] 8000cf2: f403 3300 and.w r3, r3, #131072 ; 0x20000 8000cf6: 2b00 cmp r3, #0 8000cf8: d0f0 beq.n 8000cdc 8000cfa: e014 b.n 8000d26 } } else { /* Get Start Tick */ tickstart = HAL_GetTick(); 8000cfc: f7ff fcda bl 80006b4 8000d00: 6138 str r0, [r7, #16] /* Wait till HSE is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) 8000d02: e008 b.n 8000d16 { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 8000d04: f7ff fcd6 bl 80006b4 8000d08: 4602 mov r2, r0 8000d0a: 693b ldr r3, [r7, #16] 8000d0c: 1ad3 subs r3, r2, r3 8000d0e: 2b64 cmp r3, #100 ; 0x64 8000d10: d901 bls.n 8000d16 { return HAL_TIMEOUT; 8000d12: 2303 movs r3, #3 8000d14: e1ec b.n 80010f0 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) 8000d16: 4b53 ldr r3, [pc, #332] ; (8000e64 ) 8000d18: 681b ldr r3, [r3, #0] 8000d1a: f403 3300 and.w r3, r3, #131072 ; 0x20000 8000d1e: 2b00 cmp r3, #0 8000d20: d1f0 bne.n 8000d04 8000d22: e000 b.n 8000d26 if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 8000d24: bf00 nop } } } } /*----------------------------- HSI Configuration --------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) 8000d26: 687b ldr r3, [r7, #4] 8000d28: 681b ldr r3, [r3, #0] 8000d2a: f003 0302 and.w r3, r3, #2 8000d2e: 2b00 cmp r3, #0 8000d30: d063 beq.n 8000dfa /* Check the parameters */ assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI) 8000d32: 4b4c ldr r3, [pc, #304] ; (8000e64 ) 8000d34: 685b ldr r3, [r3, #4] 8000d36: f003 030c and.w r3, r3, #12 8000d3a: 2b00 cmp r3, #0 8000d3c: d00b beq.n 8000d56 || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI_DIV2))) 8000d3e: 4b49 ldr r3, [pc, #292] ; (8000e64 ) 8000d40: 685b ldr r3, [r3, #4] 8000d42: f003 030c and.w r3, r3, #12 8000d46: 2b08 cmp r3, #8 8000d48: d11c bne.n 8000d84 8000d4a: 4b46 ldr r3, [pc, #280] ; (8000e64 ) 8000d4c: 685b ldr r3, [r3, #4] 8000d4e: f403 3380 and.w r3, r3, #65536 ; 0x10000 8000d52: 2b00 cmp r3, #0 8000d54: d116 bne.n 8000d84 { /* When HSI is used as system clock it will not disabled */ if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) 8000d56: 4b43 ldr r3, [pc, #268] ; (8000e64 ) 8000d58: 681b ldr r3, [r3, #0] 8000d5a: f003 0302 and.w r3, r3, #2 8000d5e: 2b00 cmp r3, #0 8000d60: d005 beq.n 8000d6e 8000d62: 687b ldr r3, [r7, #4] 8000d64: 691b ldr r3, [r3, #16] 8000d66: 2b01 cmp r3, #1 8000d68: d001 beq.n 8000d6e { return HAL_ERROR; 8000d6a: 2301 movs r3, #1 8000d6c: e1c0 b.n 80010f0 } /* Otherwise, just the calibration is allowed */ else { /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 8000d6e: 4b3d ldr r3, [pc, #244] ; (8000e64 ) 8000d70: 681b ldr r3, [r3, #0] 8000d72: f023 02f8 bic.w r2, r3, #248 ; 0xf8 8000d76: 687b ldr r3, [r7, #4] 8000d78: 695b ldr r3, [r3, #20] 8000d7a: 00db lsls r3, r3, #3 8000d7c: 4939 ldr r1, [pc, #228] ; (8000e64 ) 8000d7e: 4313 orrs r3, r2 8000d80: 600b str r3, [r1, #0] if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) 8000d82: e03a b.n 8000dfa } } else { /* Check the HSI State */ if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF) 8000d84: 687b ldr r3, [r7, #4] 8000d86: 691b ldr r3, [r3, #16] 8000d88: 2b00 cmp r3, #0 8000d8a: d020 beq.n 8000dce { /* Enable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_ENABLE(); 8000d8c: 4b36 ldr r3, [pc, #216] ; (8000e68 ) 8000d8e: 2201 movs r2, #1 8000d90: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8000d92: f7ff fc8f bl 80006b4 8000d96: 6138 str r0, [r7, #16] /* Wait till HSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 8000d98: e008 b.n 8000dac { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 8000d9a: f7ff fc8b bl 80006b4 8000d9e: 4602 mov r2, r0 8000da0: 693b ldr r3, [r7, #16] 8000da2: 1ad3 subs r3, r2, r3 8000da4: 2b02 cmp r3, #2 8000da6: d901 bls.n 8000dac { return HAL_TIMEOUT; 8000da8: 2303 movs r3, #3 8000daa: e1a1 b.n 80010f0 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 8000dac: 4b2d ldr r3, [pc, #180] ; (8000e64 ) 8000dae: 681b ldr r3, [r3, #0] 8000db0: f003 0302 and.w r3, r3, #2 8000db4: 2b00 cmp r3, #0 8000db6: d0f0 beq.n 8000d9a } } /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 8000db8: 4b2a ldr r3, [pc, #168] ; (8000e64 ) 8000dba: 681b ldr r3, [r3, #0] 8000dbc: f023 02f8 bic.w r2, r3, #248 ; 0xf8 8000dc0: 687b ldr r3, [r7, #4] 8000dc2: 695b ldr r3, [r3, #20] 8000dc4: 00db lsls r3, r3, #3 8000dc6: 4927 ldr r1, [pc, #156] ; (8000e64 ) 8000dc8: 4313 orrs r3, r2 8000dca: 600b str r3, [r1, #0] 8000dcc: e015 b.n 8000dfa } else { /* Disable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_DISABLE(); 8000dce: 4b26 ldr r3, [pc, #152] ; (8000e68 ) 8000dd0: 2200 movs r2, #0 8000dd2: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8000dd4: f7ff fc6e bl 80006b4 8000dd8: 6138 str r0, [r7, #16] /* Wait till HSI is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) 8000dda: e008 b.n 8000dee { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 8000ddc: f7ff fc6a bl 80006b4 8000de0: 4602 mov r2, r0 8000de2: 693b ldr r3, [r7, #16] 8000de4: 1ad3 subs r3, r2, r3 8000de6: 2b02 cmp r3, #2 8000de8: d901 bls.n 8000dee { return HAL_TIMEOUT; 8000dea: 2303 movs r3, #3 8000dec: e180 b.n 80010f0 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) 8000dee: 4b1d ldr r3, [pc, #116] ; (8000e64 ) 8000df0: 681b ldr r3, [r3, #0] 8000df2: f003 0302 and.w r3, r3, #2 8000df6: 2b00 cmp r3, #0 8000df8: d1f0 bne.n 8000ddc } } } } /*------------------------------ LSI Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) 8000dfa: 687b ldr r3, [r7, #4] 8000dfc: 681b ldr r3, [r3, #0] 8000dfe: f003 0308 and.w r3, r3, #8 8000e02: 2b00 cmp r3, #0 8000e04: d03a beq.n 8000e7c { /* Check the parameters */ assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); /* Check the LSI State */ if (RCC_OscInitStruct->LSIState != RCC_LSI_OFF) 8000e06: 687b ldr r3, [r7, #4] 8000e08: 699b ldr r3, [r3, #24] 8000e0a: 2b00 cmp r3, #0 8000e0c: d019 beq.n 8000e42 { /* Enable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_ENABLE(); 8000e0e: 4b17 ldr r3, [pc, #92] ; (8000e6c ) 8000e10: 2201 movs r2, #1 8000e12: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8000e14: f7ff fc4e bl 80006b4 8000e18: 6138 str r0, [r7, #16] /* Wait till LSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) 8000e1a: e008 b.n 8000e2e { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 8000e1c: f7ff fc4a bl 80006b4 8000e20: 4602 mov r2, r0 8000e22: 693b ldr r3, [r7, #16] 8000e24: 1ad3 subs r3, r2, r3 8000e26: 2b02 cmp r3, #2 8000e28: d901 bls.n 8000e2e { return HAL_TIMEOUT; 8000e2a: 2303 movs r3, #3 8000e2c: e160 b.n 80010f0 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) 8000e2e: 4b0d ldr r3, [pc, #52] ; (8000e64 ) 8000e30: 6a5b ldr r3, [r3, #36] ; 0x24 8000e32: f003 0302 and.w r3, r3, #2 8000e36: 2b00 cmp r3, #0 8000e38: d0f0 beq.n 8000e1c } } /* To have a fully stabilized clock in the specified range, a software delay of 1ms should be added.*/ RCC_Delay(1); 8000e3a: 2001 movs r0, #1 8000e3c: f000 fad8 bl 80013f0 8000e40: e01c b.n 8000e7c } else { /* Disable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_DISABLE(); 8000e42: 4b0a ldr r3, [pc, #40] ; (8000e6c ) 8000e44: 2200 movs r2, #0 8000e46: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8000e48: f7ff fc34 bl 80006b4 8000e4c: 6138 str r0, [r7, #16] /* Wait till LSI is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) 8000e4e: e00f b.n 8000e70 { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 8000e50: f7ff fc30 bl 80006b4 8000e54: 4602 mov r2, r0 8000e56: 693b ldr r3, [r7, #16] 8000e58: 1ad3 subs r3, r2, r3 8000e5a: 2b02 cmp r3, #2 8000e5c: d908 bls.n 8000e70 { return HAL_TIMEOUT; 8000e5e: 2303 movs r3, #3 8000e60: e146 b.n 80010f0 8000e62: bf00 nop 8000e64: 40021000 .word 0x40021000 8000e68: 42420000 .word 0x42420000 8000e6c: 42420480 .word 0x42420480 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) 8000e70: 4b92 ldr r3, [pc, #584] ; (80010bc ) 8000e72: 6a5b ldr r3, [r3, #36] ; 0x24 8000e74: f003 0302 and.w r3, r3, #2 8000e78: 2b00 cmp r3, #0 8000e7a: d1e9 bne.n 8000e50 } } } } /*------------------------------ LSE Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) 8000e7c: 687b ldr r3, [r7, #4] 8000e7e: 681b ldr r3, [r3, #0] 8000e80: f003 0304 and.w r3, r3, #4 8000e84: 2b00 cmp r3, #0 8000e86: f000 80a6 beq.w 8000fd6 { FlagStatus pwrclkchanged = RESET; 8000e8a: 2300 movs r3, #0 8000e8c: 75fb strb r3, [r7, #23] /* Check the parameters */ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); /* Update LSE configuration in Backup Domain control register */ /* Requires to enable write access to Backup Domain of necessary */ if (__HAL_RCC_PWR_IS_CLK_DISABLED()) 8000e8e: 4b8b ldr r3, [pc, #556] ; (80010bc ) 8000e90: 69db ldr r3, [r3, #28] 8000e92: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 8000e96: 2b00 cmp r3, #0 8000e98: d10d bne.n 8000eb6 { __HAL_RCC_PWR_CLK_ENABLE(); 8000e9a: 4b88 ldr r3, [pc, #544] ; (80010bc ) 8000e9c: 69db ldr r3, [r3, #28] 8000e9e: 4a87 ldr r2, [pc, #540] ; (80010bc ) 8000ea0: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 8000ea4: 61d3 str r3, [r2, #28] 8000ea6: 4b85 ldr r3, [pc, #532] ; (80010bc ) 8000ea8: 69db ldr r3, [r3, #28] 8000eaa: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 8000eae: 60bb str r3, [r7, #8] 8000eb0: 68bb ldr r3, [r7, #8] pwrclkchanged = SET; 8000eb2: 2301 movs r3, #1 8000eb4: 75fb strb r3, [r7, #23] } if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8000eb6: 4b82 ldr r3, [pc, #520] ; (80010c0 ) 8000eb8: 681b ldr r3, [r3, #0] 8000eba: f403 7380 and.w r3, r3, #256 ; 0x100 8000ebe: 2b00 cmp r3, #0 8000ec0: d118 bne.n 8000ef4 { /* Enable write access to Backup domain */ SET_BIT(PWR->CR, PWR_CR_DBP); 8000ec2: 4b7f ldr r3, [pc, #508] ; (80010c0 ) 8000ec4: 681b ldr r3, [r3, #0] 8000ec6: 4a7e ldr r2, [pc, #504] ; (80010c0 ) 8000ec8: f443 7380 orr.w r3, r3, #256 ; 0x100 8000ecc: 6013 str r3, [r2, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 8000ece: f7ff fbf1 bl 80006b4 8000ed2: 6138 str r0, [r7, #16] while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8000ed4: e008 b.n 8000ee8 { if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 8000ed6: f7ff fbed bl 80006b4 8000eda: 4602 mov r2, r0 8000edc: 693b ldr r3, [r7, #16] 8000ede: 1ad3 subs r3, r2, r3 8000ee0: 2b64 cmp r3, #100 ; 0x64 8000ee2: d901 bls.n 8000ee8 { return HAL_TIMEOUT; 8000ee4: 2303 movs r3, #3 8000ee6: e103 b.n 80010f0 while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8000ee8: 4b75 ldr r3, [pc, #468] ; (80010c0 ) 8000eea: 681b ldr r3, [r3, #0] 8000eec: f403 7380 and.w r3, r3, #256 ; 0x100 8000ef0: 2b00 cmp r3, #0 8000ef2: d0f0 beq.n 8000ed6 } } } /* Set the new LSE configuration -----------------------------------------*/ __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); 8000ef4: 687b ldr r3, [r7, #4] 8000ef6: 68db ldr r3, [r3, #12] 8000ef8: 2b01 cmp r3, #1 8000efa: d106 bne.n 8000f0a 8000efc: 4b6f ldr r3, [pc, #444] ; (80010bc ) 8000efe: 6a1b ldr r3, [r3, #32] 8000f00: 4a6e ldr r2, [pc, #440] ; (80010bc ) 8000f02: f043 0301 orr.w r3, r3, #1 8000f06: 6213 str r3, [r2, #32] 8000f08: e02d b.n 8000f66 8000f0a: 687b ldr r3, [r7, #4] 8000f0c: 68db ldr r3, [r3, #12] 8000f0e: 2b00 cmp r3, #0 8000f10: d10c bne.n 8000f2c 8000f12: 4b6a ldr r3, [pc, #424] ; (80010bc ) 8000f14: 6a1b ldr r3, [r3, #32] 8000f16: 4a69 ldr r2, [pc, #420] ; (80010bc ) 8000f18: f023 0301 bic.w r3, r3, #1 8000f1c: 6213 str r3, [r2, #32] 8000f1e: 4b67 ldr r3, [pc, #412] ; (80010bc ) 8000f20: 6a1b ldr r3, [r3, #32] 8000f22: 4a66 ldr r2, [pc, #408] ; (80010bc ) 8000f24: f023 0304 bic.w r3, r3, #4 8000f28: 6213 str r3, [r2, #32] 8000f2a: e01c b.n 8000f66 8000f2c: 687b ldr r3, [r7, #4] 8000f2e: 68db ldr r3, [r3, #12] 8000f30: 2b05 cmp r3, #5 8000f32: d10c bne.n 8000f4e 8000f34: 4b61 ldr r3, [pc, #388] ; (80010bc ) 8000f36: 6a1b ldr r3, [r3, #32] 8000f38: 4a60 ldr r2, [pc, #384] ; (80010bc ) 8000f3a: f043 0304 orr.w r3, r3, #4 8000f3e: 6213 str r3, [r2, #32] 8000f40: 4b5e ldr r3, [pc, #376] ; (80010bc ) 8000f42: 6a1b ldr r3, [r3, #32] 8000f44: 4a5d ldr r2, [pc, #372] ; (80010bc ) 8000f46: f043 0301 orr.w r3, r3, #1 8000f4a: 6213 str r3, [r2, #32] 8000f4c: e00b b.n 8000f66 8000f4e: 4b5b ldr r3, [pc, #364] ; (80010bc ) 8000f50: 6a1b ldr r3, [r3, #32] 8000f52: 4a5a ldr r2, [pc, #360] ; (80010bc ) 8000f54: f023 0301 bic.w r3, r3, #1 8000f58: 6213 str r3, [r2, #32] 8000f5a: 4b58 ldr r3, [pc, #352] ; (80010bc ) 8000f5c: 6a1b ldr r3, [r3, #32] 8000f5e: 4a57 ldr r2, [pc, #348] ; (80010bc ) 8000f60: f023 0304 bic.w r3, r3, #4 8000f64: 6213 str r3, [r2, #32] /* Check the LSE State */ if (RCC_OscInitStruct->LSEState != RCC_LSE_OFF) 8000f66: 687b ldr r3, [r7, #4] 8000f68: 68db ldr r3, [r3, #12] 8000f6a: 2b00 cmp r3, #0 8000f6c: d015 beq.n 8000f9a { /* Get Start Tick */ tickstart = HAL_GetTick(); 8000f6e: f7ff fba1 bl 80006b4 8000f72: 6138 str r0, [r7, #16] /* Wait till LSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 8000f74: e00a b.n 8000f8c { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 8000f76: f7ff fb9d bl 80006b4 8000f7a: 4602 mov r2, r0 8000f7c: 693b ldr r3, [r7, #16] 8000f7e: 1ad3 subs r3, r2, r3 8000f80: f241 3288 movw r2, #5000 ; 0x1388 8000f84: 4293 cmp r3, r2 8000f86: d901 bls.n 8000f8c { return HAL_TIMEOUT; 8000f88: 2303 movs r3, #3 8000f8a: e0b1 b.n 80010f0 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 8000f8c: 4b4b ldr r3, [pc, #300] ; (80010bc ) 8000f8e: 6a1b ldr r3, [r3, #32] 8000f90: f003 0302 and.w r3, r3, #2 8000f94: 2b00 cmp r3, #0 8000f96: d0ee beq.n 8000f76 8000f98: e014 b.n 8000fc4 } } else { /* Get Start Tick */ tickstart = HAL_GetTick(); 8000f9a: f7ff fb8b bl 80006b4 8000f9e: 6138 str r0, [r7, #16] /* Wait till LSE is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) 8000fa0: e00a b.n 8000fb8 { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 8000fa2: f7ff fb87 bl 80006b4 8000fa6: 4602 mov r2, r0 8000fa8: 693b ldr r3, [r7, #16] 8000faa: 1ad3 subs r3, r2, r3 8000fac: f241 3288 movw r2, #5000 ; 0x1388 8000fb0: 4293 cmp r3, r2 8000fb2: d901 bls.n 8000fb8 { return HAL_TIMEOUT; 8000fb4: 2303 movs r3, #3 8000fb6: e09b b.n 80010f0