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stm32-course-old/Examples/PWM_BUZZER/Debug/PWM_BUZZER.list

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PWM_BUZZER.elf: file format elf32-littlearm
Sections:
Idx Name Size VMA LMA File off Algn
0 .isr_vector 0000010c 08000000 08000000 00010000 2**0
CONTENTS, ALLOC, LOAD, READONLY, DATA
1 .text 00001e90 0800010c 0800010c 0001010c 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
2 .rodata 00000020 08001f9c 08001f9c 00011f9c 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
3 .ARM.extab 00000000 08001fbc 08001fbc 0002000c 2**0
CONTENTS
4 .ARM 00000000 08001fbc 08001fbc 0002000c 2**0
CONTENTS
5 .preinit_array 00000000 08001fbc 08001fbc 0002000c 2**0
CONTENTS, ALLOC, LOAD, DATA
6 .init_array 00000004 08001fbc 08001fbc 00011fbc 2**2
CONTENTS, ALLOC, LOAD, DATA
7 .fini_array 00000004 08001fc0 08001fc0 00011fc0 2**2
CONTENTS, ALLOC, LOAD, DATA
8 .data 0000000c 20000000 08001fc4 00020000 2**2
CONTENTS, ALLOC, LOAD, DATA
9 .bss 00000068 2000000c 08001fd0 0002000c 2**2
ALLOC
10 ._user_heap_stack 00000604 20000074 08001fd0 00020074 2**0
ALLOC
11 .ARM.attributes 00000029 00000000 00000000 0002000c 2**0
CONTENTS, READONLY
12 .debug_info 00007bb3 00000000 00000000 00020035 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
13 .debug_abbrev 000015ef 00000000 00000000 00027be8 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
14 .debug_aranges 00000958 00000000 00000000 000291d8 2**3
CONTENTS, READONLY, DEBUGGING, OCTETS
15 .debug_ranges 00000890 00000000 00000000 00029b30 2**3
CONTENTS, READONLY, DEBUGGING, OCTETS
16 .debug_macro 00016900 00000000 00000000 0002a3c0 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
17 .debug_line 00009f37 00000000 00000000 00040cc0 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
18 .debug_str 00083e29 00000000 00000000 0004abf7 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
19 .comment 00000050 00000000 00000000 000cea20 2**0
CONTENTS, READONLY
20 .debug_frame 000025d8 00000000 00000000 000cea70 2**2
CONTENTS, READONLY, DEBUGGING, OCTETS
Disassembly of section .text:
0800010c <__do_global_dtors_aux>:
800010c: b510 push {r4, lr}
800010e: 4c05 ldr r4, [pc, #20] ; (8000124 <__do_global_dtors_aux+0x18>)
8000110: 7823 ldrb r3, [r4, #0]
8000112: b933 cbnz r3, 8000122 <__do_global_dtors_aux+0x16>
8000114: 4b04 ldr r3, [pc, #16] ; (8000128 <__do_global_dtors_aux+0x1c>)
8000116: b113 cbz r3, 800011e <__do_global_dtors_aux+0x12>
8000118: 4804 ldr r0, [pc, #16] ; (800012c <__do_global_dtors_aux+0x20>)
800011a: f3af 8000 nop.w
800011e: 2301 movs r3, #1
8000120: 7023 strb r3, [r4, #0]
8000122: bd10 pop {r4, pc}
8000124: 2000000c .word 0x2000000c
8000128: 00000000 .word 0x00000000
800012c: 08001f84 .word 0x08001f84
08000130 <frame_dummy>:
8000130: b508 push {r3, lr}
8000132: 4b03 ldr r3, [pc, #12] ; (8000140 <frame_dummy+0x10>)
8000134: b11b cbz r3, 800013e <frame_dummy+0xe>
8000136: 4903 ldr r1, [pc, #12] ; (8000144 <frame_dummy+0x14>)
8000138: 4803 ldr r0, [pc, #12] ; (8000148 <frame_dummy+0x18>)
800013a: f3af 8000 nop.w
800013e: bd08 pop {r3, pc}
8000140: 00000000 .word 0x00000000
8000144: 20000010 .word 0x20000010
8000148: 08001f84 .word 0x08001f84
0800014c <MX_GPIO_Init>:
* Output
* EVENT_OUT
* EXTI
*/
void MX_GPIO_Init(void)
{
800014c: b580 push {r7, lr}
800014e: b088 sub sp, #32
8000150: af00 add r7, sp, #0
GPIO_InitTypeDef GPIO_InitStruct = {0};
8000152: f107 0310 add.w r3, r7, #16
8000156: 2200 movs r2, #0
8000158: 601a str r2, [r3, #0]
800015a: 605a str r2, [r3, #4]
800015c: 609a str r2, [r3, #8]
800015e: 60da str r2, [r3, #12]
/* GPIO Ports Clock Enable */
__HAL_RCC_GPIOD_CLK_ENABLE();
8000160: 4b20 ldr r3, [pc, #128] ; (80001e4 <MX_GPIO_Init+0x98>)
8000162: 699b ldr r3, [r3, #24]
8000164: 4a1f ldr r2, [pc, #124] ; (80001e4 <MX_GPIO_Init+0x98>)
8000166: f043 0320 orr.w r3, r3, #32
800016a: 6193 str r3, [r2, #24]
800016c: 4b1d ldr r3, [pc, #116] ; (80001e4 <MX_GPIO_Init+0x98>)
800016e: 699b ldr r3, [r3, #24]
8000170: f003 0320 and.w r3, r3, #32
8000174: 60fb str r3, [r7, #12]
8000176: 68fb ldr r3, [r7, #12]
__HAL_RCC_GPIOB_CLK_ENABLE();
8000178: 4b1a ldr r3, [pc, #104] ; (80001e4 <MX_GPIO_Init+0x98>)
800017a: 699b ldr r3, [r3, #24]
800017c: 4a19 ldr r2, [pc, #100] ; (80001e4 <MX_GPIO_Init+0x98>)
800017e: f043 0308 orr.w r3, r3, #8
8000182: 6193 str r3, [r2, #24]
8000184: 4b17 ldr r3, [pc, #92] ; (80001e4 <MX_GPIO_Init+0x98>)
8000186: 699b ldr r3, [r3, #24]
8000188: f003 0308 and.w r3, r3, #8
800018c: 60bb str r3, [r7, #8]
800018e: 68bb ldr r3, [r7, #8]
__HAL_RCC_GPIOA_CLK_ENABLE();
8000190: 4b14 ldr r3, [pc, #80] ; (80001e4 <MX_GPIO_Init+0x98>)
8000192: 699b ldr r3, [r3, #24]
8000194: 4a13 ldr r2, [pc, #76] ; (80001e4 <MX_GPIO_Init+0x98>)
8000196: f043 0304 orr.w r3, r3, #4
800019a: 6193 str r3, [r2, #24]
800019c: 4b11 ldr r3, [pc, #68] ; (80001e4 <MX_GPIO_Init+0x98>)
800019e: 699b ldr r3, [r3, #24]
80001a0: f003 0304 and.w r3, r3, #4
80001a4: 607b str r3, [r7, #4]
80001a6: 687b ldr r3, [r7, #4]
/*Configure GPIO pin : PtPin */
GPIO_InitStruct.Pin = KEY1_Pin;
80001a8: f44f 5380 mov.w r3, #4096 ; 0x1000
80001ac: 613b str r3, [r7, #16]
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
80001ae: 2300 movs r3, #0
80001b0: 617b str r3, [r7, #20]
GPIO_InitStruct.Pull = GPIO_NOPULL;
80001b2: 2300 movs r3, #0
80001b4: 61bb str r3, [r7, #24]
HAL_GPIO_Init(KEY1_GPIO_Port, &GPIO_InitStruct);
80001b6: f107 0310 add.w r3, r7, #16
80001ba: 4619 mov r1, r3
80001bc: 480a ldr r0, [pc, #40] ; (80001e8 <MX_GPIO_Init+0x9c>)
80001be: f000 fb63 bl 8000888 <HAL_GPIO_Init>
/*Configure GPIO pin : PtPin */
GPIO_InitStruct.Pin = KEY2_Pin;
80001c2: f44f 5300 mov.w r3, #8192 ; 0x2000
80001c6: 613b str r3, [r7, #16]
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
80001c8: 2300 movs r3, #0
80001ca: 617b str r3, [r7, #20]
GPIO_InitStruct.Pull = GPIO_PULLUP;
80001cc: 2301 movs r3, #1
80001ce: 61bb str r3, [r7, #24]
HAL_GPIO_Init(KEY2_GPIO_Port, &GPIO_InitStruct);
80001d0: f107 0310 add.w r3, r7, #16
80001d4: 4619 mov r1, r3
80001d6: 4804 ldr r0, [pc, #16] ; (80001e8 <MX_GPIO_Init+0x9c>)
80001d8: f000 fb56 bl 8000888 <HAL_GPIO_Init>
}
80001dc: bf00 nop
80001de: 3720 adds r7, #32
80001e0: 46bd mov sp, r7
80001e2: bd80 pop {r7, pc}
80001e4: 40021000 .word 0x40021000
80001e8: 40010c00 .word 0x40010c00
080001ec <main>:
/**
* @brief The application entry point.
* @retval int
*/
int main(void) {
80001ec: b580 push {r7, lr}
80001ee: af00 add r7, sp, #0
/* USER CODE END 1 */
/* MCU Configuration--------------------------------------------------------*/
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
HAL_Init();
80001f0: f000 f9e0 bl 80005b4 <HAL_Init>
/* USER CODE BEGIN Init */
/* USER CODE END Init */
/* Configure the system clock */
SystemClock_Config();
80001f4: f000 f846 bl 8000284 <SystemClock_Config>
/* USER CODE BEGIN SysInit */
/* USER CODE END SysInit */
/* Initialize all configured peripherals */
MX_GPIO_Init();
80001f8: f7ff ffa8 bl 800014c <MX_GPIO_Init>
MX_TIM4_Init();
80001fc: f000 f8ec bl 80003d8 <MX_TIM4_Init>
/* USER CODE BEGIN 2 */
HAL_TIM_PWM_Start(&htim4, TIM_CHANNEL_4);
8000200: 210c movs r1, #12
8000202: 481d ldr r0, [pc, #116] ; (8000278 <main+0x8c>)
8000204: f001 f96c bl 80014e0 <HAL_TIM_PWM_Start>
/* Infinite loop */
/* USER CODE BEGIN WHILE */
while (1) {
//如果按下KEY1，发出2kHz的音频
if (!HAL_GPIO_ReadPin(KEY1_GPIO_Port, KEY1_Pin)) {
8000208: f44f 5180 mov.w r1, #4096 ; 0x1000
800020c: 481b ldr r0, [pc, #108] ; (800027c <main+0x90>)
800020e: f000 fcbf bl 8000b90 <HAL_GPIO_ReadPin>
8000212: 4603 mov r3, r0
8000214: 2b00 cmp r3, #0
8000216: d10f bne.n 8000238 <main+0x4c>
//设置音频频率，频<EFBC8C>? = 1000/ARR（kHz<48>?
htim4.Instance->ARR = 500;
8000218: 4b17 ldr r3, [pc, #92] ; (8000278 <main+0x8c>)
800021a: 681b ldr r3, [r3, #0]
800021c: f44f 72fa mov.w r2, #500 ; 0x1f4
8000220: 62da str r2, [r3, #44] ; 0x2c
//设置占空比为20%
__HAL_TIM_SET_COMPARE(&htim4, TIM_CHANNEL_4,
8000222: 4b15 ldr r3, [pc, #84] ; (8000278 <main+0x8c>)
8000224: 681b ldr r3, [r3, #0]
8000226: 6ada ldr r2, [r3, #44] ; 0x2c
8000228: 4b13 ldr r3, [pc, #76] ; (8000278 <main+0x8c>)
800022a: 681b ldr r3, [r3, #0]
800022c: 4914 ldr r1, [pc, #80] ; (8000280 <main+0x94>)
800022e: fba1 1202 umull r1, r2, r1, r2
8000232: 0892 lsrs r2, r2, #2
8000234: 641a str r2, [r3, #64] ; 0x40
8000236: e01b b.n 8000270 <main+0x84>
htim4.Instance->ARR / 5);
}
//如果按下KEY2，发出3kHz的音频
else if (!HAL_GPIO_ReadPin(KEY2_GPIO_Port, KEY2_Pin)) {
8000238: f44f 5100 mov.w r1, #8192 ; 0x2000
800023c: 480f ldr r0, [pc, #60] ; (800027c <main+0x90>)
800023e: f000 fca7 bl 8000b90 <HAL_GPIO_ReadPin>
8000242: 4603 mov r3, r0
8000244: 2b00 cmp r3, #0
8000246: d10f bne.n 8000268 <main+0x7c>
//设置音频频率，频<EFBC8C>? = 1000/ARR（kHz<48>?
htim4.Instance->ARR = 334;
8000248: 4b0b ldr r3, [pc, #44] ; (8000278 <main+0x8c>)
800024a: 681b ldr r3, [r3, #0]
800024c: f44f 72a7 mov.w r2, #334 ; 0x14e
8000250: 62da str r2, [r3, #44] ; 0x2c
//设置占空比为20%
__HAL_TIM_SET_COMPARE(&htim4, TIM_CHANNEL_4,
8000252: 4b09 ldr r3, [pc, #36] ; (8000278 <main+0x8c>)
8000254: 681b ldr r3, [r3, #0]
8000256: 6ada ldr r2, [r3, #44] ; 0x2c
8000258: 4b07 ldr r3, [pc, #28] ; (8000278 <main+0x8c>)
800025a: 681b ldr r3, [r3, #0]
800025c: 4908 ldr r1, [pc, #32] ; (8000280 <main+0x94>)
800025e: fba1 1202 umull r1, r2, r1, r2
8000262: 0892 lsrs r2, r2, #2
8000264: 641a str r2, [r3, #64] ; 0x40
8000266: e003 b.n 8000270 <main+0x84>
htim4.Instance->ARR / 5);
}
//如果没有按键被按下，不发声
else {
//设置占空比为0%，不发声
__HAL_TIM_SET_COMPARE(&htim4, TIM_CHANNEL_4, 0);
8000268: 4b03 ldr r3, [pc, #12] ; (8000278 <main+0x8c>)
800026a: 681b ldr r3, [r3, #0]
800026c: 2200 movs r2, #0
800026e: 641a str r2, [r3, #64] ; 0x40
}
HAL_Delay(100);
8000270: 2064 movs r0, #100 ; 0x64
8000272: f000 fa01 bl 8000678 <HAL_Delay>
if (!HAL_GPIO_ReadPin(KEY1_GPIO_Port, KEY1_Pin)) {
8000276: e7c7 b.n 8000208 <main+0x1c>
8000278: 20000028 .word 0x20000028
800027c: 40010c00 .word 0x40010c00
8000280: cccccccd .word 0xcccccccd
08000284 <SystemClock_Config>:
/**
* @brief System Clock Configuration
* @retval None
*/
void SystemClock_Config(void) {
8000284: b580 push {r7, lr}
8000286: b090 sub sp, #64 ; 0x40
8000288: af00 add r7, sp, #0
RCC_OscInitTypeDef RCC_OscInitStruct = { 0 };
800028a: f107 0318 add.w r3, r7, #24
800028e: 2228 movs r2, #40 ; 0x28
8000290: 2100 movs r1, #0
8000292: 4618 mov r0, r3
8000294: f001 fe6e bl 8001f74 <memset>
RCC_ClkInitTypeDef RCC_ClkInitStruct = { 0 };
8000298: 1d3b adds r3, r7, #4
800029a: 2200 movs r2, #0
800029c: 601a str r2, [r3, #0]
800029e: 605a str r2, [r3, #4]
80002a0: 609a str r2, [r3, #8]
80002a2: 60da str r2, [r3, #12]
80002a4: 611a str r2, [r3, #16]
/** Initializes the RCC Oscillators according to the specified parameters
* in the RCC_OscInitTypeDef structure.
*/
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
80002a6: 2301 movs r3, #1
80002a8: 61bb str r3, [r7, #24]
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
80002aa: f44f 3380 mov.w r3, #65536 ; 0x10000
80002ae: 61fb str r3, [r7, #28]
RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV1;
80002b0: 2300 movs r3, #0
80002b2: 623b str r3, [r7, #32]
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
80002b4: 2301 movs r3, #1
80002b6: 62bb str r3, [r7, #40] ; 0x28
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
80002b8: 2302 movs r3, #2
80002ba: 637b str r3, [r7, #52] ; 0x34
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
80002bc: f44f 3380 mov.w r3, #65536 ; 0x10000
80002c0: 63bb str r3, [r7, #56] ; 0x38
RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9;
80002c2: f44f 13e0 mov.w r3, #1835008 ; 0x1c0000
80002c6: 63fb str r3, [r7, #60] ; 0x3c
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
80002c8: f107 0318 add.w r3, r7, #24
80002cc: 4618 mov r0, r3
80002ce: f000 fc77 bl 8000bc0 <HAL_RCC_OscConfig>
80002d2: 4603 mov r3, r0
80002d4: 2b00 cmp r3, #0
80002d6: d001 beq.n 80002dc <SystemClock_Config+0x58>
Error_Handler();
80002d8: f000 f819 bl 800030e <Error_Handler>
}
/** Initializes the CPU, AHB and APB buses clocks
*/
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
80002dc: 230f movs r3, #15
80002de: 607b str r3, [r7, #4]
| RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
80002e0: 2302 movs r3, #2
80002e2: 60bb str r3, [r7, #8]
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
80002e4: 2300 movs r3, #0
80002e6: 60fb str r3, [r7, #12]
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
80002e8: f44f 6380 mov.w r3, #1024 ; 0x400
80002ec: 613b str r3, [r7, #16]
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
80002ee: 2300 movs r3, #0
80002f0: 617b str r3, [r7, #20]
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) {
80002f2: 1d3b adds r3, r7, #4
80002f4: 2102 movs r1, #2
80002f6: 4618 mov r0, r3
80002f8: f000 fee4 bl 80010c4 <HAL_RCC_ClockConfig>
80002fc: 4603 mov r3, r0
80002fe: 2b00 cmp r3, #0
8000300: d001 beq.n 8000306 <SystemClock_Config+0x82>
Error_Handler();
8000302: f000 f804 bl 800030e <Error_Handler>
}
}
8000306: bf00 nop
8000308: 3740 adds r7, #64 ; 0x40
800030a: 46bd mov sp, r7
800030c: bd80 pop {r7, pc}
0800030e <Error_Handler>:
/**
* @brief This function is executed in case of error occurrence.
* @retval None
*/
void Error_Handler(void) {
800030e: b480 push {r7}
8000310: af00 add r7, sp, #0
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__STATIC_FORCEINLINE void __disable_irq(void)
{
__ASM volatile ("cpsid i" : : : "memory");
8000312: b672 cpsid i
}
8000314: bf00 nop
/* USER CODE BEGIN Error_Handler_Debug */
/* User can add his own implementation to report the HAL error return state */
__disable_irq();
while (1) {
8000316: e7fe b.n 8000316 <Error_Handler+0x8>
08000318 <HAL_MspInit>:
/* USER CODE END 0 */
/**
* Initializes the Global MSP.
*/
void HAL_MspInit(void)
{
8000318: b480 push {r7}
800031a: b085 sub sp, #20
800031c: af00 add r7, sp, #0
/* USER CODE BEGIN MspInit 0 */
/* USER CODE END MspInit 0 */
__HAL_RCC_AFIO_CLK_ENABLE();
800031e: 4b15 ldr r3, [pc, #84] ; (8000374 <HAL_MspInit+0x5c>)
8000320: 699b ldr r3, [r3, #24]
8000322: 4a14 ldr r2, [pc, #80] ; (8000374 <HAL_MspInit+0x5c>)
8000324: f043 0301 orr.w r3, r3, #1
8000328: 6193 str r3, [r2, #24]
800032a: 4b12 ldr r3, [pc, #72] ; (8000374 <HAL_MspInit+0x5c>)
800032c: 699b ldr r3, [r3, #24]
800032e: f003 0301 and.w r3, r3, #1
8000332: 60bb str r3, [r7, #8]
8000334: 68bb ldr r3, [r7, #8]
__HAL_RCC_PWR_CLK_ENABLE();
8000336: 4b0f ldr r3, [pc, #60] ; (8000374 <HAL_MspInit+0x5c>)
8000338: 69db ldr r3, [r3, #28]
800033a: 4a0e ldr r2, [pc, #56] ; (8000374 <HAL_MspInit+0x5c>)
800033c: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
8000340: 61d3 str r3, [r2, #28]
8000342: 4b0c ldr r3, [pc, #48] ; (8000374 <HAL_MspInit+0x5c>)
8000344: 69db ldr r3, [r3, #28]
8000346: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
800034a: 607b str r3, [r7, #4]
800034c: 687b ldr r3, [r7, #4]
/* System interrupt init*/
/** NOJTAG: JTAG-DP Disabled and SW-DP Enabled
*/
__HAL_AFIO_REMAP_SWJ_NOJTAG();
800034e: 4b0a ldr r3, [pc, #40] ; (8000378 <HAL_MspInit+0x60>)
8000350: 685b ldr r3, [r3, #4]
8000352: 60fb str r3, [r7, #12]
8000354: 68fb ldr r3, [r7, #12]
8000356: f023 63e0 bic.w r3, r3, #117440512 ; 0x7000000
800035a: 60fb str r3, [r7, #12]
800035c: 68fb ldr r3, [r7, #12]
800035e: f043 7300 orr.w r3, r3, #33554432 ; 0x2000000
8000362: 60fb str r3, [r7, #12]
8000364: 4a04 ldr r2, [pc, #16] ; (8000378 <HAL_MspInit+0x60>)
8000366: 68fb ldr r3, [r7, #12]
8000368: 6053 str r3, [r2, #4]
/* USER CODE BEGIN MspInit 1 */
/* USER CODE END MspInit 1 */
}
800036a: bf00 nop
800036c: 3714 adds r7, #20
800036e: 46bd mov sp, r7
8000370: bc80 pop {r7}
8000372: 4770 bx lr
8000374: 40021000 .word 0x40021000
8000378: 40010000 .word 0x40010000
0800037c <NMI_Handler>:
/******************************************************************************/
/**
* @brief This function handles Non maskable interrupt.
*/
void NMI_Handler(void)
{
800037c: b480 push {r7}
800037e: af00 add r7, sp, #0
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
/* USER CODE END NonMaskableInt_IRQn 0 */
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
while (1)
8000380: e7fe b.n 8000380 <NMI_Handler+0x4>
08000382 <HardFault_Handler>:
/**
* @brief This function handles Hard fault interrupt.
*/
void HardFault_Handler(void)
{
8000382: b480 push {r7}
8000384: af00 add r7, sp, #0
/* USER CODE BEGIN HardFault_IRQn 0 */
/* USER CODE END HardFault_IRQn 0 */
while (1)
8000386: e7fe b.n 8000386 <HardFault_Handler+0x4>
08000388 <MemManage_Handler>:
/**
* @brief This function handles Memory management fault.
*/
void MemManage_Handler(void)
{
8000388: b480 push {r7}
800038a: af00 add r7, sp, #0
/* USER CODE BEGIN MemoryManagement_IRQn 0 */
/* USER CODE END MemoryManagement_IRQn 0 */
while (1)
800038c: e7fe b.n 800038c <MemManage_Handler+0x4>
0800038e <BusFault_Handler>:
/**
* @brief This function handles Prefetch fault, memory access fault.
*/
void BusFault_Handler(void)
{
800038e: b480 push {r7}
8000390: af00 add r7, sp, #0
/* USER CODE BEGIN BusFault_IRQn 0 */
/* USER CODE END BusFault_IRQn 0 */
while (1)
8000392: e7fe b.n 8000392 <BusFault_Handler+0x4>
08000394 <UsageFault_Handler>:
/**
* @brief This function handles Undefined instruction or illegal state.
*/
void UsageFault_Handler(void)
{
8000394: b480 push {r7}
8000396: af00 add r7, sp, #0
/* USER CODE BEGIN UsageFault_IRQn 0 */
/* USER CODE END UsageFault_IRQn 0 */
while (1)
8000398: e7fe b.n 8000398 <UsageFault_Handler+0x4>
0800039a <SVC_Handler>:
/**
* @brief This function handles System service call via SWI instruction.
*/
void SVC_Handler(void)
{
800039a: b480 push {r7}
800039c: af00 add r7, sp, #0
/* USER CODE END SVCall_IRQn 0 */
/* USER CODE BEGIN SVCall_IRQn 1 */
/* USER CODE END SVCall_IRQn 1 */
}
800039e: bf00 nop
80003a0: 46bd mov sp, r7
80003a2: bc80 pop {r7}
80003a4: 4770 bx lr
080003a6 <DebugMon_Handler>:
/**
* @brief This function handles Debug monitor.
*/
void DebugMon_Handler(void)
{
80003a6: b480 push {r7}
80003a8: af00 add r7, sp, #0
/* USER CODE END DebugMonitor_IRQn 0 */
/* USER CODE BEGIN DebugMonitor_IRQn 1 */
/* USER CODE END DebugMonitor_IRQn 1 */
}
80003aa: bf00 nop
80003ac: 46bd mov sp, r7
80003ae: bc80 pop {r7}
80003b0: 4770 bx lr
080003b2 <PendSV_Handler>:
/**
* @brief This function handles Pendable request for system service.
*/
void PendSV_Handler(void)
{
80003b2: b480 push {r7}
80003b4: af00 add r7, sp, #0
/* USER CODE END PendSV_IRQn 0 */
/* USER CODE BEGIN PendSV_IRQn 1 */
/* USER CODE END PendSV_IRQn 1 */
}
80003b6: bf00 nop
80003b8: 46bd mov sp, r7
80003ba: bc80 pop {r7}
80003bc: 4770 bx lr
080003be <SysTick_Handler>:
/**
* @brief This function handles System tick timer.
*/
void SysTick_Handler(void)
{
80003be: b580 push {r7, lr}
80003c0: af00 add r7, sp, #0
/* USER CODE BEGIN SysTick_IRQn 0 */
/* USER CODE END SysTick_IRQn 0 */
HAL_IncTick();
80003c2: f000 f93d bl 8000640 <HAL_IncTick>
/* USER CODE BEGIN SysTick_IRQn 1 */
/* USER CODE END SysTick_IRQn 1 */
}
80003c6: bf00 nop
80003c8: bd80 pop {r7, pc}
080003ca <SystemInit>:
* @note This function should be used only after reset.
* @param None
* @retval None
*/
void SystemInit (void)
{
80003ca: b480 push {r7}
80003cc: af00 add r7, sp, #0
/* Configure the Vector Table location -------------------------------------*/
#if defined(USER_VECT_TAB_ADDRESS)
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
#endif /* USER_VECT_TAB_ADDRESS */
}
80003ce: bf00 nop
80003d0: 46bd mov sp, r7
80003d2: bc80 pop {r7}
80003d4: 4770 bx lr
...
080003d8 <MX_TIM4_Init>:
TIM_HandleTypeDef htim4;
/* TIM4 init function */
void MX_TIM4_Init(void)
{
80003d8: b580 push {r7, lr}
80003da: b08e sub sp, #56 ; 0x38
80003dc: af00 add r7, sp, #0
/* USER CODE BEGIN TIM4_Init 0 */
/* USER CODE END TIM4_Init 0 */
TIM_ClockConfigTypeDef sClockSourceConfig = {0};
80003de: f107 0328 add.w r3, r7, #40 ; 0x28
80003e2: 2200 movs r2, #0
80003e4: 601a str r2, [r3, #0]
80003e6: 605a str r2, [r3, #4]
80003e8: 609a str r2, [r3, #8]
80003ea: 60da str r2, [r3, #12]
TIM_MasterConfigTypeDef sMasterConfig = {0};
80003ec: f107 0320 add.w r3, r7, #32
80003f0: 2200 movs r2, #0
80003f2: 601a str r2, [r3, #0]
80003f4: 605a str r2, [r3, #4]
TIM_OC_InitTypeDef sConfigOC = {0};
80003f6: 1d3b adds r3, r7, #4
80003f8: 2200 movs r2, #0
80003fa: 601a str r2, [r3, #0]
80003fc: 605a str r2, [r3, #4]
80003fe: 609a str r2, [r3, #8]
8000400: 60da str r2, [r3, #12]
8000402: 611a str r2, [r3, #16]
8000404: 615a str r2, [r3, #20]
8000406: 619a str r2, [r3, #24]
/* USER CODE BEGIN TIM4_Init 1 */
/* USER CODE END TIM4_Init 1 */
htim4.Instance = TIM4;
8000408: 4b2c ldr r3, [pc, #176] ; (80004bc <MX_TIM4_Init+0xe4>)
800040a: 4a2d ldr r2, [pc, #180] ; (80004c0 <MX_TIM4_Init+0xe8>)
800040c: 601a str r2, [r3, #0]
htim4.Init.Prescaler = 72-1;
800040e: 4b2b ldr r3, [pc, #172] ; (80004bc <MX_TIM4_Init+0xe4>)
8000410: 2247 movs r2, #71 ; 0x47
8000412: 605a str r2, [r3, #4]
htim4.Init.CounterMode = TIM_COUNTERMODE_UP;
8000414: 4b29 ldr r3, [pc, #164] ; (80004bc <MX_TIM4_Init+0xe4>)
8000416: 2200 movs r2, #0
8000418: 609a str r2, [r3, #8]
htim4.Init.Period = 500-1;
800041a: 4b28 ldr r3, [pc, #160] ; (80004bc <MX_TIM4_Init+0xe4>)
800041c: f240 12f3 movw r2, #499 ; 0x1f3
8000420: 60da str r2, [r3, #12]
htim4.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
8000422: 4b26 ldr r3, [pc, #152] ; (80004bc <MX_TIM4_Init+0xe4>)
8000424: 2200 movs r2, #0
8000426: 611a str r2, [r3, #16]
htim4.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
8000428: 4b24 ldr r3, [pc, #144] ; (80004bc <MX_TIM4_Init+0xe4>)
800042a: 2200 movs r2, #0
800042c: 619a str r2, [r3, #24]
if (HAL_TIM_Base_Init(&htim4) != HAL_OK)
800042e: 4823 ldr r0, [pc, #140] ; (80004bc <MX_TIM4_Init+0xe4>)
8000430: f000 ffae bl 8001390 <HAL_TIM_Base_Init>
8000434: 4603 mov r3, r0
8000436: 2b00 cmp r3, #0
8000438: d001 beq.n 800043e <MX_TIM4_Init+0x66>
{
Error_Handler();
800043a: f7ff ff68 bl 800030e <Error_Handler>
}
sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
800043e: f44f 5380 mov.w r3, #4096 ; 0x1000
8000442: 62bb str r3, [r7, #40] ; 0x28
if (HAL_TIM_ConfigClockSource(&htim4, &sClockSourceConfig) != HAL_OK)
8000444: f107 0328 add.w r3, r7, #40 ; 0x28
8000448: 4619 mov r1, r3
800044a: 481c ldr r0, [pc, #112] ; (80004bc <MX_TIM4_Init+0xe4>)
800044c: f001 f9a8 bl 80017a0 <HAL_TIM_ConfigClockSource>
8000450: 4603 mov r3, r0
8000452: 2b00 cmp r3, #0
8000454: d001 beq.n 800045a <MX_TIM4_Init+0x82>
{
Error_Handler();
8000456: f7ff ff5a bl 800030e <Error_Handler>
}
if (HAL_TIM_PWM_Init(&htim4) != HAL_OK)
800045a: 4818 ldr r0, [pc, #96] ; (80004bc <MX_TIM4_Init+0xe4>)
800045c: f000 ffe7 bl 800142e <HAL_TIM_PWM_Init>
8000460: 4603 mov r3, r0
8000462: 2b00 cmp r3, #0
8000464: d001 beq.n 800046a <MX_TIM4_Init+0x92>
{
Error_Handler();
8000466: f7ff ff52 bl 800030e <Error_Handler>
}
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
800046a: 2300 movs r3, #0
800046c: 623b str r3, [r7, #32]
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
800046e: 2300 movs r3, #0
8000470: 627b str r3, [r7, #36] ; 0x24
if (HAL_TIMEx_MasterConfigSynchronization(&htim4, &sMasterConfig) != HAL_OK)
8000472: f107 0320 add.w r3, r7, #32
8000476: 4619 mov r1, r3
8000478: 4810 ldr r0, [pc, #64] ; (80004bc <MX_TIM4_Init+0xe4>)
800047a: f001 fcf9 bl 8001e70 <HAL_TIMEx_MasterConfigSynchronization>
800047e: 4603 mov r3, r0
8000480: 2b00 cmp r3, #0
8000482: d001 beq.n 8000488 <MX_TIM4_Init+0xb0>
{
Error_Handler();
8000484: f7ff ff43 bl 800030e <Error_Handler>
}
sConfigOC.OCMode = TIM_OCMODE_PWM1;
8000488: 2360 movs r3, #96 ; 0x60
800048a: 607b str r3, [r7, #4]
sConfigOC.Pulse = 0;
800048c: 2300 movs r3, #0
800048e: 60bb str r3, [r7, #8]
sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
8000490: 2300 movs r3, #0
8000492: 60fb str r3, [r7, #12]
sConfigOC.OCFastMode = TIM_OCFAST_DISABLE;
8000494: 2300 movs r3, #0
8000496: 617b str r3, [r7, #20]
if (HAL_TIM_PWM_ConfigChannel(&htim4, &sConfigOC, TIM_CHANNEL_4) != HAL_OK)
8000498: 1d3b adds r3, r7, #4
800049a: 220c movs r2, #12
800049c: 4619 mov r1, r3
800049e: 4807 ldr r0, [pc, #28] ; (80004bc <MX_TIM4_Init+0xe4>)
80004a0: f001 f8c0 bl 8001624 <HAL_TIM_PWM_ConfigChannel>
80004a4: 4603 mov r3, r0
80004a6: 2b00 cmp r3, #0
80004a8: d001 beq.n 80004ae <MX_TIM4_Init+0xd6>
{
Error_Handler();
80004aa: f7ff ff30 bl 800030e <Error_Handler>
}
/* USER CODE BEGIN TIM4_Init 2 */
/* USER CODE END TIM4_Init 2 */
HAL_TIM_MspPostInit(&htim4);
80004ae: 4803 ldr r0, [pc, #12] ; (80004bc <MX_TIM4_Init+0xe4>)
80004b0: f000 f826 bl 8000500 <HAL_TIM_MspPostInit>
}
80004b4: bf00 nop
80004b6: 3738 adds r7, #56 ; 0x38
80004b8: 46bd mov sp, r7
80004ba: bd80 pop {r7, pc}
80004bc: 20000028 .word 0x20000028
80004c0: 40000800 .word 0x40000800
080004c4 <HAL_TIM_Base_MspInit>:
void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* tim_baseHandle)
{
80004c4: b480 push {r7}
80004c6: b085 sub sp, #20
80004c8: af00 add r7, sp, #0
80004ca: 6078 str r0, [r7, #4]
if(tim_baseHandle->Instance==TIM4)
80004cc: 687b ldr r3, [r7, #4]
80004ce: 681b ldr r3, [r3, #0]
80004d0: 4a09 ldr r2, [pc, #36] ; (80004f8 <HAL_TIM_Base_MspInit+0x34>)
80004d2: 4293 cmp r3, r2
80004d4: d10b bne.n 80004ee <HAL_TIM_Base_MspInit+0x2a>
{
/* USER CODE BEGIN TIM4_MspInit 0 */
/* USER CODE END TIM4_MspInit 0 */
/* TIM4 clock enable */
__HAL_RCC_TIM4_CLK_ENABLE();
80004d6: 4b09 ldr r3, [pc, #36] ; (80004fc <HAL_TIM_Base_MspInit+0x38>)
80004d8: 69db ldr r3, [r3, #28]
80004da: 4a08 ldr r2, [pc, #32] ; (80004fc <HAL_TIM_Base_MspInit+0x38>)
80004dc: f043 0304 orr.w r3, r3, #4
80004e0: 61d3 str r3, [r2, #28]
80004e2: 4b06 ldr r3, [pc, #24] ; (80004fc <HAL_TIM_Base_MspInit+0x38>)
80004e4: 69db ldr r3, [r3, #28]
80004e6: f003 0304 and.w r3, r3, #4
80004ea: 60fb str r3, [r7, #12]
80004ec: 68fb ldr r3, [r7, #12]
/* USER CODE BEGIN TIM4_MspInit 1 */
/* USER CODE END TIM4_MspInit 1 */
}
}
80004ee: bf00 nop
80004f0: 3714 adds r7, #20
80004f2: 46bd mov sp, r7
80004f4: bc80 pop {r7}
80004f6: 4770 bx lr
80004f8: 40000800 .word 0x40000800
80004fc: 40021000 .word 0x40021000
08000500 <HAL_TIM_MspPostInit>:
void HAL_TIM_MspPostInit(TIM_HandleTypeDef* timHandle)
{
8000500: b580 push {r7, lr}
8000502: b088 sub sp, #32
8000504: af00 add r7, sp, #0
8000506: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
8000508: f107 0310 add.w r3, r7, #16
800050c: 2200 movs r2, #0
800050e: 601a str r2, [r3, #0]
8000510: 605a str r2, [r3, #4]
8000512: 609a str r2, [r3, #8]
8000514: 60da str r2, [r3, #12]
if(timHandle->Instance==TIM4)
8000516: 687b ldr r3, [r7, #4]
8000518: 681b ldr r3, [r3, #0]
800051a: 4a10 ldr r2, [pc, #64] ; (800055c <HAL_TIM_MspPostInit+0x5c>)
800051c: 4293 cmp r3, r2
800051e: d118 bne.n 8000552 <HAL_TIM_MspPostInit+0x52>
{
/* USER CODE BEGIN TIM4_MspPostInit 0 */
/* USER CODE END TIM4_MspPostInit 0 */
__HAL_RCC_GPIOB_CLK_ENABLE();
8000520: 4b0f ldr r3, [pc, #60] ; (8000560 <HAL_TIM_MspPostInit+0x60>)
8000522: 699b ldr r3, [r3, #24]
8000524: 4a0e ldr r2, [pc, #56] ; (8000560 <HAL_TIM_MspPostInit+0x60>)
8000526: f043 0308 orr.w r3, r3, #8
800052a: 6193 str r3, [r2, #24]
800052c: 4b0c ldr r3, [pc, #48] ; (8000560 <HAL_TIM_MspPostInit+0x60>)
800052e: 699b ldr r3, [r3, #24]
8000530: f003 0308 and.w r3, r3, #8
8000534: 60fb str r3, [r7, #12]
8000536: 68fb ldr r3, [r7, #12]
/**TIM4 GPIO Configuration
PB9 ------> TIM4_CH4
*/
GPIO_InitStruct.Pin = GPIO_PIN_9;
8000538: f44f 7300 mov.w r3, #512 ; 0x200
800053c: 613b str r3, [r7, #16]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
800053e: 2302 movs r3, #2
8000540: 617b str r3, [r7, #20]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8000542: 2302 movs r3, #2
8000544: 61fb str r3, [r7, #28]
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
8000546: f107 0310 add.w r3, r7, #16
800054a: 4619 mov r1, r3
800054c: 4805 ldr r0, [pc, #20] ; (8000564 <HAL_TIM_MspPostInit+0x64>)
800054e: f000 f99b bl 8000888 <HAL_GPIO_Init>
/* USER CODE BEGIN TIM4_MspPostInit 1 */
/* USER CODE END TIM4_MspPostInit 1 */
}
}
8000552: bf00 nop
8000554: 3720 adds r7, #32
8000556: 46bd mov sp, r7
8000558: bd80 pop {r7, pc}
800055a: bf00 nop
800055c: 40000800 .word 0x40000800
8000560: 40021000 .word 0x40021000
8000564: 40010c00 .word 0x40010c00
08000568 <Reset_Handler>:
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
8000568: 480c ldr r0, [pc, #48] ; (800059c <LoopFillZerobss+0x12>)
ldr r1, =_edata
800056a: 490d ldr r1, [pc, #52] ; (80005a0 <LoopFillZerobss+0x16>)
ldr r2, =_sidata
800056c: 4a0d ldr r2, [pc, #52] ; (80005a4 <LoopFillZerobss+0x1a>)
movs r3, #0
800056e: 2300 movs r3, #0
b LoopCopyDataInit
8000570: e002 b.n 8000578 <LoopCopyDataInit>
08000572 <CopyDataInit>:
CopyDataInit:
ldr r4, [r2, r3]
8000572: 58d4 ldr r4, [r2, r3]
str r4, [r0, r3]
8000574: 50c4 str r4, [r0, r3]
adds r3, r3, #4
8000576: 3304 adds r3, #4
08000578 <LoopCopyDataInit>:
LoopCopyDataInit:
adds r4, r0, r3
8000578: 18c4 adds r4, r0, r3
cmp r4, r1
800057a: 428c cmp r4, r1
bcc CopyDataInit
800057c: d3f9 bcc.n 8000572 <CopyDataInit>
/* Zero fill the bss segment. */
ldr r2, =_sbss
800057e: 4a0a ldr r2, [pc, #40] ; (80005a8 <LoopFillZerobss+0x1e>)
ldr r4, =_ebss
8000580: 4c0a ldr r4, [pc, #40] ; (80005ac <LoopFillZerobss+0x22>)
movs r3, #0
8000582: 2300 movs r3, #0
b LoopFillZerobss
8000584: e001 b.n 800058a <LoopFillZerobss>
08000586 <FillZerobss>:
FillZerobss:
str r3, [r2]
8000586: 6013 str r3, [r2, #0]
adds r2, r2, #4
8000588: 3204 adds r2, #4
0800058a <LoopFillZerobss>:
LoopFillZerobss:
cmp r2, r4
800058a: 42a2 cmp r2, r4
bcc FillZerobss
800058c: d3fb bcc.n 8000586 <FillZerobss>
/* Call the clock system intitialization function.*/
bl SystemInit
800058e: f7ff ff1c bl 80003ca <SystemInit>
/* Call static constructors */
bl __libc_init_array
8000592: f001 fccb bl 8001f2c <__libc_init_array>
/* Call the application's entry point.*/
bl main
8000596: f7ff fe29 bl 80001ec <main>
bx lr
800059a: 4770 bx lr
ldr r0, =_sdata
800059c: 20000000 .word 0x20000000
ldr r1, =_edata
80005a0: 2000000c .word 0x2000000c
ldr r2, =_sidata
80005a4: 08001fc4 .word 0x08001fc4
ldr r2, =_sbss
80005a8: 2000000c .word 0x2000000c
ldr r4, =_ebss
80005ac: 20000074 .word 0x20000074
080005b0 <ADC1_2_IRQHandler>:
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
80005b0: e7fe b.n 80005b0 <ADC1_2_IRQHandler>
...
080005b4 <HAL_Init>:
* need to ensure that the SysTick time base is always set to 1 millisecond
* to have correct HAL operation.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_Init(void)
{
80005b4: b580 push {r7, lr}
80005b6: af00 add r7, sp, #0
defined(STM32F102x6) || defined(STM32F102xB) || \
defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || \
defined(STM32F105xC) || defined(STM32F107xC)
/* Prefetch buffer is not available on value line devices */
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
80005b8: 4b08 ldr r3, [pc, #32] ; (80005dc <HAL_Init+0x28>)
80005ba: 681b ldr r3, [r3, #0]
80005bc: 4a07 ldr r2, [pc, #28] ; (80005dc <HAL_Init+0x28>)
80005be: f043 0310 orr.w r3, r3, #16
80005c2: 6013 str r3, [r2, #0]
#endif
#endif /* PREFETCH_ENABLE */
/* Set Interrupt Group Priority */
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
80005c4: 2003 movs r0, #3
80005c6: f000 f92b bl 8000820 <HAL_NVIC_SetPriorityGrouping>
/* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
HAL_InitTick(TICK_INT_PRIORITY);
80005ca: 200f movs r0, #15
80005cc: f000 f808 bl 80005e0 <HAL_InitTick>
/* Init the low level hardware */
HAL_MspInit();
80005d0: f7ff fea2 bl 8000318 <HAL_MspInit>
/* Return function status */
return HAL_OK;
80005d4: 2300 movs r3, #0
}
80005d6: 4618 mov r0, r3
80005d8: bd80 pop {r7, pc}
80005da: bf00 nop
80005dc: 40022000 .word 0x40022000
080005e0 <HAL_InitTick>:
* implementation in user file.
* @param TickPriority Tick interrupt priority.
* @retval HAL status
*/
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
80005e0: b580 push {r7, lr}
80005e2: b082 sub sp, #8
80005e4: af00 add r7, sp, #0
80005e6: 6078 str r0, [r7, #4]
/* Configure the SysTick to have interrupt in 1ms time basis*/
if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U)
80005e8: 4b12 ldr r3, [pc, #72] ; (8000634 <HAL_InitTick+0x54>)
80005ea: 681a ldr r2, [r3, #0]
80005ec: 4b12 ldr r3, [pc, #72] ; (8000638 <HAL_InitTick+0x58>)
80005ee: 781b ldrb r3, [r3, #0]
80005f0: 4619 mov r1, r3
80005f2: f44f 737a mov.w r3, #1000 ; 0x3e8
80005f6: fbb3 f3f1 udiv r3, r3, r1
80005fa: fbb2 f3f3 udiv r3, r2, r3
80005fe: 4618 mov r0, r3
8000600: f000 f935 bl 800086e <HAL_SYSTICK_Config>
8000604: 4603 mov r3, r0
8000606: 2b00 cmp r3, #0
8000608: d001 beq.n 800060e <HAL_InitTick+0x2e>
{
return HAL_ERROR;
800060a: 2301 movs r3, #1
800060c: e00e b.n 800062c <HAL_InitTick+0x4c>
}
/* Configure the SysTick IRQ priority */
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
800060e: 687b ldr r3, [r7, #4]
8000610: 2b0f cmp r3, #15
8000612: d80a bhi.n 800062a <HAL_InitTick+0x4a>
{
HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
8000614: 2200 movs r2, #0
8000616: 6879 ldr r1, [r7, #4]
8000618: f04f 30ff mov.w r0, #4294967295
800061c: f000 f90b bl 8000836 <HAL_NVIC_SetPriority>
uwTickPrio = TickPriority;
8000620: 4a06 ldr r2, [pc, #24] ; (800063c <HAL_InitTick+0x5c>)
8000622: 687b ldr r3, [r7, #4]
8000624: 6013 str r3, [r2, #0]
{
return HAL_ERROR;
}
/* Return function status */
return HAL_OK;
8000626: 2300 movs r3, #0
8000628: e000 b.n 800062c <HAL_InitTick+0x4c>
return HAL_ERROR;
800062a: 2301 movs r3, #1
}
800062c: 4618 mov r0, r3
800062e: 3708 adds r7, #8
8000630: 46bd mov sp, r7
8000632: bd80 pop {r7, pc}
8000634: 20000000 .word 0x20000000
8000638: 20000008 .word 0x20000008
800063c: 20000004 .word 0x20000004
08000640 <HAL_IncTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval None
*/
__weak void HAL_IncTick(void)
{
8000640: b480 push {r7}
8000642: af00 add r7, sp, #0
uwTick += uwTickFreq;
8000644: 4b05 ldr r3, [pc, #20] ; (800065c <HAL_IncTick+0x1c>)
8000646: 781b ldrb r3, [r3, #0]
8000648: 461a mov r2, r3
800064a: 4b05 ldr r3, [pc, #20] ; (8000660 <HAL_IncTick+0x20>)
800064c: 681b ldr r3, [r3, #0]
800064e: 4413 add r3, r2
8000650: 4a03 ldr r2, [pc, #12] ; (8000660 <HAL_IncTick+0x20>)
8000652: 6013 str r3, [r2, #0]
}
8000654: bf00 nop
8000656: 46bd mov sp, r7
8000658: bc80 pop {r7}
800065a: 4770 bx lr
800065c: 20000008 .word 0x20000008
8000660: 20000070 .word 0x20000070
08000664 <HAL_GetTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval tick value
*/
__weak uint32_t HAL_GetTick(void)
{
8000664: b480 push {r7}
8000666: af00 add r7, sp, #0
return uwTick;
8000668: 4b02 ldr r3, [pc, #8] ; (8000674 <HAL_GetTick+0x10>)
800066a: 681b ldr r3, [r3, #0]
}
800066c: 4618 mov r0, r3
800066e: 46bd mov sp, r7
8000670: bc80 pop {r7}
8000672: 4770 bx lr
8000674: 20000070 .word 0x20000070
08000678 <HAL_Delay>:
* implementations in user file.
* @param Delay specifies the delay time length, in milliseconds.
* @retval None
*/
__weak void HAL_Delay(uint32_t Delay)
{
8000678: b580 push {r7, lr}
800067a: b084 sub sp, #16
800067c: af00 add r7, sp, #0
800067e: 6078 str r0, [r7, #4]
uint32_t tickstart = HAL_GetTick();
8000680: f7ff fff0 bl 8000664 <HAL_GetTick>
8000684: 60b8 str r0, [r7, #8]
uint32_t wait = Delay;
8000686: 687b ldr r3, [r7, #4]
8000688: 60fb str r3, [r7, #12]
/* Add a freq to guarantee minimum wait */
if (wait < HAL_MAX_DELAY)
800068a: 68fb ldr r3, [r7, #12]
800068c: f1b3 3fff cmp.w r3, #4294967295
8000690: d005 beq.n 800069e <HAL_Delay+0x26>
{
wait += (uint32_t)(uwTickFreq);
8000692: 4b0a ldr r3, [pc, #40] ; (80006bc <HAL_Delay+0x44>)
8000694: 781b ldrb r3, [r3, #0]
8000696: 461a mov r2, r3
8000698: 68fb ldr r3, [r7, #12]
800069a: 4413 add r3, r2
800069c: 60fb str r3, [r7, #12]
}
while ((HAL_GetTick() - tickstart) < wait)
800069e: bf00 nop
80006a0: f7ff ffe0 bl 8000664 <HAL_GetTick>
80006a4: 4602 mov r2, r0
80006a6: 68bb ldr r3, [r7, #8]
80006a8: 1ad3 subs r3, r2, r3
80006aa: 68fa ldr r2, [r7, #12]
80006ac: 429a cmp r2, r3
80006ae: d8f7 bhi.n 80006a0 <HAL_Delay+0x28>
{
}
}
80006b0: bf00 nop
80006b2: bf00 nop
80006b4: 3710 adds r7, #16
80006b6: 46bd mov sp, r7
80006b8: bd80 pop {r7, pc}
80006ba: bf00 nop
80006bc: 20000008 .word 0x20000008
080006c0 <__NVIC_SetPriorityGrouping>:
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Priority grouping field.
*/
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
80006c0: b480 push {r7}
80006c2: b085 sub sp, #20
80006c4: af00 add r7, sp, #0
80006c6: 6078 str r0, [r7, #4]
uint32_t reg_value;
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
80006c8: 687b ldr r3, [r7, #4]
80006ca: f003 0307 and.w r3, r3, #7
80006ce: 60fb str r3, [r7, #12]
reg_value = SCB->AIRCR; /* read old register configuration */
80006d0: 4b0c ldr r3, [pc, #48] ; (8000704 <__NVIC_SetPriorityGrouping+0x44>)
80006d2: 68db ldr r3, [r3, #12]
80006d4: 60bb str r3, [r7, #8]
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
80006d6: 68ba ldr r2, [r7, #8]
80006d8: f64f 03ff movw r3, #63743 ; 0xf8ff
80006dc: 4013 ands r3, r2
80006de: 60bb str r3, [r7, #8]
reg_value = (reg_value |
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
(PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
80006e0: 68fb ldr r3, [r7, #12]
80006e2: 021a lsls r2, r3, #8
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
80006e4: 68bb ldr r3, [r7, #8]
80006e6: 4313 orrs r3, r2
reg_value = (reg_value |
80006e8: f043 63bf orr.w r3, r3, #100139008 ; 0x5f80000
80006ec: f443 3300 orr.w r3, r3, #131072 ; 0x20000
80006f0: 60bb str r3, [r7, #8]
SCB->AIRCR = reg_value;
80006f2: 4a04 ldr r2, [pc, #16] ; (8000704 <__NVIC_SetPriorityGrouping+0x44>)
80006f4: 68bb ldr r3, [r7, #8]
80006f6: 60d3 str r3, [r2, #12]
}
80006f8: bf00 nop
80006fa: 3714 adds r7, #20
80006fc: 46bd mov sp, r7
80006fe: bc80 pop {r7}
8000700: 4770 bx lr
8000702: bf00 nop
8000704: e000ed00 .word 0xe000ed00
08000708 <__NVIC_GetPriorityGrouping>:
\brief Get Priority Grouping
\details Reads the priority grouping field from the NVIC Interrupt Controller.
\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
*/
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
{
8000708: b480 push {r7}
800070a: af00 add r7, sp, #0
return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
800070c: 4b04 ldr r3, [pc, #16] ; (8000720 <__NVIC_GetPriorityGrouping+0x18>)
800070e: 68db ldr r3, [r3, #12]
8000710: 0a1b lsrs r3, r3, #8
8000712: f003 0307 and.w r3, r3, #7
}
8000716: 4618 mov r0, r3
8000718: 46bd mov sp, r7
800071a: bc80 pop {r7}
800071c: 4770 bx lr
800071e: bf00 nop
8000720: e000ed00 .word 0xe000ed00
08000724 <__NVIC_SetPriority>:
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
8000724: b480 push {r7}
8000726: b083 sub sp, #12
8000728: af00 add r7, sp, #0
800072a: 4603 mov r3, r0
800072c: 6039 str r1, [r7, #0]
800072e: 71fb strb r3, [r7, #7]
if ((int32_t)(IRQn) >= 0)
8000730: f997 3007 ldrsb.w r3, [r7, #7]
8000734: 2b00 cmp r3, #0
8000736: db0a blt.n 800074e <__NVIC_SetPriority+0x2a>
{
NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
8000738: 683b ldr r3, [r7, #0]
800073a: b2da uxtb r2, r3
800073c: 490c ldr r1, [pc, #48] ; (8000770 <__NVIC_SetPriority+0x4c>)
800073e: f997 3007 ldrsb.w r3, [r7, #7]
8000742: 0112 lsls r2, r2, #4
8000744: b2d2 uxtb r2, r2
8000746: 440b add r3, r1
8000748: f883 2300 strb.w r2, [r3, #768] ; 0x300
}
else
{
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
}
}
800074c: e00a b.n 8000764 <__NVIC_SetPriority+0x40>
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
800074e: 683b ldr r3, [r7, #0]
8000750: b2da uxtb r2, r3
8000752: 4908 ldr r1, [pc, #32] ; (8000774 <__NVIC_SetPriority+0x50>)
8000754: 79fb ldrb r3, [r7, #7]
8000756: f003 030f and.w r3, r3, #15
800075a: 3b04 subs r3, #4
800075c: 0112 lsls r2, r2, #4
800075e: b2d2 uxtb r2, r2
8000760: 440b add r3, r1
8000762: 761a strb r2, [r3, #24]
}
8000764: bf00 nop
8000766: 370c adds r7, #12
8000768: 46bd mov sp, r7
800076a: bc80 pop {r7}
800076c: 4770 bx lr
800076e: bf00 nop
8000770: e000e100 .word 0xe000e100
8000774: e000ed00 .word 0xe000ed00
08000778 <NVIC_EncodePriority>:
\param [in] PreemptPriority Preemptive priority value (starting from 0).
\param [in] SubPriority Subpriority value (starting from 0).
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
8000778: b480 push {r7}
800077a: b089 sub sp, #36 ; 0x24
800077c: af00 add r7, sp, #0
800077e: 60f8 str r0, [r7, #12]
8000780: 60b9 str r1, [r7, #8]
8000782: 607a str r2, [r7, #4]
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
8000784: 68fb ldr r3, [r7, #12]
8000786: f003 0307 and.w r3, r3, #7
800078a: 61fb str r3, [r7, #28]
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
800078c: 69fb ldr r3, [r7, #28]
800078e: f1c3 0307 rsb r3, r3, #7
8000792: 2b04 cmp r3, #4
8000794: bf28 it cs
8000796: 2304 movcs r3, #4
8000798: 61bb str r3, [r7, #24]
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
800079a: 69fb ldr r3, [r7, #28]
800079c: 3304 adds r3, #4
800079e: 2b06 cmp r3, #6
80007a0: d902 bls.n 80007a8 <NVIC_EncodePriority+0x30>
80007a2: 69fb ldr r3, [r7, #28]
80007a4: 3b03 subs r3, #3
80007a6: e000 b.n 80007aa <NVIC_EncodePriority+0x32>
80007a8: 2300 movs r3, #0
80007aa: 617b str r3, [r7, #20]
return (
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
80007ac: f04f 32ff mov.w r2, #4294967295
80007b0: 69bb ldr r3, [r7, #24]
80007b2: fa02 f303 lsl.w r3, r2, r3
80007b6: 43da mvns r2, r3
80007b8: 68bb ldr r3, [r7, #8]
80007ba: 401a ands r2, r3
80007bc: 697b ldr r3, [r7, #20]
80007be: 409a lsls r2, r3
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
80007c0: f04f 31ff mov.w r1, #4294967295
80007c4: 697b ldr r3, [r7, #20]
80007c6: fa01 f303 lsl.w r3, r1, r3
80007ca: 43d9 mvns r1, r3
80007cc: 687b ldr r3, [r7, #4]
80007ce: 400b ands r3, r1
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
80007d0: 4313 orrs r3, r2
);
}
80007d2: 4618 mov r0, r3
80007d4: 3724 adds r7, #36 ; 0x24
80007d6: 46bd mov sp, r7
80007d8: bc80 pop {r7}
80007da: 4770 bx lr
080007dc <SysTick_Config>:
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
80007dc: b580 push {r7, lr}
80007de: b082 sub sp, #8
80007e0: af00 add r7, sp, #0
80007e2: 6078 str r0, [r7, #4]
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
80007e4: 687b ldr r3, [r7, #4]
80007e6: 3b01 subs r3, #1
80007e8: f1b3 7f80 cmp.w r3, #16777216 ; 0x1000000
80007ec: d301 bcc.n 80007f2 <SysTick_Config+0x16>
{
return (1UL); /* Reload value impossible */
80007ee: 2301 movs r3, #1
80007f0: e00f b.n 8000812 <SysTick_Config+0x36>
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
80007f2: 4a0a ldr r2, [pc, #40] ; (800081c <SysTick_Config+0x40>)
80007f4: 687b ldr r3, [r7, #4]
80007f6: 3b01 subs r3, #1
80007f8: 6053 str r3, [r2, #4]
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
80007fa: 210f movs r1, #15
80007fc: f04f 30ff mov.w r0, #4294967295
8000800: f7ff ff90 bl 8000724 <__NVIC_SetPriority>
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
8000804: 4b05 ldr r3, [pc, #20] ; (800081c <SysTick_Config+0x40>)
8000806: 2200 movs r2, #0
8000808: 609a str r2, [r3, #8]
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
800080a: 4b04 ldr r3, [pc, #16] ; (800081c <SysTick_Config+0x40>)
800080c: 2207 movs r2, #7
800080e: 601a str r2, [r3, #0]
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
8000810: 2300 movs r3, #0
}
8000812: 4618 mov r0, r3
8000814: 3708 adds r7, #8
8000816: 46bd mov sp, r7
8000818: bd80 pop {r7, pc}
800081a: bf00 nop
800081c: e000e010 .word 0xe000e010
08000820 <HAL_NVIC_SetPriorityGrouping>:
* @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible.
* The pending IRQ priority will be managed only by the subpriority.
* @retval None
*/
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
8000820: b580 push {r7, lr}
8000822: b082 sub sp, #8
8000824: af00 add r7, sp, #0
8000826: 6078 str r0, [r7, #4]
/* Check the parameters */
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
/* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
NVIC_SetPriorityGrouping(PriorityGroup);
8000828: 6878 ldr r0, [r7, #4]
800082a: f7ff ff49 bl 80006c0 <__NVIC_SetPriorityGrouping>
}
800082e: bf00 nop
8000830: 3708 adds r7, #8
8000832: 46bd mov sp, r7
8000834: bd80 pop {r7, pc}
08000836 <HAL_NVIC_SetPriority>:
* This parameter can be a value between 0 and 15
* A lower priority value indicates a higher priority.
* @retval None
*/
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
{
8000836: b580 push {r7, lr}
8000838: b086 sub sp, #24
800083a: af00 add r7, sp, #0
800083c: 4603 mov r3, r0
800083e: 60b9 str r1, [r7, #8]
8000840: 607a str r2, [r7, #4]
8000842: 73fb strb r3, [r7, #15]
uint32_t prioritygroup = 0x00U;
8000844: 2300 movs r3, #0
8000846: 617b str r3, [r7, #20]
/* Check the parameters */
assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
prioritygroup = NVIC_GetPriorityGrouping();
8000848: f7ff ff5e bl 8000708 <__NVIC_GetPriorityGrouping>
800084c: 6178 str r0, [r7, #20]
NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
800084e: 687a ldr r2, [r7, #4]
8000850: 68b9 ldr r1, [r7, #8]
8000852: 6978 ldr r0, [r7, #20]
8000854: f7ff ff90 bl 8000778 <NVIC_EncodePriority>
8000858: 4602 mov r2, r0
800085a: f997 300f ldrsb.w r3, [r7, #15]
800085e: 4611 mov r1, r2
8000860: 4618 mov r0, r3
8000862: f7ff ff5f bl 8000724 <__NVIC_SetPriority>
}
8000866: bf00 nop
8000868: 3718 adds r7, #24
800086a: 46bd mov sp, r7
800086c: bd80 pop {r7, pc}
0800086e <HAL_SYSTICK_Config>:
* @param TicksNumb: Specifies the ticks Number of ticks between two interrupts.
* @retval status: - 0 Function succeeded.
* - 1 Function failed.
*/
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
{
800086e: b580 push {r7, lr}
8000870: b082 sub sp, #8
8000872: af00 add r7, sp, #0
8000874: 6078 str r0, [r7, #4]
return SysTick_Config(TicksNumb);
8000876: 6878 ldr r0, [r7, #4]
8000878: f7ff ffb0 bl 80007dc <SysTick_Config>
800087c: 4603 mov r3, r0
}
800087e: 4618 mov r0, r3
8000880: 3708 adds r7, #8
8000882: 46bd mov sp, r7
8000884: bd80 pop {r7, pc}
...
08000888 <HAL_GPIO_Init>:
* @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains
* the configuration information for the specified GPIO peripheral.
* @retval None
*/
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
{
8000888: b480 push {r7}
800088a: b08b sub sp, #44 ; 0x2c
800088c: af00 add r7, sp, #0
800088e: 6078 str r0, [r7, #4]
8000890: 6039 str r1, [r7, #0]
uint32_t position = 0x00u;
8000892: 2300 movs r3, #0
8000894: 627b str r3, [r7, #36] ; 0x24
uint32_t ioposition;
uint32_t iocurrent;
uint32_t temp;
uint32_t config = 0x00u;
8000896: 2300 movs r3, #0
8000898: 623b str r3, [r7, #32]
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
/* Configure the port pins */
while (((GPIO_Init->Pin) >> position) != 0x00u)
800089a: e169 b.n 8000b70 <HAL_GPIO_Init+0x2e8>
{
/* Get the IO position */
ioposition = (0x01uL << position);
800089c: 2201 movs r2, #1
800089e: 6a7b ldr r3, [r7, #36] ; 0x24
80008a0: fa02 f303 lsl.w r3, r2, r3
80008a4: 61fb str r3, [r7, #28]
/* Get the current IO position */
iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition;
80008a6: 683b ldr r3, [r7, #0]
80008a8: 681b ldr r3, [r3, #0]
80008aa: 69fa ldr r2, [r7, #28]
80008ac: 4013 ands r3, r2
80008ae: 61bb str r3, [r7, #24]
if (iocurrent == ioposition)
80008b0: 69ba ldr r2, [r7, #24]
80008b2: 69fb ldr r3, [r7, #28]
80008b4: 429a cmp r2, r3
80008b6: f040 8158 bne.w 8000b6a <HAL_GPIO_Init+0x2e2>
{
/* Check the Alternate function parameters */
assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
/* Based on the required mode, filling config variable with MODEy[1:0] and CNFy[3:2] corresponding bits */
switch (GPIO_Init->Mode)
80008ba: 683b ldr r3, [r7, #0]
80008bc: 685b ldr r3, [r3, #4]
80008be: 4a9a ldr r2, [pc, #616] ; (8000b28 <HAL_GPIO_Init+0x2a0>)
80008c0: 4293 cmp r3, r2
80008c2: d05e beq.n 8000982 <HAL_GPIO_Init+0xfa>
80008c4: 4a98 ldr r2, [pc, #608] ; (8000b28 <HAL_GPIO_Init+0x2a0>)
80008c6: 4293 cmp r3, r2
80008c8: d875 bhi.n 80009b6 <HAL_GPIO_Init+0x12e>
80008ca: 4a98 ldr r2, [pc, #608] ; (8000b2c <HAL_GPIO_Init+0x2a4>)
80008cc: 4293 cmp r3, r2
80008ce: d058 beq.n 8000982 <HAL_GPIO_Init+0xfa>
80008d0: 4a96 ldr r2, [pc, #600] ; (8000b2c <HAL_GPIO_Init+0x2a4>)
80008d2: 4293 cmp r3, r2
80008d4: d86f bhi.n 80009b6 <HAL_GPIO_Init+0x12e>
80008d6: 4a96 ldr r2, [pc, #600] ; (8000b30 <HAL_GPIO_Init+0x2a8>)
80008d8: 4293 cmp r3, r2
80008da: d052 beq.n 8000982 <HAL_GPIO_Init+0xfa>
80008dc: 4a94 ldr r2, [pc, #592] ; (8000b30 <HAL_GPIO_Init+0x2a8>)
80008de: 4293 cmp r3, r2
80008e0: d869 bhi.n 80009b6 <HAL_GPIO_Init+0x12e>
80008e2: 4a94 ldr r2, [pc, #592] ; (8000b34 <HAL_GPIO_Init+0x2ac>)
80008e4: 4293 cmp r3, r2
80008e6: d04c beq.n 8000982 <HAL_GPIO_Init+0xfa>
80008e8: 4a92 ldr r2, [pc, #584] ; (8000b34 <HAL_GPIO_Init+0x2ac>)
80008ea: 4293 cmp r3, r2
80008ec: d863 bhi.n 80009b6 <HAL_GPIO_Init+0x12e>
80008ee: 4a92 ldr r2, [pc, #584] ; (8000b38 <HAL_GPIO_Init+0x2b0>)
80008f0: 4293 cmp r3, r2
80008f2: d046 beq.n 8000982 <HAL_GPIO_Init+0xfa>
80008f4: 4a90 ldr r2, [pc, #576] ; (8000b38 <HAL_GPIO_Init+0x2b0>)
80008f6: 4293 cmp r3, r2
80008f8: d85d bhi.n 80009b6 <HAL_GPIO_Init+0x12e>
80008fa: 2b12 cmp r3, #18
80008fc: d82a bhi.n 8000954 <HAL_GPIO_Init+0xcc>
80008fe: 2b12 cmp r3, #18
8000900: d859 bhi.n 80009b6 <HAL_GPIO_Init+0x12e>
8000902: a201 add r2, pc, #4 ; (adr r2, 8000908 <HAL_GPIO_Init+0x80>)
8000904: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8000908: 08000983 .word 0x08000983
800090c: 0800095d .word 0x0800095d
8000910: 0800096f .word 0x0800096f
8000914: 080009b1 .word 0x080009b1
8000918: 080009b7 .word 0x080009b7
800091c: 080009b7 .word 0x080009b7
8000920: 080009b7 .word 0x080009b7
8000924: 080009b7 .word 0x080009b7
8000928: 080009b7 .word 0x080009b7
800092c: 080009b7 .word 0x080009b7
8000930: 080009b7 .word 0x080009b7
8000934: 080009b7 .word 0x080009b7
8000938: 080009b7 .word 0x080009b7
800093c: 080009b7 .word 0x080009b7
8000940: 080009b7 .word 0x080009b7
8000944: 080009b7 .word 0x080009b7
8000948: 080009b7 .word 0x080009b7
800094c: 08000965 .word 0x08000965
8000950: 08000979 .word 0x08000979
8000954: 4a79 ldr r2, [pc, #484] ; (8000b3c <HAL_GPIO_Init+0x2b4>)
8000956: 4293 cmp r3, r2
8000958: d013 beq.n 8000982 <HAL_GPIO_Init+0xfa>
config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG;
break;
/* Parameters are checked with assert_param */
default:
break;
800095a: e02c b.n 80009b6 <HAL_GPIO_Init+0x12e>
config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_PP;
800095c: 683b ldr r3, [r7, #0]
800095e: 68db ldr r3, [r3, #12]
8000960: 623b str r3, [r7, #32]
break;
8000962: e029 b.n 80009b8 <HAL_GPIO_Init+0x130>
config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_OD;
8000964: 683b ldr r3, [r7, #0]
8000966: 68db ldr r3, [r3, #12]
8000968: 3304 adds r3, #4
800096a: 623b str r3, [r7, #32]
break;
800096c: e024 b.n 80009b8 <HAL_GPIO_Init+0x130>
config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_PP;
800096e: 683b ldr r3, [r7, #0]
8000970: 68db ldr r3, [r3, #12]
8000972: 3308 adds r3, #8
8000974: 623b str r3, [r7, #32]
break;
8000976: e01f b.n 80009b8 <HAL_GPIO_Init+0x130>
config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_OD;
8000978: 683b ldr r3, [r7, #0]
800097a: 68db ldr r3, [r3, #12]
800097c: 330c adds r3, #12
800097e: 623b str r3, [r7, #32]
break;
8000980: e01a b.n 80009b8 <HAL_GPIO_Init+0x130>
if (GPIO_Init->Pull == GPIO_NOPULL)
8000982: 683b ldr r3, [r7, #0]
8000984: 689b ldr r3, [r3, #8]
8000986: 2b00 cmp r3, #0
8000988: d102 bne.n 8000990 <HAL_GPIO_Init+0x108>
config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_FLOATING;
800098a: 2304 movs r3, #4
800098c: 623b str r3, [r7, #32]
break;
800098e: e013 b.n 80009b8 <HAL_GPIO_Init+0x130>
else if (GPIO_Init->Pull == GPIO_PULLUP)
8000990: 683b ldr r3, [r7, #0]
8000992: 689b ldr r3, [r3, #8]
8000994: 2b01 cmp r3, #1
8000996: d105 bne.n 80009a4 <HAL_GPIO_Init+0x11c>
config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD;
8000998: 2308 movs r3, #8
800099a: 623b str r3, [r7, #32]
GPIOx->BSRR = ioposition;
800099c: 687b ldr r3, [r7, #4]
800099e: 69fa ldr r2, [r7, #28]
80009a0: 611a str r2, [r3, #16]
break;
80009a2: e009 b.n 80009b8 <HAL_GPIO_Init+0x130>
config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD;
80009a4: 2308 movs r3, #8
80009a6: 623b str r3, [r7, #32]
GPIOx->BRR = ioposition;
80009a8: 687b ldr r3, [r7, #4]
80009aa: 69fa ldr r2, [r7, #28]
80009ac: 615a str r2, [r3, #20]
break;
80009ae: e003 b.n 80009b8 <HAL_GPIO_Init+0x130>
config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG;
80009b0: 2300 movs r3, #0
80009b2: 623b str r3, [r7, #32]
break;
80009b4: e000 b.n 80009b8 <HAL_GPIO_Init+0x130>
break;
80009b6: bf00 nop
}
/* Check if the current bit belongs to first half or last half of the pin count number
in order to address CRH or CRL register*/
configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL : &GPIOx->CRH;
80009b8: 69bb ldr r3, [r7, #24]
80009ba: 2bff cmp r3, #255 ; 0xff
80009bc: d801 bhi.n 80009c2 <HAL_GPIO_Init+0x13a>
80009be: 687b ldr r3, [r7, #4]
80009c0: e001 b.n 80009c6 <HAL_GPIO_Init+0x13e>
80009c2: 687b ldr r3, [r7, #4]
80009c4: 3304 adds r3, #4
80009c6: 617b str r3, [r7, #20]
registeroffset = (iocurrent < GPIO_PIN_8) ? (position << 2u) : ((position - 8u) << 2u);
80009c8: 69bb ldr r3, [r7, #24]
80009ca: 2bff cmp r3, #255 ; 0xff
80009cc: d802 bhi.n 80009d4 <HAL_GPIO_Init+0x14c>
80009ce: 6a7b ldr r3, [r7, #36] ; 0x24
80009d0: 009b lsls r3, r3, #2
80009d2: e002 b.n 80009da <HAL_GPIO_Init+0x152>
80009d4: 6a7b ldr r3, [r7, #36] ; 0x24
80009d6: 3b08 subs r3, #8
80009d8: 009b lsls r3, r3, #2
80009da: 613b str r3, [r7, #16]
/* Apply the new configuration of the pin to the register */
MODIFY_REG((*configregister), ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset), (config << registeroffset));
80009dc: 697b ldr r3, [r7, #20]
80009de: 681a ldr r2, [r3, #0]
80009e0: 210f movs r1, #15
80009e2: 693b ldr r3, [r7, #16]
80009e4: fa01 f303 lsl.w r3, r1, r3
80009e8: 43db mvns r3, r3
80009ea: 401a ands r2, r3
80009ec: 6a39 ldr r1, [r7, #32]
80009ee: 693b ldr r3, [r7, #16]
80009f0: fa01 f303 lsl.w r3, r1, r3
80009f4: 431a orrs r2, r3
80009f6: 697b ldr r3, [r7, #20]
80009f8: 601a str r2, [r3, #0]
/*--------------------- EXTI Mode Configuration ------------------------*/
/* Configure the External Interrupt or event for the current IO */
if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
80009fa: 683b ldr r3, [r7, #0]
80009fc: 685b ldr r3, [r3, #4]
80009fe: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
8000a02: 2b00 cmp r3, #0
8000a04: f000 80b1 beq.w 8000b6a <HAL_GPIO_Init+0x2e2>
{
/* Enable AFIO Clock */
__HAL_RCC_AFIO_CLK_ENABLE();
8000a08: 4b4d ldr r3, [pc, #308] ; (8000b40 <HAL_GPIO_Init+0x2b8>)
8000a0a: 699b ldr r3, [r3, #24]
8000a0c: 4a4c ldr r2, [pc, #304] ; (8000b40 <HAL_GPIO_Init+0x2b8>)
8000a0e: f043 0301 orr.w r3, r3, #1
8000a12: 6193 str r3, [r2, #24]
8000a14: 4b4a ldr r3, [pc, #296] ; (8000b40 <HAL_GPIO_Init+0x2b8>)
8000a16: 699b ldr r3, [r3, #24]
8000a18: f003 0301 and.w r3, r3, #1
8000a1c: 60bb str r3, [r7, #8]
8000a1e: 68bb ldr r3, [r7, #8]
temp = AFIO->EXTICR[position >> 2u];
8000a20: 4a48 ldr r2, [pc, #288] ; (8000b44 <HAL_GPIO_Init+0x2bc>)
8000a22: 6a7b ldr r3, [r7, #36] ; 0x24
8000a24: 089b lsrs r3, r3, #2
8000a26: 3302 adds r3, #2
8000a28: f852 3023 ldr.w r3, [r2, r3, lsl #2]
8000a2c: 60fb str r3, [r7, #12]
CLEAR_BIT(temp, (0x0Fu) << (4u * (position & 0x03u)));
8000a2e: 6a7b ldr r3, [r7, #36] ; 0x24
8000a30: f003 0303 and.w r3, r3, #3
8000a34: 009b lsls r3, r3, #2
8000a36: 220f movs r2, #15
8000a38: fa02 f303 lsl.w r3, r2, r3
8000a3c: 43db mvns r3, r3
8000a3e: 68fa ldr r2, [r7, #12]
8000a40: 4013 ands r3, r2
8000a42: 60fb str r3, [r7, #12]
SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4u * (position & 0x03u)));
8000a44: 687b ldr r3, [r7, #4]
8000a46: 4a40 ldr r2, [pc, #256] ; (8000b48 <HAL_GPIO_Init+0x2c0>)
8000a48: 4293 cmp r3, r2
8000a4a: d013 beq.n 8000a74 <HAL_GPIO_Init+0x1ec>
8000a4c: 687b ldr r3, [r7, #4]
8000a4e: 4a3f ldr r2, [pc, #252] ; (8000b4c <HAL_GPIO_Init+0x2c4>)
8000a50: 4293 cmp r3, r2
8000a52: d00d beq.n 8000a70 <HAL_GPIO_Init+0x1e8>
8000a54: 687b ldr r3, [r7, #4]
8000a56: 4a3e ldr r2, [pc, #248] ; (8000b50 <HAL_GPIO_Init+0x2c8>)
8000a58: 4293 cmp r3, r2
8000a5a: d007 beq.n 8000a6c <HAL_GPIO_Init+0x1e4>
8000a5c: 687b ldr r3, [r7, #4]
8000a5e: 4a3d ldr r2, [pc, #244] ; (8000b54 <HAL_GPIO_Init+0x2cc>)
8000a60: 4293 cmp r3, r2
8000a62: d101 bne.n 8000a68 <HAL_GPIO_Init+0x1e0>
8000a64: 2303 movs r3, #3
8000a66: e006 b.n 8000a76 <HAL_GPIO_Init+0x1ee>
8000a68: 2304 movs r3, #4
8000a6a: e004 b.n 8000a76 <HAL_GPIO_Init+0x1ee>
8000a6c: 2302 movs r3, #2
8000a6e: e002 b.n 8000a76 <HAL_GPIO_Init+0x1ee>
8000a70: 2301 movs r3, #1
8000a72: e000 b.n 8000a76 <HAL_GPIO_Init+0x1ee>
8000a74: 2300 movs r3, #0
8000a76: 6a7a ldr r2, [r7, #36] ; 0x24
8000a78: f002 0203 and.w r2, r2, #3
8000a7c: 0092 lsls r2, r2, #2
8000a7e: 4093 lsls r3, r2
8000a80: 68fa ldr r2, [r7, #12]
8000a82: 4313 orrs r3, r2
8000a84: 60fb str r3, [r7, #12]
AFIO->EXTICR[position >> 2u] = temp;
8000a86: 492f ldr r1, [pc, #188] ; (8000b44 <HAL_GPIO_Init+0x2bc>)
8000a88: 6a7b ldr r3, [r7, #36] ; 0x24
8000a8a: 089b lsrs r3, r3, #2
8000a8c: 3302 adds r3, #2
8000a8e: 68fa ldr r2, [r7, #12]
8000a90: f841 2023 str.w r2, [r1, r3, lsl #2]
/* Configure the interrupt mask */
if ((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
8000a94: 683b ldr r3, [r7, #0]
8000a96: 685b ldr r3, [r3, #4]
8000a98: f403 3380 and.w r3, r3, #65536 ; 0x10000
8000a9c: 2b00 cmp r3, #0
8000a9e: d006 beq.n 8000aae <HAL_GPIO_Init+0x226>
{
SET_BIT(EXTI->IMR, iocurrent);
8000aa0: 4b2d ldr r3, [pc, #180] ; (8000b58 <HAL_GPIO_Init+0x2d0>)
8000aa2: 681a ldr r2, [r3, #0]
8000aa4: 492c ldr r1, [pc, #176] ; (8000b58 <HAL_GPIO_Init+0x2d0>)
8000aa6: 69bb ldr r3, [r7, #24]
8000aa8: 4313 orrs r3, r2
8000aaa: 600b str r3, [r1, #0]
8000aac: e006 b.n 8000abc <HAL_GPIO_Init+0x234>
}
else
{
CLEAR_BIT(EXTI->IMR, iocurrent);
8000aae: 4b2a ldr r3, [pc, #168] ; (8000b58 <HAL_GPIO_Init+0x2d0>)
8000ab0: 681a ldr r2, [r3, #0]
8000ab2: 69bb ldr r3, [r7, #24]
8000ab4: 43db mvns r3, r3
8000ab6: 4928 ldr r1, [pc, #160] ; (8000b58 <HAL_GPIO_Init+0x2d0>)
8000ab8: 4013 ands r3, r2
8000aba: 600b str r3, [r1, #0]
}
/* Configure the event mask */
if ((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
8000abc: 683b ldr r3, [r7, #0]
8000abe: 685b ldr r3, [r3, #4]
8000ac0: f403 3300 and.w r3, r3, #131072 ; 0x20000
8000ac4: 2b00 cmp r3, #0
8000ac6: d006 beq.n 8000ad6 <HAL_GPIO_Init+0x24e>
{
SET_BIT(EXTI->EMR, iocurrent);
8000ac8: 4b23 ldr r3, [pc, #140] ; (8000b58 <HAL_GPIO_Init+0x2d0>)
8000aca: 685a ldr r2, [r3, #4]
8000acc: 4922 ldr r1, [pc, #136] ; (8000b58 <HAL_GPIO_Init+0x2d0>)
8000ace: 69bb ldr r3, [r7, #24]
8000ad0: 4313 orrs r3, r2
8000ad2: 604b str r3, [r1, #4]
8000ad4: e006 b.n 8000ae4 <HAL_GPIO_Init+0x25c>
}
else
{
CLEAR_BIT(EXTI->EMR, iocurrent);
8000ad6: 4b20 ldr r3, [pc, #128] ; (8000b58 <HAL_GPIO_Init+0x2d0>)
8000ad8: 685a ldr r2, [r3, #4]
8000ada: 69bb ldr r3, [r7, #24]
8000adc: 43db mvns r3, r3
8000ade: 491e ldr r1, [pc, #120] ; (8000b58 <HAL_GPIO_Init+0x2d0>)
8000ae0: 4013 ands r3, r2
8000ae2: 604b str r3, [r1, #4]
}
/* Enable or disable the rising trigger */
if ((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
8000ae4: 683b ldr r3, [r7, #0]
8000ae6: 685b ldr r3, [r3, #4]
8000ae8: f403 1380 and.w r3, r3, #1048576 ; 0x100000
8000aec: 2b00 cmp r3, #0
8000aee: d006 beq.n 8000afe <HAL_GPIO_Init+0x276>
{
SET_BIT(EXTI->RTSR, iocurrent);
8000af0: 4b19 ldr r3, [pc, #100] ; (8000b58 <HAL_GPIO_Init+0x2d0>)
8000af2: 689a ldr r2, [r3, #8]
8000af4: 4918 ldr r1, [pc, #96] ; (8000b58 <HAL_GPIO_Init+0x2d0>)
8000af6: 69bb ldr r3, [r7, #24]
8000af8: 4313 orrs r3, r2
8000afa: 608b str r3, [r1, #8]
8000afc: e006 b.n 8000b0c <HAL_GPIO_Init+0x284>
}
else
{
CLEAR_BIT(EXTI->RTSR, iocurrent);
8000afe: 4b16 ldr r3, [pc, #88] ; (8000b58 <HAL_GPIO_Init+0x2d0>)
8000b00: 689a ldr r2, [r3, #8]
8000b02: 69bb ldr r3, [r7, #24]
8000b04: 43db mvns r3, r3
8000b06: 4914 ldr r1, [pc, #80] ; (8000b58 <HAL_GPIO_Init+0x2d0>)
8000b08: 4013 ands r3, r2
8000b0a: 608b str r3, [r1, #8]
}
/* Enable or disable the falling trigger */
if ((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
8000b0c: 683b ldr r3, [r7, #0]
8000b0e: 685b ldr r3, [r3, #4]
8000b10: f403 1300 and.w r3, r3, #2097152 ; 0x200000
8000b14: 2b00 cmp r3, #0
8000b16: d021 beq.n 8000b5c <HAL_GPIO_Init+0x2d4>
{
SET_BIT(EXTI->FTSR, iocurrent);
8000b18: 4b0f ldr r3, [pc, #60] ; (8000b58 <HAL_GPIO_Init+0x2d0>)
8000b1a: 68da ldr r2, [r3, #12]
8000b1c: 490e ldr r1, [pc, #56] ; (8000b58 <HAL_GPIO_Init+0x2d0>)
8000b1e: 69bb ldr r3, [r7, #24]
8000b20: 4313 orrs r3, r2
8000b22: 60cb str r3, [r1, #12]
8000b24: e021 b.n 8000b6a <HAL_GPIO_Init+0x2e2>
8000b26: bf00 nop
8000b28: 10320000 .word 0x10320000
8000b2c: 10310000 .word 0x10310000
8000b30: 10220000 .word 0x10220000
8000b34: 10210000 .word 0x10210000
8000b38: 10120000 .word 0x10120000
8000b3c: 10110000 .word 0x10110000
8000b40: 40021000 .word 0x40021000
8000b44: 40010000 .word 0x40010000
8000b48: 40010800 .word 0x40010800
8000b4c: 40010c00 .word 0x40010c00
8000b50: 40011000 .word 0x40011000
8000b54: 40011400 .word 0x40011400
8000b58: 40010400 .word 0x40010400
}
else
{
CLEAR_BIT(EXTI->FTSR, iocurrent);
8000b5c: 4b0b ldr r3, [pc, #44] ; (8000b8c <HAL_GPIO_Init+0x304>)
8000b5e: 68da ldr r2, [r3, #12]
8000b60: 69bb ldr r3, [r7, #24]
8000b62: 43db mvns r3, r3
8000b64: 4909 ldr r1, [pc, #36] ; (8000b8c <HAL_GPIO_Init+0x304>)
8000b66: 4013 ands r3, r2
8000b68: 60cb str r3, [r1, #12]
}
}
}
position++;
8000b6a: 6a7b ldr r3, [r7, #36] ; 0x24
8000b6c: 3301 adds r3, #1
8000b6e: 627b str r3, [r7, #36] ; 0x24
while (((GPIO_Init->Pin) >> position) != 0x00u)
8000b70: 683b ldr r3, [r7, #0]
8000b72: 681a ldr r2, [r3, #0]
8000b74: 6a7b ldr r3, [r7, #36] ; 0x24
8000b76: fa22 f303 lsr.w r3, r2, r3
8000b7a: 2b00 cmp r3, #0
8000b7c: f47f ae8e bne.w 800089c <HAL_GPIO_Init+0x14>
}
}
8000b80: bf00 nop
8000b82: bf00 nop
8000b84: 372c adds r7, #44 ; 0x2c
8000b86: 46bd mov sp, r7
8000b88: bc80 pop {r7}
8000b8a: 4770 bx lr
8000b8c: 40010400 .word 0x40010400
08000b90 <HAL_GPIO_ReadPin>:
* @param GPIO_Pin: specifies the port bit to read.
* This parameter can be GPIO_PIN_x where x can be (0..15).
* @retval The input port pin value.
*/
GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
{
8000b90: b480 push {r7}
8000b92: b085 sub sp, #20
8000b94: af00 add r7, sp, #0
8000b96: 6078 str r0, [r7, #4]
8000b98: 460b mov r3, r1
8000b9a: 807b strh r3, [r7, #2]
GPIO_PinState bitstatus;
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET)
8000b9c: 687b ldr r3, [r7, #4]
8000b9e: 689a ldr r2, [r3, #8]
8000ba0: 887b ldrh r3, [r7, #2]
8000ba2: 4013 ands r3, r2
8000ba4: 2b00 cmp r3, #0
8000ba6: d002 beq.n 8000bae <HAL_GPIO_ReadPin+0x1e>
{
bitstatus = GPIO_PIN_SET;
8000ba8: 2301 movs r3, #1
8000baa: 73fb strb r3, [r7, #15]
8000bac: e001 b.n 8000bb2 <HAL_GPIO_ReadPin+0x22>
}
else
{
bitstatus = GPIO_PIN_RESET;
8000bae: 2300 movs r3, #0
8000bb0: 73fb strb r3, [r7, #15]
}
return bitstatus;
8000bb2: 7bfb ldrb r3, [r7, #15]
}
8000bb4: 4618 mov r0, r3
8000bb6: 3714 adds r7, #20
8000bb8: 46bd mov sp, r7
8000bba: bc80 pop {r7}
8000bbc: 4770 bx lr
...
08000bc0 <HAL_RCC_OscConfig>:
* supported by this macro. User should request a transition to HSE Off
* first and then HSE On or HSE Bypass.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
{
8000bc0: b580 push {r7, lr}
8000bc2: b086 sub sp, #24
8000bc4: af00 add r7, sp, #0
8000bc6: 6078 str r0, [r7, #4]
uint32_t tickstart;
uint32_t pll_config;
/* Check Null pointer */
if (RCC_OscInitStruct == NULL)
8000bc8: 687b ldr r3, [r7, #4]
8000bca: 2b00 cmp r3, #0
8000bcc: d101 bne.n 8000bd2 <HAL_RCC_OscConfig+0x12>
{
return HAL_ERROR;
8000bce: 2301 movs r3, #1
8000bd0: e272 b.n 80010b8 <HAL_RCC_OscConfig+0x4f8>
/* Check the parameters */
assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
/*------------------------------- HSE Configuration ------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
8000bd2: 687b ldr r3, [r7, #4]
8000bd4: 681b ldr r3, [r3, #0]
8000bd6: f003 0301 and.w r3, r3, #1
8000bda: 2b00 cmp r3, #0
8000bdc: f000 8087 beq.w 8000cee <HAL_RCC_OscConfig+0x12e>
{
/* Check the parameters */
assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
/* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)
8000be0: 4b92 ldr r3, [pc, #584] ; (8000e2c <HAL_RCC_OscConfig+0x26c>)
8000be2: 685b ldr r3, [r3, #4]
8000be4: f003 030c and.w r3, r3, #12
8000be8: 2b04 cmp r3, #4
8000bea: d00c beq.n 8000c06 <HAL_RCC_OscConfig+0x46>
|| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE)))
8000bec: 4b8f ldr r3, [pc, #572] ; (8000e2c <HAL_RCC_OscConfig+0x26c>)
8000bee: 685b ldr r3, [r3, #4]
8000bf0: f003 030c and.w r3, r3, #12
8000bf4: 2b08 cmp r3, #8
8000bf6: d112 bne.n 8000c1e <HAL_RCC_OscConfig+0x5e>
8000bf8: 4b8c ldr r3, [pc, #560] ; (8000e2c <HAL_RCC_OscConfig+0x26c>)
8000bfa: 685b ldr r3, [r3, #4]
8000bfc: f403 3380 and.w r3, r3, #65536 ; 0x10000
8000c00: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
8000c04: d10b bne.n 8000c1e <HAL_RCC_OscConfig+0x5e>
{
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
8000c06: 4b89 ldr r3, [pc, #548] ; (8000e2c <HAL_RCC_OscConfig+0x26c>)
8000c08: 681b ldr r3, [r3, #0]
8000c0a: f403 3300 and.w r3, r3, #131072 ; 0x20000
8000c0e: 2b00 cmp r3, #0
8000c10: d06c beq.n 8000cec <HAL_RCC_OscConfig+0x12c>
8000c12: 687b ldr r3, [r7, #4]
8000c14: 685b ldr r3, [r3, #4]
8000c16: 2b00 cmp r3, #0
8000c18: d168 bne.n 8000cec <HAL_RCC_OscConfig+0x12c>
{
return HAL_ERROR;
8000c1a: 2301 movs r3, #1
8000c1c: e24c b.n 80010b8 <HAL_RCC_OscConfig+0x4f8>
}
}
else
{
/* Set the new HSE configuration ---------------------------------------*/
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
8000c1e: 687b ldr r3, [r7, #4]
8000c20: 685b ldr r3, [r3, #4]
8000c22: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
8000c26: d106 bne.n 8000c36 <HAL_RCC_OscConfig+0x76>
8000c28: 4b80 ldr r3, [pc, #512] ; (8000e2c <HAL_RCC_OscConfig+0x26c>)
8000c2a: 681b ldr r3, [r3, #0]
8000c2c: 4a7f ldr r2, [pc, #508] ; (8000e2c <HAL_RCC_OscConfig+0x26c>)
8000c2e: f443 3380 orr.w r3, r3, #65536 ; 0x10000
8000c32: 6013 str r3, [r2, #0]
8000c34: e02e b.n 8000c94 <HAL_RCC_OscConfig+0xd4>
8000c36: 687b ldr r3, [r7, #4]
8000c38: 685b ldr r3, [r3, #4]
8000c3a: 2b00 cmp r3, #0
8000c3c: d10c bne.n 8000c58 <HAL_RCC_OscConfig+0x98>
8000c3e: 4b7b ldr r3, [pc, #492] ; (8000e2c <HAL_RCC_OscConfig+0x26c>)
8000c40: 681b ldr r3, [r3, #0]
8000c42: 4a7a ldr r2, [pc, #488] ; (8000e2c <HAL_RCC_OscConfig+0x26c>)
8000c44: f423 3380 bic.w r3, r3, #65536 ; 0x10000
8000c48: 6013 str r3, [r2, #0]
8000c4a: 4b78 ldr r3, [pc, #480] ; (8000e2c <HAL_RCC_OscConfig+0x26c>)
8000c4c: 681b ldr r3, [r3, #0]
8000c4e: 4a77 ldr r2, [pc, #476] ; (8000e2c <HAL_RCC_OscConfig+0x26c>)
8000c50: f423 2380 bic.w r3, r3, #262144 ; 0x40000
8000c54: 6013 str r3, [r2, #0]
8000c56: e01d b.n 8000c94 <HAL_RCC_OscConfig+0xd4>
8000c58: 687b ldr r3, [r7, #4]
8000c5a: 685b ldr r3, [r3, #4]
8000c5c: f5b3 2fa0 cmp.w r3, #327680 ; 0x50000
8000c60: d10c bne.n 8000c7c <HAL_RCC_OscConfig+0xbc>
8000c62: 4b72 ldr r3, [pc, #456] ; (8000e2c <HAL_RCC_OscConfig+0x26c>)
8000c64: 681b ldr r3, [r3, #0]
8000c66: 4a71 ldr r2, [pc, #452] ; (8000e2c <HAL_RCC_OscConfig+0x26c>)
8000c68: f443 2380 orr.w r3, r3, #262144 ; 0x40000
8000c6c: 6013 str r3, [r2, #0]
8000c6e: 4b6f ldr r3, [pc, #444] ; (8000e2c <HAL_RCC_OscConfig+0x26c>)
8000c70: 681b ldr r3, [r3, #0]
8000c72: 4a6e ldr r2, [pc, #440] ; (8000e2c <HAL_RCC_OscConfig+0x26c>)
8000c74: f443 3380 orr.w r3, r3, #65536 ; 0x10000
8000c78: 6013 str r3, [r2, #0]
8000c7a: e00b b.n 8000c94 <HAL_RCC_OscConfig+0xd4>
8000c7c: 4b6b ldr r3, [pc, #428] ; (8000e2c <HAL_RCC_OscConfig+0x26c>)
8000c7e: 681b ldr r3, [r3, #0]
8000c80: 4a6a ldr r2, [pc, #424] ; (8000e2c <HAL_RCC_OscConfig+0x26c>)
8000c82: f423 3380 bic.w r3, r3, #65536 ; 0x10000
8000c86: 6013 str r3, [r2, #0]
8000c88: 4b68 ldr r3, [pc, #416] ; (8000e2c <HAL_RCC_OscConfig+0x26c>)
8000c8a: 681b ldr r3, [r3, #0]
8000c8c: 4a67 ldr r2, [pc, #412] ; (8000e2c <HAL_RCC_OscConfig+0x26c>)
8000c8e: f423 2380 bic.w r3, r3, #262144 ; 0x40000
8000c92: 6013 str r3, [r2, #0]
/* Check the HSE State */
if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
8000c94: 687b ldr r3, [r7, #4]
8000c96: 685b ldr r3, [r3, #4]
8000c98: 2b00 cmp r3, #0
8000c9a: d013 beq.n 8000cc4 <HAL_RCC_OscConfig+0x104>
{
/* Get Start Tick */
tickstart = HAL_GetTick();
8000c9c: f7ff fce2 bl 8000664 <HAL_GetTick>
8000ca0: 6138 str r0, [r7, #16]
/* Wait till HSE is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
8000ca2: e008 b.n 8000cb6 <HAL_RCC_OscConfig+0xf6>
{
if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
8000ca4: f7ff fcde bl 8000664 <HAL_GetTick>
8000ca8: 4602 mov r2, r0
8000caa: 693b ldr r3, [r7, #16]
8000cac: 1ad3 subs r3, r2, r3
8000cae: 2b64 cmp r3, #100 ; 0x64
8000cb0: d901 bls.n 8000cb6 <HAL_RCC_OscConfig+0xf6>
{
return HAL_TIMEOUT;
8000cb2: 2303 movs r3, #3
8000cb4: e200 b.n 80010b8 <HAL_RCC_OscConfig+0x4f8>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
8000cb6: 4b5d ldr r3, [pc, #372] ; (8000e2c <HAL_RCC_OscConfig+0x26c>)
8000cb8: 681b ldr r3, [r3, #0]
8000cba: f403 3300 and.w r3, r3, #131072 ; 0x20000
8000cbe: 2b00 cmp r3, #0
8000cc0: d0f0 beq.n 8000ca4 <HAL_RCC_OscConfig+0xe4>
8000cc2: e014 b.n 8000cee <HAL_RCC_OscConfig+0x12e>
}
}
else
{
/* Get Start Tick */
tickstart = HAL_GetTick();
8000cc4: f7ff fcce bl 8000664 <HAL_GetTick>
8000cc8: 6138 str r0, [r7, #16]
/* Wait till HSE is disabled */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
8000cca: e008 b.n 8000cde <HAL_RCC_OscConfig+0x11e>
{
if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
8000ccc: f7ff fcca bl 8000664 <HAL_GetTick>
8000cd0: 4602 mov r2, r0
8000cd2: 693b ldr r3, [r7, #16]
8000cd4: 1ad3 subs r3, r2, r3
8000cd6: 2b64 cmp r3, #100 ; 0x64
8000cd8: d901 bls.n 8000cde <HAL_RCC_OscConfig+0x11e>
{
return HAL_TIMEOUT;
8000cda: 2303 movs r3, #3
8000cdc: e1ec b.n 80010b8 <HAL_RCC_OscConfig+0x4f8>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
8000cde: 4b53 ldr r3, [pc, #332] ; (8000e2c <HAL_RCC_OscConfig+0x26c>)
8000ce0: 681b ldr r3, [r3, #0]
8000ce2: f403 3300 and.w r3, r3, #131072 ; 0x20000
8000ce6: 2b00 cmp r3, #0
8000ce8: d1f0 bne.n 8000ccc <HAL_RCC_OscConfig+0x10c>
8000cea: e000 b.n 8000cee <HAL_RCC_OscConfig+0x12e>
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
8000cec: bf00 nop
}
}
}
}
/*----------------------------- HSI Configuration --------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
8000cee: 687b ldr r3, [r7, #4]
8000cf0: 681b ldr r3, [r3, #0]
8000cf2: f003 0302 and.w r3, r3, #2
8000cf6: 2b00 cmp r3, #0
8000cf8: d063 beq.n 8000dc2 <HAL_RCC_OscConfig+0x202>
/* Check the parameters */
assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
/* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)
8000cfa: 4b4c ldr r3, [pc, #304] ; (8000e2c <HAL_RCC_OscConfig+0x26c>)
8000cfc: 685b ldr r3, [r3, #4]
8000cfe: f003 030c and.w r3, r3, #12
8000d02: 2b00 cmp r3, #0
8000d04: d00b beq.n 8000d1e <HAL_RCC_OscConfig+0x15e>
|| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI_DIV2)))
8000d06: 4b49 ldr r3, [pc, #292] ; (8000e2c <HAL_RCC_OscConfig+0x26c>)
8000d08: 685b ldr r3, [r3, #4]
8000d0a: f003 030c and.w r3, r3, #12
8000d0e: 2b08 cmp r3, #8
8000d10: d11c bne.n 8000d4c <HAL_RCC_OscConfig+0x18c>
8000d12: 4b46 ldr r3, [pc, #280] ; (8000e2c <HAL_RCC_OscConfig+0x26c>)
8000d14: 685b ldr r3, [r3, #4]
8000d16: f403 3380 and.w r3, r3, #65536 ; 0x10000
8000d1a: 2b00 cmp r3, #0
8000d1c: d116 bne.n 8000d4c <HAL_RCC_OscConfig+0x18c>
{
/* When HSI is used as system clock it will not disabled */
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
8000d1e: 4b43 ldr r3, [pc, #268] ; (8000e2c <HAL_RCC_OscConfig+0x26c>)
8000d20: 681b ldr r3, [r3, #0]
8000d22: f003 0302 and.w r3, r3, #2
8000d26: 2b00 cmp r3, #0
8000d28: d005 beq.n 8000d36 <HAL_RCC_OscConfig+0x176>
8000d2a: 687b ldr r3, [r7, #4]
8000d2c: 691b ldr r3, [r3, #16]
8000d2e: 2b01 cmp r3, #1
8000d30: d001 beq.n 8000d36 <HAL_RCC_OscConfig+0x176>
{
return HAL_ERROR;
8000d32: 2301 movs r3, #1
8000d34: e1c0 b.n 80010b8 <HAL_RCC_OscConfig+0x4f8>
}
/* Otherwise, just the calibration is allowed */
else
{
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
8000d36: 4b3d ldr r3, [pc, #244] ; (8000e2c <HAL_RCC_OscConfig+0x26c>)
8000d38: 681b ldr r3, [r3, #0]
8000d3a: f023 02f8 bic.w r2, r3, #248 ; 0xf8
8000d3e: 687b ldr r3, [r7, #4]
8000d40: 695b ldr r3, [r3, #20]
8000d42: 00db lsls r3, r3, #3
8000d44: 4939 ldr r1, [pc, #228] ; (8000e2c <HAL_RCC_OscConfig+0x26c>)
8000d46: 4313 orrs r3, r2
8000d48: 600b str r3, [r1, #0]
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
8000d4a: e03a b.n 8000dc2 <HAL_RCC_OscConfig+0x202>
}
}
else
{
/* Check the HSI State */
if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
8000d4c: 687b ldr r3, [r7, #4]
8000d4e: 691b ldr r3, [r3, #16]
8000d50: 2b00 cmp r3, #0
8000d52: d020 beq.n 8000d96 <HAL_RCC_OscConfig+0x1d6>
{
/* Enable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_ENABLE();
8000d54: 4b36 ldr r3, [pc, #216] ; (8000e30 <HAL_RCC_OscConfig+0x270>)
8000d56: 2201 movs r2, #1
8000d58: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8000d5a: f7ff fc83 bl 8000664 <HAL_GetTick>
8000d5e: 6138 str r0, [r7, #16]
/* Wait till HSI is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
8000d60: e008 b.n 8000d74 <HAL_RCC_OscConfig+0x1b4>
{
if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
8000d62: f7ff fc7f bl 8000664 <HAL_GetTick>
8000d66: 4602 mov r2, r0
8000d68: 693b ldr r3, [r7, #16]
8000d6a: 1ad3 subs r3, r2, r3
8000d6c: 2b02 cmp r3, #2
8000d6e: d901 bls.n 8000d74 <HAL_RCC_OscConfig+0x1b4>
{
return HAL_TIMEOUT;
8000d70: 2303 movs r3, #3
8000d72: e1a1 b.n 80010b8 <HAL_RCC_OscConfig+0x4f8>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
8000d74: 4b2d ldr r3, [pc, #180] ; (8000e2c <HAL_RCC_OscConfig+0x26c>)
8000d76: 681b ldr r3, [r3, #0]
8000d78: f003 0302 and.w r3, r3, #2
8000d7c: 2b00 cmp r3, #0
8000d7e: d0f0 beq.n 8000d62 <HAL_RCC_OscConfig+0x1a2>
}
}
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
8000d80: 4b2a ldr r3, [pc, #168] ; (8000e2c <HAL_RCC_OscConfig+0x26c>)
8000d82: 681b ldr r3, [r3, #0]
8000d84: f023 02f8 bic.w r2, r3, #248 ; 0xf8
8000d88: 687b ldr r3, [r7, #4]
8000d8a: 695b ldr r3, [r3, #20]
8000d8c: 00db lsls r3, r3, #3
8000d8e: 4927 ldr r1, [pc, #156] ; (8000e2c <HAL_RCC_OscConfig+0x26c>)
8000d90: 4313 orrs r3, r2
8000d92: 600b str r3, [r1, #0]
8000d94: e015 b.n 8000dc2 <HAL_RCC_OscConfig+0x202>
}
else
{
/* Disable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_DISABLE();
8000d96: 4b26 ldr r3, [pc, #152] ; (8000e30 <HAL_RCC_OscConfig+0x270>)
8000d98: 2200 movs r2, #0
8000d9a: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8000d9c: f7ff fc62 bl 8000664 <HAL_GetTick>
8000da0: 6138 str r0, [r7, #16]
/* Wait till HSI is disabled */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
8000da2: e008 b.n 8000db6 <HAL_RCC_OscConfig+0x1f6>
{
if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
8000da4: f7ff fc5e bl 8000664 <HAL_GetTick>
8000da8: 4602 mov r2, r0
8000daa: 693b ldr r3, [r7, #16]
8000dac: 1ad3 subs r3, r2, r3
8000dae: 2b02 cmp r3, #2
8000db0: d901 bls.n 8000db6 <HAL_RCC_OscConfig+0x1f6>
{
return HAL_TIMEOUT;
8000db2: 2303 movs r3, #3
8000db4: e180 b.n 80010b8 <HAL_RCC_OscConfig+0x4f8>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
8000db6: 4b1d ldr r3, [pc, #116] ; (8000e2c <HAL_RCC_OscConfig+0x26c>)
8000db8: 681b ldr r3, [r3, #0]
8000dba: f003 0302 and.w r3, r3, #2
8000dbe: 2b00 cmp r3, #0
8000dc0: d1f0 bne.n 8000da4 <HAL_RCC_OscConfig+0x1e4>
}
}
}
}
/*------------------------------ LSI Configuration -------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
8000dc2: 687b ldr r3, [r7, #4]
8000dc4: 681b ldr r3, [r3, #0]
8000dc6: f003 0308 and.w r3, r3, #8
8000dca: 2b00 cmp r3, #0
8000dcc: d03a beq.n 8000e44 <HAL_RCC_OscConfig+0x284>
{
/* Check the parameters */
assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
/* Check the LSI State */
if (RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
8000dce: 687b ldr r3, [r7, #4]
8000dd0: 699b ldr r3, [r3, #24]
8000dd2: 2b00 cmp r3, #0
8000dd4: d019 beq.n 8000e0a <HAL_RCC_OscConfig+0x24a>
{
/* Enable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_ENABLE();
8000dd6: 4b17 ldr r3, [pc, #92] ; (8000e34 <HAL_RCC_OscConfig+0x274>)
8000dd8: 2201 movs r2, #1
8000dda: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8000ddc: f7ff fc42 bl 8000664 <HAL_GetTick>
8000de0: 6138 str r0, [r7, #16]
/* Wait till LSI is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
8000de2: e008 b.n 8000df6 <HAL_RCC_OscConfig+0x236>
{
if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
8000de4: f7ff fc3e bl 8000664 <HAL_GetTick>
8000de8: 4602 mov r2, r0
8000dea: 693b ldr r3, [r7, #16]
8000dec: 1ad3 subs r3, r2, r3
8000dee: 2b02 cmp r3, #2
8000df0: d901 bls.n 8000df6 <HAL_RCC_OscConfig+0x236>
{
return HAL_TIMEOUT;
8000df2: 2303 movs r3, #3
8000df4: e160 b.n 80010b8 <HAL_RCC_OscConfig+0x4f8>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
8000df6: 4b0d ldr r3, [pc, #52] ; (8000e2c <HAL_RCC_OscConfig+0x26c>)
8000df8: 6a5b ldr r3, [r3, #36] ; 0x24
8000dfa: f003 0302 and.w r3, r3, #2
8000dfe: 2b00 cmp r3, #0
8000e00: d0f0 beq.n 8000de4 <HAL_RCC_OscConfig+0x224>
}
}
/* To have a fully stabilized clock in the specified range, a software delay of 1ms
should be added.*/
RCC_Delay(1);
8000e02: 2001 movs r0, #1
8000e04: f000 faa6 bl 8001354 <RCC_Delay>
8000e08: e01c b.n 8000e44 <HAL_RCC_OscConfig+0x284>
}
else
{
/* Disable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_DISABLE();
8000e0a: 4b0a ldr r3, [pc, #40] ; (8000e34 <HAL_RCC_OscConfig+0x274>)
8000e0c: 2200 movs r2, #0
8000e0e: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8000e10: f7ff fc28 bl 8000664 <HAL_GetTick>
8000e14: 6138 str r0, [r7, #16]
/* Wait till LSI is disabled */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
8000e16: e00f b.n 8000e38 <HAL_RCC_OscConfig+0x278>
{
if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
8000e18: f7ff fc24 bl 8000664 <HAL_GetTick>
8000e1c: 4602 mov r2, r0
8000e1e: 693b ldr r3, [r7, #16]
8000e20: 1ad3 subs r3, r2, r3
8000e22: 2b02 cmp r3, #2
8000e24: d908 bls.n 8000e38 <HAL_RCC_OscConfig+0x278>
{
return HAL_TIMEOUT;
8000e26: 2303 movs r3, #3
8000e28: e146 b.n 80010b8 <HAL_RCC_OscConfig+0x4f8>
8000e2a: bf00 nop
8000e2c: 40021000 .word 0x40021000
8000e30: 42420000 .word 0x42420000
8000e34: 42420480 .word 0x42420480
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
8000e38: 4b92 ldr r3, [pc, #584] ; (8001084 <HAL_RCC_OscConfig+0x4c4>)
8000e3a: 6a5b ldr r3, [r3, #36] ; 0x24
8000e3c: f003 0302 and.w r3, r3, #2
8000e40: 2b00 cmp r3, #0
8000e42: d1e9 bne.n 8000e18 <HAL_RCC_OscConfig+0x258>
}
}
}
}
/*------------------------------ LSE Configuration -------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
8000e44: 687b ldr r3, [r7, #4]
8000e46: 681b ldr r3, [r3, #0]
8000e48: f003 0304 and.w r3, r3, #4
8000e4c: 2b00 cmp r3, #0
8000e4e: f000 80a6 beq.w 8000f9e <HAL_RCC_OscConfig+0x3de>
{
FlagStatus pwrclkchanged = RESET;
8000e52: 2300 movs r3, #0
8000e54: 75fb strb r3, [r7, #23]
/* Check the parameters */
assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
/* Update LSE configuration in Backup Domain control register */
/* Requires to enable write access to Backup Domain of necessary */
if (__HAL_RCC_PWR_IS_CLK_DISABLED())
8000e56: 4b8b ldr r3, [pc, #556] ; (8001084 <HAL_RCC_OscConfig+0x4c4>)
8000e58: 69db ldr r3, [r3, #28]
8000e5a: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
8000e5e: 2b00 cmp r3, #0
8000e60: d10d bne.n 8000e7e <HAL_RCC_OscConfig+0x2be>
{
__HAL_RCC_PWR_CLK_ENABLE();
8000e62: 4b88 ldr r3, [pc, #544] ; (8001084 <HAL_RCC_OscConfig+0x4c4>)
8000e64: 69db ldr r3, [r3, #28]
8000e66: 4a87 ldr r2, [pc, #540] ; (8001084 <HAL_RCC_OscConfig+0x4c4>)
8000e68: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
8000e6c: 61d3 str r3, [r2, #28]
8000e6e: 4b85 ldr r3, [pc, #532] ; (8001084 <HAL_RCC_OscConfig+0x4c4>)
8000e70: 69db ldr r3, [r3, #28]
8000e72: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
8000e76: 60bb str r3, [r7, #8]
8000e78: 68bb ldr r3, [r7, #8]
pwrclkchanged = SET;
8000e7a: 2301 movs r3, #1
8000e7c: 75fb strb r3, [r7, #23]
}
if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
8000e7e: 4b82 ldr r3, [pc, #520] ; (8001088 <HAL_RCC_OscConfig+0x4c8>)
8000e80: 681b ldr r3, [r3, #0]
8000e82: f403 7380 and.w r3, r3, #256 ; 0x100
8000e86: 2b00 cmp r3, #0
8000e88: d118 bne.n 8000ebc <HAL_RCC_OscConfig+0x2fc>
{
/* Enable write access to Backup domain */
SET_BIT(PWR->CR, PWR_CR_DBP);
8000e8a: 4b7f ldr r3, [pc, #508] ; (8001088 <HAL_RCC_OscConfig+0x4c8>)
8000e8c: 681b ldr r3, [r3, #0]
8000e8e: 4a7e ldr r2, [pc, #504] ; (8001088 <HAL_RCC_OscConfig+0x4c8>)
8000e90: f443 7380 orr.w r3, r3, #256 ; 0x100
8000e94: 6013 str r3, [r2, #0]
/* Wait for Backup domain Write protection disable */
tickstart = HAL_GetTick();
8000e96: f7ff fbe5 bl 8000664 <HAL_GetTick>
8000e9a: 6138 str r0, [r7, #16]
while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
8000e9c: e008 b.n 8000eb0 <HAL_RCC_OscConfig+0x2f0>
{
if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
8000e9e: f7ff fbe1 bl 8000664 <HAL_GetTick>
8000ea2: 4602 mov r2, r0
8000ea4: 693b ldr r3, [r7, #16]
8000ea6: 1ad3 subs r3, r2, r3
8000ea8: 2b64 cmp r3, #100 ; 0x64
8000eaa: d901 bls.n 8000eb0 <HAL_RCC_OscConfig+0x2f0>
{
return HAL_TIMEOUT;
8000eac: 2303 movs r3, #3
8000eae: e103 b.n 80010b8 <HAL_RCC_OscConfig+0x4f8>
while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
8000eb0: 4b75 ldr r3, [pc, #468] ; (8001088 <HAL_RCC_OscConfig+0x4c8>)
8000eb2: 681b ldr r3, [r3, #0]
8000eb4: f403 7380 and.w r3, r3, #256 ; 0x100
8000eb8: 2b00 cmp r3, #0
8000eba: d0f0 beq.n 8000e9e <HAL_RCC_OscConfig+0x2de>
}
}
}
/* Set the new LSE configuration -----------------------------------------*/
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
8000ebc: 687b ldr r3, [r7, #4]
8000ebe: 68db ldr r3, [r3, #12]
8000ec0: 2b01 cmp r3, #1
8000ec2: d106 bne.n 8000ed2 <HAL_RCC_OscConfig+0x312>
8000ec4: 4b6f ldr r3, [pc, #444] ; (8001084 <HAL_RCC_OscConfig+0x4c4>)
8000ec6: 6a1b ldr r3, [r3, #32]
8000ec8: 4a6e ldr r2, [pc, #440] ; (8001084 <HAL_RCC_OscConfig+0x4c4>)
8000eca: f043 0301 orr.w r3, r3, #1
8000ece: 6213 str r3, [r2, #32]
8000ed0: e02d b.n 8000f2e <HAL_RCC_OscConfig+0x36e>
8000ed2: 687b ldr r3, [r7, #4]
8000ed4: 68db ldr r3, [r3, #12]
8000ed6: 2b00 cmp r3, #0
8000ed8: d10c bne.n 8000ef4 <HAL_RCC_OscConfig+0x334>
8000eda: 4b6a ldr r3, [pc, #424] ; (8001084 <HAL_RCC_OscConfig+0x4c4>)
8000edc: 6a1b ldr r3, [r3, #32]
8000ede: 4a69 ldr r2, [pc, #420] ; (8001084 <HAL_RCC_OscConfig+0x4c4>)
8000ee0: f023 0301 bic.w r3, r3, #1
8000ee4: 6213 str r3, [r2, #32]
8000ee6: 4b67 ldr r3, [pc, #412] ; (8001084 <HAL_RCC_OscConfig+0x4c4>)
8000ee8: 6a1b ldr r3, [r3, #32]
8000eea: 4a66 ldr r2, [pc, #408] ; (8001084 <HAL_RCC_OscConfig+0x4c4>)
8000eec: f023 0304 bic.w r3, r3, #4
8000ef0: 6213 str r3, [r2, #32]
8000ef2: e01c b.n 8000f2e <HAL_RCC_OscConfig+0x36e>
8000ef4: 687b ldr r3, [r7, #4]
8000ef6: 68db ldr r3, [r3, #12]
8000ef8: 2b05 cmp r3, #5
8000efa: d10c bne.n 8000f16 <HAL_RCC_OscConfig+0x356>
8000efc: 4b61 ldr r3, [pc, #388] ; (8001084 <HAL_RCC_OscConfig+0x4c4>)
8000efe: 6a1b ldr r3, [r3, #32]
8000f00: 4a60 ldr r2, [pc, #384] ; (8001084 <HAL_RCC_OscConfig+0x4c4>)
8000f02: f043 0304 orr.w r3, r3, #4
8000f06: 6213 str r3, [r2, #32]
8000f08: 4b5e ldr r3, [pc, #376] ; (8001084 <HAL_RCC_OscConfig+0x4c4>)
8000f0a: 6a1b ldr r3, [r3, #32]
8000f0c: 4a5d ldr r2, [pc, #372] ; (8001084 <HAL_RCC_OscConfig+0x4c4>)
8000f0e: f043 0301 orr.w r3, r3, #1
8000f12: 6213 str r3, [r2, #32]
8000f14: e00b b.n 8000f2e <HAL_RCC_OscConfig+0x36e>
8000f16: 4b5b ldr r3, [pc, #364] ; (8001084 <HAL_RCC_OscConfig+0x4c4>)
8000f18: 6a1b ldr r3, [r3, #32]
8000f1a: 4a5a ldr r2, [pc, #360] ; (8001084 <HAL_RCC_OscConfig+0x4c4>)
8000f1c: f023 0301 bic.w r3, r3, #1
8000f20: 6213 str r3, [r2, #32]
8000f22: 4b58 ldr r3, [pc, #352] ; (8001084 <HAL_RCC_OscConfig+0x4c4>)
8000f24: 6a1b ldr r3, [r3, #32]
8000f26: 4a57 ldr r2, [pc, #348] ; (8001084 <HAL_RCC_OscConfig+0x4c4>)
8000f28: f023 0304 bic.w r3, r3, #4
8000f2c: 6213 str r3, [r2, #32]
/* Check the LSE State */
if (RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
8000f2e: 687b ldr r3, [r7, #4]
8000f30: 68db ldr r3, [r3, #12]
8000f32: 2b00 cmp r3, #0
8000f34: d015 beq.n 8000f62 <HAL_RCC_OscConfig+0x3a2>
{
/* Get Start Tick */
tickstart = HAL_GetTick();
8000f36: f7ff fb95 bl 8000664 <HAL_GetTick>
8000f3a: 6138 str r0, [r7, #16]
/* Wait till LSE is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
8000f3c: e00a b.n 8000f54 <HAL_RCC_OscConfig+0x394>
{
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
8000f3e: f7ff fb91 bl 8000664 <HAL_GetTick>
8000f42: 4602 mov r2, r0
8000f44: 693b ldr r3, [r7, #16]
8000f46: 1ad3 subs r3, r2, r3
8000f48: f241 3288 movw r2, #5000 ; 0x1388
8000f4c: 4293 cmp r3, r2
8000f4e: d901 bls.n 8000f54 <HAL_RCC_OscConfig+0x394>
{
return HAL_TIMEOUT;
8000f50: 2303 movs r3, #3
8000f52: e0b1 b.n 80010b8 <HAL_RCC_OscConfig+0x4f8>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
8000f54: 4b4b ldr r3, [pc, #300] ; (8001084 <HAL_RCC_OscConfig+0x4c4>)
8000f56: 6a1b ldr r3, [r3, #32]
8000f58: f003 0302 and.w r3, r3, #2
8000f5c: 2b00 cmp r3, #0
8000f5e: d0ee beq.n 8000f3e <HAL_RCC_OscConfig+0x37e>
8000f60: e014 b.n 8000f8c <HAL_RCC_OscConfig+0x3cc>
}
}
else
{
/* Get Start Tick */
tickstart = HAL_GetTick();
8000f62: f7ff fb7f bl 8000664 <HAL_GetTick>
8000f66: 6138 str r0, [r7, #16]
/* Wait till LSE is disabled */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
8000f68: e00a b.n 8000f80 <HAL_RCC_OscConfig+0x3c0>
{
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
8000f6a: f7ff fb7b bl 8000664 <HAL_GetTick>
8000f6e: 4602 mov r2, r0
8000f70: 693b ldr r3, [r7, #16]
8000f72: 1ad3 subs r3, r2, r3
8000f74: f241 3288 movw r2, #5000 ; 0x1388
8000f78: 4293 cmp r3, r2
8000f7a: d901 bls.n 8000f80 <HAL_RCC_OscConfig+0x3c0>
{
return HAL_TIMEOUT;
8000f7c: 2303 movs r3, #3
8000f7e: e09b b.n 80010b8 <HAL_RCC_OscConfig+0x4f8>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
8000f80: 4b40 ldr r3, [pc, #256] ; (8001084 <HAL_RCC_OscConfig+0x4c4>)
8000f82: 6a1b ldr r3, [r3, #32]
8000f84: f003 0302 and.w r3, r3, #2
8000f88: 2b00 cmp r3, #0
8000f8a: d1ee bne.n 8000f6a <HAL_RCC_OscConfig+0x3aa>
}
}
}
/* Require to disable power clock if necessary */
if (pwrclkchanged == SET)
8000f8c: 7dfb ldrb r3, [r7, #23]
8000f8e: 2b01 cmp r3, #1
8000f90: d105 bne.n 8000f9e <HAL_RCC_OscConfig+0x3de>
{
__HAL_RCC_PWR_CLK_DISABLE();
8000f92: 4b3c ldr r3, [pc, #240] ; (8001084 <HAL_RCC_OscConfig+0x4c4>)
8000f94: 69db ldr r3, [r3, #28]
8000f96: 4a3b ldr r2, [pc, #236] ; (8001084 <HAL_RCC_OscConfig+0x4c4>)
8000f98: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000
8000f9c: 61d3 str r3, [r2, #28]
#endif /* RCC_CR_PLL2ON */
/*-------------------------------- PLL Configuration -----------------------*/
/* Check the parameters */
assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
8000f9e: 687b ldr r3, [r7, #4]
8000fa0: 69db ldr r3, [r3, #28]
8000fa2: 2b00 cmp r3, #0
8000fa4: f000 8087 beq.w 80010b6 <HAL_RCC_OscConfig+0x4f6>
{
/* Check if the PLL is used as system clock or not */
if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
8000fa8: 4b36 ldr r3, [pc, #216] ; (8001084 <HAL_RCC_OscConfig+0x4c4>)
8000faa: 685b ldr r3, [r3, #4]
8000fac: f003 030c and.w r3, r3, #12
8000fb0: 2b08 cmp r3, #8
8000fb2: d061 beq.n 8001078 <HAL_RCC_OscConfig+0x4b8>
{
if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
8000fb4: 687b ldr r3, [r7, #4]
8000fb6: 69db ldr r3, [r3, #28]
8000fb8: 2b02 cmp r3, #2
8000fba: d146 bne.n 800104a <HAL_RCC_OscConfig+0x48a>
/* Check the parameters */
assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL));
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
8000fbc: 4b33 ldr r3, [pc, #204] ; (800108c <HAL_RCC_OscConfig+0x4cc>)
8000fbe: 2200 movs r2, #0
8000fc0: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8000fc2: f7ff fb4f bl 8000664 <HAL_GetTick>
8000fc6: 6138 str r0, [r7, #16]
/* Wait till PLL is disabled */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8000fc8: e008 b.n 8000fdc <HAL_RCC_OscConfig+0x41c>
{
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
8000fca: f7ff fb4b bl 8000664 <HAL_GetTick>
8000fce: 4602 mov r2, r0
8000fd0: 693b ldr r3, [r7, #16]
8000fd2: 1ad3 subs r3, r2, r3
8000fd4: 2b02 cmp r3, #2
8000fd6: d901 bls.n 8000fdc <HAL_RCC_OscConfig+0x41c>
{
return HAL_TIMEOUT;
8000fd8: 2303 movs r3, #3
8000fda: e06d b.n 80010b8 <HAL_RCC_OscConfig+0x4f8>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8000fdc: 4b29 ldr r3, [pc, #164] ; (8001084 <HAL_RCC_OscConfig+0x4c4>)
8000fde: 681b ldr r3, [r3, #0]
8000fe0: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
8000fe4: 2b00 cmp r3, #0
8000fe6: d1f0 bne.n 8000fca <HAL_RCC_OscConfig+0x40a>
}
}
/* Configure the HSE prediv factor --------------------------------*/
/* It can be written only when the PLL is disabled. Not used in PLL source is different than HSE */
if (RCC_OscInitStruct->PLL.PLLSource == RCC_PLLSOURCE_HSE)
8000fe8: 687b ldr r3, [r7, #4]
8000fea: 6a1b ldr r3, [r3, #32]
8000fec: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
8000ff0: d108 bne.n 8001004 <HAL_RCC_OscConfig+0x444>
/* Set PREDIV1 source */
SET_BIT(RCC->CFGR2, RCC_OscInitStruct->Prediv1Source);
#endif /* RCC_CFGR2_PREDIV1SRC */
/* Set PREDIV1 Value */
__HAL_RCC_HSE_PREDIV_CONFIG(RCC_OscInitStruct->HSEPredivValue);
8000ff2: 4b24 ldr r3, [pc, #144] ; (8001084 <HAL_RCC_OscConfig+0x4c4>)
8000ff4: 685b ldr r3, [r3, #4]
8000ff6: f423 3200 bic.w r2, r3, #131072 ; 0x20000
8000ffa: 687b ldr r3, [r7, #4]
8000ffc: 689b ldr r3, [r3, #8]
8000ffe: 4921 ldr r1, [pc, #132] ; (8001084 <HAL_RCC_OscConfig+0x4c4>)
8001000: 4313 orrs r3, r2
8001002: 604b str r3, [r1, #4]
}
/* Configure the main PLL clock source and multiplication factors. */
__HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
8001004: 4b1f ldr r3, [pc, #124] ; (8001084 <HAL_RCC_OscConfig+0x4c4>)
8001006: 685b ldr r3, [r3, #4]
8001008: f423 1274 bic.w r2, r3, #3997696 ; 0x3d0000
800100c: 687b ldr r3, [r7, #4]
800100e: 6a19 ldr r1, [r3, #32]
8001010: 687b ldr r3, [r7, #4]
8001012: 6a5b ldr r3, [r3, #36] ; 0x24
8001014: 430b orrs r3, r1
8001016: 491b ldr r1, [pc, #108] ; (8001084 <HAL_RCC_OscConfig+0x4c4>)
8001018: 4313 orrs r3, r2
800101a: 604b str r3, [r1, #4]
RCC_OscInitStruct->PLL.PLLMUL);
/* Enable the main PLL. */
__HAL_RCC_PLL_ENABLE();
800101c: 4b1b ldr r3, [pc, #108] ; (800108c <HAL_RCC_OscConfig+0x4cc>)
800101e: 2201 movs r2, #1
8001020: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8001022: f7ff fb1f bl 8000664 <HAL_GetTick>
8001026: 6138 str r0, [r7, #16]
/* Wait till PLL is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
8001028: e008 b.n 800103c <HAL_RCC_OscConfig+0x47c>
{
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
800102a: f7ff fb1b bl 8000664 <HAL_GetTick>
800102e: 4602 mov r2, r0
8001030: 693b ldr r3, [r7, #16]
8001032: 1ad3 subs r3, r2, r3
8001034: 2b02 cmp r3, #2
8001036: d901 bls.n 800103c <HAL_RCC_OscConfig+0x47c>
{
return HAL_TIMEOUT;
8001038: 2303 movs r3, #3
800103a: e03d b.n 80010b8 <HAL_RCC_OscConfig+0x4f8>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
800103c: 4b11 ldr r3, [pc, #68] ; (8001084 <HAL_RCC_OscConfig+0x4c4>)
800103e: 681b ldr r3, [r3, #0]
8001040: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
8001044: 2b00 cmp r3, #0
8001046: d0f0 beq.n 800102a <HAL_RCC_OscConfig+0x46a>
8001048: e035 b.n 80010b6 <HAL_RCC_OscConfig+0x4f6>
}
}
else
{
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
800104a: 4b10 ldr r3, [pc, #64] ; (800108c <HAL_RCC_OscConfig+0x4cc>)
800104c: 2200 movs r2, #0
800104e: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8001050: f7ff fb08 bl 8000664 <HAL_GetTick>
8001054: 6138 str r0, [r7, #16]
/* Wait till PLL is disabled */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8001056: e008 b.n 800106a <HAL_RCC_OscConfig+0x4aa>
{
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
8001058: f7ff fb04 bl 8000664 <HAL_GetTick>
800105c: 4602 mov r2, r0
800105e: 693b ldr r3, [r7, #16]
8001060: 1ad3 subs r3, r2, r3
8001062: 2b02 cmp r3, #2
8001064: d901 bls.n 800106a <HAL_RCC_OscConfig+0x4aa>
{
return HAL_TIMEOUT;
8001066: 2303 movs r3, #3
8001068: e026 b.n 80010b8 <HAL_RCC_OscConfig+0x4f8>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
800106a: 4b06 ldr r3, [pc, #24] ; (8001084 <HAL_RCC_OscConfig+0x4c4>)
800106c: 681b ldr r3, [r3, #0]
800106e: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
8001072: 2b00 cmp r3, #0
8001074: d1f0 bne.n 8001058 <HAL_RCC_OscConfig+0x498>
8001076: e01e b.n 80010b6 <HAL_RCC_OscConfig+0x4f6>
}
}
else
{
/* Check if there is a request to disable the PLL used as System clock source */
if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
8001078: 687b ldr r3, [r7, #4]
800107a: 69db ldr r3, [r3, #28]
800107c: 2b01 cmp r3, #1
800107e: d107 bne.n 8001090 <HAL_RCC_OscConfig+0x4d0>
{
return HAL_ERROR;
8001080: 2301 movs r3, #1
8001082: e019 b.n 80010b8 <HAL_RCC_OscConfig+0x4f8>
8001084: 40021000 .word 0x40021000
8001088: 40007000 .word 0x40007000
800108c: 42420060 .word 0x42420060
}
else
{
/* Do not return HAL_ERROR if request repeats the current configuration */
pll_config = RCC->CFGR;
8001090: 4b0b ldr r3, [pc, #44] ; (80010c0 <HAL_RCC_OscConfig+0x500>)
8001092: 685b ldr r3, [r3, #4]
8001094: 60fb str r3, [r7, #12]
if ((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
8001096: 68fb ldr r3, [r7, #12]
8001098: f403 3280 and.w r2, r3, #65536 ; 0x10000
800109c: 687b ldr r3, [r7, #4]
800109e: 6a1b ldr r3, [r3, #32]
80010a0: 429a cmp r2, r3
80010a2: d106 bne.n 80010b2 <HAL_RCC_OscConfig+0x4f2>
(READ_BIT(pll_config, RCC_CFGR_PLLMULL) != RCC_OscInitStruct->PLL.PLLMUL))
80010a4: 68fb ldr r3, [r7, #12]
80010a6: f403 1270 and.w r2, r3, #3932160 ; 0x3c0000
80010aa: 687b ldr r3, [r7, #4]
80010ac: 6a5b ldr r3, [r3, #36] ; 0x24
if ((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
80010ae: 429a cmp r2, r3
80010b0: d001 beq.n 80010b6 <HAL_RCC_OscConfig+0x4f6>
{
return HAL_ERROR;
80010b2: 2301 movs r3, #1
80010b4: e000 b.n 80010b8 <HAL_RCC_OscConfig+0x4f8>
}
}
}
}
return HAL_OK;
80010b6: 2300 movs r3, #0
}
80010b8: 4618 mov r0, r3
80010ba: 3718 adds r7, #24
80010bc: 46bd mov sp, r7
80010be: bd80 pop {r7, pc}
80010c0: 40021000 .word 0x40021000
080010c4 <HAL_RCC_ClockConfig>:
* You can use @ref HAL_RCC_GetClockConfig() function to know which clock is
* currently used as system clock source.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
{
80010c4: b580 push {r7, lr}
80010c6: b084 sub sp, #16
80010c8: af00 add r7, sp, #0
80010ca: 6078 str r0, [r7, #4]
80010cc: 6039 str r1, [r7, #0]
uint32_t tickstart;
/* Check Null pointer */
if (RCC_ClkInitStruct == NULL)
80010ce: 687b ldr r3, [r7, #4]
80010d0: 2b00 cmp r3, #0
80010d2: d101 bne.n 80010d8 <HAL_RCC_ClockConfig+0x14>
{
return HAL_ERROR;
80010d4: 2301 movs r3, #1
80010d6: e0d0 b.n 800127a <HAL_RCC_ClockConfig+0x1b6>
must be correctly programmed according to the frequency of the CPU clock
(HCLK) of the device. */
#if defined(FLASH_ACR_LATENCY)
/* Increasing the number of wait states because of higher CPU frequency */
if (FLatency > __HAL_FLASH_GET_LATENCY())
80010d8: 4b6a ldr r3, [pc, #424] ; (8001284 <HAL_RCC_ClockConfig+0x1c0>)
80010da: 681b ldr r3, [r3, #0]
80010dc: f003 0307 and.w r3, r3, #7
80010e0: 683a ldr r2, [r7, #0]
80010e2: 429a cmp r2, r3
80010e4: d910 bls.n 8001108 <HAL_RCC_ClockConfig+0x44>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
80010e6: 4b67 ldr r3, [pc, #412] ; (8001284 <HAL_RCC_ClockConfig+0x1c0>)
80010e8: 681b ldr r3, [r3, #0]
80010ea: f023 0207 bic.w r2, r3, #7
80010ee: 4965 ldr r1, [pc, #404] ; (8001284 <HAL_RCC_ClockConfig+0x1c0>)
80010f0: 683b ldr r3, [r7, #0]
80010f2: 4313 orrs r3, r2
80010f4: 600b str r3, [r1, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if (__HAL_FLASH_GET_LATENCY() != FLatency)
80010f6: 4b63 ldr r3, [pc, #396] ; (8001284 <HAL_RCC_ClockConfig+0x1c0>)
80010f8: 681b ldr r3, [r3, #0]
80010fa: f003 0307 and.w r3, r3, #7
80010fe: 683a ldr r2, [r7, #0]
8001100: 429a cmp r2, r3
8001102: d001 beq.n 8001108 <HAL_RCC_ClockConfig+0x44>
{
return HAL_ERROR;
8001104: 2301 movs r3, #1
8001106: e0b8 b.n 800127a <HAL_RCC_ClockConfig+0x1b6>
}
}
#endif /* FLASH_ACR_LATENCY */
/*-------------------------- HCLK Configuration --------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
8001108: 687b ldr r3, [r7, #4]
800110a: 681b ldr r3, [r3, #0]
800110c: f003 0302 and.w r3, r3, #2
8001110: 2b00 cmp r3, #0
8001112: d020 beq.n 8001156 <HAL_RCC_ClockConfig+0x92>
{
/* Set the highest APBx dividers in order to ensure that we do not go through
a non-spec phase whatever we decrease or increase HCLK. */
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
8001114: 687b ldr r3, [r7, #4]
8001116: 681b ldr r3, [r3, #0]
8001118: f003 0304 and.w r3, r3, #4
800111c: 2b00 cmp r3, #0
800111e: d005 beq.n 800112c <HAL_RCC_ClockConfig+0x68>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16);
8001120: 4b59 ldr r3, [pc, #356] ; (8001288 <HAL_RCC_ClockConfig+0x1c4>)
8001122: 685b ldr r3, [r3, #4]
8001124: 4a58 ldr r2, [pc, #352] ; (8001288 <HAL_RCC_ClockConfig+0x1c4>)
8001126: f443 63e0 orr.w r3, r3, #1792 ; 0x700
800112a: 6053 str r3, [r2, #4]
}
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
800112c: 687b ldr r3, [r7, #4]
800112e: 681b ldr r3, [r3, #0]
8001130: f003 0308 and.w r3, r3, #8
8001134: 2b00 cmp r3, #0
8001136: d005 beq.n 8001144 <HAL_RCC_ClockConfig+0x80>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3));
8001138: 4b53 ldr r3, [pc, #332] ; (8001288 <HAL_RCC_ClockConfig+0x1c4>)
800113a: 685b ldr r3, [r3, #4]
800113c: 4a52 ldr r2, [pc, #328] ; (8001288 <HAL_RCC_ClockConfig+0x1c4>)
800113e: f443 5360 orr.w r3, r3, #14336 ; 0x3800
8001142: 6053 str r3, [r2, #4]
}
/* Set the new HCLK clock divider */
assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
8001144: 4b50 ldr r3, [pc, #320] ; (8001288 <HAL_RCC_ClockConfig+0x1c4>)
8001146: 685b ldr r3, [r3, #4]
8001148: f023 02f0 bic.w r2, r3, #240 ; 0xf0
800114c: 687b ldr r3, [r7, #4]
800114e: 689b ldr r3, [r3, #8]
8001150: 494d ldr r1, [pc, #308] ; (8001288 <HAL_RCC_ClockConfig+0x1c4>)
8001152: 4313 orrs r3, r2
8001154: 604b str r3, [r1, #4]
}
/*------------------------- SYSCLK Configuration ---------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
8001156: 687b ldr r3, [r7, #4]
8001158: 681b ldr r3, [r3, #0]
800115a: f003 0301 and.w r3, r3, #1
800115e: 2b00 cmp r3, #0
8001160: d040 beq.n 80011e4 <HAL_RCC_ClockConfig+0x120>
{
assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
/* HSE is selected as System Clock Source */
if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
8001162: 687b ldr r3, [r7, #4]
8001164: 685b ldr r3, [r3, #4]
8001166: 2b01 cmp r3, #1
8001168: d107 bne.n 800117a <HAL_RCC_ClockConfig+0xb6>
{
/* Check the HSE ready flag */
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
800116a: 4b47 ldr r3, [pc, #284] ; (8001288 <HAL_RCC_ClockConfig+0x1c4>)
800116c: 681b ldr r3, [r3, #0]
800116e: f403 3300 and.w r3, r3, #131072 ; 0x20000
8001172: 2b00 cmp r3, #0
8001174: d115 bne.n 80011a2 <HAL_RCC_ClockConfig+0xde>
{
return HAL_ERROR;
8001176: 2301 movs r3, #1
8001178: e07f b.n 800127a <HAL_RCC_ClockConfig+0x1b6>
}
}
/* PLL is selected as System Clock Source */
else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
800117a: 687b ldr r3, [r7, #4]
800117c: 685b ldr r3, [r3, #4]
800117e: 2b02 cmp r3, #2
8001180: d107 bne.n 8001192 <HAL_RCC_ClockConfig+0xce>
{
/* Check the PLL ready flag */
if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
8001182: 4b41 ldr r3, [pc, #260] ; (8001288 <HAL_RCC_ClockConfig+0x1c4>)
8001184: 681b ldr r3, [r3, #0]
8001186: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
800118a: 2b00 cmp r3, #0
800118c: d109 bne.n 80011a2 <HAL_RCC_ClockConfig+0xde>
{
return HAL_ERROR;
800118e: 2301 movs r3, #1
8001190: e073 b.n 800127a <HAL_RCC_ClockConfig+0x1b6>
}
/* HSI is selected as System Clock Source */
else
{
/* Check the HSI ready flag */
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
8001192: 4b3d ldr r3, [pc, #244] ; (8001288 <HAL_RCC_ClockConfig+0x1c4>)
8001194: 681b ldr r3, [r3, #0]
8001196: f003 0302 and.w r3, r3, #2
800119a: 2b00 cmp r3, #0
800119c: d101 bne.n 80011a2 <HAL_RCC_ClockConfig+0xde>
{
return HAL_ERROR;
800119e: 2301 movs r3, #1
80011a0: e06b b.n 800127a <HAL_RCC_ClockConfig+0x1b6>
}
}
__HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
80011a2: 4b39 ldr r3, [pc, #228] ; (8001288 <HAL_RCC_ClockConfig+0x1c4>)
80011a4: 685b ldr r3, [r3, #4]
80011a6: f023 0203 bic.w r2, r3, #3
80011aa: 687b ldr r3, [r7, #4]
80011ac: 685b ldr r3, [r3, #4]
80011ae: 4936 ldr r1, [pc, #216] ; (8001288 <HAL_RCC_ClockConfig+0x1c4>)
80011b0: 4313 orrs r3, r2
80011b2: 604b str r3, [r1, #4]
/* Get Start Tick */
tickstart = HAL_GetTick();
80011b4: f7ff fa56 bl 8000664 <HAL_GetTick>
80011b8: 60f8 str r0, [r7, #12]
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
80011ba: e00a b.n 80011d2 <HAL_RCC_ClockConfig+0x10e>
{
if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
80011bc: f7ff fa52 bl 8000664 <HAL_GetTick>
80011c0: 4602 mov r2, r0
80011c2: 68fb ldr r3, [r7, #12]
80011c4: 1ad3 subs r3, r2, r3
80011c6: f241 3288 movw r2, #5000 ; 0x1388
80011ca: 4293 cmp r3, r2
80011cc: d901 bls.n 80011d2 <HAL_RCC_ClockConfig+0x10e>
{
return HAL_TIMEOUT;
80011ce: 2303 movs r3, #3
80011d0: e053 b.n 800127a <HAL_RCC_ClockConfig+0x1b6>
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
80011d2: 4b2d ldr r3, [pc, #180] ; (8001288 <HAL_RCC_ClockConfig+0x1c4>)
80011d4: 685b ldr r3, [r3, #4]
80011d6: f003 020c and.w r2, r3, #12
80011da: 687b ldr r3, [r7, #4]
80011dc: 685b ldr r3, [r3, #4]
80011de: 009b lsls r3, r3, #2
80011e0: 429a cmp r2, r3
80011e2: d1eb bne.n 80011bc <HAL_RCC_ClockConfig+0xf8>
}
}
#if defined(FLASH_ACR_LATENCY)
/* Decreasing the number of wait states because of lower CPU frequency */
if (FLatency < __HAL_FLASH_GET_LATENCY())
80011e4: 4b27 ldr r3, [pc, #156] ; (8001284 <HAL_RCC_ClockConfig+0x1c0>)
80011e6: 681b ldr r3, [r3, #0]
80011e8: f003 0307 and.w r3, r3, #7
80011ec: 683a ldr r2, [r7, #0]
80011ee: 429a cmp r2, r3
80011f0: d210 bcs.n 8001214 <HAL_RCC_ClockConfig+0x150>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
80011f2: 4b24 ldr r3, [pc, #144] ; (8001284 <HAL_RCC_ClockConfig+0x1c0>)
80011f4: 681b ldr r3, [r3, #0]
80011f6: f023 0207 bic.w r2, r3, #7
80011fa: 4922 ldr r1, [pc, #136] ; (8001284 <HAL_RCC_ClockConfig+0x1c0>)
80011fc: 683b ldr r3, [r7, #0]
80011fe: 4313 orrs r3, r2
8001200: 600b str r3, [r1, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if (__HAL_FLASH_GET_LATENCY() != FLatency)
8001202: 4b20 ldr r3, [pc, #128] ; (8001284 <HAL_RCC_ClockConfig+0x1c0>)
8001204: 681b ldr r3, [r3, #0]
8001206: f003 0307 and.w r3, r3, #7
800120a: 683a ldr r2, [r7, #0]
800120c: 429a cmp r2, r3
800120e: d001 beq.n 8001214 <HAL_RCC_ClockConfig+0x150>
{
return HAL_ERROR;
8001210: 2301 movs r3, #1
8001212: e032 b.n 800127a <HAL_RCC_ClockConfig+0x1b6>
}
}
#endif /* FLASH_ACR_LATENCY */
/*-------------------------- PCLK1 Configuration ---------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
8001214: 687b ldr r3, [r7, #4]
8001216: 681b ldr r3, [r3, #0]
8001218: f003 0304 and.w r3, r3, #4
800121c: 2b00 cmp r3, #0
800121e: d008 beq.n 8001232 <HAL_RCC_ClockConfig+0x16e>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
8001220: 4b19 ldr r3, [pc, #100] ; (8001288 <HAL_RCC_ClockConfig+0x1c4>)
8001222: 685b ldr r3, [r3, #4]
8001224: f423 62e0 bic.w r2, r3, #1792 ; 0x700
8001228: 687b ldr r3, [r7, #4]
800122a: 68db ldr r3, [r3, #12]
800122c: 4916 ldr r1, [pc, #88] ; (8001288 <HAL_RCC_ClockConfig+0x1c4>)
800122e: 4313 orrs r3, r2
8001230: 604b str r3, [r1, #4]
}
/*-------------------------- PCLK2 Configuration ---------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
8001232: 687b ldr r3, [r7, #4]
8001234: 681b ldr r3, [r3, #0]
8001236: f003 0308 and.w r3, r3, #8
800123a: 2b00 cmp r3, #0
800123c: d009 beq.n 8001252 <HAL_RCC_ClockConfig+0x18e>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3));
800123e: 4b12 ldr r3, [pc, #72] ; (8001288 <HAL_RCC_ClockConfig+0x1c4>)
8001240: 685b ldr r3, [r3, #4]
8001242: f423 5260 bic.w r2, r3, #14336 ; 0x3800
8001246: 687b ldr r3, [r7, #4]
8001248: 691b ldr r3, [r3, #16]
800124a: 00db lsls r3, r3, #3
800124c: 490e ldr r1, [pc, #56] ; (8001288 <HAL_RCC_ClockConfig+0x1c4>)
800124e: 4313 orrs r3, r2
8001250: 604b str r3, [r1, #4]
}
/* Update the SystemCoreClock global variable */
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos];
8001252: f000 f821 bl 8001298 <HAL_RCC_GetSysClockFreq>
8001256: 4602 mov r2, r0
8001258: 4b0b ldr r3, [pc, #44] ; (8001288 <HAL_RCC_ClockConfig+0x1c4>)
800125a: 685b ldr r3, [r3, #4]
800125c: 091b lsrs r3, r3, #4
800125e: f003 030f and.w r3, r3, #15
8001262: 490a ldr r1, [pc, #40] ; (800128c <HAL_RCC_ClockConfig+0x1c8>)
8001264: 5ccb ldrb r3, [r1, r3]
8001266: fa22 f303 lsr.w r3, r2, r3
800126a: 4a09 ldr r2, [pc, #36] ; (8001290 <HAL_RCC_ClockConfig+0x1cc>)
800126c: 6013 str r3, [r2, #0]
/* Configure the source of time base considering new system clocks settings*/
HAL_InitTick(uwTickPrio);
800126e: 4b09 ldr r3, [pc, #36] ; (8001294 <HAL_RCC_ClockConfig+0x1d0>)
8001270: 681b ldr r3, [r3, #0]
8001272: 4618 mov r0, r3
8001274: f7ff f9b4 bl 80005e0 <HAL_InitTick>
return HAL_OK;
8001278: 2300 movs r3, #0
}
800127a: 4618 mov r0, r3
800127c: 3710 adds r7, #16
800127e: 46bd mov sp, r7
8001280: bd80 pop {r7, pc}
8001282: bf00 nop
8001284: 40022000 .word 0x40022000
8001288: 40021000 .word 0x40021000
800128c: 08001fac .word 0x08001fac
8001290: 20000000 .word 0x20000000
8001294: 20000004 .word 0x20000004
08001298 <HAL_RCC_GetSysClockFreq>:
* right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
*
* @retval SYSCLK frequency
*/
uint32_t HAL_RCC_GetSysClockFreq(void)
{
8001298: b490 push {r4, r7}
800129a: b08a sub sp, #40 ; 0x28
800129c: af00 add r7, sp, #0
#if defined(RCC_CFGR2_PREDIV1SRC)
const uint8_t aPLLMULFactorTable[14] = {0, 0, 4, 5, 6, 7, 8, 9, 0, 0, 0, 0, 0, 13};
const uint8_t aPredivFactorTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16};
#else
const uint8_t aPLLMULFactorTable[16] = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16};
800129e: 4b29 ldr r3, [pc, #164] ; (8001344 <HAL_RCC_GetSysClockFreq+0xac>)
80012a0: 1d3c adds r4, r7, #4
80012a2: cb0f ldmia r3, {r0, r1, r2, r3}
80012a4: e884 000f stmia.w r4, {r0, r1, r2, r3}
#if defined(RCC_CFGR2_PREDIV1)
const uint8_t aPredivFactorTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16};
#else
const uint8_t aPredivFactorTable[2] = {1, 2};
80012a8: f240 2301 movw r3, #513 ; 0x201
80012ac: 803b strh r3, [r7, #0]
#endif /*RCC_CFGR2_PREDIV1*/
#endif
uint32_t tmpreg = 0U, prediv = 0U, pllclk = 0U, pllmul = 0U;
80012ae: 2300 movs r3, #0
80012b0: 61fb str r3, [r7, #28]
80012b2: 2300 movs r3, #0
80012b4: 61bb str r3, [r7, #24]
80012b6: 2300 movs r3, #0
80012b8: 627b str r3, [r7, #36] ; 0x24
80012ba: 2300 movs r3, #0
80012bc: 617b str r3, [r7, #20]
uint32_t sysclockfreq = 0U;
80012be: 2300 movs r3, #0
80012c0: 623b str r3, [r7, #32]
#if defined(RCC_CFGR2_PREDIV1SRC)
uint32_t prediv2 = 0U, pll2mul = 0U;
#endif /*RCC_CFGR2_PREDIV1SRC*/
tmpreg = RCC->CFGR;
80012c2: 4b21 ldr r3, [pc, #132] ; (8001348 <HAL_RCC_GetSysClockFreq+0xb0>)
80012c4: 685b ldr r3, [r3, #4]
80012c6: 61fb str r3, [r7, #28]
/* Get SYSCLK source -------------------------------------------------------*/
switch (tmpreg & RCC_CFGR_SWS)
80012c8: 69fb ldr r3, [r7, #28]
80012ca: f003 030c and.w r3, r3, #12
80012ce: 2b04 cmp r3, #4
80012d0: d002 beq.n 80012d8 <HAL_RCC_GetSysClockFreq+0x40>
80012d2: 2b08 cmp r3, #8
80012d4: d003 beq.n 80012de <HAL_RCC_GetSysClockFreq+0x46>
80012d6: e02b b.n 8001330 <HAL_RCC_GetSysClockFreq+0x98>
{
case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */
{
sysclockfreq = HSE_VALUE;
80012d8: 4b1c ldr r3, [pc, #112] ; (800134c <HAL_RCC_GetSysClockFreq+0xb4>)
80012da: 623b str r3, [r7, #32]
break;
80012dc: e02b b.n 8001336 <HAL_RCC_GetSysClockFreq+0x9e>
}
case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */
{
pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos];
80012de: 69fb ldr r3, [r7, #28]
80012e0: 0c9b lsrs r3, r3, #18
80012e2: f003 030f and.w r3, r3, #15
80012e6: 3328 adds r3, #40 ; 0x28
80012e8: 443b add r3, r7
80012ea: f813 3c24 ldrb.w r3, [r3, #-36]
80012ee: 617b str r3, [r7, #20]
if ((tmpreg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2)
80012f0: 69fb ldr r3, [r7, #28]
80012f2: f403 3380 and.w r3, r3, #65536 ; 0x10000
80012f6: 2b00 cmp r3, #0
80012f8: d012 beq.n 8001320 <HAL_RCC_GetSysClockFreq+0x88>
{
#if defined(RCC_CFGR2_PREDIV1)
prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> RCC_CFGR2_PREDIV1_Pos];
#else
prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos];
80012fa: 4b13 ldr r3, [pc, #76] ; (8001348 <HAL_RCC_GetSysClockFreq+0xb0>)
80012fc: 685b ldr r3, [r3, #4]
80012fe: 0c5b lsrs r3, r3, #17
8001300: f003 0301 and.w r3, r3, #1
8001304: 3328 adds r3, #40 ; 0x28
8001306: 443b add r3, r7
8001308: f813 3c28 ldrb.w r3, [r3, #-40]
800130c: 61bb str r3, [r7, #24]
{
pllclk = pllclk / 2;
}
#else
/* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */
pllclk = (uint32_t)((HSE_VALUE * pllmul) / prediv);
800130e: 697b ldr r3, [r7, #20]
8001310: 4a0e ldr r2, [pc, #56] ; (800134c <HAL_RCC_GetSysClockFreq+0xb4>)
8001312: fb03 f202 mul.w r2, r3, r2
8001316: 69bb ldr r3, [r7, #24]
8001318: fbb2 f3f3 udiv r3, r2, r3
800131c: 627b str r3, [r7, #36] ; 0x24
800131e: e004 b.n 800132a <HAL_RCC_GetSysClockFreq+0x92>
#endif /*RCC_CFGR2_PREDIV1SRC*/
}
else
{
/* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */
pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul);
8001320: 697b ldr r3, [r7, #20]
8001322: 4a0b ldr r2, [pc, #44] ; (8001350 <HAL_RCC_GetSysClockFreq+0xb8>)
8001324: fb02 f303 mul.w r3, r2, r3
8001328: 627b str r3, [r7, #36] ; 0x24
}
sysclockfreq = pllclk;
800132a: 6a7b ldr r3, [r7, #36] ; 0x24
800132c: 623b str r3, [r7, #32]
break;
800132e: e002 b.n 8001336 <HAL_RCC_GetSysClockFreq+0x9e>
}
case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
default: /* HSI used as system clock */
{
sysclockfreq = HSI_VALUE;
8001330: 4b06 ldr r3, [pc, #24] ; (800134c <HAL_RCC_GetSysClockFreq+0xb4>)
8001332: 623b str r3, [r7, #32]
break;
8001334: bf00 nop
}
}
return sysclockfreq;
8001336: 6a3b ldr r3, [r7, #32]
}
8001338: 4618 mov r0, r3
800133a: 3728 adds r7, #40 ; 0x28
800133c: 46bd mov sp, r7
800133e: bc90 pop {r4, r7}
8001340: 4770 bx lr
8001342: bf00 nop
8001344: 08001f9c .word 0x08001f9c
8001348: 40021000 .word 0x40021000
800134c: 007a1200 .word 0x007a1200
8001350: 003d0900 .word 0x003d0900
08001354 <RCC_Delay>:
* @brief This function provides delay (in milliseconds) based on CPU cycles method.
* @param mdelay: specifies the delay time length, in milliseconds.
* @retval None
*/
static void RCC_Delay(uint32_t mdelay)
{
8001354: b480 push {r7}
8001356: b085 sub sp, #20
8001358: af00 add r7, sp, #0
800135a: 6078 str r0, [r7, #4]
__IO uint32_t Delay = mdelay * (SystemCoreClock / 8U / 1000U);
800135c: 4b0a ldr r3, [pc, #40] ; (8001388 <RCC_Delay+0x34>)
800135e: 681b ldr r3, [r3, #0]
8001360: 4a0a ldr r2, [pc, #40] ; (800138c <RCC_Delay+0x38>)
8001362: fba2 2303 umull r2, r3, r2, r3
8001366: 0a5b lsrs r3, r3, #9
8001368: 687a ldr r2, [r7, #4]
800136a: fb02 f303 mul.w r3, r2, r3
800136e: 60fb str r3, [r7, #12]
do
{
__NOP();
8001370: bf00 nop
}
while (Delay --);
8001372: 68fb ldr r3, [r7, #12]
8001374: 1e5a subs r2, r3, #1
8001376: 60fa str r2, [r7, #12]
8001378: 2b00 cmp r3, #0
800137a: d1f9 bne.n 8001370 <RCC_Delay+0x1c>
}
800137c: bf00 nop
800137e: bf00 nop
8001380: 3714 adds r7, #20
8001382: 46bd mov sp, r7
8001384: bc80 pop {r7}
8001386: 4770 bx lr
8001388: 20000000 .word 0x20000000
800138c: 10624dd3 .word 0x10624dd3
08001390 <HAL_TIM_Base_Init>:
* Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
* @param htim TIM Base handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
{
8001390: b580 push {r7, lr}
8001392: b082 sub sp, #8
8001394: af00 add r7, sp, #0
8001396: 6078 str r0, [r7, #4]
/* Check the TIM handle allocation */
if (htim == NULL)
8001398: 687b ldr r3, [r7, #4]
800139a: 2b00 cmp r3, #0
800139c: d101 bne.n 80013a2 <HAL_TIM_Base_Init+0x12>
{
return HAL_ERROR;
800139e: 2301 movs r3, #1
80013a0: e041 b.n 8001426 <HAL_TIM_Base_Init+0x96>
assert_param(IS_TIM_INSTANCE(htim->Instance));
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
if (htim->State == HAL_TIM_STATE_RESET)
80013a2: 687b ldr r3, [r7, #4]
80013a4: f893 303d ldrb.w r3, [r3, #61] ; 0x3d
80013a8: b2db uxtb r3, r3
80013aa: 2b00 cmp r3, #0
80013ac: d106 bne.n 80013bc <HAL_TIM_Base_Init+0x2c>
{
/* Allocate lock resource and initialize it */
htim->Lock = HAL_UNLOCKED;
80013ae: 687b ldr r3, [r7, #4]
80013b0: 2200 movs r2, #0
80013b2: f883 203c strb.w r2, [r3, #60] ; 0x3c
}
/* Init the low level hardware : GPIO, CLOCK, NVIC */
htim->Base_MspInitCallback(htim);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC */
HAL_TIM_Base_MspInit(htim);
80013b6: 6878 ldr r0, [r7, #4]
80013b8: f7ff f884 bl 80004c4 <HAL_TIM_Base_MspInit>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
/* Set the TIM state */
htim->State = HAL_TIM_STATE_BUSY;
80013bc: 687b ldr r3, [r7, #4]
80013be: 2202 movs r2, #2
80013c0: f883 203d strb.w r2, [r3, #61] ; 0x3d
/* Set the Time Base configuration */
TIM_Base_SetConfig(htim->Instance, &htim->Init);
80013c4: 687b ldr r3, [r7, #4]
80013c6: 681a ldr r2, [r3, #0]
80013c8: 687b ldr r3, [r7, #4]
80013ca: 3304 adds r3, #4
80013cc: 4619 mov r1, r3
80013ce: 4610 mov r0, r2
80013d0: f000 faaa bl 8001928 <TIM_Base_SetConfig>
/* Initialize the DMA burst operation state */
htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
80013d4: 687b ldr r3, [r7, #4]
80013d6: 2201 movs r2, #1
80013d8: f883 2046 strb.w r2, [r3, #70] ; 0x46
/* Initialize the TIM channels state */
TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
80013dc: 687b ldr r3, [r7, #4]
80013de: 2201 movs r2, #1
80013e0: f883 203e strb.w r2, [r3, #62] ; 0x3e
80013e4: 687b ldr r3, [r7, #4]
80013e6: 2201 movs r2, #1
80013e8: f883 203f strb.w r2, [r3, #63] ; 0x3f
80013ec: 687b ldr r3, [r7, #4]
80013ee: 2201 movs r2, #1
80013f0: f883 2040 strb.w r2, [r3, #64] ; 0x40
80013f4: 687b ldr r3, [r7, #4]
80013f6: 2201 movs r2, #1
80013f8: f883 2041 strb.w r2, [r3, #65] ; 0x41
TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
80013fc: 687b ldr r3, [r7, #4]
80013fe: 2201 movs r2, #1
8001400: f883 2042 strb.w r2, [r3, #66] ; 0x42
8001404: 687b ldr r3, [r7, #4]
8001406: 2201 movs r2, #1
8001408: f883 2043 strb.w r2, [r3, #67] ; 0x43
800140c: 687b ldr r3, [r7, #4]
800140e: 2201 movs r2, #1
8001410: f883 2044 strb.w r2, [r3, #68] ; 0x44
8001414: 687b ldr r3, [r7, #4]
8001416: 2201 movs r2, #1
8001418: f883 2045 strb.w r2, [r3, #69] ; 0x45
/* Initialize the TIM state*/
htim->State = HAL_TIM_STATE_READY;
800141c: 687b ldr r3, [r7, #4]
800141e: 2201 movs r2, #1
8001420: f883 203d strb.w r2, [r3, #61] ; 0x3d
return HAL_OK;
8001424: 2300 movs r3, #0
}
8001426: 4618 mov r0, r3
8001428: 3708 adds r7, #8
800142a: 46bd mov sp, r7
800142c: bd80 pop {r7, pc}
0800142e <HAL_TIM_PWM_Init>:
* Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init()
* @param htim TIM PWM handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
{
800142e: b580 push {r7, lr}
8001430: b082 sub sp, #8
8001432: af00 add r7, sp, #0
8001434: 6078 str r0, [r7, #4]
/* Check the TIM handle allocation */
if (htim == NULL)
8001436: 687b ldr r3, [r7, #4]
8001438: 2b00 cmp r3, #0
800143a: d101 bne.n 8001440 <HAL_TIM_PWM_Init+0x12>
{
return HAL_ERROR;
800143c: 2301 movs r3, #1
800143e: e041 b.n 80014c4 <HAL_TIM_PWM_Init+0x96>
assert_param(IS_TIM_INSTANCE(htim->Instance));
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
if (htim->State == HAL_TIM_STATE_RESET)
8001440: 687b ldr r3, [r7, #4]
8001442: f893 303d ldrb.w r3, [r3, #61] ; 0x3d
8001446: b2db uxtb r3, r3
8001448: 2b00 cmp r3, #0
800144a: d106 bne.n 800145a <HAL_TIM_PWM_Init+0x2c>
{
/* Allocate lock resource and initialize it */
htim->Lock = HAL_UNLOCKED;
800144c: 687b ldr r3, [r7, #4]
800144e: 2200 movs r2, #0
8001450: f883 203c strb.w r2, [r3, #60] ; 0x3c
}
/* Init the low level hardware : GPIO, CLOCK, NVIC */
htim->PWM_MspInitCallback(htim);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
HAL_TIM_PWM_MspInit(htim);
8001454: 6878 ldr r0, [r7, #4]
8001456: f000 f839 bl 80014cc <HAL_TIM_PWM_MspInit>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
/* Set the TIM state */
htim->State = HAL_TIM_STATE_BUSY;
800145a: 687b ldr r3, [r7, #4]
800145c: 2202 movs r2, #2
800145e: f883 203d strb.w r2, [r3, #61] ; 0x3d
/* Init the base time for the PWM */
TIM_Base_SetConfig(htim->Instance, &htim->Init);
8001462: 687b ldr r3, [r7, #4]
8001464: 681a ldr r2, [r3, #0]
8001466: 687b ldr r3, [r7, #4]
8001468: 3304 adds r3, #4
800146a: 4619 mov r1, r3
800146c: 4610 mov r0, r2
800146e: f000 fa5b bl 8001928 <TIM_Base_SetConfig>
/* Initialize the DMA burst operation state */
htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
8001472: 687b ldr r3, [r7, #4]
8001474: 2201 movs r2, #1
8001476: f883 2046 strb.w r2, [r3, #70] ; 0x46
/* Initialize the TIM channels state */
TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
800147a: 687b ldr r3, [r7, #4]
800147c: 2201 movs r2, #1
800147e: f883 203e strb.w r2, [r3, #62] ; 0x3e
8001482: 687b ldr r3, [r7, #4]
8001484: 2201 movs r2, #1
8001486: f883 203f strb.w r2, [r3, #63] ; 0x3f
800148a: 687b ldr r3, [r7, #4]
800148c: 2201 movs r2, #1
800148e: f883 2040 strb.w r2, [r3, #64] ; 0x40
8001492: 687b ldr r3, [r7, #4]
8001494: 2201 movs r2, #1
8001496: f883 2041 strb.w r2, [r3, #65] ; 0x41
TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
800149a: 687b ldr r3, [r7, #4]
800149c: 2201 movs r2, #1
800149e: f883 2042 strb.w r2, [r3, #66] ; 0x42
80014a2: 687b ldr r3, [r7, #4]
80014a4: 2201 movs r2, #1
80014a6: f883 2043 strb.w r2, [r3, #67] ; 0x43
80014aa: 687b ldr r3, [r7, #4]
80014ac: 2201 movs r2, #1
80014ae: f883 2044 strb.w r2, [r3, #68] ; 0x44
80014b2: 687b ldr r3, [r7, #4]
80014b4: 2201 movs r2, #1
80014b6: f883 2045 strb.w r2, [r3, #69] ; 0x45
/* Initialize the TIM state*/
htim->State = HAL_TIM_STATE_READY;
80014ba: 687b ldr r3, [r7, #4]
80014bc: 2201 movs r2, #1
80014be: f883 203d strb.w r2, [r3, #61] ; 0x3d
return HAL_OK;
80014c2: 2300 movs r3, #0
}
80014c4: 4618 mov r0, r3
80014c6: 3708 adds r7, #8
80014c8: 46bd mov sp, r7
80014ca: bd80 pop {r7, pc}
080014cc <HAL_TIM_PWM_MspInit>:
* @brief Initializes the TIM PWM MSP.
* @param htim TIM PWM handle
* @retval None
*/
__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
{
80014cc: b480 push {r7}
80014ce: b083 sub sp, #12
80014d0: af00 add r7, sp, #0
80014d2: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_PWM_MspInit could be implemented in the user file
*/
}
80014d4: bf00 nop
80014d6: 370c adds r7, #12
80014d8: 46bd mov sp, r7
80014da: bc80 pop {r7}
80014dc: 4770 bx lr
...
080014e0 <HAL_TIM_PWM_Start>:
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
{
80014e0: b580 push {r7, lr}
80014e2: b084 sub sp, #16
80014e4: af00 add r7, sp, #0
80014e6: 6078 str r0, [r7, #4]
80014e8: 6039 str r1, [r7, #0]
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
/* Check the TIM channel state */
if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
80014ea: 683b ldr r3, [r7, #0]
80014ec: 2b00 cmp r3, #0
80014ee: d109 bne.n 8001504 <HAL_TIM_PWM_Start+0x24>
80014f0: 687b ldr r3, [r7, #4]
80014f2: f893 303e ldrb.w r3, [r3, #62] ; 0x3e
80014f6: b2db uxtb r3, r3
80014f8: 2b01 cmp r3, #1
80014fa: bf14 ite ne
80014fc: 2301 movne r3, #1
80014fe: 2300 moveq r3, #0
8001500: b2db uxtb r3, r3
8001502: e022 b.n 800154a <HAL_TIM_PWM_Start+0x6a>
8001504: 683b ldr r3, [r7, #0]
8001506: 2b04 cmp r3, #4
8001508: d109 bne.n 800151e <HAL_TIM_PWM_Start+0x3e>
800150a: 687b ldr r3, [r7, #4]
800150c: f893 303f ldrb.w r3, [r3, #63] ; 0x3f
8001510: b2db uxtb r3, r3
8001512: 2b01 cmp r3, #1
8001514: bf14 ite ne
8001516: 2301 movne r3, #1
8001518: 2300 moveq r3, #0
800151a: b2db uxtb r3, r3
800151c: e015 b.n 800154a <HAL_TIM_PWM_Start+0x6a>
800151e: 683b ldr r3, [r7, #0]
8001520: 2b08 cmp r3, #8
8001522: d109 bne.n 8001538 <HAL_TIM_PWM_Start+0x58>
8001524: 687b ldr r3, [r7, #4]
8001526: f893 3040 ldrb.w r3, [r3, #64] ; 0x40
800152a: b2db uxtb r3, r3
800152c: 2b01 cmp r3, #1
800152e: bf14 ite ne
8001530: 2301 movne r3, #1
8001532: 2300 moveq r3, #0
8001534: b2db uxtb r3, r3
8001536: e008 b.n 800154a <HAL_TIM_PWM_Start+0x6a>
8001538: 687b ldr r3, [r7, #4]
800153a: f893 3041 ldrb.w r3, [r3, #65] ; 0x41
800153e: b2db uxtb r3, r3
8001540: 2b01 cmp r3, #1
8001542: bf14 ite ne
8001544: 2301 movne r3, #1
8001546: 2300 moveq r3, #0
8001548: b2db uxtb r3, r3
800154a: 2b00 cmp r3, #0
800154c: d001 beq.n 8001552 <HAL_TIM_PWM_Start+0x72>
{
return HAL_ERROR;
800154e: 2301 movs r3, #1
8001550: e05e b.n 8001610 <HAL_TIM_PWM_Start+0x130>
}
/* Set the TIM channel state */
TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
8001552: 683b ldr r3, [r7, #0]
8001554: 2b00 cmp r3, #0
8001556: d104 bne.n 8001562 <HAL_TIM_PWM_Start+0x82>
8001558: 687b ldr r3, [r7, #4]
800155a: 2202 movs r2, #2
800155c: f883 203e strb.w r2, [r3, #62] ; 0x3e
8001560: e013 b.n 800158a <HAL_TIM_PWM_Start+0xaa>
8001562: 683b ldr r3, [r7, #0]
8001564: 2b04 cmp r3, #4
8001566: d104 bne.n 8001572 <HAL_TIM_PWM_Start+0x92>
8001568: 687b ldr r3, [r7, #4]
800156a: 2202 movs r2, #2
800156c: f883 203f strb.w r2, [r3, #63] ; 0x3f
8001570: e00b b.n 800158a <HAL_TIM_PWM_Start+0xaa>
8001572: 683b ldr r3, [r7, #0]
8001574: 2b08 cmp r3, #8
8001576: d104 bne.n 8001582 <HAL_TIM_PWM_Start+0xa2>
8001578: 687b ldr r3, [r7, #4]
800157a: 2202 movs r2, #2
800157c: f883 2040 strb.w r2, [r3, #64] ; 0x40
8001580: e003 b.n 800158a <HAL_TIM_PWM_Start+0xaa>
8001582: 687b ldr r3, [r7, #4]
8001584: 2202 movs r2, #2
8001586: f883 2041 strb.w r2, [r3, #65] ; 0x41
/* Enable the Capture compare channel */
TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
800158a: 687b ldr r3, [r7, #4]
800158c: 681b ldr r3, [r3, #0]
800158e: 2201 movs r2, #1
8001590: 6839 ldr r1, [r7, #0]
8001592: 4618 mov r0, r3
8001594: f000 fc48 bl 8001e28 <TIM_CCxChannelCmd>
if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
8001598: 687b ldr r3, [r7, #4]
800159a: 681b ldr r3, [r3, #0]
800159c: 4a1e ldr r2, [pc, #120] ; (8001618 <HAL_TIM_PWM_Start+0x138>)
800159e: 4293 cmp r3, r2
80015a0: d107 bne.n 80015b2 <HAL_TIM_PWM_Start+0xd2>
{
/* Enable the main output */
__HAL_TIM_MOE_ENABLE(htim);
80015a2: 687b ldr r3, [r7, #4]
80015a4: 681b ldr r3, [r3, #0]
80015a6: 6c5a ldr r2, [r3, #68] ; 0x44
80015a8: 687b ldr r3, [r7, #4]
80015aa: 681b ldr r3, [r3, #0]
80015ac: f442 4200 orr.w r2, r2, #32768 ; 0x8000
80015b0: 645a str r2, [r3, #68] ; 0x44
}
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
80015b2: 687b ldr r3, [r7, #4]
80015b4: 681b ldr r3, [r3, #0]
80015b6: 4a18 ldr r2, [pc, #96] ; (8001618 <HAL_TIM_PWM_Start+0x138>)
80015b8: 4293 cmp r3, r2
80015ba: d00e beq.n 80015da <HAL_TIM_PWM_Start+0xfa>
80015bc: 687b ldr r3, [r7, #4]
80015be: 681b ldr r3, [r3, #0]
80015c0: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
80015c4: d009 beq.n 80015da <HAL_TIM_PWM_Start+0xfa>
80015c6: 687b ldr r3, [r7, #4]
80015c8: 681b ldr r3, [r3, #0]
80015ca: 4a14 ldr r2, [pc, #80] ; (800161c <HAL_TIM_PWM_Start+0x13c>)
80015cc: 4293 cmp r3, r2
80015ce: d004 beq.n 80015da <HAL_TIM_PWM_Start+0xfa>
80015d0: 687b ldr r3, [r7, #4]
80015d2: 681b ldr r3, [r3, #0]
80015d4: 4a12 ldr r2, [pc, #72] ; (8001620 <HAL_TIM_PWM_Start+0x140>)
80015d6: 4293 cmp r3, r2
80015d8: d111 bne.n 80015fe <HAL_TIM_PWM_Start+0x11e>
{
tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
80015da: 687b ldr r3, [r7, #4]
80015dc: 681b ldr r3, [r3, #0]
80015de: 689b ldr r3, [r3, #8]
80015e0: f003 0307 and.w r3, r3, #7
80015e4: 60fb str r3, [r7, #12]
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
80015e6: 68fb ldr r3, [r7, #12]
80015e8: 2b06 cmp r3, #6
80015ea: d010 beq.n 800160e <HAL_TIM_PWM_Start+0x12e>
{
__HAL_TIM_ENABLE(htim);
80015ec: 687b ldr r3, [r7, #4]
80015ee: 681b ldr r3, [r3, #0]
80015f0: 681a ldr r2, [r3, #0]
80015f2: 687b ldr r3, [r7, #4]
80015f4: 681b ldr r3, [r3, #0]
80015f6: f042 0201 orr.w r2, r2, #1
80015fa: 601a str r2, [r3, #0]
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
80015fc: e007 b.n 800160e <HAL_TIM_PWM_Start+0x12e>
}
}
else
{
__HAL_TIM_ENABLE(htim);
80015fe: 687b ldr r3, [r7, #4]
8001600: 681b ldr r3, [r3, #0]
8001602: 681a ldr r2, [r3, #0]
8001604: 687b ldr r3, [r7, #4]
8001606: 681b ldr r3, [r3, #0]
8001608: f042 0201 orr.w r2, r2, #1
800160c: 601a str r2, [r3, #0]
}
/* Return function status */
return HAL_OK;
800160e: 2300 movs r3, #0
}
8001610: 4618 mov r0, r3
8001612: 3710 adds r7, #16
8001614: 46bd mov sp, r7
8001616: bd80 pop {r7, pc}
8001618: 40012c00 .word 0x40012c00
800161c: 40000400 .word 0x40000400
8001620: 40000800 .word 0x40000800
08001624 <HAL_TIM_PWM_ConfigChannel>:
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
TIM_OC_InitTypeDef *sConfig,
uint32_t Channel)
{
8001624: b580 push {r7, lr}
8001626: b084 sub sp, #16
8001628: af00 add r7, sp, #0
800162a: 60f8 str r0, [r7, #12]
800162c: 60b9 str r1, [r7, #8]
800162e: 607a str r2, [r7, #4]
assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
/* Process Locked */
__HAL_LOCK(htim);
8001630: 68fb ldr r3, [r7, #12]
8001632: f893 303c ldrb.w r3, [r3, #60] ; 0x3c
8001636: 2b01 cmp r3, #1
8001638: d101 bne.n 800163e <HAL_TIM_PWM_ConfigChannel+0x1a>
800163a: 2302 movs r3, #2
800163c: e0ac b.n 8001798 <HAL_TIM_PWM_ConfigChannel+0x174>
800163e: 68fb ldr r3, [r7, #12]
8001640: 2201 movs r2, #1
8001642: f883 203c strb.w r2, [r3, #60] ; 0x3c
switch (Channel)
8001646: 687b ldr r3, [r7, #4]
8001648: 2b0c cmp r3, #12
800164a: f200 809f bhi.w 800178c <HAL_TIM_PWM_ConfigChannel+0x168>
800164e: a201 add r2, pc, #4 ; (adr r2, 8001654 <HAL_TIM_PWM_ConfigChannel+0x30>)
8001650: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8001654: 08001689 .word 0x08001689
8001658: 0800178d .word 0x0800178d
800165c: 0800178d .word 0x0800178d
8001660: 0800178d .word 0x0800178d
8001664: 080016c9 .word 0x080016c9
8001668: 0800178d .word 0x0800178d
800166c: 0800178d .word 0x0800178d
8001670: 0800178d .word 0x0800178d
8001674: 0800170b .word 0x0800170b
8001678: 0800178d .word 0x0800178d
800167c: 0800178d .word 0x0800178d
8001680: 0800178d .word 0x0800178d
8001684: 0800174b .word 0x0800174b
{
/* Check the parameters */
assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
/* Configure the Channel 1 in PWM mode */
TIM_OC1_SetConfig(htim->Instance, sConfig);
8001688: 68fb ldr r3, [r7, #12]
800168a: 681b ldr r3, [r3, #0]
800168c: 68b9 ldr r1, [r7, #8]
800168e: 4618 mov r0, r3
8001690: f000 f9ac bl 80019ec <TIM_OC1_SetConfig>
/* Set the Preload enable bit for channel1 */
htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
8001694: 68fb ldr r3, [r7, #12]
8001696: 681b ldr r3, [r3, #0]
8001698: 699a ldr r2, [r3, #24]
800169a: 68fb ldr r3, [r7, #12]
800169c: 681b ldr r3, [r3, #0]
800169e: f042 0208 orr.w r2, r2, #8
80016a2: 619a str r2, [r3, #24]
/* Configure the Output Fast mode */
htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
80016a4: 68fb ldr r3, [r7, #12]
80016a6: 681b ldr r3, [r3, #0]
80016a8: 699a ldr r2, [r3, #24]
80016aa: 68fb ldr r3, [r7, #12]
80016ac: 681b ldr r3, [r3, #0]
80016ae: f022 0204 bic.w r2, r2, #4
80016b2: 619a str r2, [r3, #24]
htim->Instance->CCMR1 |= sConfig->OCFastMode;
80016b4: 68fb ldr r3, [r7, #12]
80016b6: 681b ldr r3, [r3, #0]
80016b8: 6999 ldr r1, [r3, #24]
80016ba: 68bb ldr r3, [r7, #8]
80016bc: 691a ldr r2, [r3, #16]
80016be: 68fb ldr r3, [r7, #12]
80016c0: 681b ldr r3, [r3, #0]
80016c2: 430a orrs r2, r1
80016c4: 619a str r2, [r3, #24]
break;
80016c6: e062 b.n 800178e <HAL_TIM_PWM_ConfigChannel+0x16a>
{
/* Check the parameters */
assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
/* Configure the Channel 2 in PWM mode */
TIM_OC2_SetConfig(htim->Instance, sConfig);
80016c8: 68fb ldr r3, [r7, #12]
80016ca: 681b ldr r3, [r3, #0]
80016cc: 68b9 ldr r1, [r7, #8]
80016ce: 4618 mov r0, r3
80016d0: f000 f9f2 bl 8001ab8 <TIM_OC2_SetConfig>
/* Set the Preload enable bit for channel2 */
htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
80016d4: 68fb ldr r3, [r7, #12]
80016d6: 681b ldr r3, [r3, #0]
80016d8: 699a ldr r2, [r3, #24]
80016da: 68fb ldr r3, [r7, #12]
80016dc: 681b ldr r3, [r3, #0]
80016de: f442 6200 orr.w r2, r2, #2048 ; 0x800
80016e2: 619a str r2, [r3, #24]
/* Configure the Output Fast mode */
htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
80016e4: 68fb ldr r3, [r7, #12]
80016e6: 681b ldr r3, [r3, #0]
80016e8: 699a ldr r2, [r3, #24]
80016ea: 68fb ldr r3, [r7, #12]
80016ec: 681b ldr r3, [r3, #0]
80016ee: f422 6280 bic.w r2, r2, #1024 ; 0x400
80016f2: 619a str r2, [r3, #24]
htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
80016f4: 68fb ldr r3, [r7, #12]
80016f6: 681b ldr r3, [r3, #0]
80016f8: 6999 ldr r1, [r3, #24]
80016fa: 68bb ldr r3, [r7, #8]
80016fc: 691b ldr r3, [r3, #16]
80016fe: 021a lsls r2, r3, #8
8001700: 68fb ldr r3, [r7, #12]
8001702: 681b ldr r3, [r3, #0]
8001704: 430a orrs r2, r1
8001706: 619a str r2, [r3, #24]
break;
8001708: e041 b.n 800178e <HAL_TIM_PWM_ConfigChannel+0x16a>
{
/* Check the parameters */
assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
/* Configure the Channel 3 in PWM mode */
TIM_OC3_SetConfig(htim->Instance, sConfig);
800170a: 68fb ldr r3, [r7, #12]
800170c: 681b ldr r3, [r3, #0]
800170e: 68b9 ldr r1, [r7, #8]
8001710: 4618 mov r0, r3
8001712: f000 fa3b bl 8001b8c <TIM_OC3_SetConfig>
/* Set the Preload enable bit for channel3 */
htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
8001716: 68fb ldr r3, [r7, #12]
8001718: 681b ldr r3, [r3, #0]
800171a: 69da ldr r2, [r3, #28]
800171c: 68fb ldr r3, [r7, #12]
800171e: 681b ldr r3, [r3, #0]
8001720: f042 0208 orr.w r2, r2, #8
8001724: 61da str r2, [r3, #28]
/* Configure the Output Fast mode */
htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
8001726: 68fb ldr r3, [r7, #12]
8001728: 681b ldr r3, [r3, #0]
800172a: 69da ldr r2, [r3, #28]
800172c: 68fb ldr r3, [r7, #12]
800172e: 681b ldr r3, [r3, #0]
8001730: f022 0204 bic.w r2, r2, #4
8001734: 61da str r2, [r3, #28]
htim->Instance->CCMR2 |= sConfig->OCFastMode;
8001736: 68fb ldr r3, [r7, #12]
8001738: 681b ldr r3, [r3, #0]
800173a: 69d9 ldr r1, [r3, #28]
800173c: 68bb ldr r3, [r7, #8]
800173e: 691a ldr r2, [r3, #16]
8001740: 68fb ldr r3, [r7, #12]
8001742: 681b ldr r3, [r3, #0]
8001744: 430a orrs r2, r1
8001746: 61da str r2, [r3, #28]
break;
8001748: e021 b.n 800178e <HAL_TIM_PWM_ConfigChannel+0x16a>
{
/* Check the parameters */
assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
/* Configure the Channel 4 in PWM mode */
TIM_OC4_SetConfig(htim->Instance, sConfig);
800174a: 68fb ldr r3, [r7, #12]
800174c: 681b ldr r3, [r3, #0]
800174e: 68b9 ldr r1, [r7, #8]
8001750: 4618 mov r0, r3
8001752: f000 fa85 bl 8001c60 <TIM_OC4_SetConfig>
/* Set the Preload enable bit for channel4 */
htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
8001756: 68fb ldr r3, [r7, #12]
8001758: 681b ldr r3, [r3, #0]
800175a: 69da ldr r2, [r3, #28]
800175c: 68fb ldr r3, [r7, #12]
800175e: 681b ldr r3, [r3, #0]
8001760: f442 6200 orr.w r2, r2, #2048 ; 0x800
8001764: 61da str r2, [r3, #28]
/* Configure the Output Fast mode */
htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
8001766: 68fb ldr r3, [r7, #12]
8001768: 681b ldr r3, [r3, #0]
800176a: 69da ldr r2, [r3, #28]
800176c: 68fb ldr r3, [r7, #12]
800176e: 681b ldr r3, [r3, #0]
8001770: f422 6280 bic.w r2, r2, #1024 ; 0x400
8001774: 61da str r2, [r3, #28]
htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
8001776: 68fb ldr r3, [r7, #12]
8001778: 681b ldr r3, [r3, #0]
800177a: 69d9 ldr r1, [r3, #28]
800177c: 68bb ldr r3, [r7, #8]
800177e: 691b ldr r3, [r3, #16]
8001780: 021a lsls r2, r3, #8
8001782: 68fb ldr r3, [r7, #12]
8001784: 681b ldr r3, [r3, #0]
8001786: 430a orrs r2, r1
8001788: 61da str r2, [r3, #28]
break;
800178a: e000 b.n 800178e <HAL_TIM_PWM_ConfigChannel+0x16a>
}
default:
break;
800178c: bf00 nop
}
__HAL_UNLOCK(htim);
800178e: 68fb ldr r3, [r7, #12]
8001790: 2200 movs r2, #0
8001792: f883 203c strb.w r2, [r3, #60] ; 0x3c
return HAL_OK;
8001796: 2300 movs r3, #0
}
8001798: 4618 mov r0, r3
800179a: 3710 adds r7, #16
800179c: 46bd mov sp, r7
800179e: bd80 pop {r7, pc}
080017a0 <HAL_TIM_ConfigClockSource>:
* @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that
* contains the clock source information for the TIM peripheral.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig)
{
80017a0: b580 push {r7, lr}
80017a2: b084 sub sp, #16
80017a4: af00 add r7, sp, #0
80017a6: 6078 str r0, [r7, #4]
80017a8: 6039 str r1, [r7, #0]
uint32_t tmpsmcr;
/* Process Locked */
__HAL_LOCK(htim);
80017aa: 687b ldr r3, [r7, #4]
80017ac: f893 303c ldrb.w r3, [r3, #60] ; 0x3c
80017b0: 2b01 cmp r3, #1
80017b2: d101 bne.n 80017b8 <HAL_TIM_ConfigClockSource+0x18>
80017b4: 2302 movs r3, #2
80017b6: e0b3 b.n 8001920 <HAL_TIM_ConfigClockSource+0x180>
80017b8: 687b ldr r3, [r7, #4]
80017ba: 2201 movs r2, #1
80017bc: f883 203c strb.w r2, [r3, #60] ; 0x3c
htim->State = HAL_TIM_STATE_BUSY;
80017c0: 687b ldr r3, [r7, #4]
80017c2: 2202 movs r2, #2
80017c4: f883 203d strb.w r2, [r3, #61] ; 0x3d
/* Check the parameters */
assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
/* Reset the SMS, TS, ECE, ETPS and ETRF bits */
tmpsmcr = htim->Instance->SMCR;
80017c8: 687b ldr r3, [r7, #4]
80017ca: 681b ldr r3, [r3, #0]
80017cc: 689b ldr r3, [r3, #8]
80017ce: 60fb str r3, [r7, #12]
tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
80017d0: 68fb ldr r3, [r7, #12]
80017d2: f023 0377 bic.w r3, r3, #119 ; 0x77
80017d6: 60fb str r3, [r7, #12]
tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
80017d8: 68fb ldr r3, [r7, #12]
80017da: f423 437f bic.w r3, r3, #65280 ; 0xff00
80017de: 60fb str r3, [r7, #12]
htim->Instance->SMCR = tmpsmcr;
80017e0: 687b ldr r3, [r7, #4]
80017e2: 681b ldr r3, [r3, #0]
80017e4: 68fa ldr r2, [r7, #12]
80017e6: 609a str r2, [r3, #8]
switch (sClockSourceConfig->ClockSource)
80017e8: 683b ldr r3, [r7, #0]
80017ea: 681b ldr r3, [r3, #0]
80017ec: f5b3 5f00 cmp.w r3, #8192 ; 0x2000
80017f0: d03e beq.n 8001870 <HAL_TIM_ConfigClockSource+0xd0>
80017f2: f5b3 5f00 cmp.w r3, #8192 ; 0x2000
80017f6: f200 8087 bhi.w 8001908 <HAL_TIM_ConfigClockSource+0x168>
80017fa: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
80017fe: f000 8085 beq.w 800190c <HAL_TIM_ConfigClockSource+0x16c>
8001802: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
8001806: d87f bhi.n 8001908 <HAL_TIM_ConfigClockSource+0x168>
8001808: 2b70 cmp r3, #112 ; 0x70
800180a: d01a beq.n 8001842 <HAL_TIM_ConfigClockSource+0xa2>
800180c: 2b70 cmp r3, #112 ; 0x70
800180e: d87b bhi.n 8001908 <HAL_TIM_ConfigClockSource+0x168>
8001810: 2b60 cmp r3, #96 ; 0x60
8001812: d050 beq.n 80018b6 <HAL_TIM_ConfigClockSource+0x116>
8001814: 2b60 cmp r3, #96 ; 0x60
8001816: d877 bhi.n 8001908 <HAL_TIM_ConfigClockSource+0x168>
8001818: 2b50 cmp r3, #80 ; 0x50
800181a: d03c beq.n 8001896 <HAL_TIM_ConfigClockSource+0xf6>
800181c: 2b50 cmp r3, #80 ; 0x50
800181e: d873 bhi.n 8001908 <HAL_TIM_ConfigClockSource+0x168>
8001820: 2b40 cmp r3, #64 ; 0x40
8001822: d058 beq.n 80018d6 <HAL_TIM_ConfigClockSource+0x136>
8001824: 2b40 cmp r3, #64 ; 0x40
8001826: d86f bhi.n 8001908 <HAL_TIM_ConfigClockSource+0x168>
8001828: 2b30 cmp r3, #48 ; 0x30
800182a: d064 beq.n 80018f6 <HAL_TIM_ConfigClockSource+0x156>
800182c: 2b30 cmp r3, #48 ; 0x30
800182e: d86b bhi.n 8001908 <HAL_TIM_ConfigClockSource+0x168>
8001830: 2b20 cmp r3, #32
8001832: d060 beq.n 80018f6 <HAL_TIM_ConfigClockSource+0x156>
8001834: 2b20 cmp r3, #32
8001836: d867 bhi.n 8001908 <HAL_TIM_ConfigClockSource+0x168>
8001838: 2b00 cmp r3, #0
800183a: d05c beq.n 80018f6 <HAL_TIM_ConfigClockSource+0x156>
800183c: 2b10 cmp r3, #16
800183e: d05a beq.n 80018f6 <HAL_TIM_ConfigClockSource+0x156>
TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
break;
}
default:
break;
8001840: e062 b.n 8001908 <HAL_TIM_ConfigClockSource+0x168>
TIM_ETR_SetConfig(htim->Instance,
8001842: 687b ldr r3, [r7, #4]
8001844: 6818 ldr r0, [r3, #0]
8001846: 683b ldr r3, [r7, #0]
8001848: 6899 ldr r1, [r3, #8]
800184a: 683b ldr r3, [r7, #0]
800184c: 685a ldr r2, [r3, #4]
800184e: 683b ldr r3, [r7, #0]
8001850: 68db ldr r3, [r3, #12]
8001852: f000 faca bl 8001dea <TIM_ETR_SetConfig>
tmpsmcr = htim->Instance->SMCR;
8001856: 687b ldr r3, [r7, #4]
8001858: 681b ldr r3, [r3, #0]
800185a: 689b ldr r3, [r3, #8]
800185c: 60fb str r3, [r7, #12]
tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
800185e: 68fb ldr r3, [r7, #12]
8001860: f043 0377 orr.w r3, r3, #119 ; 0x77
8001864: 60fb str r3, [r7, #12]
htim->Instance->SMCR = tmpsmcr;
8001866: 687b ldr r3, [r7, #4]
8001868: 681b ldr r3, [r3, #0]
800186a: 68fa ldr r2, [r7, #12]
800186c: 609a str r2, [r3, #8]
break;
800186e: e04e b.n 800190e <HAL_TIM_ConfigClockSource+0x16e>
TIM_ETR_SetConfig(htim->Instance,
8001870: 687b ldr r3, [r7, #4]
8001872: 6818 ldr r0, [r3, #0]
8001874: 683b ldr r3, [r7, #0]
8001876: 6899 ldr r1, [r3, #8]
8001878: 683b ldr r3, [r7, #0]
800187a: 685a ldr r2, [r3, #4]
800187c: 683b ldr r3, [r7, #0]
800187e: 68db ldr r3, [r3, #12]
8001880: f000 fab3 bl 8001dea <TIM_ETR_SetConfig>
htim->Instance->SMCR |= TIM_SMCR_ECE;
8001884: 687b ldr r3, [r7, #4]
8001886: 681b ldr r3, [r3, #0]
8001888: 689a ldr r2, [r3, #8]
800188a: 687b ldr r3, [r7, #4]
800188c: 681b ldr r3, [r3, #0]
800188e: f442 4280 orr.w r2, r2, #16384 ; 0x4000
8001892: 609a str r2, [r3, #8]
break;
8001894: e03b b.n 800190e <HAL_TIM_ConfigClockSource+0x16e>
TIM_TI1_ConfigInputStage(htim->Instance,
8001896: 687b ldr r3, [r7, #4]
8001898: 6818 ldr r0, [r3, #0]
800189a: 683b ldr r3, [r7, #0]
800189c: 6859 ldr r1, [r3, #4]
800189e: 683b ldr r3, [r7, #0]
80018a0: 68db ldr r3, [r3, #12]
80018a2: 461a mov r2, r3
80018a4: f000 fa2a bl 8001cfc <TIM_TI1_ConfigInputStage>
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
80018a8: 687b ldr r3, [r7, #4]
80018aa: 681b ldr r3, [r3, #0]
80018ac: 2150 movs r1, #80 ; 0x50
80018ae: 4618 mov r0, r3
80018b0: f000 fa81 bl 8001db6 <TIM_ITRx_SetConfig>
break;
80018b4: e02b b.n 800190e <HAL_TIM_ConfigClockSource+0x16e>
TIM_TI2_ConfigInputStage(htim->Instance,
80018b6: 687b ldr r3, [r7, #4]
80018b8: 6818 ldr r0, [r3, #0]
80018ba: 683b ldr r3, [r7, #0]
80018bc: 6859 ldr r1, [r3, #4]
80018be: 683b ldr r3, [r7, #0]
80018c0: 68db ldr r3, [r3, #12]
80018c2: 461a mov r2, r3
80018c4: f000 fa48 bl 8001d58 <TIM_TI2_ConfigInputStage>
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
80018c8: 687b ldr r3, [r7, #4]
80018ca: 681b ldr r3, [r3, #0]
80018cc: 2160 movs r1, #96 ; 0x60
80018ce: 4618 mov r0, r3
80018d0: f000 fa71 bl 8001db6 <TIM_ITRx_SetConfig>
break;
80018d4: e01b b.n 800190e <HAL_TIM_ConfigClockSource+0x16e>
TIM_TI1_ConfigInputStage(htim->Instance,
80018d6: 687b ldr r3, [r7, #4]
80018d8: 6818 ldr r0, [r3, #0]
80018da: 683b ldr r3, [r7, #0]
80018dc: 6859 ldr r1, [r3, #4]
80018de: 683b ldr r3, [r7, #0]
80018e0: 68db ldr r3, [r3, #12]
80018e2: 461a mov r2, r3
80018e4: f000 fa0a bl 8001cfc <TIM_TI1_ConfigInputStage>
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
80018e8: 687b ldr r3, [r7, #4]
80018ea: 681b ldr r3, [r3, #0]
80018ec: 2140 movs r1, #64 ; 0x40
80018ee: 4618 mov r0, r3
80018f0: f000 fa61 bl 8001db6 <TIM_ITRx_SetConfig>
break;
80018f4: e00b b.n 800190e <HAL_TIM_ConfigClockSource+0x16e>
TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
80018f6: 687b ldr r3, [r7, #4]
80018f8: 681a ldr r2, [r3, #0]
80018fa: 683b ldr r3, [r7, #0]
80018fc: 681b ldr r3, [r3, #0]
80018fe: 4619 mov r1, r3
8001900: 4610 mov r0, r2
8001902: f000 fa58 bl 8001db6 <TIM_ITRx_SetConfig>
break;
8001906: e002 b.n 800190e <HAL_TIM_ConfigClockSource+0x16e>
break;
8001908: bf00 nop
800190a: e000 b.n 800190e <HAL_TIM_ConfigClockSource+0x16e>
break;
800190c: bf00 nop
}
htim->State = HAL_TIM_STATE_READY;
800190e: 687b ldr r3, [r7, #4]
8001910: 2201 movs r2, #1
8001912: f883 203d strb.w r2, [r3, #61] ; 0x3d
__HAL_UNLOCK(htim);
8001916: 687b ldr r3, [r7, #4]
8001918: 2200 movs r2, #0
800191a: f883 203c strb.w r2, [r3, #60] ; 0x3c
return HAL_OK;
800191e: 2300 movs r3, #0
}
8001920: 4618 mov r0, r3
8001922: 3710 adds r7, #16
8001924: 46bd mov sp, r7
8001926: bd80 pop {r7, pc}
08001928 <TIM_Base_SetConfig>:
* @param TIMx TIM peripheral
* @param Structure TIM Base configuration structure
* @retval None
*/
void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
{
8001928: b480 push {r7}
800192a: b085 sub sp, #20
800192c: af00 add r7, sp, #0
800192e: 6078 str r0, [r7, #4]
8001930: 6039 str r1, [r7, #0]
uint32_t tmpcr1;
tmpcr1 = TIMx->CR1;
8001932: 687b ldr r3, [r7, #4]
8001934: 681b ldr r3, [r3, #0]
8001936: 60fb str r3, [r7, #12]
/* Set TIM Time Base Unit parameters ---------------------------------------*/
if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
8001938: 687b ldr r3, [r7, #4]
800193a: 4a29 ldr r2, [pc, #164] ; (80019e0 <TIM_Base_SetConfig+0xb8>)
800193c: 4293 cmp r3, r2
800193e: d00b beq.n 8001958 <TIM_Base_SetConfig+0x30>
8001940: 687b ldr r3, [r7, #4]
8001942: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
8001946: d007 beq.n 8001958 <TIM_Base_SetConfig+0x30>
8001948: 687b ldr r3, [r7, #4]
800194a: 4a26 ldr r2, [pc, #152] ; (80019e4 <TIM_Base_SetConfig+0xbc>)
800194c: 4293 cmp r3, r2
800194e: d003 beq.n 8001958 <TIM_Base_SetConfig+0x30>
8001950: 687b ldr r3, [r7, #4]
8001952: 4a25 ldr r2, [pc, #148] ; (80019e8 <TIM_Base_SetConfig+0xc0>)
8001954: 4293 cmp r3, r2
8001956: d108 bne.n 800196a <TIM_Base_SetConfig+0x42>
{
/* Select the Counter Mode */
tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
8001958: 68fb ldr r3, [r7, #12]
800195a: f023 0370 bic.w r3, r3, #112 ; 0x70
800195e: 60fb str r3, [r7, #12]
tmpcr1 |= Structure->CounterMode;
8001960: 683b ldr r3, [r7, #0]
8001962: 685b ldr r3, [r3, #4]
8001964: 68fa ldr r2, [r7, #12]
8001966: 4313 orrs r3, r2
8001968: 60fb str r3, [r7, #12]
}
if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
800196a: 687b ldr r3, [r7, #4]
800196c: 4a1c ldr r2, [pc, #112] ; (80019e0 <TIM_Base_SetConfig+0xb8>)
800196e: 4293 cmp r3, r2
8001970: d00b beq.n 800198a <TIM_Base_SetConfig+0x62>
8001972: 687b ldr r3, [r7, #4]
8001974: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
8001978: d007 beq.n 800198a <TIM_Base_SetConfig+0x62>
800197a: 687b ldr r3, [r7, #4]
800197c: 4a19 ldr r2, [pc, #100] ; (80019e4 <TIM_Base_SetConfig+0xbc>)
800197e: 4293 cmp r3, r2
8001980: d003 beq.n 800198a <TIM_Base_SetConfig+0x62>
8001982: 687b ldr r3, [r7, #4]
8001984: 4a18 ldr r2, [pc, #96] ; (80019e8 <TIM_Base_SetConfig+0xc0>)
8001986: 4293 cmp r3, r2
8001988: d108 bne.n 800199c <TIM_Base_SetConfig+0x74>
{
/* Set the clock division */
tmpcr1 &= ~TIM_CR1_CKD;
800198a: 68fb ldr r3, [r7, #12]
800198c: f423 7340 bic.w r3, r3, #768 ; 0x300
8001990: 60fb str r3, [r7, #12]
tmpcr1 |= (uint32_t)Structure->ClockDivision;
8001992: 683b ldr r3, [r7, #0]
8001994: 68db ldr r3, [r3, #12]
8001996: 68fa ldr r2, [r7, #12]
8001998: 4313 orrs r3, r2
800199a: 60fb str r3, [r7, #12]
}
/* Set the auto-reload preload */
MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
800199c: 68fb ldr r3, [r7, #12]
800199e: f023 0280 bic.w r2, r3, #128 ; 0x80
80019a2: 683b ldr r3, [r7, #0]
80019a4: 695b ldr r3, [r3, #20]
80019a6: 4313 orrs r3, r2
80019a8: 60fb str r3, [r7, #12]
TIMx->CR1 = tmpcr1;
80019aa: 687b ldr r3, [r7, #4]
80019ac: 68fa ldr r2, [r7, #12]
80019ae: 601a str r2, [r3, #0]
/* Set the Autoreload value */
TIMx->ARR = (uint32_t)Structure->Period ;
80019b0: 683b ldr r3, [r7, #0]
80019b2: 689a ldr r2, [r3, #8]
80019b4: 687b ldr r3, [r7, #4]
80019b6: 62da str r2, [r3, #44] ; 0x2c
/* Set the Prescaler value */
TIMx->PSC = Structure->Prescaler;
80019b8: 683b ldr r3, [r7, #0]
80019ba: 681a ldr r2, [r3, #0]
80019bc: 687b ldr r3, [r7, #4]
80019be: 629a str r2, [r3, #40] ; 0x28
if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
80019c0: 687b ldr r3, [r7, #4]
80019c2: 4a07 ldr r2, [pc, #28] ; (80019e0 <TIM_Base_SetConfig+0xb8>)
80019c4: 4293 cmp r3, r2
80019c6: d103 bne.n 80019d0 <TIM_Base_SetConfig+0xa8>
{
/* Set the Repetition Counter value */
TIMx->RCR = Structure->RepetitionCounter;
80019c8: 683b ldr r3, [r7, #0]
80019ca: 691a ldr r2, [r3, #16]
80019cc: 687b ldr r3, [r7, #4]
80019ce: 631a str r2, [r3, #48] ; 0x30
}
/* Generate an update event to reload the Prescaler
and the repetition counter (only for advanced timer) value immediately */
TIMx->EGR = TIM_EGR_UG;
80019d0: 687b ldr r3, [r7, #4]
80019d2: 2201 movs r2, #1
80019d4: 615a str r2, [r3, #20]
}
80019d6: bf00 nop
80019d8: 3714 adds r7, #20
80019da: 46bd mov sp, r7
80019dc: bc80 pop {r7}
80019de: 4770 bx lr
80019e0: 40012c00 .word 0x40012c00
80019e4: 40000400 .word 0x40000400
80019e8: 40000800 .word 0x40000800
080019ec <TIM_OC1_SetConfig>:
* @param TIMx to select the TIM peripheral
* @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
{
80019ec: b480 push {r7}
80019ee: b087 sub sp, #28
80019f0: af00 add r7, sp, #0
80019f2: 6078 str r0, [r7, #4]
80019f4: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Disable the Channel 1: Reset the CC1E Bit */
TIMx->CCER &= ~TIM_CCER_CC1E;
80019f6: 687b ldr r3, [r7, #4]
80019f8: 6a1b ldr r3, [r3, #32]
80019fa: f023 0201 bic.w r2, r3, #1
80019fe: 687b ldr r3, [r7, #4]
8001a00: 621a str r2, [r3, #32]
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
8001a02: 687b ldr r3, [r7, #4]
8001a04: 6a1b ldr r3, [r3, #32]
8001a06: 617b str r3, [r7, #20]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
8001a08: 687b ldr r3, [r7, #4]
8001a0a: 685b ldr r3, [r3, #4]
8001a0c: 613b str r3, [r7, #16]
/* Get the TIMx CCMR1 register value */
tmpccmrx = TIMx->CCMR1;
8001a0e: 687b ldr r3, [r7, #4]
8001a10: 699b ldr r3, [r3, #24]
8001a12: 60fb str r3, [r7, #12]
/* Reset the Output Compare Mode Bits */
tmpccmrx &= ~TIM_CCMR1_OC1M;
8001a14: 68fb ldr r3, [r7, #12]
8001a16: f023 0370 bic.w r3, r3, #112 ; 0x70
8001a1a: 60fb str r3, [r7, #12]
tmpccmrx &= ~TIM_CCMR1_CC1S;
8001a1c: 68fb ldr r3, [r7, #12]
8001a1e: f023 0303 bic.w r3, r3, #3
8001a22: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= OC_Config->OCMode;
8001a24: 683b ldr r3, [r7, #0]
8001a26: 681b ldr r3, [r3, #0]
8001a28: 68fa ldr r2, [r7, #12]
8001a2a: 4313 orrs r3, r2
8001a2c: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC1P;
8001a2e: 697b ldr r3, [r7, #20]
8001a30: f023 0302 bic.w r3, r3, #2
8001a34: 617b str r3, [r7, #20]
/* Set the Output Compare Polarity */
tmpccer |= OC_Config->OCPolarity;
8001a36: 683b ldr r3, [r7, #0]
8001a38: 689b ldr r3, [r3, #8]
8001a3a: 697a ldr r2, [r7, #20]
8001a3c: 4313 orrs r3, r2
8001a3e: 617b str r3, [r7, #20]
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
8001a40: 687b ldr r3, [r7, #4]
8001a42: 4a1c ldr r2, [pc, #112] ; (8001ab4 <TIM_OC1_SetConfig+0xc8>)
8001a44: 4293 cmp r3, r2
8001a46: d10c bne.n 8001a62 <TIM_OC1_SetConfig+0x76>
{
/* Check parameters */
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
/* Reset the Output N Polarity level */
tmpccer &= ~TIM_CCER_CC1NP;
8001a48: 697b ldr r3, [r7, #20]
8001a4a: f023 0308 bic.w r3, r3, #8
8001a4e: 617b str r3, [r7, #20]
/* Set the Output N Polarity */
tmpccer |= OC_Config->OCNPolarity;
8001a50: 683b ldr r3, [r7, #0]
8001a52: 68db ldr r3, [r3, #12]
8001a54: 697a ldr r2, [r7, #20]
8001a56: 4313 orrs r3, r2
8001a58: 617b str r3, [r7, #20]
/* Reset the Output N State */
tmpccer &= ~TIM_CCER_CC1NE;
8001a5a: 697b ldr r3, [r7, #20]
8001a5c: f023 0304 bic.w r3, r3, #4
8001a60: 617b str r3, [r7, #20]
}
if (IS_TIM_BREAK_INSTANCE(TIMx))
8001a62: 687b ldr r3, [r7, #4]
8001a64: 4a13 ldr r2, [pc, #76] ; (8001ab4 <TIM_OC1_SetConfig+0xc8>)
8001a66: 4293 cmp r3, r2
8001a68: d111 bne.n 8001a8e <TIM_OC1_SetConfig+0xa2>
/* Check parameters */
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
/* Reset the Output Compare and Output Compare N IDLE State */
tmpcr2 &= ~TIM_CR2_OIS1;
8001a6a: 693b ldr r3, [r7, #16]
8001a6c: f423 7380 bic.w r3, r3, #256 ; 0x100
8001a70: 613b str r3, [r7, #16]
tmpcr2 &= ~TIM_CR2_OIS1N;
8001a72: 693b ldr r3, [r7, #16]
8001a74: f423 7300 bic.w r3, r3, #512 ; 0x200
8001a78: 613b str r3, [r7, #16]
/* Set the Output Idle state */
tmpcr2 |= OC_Config->OCIdleState;
8001a7a: 683b ldr r3, [r7, #0]
8001a7c: 695b ldr r3, [r3, #20]
8001a7e: 693a ldr r2, [r7, #16]
8001a80: 4313 orrs r3, r2
8001a82: 613b str r3, [r7, #16]
/* Set the Output N Idle state */
tmpcr2 |= OC_Config->OCNIdleState;
8001a84: 683b ldr r3, [r7, #0]
8001a86: 699b ldr r3, [r3, #24]
8001a88: 693a ldr r2, [r7, #16]
8001a8a: 4313 orrs r3, r2
8001a8c: 613b str r3, [r7, #16]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
8001a8e: 687b ldr r3, [r7, #4]
8001a90: 693a ldr r2, [r7, #16]
8001a92: 605a str r2, [r3, #4]
/* Write to TIMx CCMR1 */
TIMx->CCMR1 = tmpccmrx;
8001a94: 687b ldr r3, [r7, #4]
8001a96: 68fa ldr r2, [r7, #12]
8001a98: 619a str r2, [r3, #24]
/* Set the Capture Compare Register value */
TIMx->CCR1 = OC_Config->Pulse;
8001a9a: 683b ldr r3, [r7, #0]
8001a9c: 685a ldr r2, [r3, #4]
8001a9e: 687b ldr r3, [r7, #4]
8001aa0: 635a str r2, [r3, #52] ; 0x34
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
8001aa2: 687b ldr r3, [r7, #4]
8001aa4: 697a ldr r2, [r7, #20]
8001aa6: 621a str r2, [r3, #32]
}
8001aa8: bf00 nop
8001aaa: 371c adds r7, #28
8001aac: 46bd mov sp, r7
8001aae: bc80 pop {r7}
8001ab0: 4770 bx lr
8001ab2: bf00 nop
8001ab4: 40012c00 .word 0x40012c00
08001ab8 <TIM_OC2_SetConfig>:
* @param TIMx to select the TIM peripheral
* @param OC_Config The output configuration structure
* @retval None
*/
void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
{
8001ab8: b480 push {r7}
8001aba: b087 sub sp, #28
8001abc: af00 add r7, sp, #0
8001abe: 6078 str r0, [r7, #4]
8001ac0: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Disable the Channel 2: Reset the CC2E Bit */
TIMx->CCER &= ~TIM_CCER_CC2E;
8001ac2: 687b ldr r3, [r7, #4]
8001ac4: 6a1b ldr r3, [r3, #32]
8001ac6: f023 0210 bic.w r2, r3, #16
8001aca: 687b ldr r3, [r7, #4]
8001acc: 621a str r2, [r3, #32]
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
8001ace: 687b ldr r3, [r7, #4]
8001ad0: 6a1b ldr r3, [r3, #32]
8001ad2: 617b str r3, [r7, #20]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
8001ad4: 687b ldr r3, [r7, #4]
8001ad6: 685b ldr r3, [r3, #4]
8001ad8: 613b str r3, [r7, #16]
/* Get the TIMx CCMR1 register value */
tmpccmrx = TIMx->CCMR1;
8001ada: 687b ldr r3, [r7, #4]
8001adc: 699b ldr r3, [r3, #24]
8001ade: 60fb str r3, [r7, #12]
/* Reset the Output Compare mode and Capture/Compare selection Bits */
tmpccmrx &= ~TIM_CCMR1_OC2M;
8001ae0: 68fb ldr r3, [r7, #12]
8001ae2: f423 43e0 bic.w r3, r3, #28672 ; 0x7000
8001ae6: 60fb str r3, [r7, #12]
tmpccmrx &= ~TIM_CCMR1_CC2S;
8001ae8: 68fb ldr r3, [r7, #12]
8001aea: f423 7340 bic.w r3, r3, #768 ; 0x300
8001aee: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= (OC_Config->OCMode << 8U);
8001af0: 683b ldr r3, [r7, #0]
8001af2: 681b ldr r3, [r3, #0]
8001af4: 021b lsls r3, r3, #8
8001af6: 68fa ldr r2, [r7, #12]
8001af8: 4313 orrs r3, r2
8001afa: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC2P;
8001afc: 697b ldr r3, [r7, #20]
8001afe: f023 0320 bic.w r3, r3, #32
8001b02: 617b str r3, [r7, #20]
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 4U);
8001b04: 683b ldr r3, [r7, #0]
8001b06: 689b ldr r3, [r3, #8]
8001b08: 011b lsls r3, r3, #4
8001b0a: 697a ldr r2, [r7, #20]
8001b0c: 4313 orrs r3, r2
8001b0e: 617b str r3, [r7, #20]
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
8001b10: 687b ldr r3, [r7, #4]
8001b12: 4a1d ldr r2, [pc, #116] ; (8001b88 <TIM_OC2_SetConfig+0xd0>)
8001b14: 4293 cmp r3, r2
8001b16: d10d bne.n 8001b34 <TIM_OC2_SetConfig+0x7c>
{
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
/* Reset the Output N Polarity level */
tmpccer &= ~TIM_CCER_CC2NP;
8001b18: 697b ldr r3, [r7, #20]
8001b1a: f023 0380 bic.w r3, r3, #128 ; 0x80
8001b1e: 617b str r3, [r7, #20]
/* Set the Output N Polarity */
tmpccer |= (OC_Config->OCNPolarity << 4U);
8001b20: 683b ldr r3, [r7, #0]
8001b22: 68db ldr r3, [r3, #12]
8001b24: 011b lsls r3, r3, #4
8001b26: 697a ldr r2, [r7, #20]
8001b28: 4313 orrs r3, r2
8001b2a: 617b str r3, [r7, #20]
/* Reset the Output N State */
tmpccer &= ~TIM_CCER_CC2NE;
8001b2c: 697b ldr r3, [r7, #20]
8001b2e: f023 0340 bic.w r3, r3, #64 ; 0x40
8001b32: 617b str r3, [r7, #20]
}
if (IS_TIM_BREAK_INSTANCE(TIMx))
8001b34: 687b ldr r3, [r7, #4]
8001b36: 4a14 ldr r2, [pc, #80] ; (8001b88 <TIM_OC2_SetConfig+0xd0>)
8001b38: 4293 cmp r3, r2
8001b3a: d113 bne.n 8001b64 <TIM_OC2_SetConfig+0xac>
/* Check parameters */
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
/* Reset the Output Compare and Output Compare N IDLE State */
tmpcr2 &= ~TIM_CR2_OIS2;
8001b3c: 693b ldr r3, [r7, #16]
8001b3e: f423 6380 bic.w r3, r3, #1024 ; 0x400
8001b42: 613b str r3, [r7, #16]
tmpcr2 &= ~TIM_CR2_OIS2N;
8001b44: 693b ldr r3, [r7, #16]
8001b46: f423 6300 bic.w r3, r3, #2048 ; 0x800
8001b4a: 613b str r3, [r7, #16]
/* Set the Output Idle state */
tmpcr2 |= (OC_Config->OCIdleState << 2U);
8001b4c: 683b ldr r3, [r7, #0]
8001b4e: 695b ldr r3, [r3, #20]
8001b50: 009b lsls r3, r3, #2
8001b52: 693a ldr r2, [r7, #16]
8001b54: 4313 orrs r3, r2
8001b56: 613b str r3, [r7, #16]
/* Set the Output N Idle state */
tmpcr2 |= (OC_Config->OCNIdleState << 2U);
8001b58: 683b ldr r3, [r7, #0]
8001b5a: 699b ldr r3, [r3, #24]
8001b5c: 009b lsls r3, r3, #2
8001b5e: 693a ldr r2, [r7, #16]
8001b60: 4313 orrs r3, r2
8001b62: 613b str r3, [r7, #16]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
8001b64: 687b ldr r3, [r7, #4]
8001b66: 693a ldr r2, [r7, #16]
8001b68: 605a str r2, [r3, #4]
/* Write to TIMx CCMR1 */
TIMx->CCMR1 = tmpccmrx;
8001b6a: 687b ldr r3, [r7, #4]
8001b6c: 68fa ldr r2, [r7, #12]
8001b6e: 619a str r2, [r3, #24]
/* Set the Capture Compare Register value */
TIMx->CCR2 = OC_Config->Pulse;
8001b70: 683b ldr r3, [r7, #0]
8001b72: 685a ldr r2, [r3, #4]
8001b74: 687b ldr r3, [r7, #4]
8001b76: 639a str r2, [r3, #56] ; 0x38
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
8001b78: 687b ldr r3, [r7, #4]
8001b7a: 697a ldr r2, [r7, #20]
8001b7c: 621a str r2, [r3, #32]
}
8001b7e: bf00 nop
8001b80: 371c adds r7, #28
8001b82: 46bd mov sp, r7
8001b84: bc80 pop {r7}
8001b86: 4770 bx lr
8001b88: 40012c00 .word 0x40012c00
08001b8c <TIM_OC3_SetConfig>:
* @param TIMx to select the TIM peripheral
* @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
{
8001b8c: b480 push {r7}
8001b8e: b087 sub sp, #28
8001b90: af00 add r7, sp, #0
8001b92: 6078 str r0, [r7, #4]
8001b94: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Disable the Channel 3: Reset the CC2E Bit */
TIMx->CCER &= ~TIM_CCER_CC3E;
8001b96: 687b ldr r3, [r7, #4]
8001b98: 6a1b ldr r3, [r3, #32]
8001b9a: f423 7280 bic.w r2, r3, #256 ; 0x100
8001b9e: 687b ldr r3, [r7, #4]
8001ba0: 621a str r2, [r3, #32]
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
8001ba2: 687b ldr r3, [r7, #4]
8001ba4: 6a1b ldr r3, [r3, #32]
8001ba6: 617b str r3, [r7, #20]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
8001ba8: 687b ldr r3, [r7, #4]
8001baa: 685b ldr r3, [r3, #4]
8001bac: 613b str r3, [r7, #16]
/* Get the TIMx CCMR2 register value */
tmpccmrx = TIMx->CCMR2;
8001bae: 687b ldr r3, [r7, #4]
8001bb0: 69db ldr r3, [r3, #28]
8001bb2: 60fb str r3, [r7, #12]
/* Reset the Output Compare mode and Capture/Compare selection Bits */
tmpccmrx &= ~TIM_CCMR2_OC3M;
8001bb4: 68fb ldr r3, [r7, #12]
8001bb6: f023 0370 bic.w r3, r3, #112 ; 0x70
8001bba: 60fb str r3, [r7, #12]
tmpccmrx &= ~TIM_CCMR2_CC3S;
8001bbc: 68fb ldr r3, [r7, #12]
8001bbe: f023 0303 bic.w r3, r3, #3
8001bc2: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= OC_Config->OCMode;
8001bc4: 683b ldr r3, [r7, #0]
8001bc6: 681b ldr r3, [r3, #0]
8001bc8: 68fa ldr r2, [r7, #12]
8001bca: 4313 orrs r3, r2
8001bcc: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC3P;
8001bce: 697b ldr r3, [r7, #20]
8001bd0: f423 7300 bic.w r3, r3, #512 ; 0x200
8001bd4: 617b str r3, [r7, #20]
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 8U);
8001bd6: 683b ldr r3, [r7, #0]
8001bd8: 689b ldr r3, [r3, #8]
8001bda: 021b lsls r3, r3, #8
8001bdc: 697a ldr r2, [r7, #20]
8001bde: 4313 orrs r3, r2
8001be0: 617b str r3, [r7, #20]
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
8001be2: 687b ldr r3, [r7, #4]
8001be4: 4a1d ldr r2, [pc, #116] ; (8001c5c <TIM_OC3_SetConfig+0xd0>)
8001be6: 4293 cmp r3, r2
8001be8: d10d bne.n 8001c06 <TIM_OC3_SetConfig+0x7a>
{
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
/* Reset the Output N Polarity level */
tmpccer &= ~TIM_CCER_CC3NP;
8001bea: 697b ldr r3, [r7, #20]
8001bec: f423 6300 bic.w r3, r3, #2048 ; 0x800
8001bf0: 617b str r3, [r7, #20]
/* Set the Output N Polarity */
tmpccer |= (OC_Config->OCNPolarity << 8U);
8001bf2: 683b ldr r3, [r7, #0]
8001bf4: 68db ldr r3, [r3, #12]
8001bf6: 021b lsls r3, r3, #8
8001bf8: 697a ldr r2, [r7, #20]
8001bfa: 4313 orrs r3, r2
8001bfc: 617b str r3, [r7, #20]
/* Reset the Output N State */
tmpccer &= ~TIM_CCER_CC3NE;
8001bfe: 697b ldr r3, [r7, #20]
8001c00: f423 6380 bic.w r3, r3, #1024 ; 0x400
8001c04: 617b str r3, [r7, #20]
}
if (IS_TIM_BREAK_INSTANCE(TIMx))
8001c06: 687b ldr r3, [r7, #4]
8001c08: 4a14 ldr r2, [pc, #80] ; (8001c5c <TIM_OC3_SetConfig+0xd0>)
8001c0a: 4293 cmp r3, r2
8001c0c: d113 bne.n 8001c36 <TIM_OC3_SetConfig+0xaa>
/* Check parameters */
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
/* Reset the Output Compare and Output Compare N IDLE State */
tmpcr2 &= ~TIM_CR2_OIS3;
8001c0e: 693b ldr r3, [r7, #16]
8001c10: f423 5380 bic.w r3, r3, #4096 ; 0x1000
8001c14: 613b str r3, [r7, #16]
tmpcr2 &= ~TIM_CR2_OIS3N;
8001c16: 693b ldr r3, [r7, #16]
8001c18: f423 5300 bic.w r3, r3, #8192 ; 0x2000
8001c1c: 613b str r3, [r7, #16]
/* Set the Output Idle state */
tmpcr2 |= (OC_Config->OCIdleState << 4U);
8001c1e: 683b ldr r3, [r7, #0]
8001c20: 695b ldr r3, [r3, #20]
8001c22: 011b lsls r3, r3, #4
8001c24: 693a ldr r2, [r7, #16]
8001c26: 4313 orrs r3, r2
8001c28: 613b str r3, [r7, #16]
/* Set the Output N Idle state */
tmpcr2 |= (OC_Config->OCNIdleState << 4U);
8001c2a: 683b ldr r3, [r7, #0]
8001c2c: 699b ldr r3, [r3, #24]
8001c2e: 011b lsls r3, r3, #4
8001c30: 693a ldr r2, [r7, #16]
8001c32: 4313 orrs r3, r2
8001c34: 613b str r3, [r7, #16]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
8001c36: 687b ldr r3, [r7, #4]
8001c38: 693a ldr r2, [r7, #16]
8001c3a: 605a str r2, [r3, #4]
/* Write to TIMx CCMR2 */
TIMx->CCMR2 = tmpccmrx;
8001c3c: 687b ldr r3, [r7, #4]
8001c3e: 68fa ldr r2, [r7, #12]
8001c40: 61da str r2, [r3, #28]
/* Set the Capture Compare Register value */
TIMx->CCR3 = OC_Config->Pulse;
8001c42: 683b ldr r3, [r7, #0]
8001c44: 685a ldr r2, [r3, #4]
8001c46: 687b ldr r3, [r7, #4]
8001c48: 63da str r2, [r3, #60] ; 0x3c
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
8001c4a: 687b ldr r3, [r7, #4]
8001c4c: 697a ldr r2, [r7, #20]
8001c4e: 621a str r2, [r3, #32]
}
8001c50: bf00 nop
8001c52: 371c adds r7, #28
8001c54: 46bd mov sp, r7
8001c56: bc80 pop {r7}
8001c58: 4770 bx lr
8001c5a: bf00 nop
8001c5c: 40012c00 .word 0x40012c00
08001c60 <TIM_OC4_SetConfig>:
* @param TIMx to select the TIM peripheral
* @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
{
8001c60: b480 push {r7}
8001c62: b087 sub sp, #28
8001c64: af00 add r7, sp, #0
8001c66: 6078 str r0, [r7, #4]
8001c68: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Disable the Channel 4: Reset the CC4E Bit */
TIMx->CCER &= ~TIM_CCER_CC4E;
8001c6a: 687b ldr r3, [r7, #4]
8001c6c: 6a1b ldr r3, [r3, #32]
8001c6e: f423 5280 bic.w r2, r3, #4096 ; 0x1000
8001c72: 687b ldr r3, [r7, #4]
8001c74: 621a str r2, [r3, #32]
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
8001c76: 687b ldr r3, [r7, #4]
8001c78: 6a1b ldr r3, [r3, #32]
8001c7a: 613b str r3, [r7, #16]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
8001c7c: 687b ldr r3, [r7, #4]
8001c7e: 685b ldr r3, [r3, #4]
8001c80: 617b str r3, [r7, #20]
/* Get the TIMx CCMR2 register value */
tmpccmrx = TIMx->CCMR2;
8001c82: 687b ldr r3, [r7, #4]
8001c84: 69db ldr r3, [r3, #28]
8001c86: 60fb str r3, [r7, #12]
/* Reset the Output Compare mode and Capture/Compare selection Bits */
tmpccmrx &= ~TIM_CCMR2_OC4M;
8001c88: 68fb ldr r3, [r7, #12]
8001c8a: f423 43e0 bic.w r3, r3, #28672 ; 0x7000
8001c8e: 60fb str r3, [r7, #12]
tmpccmrx &= ~TIM_CCMR2_CC4S;
8001c90: 68fb ldr r3, [r7, #12]
8001c92: f423 7340 bic.w r3, r3, #768 ; 0x300
8001c96: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= (OC_Config->OCMode << 8U);
8001c98: 683b ldr r3, [r7, #0]
8001c9a: 681b ldr r3, [r3, #0]
8001c9c: 021b lsls r3, r3, #8
8001c9e: 68fa ldr r2, [r7, #12]
8001ca0: 4313 orrs r3, r2
8001ca2: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC4P;
8001ca4: 693b ldr r3, [r7, #16]
8001ca6: f423 5300 bic.w r3, r3, #8192 ; 0x2000
8001caa: 613b str r3, [r7, #16]
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 12U);
8001cac: 683b ldr r3, [r7, #0]
8001cae: 689b ldr r3, [r3, #8]
8001cb0: 031b lsls r3, r3, #12
8001cb2: 693a ldr r2, [r7, #16]
8001cb4: 4313 orrs r3, r2
8001cb6: 613b str r3, [r7, #16]
if (IS_TIM_BREAK_INSTANCE(TIMx))
8001cb8: 687b ldr r3, [r7, #4]
8001cba: 4a0f ldr r2, [pc, #60] ; (8001cf8 <TIM_OC4_SetConfig+0x98>)
8001cbc: 4293 cmp r3, r2
8001cbe: d109 bne.n 8001cd4 <TIM_OC4_SetConfig+0x74>
{
/* Check parameters */
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
/* Reset the Output Compare IDLE State */
tmpcr2 &= ~TIM_CR2_OIS4;
8001cc0: 697b ldr r3, [r7, #20]
8001cc2: f423 4380 bic.w r3, r3, #16384 ; 0x4000
8001cc6: 617b str r3, [r7, #20]
/* Set the Output Idle state */
tmpcr2 |= (OC_Config->OCIdleState << 6U);
8001cc8: 683b ldr r3, [r7, #0]
8001cca: 695b ldr r3, [r3, #20]
8001ccc: 019b lsls r3, r3, #6
8001cce: 697a ldr r2, [r7, #20]
8001cd0: 4313 orrs r3, r2
8001cd2: 617b str r3, [r7, #20]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
8001cd4: 687b ldr r3, [r7, #4]
8001cd6: 697a ldr r2, [r7, #20]
8001cd8: 605a str r2, [r3, #4]
/* Write to TIMx CCMR2 */
TIMx->CCMR2 = tmpccmrx;
8001cda: 687b ldr r3, [r7, #4]
8001cdc: 68fa ldr r2, [r7, #12]
8001cde: 61da str r2, [r3, #28]
/* Set the Capture Compare Register value */
TIMx->CCR4 = OC_Config->Pulse;
8001ce0: 683b ldr r3, [r7, #0]
8001ce2: 685a ldr r2, [r3, #4]
8001ce4: 687b ldr r3, [r7, #4]
8001ce6: 641a str r2, [r3, #64] ; 0x40
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
8001ce8: 687b ldr r3, [r7, #4]
8001cea: 693a ldr r2, [r7, #16]
8001cec: 621a str r2, [r3, #32]
}
8001cee: bf00 nop
8001cf0: 371c adds r7, #28
8001cf2: 46bd mov sp, r7
8001cf4: bc80 pop {r7}
8001cf6: 4770 bx lr
8001cf8: 40012c00 .word 0x40012c00
08001cfc <TIM_TI1_ConfigInputStage>:
* @param TIM_ICFilter Specifies the Input Capture Filter.
* This parameter must be a value between 0x00 and 0x0F.
* @retval None
*/
static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
{
8001cfc: b480 push {r7}
8001cfe: b087 sub sp, #28
8001d00: af00 add r7, sp, #0
8001d02: 60f8 str r0, [r7, #12]
8001d04: 60b9 str r1, [r7, #8]
8001d06: 607a str r2, [r7, #4]
uint32_t tmpccmr1;
uint32_t tmpccer;
/* Disable the Channel 1: Reset the CC1E Bit */
tmpccer = TIMx->CCER;
8001d08: 68fb ldr r3, [r7, #12]
8001d0a: 6a1b ldr r3, [r3, #32]
8001d0c: 617b str r3, [r7, #20]
TIMx->CCER &= ~TIM_CCER_CC1E;
8001d0e: 68fb ldr r3, [r7, #12]
8001d10: 6a1b ldr r3, [r3, #32]
8001d12: f023 0201 bic.w r2, r3, #1
8001d16: 68fb ldr r3, [r7, #12]
8001d18: 621a str r2, [r3, #32]
tmpccmr1 = TIMx->CCMR1;
8001d1a: 68fb ldr r3, [r7, #12]
8001d1c: 699b ldr r3, [r3, #24]
8001d1e: 613b str r3, [r7, #16]
/* Set the filter */
tmpccmr1 &= ~TIM_CCMR1_IC1F;
8001d20: 693b ldr r3, [r7, #16]
8001d22: f023 03f0 bic.w r3, r3, #240 ; 0xf0
8001d26: 613b str r3, [r7, #16]
tmpccmr1 |= (TIM_ICFilter << 4U);
8001d28: 687b ldr r3, [r7, #4]
8001d2a: 011b lsls r3, r3, #4
8001d2c: 693a ldr r2, [r7, #16]
8001d2e: 4313 orrs r3, r2
8001d30: 613b str r3, [r7, #16]
/* Select the Polarity and set the CC1E Bit */
tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
8001d32: 697b ldr r3, [r7, #20]
8001d34: f023 030a bic.w r3, r3, #10
8001d38: 617b str r3, [r7, #20]
tmpccer |= TIM_ICPolarity;
8001d3a: 697a ldr r2, [r7, #20]
8001d3c: 68bb ldr r3, [r7, #8]
8001d3e: 4313 orrs r3, r2
8001d40: 617b str r3, [r7, #20]
/* Write to TIMx CCMR1 and CCER registers */
TIMx->CCMR1 = tmpccmr1;
8001d42: 68fb ldr r3, [r7, #12]
8001d44: 693a ldr r2, [r7, #16]
8001d46: 619a str r2, [r3, #24]
TIMx->CCER = tmpccer;
8001d48: 68fb ldr r3, [r7, #12]
8001d4a: 697a ldr r2, [r7, #20]
8001d4c: 621a str r2, [r3, #32]
}
8001d4e: bf00 nop
8001d50: 371c adds r7, #28
8001d52: 46bd mov sp, r7
8001d54: bc80 pop {r7}
8001d56: 4770 bx lr
08001d58 <TIM_TI2_ConfigInputStage>:
* @param TIM_ICFilter Specifies the Input Capture Filter.
* This parameter must be a value between 0x00 and 0x0F.
* @retval None
*/
static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
{
8001d58: b480 push {r7}
8001d5a: b087 sub sp, #28
8001d5c: af00 add r7, sp, #0
8001d5e: 60f8 str r0, [r7, #12]
8001d60: 60b9 str r1, [r7, #8]
8001d62: 607a str r2, [r7, #4]
uint32_t tmpccmr1;
uint32_t tmpccer;
/* Disable the Channel 2: Reset the CC2E Bit */
TIMx->CCER &= ~TIM_CCER_CC2E;
8001d64: 68fb ldr r3, [r7, #12]
8001d66: 6a1b ldr r3, [r3, #32]
8001d68: f023 0210 bic.w r2, r3, #16
8001d6c: 68fb ldr r3, [r7, #12]
8001d6e: 621a str r2, [r3, #32]
tmpccmr1 = TIMx->CCMR1;
8001d70: 68fb ldr r3, [r7, #12]
8001d72: 699b ldr r3, [r3, #24]
8001d74: 617b str r3, [r7, #20]
tmpccer = TIMx->CCER;
8001d76: 68fb ldr r3, [r7, #12]
8001d78: 6a1b ldr r3, [r3, #32]
8001d7a: 613b str r3, [r7, #16]
/* Set the filter */
tmpccmr1 &= ~TIM_CCMR1_IC2F;
8001d7c: 697b ldr r3, [r7, #20]
8001d7e: f423 4370 bic.w r3, r3, #61440 ; 0xf000
8001d82: 617b str r3, [r7, #20]
tmpccmr1 |= (TIM_ICFilter << 12U);
8001d84: 687b ldr r3, [r7, #4]
8001d86: 031b lsls r3, r3, #12
8001d88: 697a ldr r2, [r7, #20]
8001d8a: 4313 orrs r3, r2
8001d8c: 617b str r3, [r7, #20]
/* Select the Polarity and set the CC2E Bit */
tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
8001d8e: 693b ldr r3, [r7, #16]
8001d90: f023 03a0 bic.w r3, r3, #160 ; 0xa0
8001d94: 613b str r3, [r7, #16]
tmpccer |= (TIM_ICPolarity << 4U);
8001d96: 68bb ldr r3, [r7, #8]
8001d98: 011b lsls r3, r3, #4
8001d9a: 693a ldr r2, [r7, #16]
8001d9c: 4313 orrs r3, r2
8001d9e: 613b str r3, [r7, #16]
/* Write to TIMx CCMR1 and CCER registers */
TIMx->CCMR1 = tmpccmr1 ;
8001da0: 68fb ldr r3, [r7, #12]
8001da2: 697a ldr r2, [r7, #20]
8001da4: 619a str r2, [r3, #24]
TIMx->CCER = tmpccer;
8001da6: 68fb ldr r3, [r7, #12]
8001da8: 693a ldr r2, [r7, #16]
8001daa: 621a str r2, [r3, #32]
}
8001dac: bf00 nop
8001dae: 371c adds r7, #28
8001db0: 46bd mov sp, r7
8001db2: bc80 pop {r7}
8001db4: 4770 bx lr
08001db6 <TIM_ITRx_SetConfig>:
* @arg TIM_TS_TI2FP2: Filtered Timer Input 2
* @arg TIM_TS_ETRF: External Trigger input
* @retval None
*/
static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource)
{
8001db6: b480 push {r7}
8001db8: b085 sub sp, #20
8001dba: af00 add r7, sp, #0
8001dbc: 6078 str r0, [r7, #4]
8001dbe: 6039 str r1, [r7, #0]
uint32_t tmpsmcr;
/* Get the TIMx SMCR register value */
tmpsmcr = TIMx->SMCR;
8001dc0: 687b ldr r3, [r7, #4]
8001dc2: 689b ldr r3, [r3, #8]
8001dc4: 60fb str r3, [r7, #12]
/* Reset the TS Bits */
tmpsmcr &= ~TIM_SMCR_TS;
8001dc6: 68fb ldr r3, [r7, #12]
8001dc8: f023 0370 bic.w r3, r3, #112 ; 0x70
8001dcc: 60fb str r3, [r7, #12]
/* Set the Input Trigger source and the slave mode*/
tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1);
8001dce: 683a ldr r2, [r7, #0]
8001dd0: 68fb ldr r3, [r7, #12]
8001dd2: 4313 orrs r3, r2
8001dd4: f043 0307 orr.w r3, r3, #7
8001dd8: 60fb str r3, [r7, #12]
/* Write to TIMx SMCR */
TIMx->SMCR = tmpsmcr;
8001dda: 687b ldr r3, [r7, #4]
8001ddc: 68fa ldr r2, [r7, #12]
8001dde: 609a str r2, [r3, #8]
}
8001de0: bf00 nop
8001de2: 3714 adds r7, #20
8001de4: 46bd mov sp, r7
8001de6: bc80 pop {r7}
8001de8: 4770 bx lr
08001dea <TIM_ETR_SetConfig>:
* This parameter must be a value between 0x00 and 0x0F
* @retval None
*/
void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
{
8001dea: b480 push {r7}
8001dec: b087 sub sp, #28
8001dee: af00 add r7, sp, #0
8001df0: 60f8 str r0, [r7, #12]
8001df2: 60b9 str r1, [r7, #8]
8001df4: 607a str r2, [r7, #4]
8001df6: 603b str r3, [r7, #0]
uint32_t tmpsmcr;
tmpsmcr = TIMx->SMCR;
8001df8: 68fb ldr r3, [r7, #12]
8001dfa: 689b ldr r3, [r3, #8]
8001dfc: 617b str r3, [r7, #20]
/* Reset the ETR Bits */
tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
8001dfe: 697b ldr r3, [r7, #20]
8001e00: f423 437f bic.w r3, r3, #65280 ; 0xff00
8001e04: 617b str r3, [r7, #20]
/* Set the Prescaler, the Filter value and the Polarity */
tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));
8001e06: 683b ldr r3, [r7, #0]
8001e08: 021a lsls r2, r3, #8
8001e0a: 687b ldr r3, [r7, #4]
8001e0c: 431a orrs r2, r3
8001e0e: 68bb ldr r3, [r7, #8]
8001e10: 4313 orrs r3, r2
8001e12: 697a ldr r2, [r7, #20]
8001e14: 4313 orrs r3, r2
8001e16: 617b str r3, [r7, #20]
/* Write to TIMx SMCR */
TIMx->SMCR = tmpsmcr;
8001e18: 68fb ldr r3, [r7, #12]
8001e1a: 697a ldr r2, [r7, #20]
8001e1c: 609a str r2, [r3, #8]
}
8001e1e: bf00 nop
8001e20: 371c adds r7, #28
8001e22: 46bd mov sp, r7
8001e24: bc80 pop {r7}
8001e26: 4770 bx lr
08001e28 <TIM_CCxChannelCmd>:
* @param ChannelState specifies the TIM Channel CCxE bit new state.
* This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE.
* @retval None
*/
void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)
{
8001e28: b480 push {r7}
8001e2a: b087 sub sp, #28
8001e2c: af00 add r7, sp, #0
8001e2e: 60f8 str r0, [r7, #12]
8001e30: 60b9 str r1, [r7, #8]
8001e32: 607a str r2, [r7, #4]
/* Check the parameters */
assert_param(IS_TIM_CC1_INSTANCE(TIMx));
assert_param(IS_TIM_CHANNELS(Channel));
tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */
8001e34: 68bb ldr r3, [r7, #8]
8001e36: f003 031f and.w r3, r3, #31
8001e3a: 2201 movs r2, #1
8001e3c: fa02 f303 lsl.w r3, r2, r3
8001e40: 617b str r3, [r7, #20]
/* Reset the CCxE Bit */
TIMx->CCER &= ~tmp;
8001e42: 68fb ldr r3, [r7, #12]
8001e44: 6a1a ldr r2, [r3, #32]
8001e46: 697b ldr r3, [r7, #20]
8001e48: 43db mvns r3, r3
8001e4a: 401a ands r2, r3
8001e4c: 68fb ldr r3, [r7, #12]
8001e4e: 621a str r2, [r3, #32]
/* Set or reset the CCxE Bit */
TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
8001e50: 68fb ldr r3, [r7, #12]
8001e52: 6a1a ldr r2, [r3, #32]
8001e54: 68bb ldr r3, [r7, #8]
8001e56: f003 031f and.w r3, r3, #31
8001e5a: 6879 ldr r1, [r7, #4]
8001e5c: fa01 f303 lsl.w r3, r1, r3
8001e60: 431a orrs r2, r3
8001e62: 68fb ldr r3, [r7, #12]
8001e64: 621a str r2, [r3, #32]
}
8001e66: bf00 nop
8001e68: 371c adds r7, #28
8001e6a: 46bd mov sp, r7
8001e6c: bc80 pop {r7}
8001e6e: 4770 bx lr
08001e70 <HAL_TIMEx_MasterConfigSynchronization>:
* mode.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
TIM_MasterConfigTypeDef *sMasterConfig)
{
8001e70: b480 push {r7}
8001e72: b085 sub sp, #20
8001e74: af00 add r7, sp, #0
8001e76: 6078 str r0, [r7, #4]
8001e78: 6039 str r1, [r7, #0]
assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
/* Check input state */
__HAL_LOCK(htim);
8001e7a: 687b ldr r3, [r7, #4]
8001e7c: f893 303c ldrb.w r3, [r3, #60] ; 0x3c
8001e80: 2b01 cmp r3, #1
8001e82: d101 bne.n 8001e88 <HAL_TIMEx_MasterConfigSynchronization+0x18>
8001e84: 2302 movs r3, #2
8001e86: e046 b.n 8001f16 <HAL_TIMEx_MasterConfigSynchronization+0xa6>
8001e88: 687b ldr r3, [r7, #4]
8001e8a: 2201 movs r2, #1
8001e8c: f883 203c strb.w r2, [r3, #60] ; 0x3c
/* Change the handler state */
htim->State = HAL_TIM_STATE_BUSY;
8001e90: 687b ldr r3, [r7, #4]
8001e92: 2202 movs r2, #2
8001e94: f883 203d strb.w r2, [r3, #61] ; 0x3d
/* Get the TIMx CR2 register value */
tmpcr2 = htim->Instance->CR2;
8001e98: 687b ldr r3, [r7, #4]
8001e9a: 681b ldr r3, [r3, #0]
8001e9c: 685b ldr r3, [r3, #4]
8001e9e: 60fb str r3, [r7, #12]
/* Get the TIMx SMCR register value */
tmpsmcr = htim->Instance->SMCR;
8001ea0: 687b ldr r3, [r7, #4]
8001ea2: 681b ldr r3, [r3, #0]
8001ea4: 689b ldr r3, [r3, #8]
8001ea6: 60bb str r3, [r7, #8]
/* Reset the MMS Bits */
tmpcr2 &= ~TIM_CR2_MMS;
8001ea8: 68fb ldr r3, [r7, #12]
8001eaa: f023 0370 bic.w r3, r3, #112 ; 0x70
8001eae: 60fb str r3, [r7, #12]
/* Select the TRGO source */
tmpcr2 |= sMasterConfig->MasterOutputTrigger;
8001eb0: 683b ldr r3, [r7, #0]
8001eb2: 681b ldr r3, [r3, #0]
8001eb4: 68fa ldr r2, [r7, #12]
8001eb6: 4313 orrs r3, r2
8001eb8: 60fb str r3, [r7, #12]
/* Update TIMx CR2 */
htim->Instance->CR2 = tmpcr2;
8001eba: 687b ldr r3, [r7, #4]
8001ebc: 681b ldr r3, [r3, #0]
8001ebe: 68fa ldr r2, [r7, #12]
8001ec0: 605a str r2, [r3, #4]
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
8001ec2: 687b ldr r3, [r7, #4]
8001ec4: 681b ldr r3, [r3, #0]
8001ec6: 4a16 ldr r2, [pc, #88] ; (8001f20 <HAL_TIMEx_MasterConfigSynchronization+0xb0>)
8001ec8: 4293 cmp r3, r2
8001eca: d00e beq.n 8001eea <HAL_TIMEx_MasterConfigSynchronization+0x7a>
8001ecc: 687b ldr r3, [r7, #4]
8001ece: 681b ldr r3, [r3, #0]
8001ed0: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
8001ed4: d009 beq.n 8001eea <HAL_TIMEx_MasterConfigSynchronization+0x7a>
8001ed6: 687b ldr r3, [r7, #4]
8001ed8: 681b ldr r3, [r3, #0]
8001eda: 4a12 ldr r2, [pc, #72] ; (8001f24 <HAL_TIMEx_MasterConfigSynchronization+0xb4>)
8001edc: 4293 cmp r3, r2
8001ede: d004 beq.n 8001eea <HAL_TIMEx_MasterConfigSynchronization+0x7a>
8001ee0: 687b ldr r3, [r7, #4]
8001ee2: 681b ldr r3, [r3, #0]
8001ee4: 4a10 ldr r2, [pc, #64] ; (8001f28 <HAL_TIMEx_MasterConfigSynchronization+0xb8>)
8001ee6: 4293 cmp r3, r2
8001ee8: d10c bne.n 8001f04 <HAL_TIMEx_MasterConfigSynchronization+0x94>
{
/* Reset the MSM Bit */
tmpsmcr &= ~TIM_SMCR_MSM;
8001eea: 68bb ldr r3, [r7, #8]
8001eec: f023 0380 bic.w r3, r3, #128 ; 0x80
8001ef0: 60bb str r3, [r7, #8]
/* Set master mode */
tmpsmcr |= sMasterConfig->MasterSlaveMode;
8001ef2: 683b ldr r3, [r7, #0]
8001ef4: 685b ldr r3, [r3, #4]
8001ef6: 68ba ldr r2, [r7, #8]
8001ef8: 4313 orrs r3, r2
8001efa: 60bb str r3, [r7, #8]
/* Update TIMx SMCR */
htim->Instance->SMCR = tmpsmcr;
8001efc: 687b ldr r3, [r7, #4]
8001efe: 681b ldr r3, [r3, #0]
8001f00: 68ba ldr r2, [r7, #8]
8001f02: 609a str r2, [r3, #8]
}
/* Change the htim state */
htim->State = HAL_TIM_STATE_READY;
8001f04: 687b ldr r3, [r7, #4]
8001f06: 2201 movs r2, #1
8001f08: f883 203d strb.w r2, [r3, #61] ; 0x3d
__HAL_UNLOCK(htim);
8001f0c: 687b ldr r3, [r7, #4]
8001f0e: 2200 movs r2, #0
8001f10: f883 203c strb.w r2, [r3, #60] ; 0x3c
return HAL_OK;
8001f14: 2300 movs r3, #0
}
8001f16: 4618 mov r0, r3
8001f18: 3714 adds r7, #20
8001f1a: 46bd mov sp, r7
8001f1c: bc80 pop {r7}
8001f1e: 4770 bx lr
8001f20: 40012c00 .word 0x40012c00
8001f24: 40000400 .word 0x40000400
8001f28: 40000800 .word 0x40000800
08001f2c <__libc_init_array>:
8001f2c: b570 push {r4, r5, r6, lr}
8001f2e: 2600 movs r6, #0
8001f30: 4d0c ldr r5, [pc, #48] ; (8001f64 <__libc_init_array+0x38>)
8001f32: 4c0d ldr r4, [pc, #52] ; (8001f68 <__libc_init_array+0x3c>)
8001f34: 1b64 subs r4, r4, r5
8001f36: 10a4 asrs r4, r4, #2
8001f38: 42a6 cmp r6, r4
8001f3a: d109 bne.n 8001f50 <__libc_init_array+0x24>
8001f3c: f000 f822 bl 8001f84 <_init>
8001f40: 2600 movs r6, #0
8001f42: 4d0a ldr r5, [pc, #40] ; (8001f6c <__libc_init_array+0x40>)
8001f44: 4c0a ldr r4, [pc, #40] ; (8001f70 <__libc_init_array+0x44>)
8001f46: 1b64 subs r4, r4, r5
8001f48: 10a4 asrs r4, r4, #2
8001f4a: 42a6 cmp r6, r4
8001f4c: d105 bne.n 8001f5a <__libc_init_array+0x2e>
8001f4e: bd70 pop {r4, r5, r6, pc}
8001f50: f855 3b04 ldr.w r3, [r5], #4
8001f54: 4798 blx r3
8001f56: 3601 adds r6, #1
8001f58: e7ee b.n 8001f38 <__libc_init_array+0xc>
8001f5a: f855 3b04 ldr.w r3, [r5], #4
8001f5e: 4798 blx r3
8001f60: 3601 adds r6, #1
8001f62: e7f2 b.n 8001f4a <__libc_init_array+0x1e>
8001f64: 08001fbc .word 0x08001fbc
8001f68: 08001fbc .word 0x08001fbc
8001f6c: 08001fbc .word 0x08001fbc
8001f70: 08001fc0 .word 0x08001fc0
08001f74 <memset>:
8001f74: 4603 mov r3, r0
8001f76: 4402 add r2, r0
8001f78: 4293 cmp r3, r2
8001f7a: d100 bne.n 8001f7e <memset+0xa>
8001f7c: 4770 bx lr
8001f7e: f803 1b01 strb.w r1, [r3], #1
8001f82: e7f9 b.n 8001f78 <memset+0x4>
08001f84 <_init>:
8001f84: b5f8 push {r3, r4, r5, r6, r7, lr}
8001f86: bf00 nop
8001f88: bcf8 pop {r3, r4, r5, r6, r7}
8001f8a: bc08 pop {r3}
8001f8c: 469e mov lr, r3
8001f8e: 4770 bx lr
08001f90 <_fini>:
8001f90: b5f8 push {r3, r4, r5, r6, r7, lr}
8001f92: bf00 nop
8001f94: bcf8 pop {r3, r4, r5, r6, r7}
8001f96: bc08 pop {r3}
8001f98: 469e mov lr, r3
8001f9a: 4770 bx lr
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