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stm32-course-old/Examples/PWM_RGB/Debug/PWM_RGB.list

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PWM_RGB.elf: file format elf32-littlearm
Sections:
Idx Name Size VMA LMA File off Algn
0 .isr_vector 0000010c 08000000 08000000 00010000 2**0
CONTENTS, ALLOC, LOAD, READONLY, DATA
1 .text 00001ed4 0800010c 0800010c 0001010c 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
2 .rodata 00000020 08001fe0 08001fe0 00011fe0 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
3 .ARM.extab 00000000 08002000 08002000 0002000c 2**0
CONTENTS
4 .ARM 00000000 08002000 08002000 0002000c 2**0
CONTENTS
5 .preinit_array 00000000 08002000 08002000 0002000c 2**0
CONTENTS, ALLOC, LOAD, DATA
6 .init_array 00000004 08002000 08002000 00012000 2**2
CONTENTS, ALLOC, LOAD, DATA
7 .fini_array 00000004 08002004 08002004 00012004 2**2
CONTENTS, ALLOC, LOAD, DATA
8 .data 0000000c 20000000 08002008 00020000 2**2
CONTENTS, ALLOC, LOAD, DATA
9 .bss 00000068 2000000c 08002014 0002000c 2**2
ALLOC
10 ._user_heap_stack 00000604 20000074 08002014 00020074 2**0
ALLOC
11 .ARM.attributes 00000029 00000000 00000000 0002000c 2**0
CONTENTS, READONLY
12 .debug_info 00007a97 00000000 00000000 00020035 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
13 .debug_abbrev 000015a3 00000000 00000000 00027acc 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
14 .debug_aranges 00000958 00000000 00000000 00029070 2**3
CONTENTS, READONLY, DEBUGGING, OCTETS
15 .debug_ranges 00000890 00000000 00000000 000299c8 2**3
CONTENTS, READONLY, DEBUGGING, OCTETS
16 .debug_macro 000168cb 00000000 00000000 0002a258 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
17 .debug_line 00009fdd 00000000 00000000 00040b23 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
18 .debug_str 00083dd9 00000000 00000000 0004ab00 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
19 .comment 00000050 00000000 00000000 000ce8d9 2**0
CONTENTS, READONLY
20 .debug_frame 000025e0 00000000 00000000 000ce92c 2**2
CONTENTS, READONLY, DEBUGGING, OCTETS
Disassembly of section .text:
0800010c <__do_global_dtors_aux>:
800010c: b510 push {r4, lr}
800010e: 4c05 ldr r4, [pc, #20] ; (8000124 <__do_global_dtors_aux+0x18>)
8000110: 7823 ldrb r3, [r4, #0]
8000112: b933 cbnz r3, 8000122 <__do_global_dtors_aux+0x16>
8000114: 4b04 ldr r3, [pc, #16] ; (8000128 <__do_global_dtors_aux+0x1c>)
8000116: b113 cbz r3, 800011e <__do_global_dtors_aux+0x12>
8000118: 4804 ldr r0, [pc, #16] ; (800012c <__do_global_dtors_aux+0x20>)
800011a: f3af 8000 nop.w
800011e: 2301 movs r3, #1
8000120: 7023 strb r3, [r4, #0]
8000122: bd10 pop {r4, pc}
8000124: 2000000c .word 0x2000000c
8000128: 00000000 .word 0x00000000
800012c: 08001fc8 .word 0x08001fc8
08000130 <frame_dummy>:
8000130: b508 push {r3, lr}
8000132: 4b03 ldr r3, [pc, #12] ; (8000140 <frame_dummy+0x10>)
8000134: b11b cbz r3, 800013e <frame_dummy+0xe>
8000136: 4903 ldr r1, [pc, #12] ; (8000144 <frame_dummy+0x14>)
8000138: 4803 ldr r0, [pc, #12] ; (8000148 <frame_dummy+0x18>)
800013a: f3af 8000 nop.w
800013e: bd08 pop {r3, pc}
8000140: 00000000 .word 0x00000000
8000144: 20000010 .word 0x20000010
8000148: 08001fc8 .word 0x08001fc8
0800014c <MX_GPIO_Init>:
* Output
* EVENT_OUT
* EXTI
*/
void MX_GPIO_Init(void)
{
800014c: b480 push {r7}
800014e: b085 sub sp, #20
8000150: af00 add r7, sp, #0
/* GPIO Ports Clock Enable */
__HAL_RCC_GPIOD_CLK_ENABLE();
8000152: 4b14 ldr r3, [pc, #80] ; (80001a4 <MX_GPIO_Init+0x58>)
8000154: 699b ldr r3, [r3, #24]
8000156: 4a13 ldr r2, [pc, #76] ; (80001a4 <MX_GPIO_Init+0x58>)
8000158: f043 0320 orr.w r3, r3, #32
800015c: 6193 str r3, [r2, #24]
800015e: 4b11 ldr r3, [pc, #68] ; (80001a4 <MX_GPIO_Init+0x58>)
8000160: 699b ldr r3, [r3, #24]
8000162: f003 0320 and.w r3, r3, #32
8000166: 60fb str r3, [r7, #12]
8000168: 68fb ldr r3, [r7, #12]
__HAL_RCC_GPIOA_CLK_ENABLE();
800016a: 4b0e ldr r3, [pc, #56] ; (80001a4 <MX_GPIO_Init+0x58>)
800016c: 699b ldr r3, [r3, #24]
800016e: 4a0d ldr r2, [pc, #52] ; (80001a4 <MX_GPIO_Init+0x58>)
8000170: f043 0304 orr.w r3, r3, #4
8000174: 6193 str r3, [r2, #24]
8000176: 4b0b ldr r3, [pc, #44] ; (80001a4 <MX_GPIO_Init+0x58>)
8000178: 699b ldr r3, [r3, #24]
800017a: f003 0304 and.w r3, r3, #4
800017e: 60bb str r3, [r7, #8]
8000180: 68bb ldr r3, [r7, #8]
__HAL_RCC_GPIOB_CLK_ENABLE();
8000182: 4b08 ldr r3, [pc, #32] ; (80001a4 <MX_GPIO_Init+0x58>)
8000184: 699b ldr r3, [r3, #24]
8000186: 4a07 ldr r2, [pc, #28] ; (80001a4 <MX_GPIO_Init+0x58>)
8000188: f043 0308 orr.w r3, r3, #8
800018c: 6193 str r3, [r2, #24]
800018e: 4b05 ldr r3, [pc, #20] ; (80001a4 <MX_GPIO_Init+0x58>)
8000190: 699b ldr r3, [r3, #24]
8000192: f003 0308 and.w r3, r3, #8
8000196: 607b str r3, [r7, #4]
8000198: 687b ldr r3, [r7, #4]
}
800019a: bf00 nop
800019c: 3714 adds r7, #20
800019e: 46bd mov sp, r7
80001a0: bc80 pop {r7}
80001a2: 4770 bx lr
80001a4: 40021000 .word 0x40021000
080001a8 <main>:
/**
* @brief The application entry point.
* @retval int
*/
int main(void) {
80001a8: b580 push {r7, lr}
80001aa: b086 sub sp, #24
80001ac: af00 add r7, sp, #0
/* USER CODE END 1 */
/* MCU Configuration--------------------------------------------------------*/
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
HAL_Init();
80001ae: f000 fa3b bl 8000628 <HAL_Init>
/* USER CODE BEGIN Init */
/* USER CODE END Init */
/* Configure the system clock */
SystemClock_Config();
80001b2: f000 f873 bl 800029c <SystemClock_Config>
/* USER CODE BEGIN SysInit */
/* USER CODE END SysInit */
/* Initialize all configured peripherals */
MX_GPIO_Init();
80001b6: f7ff ffc9 bl 800014c <MX_GPIO_Init>
MX_TIM3_Init();
80001ba: f000 f919 bl 80003f0 <MX_TIM3_Init>
/* USER CODE BEGIN 2 */
//启动PWM输出
HAL_TIM_PWM_Start(&htim3, TIM_CHANNEL_1);
80001be: 2100 movs r1, #0
80001c0: 4835 ldr r0, [pc, #212] ; (8000298 <main+0xf0>)
80001c2: f001 f9af bl 8001524 <HAL_TIM_PWM_Start>
HAL_TIM_PWM_Start(&htim3, TIM_CHANNEL_2);
80001c6: 2104 movs r1, #4
80001c8: 4833 ldr r0, [pc, #204] ; (8000298 <main+0xf0>)
80001ca: f001 f9ab bl 8001524 <HAL_TIM_PWM_Start>
HAL_TIM_PWM_Start(&htim3, TIM_CHANNEL_3);
80001ce: 2108 movs r1, #8
80001d0: 4831 ldr r0, [pc, #196] ; (8000298 <main+0xf0>)
80001d2: f001 f9a7 bl 8001524 <HAL_TIM_PWM_Start>
/* Infinite loop */
/* USER CODE BEGIN WHILE */
while (1) {
//循环CH1（蓝色）先增后减
for (int period = 0; period < 100; period++) {
80001d6: 2300 movs r3, #0
80001d8: 617b str r3, [r7, #20]
80001da: e009 b.n 80001f0 <main+0x48>
__HAL_TIM_SET_COMPARE(&htim3, TIM_CHANNEL_1, period);
80001dc: 4b2e ldr r3, [pc, #184] ; (8000298 <main+0xf0>)
80001de: 681b ldr r3, [r3, #0]
80001e0: 697a ldr r2, [r7, #20]
80001e2: 635a str r2, [r3, #52] ; 0x34
HAL_Delay(7);
80001e4: 2007 movs r0, #7
80001e6: f000 fa81 bl 80006ec <HAL_Delay>
for (int period = 0; period < 100; period++) {
80001ea: 697b ldr r3, [r7, #20]
80001ec: 3301 adds r3, #1
80001ee: 617b str r3, [r7, #20]
80001f0: 697b ldr r3, [r7, #20]
80001f2: 2b63 cmp r3, #99 ; 0x63
80001f4: ddf2 ble.n 80001dc <main+0x34>
}
for (int period = 99; period >= 0; period--) {
80001f6: 2363 movs r3, #99 ; 0x63
80001f8: 613b str r3, [r7, #16]
80001fa: e009 b.n 8000210 <main+0x68>
__HAL_TIM_SET_COMPARE(&htim3, TIM_CHANNEL_1, period);
80001fc: 4b26 ldr r3, [pc, #152] ; (8000298 <main+0xf0>)
80001fe: 681b ldr r3, [r3, #0]
8000200: 693a ldr r2, [r7, #16]
8000202: 635a str r2, [r3, #52] ; 0x34
HAL_Delay(7);
8000204: 2007 movs r0, #7
8000206: f000 fa71 bl 80006ec <HAL_Delay>
for (int period = 99; period >= 0; period--) {
800020a: 693b ldr r3, [r7, #16]
800020c: 3b01 subs r3, #1
800020e: 613b str r3, [r7, #16]
8000210: 693b ldr r3, [r7, #16]
8000212: 2b00 cmp r3, #0
8000214: daf2 bge.n 80001fc <main+0x54>
}
//循环CH2（绿色）先增后减
for (int period = 0; period < 100; period++) {
8000216: 2300 movs r3, #0
8000218: 60fb str r3, [r7, #12]
800021a: e009 b.n 8000230 <main+0x88>
__HAL_TIM_SET_COMPARE(&htim3, TIM_CHANNEL_2, period);
800021c: 4b1e ldr r3, [pc, #120] ; (8000298 <main+0xf0>)
800021e: 681b ldr r3, [r3, #0]
8000220: 68fa ldr r2, [r7, #12]
8000222: 639a str r2, [r3, #56] ; 0x38
HAL_Delay(7);
8000224: 2007 movs r0, #7
8000226: f000 fa61 bl 80006ec <HAL_Delay>
for (int period = 0; period < 100; period++) {
800022a: 68fb ldr r3, [r7, #12]
800022c: 3301 adds r3, #1
800022e: 60fb str r3, [r7, #12]
8000230: 68fb ldr r3, [r7, #12]
8000232: 2b63 cmp r3, #99 ; 0x63
8000234: ddf2 ble.n 800021c <main+0x74>
}
for (int period = 99; period >= 0; period--) {
8000236: 2363 movs r3, #99 ; 0x63
8000238: 60bb str r3, [r7, #8]
800023a: e009 b.n 8000250 <main+0xa8>
__HAL_TIM_SET_COMPARE(&htim3, TIM_CHANNEL_2, period);
800023c: 4b16 ldr r3, [pc, #88] ; (8000298 <main+0xf0>)
800023e: 681b ldr r3, [r3, #0]
8000240: 68ba ldr r2, [r7, #8]
8000242: 639a str r2, [r3, #56] ; 0x38
HAL_Delay(7);
8000244: 2007 movs r0, #7
8000246: f000 fa51 bl 80006ec <HAL_Delay>
for (int period = 99; period >= 0; period--) {
800024a: 68bb ldr r3, [r7, #8]
800024c: 3b01 subs r3, #1
800024e: 60bb str r3, [r7, #8]
8000250: 68bb ldr r3, [r7, #8]
8000252: 2b00 cmp r3, #0
8000254: daf2 bge.n 800023c <main+0x94>
}
//循环CH3（红色）先增后减
for (int period = 0; period < 100; period++) {
8000256: 2300 movs r3, #0
8000258: 607b str r3, [r7, #4]
800025a: e009 b.n 8000270 <main+0xc8>
__HAL_TIM_SET_COMPARE(&htim3, TIM_CHANNEL_3, period);
800025c: 4b0e ldr r3, [pc, #56] ; (8000298 <main+0xf0>)
800025e: 681b ldr r3, [r3, #0]
8000260: 687a ldr r2, [r7, #4]
8000262: 63da str r2, [r3, #60] ; 0x3c
HAL_Delay(7);
8000264: 2007 movs r0, #7
8000266: f000 fa41 bl 80006ec <HAL_Delay>
for (int period = 0; period < 100; period++) {
800026a: 687b ldr r3, [r7, #4]
800026c: 3301 adds r3, #1
800026e: 607b str r3, [r7, #4]
8000270: 687b ldr r3, [r7, #4]
8000272: 2b63 cmp r3, #99 ; 0x63
8000274: ddf2 ble.n 800025c <main+0xb4>
}
for (int period = 99; period >= 0; period--) {
8000276: 2363 movs r3, #99 ; 0x63
8000278: 603b str r3, [r7, #0]
800027a: e009 b.n 8000290 <main+0xe8>
__HAL_TIM_SET_COMPARE(&htim3, TIM_CHANNEL_3, period);
800027c: 4b06 ldr r3, [pc, #24] ; (8000298 <main+0xf0>)
800027e: 681b ldr r3, [r3, #0]
8000280: 683a ldr r2, [r7, #0]
8000282: 63da str r2, [r3, #60] ; 0x3c
HAL_Delay(7);
8000284: 2007 movs r0, #7
8000286: f000 fa31 bl 80006ec <HAL_Delay>
for (int period = 99; period >= 0; period--) {
800028a: 683b ldr r3, [r7, #0]
800028c: 3b01 subs r3, #1
800028e: 603b str r3, [r7, #0]
8000290: 683b ldr r3, [r7, #0]
8000292: 2b00 cmp r3, #0
8000294: daf2 bge.n 800027c <main+0xd4>
for (int period = 0; period < 100; period++) {
8000296: e79e b.n 80001d6 <main+0x2e>
8000298: 20000028 .word 0x20000028
0800029c <SystemClock_Config>:
/**
* @brief System Clock Configuration
* @retval None
*/
void SystemClock_Config(void) {
800029c: b580 push {r7, lr}
800029e: b090 sub sp, #64 ; 0x40
80002a0: af00 add r7, sp, #0
RCC_OscInitTypeDef RCC_OscInitStruct = { 0 };
80002a2: f107 0318 add.w r3, r7, #24
80002a6: 2228 movs r2, #40 ; 0x28
80002a8: 2100 movs r1, #0
80002aa: 4618 mov r0, r3
80002ac: f001 fe84 bl 8001fb8 <memset>
RCC_ClkInitTypeDef RCC_ClkInitStruct = { 0 };
80002b0: 1d3b adds r3, r7, #4
80002b2: 2200 movs r2, #0
80002b4: 601a str r2, [r3, #0]
80002b6: 605a str r2, [r3, #4]
80002b8: 609a str r2, [r3, #8]
80002ba: 60da str r2, [r3, #12]
80002bc: 611a str r2, [r3, #16]
/** Initializes the RCC Oscillators according to the specified parameters
* in the RCC_OscInitTypeDef structure.
*/
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
80002be: 2301 movs r3, #1
80002c0: 61bb str r3, [r7, #24]
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
80002c2: f44f 3380 mov.w r3, #65536 ; 0x10000
80002c6: 61fb str r3, [r7, #28]
RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV1;
80002c8: 2300 movs r3, #0
80002ca: 623b str r3, [r7, #32]
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
80002cc: 2301 movs r3, #1
80002ce: 62bb str r3, [r7, #40] ; 0x28
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
80002d0: 2302 movs r3, #2
80002d2: 637b str r3, [r7, #52] ; 0x34
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
80002d4: f44f 3380 mov.w r3, #65536 ; 0x10000
80002d8: 63bb str r3, [r7, #56] ; 0x38
RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9;
80002da: f44f 13e0 mov.w r3, #1835008 ; 0x1c0000
80002de: 63fb str r3, [r7, #60] ; 0x3c
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
80002e0: f107 0318 add.w r3, r7, #24
80002e4: 4618 mov r0, r3
80002e6: f000 fc8d bl 8000c04 <HAL_RCC_OscConfig>
80002ea: 4603 mov r3, r0
80002ec: 2b00 cmp r3, #0
80002ee: d001 beq.n 80002f4 <SystemClock_Config+0x58>
Error_Handler();
80002f0: f000 f819 bl 8000326 <Error_Handler>
}
/** Initializes the CPU, AHB and APB buses clocks
*/
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
80002f4: 230f movs r3, #15
80002f6: 607b str r3, [r7, #4]
| RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
80002f8: 2302 movs r3, #2
80002fa: 60bb str r3, [r7, #8]
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
80002fc: 2300 movs r3, #0
80002fe: 60fb str r3, [r7, #12]
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
8000300: f44f 6380 mov.w r3, #1024 ; 0x400
8000304: 613b str r3, [r7, #16]
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
8000306: 2300 movs r3, #0
8000308: 617b str r3, [r7, #20]
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) {
800030a: 1d3b adds r3, r7, #4
800030c: 2102 movs r1, #2
800030e: 4618 mov r0, r3
8000310: f000 fefa bl 8001108 <HAL_RCC_ClockConfig>
8000314: 4603 mov r3, r0
8000316: 2b00 cmp r3, #0
8000318: d001 beq.n 800031e <SystemClock_Config+0x82>
Error_Handler();
800031a: f000 f804 bl 8000326 <Error_Handler>
}
}
800031e: bf00 nop
8000320: 3740 adds r7, #64 ; 0x40
8000322: 46bd mov sp, r7
8000324: bd80 pop {r7, pc}
08000326 <Error_Handler>:
/**
* @brief This function is executed in case of error occurrence.
* @retval None
*/
void Error_Handler(void) {
8000326: b480 push {r7}
8000328: af00 add r7, sp, #0
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__STATIC_FORCEINLINE void __disable_irq(void)
{
__ASM volatile ("cpsid i" : : : "memory");
800032a: b672 cpsid i
}
800032c: bf00 nop
/* USER CODE BEGIN Error_Handler_Debug */
/* User can add his own implementation to report the HAL error return state */
__disable_irq();
while (1) {
800032e: e7fe b.n 800032e <Error_Handler+0x8>
08000330 <HAL_MspInit>:
/* USER CODE END 0 */
/**
* Initializes the Global MSP.
*/
void HAL_MspInit(void)
{
8000330: b480 push {r7}
8000332: b085 sub sp, #20
8000334: af00 add r7, sp, #0
/* USER CODE BEGIN MspInit 0 */
/* USER CODE END MspInit 0 */
__HAL_RCC_AFIO_CLK_ENABLE();
8000336: 4b15 ldr r3, [pc, #84] ; (800038c <HAL_MspInit+0x5c>)
8000338: 699b ldr r3, [r3, #24]
800033a: 4a14 ldr r2, [pc, #80] ; (800038c <HAL_MspInit+0x5c>)
800033c: f043 0301 orr.w r3, r3, #1
8000340: 6193 str r3, [r2, #24]
8000342: 4b12 ldr r3, [pc, #72] ; (800038c <HAL_MspInit+0x5c>)
8000344: 699b ldr r3, [r3, #24]
8000346: f003 0301 and.w r3, r3, #1
800034a: 60bb str r3, [r7, #8]
800034c: 68bb ldr r3, [r7, #8]
__HAL_RCC_PWR_CLK_ENABLE();
800034e: 4b0f ldr r3, [pc, #60] ; (800038c <HAL_MspInit+0x5c>)
8000350: 69db ldr r3, [r3, #28]
8000352: 4a0e ldr r2, [pc, #56] ; (800038c <HAL_MspInit+0x5c>)
8000354: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
8000358: 61d3 str r3, [r2, #28]
800035a: 4b0c ldr r3, [pc, #48] ; (800038c <HAL_MspInit+0x5c>)
800035c: 69db ldr r3, [r3, #28]
800035e: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
8000362: 607b str r3, [r7, #4]
8000364: 687b ldr r3, [r7, #4]
/* System interrupt init*/
/** NOJTAG: JTAG-DP Disabled and SW-DP Enabled
*/
__HAL_AFIO_REMAP_SWJ_NOJTAG();
8000366: 4b0a ldr r3, [pc, #40] ; (8000390 <HAL_MspInit+0x60>)
8000368: 685b ldr r3, [r3, #4]
800036a: 60fb str r3, [r7, #12]
800036c: 68fb ldr r3, [r7, #12]
800036e: f023 63e0 bic.w r3, r3, #117440512 ; 0x7000000
8000372: 60fb str r3, [r7, #12]
8000374: 68fb ldr r3, [r7, #12]
8000376: f043 7300 orr.w r3, r3, #33554432 ; 0x2000000
800037a: 60fb str r3, [r7, #12]
800037c: 4a04 ldr r2, [pc, #16] ; (8000390 <HAL_MspInit+0x60>)
800037e: 68fb ldr r3, [r7, #12]
8000380: 6053 str r3, [r2, #4]
/* USER CODE BEGIN MspInit 1 */
/* USER CODE END MspInit 1 */
}
8000382: bf00 nop
8000384: 3714 adds r7, #20
8000386: 46bd mov sp, r7
8000388: bc80 pop {r7}
800038a: 4770 bx lr
800038c: 40021000 .word 0x40021000
8000390: 40010000 .word 0x40010000
08000394 <NMI_Handler>:
/******************************************************************************/
/**
* @brief This function handles Non maskable interrupt.
*/
void NMI_Handler(void)
{
8000394: b480 push {r7}
8000396: af00 add r7, sp, #0
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
/* USER CODE END NonMaskableInt_IRQn 0 */
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
while (1)
8000398: e7fe b.n 8000398 <NMI_Handler+0x4>
0800039a <HardFault_Handler>:
/**
* @brief This function handles Hard fault interrupt.
*/
void HardFault_Handler(void)
{
800039a: b480 push {r7}
800039c: af00 add r7, sp, #0
/* USER CODE BEGIN HardFault_IRQn 0 */
/* USER CODE END HardFault_IRQn 0 */
while (1)
800039e: e7fe b.n 800039e <HardFault_Handler+0x4>
080003a0 <MemManage_Handler>:
/**
* @brief This function handles Memory management fault.
*/
void MemManage_Handler(void)
{
80003a0: b480 push {r7}
80003a2: af00 add r7, sp, #0
/* USER CODE BEGIN MemoryManagement_IRQn 0 */
/* USER CODE END MemoryManagement_IRQn 0 */
while (1)
80003a4: e7fe b.n 80003a4 <MemManage_Handler+0x4>
080003a6 <BusFault_Handler>:
/**
* @brief This function handles Prefetch fault, memory access fault.
*/
void BusFault_Handler(void)
{
80003a6: b480 push {r7}
80003a8: af00 add r7, sp, #0
/* USER CODE BEGIN BusFault_IRQn 0 */
/* USER CODE END BusFault_IRQn 0 */
while (1)
80003aa: e7fe b.n 80003aa <BusFault_Handler+0x4>
080003ac <UsageFault_Handler>:
/**
* @brief This function handles Undefined instruction or illegal state.
*/
void UsageFault_Handler(void)
{
80003ac: b480 push {r7}
80003ae: af00 add r7, sp, #0
/* USER CODE BEGIN UsageFault_IRQn 0 */
/* USER CODE END UsageFault_IRQn 0 */
while (1)
80003b0: e7fe b.n 80003b0 <UsageFault_Handler+0x4>
080003b2 <SVC_Handler>:
/**
* @brief This function handles System service call via SWI instruction.
*/
void SVC_Handler(void)
{
80003b2: b480 push {r7}
80003b4: af00 add r7, sp, #0
/* USER CODE END SVCall_IRQn 0 */
/* USER CODE BEGIN SVCall_IRQn 1 */
/* USER CODE END SVCall_IRQn 1 */
}
80003b6: bf00 nop
80003b8: 46bd mov sp, r7
80003ba: bc80 pop {r7}
80003bc: 4770 bx lr
080003be <DebugMon_Handler>:
/**
* @brief This function handles Debug monitor.
*/
void DebugMon_Handler(void)
{
80003be: b480 push {r7}
80003c0: af00 add r7, sp, #0
/* USER CODE END DebugMonitor_IRQn 0 */
/* USER CODE BEGIN DebugMonitor_IRQn 1 */
/* USER CODE END DebugMonitor_IRQn 1 */
}
80003c2: bf00 nop
80003c4: 46bd mov sp, r7
80003c6: bc80 pop {r7}
80003c8: 4770 bx lr
080003ca <PendSV_Handler>:
/**
* @brief This function handles Pendable request for system service.
*/
void PendSV_Handler(void)
{
80003ca: b480 push {r7}
80003cc: af00 add r7, sp, #0
/* USER CODE END PendSV_IRQn 0 */
/* USER CODE BEGIN PendSV_IRQn 1 */
/* USER CODE END PendSV_IRQn 1 */
}
80003ce: bf00 nop
80003d0: 46bd mov sp, r7
80003d2: bc80 pop {r7}
80003d4: 4770 bx lr
080003d6 <SysTick_Handler>:
/**
* @brief This function handles System tick timer.
*/
void SysTick_Handler(void)
{
80003d6: b580 push {r7, lr}
80003d8: af00 add r7, sp, #0
/* USER CODE BEGIN SysTick_IRQn 0 */
/* USER CODE END SysTick_IRQn 0 */
HAL_IncTick();
80003da: f000 f96b bl 80006b4 <HAL_IncTick>
/* USER CODE BEGIN SysTick_IRQn 1 */
/* USER CODE END SysTick_IRQn 1 */
}
80003de: bf00 nop
80003e0: bd80 pop {r7, pc}
080003e2 <SystemInit>:
* @note This function should be used only after reset.
* @param None
* @retval None
*/
void SystemInit (void)
{
80003e2: b480 push {r7}
80003e4: af00 add r7, sp, #0
/* Configure the Vector Table location -------------------------------------*/
#if defined(USER_VECT_TAB_ADDRESS)
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
#endif /* USER_VECT_TAB_ADDRESS */
}
80003e6: bf00 nop
80003e8: 46bd mov sp, r7
80003ea: bc80 pop {r7}
80003ec: 4770 bx lr
...
080003f0 <MX_TIM3_Init>:
TIM_HandleTypeDef htim3;
/* TIM3 init function */
void MX_TIM3_Init(void)
{
80003f0: b580 push {r7, lr}
80003f2: b08e sub sp, #56 ; 0x38
80003f4: af00 add r7, sp, #0
/* USER CODE BEGIN TIM3_Init 0 */
/* USER CODE END TIM3_Init 0 */
TIM_ClockConfigTypeDef sClockSourceConfig = {0};
80003f6: f107 0328 add.w r3, r7, #40 ; 0x28
80003fa: 2200 movs r2, #0
80003fc: 601a str r2, [r3, #0]
80003fe: 605a str r2, [r3, #4]
8000400: 609a str r2, [r3, #8]
8000402: 60da str r2, [r3, #12]
TIM_MasterConfigTypeDef sMasterConfig = {0};
8000404: f107 0320 add.w r3, r7, #32
8000408: 2200 movs r2, #0
800040a: 601a str r2, [r3, #0]
800040c: 605a str r2, [r3, #4]
TIM_OC_InitTypeDef sConfigOC = {0};
800040e: 1d3b adds r3, r7, #4
8000410: 2200 movs r2, #0
8000412: 601a str r2, [r3, #0]
8000414: 605a str r2, [r3, #4]
8000416: 609a str r2, [r3, #8]
8000418: 60da str r2, [r3, #12]
800041a: 611a str r2, [r3, #16]
800041c: 615a str r2, [r3, #20]
800041e: 619a str r2, [r3, #24]
/* USER CODE BEGIN TIM3_Init 1 */
/* USER CODE END TIM3_Init 1 */
htim3.Instance = TIM3;
8000420: 4b37 ldr r3, [pc, #220] ; (8000500 <MX_TIM3_Init+0x110>)
8000422: 4a38 ldr r2, [pc, #224] ; (8000504 <MX_TIM3_Init+0x114>)
8000424: 601a str r2, [r3, #0]
htim3.Init.Prescaler = 72-1;
8000426: 4b36 ldr r3, [pc, #216] ; (8000500 <MX_TIM3_Init+0x110>)
8000428: 2247 movs r2, #71 ; 0x47
800042a: 605a str r2, [r3, #4]
htim3.Init.CounterMode = TIM_COUNTERMODE_UP;
800042c: 4b34 ldr r3, [pc, #208] ; (8000500 <MX_TIM3_Init+0x110>)
800042e: 2200 movs r2, #0
8000430: 609a str r2, [r3, #8]
htim3.Init.Period = 100-1;
8000432: 4b33 ldr r3, [pc, #204] ; (8000500 <MX_TIM3_Init+0x110>)
8000434: 2263 movs r2, #99 ; 0x63
8000436: 60da str r2, [r3, #12]
htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
8000438: 4b31 ldr r3, [pc, #196] ; (8000500 <MX_TIM3_Init+0x110>)
800043a: 2200 movs r2, #0
800043c: 611a str r2, [r3, #16]
htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
800043e: 4b30 ldr r3, [pc, #192] ; (8000500 <MX_TIM3_Init+0x110>)
8000440: 2200 movs r2, #0
8000442: 619a str r2, [r3, #24]
if (HAL_TIM_Base_Init(&htim3) != HAL_OK)
8000444: 482e ldr r0, [pc, #184] ; (8000500 <MX_TIM3_Init+0x110>)
8000446: f000 ffc5 bl 80013d4 <HAL_TIM_Base_Init>
800044a: 4603 mov r3, r0
800044c: 2b00 cmp r3, #0
800044e: d001 beq.n 8000454 <MX_TIM3_Init+0x64>
{
Error_Handler();
8000450: f7ff ff69 bl 8000326 <Error_Handler>
}
sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
8000454: f44f 5380 mov.w r3, #4096 ; 0x1000
8000458: 62bb str r3, [r7, #40] ; 0x28
if (HAL_TIM_ConfigClockSource(&htim3, &sClockSourceConfig) != HAL_OK)
800045a: f107 0328 add.w r3, r7, #40 ; 0x28
800045e: 4619 mov r1, r3
8000460: 4827 ldr r0, [pc, #156] ; (8000500 <MX_TIM3_Init+0x110>)
8000462: f001 f9bf bl 80017e4 <HAL_TIM_ConfigClockSource>
8000466: 4603 mov r3, r0
8000468: 2b00 cmp r3, #0
800046a: d001 beq.n 8000470 <MX_TIM3_Init+0x80>
{
Error_Handler();
800046c: f7ff ff5b bl 8000326 <Error_Handler>
}
if (HAL_TIM_PWM_Init(&htim3) != HAL_OK)
8000470: 4823 ldr r0, [pc, #140] ; (8000500 <MX_TIM3_Init+0x110>)
8000472: f000 fffe bl 8001472 <HAL_TIM_PWM_Init>
8000476: 4603 mov r3, r0
8000478: 2b00 cmp r3, #0
800047a: d001 beq.n 8000480 <MX_TIM3_Init+0x90>
{
Error_Handler();
800047c: f7ff ff53 bl 8000326 <Error_Handler>
}
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
8000480: 2300 movs r3, #0
8000482: 623b str r3, [r7, #32]
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
8000484: 2300 movs r3, #0
8000486: 627b str r3, [r7, #36] ; 0x24
if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK)
8000488: f107 0320 add.w r3, r7, #32
800048c: 4619 mov r1, r3
800048e: 481c ldr r0, [pc, #112] ; (8000500 <MX_TIM3_Init+0x110>)
8000490: f001 fd10 bl 8001eb4 <HAL_TIMEx_MasterConfigSynchronization>
8000494: 4603 mov r3, r0
8000496: 2b00 cmp r3, #0
8000498: d001 beq.n 800049e <MX_TIM3_Init+0xae>
{
Error_Handler();
800049a: f7ff ff44 bl 8000326 <Error_Handler>
}
sConfigOC.OCMode = TIM_OCMODE_PWM1;
800049e: 2360 movs r3, #96 ; 0x60
80004a0: 607b str r3, [r7, #4]
sConfigOC.Pulse = 0;
80004a2: 2300 movs r3, #0
80004a4: 60bb str r3, [r7, #8]
sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
80004a6: 2300 movs r3, #0
80004a8: 60fb str r3, [r7, #12]
sConfigOC.OCFastMode = TIM_OCFAST_DISABLE;
80004aa: 2300 movs r3, #0
80004ac: 617b str r3, [r7, #20]
if (HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_1) != HAL_OK)
80004ae: 1d3b adds r3, r7, #4
80004b0: 2200 movs r2, #0
80004b2: 4619 mov r1, r3
80004b4: 4812 ldr r0, [pc, #72] ; (8000500 <MX_TIM3_Init+0x110>)
80004b6: f001 f8d7 bl 8001668 <HAL_TIM_PWM_ConfigChannel>
80004ba: 4603 mov r3, r0
80004bc: 2b00 cmp r3, #0
80004be: d001 beq.n 80004c4 <MX_TIM3_Init+0xd4>
{
Error_Handler();
80004c0: f7ff ff31 bl 8000326 <Error_Handler>
}
if (HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_2) != HAL_OK)
80004c4: 1d3b adds r3, r7, #4
80004c6: 2204 movs r2, #4
80004c8: 4619 mov r1, r3
80004ca: 480d ldr r0, [pc, #52] ; (8000500 <MX_TIM3_Init+0x110>)
80004cc: f001 f8cc bl 8001668 <HAL_TIM_PWM_ConfigChannel>
80004d0: 4603 mov r3, r0
80004d2: 2b00 cmp r3, #0
80004d4: d001 beq.n 80004da <MX_TIM3_Init+0xea>
{
Error_Handler();
80004d6: f7ff ff26 bl 8000326 <Error_Handler>
}
if (HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_3) != HAL_OK)
80004da: 1d3b adds r3, r7, #4
80004dc: 2208 movs r2, #8
80004de: 4619 mov r1, r3
80004e0: 4807 ldr r0, [pc, #28] ; (8000500 <MX_TIM3_Init+0x110>)
80004e2: f001 f8c1 bl 8001668 <HAL_TIM_PWM_ConfigChannel>
80004e6: 4603 mov r3, r0
80004e8: 2b00 cmp r3, #0
80004ea: d001 beq.n 80004f0 <MX_TIM3_Init+0x100>
{
Error_Handler();
80004ec: f7ff ff1b bl 8000326 <Error_Handler>
}
/* USER CODE BEGIN TIM3_Init 2 */
/* USER CODE END TIM3_Init 2 */
HAL_TIM_MspPostInit(&htim3);
80004f0: 4803 ldr r0, [pc, #12] ; (8000500 <MX_TIM3_Init+0x110>)
80004f2: f000 f827 bl 8000544 <HAL_TIM_MspPostInit>
}
80004f6: bf00 nop
80004f8: 3738 adds r7, #56 ; 0x38
80004fa: 46bd mov sp, r7
80004fc: bd80 pop {r7, pc}
80004fe: bf00 nop
8000500: 20000028 .word 0x20000028
8000504: 40000400 .word 0x40000400
08000508 <HAL_TIM_Base_MspInit>:
void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* tim_baseHandle)
{
8000508: b480 push {r7}
800050a: b085 sub sp, #20
800050c: af00 add r7, sp, #0
800050e: 6078 str r0, [r7, #4]
if(tim_baseHandle->Instance==TIM3)
8000510: 687b ldr r3, [r7, #4]
8000512: 681b ldr r3, [r3, #0]
8000514: 4a09 ldr r2, [pc, #36] ; (800053c <HAL_TIM_Base_MspInit+0x34>)
8000516: 4293 cmp r3, r2
8000518: d10b bne.n 8000532 <HAL_TIM_Base_MspInit+0x2a>
{
/* USER CODE BEGIN TIM3_MspInit 0 */
/* USER CODE END TIM3_MspInit 0 */
/* TIM3 clock enable */
__HAL_RCC_TIM3_CLK_ENABLE();
800051a: 4b09 ldr r3, [pc, #36] ; (8000540 <HAL_TIM_Base_MspInit+0x38>)
800051c: 69db ldr r3, [r3, #28]
800051e: 4a08 ldr r2, [pc, #32] ; (8000540 <HAL_TIM_Base_MspInit+0x38>)
8000520: f043 0302 orr.w r3, r3, #2
8000524: 61d3 str r3, [r2, #28]
8000526: 4b06 ldr r3, [pc, #24] ; (8000540 <HAL_TIM_Base_MspInit+0x38>)
8000528: 69db ldr r3, [r3, #28]
800052a: f003 0302 and.w r3, r3, #2
800052e: 60fb str r3, [r7, #12]
8000530: 68fb ldr r3, [r7, #12]
/* USER CODE BEGIN TIM3_MspInit 1 */
/* USER CODE END TIM3_MspInit 1 */
}
}
8000532: bf00 nop
8000534: 3714 adds r7, #20
8000536: 46bd mov sp, r7
8000538: bc80 pop {r7}
800053a: 4770 bx lr
800053c: 40000400 .word 0x40000400
8000540: 40021000 .word 0x40021000
08000544 <HAL_TIM_MspPostInit>:
void HAL_TIM_MspPostInit(TIM_HandleTypeDef* timHandle)
{
8000544: b580 push {r7, lr}
8000546: b088 sub sp, #32
8000548: af00 add r7, sp, #0
800054a: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
800054c: f107 0310 add.w r3, r7, #16
8000550: 2200 movs r2, #0
8000552: 601a str r2, [r3, #0]
8000554: 605a str r2, [r3, #4]
8000556: 609a str r2, [r3, #8]
8000558: 60da str r2, [r3, #12]
if(timHandle->Instance==TIM3)
800055a: 687b ldr r3, [r7, #4]
800055c: 681b ldr r3, [r3, #0]
800055e: 4a1b ldr r2, [pc, #108] ; (80005cc <HAL_TIM_MspPostInit+0x88>)
8000560: 4293 cmp r3, r2
8000562: d12f bne.n 80005c4 <HAL_TIM_MspPostInit+0x80>
{
/* USER CODE BEGIN TIM3_MspPostInit 0 */
/* USER CODE END TIM3_MspPostInit 0 */
__HAL_RCC_GPIOA_CLK_ENABLE();
8000564: 4b1a ldr r3, [pc, #104] ; (80005d0 <HAL_TIM_MspPostInit+0x8c>)
8000566: 699b ldr r3, [r3, #24]
8000568: 4a19 ldr r2, [pc, #100] ; (80005d0 <HAL_TIM_MspPostInit+0x8c>)
800056a: f043 0304 orr.w r3, r3, #4
800056e: 6193 str r3, [r2, #24]
8000570: 4b17 ldr r3, [pc, #92] ; (80005d0 <HAL_TIM_MspPostInit+0x8c>)
8000572: 699b ldr r3, [r3, #24]
8000574: f003 0304 and.w r3, r3, #4
8000578: 60fb str r3, [r7, #12]
800057a: 68fb ldr r3, [r7, #12]
__HAL_RCC_GPIOB_CLK_ENABLE();
800057c: 4b14 ldr r3, [pc, #80] ; (80005d0 <HAL_TIM_MspPostInit+0x8c>)
800057e: 699b ldr r3, [r3, #24]
8000580: 4a13 ldr r2, [pc, #76] ; (80005d0 <HAL_TIM_MspPostInit+0x8c>)
8000582: f043 0308 orr.w r3, r3, #8
8000586: 6193 str r3, [r2, #24]
8000588: 4b11 ldr r3, [pc, #68] ; (80005d0 <HAL_TIM_MspPostInit+0x8c>)
800058a: 699b ldr r3, [r3, #24]
800058c: f003 0308 and.w r3, r3, #8
8000590: 60bb str r3, [r7, #8]
8000592: 68bb ldr r3, [r7, #8]
/**TIM3 GPIO Configuration
PA6 ------> TIM3_CH1
PA7 ------> TIM3_CH2
PB0 ------> TIM3_CH3
*/
GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7;
8000594: 23c0 movs r3, #192 ; 0xc0
8000596: 613b str r3, [r7, #16]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000598: 2302 movs r3, #2
800059a: 617b str r3, [r7, #20]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
800059c: 2302 movs r3, #2
800059e: 61fb str r3, [r7, #28]
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
80005a0: f107 0310 add.w r3, r7, #16
80005a4: 4619 mov r1, r3
80005a6: 480b ldr r0, [pc, #44] ; (80005d4 <HAL_TIM_MspPostInit+0x90>)
80005a8: f000 f9a8 bl 80008fc <HAL_GPIO_Init>
GPIO_InitStruct.Pin = GPIO_PIN_0;
80005ac: 2301 movs r3, #1
80005ae: 613b str r3, [r7, #16]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
80005b0: 2302 movs r3, #2
80005b2: 617b str r3, [r7, #20]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
80005b4: 2302 movs r3, #2
80005b6: 61fb str r3, [r7, #28]
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
80005b8: f107 0310 add.w r3, r7, #16
80005bc: 4619 mov r1, r3
80005be: 4806 ldr r0, [pc, #24] ; (80005d8 <HAL_TIM_MspPostInit+0x94>)
80005c0: f000 f99c bl 80008fc <HAL_GPIO_Init>
/* USER CODE BEGIN TIM3_MspPostInit 1 */
/* USER CODE END TIM3_MspPostInit 1 */
}
}
80005c4: bf00 nop
80005c6: 3720 adds r7, #32
80005c8: 46bd mov sp, r7
80005ca: bd80 pop {r7, pc}
80005cc: 40000400 .word 0x40000400
80005d0: 40021000 .word 0x40021000
80005d4: 40010800 .word 0x40010800
80005d8: 40010c00 .word 0x40010c00
080005dc <Reset_Handler>:
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
80005dc: 480c ldr r0, [pc, #48] ; (8000610 <LoopFillZerobss+0x12>)
ldr r1, =_edata
80005de: 490d ldr r1, [pc, #52] ; (8000614 <LoopFillZerobss+0x16>)
ldr r2, =_sidata
80005e0: 4a0d ldr r2, [pc, #52] ; (8000618 <LoopFillZerobss+0x1a>)
movs r3, #0
80005e2: 2300 movs r3, #0
b LoopCopyDataInit
80005e4: e002 b.n 80005ec <LoopCopyDataInit>
080005e6 <CopyDataInit>:
CopyDataInit:
ldr r4, [r2, r3]
80005e6: 58d4 ldr r4, [r2, r3]
str r4, [r0, r3]
80005e8: 50c4 str r4, [r0, r3]
adds r3, r3, #4
80005ea: 3304 adds r3, #4
080005ec <LoopCopyDataInit>:
LoopCopyDataInit:
adds r4, r0, r3
80005ec: 18c4 adds r4, r0, r3
cmp r4, r1
80005ee: 428c cmp r4, r1
bcc CopyDataInit
80005f0: d3f9 bcc.n 80005e6 <CopyDataInit>
/* Zero fill the bss segment. */
ldr r2, =_sbss
80005f2: 4a0a ldr r2, [pc, #40] ; (800061c <LoopFillZerobss+0x1e>)
ldr r4, =_ebss
80005f4: 4c0a ldr r4, [pc, #40] ; (8000620 <LoopFillZerobss+0x22>)
movs r3, #0
80005f6: 2300 movs r3, #0
b LoopFillZerobss
80005f8: e001 b.n 80005fe <LoopFillZerobss>
080005fa <FillZerobss>:
FillZerobss:
str r3, [r2]
80005fa: 6013 str r3, [r2, #0]
adds r2, r2, #4
80005fc: 3204 adds r2, #4
080005fe <LoopFillZerobss>:
LoopFillZerobss:
cmp r2, r4
80005fe: 42a2 cmp r2, r4
bcc FillZerobss
8000600: d3fb bcc.n 80005fa <FillZerobss>
/* Call the clock system intitialization function.*/
bl SystemInit
8000602: f7ff feee bl 80003e2 <SystemInit>
/* Call static constructors */
bl __libc_init_array
8000606: f001 fcb3 bl 8001f70 <__libc_init_array>
/* Call the application's entry point.*/
bl main
800060a: f7ff fdcd bl 80001a8 <main>
bx lr
800060e: 4770 bx lr
ldr r0, =_sdata
8000610: 20000000 .word 0x20000000
ldr r1, =_edata
8000614: 2000000c .word 0x2000000c
ldr r2, =_sidata
8000618: 08002008 .word 0x08002008
ldr r2, =_sbss
800061c: 2000000c .word 0x2000000c
ldr r4, =_ebss
8000620: 20000074 .word 0x20000074
08000624 <ADC1_2_IRQHandler>:
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
8000624: e7fe b.n 8000624 <ADC1_2_IRQHandler>
...
08000628 <HAL_Init>:
* need to ensure that the SysTick time base is always set to 1 millisecond
* to have correct HAL operation.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_Init(void)
{
8000628: b580 push {r7, lr}
800062a: af00 add r7, sp, #0
defined(STM32F102x6) || defined(STM32F102xB) || \
defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || \
defined(STM32F105xC) || defined(STM32F107xC)
/* Prefetch buffer is not available on value line devices */
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
800062c: 4b08 ldr r3, [pc, #32] ; (8000650 <HAL_Init+0x28>)
800062e: 681b ldr r3, [r3, #0]
8000630: 4a07 ldr r2, [pc, #28] ; (8000650 <HAL_Init+0x28>)
8000632: f043 0310 orr.w r3, r3, #16
8000636: 6013 str r3, [r2, #0]
#endif
#endif /* PREFETCH_ENABLE */
/* Set Interrupt Group Priority */
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
8000638: 2003 movs r0, #3
800063a: f000 f92b bl 8000894 <HAL_NVIC_SetPriorityGrouping>
/* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
HAL_InitTick(TICK_INT_PRIORITY);
800063e: 200f movs r0, #15
8000640: f000 f808 bl 8000654 <HAL_InitTick>
/* Init the low level hardware */
HAL_MspInit();
8000644: f7ff fe74 bl 8000330 <HAL_MspInit>
/* Return function status */
return HAL_OK;
8000648: 2300 movs r3, #0
}
800064a: 4618 mov r0, r3
800064c: bd80 pop {r7, pc}
800064e: bf00 nop
8000650: 40022000 .word 0x40022000
08000654 <HAL_InitTick>:
* implementation in user file.
* @param TickPriority Tick interrupt priority.
* @retval HAL status
*/
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
8000654: b580 push {r7, lr}
8000656: b082 sub sp, #8
8000658: af00 add r7, sp, #0
800065a: 6078 str r0, [r7, #4]
/* Configure the SysTick to have interrupt in 1ms time basis*/
if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U)
800065c: 4b12 ldr r3, [pc, #72] ; (80006a8 <HAL_InitTick+0x54>)
800065e: 681a ldr r2, [r3, #0]
8000660: 4b12 ldr r3, [pc, #72] ; (80006ac <HAL_InitTick+0x58>)
8000662: 781b ldrb r3, [r3, #0]
8000664: 4619 mov r1, r3
8000666: f44f 737a mov.w r3, #1000 ; 0x3e8
800066a: fbb3 f3f1 udiv r3, r3, r1
800066e: fbb2 f3f3 udiv r3, r2, r3
8000672: 4618 mov r0, r3
8000674: f000 f935 bl 80008e2 <HAL_SYSTICK_Config>
8000678: 4603 mov r3, r0
800067a: 2b00 cmp r3, #0
800067c: d001 beq.n 8000682 <HAL_InitTick+0x2e>
{
return HAL_ERROR;
800067e: 2301 movs r3, #1
8000680: e00e b.n 80006a0 <HAL_InitTick+0x4c>
}
/* Configure the SysTick IRQ priority */
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
8000682: 687b ldr r3, [r7, #4]
8000684: 2b0f cmp r3, #15
8000686: d80a bhi.n 800069e <HAL_InitTick+0x4a>
{
HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
8000688: 2200 movs r2, #0
800068a: 6879 ldr r1, [r7, #4]
800068c: f04f 30ff mov.w r0, #4294967295
8000690: f000 f90b bl 80008aa <HAL_NVIC_SetPriority>
uwTickPrio = TickPriority;
8000694: 4a06 ldr r2, [pc, #24] ; (80006b0 <HAL_InitTick+0x5c>)
8000696: 687b ldr r3, [r7, #4]
8000698: 6013 str r3, [r2, #0]
{
return HAL_ERROR;
}
/* Return function status */
return HAL_OK;
800069a: 2300 movs r3, #0
800069c: e000 b.n 80006a0 <HAL_InitTick+0x4c>
return HAL_ERROR;
800069e: 2301 movs r3, #1
}
80006a0: 4618 mov r0, r3
80006a2: 3708 adds r7, #8
80006a4: 46bd mov sp, r7
80006a6: bd80 pop {r7, pc}
80006a8: 20000000 .word 0x20000000
80006ac: 20000008 .word 0x20000008
80006b0: 20000004 .word 0x20000004
080006b4 <HAL_IncTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval None
*/
__weak void HAL_IncTick(void)
{
80006b4: b480 push {r7}
80006b6: af00 add r7, sp, #0
uwTick += uwTickFreq;
80006b8: 4b05 ldr r3, [pc, #20] ; (80006d0 <HAL_IncTick+0x1c>)
80006ba: 781b ldrb r3, [r3, #0]
80006bc: 461a mov r2, r3
80006be: 4b05 ldr r3, [pc, #20] ; (80006d4 <HAL_IncTick+0x20>)
80006c0: 681b ldr r3, [r3, #0]
80006c2: 4413 add r3, r2
80006c4: 4a03 ldr r2, [pc, #12] ; (80006d4 <HAL_IncTick+0x20>)
80006c6: 6013 str r3, [r2, #0]
}
80006c8: bf00 nop
80006ca: 46bd mov sp, r7
80006cc: bc80 pop {r7}
80006ce: 4770 bx lr
80006d0: 20000008 .word 0x20000008
80006d4: 20000070 .word 0x20000070
080006d8 <HAL_GetTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval tick value
*/
__weak uint32_t HAL_GetTick(void)
{
80006d8: b480 push {r7}
80006da: af00 add r7, sp, #0
return uwTick;
80006dc: 4b02 ldr r3, [pc, #8] ; (80006e8 <HAL_GetTick+0x10>)
80006de: 681b ldr r3, [r3, #0]
}
80006e0: 4618 mov r0, r3
80006e2: 46bd mov sp, r7
80006e4: bc80 pop {r7}
80006e6: 4770 bx lr
80006e8: 20000070 .word 0x20000070
080006ec <HAL_Delay>:
* implementations in user file.
* @param Delay specifies the delay time length, in milliseconds.
* @retval None
*/
__weak void HAL_Delay(uint32_t Delay)
{
80006ec: b580 push {r7, lr}
80006ee: b084 sub sp, #16
80006f0: af00 add r7, sp, #0
80006f2: 6078 str r0, [r7, #4]
uint32_t tickstart = HAL_GetTick();
80006f4: f7ff fff0 bl 80006d8 <HAL_GetTick>
80006f8: 60b8 str r0, [r7, #8]
uint32_t wait = Delay;
80006fa: 687b ldr r3, [r7, #4]
80006fc: 60fb str r3, [r7, #12]
/* Add a freq to guarantee minimum wait */
if (wait < HAL_MAX_DELAY)
80006fe: 68fb ldr r3, [r7, #12]
8000700: f1b3 3fff cmp.w r3, #4294967295
8000704: d005 beq.n 8000712 <HAL_Delay+0x26>
{
wait += (uint32_t)(uwTickFreq);
8000706: 4b0a ldr r3, [pc, #40] ; (8000730 <HAL_Delay+0x44>)
8000708: 781b ldrb r3, [r3, #0]
800070a: 461a mov r2, r3
800070c: 68fb ldr r3, [r7, #12]
800070e: 4413 add r3, r2
8000710: 60fb str r3, [r7, #12]
}
while ((HAL_GetTick() - tickstart) < wait)
8000712: bf00 nop
8000714: f7ff ffe0 bl 80006d8 <HAL_GetTick>
8000718: 4602 mov r2, r0
800071a: 68bb ldr r3, [r7, #8]
800071c: 1ad3 subs r3, r2, r3
800071e: 68fa ldr r2, [r7, #12]
8000720: 429a cmp r2, r3
8000722: d8f7 bhi.n 8000714 <HAL_Delay+0x28>
{
}
}
8000724: bf00 nop
8000726: bf00 nop
8000728: 3710 adds r7, #16
800072a: 46bd mov sp, r7
800072c: bd80 pop {r7, pc}
800072e: bf00 nop
8000730: 20000008 .word 0x20000008
08000734 <__NVIC_SetPriorityGrouping>:
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Priority grouping field.
*/
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
8000734: b480 push {r7}
8000736: b085 sub sp, #20
8000738: af00 add r7, sp, #0
800073a: 6078 str r0, [r7, #4]
uint32_t reg_value;
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
800073c: 687b ldr r3, [r7, #4]
800073e: f003 0307 and.w r3, r3, #7
8000742: 60fb str r3, [r7, #12]
reg_value = SCB->AIRCR; /* read old register configuration */
8000744: 4b0c ldr r3, [pc, #48] ; (8000778 <__NVIC_SetPriorityGrouping+0x44>)
8000746: 68db ldr r3, [r3, #12]
8000748: 60bb str r3, [r7, #8]
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
800074a: 68ba ldr r2, [r7, #8]
800074c: f64f 03ff movw r3, #63743 ; 0xf8ff
8000750: 4013 ands r3, r2
8000752: 60bb str r3, [r7, #8]
reg_value = (reg_value |
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
(PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
8000754: 68fb ldr r3, [r7, #12]
8000756: 021a lsls r2, r3, #8
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
8000758: 68bb ldr r3, [r7, #8]
800075a: 4313 orrs r3, r2
reg_value = (reg_value |
800075c: f043 63bf orr.w r3, r3, #100139008 ; 0x5f80000
8000760: f443 3300 orr.w r3, r3, #131072 ; 0x20000
8000764: 60bb str r3, [r7, #8]
SCB->AIRCR = reg_value;
8000766: 4a04 ldr r2, [pc, #16] ; (8000778 <__NVIC_SetPriorityGrouping+0x44>)
8000768: 68bb ldr r3, [r7, #8]
800076a: 60d3 str r3, [r2, #12]
}
800076c: bf00 nop
800076e: 3714 adds r7, #20
8000770: 46bd mov sp, r7
8000772: bc80 pop {r7}
8000774: 4770 bx lr
8000776: bf00 nop
8000778: e000ed00 .word 0xe000ed00
0800077c <__NVIC_GetPriorityGrouping>:
\brief Get Priority Grouping
\details Reads the priority grouping field from the NVIC Interrupt Controller.
\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
*/
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
{
800077c: b480 push {r7}
800077e: af00 add r7, sp, #0
return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
8000780: 4b04 ldr r3, [pc, #16] ; (8000794 <__NVIC_GetPriorityGrouping+0x18>)
8000782: 68db ldr r3, [r3, #12]
8000784: 0a1b lsrs r3, r3, #8
8000786: f003 0307 and.w r3, r3, #7
}
800078a: 4618 mov r0, r3
800078c: 46bd mov sp, r7
800078e: bc80 pop {r7}
8000790: 4770 bx lr
8000792: bf00 nop
8000794: e000ed00 .word 0xe000ed00
08000798 <__NVIC_SetPriority>:
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
8000798: b480 push {r7}
800079a: b083 sub sp, #12
800079c: af00 add r7, sp, #0
800079e: 4603 mov r3, r0
80007a0: 6039 str r1, [r7, #0]
80007a2: 71fb strb r3, [r7, #7]
if ((int32_t)(IRQn) >= 0)
80007a4: f997 3007 ldrsb.w r3, [r7, #7]
80007a8: 2b00 cmp r3, #0
80007aa: db0a blt.n 80007c2 <__NVIC_SetPriority+0x2a>
{
NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
80007ac: 683b ldr r3, [r7, #0]
80007ae: b2da uxtb r2, r3
80007b0: 490c ldr r1, [pc, #48] ; (80007e4 <__NVIC_SetPriority+0x4c>)
80007b2: f997 3007 ldrsb.w r3, [r7, #7]
80007b6: 0112 lsls r2, r2, #4
80007b8: b2d2 uxtb r2, r2
80007ba: 440b add r3, r1
80007bc: f883 2300 strb.w r2, [r3, #768] ; 0x300
}
else
{
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
}
}
80007c0: e00a b.n 80007d8 <__NVIC_SetPriority+0x40>
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
80007c2: 683b ldr r3, [r7, #0]
80007c4: b2da uxtb r2, r3
80007c6: 4908 ldr r1, [pc, #32] ; (80007e8 <__NVIC_SetPriority+0x50>)
80007c8: 79fb ldrb r3, [r7, #7]
80007ca: f003 030f and.w r3, r3, #15
80007ce: 3b04 subs r3, #4
80007d0: 0112 lsls r2, r2, #4
80007d2: b2d2 uxtb r2, r2
80007d4: 440b add r3, r1
80007d6: 761a strb r2, [r3, #24]
}
80007d8: bf00 nop
80007da: 370c adds r7, #12
80007dc: 46bd mov sp, r7
80007de: bc80 pop {r7}
80007e0: 4770 bx lr
80007e2: bf00 nop
80007e4: e000e100 .word 0xe000e100
80007e8: e000ed00 .word 0xe000ed00
080007ec <NVIC_EncodePriority>:
\param [in] PreemptPriority Preemptive priority value (starting from 0).
\param [in] SubPriority Subpriority value (starting from 0).
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
80007ec: b480 push {r7}
80007ee: b089 sub sp, #36 ; 0x24
80007f0: af00 add r7, sp, #0
80007f2: 60f8 str r0, [r7, #12]
80007f4: 60b9 str r1, [r7, #8]
80007f6: 607a str r2, [r7, #4]
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
80007f8: 68fb ldr r3, [r7, #12]
80007fa: f003 0307 and.w r3, r3, #7
80007fe: 61fb str r3, [r7, #28]
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
8000800: 69fb ldr r3, [r7, #28]
8000802: f1c3 0307 rsb r3, r3, #7
8000806: 2b04 cmp r3, #4
8000808: bf28 it cs
800080a: 2304 movcs r3, #4
800080c: 61bb str r3, [r7, #24]
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
800080e: 69fb ldr r3, [r7, #28]
8000810: 3304 adds r3, #4
8000812: 2b06 cmp r3, #6
8000814: d902 bls.n 800081c <NVIC_EncodePriority+0x30>
8000816: 69fb ldr r3, [r7, #28]
8000818: 3b03 subs r3, #3
800081a: e000 b.n 800081e <NVIC_EncodePriority+0x32>
800081c: 2300 movs r3, #0
800081e: 617b str r3, [r7, #20]
return (
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
8000820: f04f 32ff mov.w r2, #4294967295
8000824: 69bb ldr r3, [r7, #24]
8000826: fa02 f303 lsl.w r3, r2, r3
800082a: 43da mvns r2, r3
800082c: 68bb ldr r3, [r7, #8]
800082e: 401a ands r2, r3
8000830: 697b ldr r3, [r7, #20]
8000832: 409a lsls r2, r3
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
8000834: f04f 31ff mov.w r1, #4294967295
8000838: 697b ldr r3, [r7, #20]
800083a: fa01 f303 lsl.w r3, r1, r3
800083e: 43d9 mvns r1, r3
8000840: 687b ldr r3, [r7, #4]
8000842: 400b ands r3, r1
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
8000844: 4313 orrs r3, r2
);
}
8000846: 4618 mov r0, r3
8000848: 3724 adds r7, #36 ; 0x24
800084a: 46bd mov sp, r7
800084c: bc80 pop {r7}
800084e: 4770 bx lr
08000850 <SysTick_Config>:
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
8000850: b580 push {r7, lr}
8000852: b082 sub sp, #8
8000854: af00 add r7, sp, #0
8000856: 6078 str r0, [r7, #4]
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
8000858: 687b ldr r3, [r7, #4]
800085a: 3b01 subs r3, #1
800085c: f1b3 7f80 cmp.w r3, #16777216 ; 0x1000000
8000860: d301 bcc.n 8000866 <SysTick_Config+0x16>
{
return (1UL); /* Reload value impossible */
8000862: 2301 movs r3, #1
8000864: e00f b.n 8000886 <SysTick_Config+0x36>
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
8000866: 4a0a ldr r2, [pc, #40] ; (8000890 <SysTick_Config+0x40>)
8000868: 687b ldr r3, [r7, #4]
800086a: 3b01 subs r3, #1
800086c: 6053 str r3, [r2, #4]
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
800086e: 210f movs r1, #15
8000870: f04f 30ff mov.w r0, #4294967295
8000874: f7ff ff90 bl 8000798 <__NVIC_SetPriority>
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
8000878: 4b05 ldr r3, [pc, #20] ; (8000890 <SysTick_Config+0x40>)
800087a: 2200 movs r2, #0
800087c: 609a str r2, [r3, #8]
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
800087e: 4b04 ldr r3, [pc, #16] ; (8000890 <SysTick_Config+0x40>)
8000880: 2207 movs r2, #7
8000882: 601a str r2, [r3, #0]
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
8000884: 2300 movs r3, #0
}
8000886: 4618 mov r0, r3
8000888: 3708 adds r7, #8
800088a: 46bd mov sp, r7
800088c: bd80 pop {r7, pc}
800088e: bf00 nop
8000890: e000e010 .word 0xe000e010
08000894 <HAL_NVIC_SetPriorityGrouping>:
* @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible.
* The pending IRQ priority will be managed only by the subpriority.
* @retval None
*/
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
8000894: b580 push {r7, lr}
8000896: b082 sub sp, #8
8000898: af00 add r7, sp, #0
800089a: 6078 str r0, [r7, #4]
/* Check the parameters */
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
/* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
NVIC_SetPriorityGrouping(PriorityGroup);
800089c: 6878 ldr r0, [r7, #4]
800089e: f7ff ff49 bl 8000734 <__NVIC_SetPriorityGrouping>
}
80008a2: bf00 nop
80008a4: 3708 adds r7, #8
80008a6: 46bd mov sp, r7
80008a8: bd80 pop {r7, pc}
080008aa <HAL_NVIC_SetPriority>:
* This parameter can be a value between 0 and 15
* A lower priority value indicates a higher priority.
* @retval None
*/
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
{
80008aa: b580 push {r7, lr}
80008ac: b086 sub sp, #24
80008ae: af00 add r7, sp, #0
80008b0: 4603 mov r3, r0
80008b2: 60b9 str r1, [r7, #8]
80008b4: 607a str r2, [r7, #4]
80008b6: 73fb strb r3, [r7, #15]
uint32_t prioritygroup = 0x00U;
80008b8: 2300 movs r3, #0
80008ba: 617b str r3, [r7, #20]
/* Check the parameters */
assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
prioritygroup = NVIC_GetPriorityGrouping();
80008bc: f7ff ff5e bl 800077c <__NVIC_GetPriorityGrouping>
80008c0: 6178 str r0, [r7, #20]
NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
80008c2: 687a ldr r2, [r7, #4]
80008c4: 68b9 ldr r1, [r7, #8]
80008c6: 6978 ldr r0, [r7, #20]
80008c8: f7ff ff90 bl 80007ec <NVIC_EncodePriority>
80008cc: 4602 mov r2, r0
80008ce: f997 300f ldrsb.w r3, [r7, #15]
80008d2: 4611 mov r1, r2
80008d4: 4618 mov r0, r3
80008d6: f7ff ff5f bl 8000798 <__NVIC_SetPriority>
}
80008da: bf00 nop
80008dc: 3718 adds r7, #24
80008de: 46bd mov sp, r7
80008e0: bd80 pop {r7, pc}
080008e2 <HAL_SYSTICK_Config>:
* @param TicksNumb: Specifies the ticks Number of ticks between two interrupts.
* @retval status: - 0 Function succeeded.
* - 1 Function failed.
*/
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
{
80008e2: b580 push {r7, lr}
80008e4: b082 sub sp, #8
80008e6: af00 add r7, sp, #0
80008e8: 6078 str r0, [r7, #4]
return SysTick_Config(TicksNumb);
80008ea: 6878 ldr r0, [r7, #4]
80008ec: f7ff ffb0 bl 8000850 <SysTick_Config>
80008f0: 4603 mov r3, r0
}
80008f2: 4618 mov r0, r3
80008f4: 3708 adds r7, #8
80008f6: 46bd mov sp, r7
80008f8: bd80 pop {r7, pc}
...
080008fc <HAL_GPIO_Init>:
* @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains
* the configuration information for the specified GPIO peripheral.
* @retval None
*/
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
{
80008fc: b480 push {r7}
80008fe: b08b sub sp, #44 ; 0x2c
8000900: af00 add r7, sp, #0
8000902: 6078 str r0, [r7, #4]
8000904: 6039 str r1, [r7, #0]
uint32_t position = 0x00u;
8000906: 2300 movs r3, #0
8000908: 627b str r3, [r7, #36] ; 0x24
uint32_t ioposition;
uint32_t iocurrent;
uint32_t temp;
uint32_t config = 0x00u;
800090a: 2300 movs r3, #0
800090c: 623b str r3, [r7, #32]
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
/* Configure the port pins */
while (((GPIO_Init->Pin) >> position) != 0x00u)
800090e: e169 b.n 8000be4 <HAL_GPIO_Init+0x2e8>
{
/* Get the IO position */
ioposition = (0x01uL << position);
8000910: 2201 movs r2, #1
8000912: 6a7b ldr r3, [r7, #36] ; 0x24
8000914: fa02 f303 lsl.w r3, r2, r3
8000918: 61fb str r3, [r7, #28]
/* Get the current IO position */
iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition;
800091a: 683b ldr r3, [r7, #0]
800091c: 681b ldr r3, [r3, #0]
800091e: 69fa ldr r2, [r7, #28]
8000920: 4013 ands r3, r2
8000922: 61bb str r3, [r7, #24]
if (iocurrent == ioposition)
8000924: 69ba ldr r2, [r7, #24]
8000926: 69fb ldr r3, [r7, #28]
8000928: 429a cmp r2, r3
800092a: f040 8158 bne.w 8000bde <HAL_GPIO_Init+0x2e2>
{
/* Check the Alternate function parameters */
assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
/* Based on the required mode, filling config variable with MODEy[1:0] and CNFy[3:2] corresponding bits */
switch (GPIO_Init->Mode)
800092e: 683b ldr r3, [r7, #0]
8000930: 685b ldr r3, [r3, #4]
8000932: 4a9a ldr r2, [pc, #616] ; (8000b9c <HAL_GPIO_Init+0x2a0>)
8000934: 4293 cmp r3, r2
8000936: d05e beq.n 80009f6 <HAL_GPIO_Init+0xfa>
8000938: 4a98 ldr r2, [pc, #608] ; (8000b9c <HAL_GPIO_Init+0x2a0>)
800093a: 4293 cmp r3, r2
800093c: d875 bhi.n 8000a2a <HAL_GPIO_Init+0x12e>
800093e: 4a98 ldr r2, [pc, #608] ; (8000ba0 <HAL_GPIO_Init+0x2a4>)
8000940: 4293 cmp r3, r2
8000942: d058 beq.n 80009f6 <HAL_GPIO_Init+0xfa>
8000944: 4a96 ldr r2, [pc, #600] ; (8000ba0 <HAL_GPIO_Init+0x2a4>)
8000946: 4293 cmp r3, r2
8000948: d86f bhi.n 8000a2a <HAL_GPIO_Init+0x12e>
800094a: 4a96 ldr r2, [pc, #600] ; (8000ba4 <HAL_GPIO_Init+0x2a8>)
800094c: 4293 cmp r3, r2
800094e: d052 beq.n 80009f6 <HAL_GPIO_Init+0xfa>
8000950: 4a94 ldr r2, [pc, #592] ; (8000ba4 <HAL_GPIO_Init+0x2a8>)
8000952: 4293 cmp r3, r2
8000954: d869 bhi.n 8000a2a <HAL_GPIO_Init+0x12e>
8000956: 4a94 ldr r2, [pc, #592] ; (8000ba8 <HAL_GPIO_Init+0x2ac>)
8000958: 4293 cmp r3, r2
800095a: d04c beq.n 80009f6 <HAL_GPIO_Init+0xfa>
800095c: 4a92 ldr r2, [pc, #584] ; (8000ba8 <HAL_GPIO_Init+0x2ac>)
800095e: 4293 cmp r3, r2
8000960: d863 bhi.n 8000a2a <HAL_GPIO_Init+0x12e>
8000962: 4a92 ldr r2, [pc, #584] ; (8000bac <HAL_GPIO_Init+0x2b0>)
8000964: 4293 cmp r3, r2
8000966: d046 beq.n 80009f6 <HAL_GPIO_Init+0xfa>
8000968: 4a90 ldr r2, [pc, #576] ; (8000bac <HAL_GPIO_Init+0x2b0>)
800096a: 4293 cmp r3, r2
800096c: d85d bhi.n 8000a2a <HAL_GPIO_Init+0x12e>
800096e: 2b12 cmp r3, #18
8000970: d82a bhi.n 80009c8 <HAL_GPIO_Init+0xcc>
8000972: 2b12 cmp r3, #18
8000974: d859 bhi.n 8000a2a <HAL_GPIO_Init+0x12e>
8000976: a201 add r2, pc, #4 ; (adr r2, 800097c <HAL_GPIO_Init+0x80>)
8000978: f852 f023 ldr.w pc, [r2, r3, lsl #2]
800097c: 080009f7 .word 0x080009f7
8000980: 080009d1 .word 0x080009d1
8000984: 080009e3 .word 0x080009e3
8000988: 08000a25 .word 0x08000a25
800098c: 08000a2b .word 0x08000a2b
8000990: 08000a2b .word 0x08000a2b
8000994: 08000a2b .word 0x08000a2b
8000998: 08000a2b .word 0x08000a2b
800099c: 08000a2b .word 0x08000a2b
80009a0: 08000a2b .word 0x08000a2b
80009a4: 08000a2b .word 0x08000a2b
80009a8: 08000a2b .word 0x08000a2b
80009ac: 08000a2b .word 0x08000a2b
80009b0: 08000a2b .word 0x08000a2b
80009b4: 08000a2b .word 0x08000a2b
80009b8: 08000a2b .word 0x08000a2b
80009bc: 08000a2b .word 0x08000a2b
80009c0: 080009d9 .word 0x080009d9
80009c4: 080009ed .word 0x080009ed
80009c8: 4a79 ldr r2, [pc, #484] ; (8000bb0 <HAL_GPIO_Init+0x2b4>)
80009ca: 4293 cmp r3, r2
80009cc: d013 beq.n 80009f6 <HAL_GPIO_Init+0xfa>
config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG;
break;
/* Parameters are checked with assert_param */
default:
break;
80009ce: e02c b.n 8000a2a <HAL_GPIO_Init+0x12e>
config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_PP;
80009d0: 683b ldr r3, [r7, #0]
80009d2: 68db ldr r3, [r3, #12]
80009d4: 623b str r3, [r7, #32]
break;
80009d6: e029 b.n 8000a2c <HAL_GPIO_Init+0x130>
config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_OD;
80009d8: 683b ldr r3, [r7, #0]
80009da: 68db ldr r3, [r3, #12]
80009dc: 3304 adds r3, #4
80009de: 623b str r3, [r7, #32]
break;
80009e0: e024 b.n 8000a2c <HAL_GPIO_Init+0x130>
config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_PP;
80009e2: 683b ldr r3, [r7, #0]
80009e4: 68db ldr r3, [r3, #12]
80009e6: 3308 adds r3, #8
80009e8: 623b str r3, [r7, #32]
break;
80009ea: e01f b.n 8000a2c <HAL_GPIO_Init+0x130>
config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_OD;
80009ec: 683b ldr r3, [r7, #0]
80009ee: 68db ldr r3, [r3, #12]
80009f0: 330c adds r3, #12
80009f2: 623b str r3, [r7, #32]
break;
80009f4: e01a b.n 8000a2c <HAL_GPIO_Init+0x130>
if (GPIO_Init->Pull == GPIO_NOPULL)
80009f6: 683b ldr r3, [r7, #0]
80009f8: 689b ldr r3, [r3, #8]
80009fa: 2b00 cmp r3, #0
80009fc: d102 bne.n 8000a04 <HAL_GPIO_Init+0x108>
config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_FLOATING;
80009fe: 2304 movs r3, #4
8000a00: 623b str r3, [r7, #32]
break;
8000a02: e013 b.n 8000a2c <HAL_GPIO_Init+0x130>
else if (GPIO_Init->Pull == GPIO_PULLUP)
8000a04: 683b ldr r3, [r7, #0]
8000a06: 689b ldr r3, [r3, #8]
8000a08: 2b01 cmp r3, #1
8000a0a: d105 bne.n 8000a18 <HAL_GPIO_Init+0x11c>
config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD;
8000a0c: 2308 movs r3, #8
8000a0e: 623b str r3, [r7, #32]
GPIOx->BSRR = ioposition;
8000a10: 687b ldr r3, [r7, #4]
8000a12: 69fa ldr r2, [r7, #28]
8000a14: 611a str r2, [r3, #16]
break;
8000a16: e009 b.n 8000a2c <HAL_GPIO_Init+0x130>
config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD;
8000a18: 2308 movs r3, #8
8000a1a: 623b str r3, [r7, #32]
GPIOx->BRR = ioposition;
8000a1c: 687b ldr r3, [r7, #4]
8000a1e: 69fa ldr r2, [r7, #28]
8000a20: 615a str r2, [r3, #20]
break;
8000a22: e003 b.n 8000a2c <HAL_GPIO_Init+0x130>
config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG;
8000a24: 2300 movs r3, #0
8000a26: 623b str r3, [r7, #32]
break;
8000a28: e000 b.n 8000a2c <HAL_GPIO_Init+0x130>
break;
8000a2a: bf00 nop
}
/* Check if the current bit belongs to first half or last half of the pin count number
in order to address CRH or CRL register*/
configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL : &GPIOx->CRH;
8000a2c: 69bb ldr r3, [r7, #24]
8000a2e: 2bff cmp r3, #255 ; 0xff
8000a30: d801 bhi.n 8000a36 <HAL_GPIO_Init+0x13a>
8000a32: 687b ldr r3, [r7, #4]
8000a34: e001 b.n 8000a3a <HAL_GPIO_Init+0x13e>
8000a36: 687b ldr r3, [r7, #4]
8000a38: 3304 adds r3, #4
8000a3a: 617b str r3, [r7, #20]
registeroffset = (iocurrent < GPIO_PIN_8) ? (position << 2u) : ((position - 8u) << 2u);
8000a3c: 69bb ldr r3, [r7, #24]
8000a3e: 2bff cmp r3, #255 ; 0xff
8000a40: d802 bhi.n 8000a48 <HAL_GPIO_Init+0x14c>
8000a42: 6a7b ldr r3, [r7, #36] ; 0x24
8000a44: 009b lsls r3, r3, #2
8000a46: e002 b.n 8000a4e <HAL_GPIO_Init+0x152>
8000a48: 6a7b ldr r3, [r7, #36] ; 0x24
8000a4a: 3b08 subs r3, #8
8000a4c: 009b lsls r3, r3, #2
8000a4e: 613b str r3, [r7, #16]
/* Apply the new configuration of the pin to the register */
MODIFY_REG((*configregister), ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset), (config << registeroffset));
8000a50: 697b ldr r3, [r7, #20]
8000a52: 681a ldr r2, [r3, #0]
8000a54: 210f movs r1, #15
8000a56: 693b ldr r3, [r7, #16]
8000a58: fa01 f303 lsl.w r3, r1, r3
8000a5c: 43db mvns r3, r3
8000a5e: 401a ands r2, r3
8000a60: 6a39 ldr r1, [r7, #32]
8000a62: 693b ldr r3, [r7, #16]
8000a64: fa01 f303 lsl.w r3, r1, r3
8000a68: 431a orrs r2, r3
8000a6a: 697b ldr r3, [r7, #20]
8000a6c: 601a str r2, [r3, #0]
/*--------------------- EXTI Mode Configuration ------------------------*/
/* Configure the External Interrupt or event for the current IO */
if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
8000a6e: 683b ldr r3, [r7, #0]
8000a70: 685b ldr r3, [r3, #4]
8000a72: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
8000a76: 2b00 cmp r3, #0
8000a78: f000 80b1 beq.w 8000bde <HAL_GPIO_Init+0x2e2>
{
/* Enable AFIO Clock */
__HAL_RCC_AFIO_CLK_ENABLE();
8000a7c: 4b4d ldr r3, [pc, #308] ; (8000bb4 <HAL_GPIO_Init+0x2b8>)
8000a7e: 699b ldr r3, [r3, #24]
8000a80: 4a4c ldr r2, [pc, #304] ; (8000bb4 <HAL_GPIO_Init+0x2b8>)
8000a82: f043 0301 orr.w r3, r3, #1
8000a86: 6193 str r3, [r2, #24]
8000a88: 4b4a ldr r3, [pc, #296] ; (8000bb4 <HAL_GPIO_Init+0x2b8>)
8000a8a: 699b ldr r3, [r3, #24]
8000a8c: f003 0301 and.w r3, r3, #1
8000a90: 60bb str r3, [r7, #8]
8000a92: 68bb ldr r3, [r7, #8]
temp = AFIO->EXTICR[position >> 2u];
8000a94: 4a48 ldr r2, [pc, #288] ; (8000bb8 <HAL_GPIO_Init+0x2bc>)
8000a96: 6a7b ldr r3, [r7, #36] ; 0x24
8000a98: 089b lsrs r3, r3, #2
8000a9a: 3302 adds r3, #2
8000a9c: f852 3023 ldr.w r3, [r2, r3, lsl #2]
8000aa0: 60fb str r3, [r7, #12]
CLEAR_BIT(temp, (0x0Fu) << (4u * (position & 0x03u)));
8000aa2: 6a7b ldr r3, [r7, #36] ; 0x24
8000aa4: f003 0303 and.w r3, r3, #3
8000aa8: 009b lsls r3, r3, #2
8000aaa: 220f movs r2, #15
8000aac: fa02 f303 lsl.w r3, r2, r3
8000ab0: 43db mvns r3, r3
8000ab2: 68fa ldr r2, [r7, #12]
8000ab4: 4013 ands r3, r2
8000ab6: 60fb str r3, [r7, #12]
SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4u * (position & 0x03u)));
8000ab8: 687b ldr r3, [r7, #4]
8000aba: 4a40 ldr r2, [pc, #256] ; (8000bbc <HAL_GPIO_Init+0x2c0>)
8000abc: 4293 cmp r3, r2
8000abe: d013 beq.n 8000ae8 <HAL_GPIO_Init+0x1ec>
8000ac0: 687b ldr r3, [r7, #4]
8000ac2: 4a3f ldr r2, [pc, #252] ; (8000bc0 <HAL_GPIO_Init+0x2c4>)
8000ac4: 4293 cmp r3, r2
8000ac6: d00d beq.n 8000ae4 <HAL_GPIO_Init+0x1e8>
8000ac8: 687b ldr r3, [r7, #4]
8000aca: 4a3e ldr r2, [pc, #248] ; (8000bc4 <HAL_GPIO_Init+0x2c8>)
8000acc: 4293 cmp r3, r2
8000ace: d007 beq.n 8000ae0 <HAL_GPIO_Init+0x1e4>
8000ad0: 687b ldr r3, [r7, #4]
8000ad2: 4a3d ldr r2, [pc, #244] ; (8000bc8 <HAL_GPIO_Init+0x2cc>)
8000ad4: 4293 cmp r3, r2
8000ad6: d101 bne.n 8000adc <HAL_GPIO_Init+0x1e0>
8000ad8: 2303 movs r3, #3
8000ada: e006 b.n 8000aea <HAL_GPIO_Init+0x1ee>
8000adc: 2304 movs r3, #4
8000ade: e004 b.n 8000aea <HAL_GPIO_Init+0x1ee>
8000ae0: 2302 movs r3, #2
8000ae2: e002 b.n 8000aea <HAL_GPIO_Init+0x1ee>
8000ae4: 2301 movs r3, #1
8000ae6: e000 b.n 8000aea <HAL_GPIO_Init+0x1ee>
8000ae8: 2300 movs r3, #0
8000aea: 6a7a ldr r2, [r7, #36] ; 0x24
8000aec: f002 0203 and.w r2, r2, #3
8000af0: 0092 lsls r2, r2, #2
8000af2: 4093 lsls r3, r2
8000af4: 68fa ldr r2, [r7, #12]
8000af6: 4313 orrs r3, r2
8000af8: 60fb str r3, [r7, #12]
AFIO->EXTICR[position >> 2u] = temp;
8000afa: 492f ldr r1, [pc, #188] ; (8000bb8 <HAL_GPIO_Init+0x2bc>)
8000afc: 6a7b ldr r3, [r7, #36] ; 0x24
8000afe: 089b lsrs r3, r3, #2
8000b00: 3302 adds r3, #2
8000b02: 68fa ldr r2, [r7, #12]
8000b04: f841 2023 str.w r2, [r1, r3, lsl #2]
/* Configure the interrupt mask */
if ((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
8000b08: 683b ldr r3, [r7, #0]
8000b0a: 685b ldr r3, [r3, #4]
8000b0c: f403 3380 and.w r3, r3, #65536 ; 0x10000
8000b10: 2b00 cmp r3, #0
8000b12: d006 beq.n 8000b22 <HAL_GPIO_Init+0x226>
{
SET_BIT(EXTI->IMR, iocurrent);
8000b14: 4b2d ldr r3, [pc, #180] ; (8000bcc <HAL_GPIO_Init+0x2d0>)
8000b16: 681a ldr r2, [r3, #0]
8000b18: 492c ldr r1, [pc, #176] ; (8000bcc <HAL_GPIO_Init+0x2d0>)
8000b1a: 69bb ldr r3, [r7, #24]
8000b1c: 4313 orrs r3, r2
8000b1e: 600b str r3, [r1, #0]
8000b20: e006 b.n 8000b30 <HAL_GPIO_Init+0x234>
}
else
{
CLEAR_BIT(EXTI->IMR, iocurrent);
8000b22: 4b2a ldr r3, [pc, #168] ; (8000bcc <HAL_GPIO_Init+0x2d0>)
8000b24: 681a ldr r2, [r3, #0]
8000b26: 69bb ldr r3, [r7, #24]
8000b28: 43db mvns r3, r3
8000b2a: 4928 ldr r1, [pc, #160] ; (8000bcc <HAL_GPIO_Init+0x2d0>)
8000b2c: 4013 ands r3, r2
8000b2e: 600b str r3, [r1, #0]
}
/* Configure the event mask */
if ((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
8000b30: 683b ldr r3, [r7, #0]
8000b32: 685b ldr r3, [r3, #4]
8000b34: f403 3300 and.w r3, r3, #131072 ; 0x20000
8000b38: 2b00 cmp r3, #0
8000b3a: d006 beq.n 8000b4a <HAL_GPIO_Init+0x24e>
{
SET_BIT(EXTI->EMR, iocurrent);
8000b3c: 4b23 ldr r3, [pc, #140] ; (8000bcc <HAL_GPIO_Init+0x2d0>)
8000b3e: 685a ldr r2, [r3, #4]
8000b40: 4922 ldr r1, [pc, #136] ; (8000bcc <HAL_GPIO_Init+0x2d0>)
8000b42: 69bb ldr r3, [r7, #24]
8000b44: 4313 orrs r3, r2
8000b46: 604b str r3, [r1, #4]
8000b48: e006 b.n 8000b58 <HAL_GPIO_Init+0x25c>
}
else
{
CLEAR_BIT(EXTI->EMR, iocurrent);
8000b4a: 4b20 ldr r3, [pc, #128] ; (8000bcc <HAL_GPIO_Init+0x2d0>)
8000b4c: 685a ldr r2, [r3, #4]
8000b4e: 69bb ldr r3, [r7, #24]
8000b50: 43db mvns r3, r3
8000b52: 491e ldr r1, [pc, #120] ; (8000bcc <HAL_GPIO_Init+0x2d0>)
8000b54: 4013 ands r3, r2
8000b56: 604b str r3, [r1, #4]
}
/* Enable or disable the rising trigger */
if ((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
8000b58: 683b ldr r3, [r7, #0]
8000b5a: 685b ldr r3, [r3, #4]
8000b5c: f403 1380 and.w r3, r3, #1048576 ; 0x100000
8000b60: 2b00 cmp r3, #0
8000b62: d006 beq.n 8000b72 <HAL_GPIO_Init+0x276>
{
SET_BIT(EXTI->RTSR, iocurrent);
8000b64: 4b19 ldr r3, [pc, #100] ; (8000bcc <HAL_GPIO_Init+0x2d0>)
8000b66: 689a ldr r2, [r3, #8]
8000b68: 4918 ldr r1, [pc, #96] ; (8000bcc <HAL_GPIO_Init+0x2d0>)
8000b6a: 69bb ldr r3, [r7, #24]
8000b6c: 4313 orrs r3, r2
8000b6e: 608b str r3, [r1, #8]
8000b70: e006 b.n 8000b80 <HAL_GPIO_Init+0x284>
}
else
{
CLEAR_BIT(EXTI->RTSR, iocurrent);
8000b72: 4b16 ldr r3, [pc, #88] ; (8000bcc <HAL_GPIO_Init+0x2d0>)
8000b74: 689a ldr r2, [r3, #8]
8000b76: 69bb ldr r3, [r7, #24]
8000b78: 43db mvns r3, r3
8000b7a: 4914 ldr r1, [pc, #80] ; (8000bcc <HAL_GPIO_Init+0x2d0>)
8000b7c: 4013 ands r3, r2
8000b7e: 608b str r3, [r1, #8]
}
/* Enable or disable the falling trigger */
if ((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
8000b80: 683b ldr r3, [r7, #0]
8000b82: 685b ldr r3, [r3, #4]
8000b84: f403 1300 and.w r3, r3, #2097152 ; 0x200000
8000b88: 2b00 cmp r3, #0
8000b8a: d021 beq.n 8000bd0 <HAL_GPIO_Init+0x2d4>
{
SET_BIT(EXTI->FTSR, iocurrent);
8000b8c: 4b0f ldr r3, [pc, #60] ; (8000bcc <HAL_GPIO_Init+0x2d0>)
8000b8e: 68da ldr r2, [r3, #12]
8000b90: 490e ldr r1, [pc, #56] ; (8000bcc <HAL_GPIO_Init+0x2d0>)
8000b92: 69bb ldr r3, [r7, #24]
8000b94: 4313 orrs r3, r2
8000b96: 60cb str r3, [r1, #12]
8000b98: e021 b.n 8000bde <HAL_GPIO_Init+0x2e2>
8000b9a: bf00 nop
8000b9c: 10320000 .word 0x10320000
8000ba0: 10310000 .word 0x10310000
8000ba4: 10220000 .word 0x10220000
8000ba8: 10210000 .word 0x10210000
8000bac: 10120000 .word 0x10120000
8000bb0: 10110000 .word 0x10110000
8000bb4: 40021000 .word 0x40021000
8000bb8: 40010000 .word 0x40010000
8000bbc: 40010800 .word 0x40010800
8000bc0: 40010c00 .word 0x40010c00
8000bc4: 40011000 .word 0x40011000
8000bc8: 40011400 .word 0x40011400
8000bcc: 40010400 .word 0x40010400
}
else
{
CLEAR_BIT(EXTI->FTSR, iocurrent);
8000bd0: 4b0b ldr r3, [pc, #44] ; (8000c00 <HAL_GPIO_Init+0x304>)
8000bd2: 68da ldr r2, [r3, #12]
8000bd4: 69bb ldr r3, [r7, #24]
8000bd6: 43db mvns r3, r3
8000bd8: 4909 ldr r1, [pc, #36] ; (8000c00 <HAL_GPIO_Init+0x304>)
8000bda: 4013 ands r3, r2
8000bdc: 60cb str r3, [r1, #12]
}
}
}
position++;
8000bde: 6a7b ldr r3, [r7, #36] ; 0x24
8000be0: 3301 adds r3, #1
8000be2: 627b str r3, [r7, #36] ; 0x24
while (((GPIO_Init->Pin) >> position) != 0x00u)
8000be4: 683b ldr r3, [r7, #0]
8000be6: 681a ldr r2, [r3, #0]
8000be8: 6a7b ldr r3, [r7, #36] ; 0x24
8000bea: fa22 f303 lsr.w r3, r2, r3
8000bee: 2b00 cmp r3, #0
8000bf0: f47f ae8e bne.w 8000910 <HAL_GPIO_Init+0x14>
}
}
8000bf4: bf00 nop
8000bf6: bf00 nop
8000bf8: 372c adds r7, #44 ; 0x2c
8000bfa: 46bd mov sp, r7
8000bfc: bc80 pop {r7}
8000bfe: 4770 bx lr
8000c00: 40010400 .word 0x40010400
08000c04 <HAL_RCC_OscConfig>:
* supported by this macro. User should request a transition to HSE Off
* first and then HSE On or HSE Bypass.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
{
8000c04: b580 push {r7, lr}
8000c06: b086 sub sp, #24
8000c08: af00 add r7, sp, #0
8000c0a: 6078 str r0, [r7, #4]
uint32_t tickstart;
uint32_t pll_config;
/* Check Null pointer */
if (RCC_OscInitStruct == NULL)
8000c0c: 687b ldr r3, [r7, #4]
8000c0e: 2b00 cmp r3, #0
8000c10: d101 bne.n 8000c16 <HAL_RCC_OscConfig+0x12>
{
return HAL_ERROR;
8000c12: 2301 movs r3, #1
8000c14: e272 b.n 80010fc <HAL_RCC_OscConfig+0x4f8>
/* Check the parameters */
assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
/*------------------------------- HSE Configuration ------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
8000c16: 687b ldr r3, [r7, #4]
8000c18: 681b ldr r3, [r3, #0]
8000c1a: f003 0301 and.w r3, r3, #1
8000c1e: 2b00 cmp r3, #0
8000c20: f000 8087 beq.w 8000d32 <HAL_RCC_OscConfig+0x12e>
{
/* Check the parameters */
assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
/* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)
8000c24: 4b92 ldr r3, [pc, #584] ; (8000e70 <HAL_RCC_OscConfig+0x26c>)
8000c26: 685b ldr r3, [r3, #4]
8000c28: f003 030c and.w r3, r3, #12
8000c2c: 2b04 cmp r3, #4
8000c2e: d00c beq.n 8000c4a <HAL_RCC_OscConfig+0x46>
|| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE)))
8000c30: 4b8f ldr r3, [pc, #572] ; (8000e70 <HAL_RCC_OscConfig+0x26c>)
8000c32: 685b ldr r3, [r3, #4]
8000c34: f003 030c and.w r3, r3, #12
8000c38: 2b08 cmp r3, #8
8000c3a: d112 bne.n 8000c62 <HAL_RCC_OscConfig+0x5e>
8000c3c: 4b8c ldr r3, [pc, #560] ; (8000e70 <HAL_RCC_OscConfig+0x26c>)
8000c3e: 685b ldr r3, [r3, #4]
8000c40: f403 3380 and.w r3, r3, #65536 ; 0x10000
8000c44: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
8000c48: d10b bne.n 8000c62 <HAL_RCC_OscConfig+0x5e>
{
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
8000c4a: 4b89 ldr r3, [pc, #548] ; (8000e70 <HAL_RCC_OscConfig+0x26c>)
8000c4c: 681b ldr r3, [r3, #0]
8000c4e: f403 3300 and.w r3, r3, #131072 ; 0x20000
8000c52: 2b00 cmp r3, #0
8000c54: d06c beq.n 8000d30 <HAL_RCC_OscConfig+0x12c>
8000c56: 687b ldr r3, [r7, #4]
8000c58: 685b ldr r3, [r3, #4]
8000c5a: 2b00 cmp r3, #0
8000c5c: d168 bne.n 8000d30 <HAL_RCC_OscConfig+0x12c>
{
return HAL_ERROR;
8000c5e: 2301 movs r3, #1
8000c60: e24c b.n 80010fc <HAL_RCC_OscConfig+0x4f8>
}
}
else
{
/* Set the new HSE configuration ---------------------------------------*/
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
8000c62: 687b ldr r3, [r7, #4]
8000c64: 685b ldr r3, [r3, #4]
8000c66: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
8000c6a: d106 bne.n 8000c7a <HAL_RCC_OscConfig+0x76>
8000c6c: 4b80 ldr r3, [pc, #512] ; (8000e70 <HAL_RCC_OscConfig+0x26c>)
8000c6e: 681b ldr r3, [r3, #0]
8000c70: 4a7f ldr r2, [pc, #508] ; (8000e70 <HAL_RCC_OscConfig+0x26c>)
8000c72: f443 3380 orr.w r3, r3, #65536 ; 0x10000
8000c76: 6013 str r3, [r2, #0]
8000c78: e02e b.n 8000cd8 <HAL_RCC_OscConfig+0xd4>
8000c7a: 687b ldr r3, [r7, #4]
8000c7c: 685b ldr r3, [r3, #4]
8000c7e: 2b00 cmp r3, #0
8000c80: d10c bne.n 8000c9c <HAL_RCC_OscConfig+0x98>
8000c82: 4b7b ldr r3, [pc, #492] ; (8000e70 <HAL_RCC_OscConfig+0x26c>)
8000c84: 681b ldr r3, [r3, #0]
8000c86: 4a7a ldr r2, [pc, #488] ; (8000e70 <HAL_RCC_OscConfig+0x26c>)
8000c88: f423 3380 bic.w r3, r3, #65536 ; 0x10000
8000c8c: 6013 str r3, [r2, #0]
8000c8e: 4b78 ldr r3, [pc, #480] ; (8000e70 <HAL_RCC_OscConfig+0x26c>)
8000c90: 681b ldr r3, [r3, #0]
8000c92: 4a77 ldr r2, [pc, #476] ; (8000e70 <HAL_RCC_OscConfig+0x26c>)
8000c94: f423 2380 bic.w r3, r3, #262144 ; 0x40000
8000c98: 6013 str r3, [r2, #0]
8000c9a: e01d b.n 8000cd8 <HAL_RCC_OscConfig+0xd4>
8000c9c: 687b ldr r3, [r7, #4]
8000c9e: 685b ldr r3, [r3, #4]
8000ca0: f5b3 2fa0 cmp.w r3, #327680 ; 0x50000
8000ca4: d10c bne.n 8000cc0 <HAL_RCC_OscConfig+0xbc>
8000ca6: 4b72 ldr r3, [pc, #456] ; (8000e70 <HAL_RCC_OscConfig+0x26c>)
8000ca8: 681b ldr r3, [r3, #0]
8000caa: 4a71 ldr r2, [pc, #452] ; (8000e70 <HAL_RCC_OscConfig+0x26c>)
8000cac: f443 2380 orr.w r3, r3, #262144 ; 0x40000
8000cb0: 6013 str r3, [r2, #0]
8000cb2: 4b6f ldr r3, [pc, #444] ; (8000e70 <HAL_RCC_OscConfig+0x26c>)
8000cb4: 681b ldr r3, [r3, #0]
8000cb6: 4a6e ldr r2, [pc, #440] ; (8000e70 <HAL_RCC_OscConfig+0x26c>)
8000cb8: f443 3380 orr.w r3, r3, #65536 ; 0x10000
8000cbc: 6013 str r3, [r2, #0]
8000cbe: e00b b.n 8000cd8 <HAL_RCC_OscConfig+0xd4>
8000cc0: 4b6b ldr r3, [pc, #428] ; (8000e70 <HAL_RCC_OscConfig+0x26c>)
8000cc2: 681b ldr r3, [r3, #0]
8000cc4: 4a6a ldr r2, [pc, #424] ; (8000e70 <HAL_RCC_OscConfig+0x26c>)
8000cc6: f423 3380 bic.w r3, r3, #65536 ; 0x10000
8000cca: 6013 str r3, [r2, #0]
8000ccc: 4b68 ldr r3, [pc, #416] ; (8000e70 <HAL_RCC_OscConfig+0x26c>)
8000cce: 681b ldr r3, [r3, #0]
8000cd0: 4a67 ldr r2, [pc, #412] ; (8000e70 <HAL_RCC_OscConfig+0x26c>)
8000cd2: f423 2380 bic.w r3, r3, #262144 ; 0x40000
8000cd6: 6013 str r3, [r2, #0]
/* Check the HSE State */
if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
8000cd8: 687b ldr r3, [r7, #4]
8000cda: 685b ldr r3, [r3, #4]
8000cdc: 2b00 cmp r3, #0
8000cde: d013 beq.n 8000d08 <HAL_RCC_OscConfig+0x104>
{
/* Get Start Tick */
tickstart = HAL_GetTick();
8000ce0: f7ff fcfa bl 80006d8 <HAL_GetTick>
8000ce4: 6138 str r0, [r7, #16]
/* Wait till HSE is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
8000ce6: e008 b.n 8000cfa <HAL_RCC_OscConfig+0xf6>
{
if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
8000ce8: f7ff fcf6 bl 80006d8 <HAL_GetTick>
8000cec: 4602 mov r2, r0
8000cee: 693b ldr r3, [r7, #16]
8000cf0: 1ad3 subs r3, r2, r3
8000cf2: 2b64 cmp r3, #100 ; 0x64
8000cf4: d901 bls.n 8000cfa <HAL_RCC_OscConfig+0xf6>
{
return HAL_TIMEOUT;
8000cf6: 2303 movs r3, #3
8000cf8: e200 b.n 80010fc <HAL_RCC_OscConfig+0x4f8>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
8000cfa: 4b5d ldr r3, [pc, #372] ; (8000e70 <HAL_RCC_OscConfig+0x26c>)
8000cfc: 681b ldr r3, [r3, #0]
8000cfe: f403 3300 and.w r3, r3, #131072 ; 0x20000
8000d02: 2b00 cmp r3, #0
8000d04: d0f0 beq.n 8000ce8 <HAL_RCC_OscConfig+0xe4>
8000d06: e014 b.n 8000d32 <HAL_RCC_OscConfig+0x12e>
}
}
else
{
/* Get Start Tick */
tickstart = HAL_GetTick();
8000d08: f7ff fce6 bl 80006d8 <HAL_GetTick>
8000d0c: 6138 str r0, [r7, #16]
/* Wait till HSE is disabled */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
8000d0e: e008 b.n 8000d22 <HAL_RCC_OscConfig+0x11e>
{
if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
8000d10: f7ff fce2 bl 80006d8 <HAL_GetTick>
8000d14: 4602 mov r2, r0
8000d16: 693b ldr r3, [r7, #16]
8000d18: 1ad3 subs r3, r2, r3
8000d1a: 2b64 cmp r3, #100 ; 0x64
8000d1c: d901 bls.n 8000d22 <HAL_RCC_OscConfig+0x11e>
{
return HAL_TIMEOUT;
8000d1e: 2303 movs r3, #3
8000d20: e1ec b.n 80010fc <HAL_RCC_OscConfig+0x4f8>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
8000d22: 4b53 ldr r3, [pc, #332] ; (8000e70 <HAL_RCC_OscConfig+0x26c>)
8000d24: 681b ldr r3, [r3, #0]
8000d26: f403 3300 and.w r3, r3, #131072 ; 0x20000
8000d2a: 2b00 cmp r3, #0
8000d2c: d1f0 bne.n 8000d10 <HAL_RCC_OscConfig+0x10c>
8000d2e: e000 b.n 8000d32 <HAL_RCC_OscConfig+0x12e>
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
8000d30: bf00 nop
}
}
}
}
/*----------------------------- HSI Configuration --------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
8000d32: 687b ldr r3, [r7, #4]
8000d34: 681b ldr r3, [r3, #0]
8000d36: f003 0302 and.w r3, r3, #2
8000d3a: 2b00 cmp r3, #0
8000d3c: d063 beq.n 8000e06 <HAL_RCC_OscConfig+0x202>
/* Check the parameters */
assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
/* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)
8000d3e: 4b4c ldr r3, [pc, #304] ; (8000e70 <HAL_RCC_OscConfig+0x26c>)
8000d40: 685b ldr r3, [r3, #4]
8000d42: f003 030c and.w r3, r3, #12
8000d46: 2b00 cmp r3, #0
8000d48: d00b beq.n 8000d62 <HAL_RCC_OscConfig+0x15e>
|| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI_DIV2)))
8000d4a: 4b49 ldr r3, [pc, #292] ; (8000e70 <HAL_RCC_OscConfig+0x26c>)
8000d4c: 685b ldr r3, [r3, #4]
8000d4e: f003 030c and.w r3, r3, #12
8000d52: 2b08 cmp r3, #8
8000d54: d11c bne.n 8000d90 <HAL_RCC_OscConfig+0x18c>
8000d56: 4b46 ldr r3, [pc, #280] ; (8000e70 <HAL_RCC_OscConfig+0x26c>)
8000d58: 685b ldr r3, [r3, #4]
8000d5a: f403 3380 and.w r3, r3, #65536 ; 0x10000
8000d5e: 2b00 cmp r3, #0
8000d60: d116 bne.n 8000d90 <HAL_RCC_OscConfig+0x18c>
{
/* When HSI is used as system clock it will not disabled */
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
8000d62: 4b43 ldr r3, [pc, #268] ; (8000e70 <HAL_RCC_OscConfig+0x26c>)
8000d64: 681b ldr r3, [r3, #0]
8000d66: f003 0302 and.w r3, r3, #2
8000d6a: 2b00 cmp r3, #0
8000d6c: d005 beq.n 8000d7a <HAL_RCC_OscConfig+0x176>
8000d6e: 687b ldr r3, [r7, #4]
8000d70: 691b ldr r3, [r3, #16]
8000d72: 2b01 cmp r3, #1
8000d74: d001 beq.n 8000d7a <HAL_RCC_OscConfig+0x176>
{
return HAL_ERROR;
8000d76: 2301 movs r3, #1
8000d78: e1c0 b.n 80010fc <HAL_RCC_OscConfig+0x4f8>
}
/* Otherwise, just the calibration is allowed */
else
{
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
8000d7a: 4b3d ldr r3, [pc, #244] ; (8000e70 <HAL_RCC_OscConfig+0x26c>)
8000d7c: 681b ldr r3, [r3, #0]
8000d7e: f023 02f8 bic.w r2, r3, #248 ; 0xf8
8000d82: 687b ldr r3, [r7, #4]
8000d84: 695b ldr r3, [r3, #20]
8000d86: 00db lsls r3, r3, #3
8000d88: 4939 ldr r1, [pc, #228] ; (8000e70 <HAL_RCC_OscConfig+0x26c>)
8000d8a: 4313 orrs r3, r2
8000d8c: 600b str r3, [r1, #0]
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
8000d8e: e03a b.n 8000e06 <HAL_RCC_OscConfig+0x202>
}
}
else
{
/* Check the HSI State */
if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
8000d90: 687b ldr r3, [r7, #4]
8000d92: 691b ldr r3, [r3, #16]
8000d94: 2b00 cmp r3, #0
8000d96: d020 beq.n 8000dda <HAL_RCC_OscConfig+0x1d6>
{
/* Enable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_ENABLE();
8000d98: 4b36 ldr r3, [pc, #216] ; (8000e74 <HAL_RCC_OscConfig+0x270>)
8000d9a: 2201 movs r2, #1
8000d9c: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8000d9e: f7ff fc9b bl 80006d8 <HAL_GetTick>
8000da2: 6138 str r0, [r7, #16]
/* Wait till HSI is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
8000da4: e008 b.n 8000db8 <HAL_RCC_OscConfig+0x1b4>
{
if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
8000da6: f7ff fc97 bl 80006d8 <HAL_GetTick>
8000daa: 4602 mov r2, r0
8000dac: 693b ldr r3, [r7, #16]
8000dae: 1ad3 subs r3, r2, r3
8000db0: 2b02 cmp r3, #2
8000db2: d901 bls.n 8000db8 <HAL_RCC_OscConfig+0x1b4>
{
return HAL_TIMEOUT;
8000db4: 2303 movs r3, #3
8000db6: e1a1 b.n 80010fc <HAL_RCC_OscConfig+0x4f8>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
8000db8: 4b2d ldr r3, [pc, #180] ; (8000e70 <HAL_RCC_OscConfig+0x26c>)
8000dba: 681b ldr r3, [r3, #0]
8000dbc: f003 0302 and.w r3, r3, #2
8000dc0: 2b00 cmp r3, #0
8000dc2: d0f0 beq.n 8000da6 <HAL_RCC_OscConfig+0x1a2>
}
}
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
8000dc4: 4b2a ldr r3, [pc, #168] ; (8000e70 <HAL_RCC_OscConfig+0x26c>)
8000dc6: 681b ldr r3, [r3, #0]
8000dc8: f023 02f8 bic.w r2, r3, #248 ; 0xf8
8000dcc: 687b ldr r3, [r7, #4]
8000dce: 695b ldr r3, [r3, #20]
8000dd0: 00db lsls r3, r3, #3
8000dd2: 4927 ldr r1, [pc, #156] ; (8000e70 <HAL_RCC_OscConfig+0x26c>)
8000dd4: 4313 orrs r3, r2
8000dd6: 600b str r3, [r1, #0]
8000dd8: e015 b.n 8000e06 <HAL_RCC_OscConfig+0x202>
}
else
{
/* Disable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_DISABLE();
8000dda: 4b26 ldr r3, [pc, #152] ; (8000e74 <HAL_RCC_OscConfig+0x270>)
8000ddc: 2200 movs r2, #0
8000dde: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8000de0: f7ff fc7a bl 80006d8 <HAL_GetTick>
8000de4: 6138 str r0, [r7, #16]
/* Wait till HSI is disabled */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
8000de6: e008 b.n 8000dfa <HAL_RCC_OscConfig+0x1f6>
{
if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
8000de8: f7ff fc76 bl 80006d8 <HAL_GetTick>
8000dec: 4602 mov r2, r0
8000dee: 693b ldr r3, [r7, #16]
8000df0: 1ad3 subs r3, r2, r3
8000df2: 2b02 cmp r3, #2
8000df4: d901 bls.n 8000dfa <HAL_RCC_OscConfig+0x1f6>
{
return HAL_TIMEOUT;
8000df6: 2303 movs r3, #3
8000df8: e180 b.n 80010fc <HAL_RCC_OscConfig+0x4f8>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
8000dfa: 4b1d ldr r3, [pc, #116] ; (8000e70 <HAL_RCC_OscConfig+0x26c>)
8000dfc: 681b ldr r3, [r3, #0]
8000dfe: f003 0302 and.w r3, r3, #2
8000e02: 2b00 cmp r3, #0
8000e04: d1f0 bne.n 8000de8 <HAL_RCC_OscConfig+0x1e4>
}
}
}
}
/*------------------------------ LSI Configuration -------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
8000e06: 687b ldr r3, [r7, #4]
8000e08: 681b ldr r3, [r3, #0]
8000e0a: f003 0308 and.w r3, r3, #8
8000e0e: 2b00 cmp r3, #0
8000e10: d03a beq.n 8000e88 <HAL_RCC_OscConfig+0x284>
{
/* Check the parameters */
assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
/* Check the LSI State */
if (RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
8000e12: 687b ldr r3, [r7, #4]
8000e14: 699b ldr r3, [r3, #24]
8000e16: 2b00 cmp r3, #0
8000e18: d019 beq.n 8000e4e <HAL_RCC_OscConfig+0x24a>
{
/* Enable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_ENABLE();
8000e1a: 4b17 ldr r3, [pc, #92] ; (8000e78 <HAL_RCC_OscConfig+0x274>)
8000e1c: 2201 movs r2, #1
8000e1e: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8000e20: f7ff fc5a bl 80006d8 <HAL_GetTick>
8000e24: 6138 str r0, [r7, #16]
/* Wait till LSI is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
8000e26: e008 b.n 8000e3a <HAL_RCC_OscConfig+0x236>
{
if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
8000e28: f7ff fc56 bl 80006d8 <HAL_GetTick>
8000e2c: 4602 mov r2, r0
8000e2e: 693b ldr r3, [r7, #16]
8000e30: 1ad3 subs r3, r2, r3
8000e32: 2b02 cmp r3, #2
8000e34: d901 bls.n 8000e3a <HAL_RCC_OscConfig+0x236>
{
return HAL_TIMEOUT;
8000e36: 2303 movs r3, #3
8000e38: e160 b.n 80010fc <HAL_RCC_OscConfig+0x4f8>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
8000e3a: 4b0d ldr r3, [pc, #52] ; (8000e70 <HAL_RCC_OscConfig+0x26c>)
8000e3c: 6a5b ldr r3, [r3, #36] ; 0x24
8000e3e: f003 0302 and.w r3, r3, #2
8000e42: 2b00 cmp r3, #0
8000e44: d0f0 beq.n 8000e28 <HAL_RCC_OscConfig+0x224>
}
}
/* To have a fully stabilized clock in the specified range, a software delay of 1ms
should be added.*/
RCC_Delay(1);
8000e46: 2001 movs r0, #1
8000e48: f000 faa6 bl 8001398 <RCC_Delay>
8000e4c: e01c b.n 8000e88 <HAL_RCC_OscConfig+0x284>
}
else
{
/* Disable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_DISABLE();
8000e4e: 4b0a ldr r3, [pc, #40] ; (8000e78 <HAL_RCC_OscConfig+0x274>)
8000e50: 2200 movs r2, #0
8000e52: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8000e54: f7ff fc40 bl 80006d8 <HAL_GetTick>
8000e58: 6138 str r0, [r7, #16]
/* Wait till LSI is disabled */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
8000e5a: e00f b.n 8000e7c <HAL_RCC_OscConfig+0x278>
{
if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
8000e5c: f7ff fc3c bl 80006d8 <HAL_GetTick>
8000e60: 4602 mov r2, r0
8000e62: 693b ldr r3, [r7, #16]
8000e64: 1ad3 subs r3, r2, r3
8000e66: 2b02 cmp r3, #2
8000e68: d908 bls.n 8000e7c <HAL_RCC_OscConfig+0x278>
{
return HAL_TIMEOUT;
8000e6a: 2303 movs r3, #3
8000e6c: e146 b.n 80010fc <HAL_RCC_OscConfig+0x4f8>
8000e6e: bf00 nop
8000e70: 40021000 .word 0x40021000
8000e74: 42420000 .word 0x42420000
8000e78: 42420480 .word 0x42420480
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
8000e7c: 4b92 ldr r3, [pc, #584] ; (80010c8 <HAL_RCC_OscConfig+0x4c4>)
8000e7e: 6a5b ldr r3, [r3, #36] ; 0x24
8000e80: f003 0302 and.w r3, r3, #2
8000e84: 2b00 cmp r3, #0
8000e86: d1e9 bne.n 8000e5c <HAL_RCC_OscConfig+0x258>
}
}
}
}
/*------------------------------ LSE Configuration -------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
8000e88: 687b ldr r3, [r7, #4]
8000e8a: 681b ldr r3, [r3, #0]
8000e8c: f003 0304 and.w r3, r3, #4
8000e90: 2b00 cmp r3, #0
8000e92: f000 80a6 beq.w 8000fe2 <HAL_RCC_OscConfig+0x3de>
{
FlagStatus pwrclkchanged = RESET;
8000e96: 2300 movs r3, #0
8000e98: 75fb strb r3, [r7, #23]
/* Check the parameters */
assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
/* Update LSE configuration in Backup Domain control register */
/* Requires to enable write access to Backup Domain of necessary */
if (__HAL_RCC_PWR_IS_CLK_DISABLED())
8000e9a: 4b8b ldr r3, [pc, #556] ; (80010c8 <HAL_RCC_OscConfig+0x4c4>)
8000e9c: 69db ldr r3, [r3, #28]
8000e9e: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
8000ea2: 2b00 cmp r3, #0
8000ea4: d10d bne.n 8000ec2 <HAL_RCC_OscConfig+0x2be>
{
__HAL_RCC_PWR_CLK_ENABLE();
8000ea6: 4b88 ldr r3, [pc, #544] ; (80010c8 <HAL_RCC_OscConfig+0x4c4>)
8000ea8: 69db ldr r3, [r3, #28]
8000eaa: 4a87 ldr r2, [pc, #540] ; (80010c8 <HAL_RCC_OscConfig+0x4c4>)
8000eac: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
8000eb0: 61d3 str r3, [r2, #28]
8000eb2: 4b85 ldr r3, [pc, #532] ; (80010c8 <HAL_RCC_OscConfig+0x4c4>)
8000eb4: 69db ldr r3, [r3, #28]
8000eb6: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
8000eba: 60bb str r3, [r7, #8]
8000ebc: 68bb ldr r3, [r7, #8]
pwrclkchanged = SET;
8000ebe: 2301 movs r3, #1
8000ec0: 75fb strb r3, [r7, #23]
}
if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
8000ec2: 4b82 ldr r3, [pc, #520] ; (80010cc <HAL_RCC_OscConfig+0x4c8>)
8000ec4: 681b ldr r3, [r3, #0]
8000ec6: f403 7380 and.w r3, r3, #256 ; 0x100
8000eca: 2b00 cmp r3, #0
8000ecc: d118 bne.n 8000f00 <HAL_RCC_OscConfig+0x2fc>
{
/* Enable write access to Backup domain */
SET_BIT(PWR->CR, PWR_CR_DBP);
8000ece: 4b7f ldr r3, [pc, #508] ; (80010cc <HAL_RCC_OscConfig+0x4c8>)
8000ed0: 681b ldr r3, [r3, #0]
8000ed2: 4a7e ldr r2, [pc, #504] ; (80010cc <HAL_RCC_OscConfig+0x4c8>)
8000ed4: f443 7380 orr.w r3, r3, #256 ; 0x100
8000ed8: 6013 str r3, [r2, #0]
/* Wait for Backup domain Write protection disable */
tickstart = HAL_GetTick();
8000eda: f7ff fbfd bl 80006d8 <HAL_GetTick>
8000ede: 6138 str r0, [r7, #16]
while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
8000ee0: e008 b.n 8000ef4 <HAL_RCC_OscConfig+0x2f0>
{
if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
8000ee2: f7ff fbf9 bl 80006d8 <HAL_GetTick>
8000ee6: 4602 mov r2, r0
8000ee8: 693b ldr r3, [r7, #16]
8000eea: 1ad3 subs r3, r2, r3
8000eec: 2b64 cmp r3, #100 ; 0x64
8000eee: d901 bls.n 8000ef4 <HAL_RCC_OscConfig+0x2f0>
{
return HAL_TIMEOUT;
8000ef0: 2303 movs r3, #3
8000ef2: e103 b.n 80010fc <HAL_RCC_OscConfig+0x4f8>
while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
8000ef4: 4b75 ldr r3, [pc, #468] ; (80010cc <HAL_RCC_OscConfig+0x4c8>)
8000ef6: 681b ldr r3, [r3, #0]
8000ef8: f403 7380 and.w r3, r3, #256 ; 0x100
8000efc: 2b00 cmp r3, #0
8000efe: d0f0 beq.n 8000ee2 <HAL_RCC_OscConfig+0x2de>
}
}
}
/* Set the new LSE configuration -----------------------------------------*/
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
8000f00: 687b ldr r3, [r7, #4]
8000f02: 68db ldr r3, [r3, #12]
8000f04: 2b01 cmp r3, #1
8000f06: d106 bne.n 8000f16 <HAL_RCC_OscConfig+0x312>
8000f08: 4b6f ldr r3, [pc, #444] ; (80010c8 <HAL_RCC_OscConfig+0x4c4>)
8000f0a: 6a1b ldr r3, [r3, #32]
8000f0c: 4a6e ldr r2, [pc, #440] ; (80010c8 <HAL_RCC_OscConfig+0x4c4>)
8000f0e: f043 0301 orr.w r3, r3, #1
8000f12: 6213 str r3, [r2, #32]
8000f14: e02d b.n 8000f72 <HAL_RCC_OscConfig+0x36e>
8000f16: 687b ldr r3, [r7, #4]
8000f18: 68db ldr r3, [r3, #12]
8000f1a: 2b00 cmp r3, #0
8000f1c: d10c bne.n 8000f38 <HAL_RCC_OscConfig+0x334>
8000f1e: 4b6a ldr r3, [pc, #424] ; (80010c8 <HAL_RCC_OscConfig+0x4c4>)
8000f20: 6a1b ldr r3, [r3, #32]
8000f22: 4a69 ldr r2, [pc, #420] ; (80010c8 <HAL_RCC_OscConfig+0x4c4>)
8000f24: f023 0301 bic.w r3, r3, #1
8000f28: 6213 str r3, [r2, #32]
8000f2a: 4b67 ldr r3, [pc, #412] ; (80010c8 <HAL_RCC_OscConfig+0x4c4>)
8000f2c: 6a1b ldr r3, [r3, #32]
8000f2e: 4a66 ldr r2, [pc, #408] ; (80010c8 <HAL_RCC_OscConfig+0x4c4>)
8000f30: f023 0304 bic.w r3, r3, #4
8000f34: 6213 str r3, [r2, #32]
8000f36: e01c b.n 8000f72 <HAL_RCC_OscConfig+0x36e>
8000f38: 687b ldr r3, [r7, #4]
8000f3a: 68db ldr r3, [r3, #12]
8000f3c: 2b05 cmp r3, #5
8000f3e: d10c bne.n 8000f5a <HAL_RCC_OscConfig+0x356>
8000f40: 4b61 ldr r3, [pc, #388] ; (80010c8 <HAL_RCC_OscConfig+0x4c4>)
8000f42: 6a1b ldr r3, [r3, #32]
8000f44: 4a60 ldr r2, [pc, #384] ; (80010c8 <HAL_RCC_OscConfig+0x4c4>)
8000f46: f043 0304 orr.w r3, r3, #4
8000f4a: 6213 str r3, [r2, #32]
8000f4c: 4b5e ldr r3, [pc, #376] ; (80010c8 <HAL_RCC_OscConfig+0x4c4>)
8000f4e: 6a1b ldr r3, [r3, #32]
8000f50: 4a5d ldr r2, [pc, #372] ; (80010c8 <HAL_RCC_OscConfig+0x4c4>)
8000f52: f043 0301 orr.w r3, r3, #1
8000f56: 6213 str r3, [r2, #32]
8000f58: e00b b.n 8000f72 <HAL_RCC_OscConfig+0x36e>
8000f5a: 4b5b ldr r3, [pc, #364] ; (80010c8 <HAL_RCC_OscConfig+0x4c4>)
8000f5c: 6a1b ldr r3, [r3, #32]
8000f5e: 4a5a ldr r2, [pc, #360] ; (80010c8 <HAL_RCC_OscConfig+0x4c4>)
8000f60: f023 0301 bic.w r3, r3, #1
8000f64: 6213 str r3, [r2, #32]
8000f66: 4b58 ldr r3, [pc, #352] ; (80010c8 <HAL_RCC_OscConfig+0x4c4>)
8000f68: 6a1b ldr r3, [r3, #32]
8000f6a: 4a57 ldr r2, [pc, #348] ; (80010c8 <HAL_RCC_OscConfig+0x4c4>)
8000f6c: f023 0304 bic.w r3, r3, #4
8000f70: 6213 str r3, [r2, #32]
/* Check the LSE State */
if (RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
8000f72: 687b ldr r3, [r7, #4]
8000f74: 68db ldr r3, [r3, #12]
8000f76: 2b00 cmp r3, #0
8000f78: d015 beq.n 8000fa6 <HAL_RCC_OscConfig+0x3a2>
{
/* Get Start Tick */
tickstart = HAL_GetTick();
8000f7a: f7ff fbad bl 80006d8 <HAL_GetTick>
8000f7e: 6138 str r0, [r7, #16]
/* Wait till LSE is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
8000f80: e00a b.n 8000f98 <HAL_RCC_OscConfig+0x394>
{
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
8000f82: f7ff fba9 bl 80006d8 <HAL_GetTick>
8000f86: 4602 mov r2, r0
8000f88: 693b ldr r3, [r7, #16]
8000f8a: 1ad3 subs r3, r2, r3
8000f8c: f241 3288 movw r2, #5000 ; 0x1388
8000f90: 4293 cmp r3, r2
8000f92: d901 bls.n 8000f98 <HAL_RCC_OscConfig+0x394>
{
return HAL_TIMEOUT;
8000f94: 2303 movs r3, #3
8000f96: e0b1 b.n 80010fc <HAL_RCC_OscConfig+0x4f8>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
8000f98: 4b4b ldr r3, [pc, #300] ; (80010c8 <HAL_RCC_OscConfig+0x4c4>)
8000f9a: 6a1b ldr r3, [r3, #32]
8000f9c: f003 0302 and.w r3, r3, #2
8000fa0: 2b00 cmp r3, #0
8000fa2: d0ee beq.n 8000f82 <HAL_RCC_OscConfig+0x37e>
8000fa4: e014 b.n 8000fd0 <HAL_RCC_OscConfig+0x3cc>
}
}
else
{
/* Get Start Tick */
tickstart = HAL_GetTick();
8000fa6: f7ff fb97 bl 80006d8 <HAL_GetTick>
8000faa: 6138 str r0, [r7, #16]
/* Wait till LSE is disabled */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
8000fac: e00a b.n 8000fc4 <HAL_RCC_OscConfig+0x3c0>
{
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
8000fae: f7ff fb93 bl 80006d8 <HAL_GetTick>
8000fb2: 4602 mov r2, r0
8000fb4: 693b ldr r3, [r7, #16]
8000fb6: 1ad3 subs r3, r2, r3
8000fb8: f241 3288 movw r2, #5000 ; 0x1388
8000fbc: 4293 cmp r3, r2
8000fbe: d901 bls.n 8000fc4 <HAL_RCC_OscConfig+0x3c0>
{
return HAL_TIMEOUT;
8000fc0: 2303 movs r3, #3
8000fc2: e09b b.n 80010fc <HAL_RCC_OscConfig+0x4f8>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
8000fc4: 4b40 ldr r3, [pc, #256] ; (80010c8 <HAL_RCC_OscConfig+0x4c4>)
8000fc6: 6a1b ldr r3, [r3, #32]
8000fc8: f003 0302 and.w r3, r3, #2
8000fcc: 2b00 cmp r3, #0
8000fce: d1ee bne.n 8000fae <HAL_RCC_OscConfig+0x3aa>
}
}
}
/* Require to disable power clock if necessary */
if (pwrclkchanged == SET)
8000fd0: 7dfb ldrb r3, [r7, #23]
8000fd2: 2b01 cmp r3, #1
8000fd4: d105 bne.n 8000fe2 <HAL_RCC_OscConfig+0x3de>
{
__HAL_RCC_PWR_CLK_DISABLE();
8000fd6: 4b3c ldr r3, [pc, #240] ; (80010c8 <HAL_RCC_OscConfig+0x4c4>)
8000fd8: 69db ldr r3, [r3, #28]
8000fda: 4a3b ldr r2, [pc, #236] ; (80010c8 <HAL_RCC_OscConfig+0x4c4>)
8000fdc: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000
8000fe0: 61d3 str r3, [r2, #28]
#endif /* RCC_CR_PLL2ON */
/*-------------------------------- PLL Configuration -----------------------*/
/* Check the parameters */
assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
8000fe2: 687b ldr r3, [r7, #4]
8000fe4: 69db ldr r3, [r3, #28]
8000fe6: 2b00 cmp r3, #0
8000fe8: f000 8087 beq.w 80010fa <HAL_RCC_OscConfig+0x4f6>
{
/* Check if the PLL is used as system clock or not */
if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
8000fec: 4b36 ldr r3, [pc, #216] ; (80010c8 <HAL_RCC_OscConfig+0x4c4>)
8000fee: 685b ldr r3, [r3, #4]
8000ff0: f003 030c and.w r3, r3, #12
8000ff4: 2b08 cmp r3, #8
8000ff6: d061 beq.n 80010bc <HAL_RCC_OscConfig+0x4b8>
{
if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
8000ff8: 687b ldr r3, [r7, #4]
8000ffa: 69db ldr r3, [r3, #28]
8000ffc: 2b02 cmp r3, #2
8000ffe: d146 bne.n 800108e <HAL_RCC_OscConfig+0x48a>
/* Check the parameters */
assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL));
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
8001000: 4b33 ldr r3, [pc, #204] ; (80010d0 <HAL_RCC_OscConfig+0x4cc>)
8001002: 2200 movs r2, #0
8001004: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8001006: f7ff fb67 bl 80006d8 <HAL_GetTick>
800100a: 6138 str r0, [r7, #16]
/* Wait till PLL is disabled */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
800100c: e008 b.n 8001020 <HAL_RCC_OscConfig+0x41c>
{
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
800100e: f7ff fb63 bl 80006d8 <HAL_GetTick>
8001012: 4602 mov r2, r0
8001014: 693b ldr r3, [r7, #16]
8001016: 1ad3 subs r3, r2, r3
8001018: 2b02 cmp r3, #2
800101a: d901 bls.n 8001020 <HAL_RCC_OscConfig+0x41c>
{
return HAL_TIMEOUT;
800101c: 2303 movs r3, #3
800101e: e06d b.n 80010fc <HAL_RCC_OscConfig+0x4f8>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8001020: 4b29 ldr r3, [pc, #164] ; (80010c8 <HAL_RCC_OscConfig+0x4c4>)
8001022: 681b ldr r3, [r3, #0]
8001024: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
8001028: 2b00 cmp r3, #0
800102a: d1f0 bne.n 800100e <HAL_RCC_OscConfig+0x40a>
}
}
/* Configure the HSE prediv factor --------------------------------*/
/* It can be written only when the PLL is disabled. Not used in PLL source is different than HSE */
if (RCC_OscInitStruct->PLL.PLLSource == RCC_PLLSOURCE_HSE)
800102c: 687b ldr r3, [r7, #4]
800102e: 6a1b ldr r3, [r3, #32]
8001030: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
8001034: d108 bne.n 8001048 <HAL_RCC_OscConfig+0x444>
/* Set PREDIV1 source */
SET_BIT(RCC->CFGR2, RCC_OscInitStruct->Prediv1Source);
#endif /* RCC_CFGR2_PREDIV1SRC */
/* Set PREDIV1 Value */
__HAL_RCC_HSE_PREDIV_CONFIG(RCC_OscInitStruct->HSEPredivValue);
8001036: 4b24 ldr r3, [pc, #144] ; (80010c8 <HAL_RCC_OscConfig+0x4c4>)
8001038: 685b ldr r3, [r3, #4]
800103a: f423 3200 bic.w r2, r3, #131072 ; 0x20000
800103e: 687b ldr r3, [r7, #4]
8001040: 689b ldr r3, [r3, #8]
8001042: 4921 ldr r1, [pc, #132] ; (80010c8 <HAL_RCC_OscConfig+0x4c4>)
8001044: 4313 orrs r3, r2
8001046: 604b str r3, [r1, #4]
}
/* Configure the main PLL clock source and multiplication factors. */
__HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
8001048: 4b1f ldr r3, [pc, #124] ; (80010c8 <HAL_RCC_OscConfig+0x4c4>)
800104a: 685b ldr r3, [r3, #4]
800104c: f423 1274 bic.w r2, r3, #3997696 ; 0x3d0000
8001050: 687b ldr r3, [r7, #4]
8001052: 6a19 ldr r1, [r3, #32]
8001054: 687b ldr r3, [r7, #4]
8001056: 6a5b ldr r3, [r3, #36] ; 0x24
8001058: 430b orrs r3, r1
800105a: 491b ldr r1, [pc, #108] ; (80010c8 <HAL_RCC_OscConfig+0x4c4>)
800105c: 4313 orrs r3, r2
800105e: 604b str r3, [r1, #4]
RCC_OscInitStruct->PLL.PLLMUL);
/* Enable the main PLL. */
__HAL_RCC_PLL_ENABLE();
8001060: 4b1b ldr r3, [pc, #108] ; (80010d0 <HAL_RCC_OscConfig+0x4cc>)
8001062: 2201 movs r2, #1
8001064: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8001066: f7ff fb37 bl 80006d8 <HAL_GetTick>
800106a: 6138 str r0, [r7, #16]
/* Wait till PLL is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
800106c: e008 b.n 8001080 <HAL_RCC_OscConfig+0x47c>
{
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
800106e: f7ff fb33 bl 80006d8 <HAL_GetTick>
8001072: 4602 mov r2, r0
8001074: 693b ldr r3, [r7, #16]
8001076: 1ad3 subs r3, r2, r3
8001078: 2b02 cmp r3, #2
800107a: d901 bls.n 8001080 <HAL_RCC_OscConfig+0x47c>
{
return HAL_TIMEOUT;
800107c: 2303 movs r3, #3
800107e: e03d b.n 80010fc <HAL_RCC_OscConfig+0x4f8>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
8001080: 4b11 ldr r3, [pc, #68] ; (80010c8 <HAL_RCC_OscConfig+0x4c4>)
8001082: 681b ldr r3, [r3, #0]
8001084: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
8001088: 2b00 cmp r3, #0
800108a: d0f0 beq.n 800106e <HAL_RCC_OscConfig+0x46a>
800108c: e035 b.n 80010fa <HAL_RCC_OscConfig+0x4f6>
}
}
else
{
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
800108e: 4b10 ldr r3, [pc, #64] ; (80010d0 <HAL_RCC_OscConfig+0x4cc>)
8001090: 2200 movs r2, #0
8001092: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8001094: f7ff fb20 bl 80006d8 <HAL_GetTick>
8001098: 6138 str r0, [r7, #16]
/* Wait till PLL is disabled */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
800109a: e008 b.n 80010ae <HAL_RCC_OscConfig+0x4aa>
{
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
800109c: f7ff fb1c bl 80006d8 <HAL_GetTick>
80010a0: 4602 mov r2, r0
80010a2: 693b ldr r3, [r7, #16]
80010a4: 1ad3 subs r3, r2, r3
80010a6: 2b02 cmp r3, #2
80010a8: d901 bls.n 80010ae <HAL_RCC_OscConfig+0x4aa>
{
return HAL_TIMEOUT;
80010aa: 2303 movs r3, #3
80010ac: e026 b.n 80010fc <HAL_RCC_OscConfig+0x4f8>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
80010ae: 4b06 ldr r3, [pc, #24] ; (80010c8 <HAL_RCC_OscConfig+0x4c4>)
80010b0: 681b ldr r3, [r3, #0]
80010b2: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
80010b6: 2b00 cmp r3, #0
80010b8: d1f0 bne.n 800109c <HAL_RCC_OscConfig+0x498>
80010ba: e01e b.n 80010fa <HAL_RCC_OscConfig+0x4f6>
}
}
else
{
/* Check if there is a request to disable the PLL used as System clock source */
if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
80010bc: 687b ldr r3, [r7, #4]
80010be: 69db ldr r3, [r3, #28]
80010c0: 2b01 cmp r3, #1
80010c2: d107 bne.n 80010d4 <HAL_RCC_OscConfig+0x4d0>
{
return HAL_ERROR;
80010c4: 2301 movs r3, #1
80010c6: e019 b.n 80010fc <HAL_RCC_OscConfig+0x4f8>
80010c8: 40021000 .word 0x40021000
80010cc: 40007000 .word 0x40007000
80010d0: 42420060 .word 0x42420060
}
else
{
/* Do not return HAL_ERROR if request repeats the current configuration */
pll_config = RCC->CFGR;
80010d4: 4b0b ldr r3, [pc, #44] ; (8001104 <HAL_RCC_OscConfig+0x500>)
80010d6: 685b ldr r3, [r3, #4]
80010d8: 60fb str r3, [r7, #12]
if ((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
80010da: 68fb ldr r3, [r7, #12]
80010dc: f403 3280 and.w r2, r3, #65536 ; 0x10000
80010e0: 687b ldr r3, [r7, #4]
80010e2: 6a1b ldr r3, [r3, #32]
80010e4: 429a cmp r2, r3
80010e6: d106 bne.n 80010f6 <HAL_RCC_OscConfig+0x4f2>
(READ_BIT(pll_config, RCC_CFGR_PLLMULL) != RCC_OscInitStruct->PLL.PLLMUL))
80010e8: 68fb ldr r3, [r7, #12]
80010ea: f403 1270 and.w r2, r3, #3932160 ; 0x3c0000
80010ee: 687b ldr r3, [r7, #4]
80010f0: 6a5b ldr r3, [r3, #36] ; 0x24
if ((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
80010f2: 429a cmp r2, r3
80010f4: d001 beq.n 80010fa <HAL_RCC_OscConfig+0x4f6>
{
return HAL_ERROR;
80010f6: 2301 movs r3, #1
80010f8: e000 b.n 80010fc <HAL_RCC_OscConfig+0x4f8>
}
}
}
}
return HAL_OK;
80010fa: 2300 movs r3, #0
}
80010fc: 4618 mov r0, r3
80010fe: 3718 adds r7, #24
8001100: 46bd mov sp, r7
8001102: bd80 pop {r7, pc}
8001104: 40021000 .word 0x40021000
08001108 <HAL_RCC_ClockConfig>:
* You can use @ref HAL_RCC_GetClockConfig() function to know which clock is
* currently used as system clock source.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
{
8001108: b580 push {r7, lr}
800110a: b084 sub sp, #16
800110c: af00 add r7, sp, #0
800110e: 6078 str r0, [r7, #4]
8001110: 6039 str r1, [r7, #0]
uint32_t tickstart;
/* Check Null pointer */
if (RCC_ClkInitStruct == NULL)
8001112: 687b ldr r3, [r7, #4]
8001114: 2b00 cmp r3, #0
8001116: d101 bne.n 800111c <HAL_RCC_ClockConfig+0x14>
{
return HAL_ERROR;
8001118: 2301 movs r3, #1
800111a: e0d0 b.n 80012be <HAL_RCC_ClockConfig+0x1b6>
must be correctly programmed according to the frequency of the CPU clock
(HCLK) of the device. */
#if defined(FLASH_ACR_LATENCY)
/* Increasing the number of wait states because of higher CPU frequency */
if (FLatency > __HAL_FLASH_GET_LATENCY())
800111c: 4b6a ldr r3, [pc, #424] ; (80012c8 <HAL_RCC_ClockConfig+0x1c0>)
800111e: 681b ldr r3, [r3, #0]
8001120: f003 0307 and.w r3, r3, #7
8001124: 683a ldr r2, [r7, #0]
8001126: 429a cmp r2, r3
8001128: d910 bls.n 800114c <HAL_RCC_ClockConfig+0x44>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
800112a: 4b67 ldr r3, [pc, #412] ; (80012c8 <HAL_RCC_ClockConfig+0x1c0>)
800112c: 681b ldr r3, [r3, #0]
800112e: f023 0207 bic.w r2, r3, #7
8001132: 4965 ldr r1, [pc, #404] ; (80012c8 <HAL_RCC_ClockConfig+0x1c0>)
8001134: 683b ldr r3, [r7, #0]
8001136: 4313 orrs r3, r2
8001138: 600b str r3, [r1, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if (__HAL_FLASH_GET_LATENCY() != FLatency)
800113a: 4b63 ldr r3, [pc, #396] ; (80012c8 <HAL_RCC_ClockConfig+0x1c0>)
800113c: 681b ldr r3, [r3, #0]
800113e: f003 0307 and.w r3, r3, #7
8001142: 683a ldr r2, [r7, #0]
8001144: 429a cmp r2, r3
8001146: d001 beq.n 800114c <HAL_RCC_ClockConfig+0x44>
{
return HAL_ERROR;
8001148: 2301 movs r3, #1
800114a: e0b8 b.n 80012be <HAL_RCC_ClockConfig+0x1b6>
}
}
#endif /* FLASH_ACR_LATENCY */
/*-------------------------- HCLK Configuration --------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
800114c: 687b ldr r3, [r7, #4]
800114e: 681b ldr r3, [r3, #0]
8001150: f003 0302 and.w r3, r3, #2
8001154: 2b00 cmp r3, #0
8001156: d020 beq.n 800119a <HAL_RCC_ClockConfig+0x92>
{
/* Set the highest APBx dividers in order to ensure that we do not go through
a non-spec phase whatever we decrease or increase HCLK. */
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
8001158: 687b ldr r3, [r7, #4]
800115a: 681b ldr r3, [r3, #0]
800115c: f003 0304 and.w r3, r3, #4
8001160: 2b00 cmp r3, #0
8001162: d005 beq.n 8001170 <HAL_RCC_ClockConfig+0x68>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16);
8001164: 4b59 ldr r3, [pc, #356] ; (80012cc <HAL_RCC_ClockConfig+0x1c4>)
8001166: 685b ldr r3, [r3, #4]
8001168: 4a58 ldr r2, [pc, #352] ; (80012cc <HAL_RCC_ClockConfig+0x1c4>)
800116a: f443 63e0 orr.w r3, r3, #1792 ; 0x700
800116e: 6053 str r3, [r2, #4]
}
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
8001170: 687b ldr r3, [r7, #4]
8001172: 681b ldr r3, [r3, #0]
8001174: f003 0308 and.w r3, r3, #8
8001178: 2b00 cmp r3, #0
800117a: d005 beq.n 8001188 <HAL_RCC_ClockConfig+0x80>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3));
800117c: 4b53 ldr r3, [pc, #332] ; (80012cc <HAL_RCC_ClockConfig+0x1c4>)
800117e: 685b ldr r3, [r3, #4]
8001180: 4a52 ldr r2, [pc, #328] ; (80012cc <HAL_RCC_ClockConfig+0x1c4>)
8001182: f443 5360 orr.w r3, r3, #14336 ; 0x3800
8001186: 6053 str r3, [r2, #4]
}
/* Set the new HCLK clock divider */
assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
8001188: 4b50 ldr r3, [pc, #320] ; (80012cc <HAL_RCC_ClockConfig+0x1c4>)
800118a: 685b ldr r3, [r3, #4]
800118c: f023 02f0 bic.w r2, r3, #240 ; 0xf0
8001190: 687b ldr r3, [r7, #4]
8001192: 689b ldr r3, [r3, #8]
8001194: 494d ldr r1, [pc, #308] ; (80012cc <HAL_RCC_ClockConfig+0x1c4>)
8001196: 4313 orrs r3, r2
8001198: 604b str r3, [r1, #4]
}
/*------------------------- SYSCLK Configuration ---------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
800119a: 687b ldr r3, [r7, #4]
800119c: 681b ldr r3, [r3, #0]
800119e: f003 0301 and.w r3, r3, #1
80011a2: 2b00 cmp r3, #0
80011a4: d040 beq.n 8001228 <HAL_RCC_ClockConfig+0x120>
{
assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
/* HSE is selected as System Clock Source */
if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
80011a6: 687b ldr r3, [r7, #4]
80011a8: 685b ldr r3, [r3, #4]
80011aa: 2b01 cmp r3, #1
80011ac: d107 bne.n 80011be <HAL_RCC_ClockConfig+0xb6>
{
/* Check the HSE ready flag */
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
80011ae: 4b47 ldr r3, [pc, #284] ; (80012cc <HAL_RCC_ClockConfig+0x1c4>)
80011b0: 681b ldr r3, [r3, #0]
80011b2: f403 3300 and.w r3, r3, #131072 ; 0x20000
80011b6: 2b00 cmp r3, #0
80011b8: d115 bne.n 80011e6 <HAL_RCC_ClockConfig+0xde>
{
return HAL_ERROR;
80011ba: 2301 movs r3, #1
80011bc: e07f b.n 80012be <HAL_RCC_ClockConfig+0x1b6>
}
}
/* PLL is selected as System Clock Source */
else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
80011be: 687b ldr r3, [r7, #4]
80011c0: 685b ldr r3, [r3, #4]
80011c2: 2b02 cmp r3, #2
80011c4: d107 bne.n 80011d6 <HAL_RCC_ClockConfig+0xce>
{
/* Check the PLL ready flag */
if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
80011c6: 4b41 ldr r3, [pc, #260] ; (80012cc <HAL_RCC_ClockConfig+0x1c4>)
80011c8: 681b ldr r3, [r3, #0]
80011ca: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
80011ce: 2b00 cmp r3, #0
80011d0: d109 bne.n 80011e6 <HAL_RCC_ClockConfig+0xde>
{
return HAL_ERROR;
80011d2: 2301 movs r3, #1
80011d4: e073 b.n 80012be <HAL_RCC_ClockConfig+0x1b6>
}
/* HSI is selected as System Clock Source */
else
{
/* Check the HSI ready flag */
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
80011d6: 4b3d ldr r3, [pc, #244] ; (80012cc <HAL_RCC_ClockConfig+0x1c4>)
80011d8: 681b ldr r3, [r3, #0]
80011da: f003 0302 and.w r3, r3, #2
80011de: 2b00 cmp r3, #0
80011e0: d101 bne.n 80011e6 <HAL_RCC_ClockConfig+0xde>
{
return HAL_ERROR;
80011e2: 2301 movs r3, #1
80011e4: e06b b.n 80012be <HAL_RCC_ClockConfig+0x1b6>
}
}
__HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
80011e6: 4b39 ldr r3, [pc, #228] ; (80012cc <HAL_RCC_ClockConfig+0x1c4>)
80011e8: 685b ldr r3, [r3, #4]
80011ea: f023 0203 bic.w r2, r3, #3
80011ee: 687b ldr r3, [r7, #4]
80011f0: 685b ldr r3, [r3, #4]
80011f2: 4936 ldr r1, [pc, #216] ; (80012cc <HAL_RCC_ClockConfig+0x1c4>)
80011f4: 4313 orrs r3, r2
80011f6: 604b str r3, [r1, #4]
/* Get Start Tick */
tickstart = HAL_GetTick();
80011f8: f7ff fa6e bl 80006d8 <HAL_GetTick>
80011fc: 60f8 str r0, [r7, #12]
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
80011fe: e00a b.n 8001216 <HAL_RCC_ClockConfig+0x10e>
{
if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
8001200: f7ff fa6a bl 80006d8 <HAL_GetTick>
8001204: 4602 mov r2, r0
8001206: 68fb ldr r3, [r7, #12]
8001208: 1ad3 subs r3, r2, r3
800120a: f241 3288 movw r2, #5000 ; 0x1388
800120e: 4293 cmp r3, r2
8001210: d901 bls.n 8001216 <HAL_RCC_ClockConfig+0x10e>
{
return HAL_TIMEOUT;
8001212: 2303 movs r3, #3
8001214: e053 b.n 80012be <HAL_RCC_ClockConfig+0x1b6>
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
8001216: 4b2d ldr r3, [pc, #180] ; (80012cc <HAL_RCC_ClockConfig+0x1c4>)
8001218: 685b ldr r3, [r3, #4]
800121a: f003 020c and.w r2, r3, #12
800121e: 687b ldr r3, [r7, #4]
8001220: 685b ldr r3, [r3, #4]
8001222: 009b lsls r3, r3, #2
8001224: 429a cmp r2, r3
8001226: d1eb bne.n 8001200 <HAL_RCC_ClockConfig+0xf8>
}
}
#if defined(FLASH_ACR_LATENCY)
/* Decreasing the number of wait states because of lower CPU frequency */
if (FLatency < __HAL_FLASH_GET_LATENCY())
8001228: 4b27 ldr r3, [pc, #156] ; (80012c8 <HAL_RCC_ClockConfig+0x1c0>)
800122a: 681b ldr r3, [r3, #0]
800122c: f003 0307 and.w r3, r3, #7
8001230: 683a ldr r2, [r7, #0]
8001232: 429a cmp r2, r3
8001234: d210 bcs.n 8001258 <HAL_RCC_ClockConfig+0x150>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
8001236: 4b24 ldr r3, [pc, #144] ; (80012c8 <HAL_RCC_ClockConfig+0x1c0>)
8001238: 681b ldr r3, [r3, #0]
800123a: f023 0207 bic.w r2, r3, #7
800123e: 4922 ldr r1, [pc, #136] ; (80012c8 <HAL_RCC_ClockConfig+0x1c0>)
8001240: 683b ldr r3, [r7, #0]
8001242: 4313 orrs r3, r2
8001244: 600b str r3, [r1, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if (__HAL_FLASH_GET_LATENCY() != FLatency)
8001246: 4b20 ldr r3, [pc, #128] ; (80012c8 <HAL_RCC_ClockConfig+0x1c0>)
8001248: 681b ldr r3, [r3, #0]
800124a: f003 0307 and.w r3, r3, #7
800124e: 683a ldr r2, [r7, #0]
8001250: 429a cmp r2, r3
8001252: d001 beq.n 8001258 <HAL_RCC_ClockConfig+0x150>
{
return HAL_ERROR;
8001254: 2301 movs r3, #1
8001256: e032 b.n 80012be <HAL_RCC_ClockConfig+0x1b6>
}
}
#endif /* FLASH_ACR_LATENCY */
/*-------------------------- PCLK1 Configuration ---------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
8001258: 687b ldr r3, [r7, #4]
800125a: 681b ldr r3, [r3, #0]
800125c: f003 0304 and.w r3, r3, #4
8001260: 2b00 cmp r3, #0
8001262: d008 beq.n 8001276 <HAL_RCC_ClockConfig+0x16e>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
8001264: 4b19 ldr r3, [pc, #100] ; (80012cc <HAL_RCC_ClockConfig+0x1c4>)
8001266: 685b ldr r3, [r3, #4]
8001268: f423 62e0 bic.w r2, r3, #1792 ; 0x700
800126c: 687b ldr r3, [r7, #4]
800126e: 68db ldr r3, [r3, #12]
8001270: 4916 ldr r1, [pc, #88] ; (80012cc <HAL_RCC_ClockConfig+0x1c4>)
8001272: 4313 orrs r3, r2
8001274: 604b str r3, [r1, #4]
}
/*-------------------------- PCLK2 Configuration ---------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
8001276: 687b ldr r3, [r7, #4]
8001278: 681b ldr r3, [r3, #0]
800127a: f003 0308 and.w r3, r3, #8
800127e: 2b00 cmp r3, #0
8001280: d009 beq.n 8001296 <HAL_RCC_ClockConfig+0x18e>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3));
8001282: 4b12 ldr r3, [pc, #72] ; (80012cc <HAL_RCC_ClockConfig+0x1c4>)
8001284: 685b ldr r3, [r3, #4]
8001286: f423 5260 bic.w r2, r3, #14336 ; 0x3800
800128a: 687b ldr r3, [r7, #4]
800128c: 691b ldr r3, [r3, #16]
800128e: 00db lsls r3, r3, #3
8001290: 490e ldr r1, [pc, #56] ; (80012cc <HAL_RCC_ClockConfig+0x1c4>)
8001292: 4313 orrs r3, r2
8001294: 604b str r3, [r1, #4]
}
/* Update the SystemCoreClock global variable */
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos];
8001296: f000 f821 bl 80012dc <HAL_RCC_GetSysClockFreq>
800129a: 4602 mov r2, r0
800129c: 4b0b ldr r3, [pc, #44] ; (80012cc <HAL_RCC_ClockConfig+0x1c4>)
800129e: 685b ldr r3, [r3, #4]
80012a0: 091b lsrs r3, r3, #4
80012a2: f003 030f and.w r3, r3, #15
80012a6: 490a ldr r1, [pc, #40] ; (80012d0 <HAL_RCC_ClockConfig+0x1c8>)
80012a8: 5ccb ldrb r3, [r1, r3]
80012aa: fa22 f303 lsr.w r3, r2, r3
80012ae: 4a09 ldr r2, [pc, #36] ; (80012d4 <HAL_RCC_ClockConfig+0x1cc>)
80012b0: 6013 str r3, [r2, #0]
/* Configure the source of time base considering new system clocks settings*/
HAL_InitTick(uwTickPrio);
80012b2: 4b09 ldr r3, [pc, #36] ; (80012d8 <HAL_RCC_ClockConfig+0x1d0>)
80012b4: 681b ldr r3, [r3, #0]
80012b6: 4618 mov r0, r3
80012b8: f7ff f9cc bl 8000654 <HAL_InitTick>
return HAL_OK;
80012bc: 2300 movs r3, #0
}
80012be: 4618 mov r0, r3
80012c0: 3710 adds r7, #16
80012c2: 46bd mov sp, r7
80012c4: bd80 pop {r7, pc}
80012c6: bf00 nop
80012c8: 40022000 .word 0x40022000
80012cc: 40021000 .word 0x40021000
80012d0: 08001ff0 .word 0x08001ff0
80012d4: 20000000 .word 0x20000000
80012d8: 20000004 .word 0x20000004
080012dc <HAL_RCC_GetSysClockFreq>:
* right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
*
* @retval SYSCLK frequency
*/
uint32_t HAL_RCC_GetSysClockFreq(void)
{
80012dc: b490 push {r4, r7}
80012de: b08a sub sp, #40 ; 0x28
80012e0: af00 add r7, sp, #0
#if defined(RCC_CFGR2_PREDIV1SRC)
const uint8_t aPLLMULFactorTable[14] = {0, 0, 4, 5, 6, 7, 8, 9, 0, 0, 0, 0, 0, 13};
const uint8_t aPredivFactorTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16};
#else
const uint8_t aPLLMULFactorTable[16] = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16};
80012e2: 4b29 ldr r3, [pc, #164] ; (8001388 <HAL_RCC_GetSysClockFreq+0xac>)
80012e4: 1d3c adds r4, r7, #4
80012e6: cb0f ldmia r3, {r0, r1, r2, r3}
80012e8: e884 000f stmia.w r4, {r0, r1, r2, r3}
#if defined(RCC_CFGR2_PREDIV1)
const uint8_t aPredivFactorTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16};
#else
const uint8_t aPredivFactorTable[2] = {1, 2};
80012ec: f240 2301 movw r3, #513 ; 0x201
80012f0: 803b strh r3, [r7, #0]
#endif /*RCC_CFGR2_PREDIV1*/
#endif
uint32_t tmpreg = 0U, prediv = 0U, pllclk = 0U, pllmul = 0U;
80012f2: 2300 movs r3, #0
80012f4: 61fb str r3, [r7, #28]
80012f6: 2300 movs r3, #0
80012f8: 61bb str r3, [r7, #24]
80012fa: 2300 movs r3, #0
80012fc: 627b str r3, [r7, #36] ; 0x24
80012fe: 2300 movs r3, #0
8001300: 617b str r3, [r7, #20]
uint32_t sysclockfreq = 0U;
8001302: 2300 movs r3, #0
8001304: 623b str r3, [r7, #32]
#if defined(RCC_CFGR2_PREDIV1SRC)
uint32_t prediv2 = 0U, pll2mul = 0U;
#endif /*RCC_CFGR2_PREDIV1SRC*/
tmpreg = RCC->CFGR;
8001306: 4b21 ldr r3, [pc, #132] ; (800138c <HAL_RCC_GetSysClockFreq+0xb0>)
8001308: 685b ldr r3, [r3, #4]
800130a: 61fb str r3, [r7, #28]
/* Get SYSCLK source -------------------------------------------------------*/
switch (tmpreg & RCC_CFGR_SWS)
800130c: 69fb ldr r3, [r7, #28]
800130e: f003 030c and.w r3, r3, #12
8001312: 2b04 cmp r3, #4
8001314: d002 beq.n 800131c <HAL_RCC_GetSysClockFreq+0x40>
8001316: 2b08 cmp r3, #8
8001318: d003 beq.n 8001322 <HAL_RCC_GetSysClockFreq+0x46>
800131a: e02b b.n 8001374 <HAL_RCC_GetSysClockFreq+0x98>
{
case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */
{
sysclockfreq = HSE_VALUE;
800131c: 4b1c ldr r3, [pc, #112] ; (8001390 <HAL_RCC_GetSysClockFreq+0xb4>)
800131e: 623b str r3, [r7, #32]
break;
8001320: e02b b.n 800137a <HAL_RCC_GetSysClockFreq+0x9e>
}
case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */
{
pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos];
8001322: 69fb ldr r3, [r7, #28]
8001324: 0c9b lsrs r3, r3, #18
8001326: f003 030f and.w r3, r3, #15
800132a: 3328 adds r3, #40 ; 0x28
800132c: 443b add r3, r7
800132e: f813 3c24 ldrb.w r3, [r3, #-36]
8001332: 617b str r3, [r7, #20]
if ((tmpreg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2)
8001334: 69fb ldr r3, [r7, #28]
8001336: f403 3380 and.w r3, r3, #65536 ; 0x10000
800133a: 2b00 cmp r3, #0
800133c: d012 beq.n 8001364 <HAL_RCC_GetSysClockFreq+0x88>
{
#if defined(RCC_CFGR2_PREDIV1)
prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> RCC_CFGR2_PREDIV1_Pos];
#else
prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos];
800133e: 4b13 ldr r3, [pc, #76] ; (800138c <HAL_RCC_GetSysClockFreq+0xb0>)
8001340: 685b ldr r3, [r3, #4]
8001342: 0c5b lsrs r3, r3, #17
8001344: f003 0301 and.w r3, r3, #1
8001348: 3328 adds r3, #40 ; 0x28
800134a: 443b add r3, r7
800134c: f813 3c28 ldrb.w r3, [r3, #-40]
8001350: 61bb str r3, [r7, #24]
{
pllclk = pllclk / 2;
}
#else
/* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */
pllclk = (uint32_t)((HSE_VALUE * pllmul) / prediv);
8001352: 697b ldr r3, [r7, #20]
8001354: 4a0e ldr r2, [pc, #56] ; (8001390 <HAL_RCC_GetSysClockFreq+0xb4>)
8001356: fb03 f202 mul.w r2, r3, r2
800135a: 69bb ldr r3, [r7, #24]
800135c: fbb2 f3f3 udiv r3, r2, r3
8001360: 627b str r3, [r7, #36] ; 0x24
8001362: e004 b.n 800136e <HAL_RCC_GetSysClockFreq+0x92>
#endif /*RCC_CFGR2_PREDIV1SRC*/
}
else
{
/* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */
pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul);
8001364: 697b ldr r3, [r7, #20]
8001366: 4a0b ldr r2, [pc, #44] ; (8001394 <HAL_RCC_GetSysClockFreq+0xb8>)
8001368: fb02 f303 mul.w r3, r2, r3
800136c: 627b str r3, [r7, #36] ; 0x24
}
sysclockfreq = pllclk;
800136e: 6a7b ldr r3, [r7, #36] ; 0x24
8001370: 623b str r3, [r7, #32]
break;
8001372: e002 b.n 800137a <HAL_RCC_GetSysClockFreq+0x9e>
}
case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
default: /* HSI used as system clock */
{
sysclockfreq = HSI_VALUE;
8001374: 4b06 ldr r3, [pc, #24] ; (8001390 <HAL_RCC_GetSysClockFreq+0xb4>)
8001376: 623b str r3, [r7, #32]
break;
8001378: bf00 nop
}
}
return sysclockfreq;
800137a: 6a3b ldr r3, [r7, #32]
}
800137c: 4618 mov r0, r3
800137e: 3728 adds r7, #40 ; 0x28
8001380: 46bd mov sp, r7
8001382: bc90 pop {r4, r7}
8001384: 4770 bx lr
8001386: bf00 nop
8001388: 08001fe0 .word 0x08001fe0
800138c: 40021000 .word 0x40021000
8001390: 007a1200 .word 0x007a1200
8001394: 003d0900 .word 0x003d0900
08001398 <RCC_Delay>:
* @brief This function provides delay (in milliseconds) based on CPU cycles method.
* @param mdelay: specifies the delay time length, in milliseconds.
* @retval None
*/
static void RCC_Delay(uint32_t mdelay)
{
8001398: b480 push {r7}
800139a: b085 sub sp, #20
800139c: af00 add r7, sp, #0
800139e: 6078 str r0, [r7, #4]
__IO uint32_t Delay = mdelay * (SystemCoreClock / 8U / 1000U);
80013a0: 4b0a ldr r3, [pc, #40] ; (80013cc <RCC_Delay+0x34>)
80013a2: 681b ldr r3, [r3, #0]
80013a4: 4a0a ldr r2, [pc, #40] ; (80013d0 <RCC_Delay+0x38>)
80013a6: fba2 2303 umull r2, r3, r2, r3
80013aa: 0a5b lsrs r3, r3, #9
80013ac: 687a ldr r2, [r7, #4]
80013ae: fb02 f303 mul.w r3, r2, r3
80013b2: 60fb str r3, [r7, #12]
do
{
__NOP();
80013b4: bf00 nop
}
while (Delay --);
80013b6: 68fb ldr r3, [r7, #12]
80013b8: 1e5a subs r2, r3, #1
80013ba: 60fa str r2, [r7, #12]
80013bc: 2b00 cmp r3, #0
80013be: d1f9 bne.n 80013b4 <RCC_Delay+0x1c>
}
80013c0: bf00 nop
80013c2: bf00 nop
80013c4: 3714 adds r7, #20
80013c6: 46bd mov sp, r7
80013c8: bc80 pop {r7}
80013ca: 4770 bx lr
80013cc: 20000000 .word 0x20000000
80013d0: 10624dd3 .word 0x10624dd3
080013d4 <HAL_TIM_Base_Init>:
* Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
* @param htim TIM Base handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
{
80013d4: b580 push {r7, lr}
80013d6: b082 sub sp, #8
80013d8: af00 add r7, sp, #0
80013da: 6078 str r0, [r7, #4]
/* Check the TIM handle allocation */
if (htim == NULL)
80013dc: 687b ldr r3, [r7, #4]
80013de: 2b00 cmp r3, #0
80013e0: d101 bne.n 80013e6 <HAL_TIM_Base_Init+0x12>
{
return HAL_ERROR;
80013e2: 2301 movs r3, #1
80013e4: e041 b.n 800146a <HAL_TIM_Base_Init+0x96>
assert_param(IS_TIM_INSTANCE(htim->Instance));
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
if (htim->State == HAL_TIM_STATE_RESET)
80013e6: 687b ldr r3, [r7, #4]
80013e8: f893 303d ldrb.w r3, [r3, #61] ; 0x3d
80013ec: b2db uxtb r3, r3
80013ee: 2b00 cmp r3, #0
80013f0: d106 bne.n 8001400 <HAL_TIM_Base_Init+0x2c>
{
/* Allocate lock resource and initialize it */
htim->Lock = HAL_UNLOCKED;
80013f2: 687b ldr r3, [r7, #4]
80013f4: 2200 movs r2, #0
80013f6: f883 203c strb.w r2, [r3, #60] ; 0x3c
}
/* Init the low level hardware : GPIO, CLOCK, NVIC */
htim->Base_MspInitCallback(htim);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC */
HAL_TIM_Base_MspInit(htim);
80013fa: 6878 ldr r0, [r7, #4]
80013fc: f7ff f884 bl 8000508 <HAL_TIM_Base_MspInit>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
/* Set the TIM state */
htim->State = HAL_TIM_STATE_BUSY;
8001400: 687b ldr r3, [r7, #4]
8001402: 2202 movs r2, #2
8001404: f883 203d strb.w r2, [r3, #61] ; 0x3d
/* Set the Time Base configuration */
TIM_Base_SetConfig(htim->Instance, &htim->Init);
8001408: 687b ldr r3, [r7, #4]
800140a: 681a ldr r2, [r3, #0]
800140c: 687b ldr r3, [r7, #4]
800140e: 3304 adds r3, #4
8001410: 4619 mov r1, r3
8001412: 4610 mov r0, r2
8001414: f000 faaa bl 800196c <TIM_Base_SetConfig>
/* Initialize the DMA burst operation state */
htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
8001418: 687b ldr r3, [r7, #4]
800141a: 2201 movs r2, #1
800141c: f883 2046 strb.w r2, [r3, #70] ; 0x46
/* Initialize the TIM channels state */
TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
8001420: 687b ldr r3, [r7, #4]
8001422: 2201 movs r2, #1
8001424: f883 203e strb.w r2, [r3, #62] ; 0x3e
8001428: 687b ldr r3, [r7, #4]
800142a: 2201 movs r2, #1
800142c: f883 203f strb.w r2, [r3, #63] ; 0x3f
8001430: 687b ldr r3, [r7, #4]
8001432: 2201 movs r2, #1
8001434: f883 2040 strb.w r2, [r3, #64] ; 0x40
8001438: 687b ldr r3, [r7, #4]
800143a: 2201 movs r2, #1
800143c: f883 2041 strb.w r2, [r3, #65] ; 0x41
TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
8001440: 687b ldr r3, [r7, #4]
8001442: 2201 movs r2, #1
8001444: f883 2042 strb.w r2, [r3, #66] ; 0x42
8001448: 687b ldr r3, [r7, #4]
800144a: 2201 movs r2, #1
800144c: f883 2043 strb.w r2, [r3, #67] ; 0x43
8001450: 687b ldr r3, [r7, #4]
8001452: 2201 movs r2, #1
8001454: f883 2044 strb.w r2, [r3, #68] ; 0x44
8001458: 687b ldr r3, [r7, #4]
800145a: 2201 movs r2, #1
800145c: f883 2045 strb.w r2, [r3, #69] ; 0x45
/* Initialize the TIM state*/
htim->State = HAL_TIM_STATE_READY;
8001460: 687b ldr r3, [r7, #4]
8001462: 2201 movs r2, #1
8001464: f883 203d strb.w r2, [r3, #61] ; 0x3d
return HAL_OK;
8001468: 2300 movs r3, #0
}
800146a: 4618 mov r0, r3
800146c: 3708 adds r7, #8
800146e: 46bd mov sp, r7
8001470: bd80 pop {r7, pc}
08001472 <HAL_TIM_PWM_Init>:
* Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init()
* @param htim TIM PWM handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
{
8001472: b580 push {r7, lr}
8001474: b082 sub sp, #8
8001476: af00 add r7, sp, #0
8001478: 6078 str r0, [r7, #4]
/* Check the TIM handle allocation */
if (htim == NULL)
800147a: 687b ldr r3, [r7, #4]
800147c: 2b00 cmp r3, #0
800147e: d101 bne.n 8001484 <HAL_TIM_PWM_Init+0x12>
{
return HAL_ERROR;
8001480: 2301 movs r3, #1
8001482: e041 b.n 8001508 <HAL_TIM_PWM_Init+0x96>
assert_param(IS_TIM_INSTANCE(htim->Instance));
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
if (htim->State == HAL_TIM_STATE_RESET)
8001484: 687b ldr r3, [r7, #4]
8001486: f893 303d ldrb.w r3, [r3, #61] ; 0x3d
800148a: b2db uxtb r3, r3
800148c: 2b00 cmp r3, #0
800148e: d106 bne.n 800149e <HAL_TIM_PWM_Init+0x2c>
{
/* Allocate lock resource and initialize it */
htim->Lock = HAL_UNLOCKED;
8001490: 687b ldr r3, [r7, #4]
8001492: 2200 movs r2, #0
8001494: f883 203c strb.w r2, [r3, #60] ; 0x3c
}
/* Init the low level hardware : GPIO, CLOCK, NVIC */
htim->PWM_MspInitCallback(htim);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
HAL_TIM_PWM_MspInit(htim);
8001498: 6878 ldr r0, [r7, #4]
800149a: f000 f839 bl 8001510 <HAL_TIM_PWM_MspInit>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
/* Set the TIM state */
htim->State = HAL_TIM_STATE_BUSY;
800149e: 687b ldr r3, [r7, #4]
80014a0: 2202 movs r2, #2
80014a2: f883 203d strb.w r2, [r3, #61] ; 0x3d
/* Init the base time for the PWM */
TIM_Base_SetConfig(htim->Instance, &htim->Init);
80014a6: 687b ldr r3, [r7, #4]
80014a8: 681a ldr r2, [r3, #0]
80014aa: 687b ldr r3, [r7, #4]
80014ac: 3304 adds r3, #4
80014ae: 4619 mov r1, r3
80014b0: 4610 mov r0, r2
80014b2: f000 fa5b bl 800196c <TIM_Base_SetConfig>
/* Initialize the DMA burst operation state */
htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
80014b6: 687b ldr r3, [r7, #4]
80014b8: 2201 movs r2, #1
80014ba: f883 2046 strb.w r2, [r3, #70] ; 0x46
/* Initialize the TIM channels state */
TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
80014be: 687b ldr r3, [r7, #4]
80014c0: 2201 movs r2, #1
80014c2: f883 203e strb.w r2, [r3, #62] ; 0x3e
80014c6: 687b ldr r3, [r7, #4]
80014c8: 2201 movs r2, #1
80014ca: f883 203f strb.w r2, [r3, #63] ; 0x3f
80014ce: 687b ldr r3, [r7, #4]
80014d0: 2201 movs r2, #1
80014d2: f883 2040 strb.w r2, [r3, #64] ; 0x40
80014d6: 687b ldr r3, [r7, #4]
80014d8: 2201 movs r2, #1
80014da: f883 2041 strb.w r2, [r3, #65] ; 0x41
TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
80014de: 687b ldr r3, [r7, #4]
80014e0: 2201 movs r2, #1
80014e2: f883 2042 strb.w r2, [r3, #66] ; 0x42
80014e6: 687b ldr r3, [r7, #4]
80014e8: 2201 movs r2, #1
80014ea: f883 2043 strb.w r2, [r3, #67] ; 0x43
80014ee: 687b ldr r3, [r7, #4]
80014f0: 2201 movs r2, #1
80014f2: f883 2044 strb.w r2, [r3, #68] ; 0x44
80014f6: 687b ldr r3, [r7, #4]
80014f8: 2201 movs r2, #1
80014fa: f883 2045 strb.w r2, [r3, #69] ; 0x45
/* Initialize the TIM state*/
htim->State = HAL_TIM_STATE_READY;
80014fe: 687b ldr r3, [r7, #4]
8001500: 2201 movs r2, #1
8001502: f883 203d strb.w r2, [r3, #61] ; 0x3d
return HAL_OK;
8001506: 2300 movs r3, #0
}
8001508: 4618 mov r0, r3
800150a: 3708 adds r7, #8
800150c: 46bd mov sp, r7
800150e: bd80 pop {r7, pc}
08001510 <HAL_TIM_PWM_MspInit>:
* @brief Initializes the TIM PWM MSP.
* @param htim TIM PWM handle
* @retval None
*/
__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
{
8001510: b480 push {r7}
8001512: b083 sub sp, #12
8001514: af00 add r7, sp, #0
8001516: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_PWM_MspInit could be implemented in the user file
*/
}
8001518: bf00 nop
800151a: 370c adds r7, #12
800151c: 46bd mov sp, r7
800151e: bc80 pop {r7}
8001520: 4770 bx lr
...
08001524 <HAL_TIM_PWM_Start>:
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
{
8001524: b580 push {r7, lr}
8001526: b084 sub sp, #16
8001528: af00 add r7, sp, #0
800152a: 6078 str r0, [r7, #4]
800152c: 6039 str r1, [r7, #0]
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
/* Check the TIM channel state */
if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
800152e: 683b ldr r3, [r7, #0]
8001530: 2b00 cmp r3, #0
8001532: d109 bne.n 8001548 <HAL_TIM_PWM_Start+0x24>
8001534: 687b ldr r3, [r7, #4]
8001536: f893 303e ldrb.w r3, [r3, #62] ; 0x3e
800153a: b2db uxtb r3, r3
800153c: 2b01 cmp r3, #1
800153e: bf14 ite ne
8001540: 2301 movne r3, #1
8001542: 2300 moveq r3, #0
8001544: b2db uxtb r3, r3
8001546: e022 b.n 800158e <HAL_TIM_PWM_Start+0x6a>
8001548: 683b ldr r3, [r7, #0]
800154a: 2b04 cmp r3, #4
800154c: d109 bne.n 8001562 <HAL_TIM_PWM_Start+0x3e>
800154e: 687b ldr r3, [r7, #4]
8001550: f893 303f ldrb.w r3, [r3, #63] ; 0x3f
8001554: b2db uxtb r3, r3
8001556: 2b01 cmp r3, #1
8001558: bf14 ite ne
800155a: 2301 movne r3, #1
800155c: 2300 moveq r3, #0
800155e: b2db uxtb r3, r3
8001560: e015 b.n 800158e <HAL_TIM_PWM_Start+0x6a>
8001562: 683b ldr r3, [r7, #0]
8001564: 2b08 cmp r3, #8
8001566: d109 bne.n 800157c <HAL_TIM_PWM_Start+0x58>
8001568: 687b ldr r3, [r7, #4]
800156a: f893 3040 ldrb.w r3, [r3, #64] ; 0x40
800156e: b2db uxtb r3, r3
8001570: 2b01 cmp r3, #1
8001572: bf14 ite ne
8001574: 2301 movne r3, #1
8001576: 2300 moveq r3, #0
8001578: b2db uxtb r3, r3
800157a: e008 b.n 800158e <HAL_TIM_PWM_Start+0x6a>
800157c: 687b ldr r3, [r7, #4]
800157e: f893 3041 ldrb.w r3, [r3, #65] ; 0x41
8001582: b2db uxtb r3, r3
8001584: 2b01 cmp r3, #1
8001586: bf14 ite ne
8001588: 2301 movne r3, #1
800158a: 2300 moveq r3, #0
800158c: b2db uxtb r3, r3
800158e: 2b00 cmp r3, #0
8001590: d001 beq.n 8001596 <HAL_TIM_PWM_Start+0x72>
{
return HAL_ERROR;
8001592: 2301 movs r3, #1
8001594: e05e b.n 8001654 <HAL_TIM_PWM_Start+0x130>
}
/* Set the TIM channel state */
TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
8001596: 683b ldr r3, [r7, #0]
8001598: 2b00 cmp r3, #0
800159a: d104 bne.n 80015a6 <HAL_TIM_PWM_Start+0x82>
800159c: 687b ldr r3, [r7, #4]
800159e: 2202 movs r2, #2
80015a0: f883 203e strb.w r2, [r3, #62] ; 0x3e
80015a4: e013 b.n 80015ce <HAL_TIM_PWM_Start+0xaa>
80015a6: 683b ldr r3, [r7, #0]
80015a8: 2b04 cmp r3, #4
80015aa: d104 bne.n 80015b6 <HAL_TIM_PWM_Start+0x92>
80015ac: 687b ldr r3, [r7, #4]
80015ae: 2202 movs r2, #2
80015b0: f883 203f strb.w r2, [r3, #63] ; 0x3f
80015b4: e00b b.n 80015ce <HAL_TIM_PWM_Start+0xaa>
80015b6: 683b ldr r3, [r7, #0]
80015b8: 2b08 cmp r3, #8
80015ba: d104 bne.n 80015c6 <HAL_TIM_PWM_Start+0xa2>
80015bc: 687b ldr r3, [r7, #4]
80015be: 2202 movs r2, #2
80015c0: f883 2040 strb.w r2, [r3, #64] ; 0x40
80015c4: e003 b.n 80015ce <HAL_TIM_PWM_Start+0xaa>
80015c6: 687b ldr r3, [r7, #4]
80015c8: 2202 movs r2, #2
80015ca: f883 2041 strb.w r2, [r3, #65] ; 0x41
/* Enable the Capture compare channel */
TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
80015ce: 687b ldr r3, [r7, #4]
80015d0: 681b ldr r3, [r3, #0]
80015d2: 2201 movs r2, #1
80015d4: 6839 ldr r1, [r7, #0]
80015d6: 4618 mov r0, r3
80015d8: f000 fc48 bl 8001e6c <TIM_CCxChannelCmd>
if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
80015dc: 687b ldr r3, [r7, #4]
80015de: 681b ldr r3, [r3, #0]
80015e0: 4a1e ldr r2, [pc, #120] ; (800165c <HAL_TIM_PWM_Start+0x138>)
80015e2: 4293 cmp r3, r2
80015e4: d107 bne.n 80015f6 <HAL_TIM_PWM_Start+0xd2>
{
/* Enable the main output */
__HAL_TIM_MOE_ENABLE(htim);
80015e6: 687b ldr r3, [r7, #4]
80015e8: 681b ldr r3, [r3, #0]
80015ea: 6c5a ldr r2, [r3, #68] ; 0x44
80015ec: 687b ldr r3, [r7, #4]
80015ee: 681b ldr r3, [r3, #0]
80015f0: f442 4200 orr.w r2, r2, #32768 ; 0x8000
80015f4: 645a str r2, [r3, #68] ; 0x44
}
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
80015f6: 687b ldr r3, [r7, #4]
80015f8: 681b ldr r3, [r3, #0]
80015fa: 4a18 ldr r2, [pc, #96] ; (800165c <HAL_TIM_PWM_Start+0x138>)
80015fc: 4293 cmp r3, r2
80015fe: d00e beq.n 800161e <HAL_TIM_PWM_Start+0xfa>
8001600: 687b ldr r3, [r7, #4]
8001602: 681b ldr r3, [r3, #0]
8001604: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
8001608: d009 beq.n 800161e <HAL_TIM_PWM_Start+0xfa>
800160a: 687b ldr r3, [r7, #4]
800160c: 681b ldr r3, [r3, #0]
800160e: 4a14 ldr r2, [pc, #80] ; (8001660 <HAL_TIM_PWM_Start+0x13c>)
8001610: 4293 cmp r3, r2
8001612: d004 beq.n 800161e <HAL_TIM_PWM_Start+0xfa>
8001614: 687b ldr r3, [r7, #4]
8001616: 681b ldr r3, [r3, #0]
8001618: 4a12 ldr r2, [pc, #72] ; (8001664 <HAL_TIM_PWM_Start+0x140>)
800161a: 4293 cmp r3, r2
800161c: d111 bne.n 8001642 <HAL_TIM_PWM_Start+0x11e>
{
tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
800161e: 687b ldr r3, [r7, #4]
8001620: 681b ldr r3, [r3, #0]
8001622: 689b ldr r3, [r3, #8]
8001624: f003 0307 and.w r3, r3, #7
8001628: 60fb str r3, [r7, #12]
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
800162a: 68fb ldr r3, [r7, #12]
800162c: 2b06 cmp r3, #6
800162e: d010 beq.n 8001652 <HAL_TIM_PWM_Start+0x12e>
{
__HAL_TIM_ENABLE(htim);
8001630: 687b ldr r3, [r7, #4]
8001632: 681b ldr r3, [r3, #0]
8001634: 681a ldr r2, [r3, #0]
8001636: 687b ldr r3, [r7, #4]
8001638: 681b ldr r3, [r3, #0]
800163a: f042 0201 orr.w r2, r2, #1
800163e: 601a str r2, [r3, #0]
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
8001640: e007 b.n 8001652 <HAL_TIM_PWM_Start+0x12e>
}
}
else
{
__HAL_TIM_ENABLE(htim);
8001642: 687b ldr r3, [r7, #4]
8001644: 681b ldr r3, [r3, #0]
8001646: 681a ldr r2, [r3, #0]
8001648: 687b ldr r3, [r7, #4]
800164a: 681b ldr r3, [r3, #0]
800164c: f042 0201 orr.w r2, r2, #1
8001650: 601a str r2, [r3, #0]
}
/* Return function status */
return HAL_OK;
8001652: 2300 movs r3, #0
}
8001654: 4618 mov r0, r3
8001656: 3710 adds r7, #16
8001658: 46bd mov sp, r7
800165a: bd80 pop {r7, pc}
800165c: 40012c00 .word 0x40012c00
8001660: 40000400 .word 0x40000400
8001664: 40000800 .word 0x40000800
08001668 <HAL_TIM_PWM_ConfigChannel>:
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
TIM_OC_InitTypeDef *sConfig,
uint32_t Channel)
{
8001668: b580 push {r7, lr}
800166a: b084 sub sp, #16
800166c: af00 add r7, sp, #0
800166e: 60f8 str r0, [r7, #12]
8001670: 60b9 str r1, [r7, #8]
8001672: 607a str r2, [r7, #4]
assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
/* Process Locked */
__HAL_LOCK(htim);
8001674: 68fb ldr r3, [r7, #12]
8001676: f893 303c ldrb.w r3, [r3, #60] ; 0x3c
800167a: 2b01 cmp r3, #1
800167c: d101 bne.n 8001682 <HAL_TIM_PWM_ConfigChannel+0x1a>
800167e: 2302 movs r3, #2
8001680: e0ac b.n 80017dc <HAL_TIM_PWM_ConfigChannel+0x174>
8001682: 68fb ldr r3, [r7, #12]
8001684: 2201 movs r2, #1
8001686: f883 203c strb.w r2, [r3, #60] ; 0x3c
switch (Channel)
800168a: 687b ldr r3, [r7, #4]
800168c: 2b0c cmp r3, #12
800168e: f200 809f bhi.w 80017d0 <HAL_TIM_PWM_ConfigChannel+0x168>
8001692: a201 add r2, pc, #4 ; (adr r2, 8001698 <HAL_TIM_PWM_ConfigChannel+0x30>)
8001694: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8001698: 080016cd .word 0x080016cd
800169c: 080017d1 .word 0x080017d1
80016a0: 080017d1 .word 0x080017d1
80016a4: 080017d1 .word 0x080017d1
80016a8: 0800170d .word 0x0800170d
80016ac: 080017d1 .word 0x080017d1
80016b0: 080017d1 .word 0x080017d1
80016b4: 080017d1 .word 0x080017d1
80016b8: 0800174f .word 0x0800174f
80016bc: 080017d1 .word 0x080017d1
80016c0: 080017d1 .word 0x080017d1
80016c4: 080017d1 .word 0x080017d1
80016c8: 0800178f .word 0x0800178f
{
/* Check the parameters */
assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
/* Configure the Channel 1 in PWM mode */
TIM_OC1_SetConfig(htim->Instance, sConfig);
80016cc: 68fb ldr r3, [r7, #12]
80016ce: 681b ldr r3, [r3, #0]
80016d0: 68b9 ldr r1, [r7, #8]
80016d2: 4618 mov r0, r3
80016d4: f000 f9ac bl 8001a30 <TIM_OC1_SetConfig>
/* Set the Preload enable bit for channel1 */
htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
80016d8: 68fb ldr r3, [r7, #12]
80016da: 681b ldr r3, [r3, #0]
80016dc: 699a ldr r2, [r3, #24]
80016de: 68fb ldr r3, [r7, #12]
80016e0: 681b ldr r3, [r3, #0]
80016e2: f042 0208 orr.w r2, r2, #8
80016e6: 619a str r2, [r3, #24]
/* Configure the Output Fast mode */
htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
80016e8: 68fb ldr r3, [r7, #12]
80016ea: 681b ldr r3, [r3, #0]
80016ec: 699a ldr r2, [r3, #24]
80016ee: 68fb ldr r3, [r7, #12]
80016f0: 681b ldr r3, [r3, #0]
80016f2: f022 0204 bic.w r2, r2, #4
80016f6: 619a str r2, [r3, #24]
htim->Instance->CCMR1 |= sConfig->OCFastMode;
80016f8: 68fb ldr r3, [r7, #12]
80016fa: 681b ldr r3, [r3, #0]
80016fc: 6999 ldr r1, [r3, #24]
80016fe: 68bb ldr r3, [r7, #8]
8001700: 691a ldr r2, [r3, #16]
8001702: 68fb ldr r3, [r7, #12]
8001704: 681b ldr r3, [r3, #0]
8001706: 430a orrs r2, r1
8001708: 619a str r2, [r3, #24]
break;
800170a: e062 b.n 80017d2 <HAL_TIM_PWM_ConfigChannel+0x16a>
{
/* Check the parameters */
assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
/* Configure the Channel 2 in PWM mode */
TIM_OC2_SetConfig(htim->Instance, sConfig);
800170c: 68fb ldr r3, [r7, #12]
800170e: 681b ldr r3, [r3, #0]
8001710: 68b9 ldr r1, [r7, #8]
8001712: 4618 mov r0, r3
8001714: f000 f9f2 bl 8001afc <TIM_OC2_SetConfig>
/* Set the Preload enable bit for channel2 */
htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
8001718: 68fb ldr r3, [r7, #12]
800171a: 681b ldr r3, [r3, #0]
800171c: 699a ldr r2, [r3, #24]
800171e: 68fb ldr r3, [r7, #12]
8001720: 681b ldr r3, [r3, #0]
8001722: f442 6200 orr.w r2, r2, #2048 ; 0x800
8001726: 619a str r2, [r3, #24]
/* Configure the Output Fast mode */
htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
8001728: 68fb ldr r3, [r7, #12]
800172a: 681b ldr r3, [r3, #0]
800172c: 699a ldr r2, [r3, #24]
800172e: 68fb ldr r3, [r7, #12]
8001730: 681b ldr r3, [r3, #0]
8001732: f422 6280 bic.w r2, r2, #1024 ; 0x400
8001736: 619a str r2, [r3, #24]
htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
8001738: 68fb ldr r3, [r7, #12]
800173a: 681b ldr r3, [r3, #0]
800173c: 6999 ldr r1, [r3, #24]
800173e: 68bb ldr r3, [r7, #8]
8001740: 691b ldr r3, [r3, #16]
8001742: 021a lsls r2, r3, #8
8001744: 68fb ldr r3, [r7, #12]
8001746: 681b ldr r3, [r3, #0]
8001748: 430a orrs r2, r1
800174a: 619a str r2, [r3, #24]
break;
800174c: e041 b.n 80017d2 <HAL_TIM_PWM_ConfigChannel+0x16a>
{
/* Check the parameters */
assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
/* Configure the Channel 3 in PWM mode */
TIM_OC3_SetConfig(htim->Instance, sConfig);
800174e: 68fb ldr r3, [r7, #12]
8001750: 681b ldr r3, [r3, #0]
8001752: 68b9 ldr r1, [r7, #8]
8001754: 4618 mov r0, r3
8001756: f000 fa3b bl 8001bd0 <TIM_OC3_SetConfig>
/* Set the Preload enable bit for channel3 */
htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
800175a: 68fb ldr r3, [r7, #12]
800175c: 681b ldr r3, [r3, #0]
800175e: 69da ldr r2, [r3, #28]
8001760: 68fb ldr r3, [r7, #12]
8001762: 681b ldr r3, [r3, #0]
8001764: f042 0208 orr.w r2, r2, #8
8001768: 61da str r2, [r3, #28]
/* Configure the Output Fast mode */
htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
800176a: 68fb ldr r3, [r7, #12]
800176c: 681b ldr r3, [r3, #0]
800176e: 69da ldr r2, [r3, #28]
8001770: 68fb ldr r3, [r7, #12]
8001772: 681b ldr r3, [r3, #0]
8001774: f022 0204 bic.w r2, r2, #4
8001778: 61da str r2, [r3, #28]
htim->Instance->CCMR2 |= sConfig->OCFastMode;
800177a: 68fb ldr r3, [r7, #12]
800177c: 681b ldr r3, [r3, #0]
800177e: 69d9 ldr r1, [r3, #28]
8001780: 68bb ldr r3, [r7, #8]
8001782: 691a ldr r2, [r3, #16]
8001784: 68fb ldr r3, [r7, #12]
8001786: 681b ldr r3, [r3, #0]
8001788: 430a orrs r2, r1
800178a: 61da str r2, [r3, #28]
break;
800178c: e021 b.n 80017d2 <HAL_TIM_PWM_ConfigChannel+0x16a>
{
/* Check the parameters */
assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
/* Configure the Channel 4 in PWM mode */
TIM_OC4_SetConfig(htim->Instance, sConfig);
800178e: 68fb ldr r3, [r7, #12]
8001790: 681b ldr r3, [r3, #0]
8001792: 68b9 ldr r1, [r7, #8]
8001794: 4618 mov r0, r3
8001796: f000 fa85 bl 8001ca4 <TIM_OC4_SetConfig>
/* Set the Preload enable bit for channel4 */
htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
800179a: 68fb ldr r3, [r7, #12]
800179c: 681b ldr r3, [r3, #0]
800179e: 69da ldr r2, [r3, #28]
80017a0: 68fb ldr r3, [r7, #12]
80017a2: 681b ldr r3, [r3, #0]
80017a4: f442 6200 orr.w r2, r2, #2048 ; 0x800
80017a8: 61da str r2, [r3, #28]
/* Configure the Output Fast mode */
htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
80017aa: 68fb ldr r3, [r7, #12]
80017ac: 681b ldr r3, [r3, #0]
80017ae: 69da ldr r2, [r3, #28]
80017b0: 68fb ldr r3, [r7, #12]
80017b2: 681b ldr r3, [r3, #0]
80017b4: f422 6280 bic.w r2, r2, #1024 ; 0x400
80017b8: 61da str r2, [r3, #28]
htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
80017ba: 68fb ldr r3, [r7, #12]
80017bc: 681b ldr r3, [r3, #0]
80017be: 69d9 ldr r1, [r3, #28]
80017c0: 68bb ldr r3, [r7, #8]
80017c2: 691b ldr r3, [r3, #16]
80017c4: 021a lsls r2, r3, #8
80017c6: 68fb ldr r3, [r7, #12]
80017c8: 681b ldr r3, [r3, #0]
80017ca: 430a orrs r2, r1
80017cc: 61da str r2, [r3, #28]
break;
80017ce: e000 b.n 80017d2 <HAL_TIM_PWM_ConfigChannel+0x16a>
}
default:
break;
80017d0: bf00 nop
}
__HAL_UNLOCK(htim);
80017d2: 68fb ldr r3, [r7, #12]
80017d4: 2200 movs r2, #0
80017d6: f883 203c strb.w r2, [r3, #60] ; 0x3c
return HAL_OK;
80017da: 2300 movs r3, #0
}
80017dc: 4618 mov r0, r3
80017de: 3710 adds r7, #16
80017e0: 46bd mov sp, r7
80017e2: bd80 pop {r7, pc}
080017e4 <HAL_TIM_ConfigClockSource>:
* @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that
* contains the clock source information for the TIM peripheral.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig)
{
80017e4: b580 push {r7, lr}
80017e6: b084 sub sp, #16
80017e8: af00 add r7, sp, #0
80017ea: 6078 str r0, [r7, #4]
80017ec: 6039 str r1, [r7, #0]
uint32_t tmpsmcr;
/* Process Locked */
__HAL_LOCK(htim);
80017ee: 687b ldr r3, [r7, #4]
80017f0: f893 303c ldrb.w r3, [r3, #60] ; 0x3c
80017f4: 2b01 cmp r3, #1
80017f6: d101 bne.n 80017fc <HAL_TIM_ConfigClockSource+0x18>
80017f8: 2302 movs r3, #2
80017fa: e0b3 b.n 8001964 <HAL_TIM_ConfigClockSource+0x180>
80017fc: 687b ldr r3, [r7, #4]
80017fe: 2201 movs r2, #1
8001800: f883 203c strb.w r2, [r3, #60] ; 0x3c
htim->State = HAL_TIM_STATE_BUSY;
8001804: 687b ldr r3, [r7, #4]
8001806: 2202 movs r2, #2
8001808: f883 203d strb.w r2, [r3, #61] ; 0x3d
/* Check the parameters */
assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
/* Reset the SMS, TS, ECE, ETPS and ETRF bits */
tmpsmcr = htim->Instance->SMCR;
800180c: 687b ldr r3, [r7, #4]
800180e: 681b ldr r3, [r3, #0]
8001810: 689b ldr r3, [r3, #8]
8001812: 60fb str r3, [r7, #12]
tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
8001814: 68fb ldr r3, [r7, #12]
8001816: f023 0377 bic.w r3, r3, #119 ; 0x77
800181a: 60fb str r3, [r7, #12]
tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
800181c: 68fb ldr r3, [r7, #12]
800181e: f423 437f bic.w r3, r3, #65280 ; 0xff00
8001822: 60fb str r3, [r7, #12]
htim->Instance->SMCR = tmpsmcr;
8001824: 687b ldr r3, [r7, #4]
8001826: 681b ldr r3, [r3, #0]
8001828: 68fa ldr r2, [r7, #12]
800182a: 609a str r2, [r3, #8]
switch (sClockSourceConfig->ClockSource)
800182c: 683b ldr r3, [r7, #0]
800182e: 681b ldr r3, [r3, #0]
8001830: f5b3 5f00 cmp.w r3, #8192 ; 0x2000
8001834: d03e beq.n 80018b4 <HAL_TIM_ConfigClockSource+0xd0>
8001836: f5b3 5f00 cmp.w r3, #8192 ; 0x2000
800183a: f200 8087 bhi.w 800194c <HAL_TIM_ConfigClockSource+0x168>
800183e: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
8001842: f000 8085 beq.w 8001950 <HAL_TIM_ConfigClockSource+0x16c>
8001846: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
800184a: d87f bhi.n 800194c <HAL_TIM_ConfigClockSource+0x168>
800184c: 2b70 cmp r3, #112 ; 0x70
800184e: d01a beq.n 8001886 <HAL_TIM_ConfigClockSource+0xa2>
8001850: 2b70 cmp r3, #112 ; 0x70
8001852: d87b bhi.n 800194c <HAL_TIM_ConfigClockSource+0x168>
8001854: 2b60 cmp r3, #96 ; 0x60
8001856: d050 beq.n 80018fa <HAL_TIM_ConfigClockSource+0x116>
8001858: 2b60 cmp r3, #96 ; 0x60
800185a: d877 bhi.n 800194c <HAL_TIM_ConfigClockSource+0x168>
800185c: 2b50 cmp r3, #80 ; 0x50
800185e: d03c beq.n 80018da <HAL_TIM_ConfigClockSource+0xf6>
8001860: 2b50 cmp r3, #80 ; 0x50
8001862: d873 bhi.n 800194c <HAL_TIM_ConfigClockSource+0x168>
8001864: 2b40 cmp r3, #64 ; 0x40
8001866: d058 beq.n 800191a <HAL_TIM_ConfigClockSource+0x136>
8001868: 2b40 cmp r3, #64 ; 0x40
800186a: d86f bhi.n 800194c <HAL_TIM_ConfigClockSource+0x168>
800186c: 2b30 cmp r3, #48 ; 0x30
800186e: d064 beq.n 800193a <HAL_TIM_ConfigClockSource+0x156>
8001870: 2b30 cmp r3, #48 ; 0x30
8001872: d86b bhi.n 800194c <HAL_TIM_ConfigClockSource+0x168>
8001874: 2b20 cmp r3, #32
8001876: d060 beq.n 800193a <HAL_TIM_ConfigClockSource+0x156>
8001878: 2b20 cmp r3, #32
800187a: d867 bhi.n 800194c <HAL_TIM_ConfigClockSource+0x168>
800187c: 2b00 cmp r3, #0
800187e: d05c beq.n 800193a <HAL_TIM_ConfigClockSource+0x156>
8001880: 2b10 cmp r3, #16
8001882: d05a beq.n 800193a <HAL_TIM_ConfigClockSource+0x156>
TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
break;
}
default:
break;
8001884: e062 b.n 800194c <HAL_TIM_ConfigClockSource+0x168>
TIM_ETR_SetConfig(htim->Instance,
8001886: 687b ldr r3, [r7, #4]
8001888: 6818 ldr r0, [r3, #0]
800188a: 683b ldr r3, [r7, #0]
800188c: 6899 ldr r1, [r3, #8]
800188e: 683b ldr r3, [r7, #0]
8001890: 685a ldr r2, [r3, #4]
8001892: 683b ldr r3, [r7, #0]
8001894: 68db ldr r3, [r3, #12]
8001896: f000 faca bl 8001e2e <TIM_ETR_SetConfig>
tmpsmcr = htim->Instance->SMCR;
800189a: 687b ldr r3, [r7, #4]
800189c: 681b ldr r3, [r3, #0]
800189e: 689b ldr r3, [r3, #8]
80018a0: 60fb str r3, [r7, #12]
tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
80018a2: 68fb ldr r3, [r7, #12]
80018a4: f043 0377 orr.w r3, r3, #119 ; 0x77
80018a8: 60fb str r3, [r7, #12]
htim->Instance->SMCR = tmpsmcr;
80018aa: 687b ldr r3, [r7, #4]
80018ac: 681b ldr r3, [r3, #0]
80018ae: 68fa ldr r2, [r7, #12]
80018b0: 609a str r2, [r3, #8]
break;
80018b2: e04e b.n 8001952 <HAL_TIM_ConfigClockSource+0x16e>
TIM_ETR_SetConfig(htim->Instance,
80018b4: 687b ldr r3, [r7, #4]
80018b6: 6818 ldr r0, [r3, #0]
80018b8: 683b ldr r3, [r7, #0]
80018ba: 6899 ldr r1, [r3, #8]
80018bc: 683b ldr r3, [r7, #0]
80018be: 685a ldr r2, [r3, #4]
80018c0: 683b ldr r3, [r7, #0]
80018c2: 68db ldr r3, [r3, #12]
80018c4: f000 fab3 bl 8001e2e <TIM_ETR_SetConfig>
htim->Instance->SMCR |= TIM_SMCR_ECE;
80018c8: 687b ldr r3, [r7, #4]
80018ca: 681b ldr r3, [r3, #0]
80018cc: 689a ldr r2, [r3, #8]
80018ce: 687b ldr r3, [r7, #4]
80018d0: 681b ldr r3, [r3, #0]
80018d2: f442 4280 orr.w r2, r2, #16384 ; 0x4000
80018d6: 609a str r2, [r3, #8]
break;
80018d8: e03b b.n 8001952 <HAL_TIM_ConfigClockSource+0x16e>
TIM_TI1_ConfigInputStage(htim->Instance,
80018da: 687b ldr r3, [r7, #4]
80018dc: 6818 ldr r0, [r3, #0]
80018de: 683b ldr r3, [r7, #0]
80018e0: 6859 ldr r1, [r3, #4]
80018e2: 683b ldr r3, [r7, #0]
80018e4: 68db ldr r3, [r3, #12]
80018e6: 461a mov r2, r3
80018e8: f000 fa2a bl 8001d40 <TIM_TI1_ConfigInputStage>
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
80018ec: 687b ldr r3, [r7, #4]
80018ee: 681b ldr r3, [r3, #0]
80018f0: 2150 movs r1, #80 ; 0x50
80018f2: 4618 mov r0, r3
80018f4: f000 fa81 bl 8001dfa <TIM_ITRx_SetConfig>
break;
80018f8: e02b b.n 8001952 <HAL_TIM_ConfigClockSource+0x16e>
TIM_TI2_ConfigInputStage(htim->Instance,
80018fa: 687b ldr r3, [r7, #4]
80018fc: 6818 ldr r0, [r3, #0]
80018fe: 683b ldr r3, [r7, #0]
8001900: 6859 ldr r1, [r3, #4]
8001902: 683b ldr r3, [r7, #0]
8001904: 68db ldr r3, [r3, #12]
8001906: 461a mov r2, r3
8001908: f000 fa48 bl 8001d9c <TIM_TI2_ConfigInputStage>
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
800190c: 687b ldr r3, [r7, #4]
800190e: 681b ldr r3, [r3, #0]
8001910: 2160 movs r1, #96 ; 0x60
8001912: 4618 mov r0, r3
8001914: f000 fa71 bl 8001dfa <TIM_ITRx_SetConfig>
break;
8001918: e01b b.n 8001952 <HAL_TIM_ConfigClockSource+0x16e>
TIM_TI1_ConfigInputStage(htim->Instance,
800191a: 687b ldr r3, [r7, #4]
800191c: 6818 ldr r0, [r3, #0]
800191e: 683b ldr r3, [r7, #0]
8001920: 6859 ldr r1, [r3, #4]
8001922: 683b ldr r3, [r7, #0]
8001924: 68db ldr r3, [r3, #12]
8001926: 461a mov r2, r3
8001928: f000 fa0a bl 8001d40 <TIM_TI1_ConfigInputStage>
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
800192c: 687b ldr r3, [r7, #4]
800192e: 681b ldr r3, [r3, #0]
8001930: 2140 movs r1, #64 ; 0x40
8001932: 4618 mov r0, r3
8001934: f000 fa61 bl 8001dfa <TIM_ITRx_SetConfig>
break;
8001938: e00b b.n 8001952 <HAL_TIM_ConfigClockSource+0x16e>
TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
800193a: 687b ldr r3, [r7, #4]
800193c: 681a ldr r2, [r3, #0]
800193e: 683b ldr r3, [r7, #0]
8001940: 681b ldr r3, [r3, #0]
8001942: 4619 mov r1, r3
8001944: 4610 mov r0, r2
8001946: f000 fa58 bl 8001dfa <TIM_ITRx_SetConfig>
break;
800194a: e002 b.n 8001952 <HAL_TIM_ConfigClockSource+0x16e>
break;
800194c: bf00 nop
800194e: e000 b.n 8001952 <HAL_TIM_ConfigClockSource+0x16e>
break;
8001950: bf00 nop
}
htim->State = HAL_TIM_STATE_READY;
8001952: 687b ldr r3, [r7, #4]
8001954: 2201 movs r2, #1
8001956: f883 203d strb.w r2, [r3, #61] ; 0x3d
__HAL_UNLOCK(htim);
800195a: 687b ldr r3, [r7, #4]
800195c: 2200 movs r2, #0
800195e: f883 203c strb.w r2, [r3, #60] ; 0x3c
return HAL_OK;
8001962: 2300 movs r3, #0
}
8001964: 4618 mov r0, r3
8001966: 3710 adds r7, #16
8001968: 46bd mov sp, r7
800196a: bd80 pop {r7, pc}
0800196c <TIM_Base_SetConfig>:
* @param TIMx TIM peripheral
* @param Structure TIM Base configuration structure
* @retval None
*/
void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
{
800196c: b480 push {r7}
800196e: b085 sub sp, #20
8001970: af00 add r7, sp, #0
8001972: 6078 str r0, [r7, #4]
8001974: 6039 str r1, [r7, #0]
uint32_t tmpcr1;
tmpcr1 = TIMx->CR1;
8001976: 687b ldr r3, [r7, #4]
8001978: 681b ldr r3, [r3, #0]
800197a: 60fb str r3, [r7, #12]
/* Set TIM Time Base Unit parameters ---------------------------------------*/
if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
800197c: 687b ldr r3, [r7, #4]
800197e: 4a29 ldr r2, [pc, #164] ; (8001a24 <TIM_Base_SetConfig+0xb8>)
8001980: 4293 cmp r3, r2
8001982: d00b beq.n 800199c <TIM_Base_SetConfig+0x30>
8001984: 687b ldr r3, [r7, #4]
8001986: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
800198a: d007 beq.n 800199c <TIM_Base_SetConfig+0x30>
800198c: 687b ldr r3, [r7, #4]
800198e: 4a26 ldr r2, [pc, #152] ; (8001a28 <TIM_Base_SetConfig+0xbc>)
8001990: 4293 cmp r3, r2
8001992: d003 beq.n 800199c <TIM_Base_SetConfig+0x30>
8001994: 687b ldr r3, [r7, #4]
8001996: 4a25 ldr r2, [pc, #148] ; (8001a2c <TIM_Base_SetConfig+0xc0>)
8001998: 4293 cmp r3, r2
800199a: d108 bne.n 80019ae <TIM_Base_SetConfig+0x42>
{
/* Select the Counter Mode */
tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
800199c: 68fb ldr r3, [r7, #12]
800199e: f023 0370 bic.w r3, r3, #112 ; 0x70
80019a2: 60fb str r3, [r7, #12]
tmpcr1 |= Structure->CounterMode;
80019a4: 683b ldr r3, [r7, #0]
80019a6: 685b ldr r3, [r3, #4]
80019a8: 68fa ldr r2, [r7, #12]
80019aa: 4313 orrs r3, r2
80019ac: 60fb str r3, [r7, #12]
}
if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
80019ae: 687b ldr r3, [r7, #4]
80019b0: 4a1c ldr r2, [pc, #112] ; (8001a24 <TIM_Base_SetConfig+0xb8>)
80019b2: 4293 cmp r3, r2
80019b4: d00b beq.n 80019ce <TIM_Base_SetConfig+0x62>
80019b6: 687b ldr r3, [r7, #4]
80019b8: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
80019bc: d007 beq.n 80019ce <TIM_Base_SetConfig+0x62>
80019be: 687b ldr r3, [r7, #4]
80019c0: 4a19 ldr r2, [pc, #100] ; (8001a28 <TIM_Base_SetConfig+0xbc>)
80019c2: 4293 cmp r3, r2
80019c4: d003 beq.n 80019ce <TIM_Base_SetConfig+0x62>
80019c6: 687b ldr r3, [r7, #4]
80019c8: 4a18 ldr r2, [pc, #96] ; (8001a2c <TIM_Base_SetConfig+0xc0>)
80019ca: 4293 cmp r3, r2
80019cc: d108 bne.n 80019e0 <TIM_Base_SetConfig+0x74>
{
/* Set the clock division */
tmpcr1 &= ~TIM_CR1_CKD;
80019ce: 68fb ldr r3, [r7, #12]
80019d0: f423 7340 bic.w r3, r3, #768 ; 0x300
80019d4: 60fb str r3, [r7, #12]
tmpcr1 |= (uint32_t)Structure->ClockDivision;
80019d6: 683b ldr r3, [r7, #0]
80019d8: 68db ldr r3, [r3, #12]
80019da: 68fa ldr r2, [r7, #12]
80019dc: 4313 orrs r3, r2
80019de: 60fb str r3, [r7, #12]
}
/* Set the auto-reload preload */
MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
80019e0: 68fb ldr r3, [r7, #12]
80019e2: f023 0280 bic.w r2, r3, #128 ; 0x80
80019e6: 683b ldr r3, [r7, #0]
80019e8: 695b ldr r3, [r3, #20]
80019ea: 4313 orrs r3, r2
80019ec: 60fb str r3, [r7, #12]
TIMx->CR1 = tmpcr1;
80019ee: 687b ldr r3, [r7, #4]
80019f0: 68fa ldr r2, [r7, #12]
80019f2: 601a str r2, [r3, #0]
/* Set the Autoreload value */
TIMx->ARR = (uint32_t)Structure->Period ;
80019f4: 683b ldr r3, [r7, #0]
80019f6: 689a ldr r2, [r3, #8]
80019f8: 687b ldr r3, [r7, #4]
80019fa: 62da str r2, [r3, #44] ; 0x2c
/* Set the Prescaler value */
TIMx->PSC = Structure->Prescaler;
80019fc: 683b ldr r3, [r7, #0]
80019fe: 681a ldr r2, [r3, #0]
8001a00: 687b ldr r3, [r7, #4]
8001a02: 629a str r2, [r3, #40] ; 0x28
if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
8001a04: 687b ldr r3, [r7, #4]
8001a06: 4a07 ldr r2, [pc, #28] ; (8001a24 <TIM_Base_SetConfig+0xb8>)
8001a08: 4293 cmp r3, r2
8001a0a: d103 bne.n 8001a14 <TIM_Base_SetConfig+0xa8>
{
/* Set the Repetition Counter value */
TIMx->RCR = Structure->RepetitionCounter;
8001a0c: 683b ldr r3, [r7, #0]
8001a0e: 691a ldr r2, [r3, #16]
8001a10: 687b ldr r3, [r7, #4]
8001a12: 631a str r2, [r3, #48] ; 0x30
}
/* Generate an update event to reload the Prescaler
and the repetition counter (only for advanced timer) value immediately */
TIMx->EGR = TIM_EGR_UG;
8001a14: 687b ldr r3, [r7, #4]
8001a16: 2201 movs r2, #1
8001a18: 615a str r2, [r3, #20]
}
8001a1a: bf00 nop
8001a1c: 3714 adds r7, #20
8001a1e: 46bd mov sp, r7
8001a20: bc80 pop {r7}
8001a22: 4770 bx lr
8001a24: 40012c00 .word 0x40012c00
8001a28: 40000400 .word 0x40000400
8001a2c: 40000800 .word 0x40000800
08001a30 <TIM_OC1_SetConfig>:
* @param TIMx to select the TIM peripheral
* @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
{
8001a30: b480 push {r7}
8001a32: b087 sub sp, #28
8001a34: af00 add r7, sp, #0
8001a36: 6078 str r0, [r7, #4]
8001a38: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Disable the Channel 1: Reset the CC1E Bit */
TIMx->CCER &= ~TIM_CCER_CC1E;
8001a3a: 687b ldr r3, [r7, #4]
8001a3c: 6a1b ldr r3, [r3, #32]
8001a3e: f023 0201 bic.w r2, r3, #1
8001a42: 687b ldr r3, [r7, #4]
8001a44: 621a str r2, [r3, #32]
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
8001a46: 687b ldr r3, [r7, #4]
8001a48: 6a1b ldr r3, [r3, #32]
8001a4a: 617b str r3, [r7, #20]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
8001a4c: 687b ldr r3, [r7, #4]
8001a4e: 685b ldr r3, [r3, #4]
8001a50: 613b str r3, [r7, #16]
/* Get the TIMx CCMR1 register value */
tmpccmrx = TIMx->CCMR1;
8001a52: 687b ldr r3, [r7, #4]
8001a54: 699b ldr r3, [r3, #24]
8001a56: 60fb str r3, [r7, #12]
/* Reset the Output Compare Mode Bits */
tmpccmrx &= ~TIM_CCMR1_OC1M;
8001a58: 68fb ldr r3, [r7, #12]
8001a5a: f023 0370 bic.w r3, r3, #112 ; 0x70
8001a5e: 60fb str r3, [r7, #12]
tmpccmrx &= ~TIM_CCMR1_CC1S;
8001a60: 68fb ldr r3, [r7, #12]
8001a62: f023 0303 bic.w r3, r3, #3
8001a66: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= OC_Config->OCMode;
8001a68: 683b ldr r3, [r7, #0]
8001a6a: 681b ldr r3, [r3, #0]
8001a6c: 68fa ldr r2, [r7, #12]
8001a6e: 4313 orrs r3, r2
8001a70: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC1P;
8001a72: 697b ldr r3, [r7, #20]
8001a74: f023 0302 bic.w r3, r3, #2
8001a78: 617b str r3, [r7, #20]
/* Set the Output Compare Polarity */
tmpccer |= OC_Config->OCPolarity;
8001a7a: 683b ldr r3, [r7, #0]
8001a7c: 689b ldr r3, [r3, #8]
8001a7e: 697a ldr r2, [r7, #20]
8001a80: 4313 orrs r3, r2
8001a82: 617b str r3, [r7, #20]
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
8001a84: 687b ldr r3, [r7, #4]
8001a86: 4a1c ldr r2, [pc, #112] ; (8001af8 <TIM_OC1_SetConfig+0xc8>)
8001a88: 4293 cmp r3, r2
8001a8a: d10c bne.n 8001aa6 <TIM_OC1_SetConfig+0x76>
{
/* Check parameters */
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
/* Reset the Output N Polarity level */
tmpccer &= ~TIM_CCER_CC1NP;
8001a8c: 697b ldr r3, [r7, #20]
8001a8e: f023 0308 bic.w r3, r3, #8
8001a92: 617b str r3, [r7, #20]
/* Set the Output N Polarity */
tmpccer |= OC_Config->OCNPolarity;
8001a94: 683b ldr r3, [r7, #0]
8001a96: 68db ldr r3, [r3, #12]
8001a98: 697a ldr r2, [r7, #20]
8001a9a: 4313 orrs r3, r2
8001a9c: 617b str r3, [r7, #20]
/* Reset the Output N State */
tmpccer &= ~TIM_CCER_CC1NE;
8001a9e: 697b ldr r3, [r7, #20]
8001aa0: f023 0304 bic.w r3, r3, #4
8001aa4: 617b str r3, [r7, #20]
}
if (IS_TIM_BREAK_INSTANCE(TIMx))
8001aa6: 687b ldr r3, [r7, #4]
8001aa8: 4a13 ldr r2, [pc, #76] ; (8001af8 <TIM_OC1_SetConfig+0xc8>)
8001aaa: 4293 cmp r3, r2
8001aac: d111 bne.n 8001ad2 <TIM_OC1_SetConfig+0xa2>
/* Check parameters */
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
/* Reset the Output Compare and Output Compare N IDLE State */
tmpcr2 &= ~TIM_CR2_OIS1;
8001aae: 693b ldr r3, [r7, #16]
8001ab0: f423 7380 bic.w r3, r3, #256 ; 0x100
8001ab4: 613b str r3, [r7, #16]
tmpcr2 &= ~TIM_CR2_OIS1N;
8001ab6: 693b ldr r3, [r7, #16]
8001ab8: f423 7300 bic.w r3, r3, #512 ; 0x200
8001abc: 613b str r3, [r7, #16]
/* Set the Output Idle state */
tmpcr2 |= OC_Config->OCIdleState;
8001abe: 683b ldr r3, [r7, #0]
8001ac0: 695b ldr r3, [r3, #20]
8001ac2: 693a ldr r2, [r7, #16]
8001ac4: 4313 orrs r3, r2
8001ac6: 613b str r3, [r7, #16]
/* Set the Output N Idle state */
tmpcr2 |= OC_Config->OCNIdleState;
8001ac8: 683b ldr r3, [r7, #0]
8001aca: 699b ldr r3, [r3, #24]
8001acc: 693a ldr r2, [r7, #16]
8001ace: 4313 orrs r3, r2
8001ad0: 613b str r3, [r7, #16]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
8001ad2: 687b ldr r3, [r7, #4]
8001ad4: 693a ldr r2, [r7, #16]
8001ad6: 605a str r2, [r3, #4]
/* Write to TIMx CCMR1 */
TIMx->CCMR1 = tmpccmrx;
8001ad8: 687b ldr r3, [r7, #4]
8001ada: 68fa ldr r2, [r7, #12]
8001adc: 619a str r2, [r3, #24]
/* Set the Capture Compare Register value */
TIMx->CCR1 = OC_Config->Pulse;
8001ade: 683b ldr r3, [r7, #0]
8001ae0: 685a ldr r2, [r3, #4]
8001ae2: 687b ldr r3, [r7, #4]
8001ae4: 635a str r2, [r3, #52] ; 0x34
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
8001ae6: 687b ldr r3, [r7, #4]
8001ae8: 697a ldr r2, [r7, #20]
8001aea: 621a str r2, [r3, #32]
}
8001aec: bf00 nop
8001aee: 371c adds r7, #28
8001af0: 46bd mov sp, r7
8001af2: bc80 pop {r7}
8001af4: 4770 bx lr
8001af6: bf00 nop
8001af8: 40012c00 .word 0x40012c00
08001afc <TIM_OC2_SetConfig>:
* @param TIMx to select the TIM peripheral
* @param OC_Config The output configuration structure
* @retval None
*/
void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
{
8001afc: b480 push {r7}
8001afe: b087 sub sp, #28
8001b00: af00 add r7, sp, #0
8001b02: 6078 str r0, [r7, #4]
8001b04: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Disable the Channel 2: Reset the CC2E Bit */
TIMx->CCER &= ~TIM_CCER_CC2E;
8001b06: 687b ldr r3, [r7, #4]
8001b08: 6a1b ldr r3, [r3, #32]
8001b0a: f023 0210 bic.w r2, r3, #16
8001b0e: 687b ldr r3, [r7, #4]
8001b10: 621a str r2, [r3, #32]
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
8001b12: 687b ldr r3, [r7, #4]
8001b14: 6a1b ldr r3, [r3, #32]
8001b16: 617b str r3, [r7, #20]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
8001b18: 687b ldr r3, [r7, #4]
8001b1a: 685b ldr r3, [r3, #4]
8001b1c: 613b str r3, [r7, #16]
/* Get the TIMx CCMR1 register value */
tmpccmrx = TIMx->CCMR1;
8001b1e: 687b ldr r3, [r7, #4]
8001b20: 699b ldr r3, [r3, #24]
8001b22: 60fb str r3, [r7, #12]
/* Reset the Output Compare mode and Capture/Compare selection Bits */
tmpccmrx &= ~TIM_CCMR1_OC2M;
8001b24: 68fb ldr r3, [r7, #12]
8001b26: f423 43e0 bic.w r3, r3, #28672 ; 0x7000
8001b2a: 60fb str r3, [r7, #12]
tmpccmrx &= ~TIM_CCMR1_CC2S;
8001b2c: 68fb ldr r3, [r7, #12]
8001b2e: f423 7340 bic.w r3, r3, #768 ; 0x300
8001b32: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= (OC_Config->OCMode << 8U);
8001b34: 683b ldr r3, [r7, #0]
8001b36: 681b ldr r3, [r3, #0]
8001b38: 021b lsls r3, r3, #8
8001b3a: 68fa ldr r2, [r7, #12]
8001b3c: 4313 orrs r3, r2
8001b3e: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC2P;
8001b40: 697b ldr r3, [r7, #20]
8001b42: f023 0320 bic.w r3, r3, #32
8001b46: 617b str r3, [r7, #20]
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 4U);
8001b48: 683b ldr r3, [r7, #0]
8001b4a: 689b ldr r3, [r3, #8]
8001b4c: 011b lsls r3, r3, #4
8001b4e: 697a ldr r2, [r7, #20]
8001b50: 4313 orrs r3, r2
8001b52: 617b str r3, [r7, #20]
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
8001b54: 687b ldr r3, [r7, #4]
8001b56: 4a1d ldr r2, [pc, #116] ; (8001bcc <TIM_OC2_SetConfig+0xd0>)
8001b58: 4293 cmp r3, r2
8001b5a: d10d bne.n 8001b78 <TIM_OC2_SetConfig+0x7c>
{
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
/* Reset the Output N Polarity level */
tmpccer &= ~TIM_CCER_CC2NP;
8001b5c: 697b ldr r3, [r7, #20]
8001b5e: f023 0380 bic.w r3, r3, #128 ; 0x80
8001b62: 617b str r3, [r7, #20]
/* Set the Output N Polarity */
tmpccer |= (OC_Config->OCNPolarity << 4U);
8001b64: 683b ldr r3, [r7, #0]
8001b66: 68db ldr r3, [r3, #12]
8001b68: 011b lsls r3, r3, #4
8001b6a: 697a ldr r2, [r7, #20]
8001b6c: 4313 orrs r3, r2
8001b6e: 617b str r3, [r7, #20]
/* Reset the Output N State */
tmpccer &= ~TIM_CCER_CC2NE;
8001b70: 697b ldr r3, [r7, #20]
8001b72: f023 0340 bic.w r3, r3, #64 ; 0x40
8001b76: 617b str r3, [r7, #20]
}
if (IS_TIM_BREAK_INSTANCE(TIMx))
8001b78: 687b ldr r3, [r7, #4]
8001b7a: 4a14 ldr r2, [pc, #80] ; (8001bcc <TIM_OC2_SetConfig+0xd0>)
8001b7c: 4293 cmp r3, r2
8001b7e: d113 bne.n 8001ba8 <TIM_OC2_SetConfig+0xac>
/* Check parameters */
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
/* Reset the Output Compare and Output Compare N IDLE State */
tmpcr2 &= ~TIM_CR2_OIS2;
8001b80: 693b ldr r3, [r7, #16]
8001b82: f423 6380 bic.w r3, r3, #1024 ; 0x400
8001b86: 613b str r3, [r7, #16]
tmpcr2 &= ~TIM_CR2_OIS2N;
8001b88: 693b ldr r3, [r7, #16]
8001b8a: f423 6300 bic.w r3, r3, #2048 ; 0x800
8001b8e: 613b str r3, [r7, #16]
/* Set the Output Idle state */
tmpcr2 |= (OC_Config->OCIdleState << 2U);
8001b90: 683b ldr r3, [r7, #0]
8001b92: 695b ldr r3, [r3, #20]
8001b94: 009b lsls r3, r3, #2
8001b96: 693a ldr r2, [r7, #16]
8001b98: 4313 orrs r3, r2
8001b9a: 613b str r3, [r7, #16]
/* Set the Output N Idle state */
tmpcr2 |= (OC_Config->OCNIdleState << 2U);
8001b9c: 683b ldr r3, [r7, #0]
8001b9e: 699b ldr r3, [r3, #24]
8001ba0: 009b lsls r3, r3, #2
8001ba2: 693a ldr r2, [r7, #16]
8001ba4: 4313 orrs r3, r2
8001ba6: 613b str r3, [r7, #16]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
8001ba8: 687b ldr r3, [r7, #4]
8001baa: 693a ldr r2, [r7, #16]
8001bac: 605a str r2, [r3, #4]
/* Write to TIMx CCMR1 */
TIMx->CCMR1 = tmpccmrx;
8001bae: 687b ldr r3, [r7, #4]
8001bb0: 68fa ldr r2, [r7, #12]
8001bb2: 619a str r2, [r3, #24]
/* Set the Capture Compare Register value */
TIMx->CCR2 = OC_Config->Pulse;
8001bb4: 683b ldr r3, [r7, #0]
8001bb6: 685a ldr r2, [r3, #4]
8001bb8: 687b ldr r3, [r7, #4]
8001bba: 639a str r2, [r3, #56] ; 0x38
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
8001bbc: 687b ldr r3, [r7, #4]
8001bbe: 697a ldr r2, [r7, #20]
8001bc0: 621a str r2, [r3, #32]
}
8001bc2: bf00 nop
8001bc4: 371c adds r7, #28
8001bc6: 46bd mov sp, r7
8001bc8: bc80 pop {r7}
8001bca: 4770 bx lr
8001bcc: 40012c00 .word 0x40012c00
08001bd0 <TIM_OC3_SetConfig>:
* @param TIMx to select the TIM peripheral
* @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
{
8001bd0: b480 push {r7}
8001bd2: b087 sub sp, #28
8001bd4: af00 add r7, sp, #0
8001bd6: 6078 str r0, [r7, #4]
8001bd8: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Disable the Channel 3: Reset the CC2E Bit */
TIMx->CCER &= ~TIM_CCER_CC3E;
8001bda: 687b ldr r3, [r7, #4]
8001bdc: 6a1b ldr r3, [r3, #32]
8001bde: f423 7280 bic.w r2, r3, #256 ; 0x100
8001be2: 687b ldr r3, [r7, #4]
8001be4: 621a str r2, [r3, #32]
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
8001be6: 687b ldr r3, [r7, #4]
8001be8: 6a1b ldr r3, [r3, #32]
8001bea: 617b str r3, [r7, #20]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
8001bec: 687b ldr r3, [r7, #4]
8001bee: 685b ldr r3, [r3, #4]
8001bf0: 613b str r3, [r7, #16]
/* Get the TIMx CCMR2 register value */
tmpccmrx = TIMx->CCMR2;
8001bf2: 687b ldr r3, [r7, #4]
8001bf4: 69db ldr r3, [r3, #28]
8001bf6: 60fb str r3, [r7, #12]
/* Reset the Output Compare mode and Capture/Compare selection Bits */
tmpccmrx &= ~TIM_CCMR2_OC3M;
8001bf8: 68fb ldr r3, [r7, #12]
8001bfa: f023 0370 bic.w r3, r3, #112 ; 0x70
8001bfe: 60fb str r3, [r7, #12]
tmpccmrx &= ~TIM_CCMR2_CC3S;
8001c00: 68fb ldr r3, [r7, #12]
8001c02: f023 0303 bic.w r3, r3, #3
8001c06: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= OC_Config->OCMode;
8001c08: 683b ldr r3, [r7, #0]
8001c0a: 681b ldr r3, [r3, #0]
8001c0c: 68fa ldr r2, [r7, #12]
8001c0e: 4313 orrs r3, r2
8001c10: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC3P;
8001c12: 697b ldr r3, [r7, #20]
8001c14: f423 7300 bic.w r3, r3, #512 ; 0x200
8001c18: 617b str r3, [r7, #20]
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 8U);
8001c1a: 683b ldr r3, [r7, #0]
8001c1c: 689b ldr r3, [r3, #8]
8001c1e: 021b lsls r3, r3, #8
8001c20: 697a ldr r2, [r7, #20]
8001c22: 4313 orrs r3, r2
8001c24: 617b str r3, [r7, #20]
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
8001c26: 687b ldr r3, [r7, #4]
8001c28: 4a1d ldr r2, [pc, #116] ; (8001ca0 <TIM_OC3_SetConfig+0xd0>)
8001c2a: 4293 cmp r3, r2
8001c2c: d10d bne.n 8001c4a <TIM_OC3_SetConfig+0x7a>
{
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
/* Reset the Output N Polarity level */
tmpccer &= ~TIM_CCER_CC3NP;
8001c2e: 697b ldr r3, [r7, #20]
8001c30: f423 6300 bic.w r3, r3, #2048 ; 0x800
8001c34: 617b str r3, [r7, #20]
/* Set the Output N Polarity */
tmpccer |= (OC_Config->OCNPolarity << 8U);
8001c36: 683b ldr r3, [r7, #0]
8001c38: 68db ldr r3, [r3, #12]
8001c3a: 021b lsls r3, r3, #8
8001c3c: 697a ldr r2, [r7, #20]
8001c3e: 4313 orrs r3, r2
8001c40: 617b str r3, [r7, #20]
/* Reset the Output N State */
tmpccer &= ~TIM_CCER_CC3NE;
8001c42: 697b ldr r3, [r7, #20]
8001c44: f423 6380 bic.w r3, r3, #1024 ; 0x400
8001c48: 617b str r3, [r7, #20]
}
if (IS_TIM_BREAK_INSTANCE(TIMx))
8001c4a: 687b ldr r3, [r7, #4]
8001c4c: 4a14 ldr r2, [pc, #80] ; (8001ca0 <TIM_OC3_SetConfig+0xd0>)
8001c4e: 4293 cmp r3, r2
8001c50: d113 bne.n 8001c7a <TIM_OC3_SetConfig+0xaa>
/* Check parameters */
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
/* Reset the Output Compare and Output Compare N IDLE State */
tmpcr2 &= ~TIM_CR2_OIS3;
8001c52: 693b ldr r3, [r7, #16]
8001c54: f423 5380 bic.w r3, r3, #4096 ; 0x1000
8001c58: 613b str r3, [r7, #16]
tmpcr2 &= ~TIM_CR2_OIS3N;
8001c5a: 693b ldr r3, [r7, #16]
8001c5c: f423 5300 bic.w r3, r3, #8192 ; 0x2000
8001c60: 613b str r3, [r7, #16]
/* Set the Output Idle state */
tmpcr2 |= (OC_Config->OCIdleState << 4U);
8001c62: 683b ldr r3, [r7, #0]
8001c64: 695b ldr r3, [r3, #20]
8001c66: 011b lsls r3, r3, #4
8001c68: 693a ldr r2, [r7, #16]
8001c6a: 4313 orrs r3, r2
8001c6c: 613b str r3, [r7, #16]
/* Set the Output N Idle state */
tmpcr2 |= (OC_Config->OCNIdleState << 4U);
8001c6e: 683b ldr r3, [r7, #0]
8001c70: 699b ldr r3, [r3, #24]
8001c72: 011b lsls r3, r3, #4
8001c74: 693a ldr r2, [r7, #16]
8001c76: 4313 orrs r3, r2
8001c78: 613b str r3, [r7, #16]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
8001c7a: 687b ldr r3, [r7, #4]
8001c7c: 693a ldr r2, [r7, #16]
8001c7e: 605a str r2, [r3, #4]
/* Write to TIMx CCMR2 */
TIMx->CCMR2 = tmpccmrx;
8001c80: 687b ldr r3, [r7, #4]
8001c82: 68fa ldr r2, [r7, #12]
8001c84: 61da str r2, [r3, #28]
/* Set the Capture Compare Register value */
TIMx->CCR3 = OC_Config->Pulse;
8001c86: 683b ldr r3, [r7, #0]
8001c88: 685a ldr r2, [r3, #4]
8001c8a: 687b ldr r3, [r7, #4]
8001c8c: 63da str r2, [r3, #60] ; 0x3c
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
8001c8e: 687b ldr r3, [r7, #4]
8001c90: 697a ldr r2, [r7, #20]
8001c92: 621a str r2, [r3, #32]
}
8001c94: bf00 nop
8001c96: 371c adds r7, #28
8001c98: 46bd mov sp, r7
8001c9a: bc80 pop {r7}
8001c9c: 4770 bx lr
8001c9e: bf00 nop
8001ca0: 40012c00 .word 0x40012c00
08001ca4 <TIM_OC4_SetConfig>:
* @param TIMx to select the TIM peripheral
* @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
{
8001ca4: b480 push {r7}
8001ca6: b087 sub sp, #28
8001ca8: af00 add r7, sp, #0
8001caa: 6078 str r0, [r7, #4]
8001cac: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Disable the Channel 4: Reset the CC4E Bit */
TIMx->CCER &= ~TIM_CCER_CC4E;
8001cae: 687b ldr r3, [r7, #4]
8001cb0: 6a1b ldr r3, [r3, #32]
8001cb2: f423 5280 bic.w r2, r3, #4096 ; 0x1000
8001cb6: 687b ldr r3, [r7, #4]
8001cb8: 621a str r2, [r3, #32]
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
8001cba: 687b ldr r3, [r7, #4]
8001cbc: 6a1b ldr r3, [r3, #32]
8001cbe: 613b str r3, [r7, #16]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
8001cc0: 687b ldr r3, [r7, #4]
8001cc2: 685b ldr r3, [r3, #4]
8001cc4: 617b str r3, [r7, #20]
/* Get the TIMx CCMR2 register value */
tmpccmrx = TIMx->CCMR2;
8001cc6: 687b ldr r3, [r7, #4]
8001cc8: 69db ldr r3, [r3, #28]
8001cca: 60fb str r3, [r7, #12]
/* Reset the Output Compare mode and Capture/Compare selection Bits */
tmpccmrx &= ~TIM_CCMR2_OC4M;
8001ccc: 68fb ldr r3, [r7, #12]
8001cce: f423 43e0 bic.w r3, r3, #28672 ; 0x7000
8001cd2: 60fb str r3, [r7, #12]
tmpccmrx &= ~TIM_CCMR2_CC4S;
8001cd4: 68fb ldr r3, [r7, #12]
8001cd6: f423 7340 bic.w r3, r3, #768 ; 0x300
8001cda: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= (OC_Config->OCMode << 8U);
8001cdc: 683b ldr r3, [r7, #0]
8001cde: 681b ldr r3, [r3, #0]
8001ce0: 021b lsls r3, r3, #8
8001ce2: 68fa ldr r2, [r7, #12]
8001ce4: 4313 orrs r3, r2
8001ce6: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC4P;
8001ce8: 693b ldr r3, [r7, #16]
8001cea: f423 5300 bic.w r3, r3, #8192 ; 0x2000
8001cee: 613b str r3, [r7, #16]
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 12U);
8001cf0: 683b ldr r3, [r7, #0]
8001cf2: 689b ldr r3, [r3, #8]
8001cf4: 031b lsls r3, r3, #12
8001cf6: 693a ldr r2, [r7, #16]
8001cf8: 4313 orrs r3, r2
8001cfa: 613b str r3, [r7, #16]
if (IS_TIM_BREAK_INSTANCE(TIMx))
8001cfc: 687b ldr r3, [r7, #4]
8001cfe: 4a0f ldr r2, [pc, #60] ; (8001d3c <TIM_OC4_SetConfig+0x98>)
8001d00: 4293 cmp r3, r2
8001d02: d109 bne.n 8001d18 <TIM_OC4_SetConfig+0x74>
{
/* Check parameters */
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
/* Reset the Output Compare IDLE State */
tmpcr2 &= ~TIM_CR2_OIS4;
8001d04: 697b ldr r3, [r7, #20]
8001d06: f423 4380 bic.w r3, r3, #16384 ; 0x4000
8001d0a: 617b str r3, [r7, #20]
/* Set the Output Idle state */
tmpcr2 |= (OC_Config->OCIdleState << 6U);
8001d0c: 683b ldr r3, [r7, #0]
8001d0e: 695b ldr r3, [r3, #20]
8001d10: 019b lsls r3, r3, #6
8001d12: 697a ldr r2, [r7, #20]
8001d14: 4313 orrs r3, r2
8001d16: 617b str r3, [r7, #20]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
8001d18: 687b ldr r3, [r7, #4]
8001d1a: 697a ldr r2, [r7, #20]
8001d1c: 605a str r2, [r3, #4]
/* Write to TIMx CCMR2 */
TIMx->CCMR2 = tmpccmrx;
8001d1e: 687b ldr r3, [r7, #4]
8001d20: 68fa ldr r2, [r7, #12]
8001d22: 61da str r2, [r3, #28]
/* Set the Capture Compare Register value */
TIMx->CCR4 = OC_Config->Pulse;
8001d24: 683b ldr r3, [r7, #0]
8001d26: 685a ldr r2, [r3, #4]
8001d28: 687b ldr r3, [r7, #4]
8001d2a: 641a str r2, [r3, #64] ; 0x40
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
8001d2c: 687b ldr r3, [r7, #4]
8001d2e: 693a ldr r2, [r7, #16]
8001d30: 621a str r2, [r3, #32]
}
8001d32: bf00 nop
8001d34: 371c adds r7, #28
8001d36: 46bd mov sp, r7
8001d38: bc80 pop {r7}
8001d3a: 4770 bx lr
8001d3c: 40012c00 .word 0x40012c00
08001d40 <TIM_TI1_ConfigInputStage>:
* @param TIM_ICFilter Specifies the Input Capture Filter.
* This parameter must be a value between 0x00 and 0x0F.
* @retval None
*/
static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
{
8001d40: b480 push {r7}
8001d42: b087 sub sp, #28
8001d44: af00 add r7, sp, #0
8001d46: 60f8 str r0, [r7, #12]
8001d48: 60b9 str r1, [r7, #8]
8001d4a: 607a str r2, [r7, #4]
uint32_t tmpccmr1;
uint32_t tmpccer;
/* Disable the Channel 1: Reset the CC1E Bit */
tmpccer = TIMx->CCER;
8001d4c: 68fb ldr r3, [r7, #12]
8001d4e: 6a1b ldr r3, [r3, #32]
8001d50: 617b str r3, [r7, #20]
TIMx->CCER &= ~TIM_CCER_CC1E;
8001d52: 68fb ldr r3, [r7, #12]
8001d54: 6a1b ldr r3, [r3, #32]
8001d56: f023 0201 bic.w r2, r3, #1
8001d5a: 68fb ldr r3, [r7, #12]
8001d5c: 621a str r2, [r3, #32]
tmpccmr1 = TIMx->CCMR1;
8001d5e: 68fb ldr r3, [r7, #12]
8001d60: 699b ldr r3, [r3, #24]
8001d62: 613b str r3, [r7, #16]
/* Set the filter */
tmpccmr1 &= ~TIM_CCMR1_IC1F;
8001d64: 693b ldr r3, [r7, #16]
8001d66: f023 03f0 bic.w r3, r3, #240 ; 0xf0
8001d6a: 613b str r3, [r7, #16]
tmpccmr1 |= (TIM_ICFilter << 4U);
8001d6c: 687b ldr r3, [r7, #4]
8001d6e: 011b lsls r3, r3, #4
8001d70: 693a ldr r2, [r7, #16]
8001d72: 4313 orrs r3, r2
8001d74: 613b str r3, [r7, #16]
/* Select the Polarity and set the CC1E Bit */
tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
8001d76: 697b ldr r3, [r7, #20]
8001d78: f023 030a bic.w r3, r3, #10
8001d7c: 617b str r3, [r7, #20]
tmpccer |= TIM_ICPolarity;
8001d7e: 697a ldr r2, [r7, #20]
8001d80: 68bb ldr r3, [r7, #8]
8001d82: 4313 orrs r3, r2
8001d84: 617b str r3, [r7, #20]
/* Write to TIMx CCMR1 and CCER registers */
TIMx->CCMR1 = tmpccmr1;
8001d86: 68fb ldr r3, [r7, #12]
8001d88: 693a ldr r2, [r7, #16]
8001d8a: 619a str r2, [r3, #24]
TIMx->CCER = tmpccer;
8001d8c: 68fb ldr r3, [r7, #12]
8001d8e: 697a ldr r2, [r7, #20]
8001d90: 621a str r2, [r3, #32]
}
8001d92: bf00 nop
8001d94: 371c adds r7, #28
8001d96: 46bd mov sp, r7
8001d98: bc80 pop {r7}
8001d9a: 4770 bx lr
08001d9c <TIM_TI2_ConfigInputStage>:
* @param TIM_ICFilter Specifies the Input Capture Filter.
* This parameter must be a value between 0x00 and 0x0F.
* @retval None
*/
static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
{
8001d9c: b480 push {r7}
8001d9e: b087 sub sp, #28
8001da0: af00 add r7, sp, #0
8001da2: 60f8 str r0, [r7, #12]
8001da4: 60b9 str r1, [r7, #8]
8001da6: 607a str r2, [r7, #4]
uint32_t tmpccmr1;
uint32_t tmpccer;
/* Disable the Channel 2: Reset the CC2E Bit */
TIMx->CCER &= ~TIM_CCER_CC2E;
8001da8: 68fb ldr r3, [r7, #12]
8001daa: 6a1b ldr r3, [r3, #32]
8001dac: f023 0210 bic.w r2, r3, #16
8001db0: 68fb ldr r3, [r7, #12]
8001db2: 621a str r2, [r3, #32]
tmpccmr1 = TIMx->CCMR1;
8001db4: 68fb ldr r3, [r7, #12]
8001db6: 699b ldr r3, [r3, #24]
8001db8: 617b str r3, [r7, #20]
tmpccer = TIMx->CCER;
8001dba: 68fb ldr r3, [r7, #12]
8001dbc: 6a1b ldr r3, [r3, #32]
8001dbe: 613b str r3, [r7, #16]
/* Set the filter */
tmpccmr1 &= ~TIM_CCMR1_IC2F;
8001dc0: 697b ldr r3, [r7, #20]
8001dc2: f423 4370 bic.w r3, r3, #61440 ; 0xf000
8001dc6: 617b str r3, [r7, #20]
tmpccmr1 |= (TIM_ICFilter << 12U);
8001dc8: 687b ldr r3, [r7, #4]
8001dca: 031b lsls r3, r3, #12
8001dcc: 697a ldr r2, [r7, #20]
8001dce: 4313 orrs r3, r2
8001dd0: 617b str r3, [r7, #20]
/* Select the Polarity and set the CC2E Bit */
tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
8001dd2: 693b ldr r3, [r7, #16]
8001dd4: f023 03a0 bic.w r3, r3, #160 ; 0xa0
8001dd8: 613b str r3, [r7, #16]
tmpccer |= (TIM_ICPolarity << 4U);
8001dda: 68bb ldr r3, [r7, #8]
8001ddc: 011b lsls r3, r3, #4
8001dde: 693a ldr r2, [r7, #16]
8001de0: 4313 orrs r3, r2
8001de2: 613b str r3, [r7, #16]
/* Write to TIMx CCMR1 and CCER registers */
TIMx->CCMR1 = tmpccmr1 ;
8001de4: 68fb ldr r3, [r7, #12]
8001de6: 697a ldr r2, [r7, #20]
8001de8: 619a str r2, [r3, #24]
TIMx->CCER = tmpccer;
8001dea: 68fb ldr r3, [r7, #12]
8001dec: 693a ldr r2, [r7, #16]
8001dee: 621a str r2, [r3, #32]
}
8001df0: bf00 nop
8001df2: 371c adds r7, #28
8001df4: 46bd mov sp, r7
8001df6: bc80 pop {r7}
8001df8: 4770 bx lr
08001dfa <TIM_ITRx_SetConfig>:
* @arg TIM_TS_TI2FP2: Filtered Timer Input 2
* @arg TIM_TS_ETRF: External Trigger input
* @retval None
*/
static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource)
{
8001dfa: b480 push {r7}
8001dfc: b085 sub sp, #20
8001dfe: af00 add r7, sp, #0
8001e00: 6078 str r0, [r7, #4]
8001e02: 6039 str r1, [r7, #0]
uint32_t tmpsmcr;
/* Get the TIMx SMCR register value */
tmpsmcr = TIMx->SMCR;
8001e04: 687b ldr r3, [r7, #4]
8001e06: 689b ldr r3, [r3, #8]
8001e08: 60fb str r3, [r7, #12]
/* Reset the TS Bits */
tmpsmcr &= ~TIM_SMCR_TS;
8001e0a: 68fb ldr r3, [r7, #12]
8001e0c: f023 0370 bic.w r3, r3, #112 ; 0x70
8001e10: 60fb str r3, [r7, #12]
/* Set the Input Trigger source and the slave mode*/
tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1);
8001e12: 683a ldr r2, [r7, #0]
8001e14: 68fb ldr r3, [r7, #12]
8001e16: 4313 orrs r3, r2
8001e18: f043 0307 orr.w r3, r3, #7
8001e1c: 60fb str r3, [r7, #12]
/* Write to TIMx SMCR */
TIMx->SMCR = tmpsmcr;
8001e1e: 687b ldr r3, [r7, #4]
8001e20: 68fa ldr r2, [r7, #12]
8001e22: 609a str r2, [r3, #8]
}
8001e24: bf00 nop
8001e26: 3714 adds r7, #20
8001e28: 46bd mov sp, r7
8001e2a: bc80 pop {r7}
8001e2c: 4770 bx lr
08001e2e <TIM_ETR_SetConfig>:
* This parameter must be a value between 0x00 and 0x0F
* @retval None
*/
void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
{
8001e2e: b480 push {r7}
8001e30: b087 sub sp, #28
8001e32: af00 add r7, sp, #0
8001e34: 60f8 str r0, [r7, #12]
8001e36: 60b9 str r1, [r7, #8]
8001e38: 607a str r2, [r7, #4]
8001e3a: 603b str r3, [r7, #0]
uint32_t tmpsmcr;
tmpsmcr = TIMx->SMCR;
8001e3c: 68fb ldr r3, [r7, #12]
8001e3e: 689b ldr r3, [r3, #8]
8001e40: 617b str r3, [r7, #20]
/* Reset the ETR Bits */
tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
8001e42: 697b ldr r3, [r7, #20]
8001e44: f423 437f bic.w r3, r3, #65280 ; 0xff00
8001e48: 617b str r3, [r7, #20]
/* Set the Prescaler, the Filter value and the Polarity */
tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));
8001e4a: 683b ldr r3, [r7, #0]
8001e4c: 021a lsls r2, r3, #8
8001e4e: 687b ldr r3, [r7, #4]
8001e50: 431a orrs r2, r3
8001e52: 68bb ldr r3, [r7, #8]
8001e54: 4313 orrs r3, r2
8001e56: 697a ldr r2, [r7, #20]
8001e58: 4313 orrs r3, r2
8001e5a: 617b str r3, [r7, #20]
/* Write to TIMx SMCR */
TIMx->SMCR = tmpsmcr;
8001e5c: 68fb ldr r3, [r7, #12]
8001e5e: 697a ldr r2, [r7, #20]
8001e60: 609a str r2, [r3, #8]
}
8001e62: bf00 nop
8001e64: 371c adds r7, #28
8001e66: 46bd mov sp, r7
8001e68: bc80 pop {r7}
8001e6a: 4770 bx lr
08001e6c <TIM_CCxChannelCmd>:
* @param ChannelState specifies the TIM Channel CCxE bit new state.
* This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE.
* @retval None
*/
void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)
{
8001e6c: b480 push {r7}
8001e6e: b087 sub sp, #28
8001e70: af00 add r7, sp, #0
8001e72: 60f8 str r0, [r7, #12]
8001e74: 60b9 str r1, [r7, #8]
8001e76: 607a str r2, [r7, #4]
/* Check the parameters */
assert_param(IS_TIM_CC1_INSTANCE(TIMx));
assert_param(IS_TIM_CHANNELS(Channel));
tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */
8001e78: 68bb ldr r3, [r7, #8]
8001e7a: f003 031f and.w r3, r3, #31
8001e7e: 2201 movs r2, #1
8001e80: fa02 f303 lsl.w r3, r2, r3
8001e84: 617b str r3, [r7, #20]
/* Reset the CCxE Bit */
TIMx->CCER &= ~tmp;
8001e86: 68fb ldr r3, [r7, #12]
8001e88: 6a1a ldr r2, [r3, #32]
8001e8a: 697b ldr r3, [r7, #20]
8001e8c: 43db mvns r3, r3
8001e8e: 401a ands r2, r3
8001e90: 68fb ldr r3, [r7, #12]
8001e92: 621a str r2, [r3, #32]
/* Set or reset the CCxE Bit */
TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
8001e94: 68fb ldr r3, [r7, #12]
8001e96: 6a1a ldr r2, [r3, #32]
8001e98: 68bb ldr r3, [r7, #8]
8001e9a: f003 031f and.w r3, r3, #31
8001e9e: 6879 ldr r1, [r7, #4]
8001ea0: fa01 f303 lsl.w r3, r1, r3
8001ea4: 431a orrs r2, r3
8001ea6: 68fb ldr r3, [r7, #12]
8001ea8: 621a str r2, [r3, #32]
}
8001eaa: bf00 nop
8001eac: 371c adds r7, #28
8001eae: 46bd mov sp, r7
8001eb0: bc80 pop {r7}
8001eb2: 4770 bx lr
08001eb4 <HAL_TIMEx_MasterConfigSynchronization>:
* mode.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
TIM_MasterConfigTypeDef *sMasterConfig)
{
8001eb4: b480 push {r7}
8001eb6: b085 sub sp, #20
8001eb8: af00 add r7, sp, #0
8001eba: 6078 str r0, [r7, #4]
8001ebc: 6039 str r1, [r7, #0]
assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
/* Check input state */
__HAL_LOCK(htim);
8001ebe: 687b ldr r3, [r7, #4]
8001ec0: f893 303c ldrb.w r3, [r3, #60] ; 0x3c
8001ec4: 2b01 cmp r3, #1
8001ec6: d101 bne.n 8001ecc <HAL_TIMEx_MasterConfigSynchronization+0x18>
8001ec8: 2302 movs r3, #2
8001eca: e046 b.n 8001f5a <HAL_TIMEx_MasterConfigSynchronization+0xa6>
8001ecc: 687b ldr r3, [r7, #4]
8001ece: 2201 movs r2, #1
8001ed0: f883 203c strb.w r2, [r3, #60] ; 0x3c
/* Change the handler state */
htim->State = HAL_TIM_STATE_BUSY;
8001ed4: 687b ldr r3, [r7, #4]
8001ed6: 2202 movs r2, #2
8001ed8: f883 203d strb.w r2, [r3, #61] ; 0x3d
/* Get the TIMx CR2 register value */
tmpcr2 = htim->Instance->CR2;
8001edc: 687b ldr r3, [r7, #4]
8001ede: 681b ldr r3, [r3, #0]
8001ee0: 685b ldr r3, [r3, #4]
8001ee2: 60fb str r3, [r7, #12]
/* Get the TIMx SMCR register value */
tmpsmcr = htim->Instance->SMCR;
8001ee4: 687b ldr r3, [r7, #4]
8001ee6: 681b ldr r3, [r3, #0]
8001ee8: 689b ldr r3, [r3, #8]
8001eea: 60bb str r3, [r7, #8]
/* Reset the MMS Bits */
tmpcr2 &= ~TIM_CR2_MMS;
8001eec: 68fb ldr r3, [r7, #12]
8001eee: f023 0370 bic.w r3, r3, #112 ; 0x70
8001ef2: 60fb str r3, [r7, #12]
/* Select the TRGO source */
tmpcr2 |= sMasterConfig->MasterOutputTrigger;
8001ef4: 683b ldr r3, [r7, #0]
8001ef6: 681b ldr r3, [r3, #0]
8001ef8: 68fa ldr r2, [r7, #12]
8001efa: 4313 orrs r3, r2
8001efc: 60fb str r3, [r7, #12]
/* Update TIMx CR2 */
htim->Instance->CR2 = tmpcr2;
8001efe: 687b ldr r3, [r7, #4]
8001f00: 681b ldr r3, [r3, #0]
8001f02: 68fa ldr r2, [r7, #12]
8001f04: 605a str r2, [r3, #4]
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
8001f06: 687b ldr r3, [r7, #4]
8001f08: 681b ldr r3, [r3, #0]
8001f0a: 4a16 ldr r2, [pc, #88] ; (8001f64 <HAL_TIMEx_MasterConfigSynchronization+0xb0>)
8001f0c: 4293 cmp r3, r2
8001f0e: d00e beq.n 8001f2e <HAL_TIMEx_MasterConfigSynchronization+0x7a>
8001f10: 687b ldr r3, [r7, #4]
8001f12: 681b ldr r3, [r3, #0]
8001f14: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
8001f18: d009 beq.n 8001f2e <HAL_TIMEx_MasterConfigSynchronization+0x7a>
8001f1a: 687b ldr r3, [r7, #4]
8001f1c: 681b ldr r3, [r3, #0]
8001f1e: 4a12 ldr r2, [pc, #72] ; (8001f68 <HAL_TIMEx_MasterConfigSynchronization+0xb4>)
8001f20: 4293 cmp r3, r2
8001f22: d004 beq.n 8001f2e <HAL_TIMEx_MasterConfigSynchronization+0x7a>
8001f24: 687b ldr r3, [r7, #4]
8001f26: 681b ldr r3, [r3, #0]
8001f28: 4a10 ldr r2, [pc, #64] ; (8001f6c <HAL_TIMEx_MasterConfigSynchronization+0xb8>)
8001f2a: 4293 cmp r3, r2
8001f2c: d10c bne.n 8001f48 <HAL_TIMEx_MasterConfigSynchronization+0x94>
{
/* Reset the MSM Bit */
tmpsmcr &= ~TIM_SMCR_MSM;
8001f2e: 68bb ldr r3, [r7, #8]
8001f30: f023 0380 bic.w r3, r3, #128 ; 0x80
8001f34: 60bb str r3, [r7, #8]
/* Set master mode */
tmpsmcr |= sMasterConfig->MasterSlaveMode;
8001f36: 683b ldr r3, [r7, #0]
8001f38: 685b ldr r3, [r3, #4]
8001f3a: 68ba ldr r2, [r7, #8]
8001f3c: 4313 orrs r3, r2
8001f3e: 60bb str r3, [r7, #8]
/* Update TIMx SMCR */
htim->Instance->SMCR = tmpsmcr;
8001f40: 687b ldr r3, [r7, #4]
8001f42: 681b ldr r3, [r3, #0]
8001f44: 68ba ldr r2, [r7, #8]
8001f46: 609a str r2, [r3, #8]
}
/* Change the htim state */
htim->State = HAL_TIM_STATE_READY;
8001f48: 687b ldr r3, [r7, #4]
8001f4a: 2201 movs r2, #1
8001f4c: f883 203d strb.w r2, [r3, #61] ; 0x3d
__HAL_UNLOCK(htim);
8001f50: 687b ldr r3, [r7, #4]
8001f52: 2200 movs r2, #0
8001f54: f883 203c strb.w r2, [r3, #60] ; 0x3c
return HAL_OK;
8001f58: 2300 movs r3, #0
}
8001f5a: 4618 mov r0, r3
8001f5c: 3714 adds r7, #20
8001f5e: 46bd mov sp, r7
8001f60: bc80 pop {r7}
8001f62: 4770 bx lr
8001f64: 40012c00 .word 0x40012c00
8001f68: 40000400 .word 0x40000400
8001f6c: 40000800 .word 0x40000800
08001f70 <__libc_init_array>:
8001f70: b570 push {r4, r5, r6, lr}
8001f72: 2600 movs r6, #0
8001f74: 4d0c ldr r5, [pc, #48] ; (8001fa8 <__libc_init_array+0x38>)
8001f76: 4c0d ldr r4, [pc, #52] ; (8001fac <__libc_init_array+0x3c>)
8001f78: 1b64 subs r4, r4, r5
8001f7a: 10a4 asrs r4, r4, #2
8001f7c: 42a6 cmp r6, r4
8001f7e: d109 bne.n 8001f94 <__libc_init_array+0x24>
8001f80: f000 f822 bl 8001fc8 <_init>
8001f84: 2600 movs r6, #0
8001f86: 4d0a ldr r5, [pc, #40] ; (8001fb0 <__libc_init_array+0x40>)
8001f88: 4c0a ldr r4, [pc, #40] ; (8001fb4 <__libc_init_array+0x44>)
8001f8a: 1b64 subs r4, r4, r5
8001f8c: 10a4 asrs r4, r4, #2
8001f8e: 42a6 cmp r6, r4
8001f90: d105 bne.n 8001f9e <__libc_init_array+0x2e>
8001f92: bd70 pop {r4, r5, r6, pc}
8001f94: f855 3b04 ldr.w r3, [r5], #4
8001f98: 4798 blx r3
8001f9a: 3601 adds r6, #1
8001f9c: e7ee b.n 8001f7c <__libc_init_array+0xc>
8001f9e: f855 3b04 ldr.w r3, [r5], #4
8001fa2: 4798 blx r3
8001fa4: 3601 adds r6, #1
8001fa6: e7f2 b.n 8001f8e <__libc_init_array+0x1e>
8001fa8: 08002000 .word 0x08002000
8001fac: 08002000 .word 0x08002000
8001fb0: 08002000 .word 0x08002000
8001fb4: 08002004 .word 0x08002004
08001fb8 <memset>:
8001fb8: 4603 mov r3, r0
8001fba: 4402 add r2, r0
8001fbc: 4293 cmp r3, r2
8001fbe: d100 bne.n 8001fc2 <memset+0xa>
8001fc0: 4770 bx lr
8001fc2: f803 1b01 strb.w r1, [r3], #1
8001fc6: e7f9 b.n 8001fbc <memset+0x4>
08001fc8 <_init>:
8001fc8: b5f8 push {r3, r4, r5, r6, r7, lr}
8001fca: bf00 nop
8001fcc: bcf8 pop {r3, r4, r5, r6, r7}
8001fce: bc08 pop {r3}
8001fd0: 469e mov lr, r3
8001fd2: 4770 bx lr
08001fd4 <_fini>:
8001fd4: b5f8 push {r3, r4, r5, r6, r7, lr}
8001fd6: bf00 nop
8001fd8: bcf8 pop {r3, r4, r5, r6, r7}
8001fda: bc08 pop {r3}
8001fdc: 469e mov lr, r3
8001fde: 4770 bx lr
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