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5542 lines
207 KiB
Plaintext
5542 lines
207 KiB
Plaintext
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PWM_Servo.elf: file format elf32-littlearm
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Sections:
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Idx Name Size VMA LMA File off Algn
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0 .isr_vector 0000010c 08000000 08000000 00010000 2**0
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CONTENTS, ALLOC, LOAD, READONLY, DATA
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1 .text 00001dcc 0800010c 0800010c 0001010c 2**2
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CONTENTS, ALLOC, LOAD, READONLY, CODE
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2 .rodata 00000020 08001ed8 08001ed8 00011ed8 2**2
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CONTENTS, ALLOC, LOAD, READONLY, DATA
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3 .ARM.extab 00000000 08001ef8 08001ef8 0002000c 2**0
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CONTENTS
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4 .ARM 00000000 08001ef8 08001ef8 0002000c 2**0
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CONTENTS
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5 .preinit_array 00000000 08001ef8 08001ef8 0002000c 2**0
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CONTENTS, ALLOC, LOAD, DATA
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6 .init_array 00000004 08001ef8 08001ef8 00011ef8 2**2
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CONTENTS, ALLOC, LOAD, DATA
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7 .fini_array 00000004 08001efc 08001efc 00011efc 2**2
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CONTENTS, ALLOC, LOAD, DATA
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8 .data 0000000c 20000000 08001f00 00020000 2**2
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CONTENTS, ALLOC, LOAD, DATA
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9 .bss 00000068 2000000c 08001f0c 0002000c 2**2
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ALLOC
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10 ._user_heap_stack 00000604 20000074 08001f0c 00020074 2**0
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ALLOC
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11 .ARM.attributes 00000029 00000000 00000000 0002000c 2**0
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CONTENTS, READONLY
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12 .debug_info 00007971 00000000 00000000 00020035 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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13 .debug_abbrev 00001572 00000000 00000000 000279a6 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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14 .debug_aranges 00000958 00000000 00000000 00028f18 2**3
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CONTENTS, READONLY, DEBUGGING, OCTETS
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15 .debug_ranges 00000890 00000000 00000000 00029870 2**3
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CONTENTS, READONLY, DEBUGGING, OCTETS
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16 .debug_macro 000168cb 00000000 00000000 0002a100 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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17 .debug_line 00009f20 00000000 00000000 000409cb 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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18 .debug_str 00083de3 00000000 00000000 0004a8eb 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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19 .comment 00000050 00000000 00000000 000ce6ce 2**0
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CONTENTS, READONLY
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20 .debug_frame 000025e0 00000000 00000000 000ce720 2**2
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CONTENTS, READONLY, DEBUGGING, OCTETS
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Disassembly of section .text:
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0800010c <__do_global_dtors_aux>:
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800010c: b510 push {r4, lr}
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800010e: 4c05 ldr r4, [pc, #20] ; (8000124 <__do_global_dtors_aux+0x18>)
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8000110: 7823 ldrb r3, [r4, #0]
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8000112: b933 cbnz r3, 8000122 <__do_global_dtors_aux+0x16>
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8000114: 4b04 ldr r3, [pc, #16] ; (8000128 <__do_global_dtors_aux+0x1c>)
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8000116: b113 cbz r3, 800011e <__do_global_dtors_aux+0x12>
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8000118: 4804 ldr r0, [pc, #16] ; (800012c <__do_global_dtors_aux+0x20>)
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800011a: f3af 8000 nop.w
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800011e: 2301 movs r3, #1
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8000120: 7023 strb r3, [r4, #0]
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8000122: bd10 pop {r4, pc}
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8000124: 2000000c .word 0x2000000c
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8000128: 00000000 .word 0x00000000
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800012c: 08001ec0 .word 0x08001ec0
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08000130 <frame_dummy>:
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8000130: b508 push {r3, lr}
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8000132: 4b03 ldr r3, [pc, #12] ; (8000140 <frame_dummy+0x10>)
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8000134: b11b cbz r3, 800013e <frame_dummy+0xe>
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8000136: 4903 ldr r1, [pc, #12] ; (8000144 <frame_dummy+0x14>)
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8000138: 4803 ldr r0, [pc, #12] ; (8000148 <frame_dummy+0x18>)
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800013a: f3af 8000 nop.w
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800013e: bd08 pop {r3, pc}
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8000140: 00000000 .word 0x00000000
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8000144: 20000010 .word 0x20000010
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8000148: 08001ec0 .word 0x08001ec0
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0800014c <MX_GPIO_Init>:
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* Output
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* EVENT_OUT
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* EXTI
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*/
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void MX_GPIO_Init(void)
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{
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800014c: b480 push {r7}
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800014e: b083 sub sp, #12
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8000150: af00 add r7, sp, #0
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/* GPIO Ports Clock Enable */
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__HAL_RCC_GPIOD_CLK_ENABLE();
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8000152: 4b0e ldr r3, [pc, #56] ; (800018c <MX_GPIO_Init+0x40>)
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8000154: 699b ldr r3, [r3, #24]
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8000156: 4a0d ldr r2, [pc, #52] ; (800018c <MX_GPIO_Init+0x40>)
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8000158: f043 0320 orr.w r3, r3, #32
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800015c: 6193 str r3, [r2, #24]
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800015e: 4b0b ldr r3, [pc, #44] ; (800018c <MX_GPIO_Init+0x40>)
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8000160: 699b ldr r3, [r3, #24]
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8000162: f003 0320 and.w r3, r3, #32
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8000166: 607b str r3, [r7, #4]
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8000168: 687b ldr r3, [r7, #4]
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__HAL_RCC_GPIOB_CLK_ENABLE();
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800016a: 4b08 ldr r3, [pc, #32] ; (800018c <MX_GPIO_Init+0x40>)
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800016c: 699b ldr r3, [r3, #24]
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800016e: 4a07 ldr r2, [pc, #28] ; (800018c <MX_GPIO_Init+0x40>)
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8000170: f043 0308 orr.w r3, r3, #8
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8000174: 6193 str r3, [r2, #24]
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8000176: 4b05 ldr r3, [pc, #20] ; (800018c <MX_GPIO_Init+0x40>)
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8000178: 699b ldr r3, [r3, #24]
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800017a: f003 0308 and.w r3, r3, #8
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800017e: 603b str r3, [r7, #0]
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8000180: 683b ldr r3, [r7, #0]
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}
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8000182: bf00 nop
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8000184: 370c adds r7, #12
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8000186: 46bd mov sp, r7
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8000188: bc80 pop {r7}
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800018a: 4770 bx lr
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800018c: 40021000 .word 0x40021000
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08000190 <main>:
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/**
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* @brief The application entry point.
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* @retval int
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*/
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int main(void) {
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8000190: b580 push {r7, lr}
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8000192: b082 sub sp, #8
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8000194: af00 add r7, sp, #0
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/* USER CODE END 1 */
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/* MCU Configuration--------------------------------------------------------*/
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/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
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HAL_Init();
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8000196: f000 f9c3 bl 8000520 <HAL_Init>
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/* USER CODE BEGIN Init */
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/* USER CODE END Init */
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/* Configure the system clock */
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SystemClock_Config();
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800019a: f000 f837 bl 800020c <SystemClock_Config>
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/* USER CODE BEGIN SysInit */
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/* USER CODE END SysInit */
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/* Initialize all configured peripherals */
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MX_GPIO_Init();
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800019e: f7ff ffd5 bl 800014c <MX_GPIO_Init>
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MX_TIM4_Init();
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80001a2: f000 f8cd bl 8000340 <MX_TIM4_Init>
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/* USER CODE BEGIN 2 */
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HAL_TIM_PWM_Start(&htim4, TIM_CHANNEL_3);
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80001a6: 2108 movs r1, #8
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80001a8: 4817 ldr r0, [pc, #92] ; (8000208 <main+0x78>)
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80001aa: f001 f937 bl 800141c <HAL_TIM_PWM_Start>
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/* USER CODE END 2 */
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/* Infinite loop */
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/* USER CODE BEGIN WHILE */
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uint16_t servoPeriod = 100;
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80001ae: 2364 movs r3, #100 ; 0x64
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80001b0: 80fb strh r3, [r7, #6]
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uint8_t direction = 0;
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80001b2: 2300 movs r3, #0
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80001b4: 717b strb r3, [r7, #5]
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while (1) {
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if (direction) {
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80001b6: 797b ldrb r3, [r7, #5]
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80001b8: 2b00 cmp r3, #0
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80001ba: d010 beq.n 80001de <main+0x4e>
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__HAL_TIM_SET_COMPARE(&htim4, TIM_CHANNEL_3, servoPeriod++);
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80001bc: 88fb ldrh r3, [r7, #6]
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80001be: 1c5a adds r2, r3, #1
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80001c0: 80fa strh r2, [r7, #6]
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80001c2: 4a11 ldr r2, [pc, #68] ; (8000208 <main+0x78>)
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80001c4: 6812 ldr r2, [r2, #0]
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80001c6: 63d3 str r3, [r2, #60] ; 0x3c
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if (servoPeriod >= 250) {
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80001c8: 88fb ldrh r3, [r7, #6]
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80001ca: 2bf9 cmp r3, #249 ; 0xf9
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80001cc: d917 bls.n 80001fe <main+0x6e>
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direction = !direction;
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80001ce: 797b ldrb r3, [r7, #5]
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80001d0: 2b00 cmp r3, #0
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80001d2: bf0c ite eq
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80001d4: 2301 moveq r3, #1
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80001d6: 2300 movne r3, #0
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80001d8: b2db uxtb r3, r3
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80001da: 717b strb r3, [r7, #5]
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80001dc: e00f b.n 80001fe <main+0x6e>
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}
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} else {
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__HAL_TIM_SET_COMPARE(&htim4, TIM_CHANNEL_3, servoPeriod--);
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80001de: 88fb ldrh r3, [r7, #6]
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80001e0: 1e5a subs r2, r3, #1
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80001e2: 80fa strh r2, [r7, #6]
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80001e4: 4a08 ldr r2, [pc, #32] ; (8000208 <main+0x78>)
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80001e6: 6812 ldr r2, [r2, #0]
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80001e8: 63d3 str r3, [r2, #60] ; 0x3c
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if (servoPeriod <= 50) {
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80001ea: 88fb ldrh r3, [r7, #6]
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80001ec: 2b32 cmp r3, #50 ; 0x32
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80001ee: d806 bhi.n 80001fe <main+0x6e>
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direction = !direction;
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80001f0: 797b ldrb r3, [r7, #5]
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80001f2: 2b00 cmp r3, #0
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80001f4: bf0c ite eq
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80001f6: 2301 moveq r3, #1
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80001f8: 2300 movne r3, #0
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80001fa: b2db uxtb r3, r3
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80001fc: 717b strb r3, [r7, #5]
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}
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}
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HAL_Delay(5);
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80001fe: 2005 movs r0, #5
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8000200: f000 f9f0 bl 80005e4 <HAL_Delay>
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if (direction) {
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8000204: e7d7 b.n 80001b6 <main+0x26>
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8000206: bf00 nop
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8000208: 20000028 .word 0x20000028
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0800020c <SystemClock_Config>:
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/**
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* @brief System Clock Configuration
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* @retval None
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*/
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void SystemClock_Config(void) {
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800020c: b580 push {r7, lr}
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800020e: b090 sub sp, #64 ; 0x40
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8000210: af00 add r7, sp, #0
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RCC_OscInitTypeDef RCC_OscInitStruct = { 0 };
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8000212: f107 0318 add.w r3, r7, #24
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8000216: 2228 movs r2, #40 ; 0x28
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8000218: 2100 movs r1, #0
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800021a: 4618 mov r0, r3
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800021c: f001 fe48 bl 8001eb0 <memset>
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RCC_ClkInitTypeDef RCC_ClkInitStruct = { 0 };
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8000220: 1d3b adds r3, r7, #4
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8000222: 2200 movs r2, #0
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8000224: 601a str r2, [r3, #0]
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8000226: 605a str r2, [r3, #4]
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8000228: 609a str r2, [r3, #8]
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800022a: 60da str r2, [r3, #12]
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800022c: 611a str r2, [r3, #16]
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/** Initializes the RCC Oscillators according to the specified parameters
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* in the RCC_OscInitTypeDef structure.
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*/
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RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
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800022e: 2301 movs r3, #1
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8000230: 61bb str r3, [r7, #24]
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RCC_OscInitStruct.HSEState = RCC_HSE_ON;
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8000232: f44f 3380 mov.w r3, #65536 ; 0x10000
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8000236: 61fb str r3, [r7, #28]
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RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV1;
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8000238: 2300 movs r3, #0
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800023a: 623b str r3, [r7, #32]
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RCC_OscInitStruct.HSIState = RCC_HSI_ON;
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800023c: 2301 movs r3, #1
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800023e: 62bb str r3, [r7, #40] ; 0x28
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RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
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8000240: 2302 movs r3, #2
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8000242: 637b str r3, [r7, #52] ; 0x34
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RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
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8000244: f44f 3380 mov.w r3, #65536 ; 0x10000
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8000248: 63bb str r3, [r7, #56] ; 0x38
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RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9;
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800024a: f44f 13e0 mov.w r3, #1835008 ; 0x1c0000
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800024e: 63fb str r3, [r7, #60] ; 0x3c
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if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
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8000250: f107 0318 add.w r3, r7, #24
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8000254: 4618 mov r0, r3
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8000256: f000 fc51 bl 8000afc <HAL_RCC_OscConfig>
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800025a: 4603 mov r3, r0
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800025c: 2b00 cmp r3, #0
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800025e: d001 beq.n 8000264 <SystemClock_Config+0x58>
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Error_Handler();
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8000260: f000 f819 bl 8000296 <Error_Handler>
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}
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/** Initializes the CPU, AHB and APB buses clocks
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*/
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RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
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8000264: 230f movs r3, #15
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8000266: 607b str r3, [r7, #4]
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| RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
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RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
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8000268: 2302 movs r3, #2
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800026a: 60bb str r3, [r7, #8]
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RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
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800026c: 2300 movs r3, #0
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800026e: 60fb str r3, [r7, #12]
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RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
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8000270: f44f 6380 mov.w r3, #1024 ; 0x400
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8000274: 613b str r3, [r7, #16]
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RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
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8000276: 2300 movs r3, #0
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8000278: 617b str r3, [r7, #20]
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if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) {
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800027a: 1d3b adds r3, r7, #4
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800027c: 2102 movs r1, #2
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800027e: 4618 mov r0, r3
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8000280: f000 febe bl 8001000 <HAL_RCC_ClockConfig>
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8000284: 4603 mov r3, r0
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8000286: 2b00 cmp r3, #0
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8000288: d001 beq.n 800028e <SystemClock_Config+0x82>
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Error_Handler();
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800028a: f000 f804 bl 8000296 <Error_Handler>
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}
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}
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800028e: bf00 nop
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8000290: 3740 adds r7, #64 ; 0x40
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8000292: 46bd mov sp, r7
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8000294: bd80 pop {r7, pc}
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08000296 <Error_Handler>:
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|
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/**
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|
* @brief This function is executed in case of error occurrence.
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* @retval None
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*/
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|
void Error_Handler(void) {
|
|
8000296: b480 push {r7}
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|
8000298: af00 add r7, sp, #0
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\details Disables IRQ interrupts by setting the I-bit in the CPSR.
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|
Can only be executed in Privileged modes.
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|
*/
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__STATIC_FORCEINLINE void __disable_irq(void)
|
|
{
|
|
__ASM volatile ("cpsid i" : : : "memory");
|
|
800029a: b672 cpsid i
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|
}
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800029c: bf00 nop
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|
/* USER CODE BEGIN Error_Handler_Debug */
|
|
/* User can add his own implementation to report the HAL error return state */
|
|
__disable_irq();
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while (1) {
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|
800029e: e7fe b.n 800029e <Error_Handler+0x8>
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|
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080002a0 <HAL_MspInit>:
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|
/* USER CODE END 0 */
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|
/**
|
|
* Initializes the Global MSP.
|
|
*/
|
|
void HAL_MspInit(void)
|
|
{
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|
80002a0: b480 push {r7}
|
|
80002a2: b083 sub sp, #12
|
|
80002a4: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN MspInit 0 */
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|
|
|
/* USER CODE END MspInit 0 */
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|
|
__HAL_RCC_AFIO_CLK_ENABLE();
|
|
80002a6: 4b0e ldr r3, [pc, #56] ; (80002e0 <HAL_MspInit+0x40>)
|
|
80002a8: 699b ldr r3, [r3, #24]
|
|
80002aa: 4a0d ldr r2, [pc, #52] ; (80002e0 <HAL_MspInit+0x40>)
|
|
80002ac: f043 0301 orr.w r3, r3, #1
|
|
80002b0: 6193 str r3, [r2, #24]
|
|
80002b2: 4b0b ldr r3, [pc, #44] ; (80002e0 <HAL_MspInit+0x40>)
|
|
80002b4: 699b ldr r3, [r3, #24]
|
|
80002b6: f003 0301 and.w r3, r3, #1
|
|
80002ba: 607b str r3, [r7, #4]
|
|
80002bc: 687b ldr r3, [r7, #4]
|
|
__HAL_RCC_PWR_CLK_ENABLE();
|
|
80002be: 4b08 ldr r3, [pc, #32] ; (80002e0 <HAL_MspInit+0x40>)
|
|
80002c0: 69db ldr r3, [r3, #28]
|
|
80002c2: 4a07 ldr r2, [pc, #28] ; (80002e0 <HAL_MspInit+0x40>)
|
|
80002c4: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
|
|
80002c8: 61d3 str r3, [r2, #28]
|
|
80002ca: 4b05 ldr r3, [pc, #20] ; (80002e0 <HAL_MspInit+0x40>)
|
|
80002cc: 69db ldr r3, [r3, #28]
|
|
80002ce: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
|
|
80002d2: 603b str r3, [r7, #0]
|
|
80002d4: 683b ldr r3, [r7, #0]
|
|
/* System interrupt init*/
|
|
|
|
/* USER CODE BEGIN MspInit 1 */
|
|
|
|
/* USER CODE END MspInit 1 */
|
|
}
|
|
80002d6: bf00 nop
|
|
80002d8: 370c adds r7, #12
|
|
80002da: 46bd mov sp, r7
|
|
80002dc: bc80 pop {r7}
|
|
80002de: 4770 bx lr
|
|
80002e0: 40021000 .word 0x40021000
|
|
|
|
080002e4 <NMI_Handler>:
|
|
/******************************************************************************/
|
|
/**
|
|
* @brief This function handles Non maskable interrupt.
|
|
*/
|
|
void NMI_Handler(void)
|
|
{
|
|
80002e4: b480 push {r7}
|
|
80002e6: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
|
|
|
|
/* USER CODE END NonMaskableInt_IRQn 0 */
|
|
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
|
|
while (1)
|
|
80002e8: e7fe b.n 80002e8 <NMI_Handler+0x4>
|
|
|
|
080002ea <HardFault_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Hard fault interrupt.
|
|
*/
|
|
void HardFault_Handler(void)
|
|
{
|
|
80002ea: b480 push {r7}
|
|
80002ec: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN HardFault_IRQn 0 */
|
|
|
|
/* USER CODE END HardFault_IRQn 0 */
|
|
while (1)
|
|
80002ee: e7fe b.n 80002ee <HardFault_Handler+0x4>
|
|
|
|
080002f0 <MemManage_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Memory management fault.
|
|
*/
|
|
void MemManage_Handler(void)
|
|
{
|
|
80002f0: b480 push {r7}
|
|
80002f2: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN MemoryManagement_IRQn 0 */
|
|
|
|
/* USER CODE END MemoryManagement_IRQn 0 */
|
|
while (1)
|
|
80002f4: e7fe b.n 80002f4 <MemManage_Handler+0x4>
|
|
|
|
080002f6 <BusFault_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Prefetch fault, memory access fault.
|
|
*/
|
|
void BusFault_Handler(void)
|
|
{
|
|
80002f6: b480 push {r7}
|
|
80002f8: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN BusFault_IRQn 0 */
|
|
|
|
/* USER CODE END BusFault_IRQn 0 */
|
|
while (1)
|
|
80002fa: e7fe b.n 80002fa <BusFault_Handler+0x4>
|
|
|
|
080002fc <UsageFault_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Undefined instruction or illegal state.
|
|
*/
|
|
void UsageFault_Handler(void)
|
|
{
|
|
80002fc: b480 push {r7}
|
|
80002fe: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN UsageFault_IRQn 0 */
|
|
|
|
/* USER CODE END UsageFault_IRQn 0 */
|
|
while (1)
|
|
8000300: e7fe b.n 8000300 <UsageFault_Handler+0x4>
|
|
|
|
08000302 <SVC_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles System service call via SWI instruction.
|
|
*/
|
|
void SVC_Handler(void)
|
|
{
|
|
8000302: b480 push {r7}
|
|
8000304: af00 add r7, sp, #0
|
|
|
|
/* USER CODE END SVCall_IRQn 0 */
|
|
/* USER CODE BEGIN SVCall_IRQn 1 */
|
|
|
|
/* USER CODE END SVCall_IRQn 1 */
|
|
}
|
|
8000306: bf00 nop
|
|
8000308: 46bd mov sp, r7
|
|
800030a: bc80 pop {r7}
|
|
800030c: 4770 bx lr
|
|
|
|
0800030e <DebugMon_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Debug monitor.
|
|
*/
|
|
void DebugMon_Handler(void)
|
|
{
|
|
800030e: b480 push {r7}
|
|
8000310: af00 add r7, sp, #0
|
|
|
|
/* USER CODE END DebugMonitor_IRQn 0 */
|
|
/* USER CODE BEGIN DebugMonitor_IRQn 1 */
|
|
|
|
/* USER CODE END DebugMonitor_IRQn 1 */
|
|
}
|
|
8000312: bf00 nop
|
|
8000314: 46bd mov sp, r7
|
|
8000316: bc80 pop {r7}
|
|
8000318: 4770 bx lr
|
|
|
|
0800031a <PendSV_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Pendable request for system service.
|
|
*/
|
|
void PendSV_Handler(void)
|
|
{
|
|
800031a: b480 push {r7}
|
|
800031c: af00 add r7, sp, #0
|
|
|
|
/* USER CODE END PendSV_IRQn 0 */
|
|
/* USER CODE BEGIN PendSV_IRQn 1 */
|
|
|
|
/* USER CODE END PendSV_IRQn 1 */
|
|
}
|
|
800031e: bf00 nop
|
|
8000320: 46bd mov sp, r7
|
|
8000322: bc80 pop {r7}
|
|
8000324: 4770 bx lr
|
|
|
|
08000326 <SysTick_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles System tick timer.
|
|
*/
|
|
void SysTick_Handler(void)
|
|
{
|
|
8000326: b580 push {r7, lr}
|
|
8000328: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN SysTick_IRQn 0 */
|
|
|
|
/* USER CODE END SysTick_IRQn 0 */
|
|
HAL_IncTick();
|
|
800032a: f000 f93f bl 80005ac <HAL_IncTick>
|
|
/* USER CODE BEGIN SysTick_IRQn 1 */
|
|
|
|
/* USER CODE END SysTick_IRQn 1 */
|
|
}
|
|
800032e: bf00 nop
|
|
8000330: bd80 pop {r7, pc}
|
|
|
|
08000332 <SystemInit>:
|
|
* @note This function should be used only after reset.
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
void SystemInit (void)
|
|
{
|
|
8000332: b480 push {r7}
|
|
8000334: af00 add r7, sp, #0
|
|
|
|
/* Configure the Vector Table location -------------------------------------*/
|
|
#if defined(USER_VECT_TAB_ADDRESS)
|
|
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
|
|
#endif /* USER_VECT_TAB_ADDRESS */
|
|
}
|
|
8000336: bf00 nop
|
|
8000338: 46bd mov sp, r7
|
|
800033a: bc80 pop {r7}
|
|
800033c: 4770 bx lr
|
|
...
|
|
|
|
08000340 <MX_TIM4_Init>:
|
|
|
|
TIM_HandleTypeDef htim4;
|
|
|
|
/* TIM4 init function */
|
|
void MX_TIM4_Init(void)
|
|
{
|
|
8000340: b580 push {r7, lr}
|
|
8000342: b08e sub sp, #56 ; 0x38
|
|
8000344: af00 add r7, sp, #0
|
|
|
|
/* USER CODE BEGIN TIM4_Init 0 */
|
|
|
|
/* USER CODE END TIM4_Init 0 */
|
|
|
|
TIM_ClockConfigTypeDef sClockSourceConfig = {0};
|
|
8000346: f107 0328 add.w r3, r7, #40 ; 0x28
|
|
800034a: 2200 movs r2, #0
|
|
800034c: 601a str r2, [r3, #0]
|
|
800034e: 605a str r2, [r3, #4]
|
|
8000350: 609a str r2, [r3, #8]
|
|
8000352: 60da str r2, [r3, #12]
|
|
TIM_MasterConfigTypeDef sMasterConfig = {0};
|
|
8000354: f107 0320 add.w r3, r7, #32
|
|
8000358: 2200 movs r2, #0
|
|
800035a: 601a str r2, [r3, #0]
|
|
800035c: 605a str r2, [r3, #4]
|
|
TIM_OC_InitTypeDef sConfigOC = {0};
|
|
800035e: 1d3b adds r3, r7, #4
|
|
8000360: 2200 movs r2, #0
|
|
8000362: 601a str r2, [r3, #0]
|
|
8000364: 605a str r2, [r3, #4]
|
|
8000366: 609a str r2, [r3, #8]
|
|
8000368: 60da str r2, [r3, #12]
|
|
800036a: 611a str r2, [r3, #16]
|
|
800036c: 615a str r2, [r3, #20]
|
|
800036e: 619a str r2, [r3, #24]
|
|
|
|
/* USER CODE BEGIN TIM4_Init 1 */
|
|
|
|
/* USER CODE END TIM4_Init 1 */
|
|
htim4.Instance = TIM4;
|
|
8000370: 4b2d ldr r3, [pc, #180] ; (8000428 <MX_TIM4_Init+0xe8>)
|
|
8000372: 4a2e ldr r2, [pc, #184] ; (800042c <MX_TIM4_Init+0xec>)
|
|
8000374: 601a str r2, [r3, #0]
|
|
htim4.Init.Prescaler = 720-1;
|
|
8000376: 4b2c ldr r3, [pc, #176] ; (8000428 <MX_TIM4_Init+0xe8>)
|
|
8000378: f240 22cf movw r2, #719 ; 0x2cf
|
|
800037c: 605a str r2, [r3, #4]
|
|
htim4.Init.CounterMode = TIM_COUNTERMODE_UP;
|
|
800037e: 4b2a ldr r3, [pc, #168] ; (8000428 <MX_TIM4_Init+0xe8>)
|
|
8000380: 2200 movs r2, #0
|
|
8000382: 609a str r2, [r3, #8]
|
|
htim4.Init.Period = 2000-1;
|
|
8000384: 4b28 ldr r3, [pc, #160] ; (8000428 <MX_TIM4_Init+0xe8>)
|
|
8000386: f240 72cf movw r2, #1999 ; 0x7cf
|
|
800038a: 60da str r2, [r3, #12]
|
|
htim4.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
|
|
800038c: 4b26 ldr r3, [pc, #152] ; (8000428 <MX_TIM4_Init+0xe8>)
|
|
800038e: 2200 movs r2, #0
|
|
8000390: 611a str r2, [r3, #16]
|
|
htim4.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
|
|
8000392: 4b25 ldr r3, [pc, #148] ; (8000428 <MX_TIM4_Init+0xe8>)
|
|
8000394: 2200 movs r2, #0
|
|
8000396: 619a str r2, [r3, #24]
|
|
if (HAL_TIM_Base_Init(&htim4) != HAL_OK)
|
|
8000398: 4823 ldr r0, [pc, #140] ; (8000428 <MX_TIM4_Init+0xe8>)
|
|
800039a: f000 ff97 bl 80012cc <HAL_TIM_Base_Init>
|
|
800039e: 4603 mov r3, r0
|
|
80003a0: 2b00 cmp r3, #0
|
|
80003a2: d001 beq.n 80003a8 <MX_TIM4_Init+0x68>
|
|
{
|
|
Error_Handler();
|
|
80003a4: f7ff ff77 bl 8000296 <Error_Handler>
|
|
}
|
|
sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
|
|
80003a8: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
80003ac: 62bb str r3, [r7, #40] ; 0x28
|
|
if (HAL_TIM_ConfigClockSource(&htim4, &sClockSourceConfig) != HAL_OK)
|
|
80003ae: f107 0328 add.w r3, r7, #40 ; 0x28
|
|
80003b2: 4619 mov r1, r3
|
|
80003b4: 481c ldr r0, [pc, #112] ; (8000428 <MX_TIM4_Init+0xe8>)
|
|
80003b6: f001 f991 bl 80016dc <HAL_TIM_ConfigClockSource>
|
|
80003ba: 4603 mov r3, r0
|
|
80003bc: 2b00 cmp r3, #0
|
|
80003be: d001 beq.n 80003c4 <MX_TIM4_Init+0x84>
|
|
{
|
|
Error_Handler();
|
|
80003c0: f7ff ff69 bl 8000296 <Error_Handler>
|
|
}
|
|
if (HAL_TIM_PWM_Init(&htim4) != HAL_OK)
|
|
80003c4: 4818 ldr r0, [pc, #96] ; (8000428 <MX_TIM4_Init+0xe8>)
|
|
80003c6: f000 ffd0 bl 800136a <HAL_TIM_PWM_Init>
|
|
80003ca: 4603 mov r3, r0
|
|
80003cc: 2b00 cmp r3, #0
|
|
80003ce: d001 beq.n 80003d4 <MX_TIM4_Init+0x94>
|
|
{
|
|
Error_Handler();
|
|
80003d0: f7ff ff61 bl 8000296 <Error_Handler>
|
|
}
|
|
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
|
|
80003d4: 2300 movs r3, #0
|
|
80003d6: 623b str r3, [r7, #32]
|
|
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
|
|
80003d8: 2300 movs r3, #0
|
|
80003da: 627b str r3, [r7, #36] ; 0x24
|
|
if (HAL_TIMEx_MasterConfigSynchronization(&htim4, &sMasterConfig) != HAL_OK)
|
|
80003dc: f107 0320 add.w r3, r7, #32
|
|
80003e0: 4619 mov r1, r3
|
|
80003e2: 4811 ldr r0, [pc, #68] ; (8000428 <MX_TIM4_Init+0xe8>)
|
|
80003e4: f001 fce2 bl 8001dac <HAL_TIMEx_MasterConfigSynchronization>
|
|
80003e8: 4603 mov r3, r0
|
|
80003ea: 2b00 cmp r3, #0
|
|
80003ec: d001 beq.n 80003f2 <MX_TIM4_Init+0xb2>
|
|
{
|
|
Error_Handler();
|
|
80003ee: f7ff ff52 bl 8000296 <Error_Handler>
|
|
}
|
|
sConfigOC.OCMode = TIM_OCMODE_PWM1;
|
|
80003f2: 2360 movs r3, #96 ; 0x60
|
|
80003f4: 607b str r3, [r7, #4]
|
|
sConfigOC.Pulse = 150;
|
|
80003f6: 2396 movs r3, #150 ; 0x96
|
|
80003f8: 60bb str r3, [r7, #8]
|
|
sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
|
|
80003fa: 2300 movs r3, #0
|
|
80003fc: 60fb str r3, [r7, #12]
|
|
sConfigOC.OCFastMode = TIM_OCFAST_DISABLE;
|
|
80003fe: 2300 movs r3, #0
|
|
8000400: 617b str r3, [r7, #20]
|
|
if (HAL_TIM_PWM_ConfigChannel(&htim4, &sConfigOC, TIM_CHANNEL_3) != HAL_OK)
|
|
8000402: 1d3b adds r3, r7, #4
|
|
8000404: 2208 movs r2, #8
|
|
8000406: 4619 mov r1, r3
|
|
8000408: 4807 ldr r0, [pc, #28] ; (8000428 <MX_TIM4_Init+0xe8>)
|
|
800040a: f001 f8a9 bl 8001560 <HAL_TIM_PWM_ConfigChannel>
|
|
800040e: 4603 mov r3, r0
|
|
8000410: 2b00 cmp r3, #0
|
|
8000412: d001 beq.n 8000418 <MX_TIM4_Init+0xd8>
|
|
{
|
|
Error_Handler();
|
|
8000414: f7ff ff3f bl 8000296 <Error_Handler>
|
|
}
|
|
/* USER CODE BEGIN TIM4_Init 2 */
|
|
|
|
/* USER CODE END TIM4_Init 2 */
|
|
HAL_TIM_MspPostInit(&htim4);
|
|
8000418: 4803 ldr r0, [pc, #12] ; (8000428 <MX_TIM4_Init+0xe8>)
|
|
800041a: f000 f827 bl 800046c <HAL_TIM_MspPostInit>
|
|
|
|
}
|
|
800041e: bf00 nop
|
|
8000420: 3738 adds r7, #56 ; 0x38
|
|
8000422: 46bd mov sp, r7
|
|
8000424: bd80 pop {r7, pc}
|
|
8000426: bf00 nop
|
|
8000428: 20000028 .word 0x20000028
|
|
800042c: 40000800 .word 0x40000800
|
|
|
|
08000430 <HAL_TIM_Base_MspInit>:
|
|
|
|
void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* tim_baseHandle)
|
|
{
|
|
8000430: b480 push {r7}
|
|
8000432: b085 sub sp, #20
|
|
8000434: af00 add r7, sp, #0
|
|
8000436: 6078 str r0, [r7, #4]
|
|
|
|
if(tim_baseHandle->Instance==TIM4)
|
|
8000438: 687b ldr r3, [r7, #4]
|
|
800043a: 681b ldr r3, [r3, #0]
|
|
800043c: 4a09 ldr r2, [pc, #36] ; (8000464 <HAL_TIM_Base_MspInit+0x34>)
|
|
800043e: 4293 cmp r3, r2
|
|
8000440: d10b bne.n 800045a <HAL_TIM_Base_MspInit+0x2a>
|
|
{
|
|
/* USER CODE BEGIN TIM4_MspInit 0 */
|
|
|
|
/* USER CODE END TIM4_MspInit 0 */
|
|
/* TIM4 clock enable */
|
|
__HAL_RCC_TIM4_CLK_ENABLE();
|
|
8000442: 4b09 ldr r3, [pc, #36] ; (8000468 <HAL_TIM_Base_MspInit+0x38>)
|
|
8000444: 69db ldr r3, [r3, #28]
|
|
8000446: 4a08 ldr r2, [pc, #32] ; (8000468 <HAL_TIM_Base_MspInit+0x38>)
|
|
8000448: f043 0304 orr.w r3, r3, #4
|
|
800044c: 61d3 str r3, [r2, #28]
|
|
800044e: 4b06 ldr r3, [pc, #24] ; (8000468 <HAL_TIM_Base_MspInit+0x38>)
|
|
8000450: 69db ldr r3, [r3, #28]
|
|
8000452: f003 0304 and.w r3, r3, #4
|
|
8000456: 60fb str r3, [r7, #12]
|
|
8000458: 68fb ldr r3, [r7, #12]
|
|
/* USER CODE BEGIN TIM4_MspInit 1 */
|
|
|
|
/* USER CODE END TIM4_MspInit 1 */
|
|
}
|
|
}
|
|
800045a: bf00 nop
|
|
800045c: 3714 adds r7, #20
|
|
800045e: 46bd mov sp, r7
|
|
8000460: bc80 pop {r7}
|
|
8000462: 4770 bx lr
|
|
8000464: 40000800 .word 0x40000800
|
|
8000468: 40021000 .word 0x40021000
|
|
|
|
0800046c <HAL_TIM_MspPostInit>:
|
|
void HAL_TIM_MspPostInit(TIM_HandleTypeDef* timHandle)
|
|
{
|
|
800046c: b580 push {r7, lr}
|
|
800046e: b088 sub sp, #32
|
|
8000470: af00 add r7, sp, #0
|
|
8000472: 6078 str r0, [r7, #4]
|
|
|
|
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
|
8000474: f107 0310 add.w r3, r7, #16
|
|
8000478: 2200 movs r2, #0
|
|
800047a: 601a str r2, [r3, #0]
|
|
800047c: 605a str r2, [r3, #4]
|
|
800047e: 609a str r2, [r3, #8]
|
|
8000480: 60da str r2, [r3, #12]
|
|
if(timHandle->Instance==TIM4)
|
|
8000482: 687b ldr r3, [r7, #4]
|
|
8000484: 681b ldr r3, [r3, #0]
|
|
8000486: 4a10 ldr r2, [pc, #64] ; (80004c8 <HAL_TIM_MspPostInit+0x5c>)
|
|
8000488: 4293 cmp r3, r2
|
|
800048a: d118 bne.n 80004be <HAL_TIM_MspPostInit+0x52>
|
|
{
|
|
/* USER CODE BEGIN TIM4_MspPostInit 0 */
|
|
|
|
/* USER CODE END TIM4_MspPostInit 0 */
|
|
|
|
__HAL_RCC_GPIOB_CLK_ENABLE();
|
|
800048c: 4b0f ldr r3, [pc, #60] ; (80004cc <HAL_TIM_MspPostInit+0x60>)
|
|
800048e: 699b ldr r3, [r3, #24]
|
|
8000490: 4a0e ldr r2, [pc, #56] ; (80004cc <HAL_TIM_MspPostInit+0x60>)
|
|
8000492: f043 0308 orr.w r3, r3, #8
|
|
8000496: 6193 str r3, [r2, #24]
|
|
8000498: 4b0c ldr r3, [pc, #48] ; (80004cc <HAL_TIM_MspPostInit+0x60>)
|
|
800049a: 699b ldr r3, [r3, #24]
|
|
800049c: f003 0308 and.w r3, r3, #8
|
|
80004a0: 60fb str r3, [r7, #12]
|
|
80004a2: 68fb ldr r3, [r7, #12]
|
|
/**TIM4 GPIO Configuration
|
|
PB8 ------> TIM4_CH3
|
|
*/
|
|
GPIO_InitStruct.Pin = GPIO_PIN_8;
|
|
80004a4: f44f 7380 mov.w r3, #256 ; 0x100
|
|
80004a8: 613b str r3, [r7, #16]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
80004aa: 2302 movs r3, #2
|
|
80004ac: 617b str r3, [r7, #20]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
|
80004ae: 2302 movs r3, #2
|
|
80004b0: 61fb str r3, [r7, #28]
|
|
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
|
|
80004b2: f107 0310 add.w r3, r7, #16
|
|
80004b6: 4619 mov r1, r3
|
|
80004b8: 4805 ldr r0, [pc, #20] ; (80004d0 <HAL_TIM_MspPostInit+0x64>)
|
|
80004ba: f000 f99b bl 80007f4 <HAL_GPIO_Init>
|
|
/* USER CODE BEGIN TIM4_MspPostInit 1 */
|
|
|
|
/* USER CODE END TIM4_MspPostInit 1 */
|
|
}
|
|
|
|
}
|
|
80004be: bf00 nop
|
|
80004c0: 3720 adds r7, #32
|
|
80004c2: 46bd mov sp, r7
|
|
80004c4: bd80 pop {r7, pc}
|
|
80004c6: bf00 nop
|
|
80004c8: 40000800 .word 0x40000800
|
|
80004cc: 40021000 .word 0x40021000
|
|
80004d0: 40010c00 .word 0x40010c00
|
|
|
|
080004d4 <Reset_Handler>:
|
|
.weak Reset_Handler
|
|
.type Reset_Handler, %function
|
|
Reset_Handler:
|
|
|
|
/* Copy the data segment initializers from flash to SRAM */
|
|
ldr r0, =_sdata
|
|
80004d4: 480c ldr r0, [pc, #48] ; (8000508 <LoopFillZerobss+0x12>)
|
|
ldr r1, =_edata
|
|
80004d6: 490d ldr r1, [pc, #52] ; (800050c <LoopFillZerobss+0x16>)
|
|
ldr r2, =_sidata
|
|
80004d8: 4a0d ldr r2, [pc, #52] ; (8000510 <LoopFillZerobss+0x1a>)
|
|
movs r3, #0
|
|
80004da: 2300 movs r3, #0
|
|
b LoopCopyDataInit
|
|
80004dc: e002 b.n 80004e4 <LoopCopyDataInit>
|
|
|
|
080004de <CopyDataInit>:
|
|
|
|
CopyDataInit:
|
|
ldr r4, [r2, r3]
|
|
80004de: 58d4 ldr r4, [r2, r3]
|
|
str r4, [r0, r3]
|
|
80004e0: 50c4 str r4, [r0, r3]
|
|
adds r3, r3, #4
|
|
80004e2: 3304 adds r3, #4
|
|
|
|
080004e4 <LoopCopyDataInit>:
|
|
|
|
LoopCopyDataInit:
|
|
adds r4, r0, r3
|
|
80004e4: 18c4 adds r4, r0, r3
|
|
cmp r4, r1
|
|
80004e6: 428c cmp r4, r1
|
|
bcc CopyDataInit
|
|
80004e8: d3f9 bcc.n 80004de <CopyDataInit>
|
|
|
|
/* Zero fill the bss segment. */
|
|
ldr r2, =_sbss
|
|
80004ea: 4a0a ldr r2, [pc, #40] ; (8000514 <LoopFillZerobss+0x1e>)
|
|
ldr r4, =_ebss
|
|
80004ec: 4c0a ldr r4, [pc, #40] ; (8000518 <LoopFillZerobss+0x22>)
|
|
movs r3, #0
|
|
80004ee: 2300 movs r3, #0
|
|
b LoopFillZerobss
|
|
80004f0: e001 b.n 80004f6 <LoopFillZerobss>
|
|
|
|
080004f2 <FillZerobss>:
|
|
|
|
FillZerobss:
|
|
str r3, [r2]
|
|
80004f2: 6013 str r3, [r2, #0]
|
|
adds r2, r2, #4
|
|
80004f4: 3204 adds r2, #4
|
|
|
|
080004f6 <LoopFillZerobss>:
|
|
|
|
LoopFillZerobss:
|
|
cmp r2, r4
|
|
80004f6: 42a2 cmp r2, r4
|
|
bcc FillZerobss
|
|
80004f8: d3fb bcc.n 80004f2 <FillZerobss>
|
|
|
|
/* Call the clock system intitialization function.*/
|
|
bl SystemInit
|
|
80004fa: f7ff ff1a bl 8000332 <SystemInit>
|
|
/* Call static constructors */
|
|
bl __libc_init_array
|
|
80004fe: f001 fcb3 bl 8001e68 <__libc_init_array>
|
|
/* Call the application's entry point.*/
|
|
bl main
|
|
8000502: f7ff fe45 bl 8000190 <main>
|
|
bx lr
|
|
8000506: 4770 bx lr
|
|
ldr r0, =_sdata
|
|
8000508: 20000000 .word 0x20000000
|
|
ldr r1, =_edata
|
|
800050c: 2000000c .word 0x2000000c
|
|
ldr r2, =_sidata
|
|
8000510: 08001f00 .word 0x08001f00
|
|
ldr r2, =_sbss
|
|
8000514: 2000000c .word 0x2000000c
|
|
ldr r4, =_ebss
|
|
8000518: 20000074 .word 0x20000074
|
|
|
|
0800051c <ADC1_2_IRQHandler>:
|
|
* @retval : None
|
|
*/
|
|
.section .text.Default_Handler,"ax",%progbits
|
|
Default_Handler:
|
|
Infinite_Loop:
|
|
b Infinite_Loop
|
|
800051c: e7fe b.n 800051c <ADC1_2_IRQHandler>
|
|
...
|
|
|
|
08000520 <HAL_Init>:
|
|
* need to ensure that the SysTick time base is always set to 1 millisecond
|
|
* to have correct HAL operation.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_Init(void)
|
|
{
|
|
8000520: b580 push {r7, lr}
|
|
8000522: af00 add r7, sp, #0
|
|
defined(STM32F102x6) || defined(STM32F102xB) || \
|
|
defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || \
|
|
defined(STM32F105xC) || defined(STM32F107xC)
|
|
|
|
/* Prefetch buffer is not available on value line devices */
|
|
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
|
|
8000524: 4b08 ldr r3, [pc, #32] ; (8000548 <HAL_Init+0x28>)
|
|
8000526: 681b ldr r3, [r3, #0]
|
|
8000528: 4a07 ldr r2, [pc, #28] ; (8000548 <HAL_Init+0x28>)
|
|
800052a: f043 0310 orr.w r3, r3, #16
|
|
800052e: 6013 str r3, [r2, #0]
|
|
#endif
|
|
#endif /* PREFETCH_ENABLE */
|
|
|
|
/* Set Interrupt Group Priority */
|
|
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
|
|
8000530: 2003 movs r0, #3
|
|
8000532: f000 f92b bl 800078c <HAL_NVIC_SetPriorityGrouping>
|
|
|
|
/* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
|
|
HAL_InitTick(TICK_INT_PRIORITY);
|
|
8000536: 200f movs r0, #15
|
|
8000538: f000 f808 bl 800054c <HAL_InitTick>
|
|
|
|
/* Init the low level hardware */
|
|
HAL_MspInit();
|
|
800053c: f7ff feb0 bl 80002a0 <HAL_MspInit>
|
|
|
|
/* Return function status */
|
|
return HAL_OK;
|
|
8000540: 2300 movs r3, #0
|
|
}
|
|
8000542: 4618 mov r0, r3
|
|
8000544: bd80 pop {r7, pc}
|
|
8000546: bf00 nop
|
|
8000548: 40022000 .word 0x40022000
|
|
|
|
0800054c <HAL_InitTick>:
|
|
* implementation in user file.
|
|
* @param TickPriority Tick interrupt priority.
|
|
* @retval HAL status
|
|
*/
|
|
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
|
|
{
|
|
800054c: b580 push {r7, lr}
|
|
800054e: b082 sub sp, #8
|
|
8000550: af00 add r7, sp, #0
|
|
8000552: 6078 str r0, [r7, #4]
|
|
/* Configure the SysTick to have interrupt in 1ms time basis*/
|
|
if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U)
|
|
8000554: 4b12 ldr r3, [pc, #72] ; (80005a0 <HAL_InitTick+0x54>)
|
|
8000556: 681a ldr r2, [r3, #0]
|
|
8000558: 4b12 ldr r3, [pc, #72] ; (80005a4 <HAL_InitTick+0x58>)
|
|
800055a: 781b ldrb r3, [r3, #0]
|
|
800055c: 4619 mov r1, r3
|
|
800055e: f44f 737a mov.w r3, #1000 ; 0x3e8
|
|
8000562: fbb3 f3f1 udiv r3, r3, r1
|
|
8000566: fbb2 f3f3 udiv r3, r2, r3
|
|
800056a: 4618 mov r0, r3
|
|
800056c: f000 f935 bl 80007da <HAL_SYSTICK_Config>
|
|
8000570: 4603 mov r3, r0
|
|
8000572: 2b00 cmp r3, #0
|
|
8000574: d001 beq.n 800057a <HAL_InitTick+0x2e>
|
|
{
|
|
return HAL_ERROR;
|
|
8000576: 2301 movs r3, #1
|
|
8000578: e00e b.n 8000598 <HAL_InitTick+0x4c>
|
|
}
|
|
|
|
/* Configure the SysTick IRQ priority */
|
|
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
|
|
800057a: 687b ldr r3, [r7, #4]
|
|
800057c: 2b0f cmp r3, #15
|
|
800057e: d80a bhi.n 8000596 <HAL_InitTick+0x4a>
|
|
{
|
|
HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
|
|
8000580: 2200 movs r2, #0
|
|
8000582: 6879 ldr r1, [r7, #4]
|
|
8000584: f04f 30ff mov.w r0, #4294967295
|
|
8000588: f000 f90b bl 80007a2 <HAL_NVIC_SetPriority>
|
|
uwTickPrio = TickPriority;
|
|
800058c: 4a06 ldr r2, [pc, #24] ; (80005a8 <HAL_InitTick+0x5c>)
|
|
800058e: 687b ldr r3, [r7, #4]
|
|
8000590: 6013 str r3, [r2, #0]
|
|
{
|
|
return HAL_ERROR;
|
|
}
|
|
|
|
/* Return function status */
|
|
return HAL_OK;
|
|
8000592: 2300 movs r3, #0
|
|
8000594: e000 b.n 8000598 <HAL_InitTick+0x4c>
|
|
return HAL_ERROR;
|
|
8000596: 2301 movs r3, #1
|
|
}
|
|
8000598: 4618 mov r0, r3
|
|
800059a: 3708 adds r7, #8
|
|
800059c: 46bd mov sp, r7
|
|
800059e: bd80 pop {r7, pc}
|
|
80005a0: 20000000 .word 0x20000000
|
|
80005a4: 20000008 .word 0x20000008
|
|
80005a8: 20000004 .word 0x20000004
|
|
|
|
080005ac <HAL_IncTick>:
|
|
* @note This function is declared as __weak to be overwritten in case of other
|
|
* implementations in user file.
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_IncTick(void)
|
|
{
|
|
80005ac: b480 push {r7}
|
|
80005ae: af00 add r7, sp, #0
|
|
uwTick += uwTickFreq;
|
|
80005b0: 4b05 ldr r3, [pc, #20] ; (80005c8 <HAL_IncTick+0x1c>)
|
|
80005b2: 781b ldrb r3, [r3, #0]
|
|
80005b4: 461a mov r2, r3
|
|
80005b6: 4b05 ldr r3, [pc, #20] ; (80005cc <HAL_IncTick+0x20>)
|
|
80005b8: 681b ldr r3, [r3, #0]
|
|
80005ba: 4413 add r3, r2
|
|
80005bc: 4a03 ldr r2, [pc, #12] ; (80005cc <HAL_IncTick+0x20>)
|
|
80005be: 6013 str r3, [r2, #0]
|
|
}
|
|
80005c0: bf00 nop
|
|
80005c2: 46bd mov sp, r7
|
|
80005c4: bc80 pop {r7}
|
|
80005c6: 4770 bx lr
|
|
80005c8: 20000008 .word 0x20000008
|
|
80005cc: 20000070 .word 0x20000070
|
|
|
|
080005d0 <HAL_GetTick>:
|
|
* @note This function is declared as __weak to be overwritten in case of other
|
|
* implementations in user file.
|
|
* @retval tick value
|
|
*/
|
|
__weak uint32_t HAL_GetTick(void)
|
|
{
|
|
80005d0: b480 push {r7}
|
|
80005d2: af00 add r7, sp, #0
|
|
return uwTick;
|
|
80005d4: 4b02 ldr r3, [pc, #8] ; (80005e0 <HAL_GetTick+0x10>)
|
|
80005d6: 681b ldr r3, [r3, #0]
|
|
}
|
|
80005d8: 4618 mov r0, r3
|
|
80005da: 46bd mov sp, r7
|
|
80005dc: bc80 pop {r7}
|
|
80005de: 4770 bx lr
|
|
80005e0: 20000070 .word 0x20000070
|
|
|
|
080005e4 <HAL_Delay>:
|
|
* implementations in user file.
|
|
* @param Delay specifies the delay time length, in milliseconds.
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_Delay(uint32_t Delay)
|
|
{
|
|
80005e4: b580 push {r7, lr}
|
|
80005e6: b084 sub sp, #16
|
|
80005e8: af00 add r7, sp, #0
|
|
80005ea: 6078 str r0, [r7, #4]
|
|
uint32_t tickstart = HAL_GetTick();
|
|
80005ec: f7ff fff0 bl 80005d0 <HAL_GetTick>
|
|
80005f0: 60b8 str r0, [r7, #8]
|
|
uint32_t wait = Delay;
|
|
80005f2: 687b ldr r3, [r7, #4]
|
|
80005f4: 60fb str r3, [r7, #12]
|
|
|
|
/* Add a freq to guarantee minimum wait */
|
|
if (wait < HAL_MAX_DELAY)
|
|
80005f6: 68fb ldr r3, [r7, #12]
|
|
80005f8: f1b3 3fff cmp.w r3, #4294967295
|
|
80005fc: d005 beq.n 800060a <HAL_Delay+0x26>
|
|
{
|
|
wait += (uint32_t)(uwTickFreq);
|
|
80005fe: 4b0a ldr r3, [pc, #40] ; (8000628 <HAL_Delay+0x44>)
|
|
8000600: 781b ldrb r3, [r3, #0]
|
|
8000602: 461a mov r2, r3
|
|
8000604: 68fb ldr r3, [r7, #12]
|
|
8000606: 4413 add r3, r2
|
|
8000608: 60fb str r3, [r7, #12]
|
|
}
|
|
|
|
while ((HAL_GetTick() - tickstart) < wait)
|
|
800060a: bf00 nop
|
|
800060c: f7ff ffe0 bl 80005d0 <HAL_GetTick>
|
|
8000610: 4602 mov r2, r0
|
|
8000612: 68bb ldr r3, [r7, #8]
|
|
8000614: 1ad3 subs r3, r2, r3
|
|
8000616: 68fa ldr r2, [r7, #12]
|
|
8000618: 429a cmp r2, r3
|
|
800061a: d8f7 bhi.n 800060c <HAL_Delay+0x28>
|
|
{
|
|
}
|
|
}
|
|
800061c: bf00 nop
|
|
800061e: bf00 nop
|
|
8000620: 3710 adds r7, #16
|
|
8000622: 46bd mov sp, r7
|
|
8000624: bd80 pop {r7, pc}
|
|
8000626: bf00 nop
|
|
8000628: 20000008 .word 0x20000008
|
|
|
|
0800062c <__NVIC_SetPriorityGrouping>:
|
|
In case of a conflict between priority grouping and available
|
|
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
|
|
\param [in] PriorityGroup Priority grouping field.
|
|
*/
|
|
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
|
|
{
|
|
800062c: b480 push {r7}
|
|
800062e: b085 sub sp, #20
|
|
8000630: af00 add r7, sp, #0
|
|
8000632: 6078 str r0, [r7, #4]
|
|
uint32_t reg_value;
|
|
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
|
|
8000634: 687b ldr r3, [r7, #4]
|
|
8000636: f003 0307 and.w r3, r3, #7
|
|
800063a: 60fb str r3, [r7, #12]
|
|
|
|
reg_value = SCB->AIRCR; /* read old register configuration */
|
|
800063c: 4b0c ldr r3, [pc, #48] ; (8000670 <__NVIC_SetPriorityGrouping+0x44>)
|
|
800063e: 68db ldr r3, [r3, #12]
|
|
8000640: 60bb str r3, [r7, #8]
|
|
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
|
|
8000642: 68ba ldr r2, [r7, #8]
|
|
8000644: f64f 03ff movw r3, #63743 ; 0xf8ff
|
|
8000648: 4013 ands r3, r2
|
|
800064a: 60bb str r3, [r7, #8]
|
|
reg_value = (reg_value |
|
|
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
|
|
(PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
|
|
800064c: 68fb ldr r3, [r7, #12]
|
|
800064e: 021a lsls r2, r3, #8
|
|
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
|
|
8000650: 68bb ldr r3, [r7, #8]
|
|
8000652: 4313 orrs r3, r2
|
|
reg_value = (reg_value |
|
|
8000654: f043 63bf orr.w r3, r3, #100139008 ; 0x5f80000
|
|
8000658: f443 3300 orr.w r3, r3, #131072 ; 0x20000
|
|
800065c: 60bb str r3, [r7, #8]
|
|
SCB->AIRCR = reg_value;
|
|
800065e: 4a04 ldr r2, [pc, #16] ; (8000670 <__NVIC_SetPriorityGrouping+0x44>)
|
|
8000660: 68bb ldr r3, [r7, #8]
|
|
8000662: 60d3 str r3, [r2, #12]
|
|
}
|
|
8000664: bf00 nop
|
|
8000666: 3714 adds r7, #20
|
|
8000668: 46bd mov sp, r7
|
|
800066a: bc80 pop {r7}
|
|
800066c: 4770 bx lr
|
|
800066e: bf00 nop
|
|
8000670: e000ed00 .word 0xe000ed00
|
|
|
|
08000674 <__NVIC_GetPriorityGrouping>:
|
|
\brief Get Priority Grouping
|
|
\details Reads the priority grouping field from the NVIC Interrupt Controller.
|
|
\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
|
|
*/
|
|
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
|
|
{
|
|
8000674: b480 push {r7}
|
|
8000676: af00 add r7, sp, #0
|
|
return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
|
|
8000678: 4b04 ldr r3, [pc, #16] ; (800068c <__NVIC_GetPriorityGrouping+0x18>)
|
|
800067a: 68db ldr r3, [r3, #12]
|
|
800067c: 0a1b lsrs r3, r3, #8
|
|
800067e: f003 0307 and.w r3, r3, #7
|
|
}
|
|
8000682: 4618 mov r0, r3
|
|
8000684: 46bd mov sp, r7
|
|
8000686: bc80 pop {r7}
|
|
8000688: 4770 bx lr
|
|
800068a: bf00 nop
|
|
800068c: e000ed00 .word 0xe000ed00
|
|
|
|
08000690 <__NVIC_SetPriority>:
|
|
\param [in] IRQn Interrupt number.
|
|
\param [in] priority Priority to set.
|
|
\note The priority cannot be set for every processor exception.
|
|
*/
|
|
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
|
|
{
|
|
8000690: b480 push {r7}
|
|
8000692: b083 sub sp, #12
|
|
8000694: af00 add r7, sp, #0
|
|
8000696: 4603 mov r3, r0
|
|
8000698: 6039 str r1, [r7, #0]
|
|
800069a: 71fb strb r3, [r7, #7]
|
|
if ((int32_t)(IRQn) >= 0)
|
|
800069c: f997 3007 ldrsb.w r3, [r7, #7]
|
|
80006a0: 2b00 cmp r3, #0
|
|
80006a2: db0a blt.n 80006ba <__NVIC_SetPriority+0x2a>
|
|
{
|
|
NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
|
|
80006a4: 683b ldr r3, [r7, #0]
|
|
80006a6: b2da uxtb r2, r3
|
|
80006a8: 490c ldr r1, [pc, #48] ; (80006dc <__NVIC_SetPriority+0x4c>)
|
|
80006aa: f997 3007 ldrsb.w r3, [r7, #7]
|
|
80006ae: 0112 lsls r2, r2, #4
|
|
80006b0: b2d2 uxtb r2, r2
|
|
80006b2: 440b add r3, r1
|
|
80006b4: f883 2300 strb.w r2, [r3, #768] ; 0x300
|
|
}
|
|
else
|
|
{
|
|
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
|
|
}
|
|
}
|
|
80006b8: e00a b.n 80006d0 <__NVIC_SetPriority+0x40>
|
|
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
|
|
80006ba: 683b ldr r3, [r7, #0]
|
|
80006bc: b2da uxtb r2, r3
|
|
80006be: 4908 ldr r1, [pc, #32] ; (80006e0 <__NVIC_SetPriority+0x50>)
|
|
80006c0: 79fb ldrb r3, [r7, #7]
|
|
80006c2: f003 030f and.w r3, r3, #15
|
|
80006c6: 3b04 subs r3, #4
|
|
80006c8: 0112 lsls r2, r2, #4
|
|
80006ca: b2d2 uxtb r2, r2
|
|
80006cc: 440b add r3, r1
|
|
80006ce: 761a strb r2, [r3, #24]
|
|
}
|
|
80006d0: bf00 nop
|
|
80006d2: 370c adds r7, #12
|
|
80006d4: 46bd mov sp, r7
|
|
80006d6: bc80 pop {r7}
|
|
80006d8: 4770 bx lr
|
|
80006da: bf00 nop
|
|
80006dc: e000e100 .word 0xe000e100
|
|
80006e0: e000ed00 .word 0xe000ed00
|
|
|
|
080006e4 <NVIC_EncodePriority>:
|
|
\param [in] PreemptPriority Preemptive priority value (starting from 0).
|
|
\param [in] SubPriority Subpriority value (starting from 0).
|
|
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
|
|
*/
|
|
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
|
|
{
|
|
80006e4: b480 push {r7}
|
|
80006e6: b089 sub sp, #36 ; 0x24
|
|
80006e8: af00 add r7, sp, #0
|
|
80006ea: 60f8 str r0, [r7, #12]
|
|
80006ec: 60b9 str r1, [r7, #8]
|
|
80006ee: 607a str r2, [r7, #4]
|
|
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
|
|
80006f0: 68fb ldr r3, [r7, #12]
|
|
80006f2: f003 0307 and.w r3, r3, #7
|
|
80006f6: 61fb str r3, [r7, #28]
|
|
uint32_t PreemptPriorityBits;
|
|
uint32_t SubPriorityBits;
|
|
|
|
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
|
|
80006f8: 69fb ldr r3, [r7, #28]
|
|
80006fa: f1c3 0307 rsb r3, r3, #7
|
|
80006fe: 2b04 cmp r3, #4
|
|
8000700: bf28 it cs
|
|
8000702: 2304 movcs r3, #4
|
|
8000704: 61bb str r3, [r7, #24]
|
|
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
|
|
8000706: 69fb ldr r3, [r7, #28]
|
|
8000708: 3304 adds r3, #4
|
|
800070a: 2b06 cmp r3, #6
|
|
800070c: d902 bls.n 8000714 <NVIC_EncodePriority+0x30>
|
|
800070e: 69fb ldr r3, [r7, #28]
|
|
8000710: 3b03 subs r3, #3
|
|
8000712: e000 b.n 8000716 <NVIC_EncodePriority+0x32>
|
|
8000714: 2300 movs r3, #0
|
|
8000716: 617b str r3, [r7, #20]
|
|
|
|
return (
|
|
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
|
|
8000718: f04f 32ff mov.w r2, #4294967295
|
|
800071c: 69bb ldr r3, [r7, #24]
|
|
800071e: fa02 f303 lsl.w r3, r2, r3
|
|
8000722: 43da mvns r2, r3
|
|
8000724: 68bb ldr r3, [r7, #8]
|
|
8000726: 401a ands r2, r3
|
|
8000728: 697b ldr r3, [r7, #20]
|
|
800072a: 409a lsls r2, r3
|
|
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
|
|
800072c: f04f 31ff mov.w r1, #4294967295
|
|
8000730: 697b ldr r3, [r7, #20]
|
|
8000732: fa01 f303 lsl.w r3, r1, r3
|
|
8000736: 43d9 mvns r1, r3
|
|
8000738: 687b ldr r3, [r7, #4]
|
|
800073a: 400b ands r3, r1
|
|
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
|
|
800073c: 4313 orrs r3, r2
|
|
);
|
|
}
|
|
800073e: 4618 mov r0, r3
|
|
8000740: 3724 adds r7, #36 ; 0x24
|
|
8000742: 46bd mov sp, r7
|
|
8000744: bc80 pop {r7}
|
|
8000746: 4770 bx lr
|
|
|
|
08000748 <SysTick_Config>:
|
|
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
|
|
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
|
|
must contain a vendor-specific implementation of this function.
|
|
*/
|
|
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
|
|
{
|
|
8000748: b580 push {r7, lr}
|
|
800074a: b082 sub sp, #8
|
|
800074c: af00 add r7, sp, #0
|
|
800074e: 6078 str r0, [r7, #4]
|
|
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
|
|
8000750: 687b ldr r3, [r7, #4]
|
|
8000752: 3b01 subs r3, #1
|
|
8000754: f1b3 7f80 cmp.w r3, #16777216 ; 0x1000000
|
|
8000758: d301 bcc.n 800075e <SysTick_Config+0x16>
|
|
{
|
|
return (1UL); /* Reload value impossible */
|
|
800075a: 2301 movs r3, #1
|
|
800075c: e00f b.n 800077e <SysTick_Config+0x36>
|
|
}
|
|
|
|
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
|
|
800075e: 4a0a ldr r2, [pc, #40] ; (8000788 <SysTick_Config+0x40>)
|
|
8000760: 687b ldr r3, [r7, #4]
|
|
8000762: 3b01 subs r3, #1
|
|
8000764: 6053 str r3, [r2, #4]
|
|
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
|
|
8000766: 210f movs r1, #15
|
|
8000768: f04f 30ff mov.w r0, #4294967295
|
|
800076c: f7ff ff90 bl 8000690 <__NVIC_SetPriority>
|
|
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
|
|
8000770: 4b05 ldr r3, [pc, #20] ; (8000788 <SysTick_Config+0x40>)
|
|
8000772: 2200 movs r2, #0
|
|
8000774: 609a str r2, [r3, #8]
|
|
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
|
|
8000776: 4b04 ldr r3, [pc, #16] ; (8000788 <SysTick_Config+0x40>)
|
|
8000778: 2207 movs r2, #7
|
|
800077a: 601a str r2, [r3, #0]
|
|
SysTick_CTRL_TICKINT_Msk |
|
|
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
|
|
return (0UL); /* Function successful */
|
|
800077c: 2300 movs r3, #0
|
|
}
|
|
800077e: 4618 mov r0, r3
|
|
8000780: 3708 adds r7, #8
|
|
8000782: 46bd mov sp, r7
|
|
8000784: bd80 pop {r7, pc}
|
|
8000786: bf00 nop
|
|
8000788: e000e010 .word 0xe000e010
|
|
|
|
0800078c <HAL_NVIC_SetPriorityGrouping>:
|
|
* @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible.
|
|
* The pending IRQ priority will be managed only by the subpriority.
|
|
* @retval None
|
|
*/
|
|
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
|
|
{
|
|
800078c: b580 push {r7, lr}
|
|
800078e: b082 sub sp, #8
|
|
8000790: af00 add r7, sp, #0
|
|
8000792: 6078 str r0, [r7, #4]
|
|
/* Check the parameters */
|
|
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
|
|
|
|
/* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
|
|
NVIC_SetPriorityGrouping(PriorityGroup);
|
|
8000794: 6878 ldr r0, [r7, #4]
|
|
8000796: f7ff ff49 bl 800062c <__NVIC_SetPriorityGrouping>
|
|
}
|
|
800079a: bf00 nop
|
|
800079c: 3708 adds r7, #8
|
|
800079e: 46bd mov sp, r7
|
|
80007a0: bd80 pop {r7, pc}
|
|
|
|
080007a2 <HAL_NVIC_SetPriority>:
|
|
* This parameter can be a value between 0 and 15
|
|
* A lower priority value indicates a higher priority.
|
|
* @retval None
|
|
*/
|
|
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
|
|
{
|
|
80007a2: b580 push {r7, lr}
|
|
80007a4: b086 sub sp, #24
|
|
80007a6: af00 add r7, sp, #0
|
|
80007a8: 4603 mov r3, r0
|
|
80007aa: 60b9 str r1, [r7, #8]
|
|
80007ac: 607a str r2, [r7, #4]
|
|
80007ae: 73fb strb r3, [r7, #15]
|
|
uint32_t prioritygroup = 0x00U;
|
|
80007b0: 2300 movs r3, #0
|
|
80007b2: 617b str r3, [r7, #20]
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
|
|
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
|
|
|
|
prioritygroup = NVIC_GetPriorityGrouping();
|
|
80007b4: f7ff ff5e bl 8000674 <__NVIC_GetPriorityGrouping>
|
|
80007b8: 6178 str r0, [r7, #20]
|
|
|
|
NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
|
|
80007ba: 687a ldr r2, [r7, #4]
|
|
80007bc: 68b9 ldr r1, [r7, #8]
|
|
80007be: 6978 ldr r0, [r7, #20]
|
|
80007c0: f7ff ff90 bl 80006e4 <NVIC_EncodePriority>
|
|
80007c4: 4602 mov r2, r0
|
|
80007c6: f997 300f ldrsb.w r3, [r7, #15]
|
|
80007ca: 4611 mov r1, r2
|
|
80007cc: 4618 mov r0, r3
|
|
80007ce: f7ff ff5f bl 8000690 <__NVIC_SetPriority>
|
|
}
|
|
80007d2: bf00 nop
|
|
80007d4: 3718 adds r7, #24
|
|
80007d6: 46bd mov sp, r7
|
|
80007d8: bd80 pop {r7, pc}
|
|
|
|
080007da <HAL_SYSTICK_Config>:
|
|
* @param TicksNumb: Specifies the ticks Number of ticks between two interrupts.
|
|
* @retval status: - 0 Function succeeded.
|
|
* - 1 Function failed.
|
|
*/
|
|
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
|
|
{
|
|
80007da: b580 push {r7, lr}
|
|
80007dc: b082 sub sp, #8
|
|
80007de: af00 add r7, sp, #0
|
|
80007e0: 6078 str r0, [r7, #4]
|
|
return SysTick_Config(TicksNumb);
|
|
80007e2: 6878 ldr r0, [r7, #4]
|
|
80007e4: f7ff ffb0 bl 8000748 <SysTick_Config>
|
|
80007e8: 4603 mov r3, r0
|
|
}
|
|
80007ea: 4618 mov r0, r3
|
|
80007ec: 3708 adds r7, #8
|
|
80007ee: 46bd mov sp, r7
|
|
80007f0: bd80 pop {r7, pc}
|
|
...
|
|
|
|
080007f4 <HAL_GPIO_Init>:
|
|
* @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains
|
|
* the configuration information for the specified GPIO peripheral.
|
|
* @retval None
|
|
*/
|
|
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
|
|
{
|
|
80007f4: b480 push {r7}
|
|
80007f6: b08b sub sp, #44 ; 0x2c
|
|
80007f8: af00 add r7, sp, #0
|
|
80007fa: 6078 str r0, [r7, #4]
|
|
80007fc: 6039 str r1, [r7, #0]
|
|
uint32_t position = 0x00u;
|
|
80007fe: 2300 movs r3, #0
|
|
8000800: 627b str r3, [r7, #36] ; 0x24
|
|
uint32_t ioposition;
|
|
uint32_t iocurrent;
|
|
uint32_t temp;
|
|
uint32_t config = 0x00u;
|
|
8000802: 2300 movs r3, #0
|
|
8000804: 623b str r3, [r7, #32]
|
|
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
|
|
assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
|
|
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
|
|
|
|
/* Configure the port pins */
|
|
while (((GPIO_Init->Pin) >> position) != 0x00u)
|
|
8000806: e169 b.n 8000adc <HAL_GPIO_Init+0x2e8>
|
|
{
|
|
/* Get the IO position */
|
|
ioposition = (0x01uL << position);
|
|
8000808: 2201 movs r2, #1
|
|
800080a: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
800080c: fa02 f303 lsl.w r3, r2, r3
|
|
8000810: 61fb str r3, [r7, #28]
|
|
|
|
/* Get the current IO position */
|
|
iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition;
|
|
8000812: 683b ldr r3, [r7, #0]
|
|
8000814: 681b ldr r3, [r3, #0]
|
|
8000816: 69fa ldr r2, [r7, #28]
|
|
8000818: 4013 ands r3, r2
|
|
800081a: 61bb str r3, [r7, #24]
|
|
|
|
if (iocurrent == ioposition)
|
|
800081c: 69ba ldr r2, [r7, #24]
|
|
800081e: 69fb ldr r3, [r7, #28]
|
|
8000820: 429a cmp r2, r3
|
|
8000822: f040 8158 bne.w 8000ad6 <HAL_GPIO_Init+0x2e2>
|
|
{
|
|
/* Check the Alternate function parameters */
|
|
assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
|
|
|
|
/* Based on the required mode, filling config variable with MODEy[1:0] and CNFy[3:2] corresponding bits */
|
|
switch (GPIO_Init->Mode)
|
|
8000826: 683b ldr r3, [r7, #0]
|
|
8000828: 685b ldr r3, [r3, #4]
|
|
800082a: 4a9a ldr r2, [pc, #616] ; (8000a94 <HAL_GPIO_Init+0x2a0>)
|
|
800082c: 4293 cmp r3, r2
|
|
800082e: d05e beq.n 80008ee <HAL_GPIO_Init+0xfa>
|
|
8000830: 4a98 ldr r2, [pc, #608] ; (8000a94 <HAL_GPIO_Init+0x2a0>)
|
|
8000832: 4293 cmp r3, r2
|
|
8000834: d875 bhi.n 8000922 <HAL_GPIO_Init+0x12e>
|
|
8000836: 4a98 ldr r2, [pc, #608] ; (8000a98 <HAL_GPIO_Init+0x2a4>)
|
|
8000838: 4293 cmp r3, r2
|
|
800083a: d058 beq.n 80008ee <HAL_GPIO_Init+0xfa>
|
|
800083c: 4a96 ldr r2, [pc, #600] ; (8000a98 <HAL_GPIO_Init+0x2a4>)
|
|
800083e: 4293 cmp r3, r2
|
|
8000840: d86f bhi.n 8000922 <HAL_GPIO_Init+0x12e>
|
|
8000842: 4a96 ldr r2, [pc, #600] ; (8000a9c <HAL_GPIO_Init+0x2a8>)
|
|
8000844: 4293 cmp r3, r2
|
|
8000846: d052 beq.n 80008ee <HAL_GPIO_Init+0xfa>
|
|
8000848: 4a94 ldr r2, [pc, #592] ; (8000a9c <HAL_GPIO_Init+0x2a8>)
|
|
800084a: 4293 cmp r3, r2
|
|
800084c: d869 bhi.n 8000922 <HAL_GPIO_Init+0x12e>
|
|
800084e: 4a94 ldr r2, [pc, #592] ; (8000aa0 <HAL_GPIO_Init+0x2ac>)
|
|
8000850: 4293 cmp r3, r2
|
|
8000852: d04c beq.n 80008ee <HAL_GPIO_Init+0xfa>
|
|
8000854: 4a92 ldr r2, [pc, #584] ; (8000aa0 <HAL_GPIO_Init+0x2ac>)
|
|
8000856: 4293 cmp r3, r2
|
|
8000858: d863 bhi.n 8000922 <HAL_GPIO_Init+0x12e>
|
|
800085a: 4a92 ldr r2, [pc, #584] ; (8000aa4 <HAL_GPIO_Init+0x2b0>)
|
|
800085c: 4293 cmp r3, r2
|
|
800085e: d046 beq.n 80008ee <HAL_GPIO_Init+0xfa>
|
|
8000860: 4a90 ldr r2, [pc, #576] ; (8000aa4 <HAL_GPIO_Init+0x2b0>)
|
|
8000862: 4293 cmp r3, r2
|
|
8000864: d85d bhi.n 8000922 <HAL_GPIO_Init+0x12e>
|
|
8000866: 2b12 cmp r3, #18
|
|
8000868: d82a bhi.n 80008c0 <HAL_GPIO_Init+0xcc>
|
|
800086a: 2b12 cmp r3, #18
|
|
800086c: d859 bhi.n 8000922 <HAL_GPIO_Init+0x12e>
|
|
800086e: a201 add r2, pc, #4 ; (adr r2, 8000874 <HAL_GPIO_Init+0x80>)
|
|
8000870: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
8000874: 080008ef .word 0x080008ef
|
|
8000878: 080008c9 .word 0x080008c9
|
|
800087c: 080008db .word 0x080008db
|
|
8000880: 0800091d .word 0x0800091d
|
|
8000884: 08000923 .word 0x08000923
|
|
8000888: 08000923 .word 0x08000923
|
|
800088c: 08000923 .word 0x08000923
|
|
8000890: 08000923 .word 0x08000923
|
|
8000894: 08000923 .word 0x08000923
|
|
8000898: 08000923 .word 0x08000923
|
|
800089c: 08000923 .word 0x08000923
|
|
80008a0: 08000923 .word 0x08000923
|
|
80008a4: 08000923 .word 0x08000923
|
|
80008a8: 08000923 .word 0x08000923
|
|
80008ac: 08000923 .word 0x08000923
|
|
80008b0: 08000923 .word 0x08000923
|
|
80008b4: 08000923 .word 0x08000923
|
|
80008b8: 080008d1 .word 0x080008d1
|
|
80008bc: 080008e5 .word 0x080008e5
|
|
80008c0: 4a79 ldr r2, [pc, #484] ; (8000aa8 <HAL_GPIO_Init+0x2b4>)
|
|
80008c2: 4293 cmp r3, r2
|
|
80008c4: d013 beq.n 80008ee <HAL_GPIO_Init+0xfa>
|
|
config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG;
|
|
break;
|
|
|
|
/* Parameters are checked with assert_param */
|
|
default:
|
|
break;
|
|
80008c6: e02c b.n 8000922 <HAL_GPIO_Init+0x12e>
|
|
config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_PP;
|
|
80008c8: 683b ldr r3, [r7, #0]
|
|
80008ca: 68db ldr r3, [r3, #12]
|
|
80008cc: 623b str r3, [r7, #32]
|
|
break;
|
|
80008ce: e029 b.n 8000924 <HAL_GPIO_Init+0x130>
|
|
config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_OD;
|
|
80008d0: 683b ldr r3, [r7, #0]
|
|
80008d2: 68db ldr r3, [r3, #12]
|
|
80008d4: 3304 adds r3, #4
|
|
80008d6: 623b str r3, [r7, #32]
|
|
break;
|
|
80008d8: e024 b.n 8000924 <HAL_GPIO_Init+0x130>
|
|
config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_PP;
|
|
80008da: 683b ldr r3, [r7, #0]
|
|
80008dc: 68db ldr r3, [r3, #12]
|
|
80008de: 3308 adds r3, #8
|
|
80008e0: 623b str r3, [r7, #32]
|
|
break;
|
|
80008e2: e01f b.n 8000924 <HAL_GPIO_Init+0x130>
|
|
config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_OD;
|
|
80008e4: 683b ldr r3, [r7, #0]
|
|
80008e6: 68db ldr r3, [r3, #12]
|
|
80008e8: 330c adds r3, #12
|
|
80008ea: 623b str r3, [r7, #32]
|
|
break;
|
|
80008ec: e01a b.n 8000924 <HAL_GPIO_Init+0x130>
|
|
if (GPIO_Init->Pull == GPIO_NOPULL)
|
|
80008ee: 683b ldr r3, [r7, #0]
|
|
80008f0: 689b ldr r3, [r3, #8]
|
|
80008f2: 2b00 cmp r3, #0
|
|
80008f4: d102 bne.n 80008fc <HAL_GPIO_Init+0x108>
|
|
config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_FLOATING;
|
|
80008f6: 2304 movs r3, #4
|
|
80008f8: 623b str r3, [r7, #32]
|
|
break;
|
|
80008fa: e013 b.n 8000924 <HAL_GPIO_Init+0x130>
|
|
else if (GPIO_Init->Pull == GPIO_PULLUP)
|
|
80008fc: 683b ldr r3, [r7, #0]
|
|
80008fe: 689b ldr r3, [r3, #8]
|
|
8000900: 2b01 cmp r3, #1
|
|
8000902: d105 bne.n 8000910 <HAL_GPIO_Init+0x11c>
|
|
config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD;
|
|
8000904: 2308 movs r3, #8
|
|
8000906: 623b str r3, [r7, #32]
|
|
GPIOx->BSRR = ioposition;
|
|
8000908: 687b ldr r3, [r7, #4]
|
|
800090a: 69fa ldr r2, [r7, #28]
|
|
800090c: 611a str r2, [r3, #16]
|
|
break;
|
|
800090e: e009 b.n 8000924 <HAL_GPIO_Init+0x130>
|
|
config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD;
|
|
8000910: 2308 movs r3, #8
|
|
8000912: 623b str r3, [r7, #32]
|
|
GPIOx->BRR = ioposition;
|
|
8000914: 687b ldr r3, [r7, #4]
|
|
8000916: 69fa ldr r2, [r7, #28]
|
|
8000918: 615a str r2, [r3, #20]
|
|
break;
|
|
800091a: e003 b.n 8000924 <HAL_GPIO_Init+0x130>
|
|
config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG;
|
|
800091c: 2300 movs r3, #0
|
|
800091e: 623b str r3, [r7, #32]
|
|
break;
|
|
8000920: e000 b.n 8000924 <HAL_GPIO_Init+0x130>
|
|
break;
|
|
8000922: bf00 nop
|
|
}
|
|
|
|
/* Check if the current bit belongs to first half or last half of the pin count number
|
|
in order to address CRH or CRL register*/
|
|
configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL : &GPIOx->CRH;
|
|
8000924: 69bb ldr r3, [r7, #24]
|
|
8000926: 2bff cmp r3, #255 ; 0xff
|
|
8000928: d801 bhi.n 800092e <HAL_GPIO_Init+0x13a>
|
|
800092a: 687b ldr r3, [r7, #4]
|
|
800092c: e001 b.n 8000932 <HAL_GPIO_Init+0x13e>
|
|
800092e: 687b ldr r3, [r7, #4]
|
|
8000930: 3304 adds r3, #4
|
|
8000932: 617b str r3, [r7, #20]
|
|
registeroffset = (iocurrent < GPIO_PIN_8) ? (position << 2u) : ((position - 8u) << 2u);
|
|
8000934: 69bb ldr r3, [r7, #24]
|
|
8000936: 2bff cmp r3, #255 ; 0xff
|
|
8000938: d802 bhi.n 8000940 <HAL_GPIO_Init+0x14c>
|
|
800093a: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
800093c: 009b lsls r3, r3, #2
|
|
800093e: e002 b.n 8000946 <HAL_GPIO_Init+0x152>
|
|
8000940: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
8000942: 3b08 subs r3, #8
|
|
8000944: 009b lsls r3, r3, #2
|
|
8000946: 613b str r3, [r7, #16]
|
|
|
|
/* Apply the new configuration of the pin to the register */
|
|
MODIFY_REG((*configregister), ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset), (config << registeroffset));
|
|
8000948: 697b ldr r3, [r7, #20]
|
|
800094a: 681a ldr r2, [r3, #0]
|
|
800094c: 210f movs r1, #15
|
|
800094e: 693b ldr r3, [r7, #16]
|
|
8000950: fa01 f303 lsl.w r3, r1, r3
|
|
8000954: 43db mvns r3, r3
|
|
8000956: 401a ands r2, r3
|
|
8000958: 6a39 ldr r1, [r7, #32]
|
|
800095a: 693b ldr r3, [r7, #16]
|
|
800095c: fa01 f303 lsl.w r3, r1, r3
|
|
8000960: 431a orrs r2, r3
|
|
8000962: 697b ldr r3, [r7, #20]
|
|
8000964: 601a str r2, [r3, #0]
|
|
|
|
/*--------------------- EXTI Mode Configuration ------------------------*/
|
|
/* Configure the External Interrupt or event for the current IO */
|
|
if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
|
|
8000966: 683b ldr r3, [r7, #0]
|
|
8000968: 685b ldr r3, [r3, #4]
|
|
800096a: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
|
|
800096e: 2b00 cmp r3, #0
|
|
8000970: f000 80b1 beq.w 8000ad6 <HAL_GPIO_Init+0x2e2>
|
|
{
|
|
/* Enable AFIO Clock */
|
|
__HAL_RCC_AFIO_CLK_ENABLE();
|
|
8000974: 4b4d ldr r3, [pc, #308] ; (8000aac <HAL_GPIO_Init+0x2b8>)
|
|
8000976: 699b ldr r3, [r3, #24]
|
|
8000978: 4a4c ldr r2, [pc, #304] ; (8000aac <HAL_GPIO_Init+0x2b8>)
|
|
800097a: f043 0301 orr.w r3, r3, #1
|
|
800097e: 6193 str r3, [r2, #24]
|
|
8000980: 4b4a ldr r3, [pc, #296] ; (8000aac <HAL_GPIO_Init+0x2b8>)
|
|
8000982: 699b ldr r3, [r3, #24]
|
|
8000984: f003 0301 and.w r3, r3, #1
|
|
8000988: 60bb str r3, [r7, #8]
|
|
800098a: 68bb ldr r3, [r7, #8]
|
|
temp = AFIO->EXTICR[position >> 2u];
|
|
800098c: 4a48 ldr r2, [pc, #288] ; (8000ab0 <HAL_GPIO_Init+0x2bc>)
|
|
800098e: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
8000990: 089b lsrs r3, r3, #2
|
|
8000992: 3302 adds r3, #2
|
|
8000994: f852 3023 ldr.w r3, [r2, r3, lsl #2]
|
|
8000998: 60fb str r3, [r7, #12]
|
|
CLEAR_BIT(temp, (0x0Fu) << (4u * (position & 0x03u)));
|
|
800099a: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
800099c: f003 0303 and.w r3, r3, #3
|
|
80009a0: 009b lsls r3, r3, #2
|
|
80009a2: 220f movs r2, #15
|
|
80009a4: fa02 f303 lsl.w r3, r2, r3
|
|
80009a8: 43db mvns r3, r3
|
|
80009aa: 68fa ldr r2, [r7, #12]
|
|
80009ac: 4013 ands r3, r2
|
|
80009ae: 60fb str r3, [r7, #12]
|
|
SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4u * (position & 0x03u)));
|
|
80009b0: 687b ldr r3, [r7, #4]
|
|
80009b2: 4a40 ldr r2, [pc, #256] ; (8000ab4 <HAL_GPIO_Init+0x2c0>)
|
|
80009b4: 4293 cmp r3, r2
|
|
80009b6: d013 beq.n 80009e0 <HAL_GPIO_Init+0x1ec>
|
|
80009b8: 687b ldr r3, [r7, #4]
|
|
80009ba: 4a3f ldr r2, [pc, #252] ; (8000ab8 <HAL_GPIO_Init+0x2c4>)
|
|
80009bc: 4293 cmp r3, r2
|
|
80009be: d00d beq.n 80009dc <HAL_GPIO_Init+0x1e8>
|
|
80009c0: 687b ldr r3, [r7, #4]
|
|
80009c2: 4a3e ldr r2, [pc, #248] ; (8000abc <HAL_GPIO_Init+0x2c8>)
|
|
80009c4: 4293 cmp r3, r2
|
|
80009c6: d007 beq.n 80009d8 <HAL_GPIO_Init+0x1e4>
|
|
80009c8: 687b ldr r3, [r7, #4]
|
|
80009ca: 4a3d ldr r2, [pc, #244] ; (8000ac0 <HAL_GPIO_Init+0x2cc>)
|
|
80009cc: 4293 cmp r3, r2
|
|
80009ce: d101 bne.n 80009d4 <HAL_GPIO_Init+0x1e0>
|
|
80009d0: 2303 movs r3, #3
|
|
80009d2: e006 b.n 80009e2 <HAL_GPIO_Init+0x1ee>
|
|
80009d4: 2304 movs r3, #4
|
|
80009d6: e004 b.n 80009e2 <HAL_GPIO_Init+0x1ee>
|
|
80009d8: 2302 movs r3, #2
|
|
80009da: e002 b.n 80009e2 <HAL_GPIO_Init+0x1ee>
|
|
80009dc: 2301 movs r3, #1
|
|
80009de: e000 b.n 80009e2 <HAL_GPIO_Init+0x1ee>
|
|
80009e0: 2300 movs r3, #0
|
|
80009e2: 6a7a ldr r2, [r7, #36] ; 0x24
|
|
80009e4: f002 0203 and.w r2, r2, #3
|
|
80009e8: 0092 lsls r2, r2, #2
|
|
80009ea: 4093 lsls r3, r2
|
|
80009ec: 68fa ldr r2, [r7, #12]
|
|
80009ee: 4313 orrs r3, r2
|
|
80009f0: 60fb str r3, [r7, #12]
|
|
AFIO->EXTICR[position >> 2u] = temp;
|
|
80009f2: 492f ldr r1, [pc, #188] ; (8000ab0 <HAL_GPIO_Init+0x2bc>)
|
|
80009f4: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
80009f6: 089b lsrs r3, r3, #2
|
|
80009f8: 3302 adds r3, #2
|
|
80009fa: 68fa ldr r2, [r7, #12]
|
|
80009fc: f841 2023 str.w r2, [r1, r3, lsl #2]
|
|
|
|
|
|
/* Configure the interrupt mask */
|
|
if ((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
|
|
8000a00: 683b ldr r3, [r7, #0]
|
|
8000a02: 685b ldr r3, [r3, #4]
|
|
8000a04: f403 3380 and.w r3, r3, #65536 ; 0x10000
|
|
8000a08: 2b00 cmp r3, #0
|
|
8000a0a: d006 beq.n 8000a1a <HAL_GPIO_Init+0x226>
|
|
{
|
|
SET_BIT(EXTI->IMR, iocurrent);
|
|
8000a0c: 4b2d ldr r3, [pc, #180] ; (8000ac4 <HAL_GPIO_Init+0x2d0>)
|
|
8000a0e: 681a ldr r2, [r3, #0]
|
|
8000a10: 492c ldr r1, [pc, #176] ; (8000ac4 <HAL_GPIO_Init+0x2d0>)
|
|
8000a12: 69bb ldr r3, [r7, #24]
|
|
8000a14: 4313 orrs r3, r2
|
|
8000a16: 600b str r3, [r1, #0]
|
|
8000a18: e006 b.n 8000a28 <HAL_GPIO_Init+0x234>
|
|
}
|
|
else
|
|
{
|
|
CLEAR_BIT(EXTI->IMR, iocurrent);
|
|
8000a1a: 4b2a ldr r3, [pc, #168] ; (8000ac4 <HAL_GPIO_Init+0x2d0>)
|
|
8000a1c: 681a ldr r2, [r3, #0]
|
|
8000a1e: 69bb ldr r3, [r7, #24]
|
|
8000a20: 43db mvns r3, r3
|
|
8000a22: 4928 ldr r1, [pc, #160] ; (8000ac4 <HAL_GPIO_Init+0x2d0>)
|
|
8000a24: 4013 ands r3, r2
|
|
8000a26: 600b str r3, [r1, #0]
|
|
}
|
|
|
|
/* Configure the event mask */
|
|
if ((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
|
|
8000a28: 683b ldr r3, [r7, #0]
|
|
8000a2a: 685b ldr r3, [r3, #4]
|
|
8000a2c: f403 3300 and.w r3, r3, #131072 ; 0x20000
|
|
8000a30: 2b00 cmp r3, #0
|
|
8000a32: d006 beq.n 8000a42 <HAL_GPIO_Init+0x24e>
|
|
{
|
|
SET_BIT(EXTI->EMR, iocurrent);
|
|
8000a34: 4b23 ldr r3, [pc, #140] ; (8000ac4 <HAL_GPIO_Init+0x2d0>)
|
|
8000a36: 685a ldr r2, [r3, #4]
|
|
8000a38: 4922 ldr r1, [pc, #136] ; (8000ac4 <HAL_GPIO_Init+0x2d0>)
|
|
8000a3a: 69bb ldr r3, [r7, #24]
|
|
8000a3c: 4313 orrs r3, r2
|
|
8000a3e: 604b str r3, [r1, #4]
|
|
8000a40: e006 b.n 8000a50 <HAL_GPIO_Init+0x25c>
|
|
}
|
|
else
|
|
{
|
|
CLEAR_BIT(EXTI->EMR, iocurrent);
|
|
8000a42: 4b20 ldr r3, [pc, #128] ; (8000ac4 <HAL_GPIO_Init+0x2d0>)
|
|
8000a44: 685a ldr r2, [r3, #4]
|
|
8000a46: 69bb ldr r3, [r7, #24]
|
|
8000a48: 43db mvns r3, r3
|
|
8000a4a: 491e ldr r1, [pc, #120] ; (8000ac4 <HAL_GPIO_Init+0x2d0>)
|
|
8000a4c: 4013 ands r3, r2
|
|
8000a4e: 604b str r3, [r1, #4]
|
|
}
|
|
|
|
/* Enable or disable the rising trigger */
|
|
if ((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
|
|
8000a50: 683b ldr r3, [r7, #0]
|
|
8000a52: 685b ldr r3, [r3, #4]
|
|
8000a54: f403 1380 and.w r3, r3, #1048576 ; 0x100000
|
|
8000a58: 2b00 cmp r3, #0
|
|
8000a5a: d006 beq.n 8000a6a <HAL_GPIO_Init+0x276>
|
|
{
|
|
SET_BIT(EXTI->RTSR, iocurrent);
|
|
8000a5c: 4b19 ldr r3, [pc, #100] ; (8000ac4 <HAL_GPIO_Init+0x2d0>)
|
|
8000a5e: 689a ldr r2, [r3, #8]
|
|
8000a60: 4918 ldr r1, [pc, #96] ; (8000ac4 <HAL_GPIO_Init+0x2d0>)
|
|
8000a62: 69bb ldr r3, [r7, #24]
|
|
8000a64: 4313 orrs r3, r2
|
|
8000a66: 608b str r3, [r1, #8]
|
|
8000a68: e006 b.n 8000a78 <HAL_GPIO_Init+0x284>
|
|
}
|
|
else
|
|
{
|
|
CLEAR_BIT(EXTI->RTSR, iocurrent);
|
|
8000a6a: 4b16 ldr r3, [pc, #88] ; (8000ac4 <HAL_GPIO_Init+0x2d0>)
|
|
8000a6c: 689a ldr r2, [r3, #8]
|
|
8000a6e: 69bb ldr r3, [r7, #24]
|
|
8000a70: 43db mvns r3, r3
|
|
8000a72: 4914 ldr r1, [pc, #80] ; (8000ac4 <HAL_GPIO_Init+0x2d0>)
|
|
8000a74: 4013 ands r3, r2
|
|
8000a76: 608b str r3, [r1, #8]
|
|
}
|
|
|
|
/* Enable or disable the falling trigger */
|
|
if ((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
|
|
8000a78: 683b ldr r3, [r7, #0]
|
|
8000a7a: 685b ldr r3, [r3, #4]
|
|
8000a7c: f403 1300 and.w r3, r3, #2097152 ; 0x200000
|
|
8000a80: 2b00 cmp r3, #0
|
|
8000a82: d021 beq.n 8000ac8 <HAL_GPIO_Init+0x2d4>
|
|
{
|
|
SET_BIT(EXTI->FTSR, iocurrent);
|
|
8000a84: 4b0f ldr r3, [pc, #60] ; (8000ac4 <HAL_GPIO_Init+0x2d0>)
|
|
8000a86: 68da ldr r2, [r3, #12]
|
|
8000a88: 490e ldr r1, [pc, #56] ; (8000ac4 <HAL_GPIO_Init+0x2d0>)
|
|
8000a8a: 69bb ldr r3, [r7, #24]
|
|
8000a8c: 4313 orrs r3, r2
|
|
8000a8e: 60cb str r3, [r1, #12]
|
|
8000a90: e021 b.n 8000ad6 <HAL_GPIO_Init+0x2e2>
|
|
8000a92: bf00 nop
|
|
8000a94: 10320000 .word 0x10320000
|
|
8000a98: 10310000 .word 0x10310000
|
|
8000a9c: 10220000 .word 0x10220000
|
|
8000aa0: 10210000 .word 0x10210000
|
|
8000aa4: 10120000 .word 0x10120000
|
|
8000aa8: 10110000 .word 0x10110000
|
|
8000aac: 40021000 .word 0x40021000
|
|
8000ab0: 40010000 .word 0x40010000
|
|
8000ab4: 40010800 .word 0x40010800
|
|
8000ab8: 40010c00 .word 0x40010c00
|
|
8000abc: 40011000 .word 0x40011000
|
|
8000ac0: 40011400 .word 0x40011400
|
|
8000ac4: 40010400 .word 0x40010400
|
|
}
|
|
else
|
|
{
|
|
CLEAR_BIT(EXTI->FTSR, iocurrent);
|
|
8000ac8: 4b0b ldr r3, [pc, #44] ; (8000af8 <HAL_GPIO_Init+0x304>)
|
|
8000aca: 68da ldr r2, [r3, #12]
|
|
8000acc: 69bb ldr r3, [r7, #24]
|
|
8000ace: 43db mvns r3, r3
|
|
8000ad0: 4909 ldr r1, [pc, #36] ; (8000af8 <HAL_GPIO_Init+0x304>)
|
|
8000ad2: 4013 ands r3, r2
|
|
8000ad4: 60cb str r3, [r1, #12]
|
|
}
|
|
}
|
|
}
|
|
|
|
position++;
|
|
8000ad6: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
8000ad8: 3301 adds r3, #1
|
|
8000ada: 627b str r3, [r7, #36] ; 0x24
|
|
while (((GPIO_Init->Pin) >> position) != 0x00u)
|
|
8000adc: 683b ldr r3, [r7, #0]
|
|
8000ade: 681a ldr r2, [r3, #0]
|
|
8000ae0: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
8000ae2: fa22 f303 lsr.w r3, r2, r3
|
|
8000ae6: 2b00 cmp r3, #0
|
|
8000ae8: f47f ae8e bne.w 8000808 <HAL_GPIO_Init+0x14>
|
|
}
|
|
}
|
|
8000aec: bf00 nop
|
|
8000aee: bf00 nop
|
|
8000af0: 372c adds r7, #44 ; 0x2c
|
|
8000af2: 46bd mov sp, r7
|
|
8000af4: bc80 pop {r7}
|
|
8000af6: 4770 bx lr
|
|
8000af8: 40010400 .word 0x40010400
|
|
|
|
08000afc <HAL_RCC_OscConfig>:
|
|
* supported by this macro. User should request a transition to HSE Off
|
|
* first and then HSE On or HSE Bypass.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
|
|
{
|
|
8000afc: b580 push {r7, lr}
|
|
8000afe: b086 sub sp, #24
|
|
8000b00: af00 add r7, sp, #0
|
|
8000b02: 6078 str r0, [r7, #4]
|
|
uint32_t tickstart;
|
|
uint32_t pll_config;
|
|
|
|
/* Check Null pointer */
|
|
if (RCC_OscInitStruct == NULL)
|
|
8000b04: 687b ldr r3, [r7, #4]
|
|
8000b06: 2b00 cmp r3, #0
|
|
8000b08: d101 bne.n 8000b0e <HAL_RCC_OscConfig+0x12>
|
|
{
|
|
return HAL_ERROR;
|
|
8000b0a: 2301 movs r3, #1
|
|
8000b0c: e272 b.n 8000ff4 <HAL_RCC_OscConfig+0x4f8>
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
|
|
|
|
/*------------------------------- HSE Configuration ------------------------*/
|
|
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
|
|
8000b0e: 687b ldr r3, [r7, #4]
|
|
8000b10: 681b ldr r3, [r3, #0]
|
|
8000b12: f003 0301 and.w r3, r3, #1
|
|
8000b16: 2b00 cmp r3, #0
|
|
8000b18: f000 8087 beq.w 8000c2a <HAL_RCC_OscConfig+0x12e>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
|
|
|
|
/* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
|
|
if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)
|
|
8000b1c: 4b92 ldr r3, [pc, #584] ; (8000d68 <HAL_RCC_OscConfig+0x26c>)
|
|
8000b1e: 685b ldr r3, [r3, #4]
|
|
8000b20: f003 030c and.w r3, r3, #12
|
|
8000b24: 2b04 cmp r3, #4
|
|
8000b26: d00c beq.n 8000b42 <HAL_RCC_OscConfig+0x46>
|
|
|| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE)))
|
|
8000b28: 4b8f ldr r3, [pc, #572] ; (8000d68 <HAL_RCC_OscConfig+0x26c>)
|
|
8000b2a: 685b ldr r3, [r3, #4]
|
|
8000b2c: f003 030c and.w r3, r3, #12
|
|
8000b30: 2b08 cmp r3, #8
|
|
8000b32: d112 bne.n 8000b5a <HAL_RCC_OscConfig+0x5e>
|
|
8000b34: 4b8c ldr r3, [pc, #560] ; (8000d68 <HAL_RCC_OscConfig+0x26c>)
|
|
8000b36: 685b ldr r3, [r3, #4]
|
|
8000b38: f403 3380 and.w r3, r3, #65536 ; 0x10000
|
|
8000b3c: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
|
|
8000b40: d10b bne.n 8000b5a <HAL_RCC_OscConfig+0x5e>
|
|
{
|
|
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
|
|
8000b42: 4b89 ldr r3, [pc, #548] ; (8000d68 <HAL_RCC_OscConfig+0x26c>)
|
|
8000b44: 681b ldr r3, [r3, #0]
|
|
8000b46: f403 3300 and.w r3, r3, #131072 ; 0x20000
|
|
8000b4a: 2b00 cmp r3, #0
|
|
8000b4c: d06c beq.n 8000c28 <HAL_RCC_OscConfig+0x12c>
|
|
8000b4e: 687b ldr r3, [r7, #4]
|
|
8000b50: 685b ldr r3, [r3, #4]
|
|
8000b52: 2b00 cmp r3, #0
|
|
8000b54: d168 bne.n 8000c28 <HAL_RCC_OscConfig+0x12c>
|
|
{
|
|
return HAL_ERROR;
|
|
8000b56: 2301 movs r3, #1
|
|
8000b58: e24c b.n 8000ff4 <HAL_RCC_OscConfig+0x4f8>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Set the new HSE configuration ---------------------------------------*/
|
|
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
|
|
8000b5a: 687b ldr r3, [r7, #4]
|
|
8000b5c: 685b ldr r3, [r3, #4]
|
|
8000b5e: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
|
|
8000b62: d106 bne.n 8000b72 <HAL_RCC_OscConfig+0x76>
|
|
8000b64: 4b80 ldr r3, [pc, #512] ; (8000d68 <HAL_RCC_OscConfig+0x26c>)
|
|
8000b66: 681b ldr r3, [r3, #0]
|
|
8000b68: 4a7f ldr r2, [pc, #508] ; (8000d68 <HAL_RCC_OscConfig+0x26c>)
|
|
8000b6a: f443 3380 orr.w r3, r3, #65536 ; 0x10000
|
|
8000b6e: 6013 str r3, [r2, #0]
|
|
8000b70: e02e b.n 8000bd0 <HAL_RCC_OscConfig+0xd4>
|
|
8000b72: 687b ldr r3, [r7, #4]
|
|
8000b74: 685b ldr r3, [r3, #4]
|
|
8000b76: 2b00 cmp r3, #0
|
|
8000b78: d10c bne.n 8000b94 <HAL_RCC_OscConfig+0x98>
|
|
8000b7a: 4b7b ldr r3, [pc, #492] ; (8000d68 <HAL_RCC_OscConfig+0x26c>)
|
|
8000b7c: 681b ldr r3, [r3, #0]
|
|
8000b7e: 4a7a ldr r2, [pc, #488] ; (8000d68 <HAL_RCC_OscConfig+0x26c>)
|
|
8000b80: f423 3380 bic.w r3, r3, #65536 ; 0x10000
|
|
8000b84: 6013 str r3, [r2, #0]
|
|
8000b86: 4b78 ldr r3, [pc, #480] ; (8000d68 <HAL_RCC_OscConfig+0x26c>)
|
|
8000b88: 681b ldr r3, [r3, #0]
|
|
8000b8a: 4a77 ldr r2, [pc, #476] ; (8000d68 <HAL_RCC_OscConfig+0x26c>)
|
|
8000b8c: f423 2380 bic.w r3, r3, #262144 ; 0x40000
|
|
8000b90: 6013 str r3, [r2, #0]
|
|
8000b92: e01d b.n 8000bd0 <HAL_RCC_OscConfig+0xd4>
|
|
8000b94: 687b ldr r3, [r7, #4]
|
|
8000b96: 685b ldr r3, [r3, #4]
|
|
8000b98: f5b3 2fa0 cmp.w r3, #327680 ; 0x50000
|
|
8000b9c: d10c bne.n 8000bb8 <HAL_RCC_OscConfig+0xbc>
|
|
8000b9e: 4b72 ldr r3, [pc, #456] ; (8000d68 <HAL_RCC_OscConfig+0x26c>)
|
|
8000ba0: 681b ldr r3, [r3, #0]
|
|
8000ba2: 4a71 ldr r2, [pc, #452] ; (8000d68 <HAL_RCC_OscConfig+0x26c>)
|
|
8000ba4: f443 2380 orr.w r3, r3, #262144 ; 0x40000
|
|
8000ba8: 6013 str r3, [r2, #0]
|
|
8000baa: 4b6f ldr r3, [pc, #444] ; (8000d68 <HAL_RCC_OscConfig+0x26c>)
|
|
8000bac: 681b ldr r3, [r3, #0]
|
|
8000bae: 4a6e ldr r2, [pc, #440] ; (8000d68 <HAL_RCC_OscConfig+0x26c>)
|
|
8000bb0: f443 3380 orr.w r3, r3, #65536 ; 0x10000
|
|
8000bb4: 6013 str r3, [r2, #0]
|
|
8000bb6: e00b b.n 8000bd0 <HAL_RCC_OscConfig+0xd4>
|
|
8000bb8: 4b6b ldr r3, [pc, #428] ; (8000d68 <HAL_RCC_OscConfig+0x26c>)
|
|
8000bba: 681b ldr r3, [r3, #0]
|
|
8000bbc: 4a6a ldr r2, [pc, #424] ; (8000d68 <HAL_RCC_OscConfig+0x26c>)
|
|
8000bbe: f423 3380 bic.w r3, r3, #65536 ; 0x10000
|
|
8000bc2: 6013 str r3, [r2, #0]
|
|
8000bc4: 4b68 ldr r3, [pc, #416] ; (8000d68 <HAL_RCC_OscConfig+0x26c>)
|
|
8000bc6: 681b ldr r3, [r3, #0]
|
|
8000bc8: 4a67 ldr r2, [pc, #412] ; (8000d68 <HAL_RCC_OscConfig+0x26c>)
|
|
8000bca: f423 2380 bic.w r3, r3, #262144 ; 0x40000
|
|
8000bce: 6013 str r3, [r2, #0]
|
|
|
|
|
|
/* Check the HSE State */
|
|
if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
|
|
8000bd0: 687b ldr r3, [r7, #4]
|
|
8000bd2: 685b ldr r3, [r3, #4]
|
|
8000bd4: 2b00 cmp r3, #0
|
|
8000bd6: d013 beq.n 8000c00 <HAL_RCC_OscConfig+0x104>
|
|
{
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
8000bd8: f7ff fcfa bl 80005d0 <HAL_GetTick>
|
|
8000bdc: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till HSE is ready */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
|
|
8000bde: e008 b.n 8000bf2 <HAL_RCC_OscConfig+0xf6>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
|
|
8000be0: f7ff fcf6 bl 80005d0 <HAL_GetTick>
|
|
8000be4: 4602 mov r2, r0
|
|
8000be6: 693b ldr r3, [r7, #16]
|
|
8000be8: 1ad3 subs r3, r2, r3
|
|
8000bea: 2b64 cmp r3, #100 ; 0x64
|
|
8000bec: d901 bls.n 8000bf2 <HAL_RCC_OscConfig+0xf6>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8000bee: 2303 movs r3, #3
|
|
8000bf0: e200 b.n 8000ff4 <HAL_RCC_OscConfig+0x4f8>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
|
|
8000bf2: 4b5d ldr r3, [pc, #372] ; (8000d68 <HAL_RCC_OscConfig+0x26c>)
|
|
8000bf4: 681b ldr r3, [r3, #0]
|
|
8000bf6: f403 3300 and.w r3, r3, #131072 ; 0x20000
|
|
8000bfa: 2b00 cmp r3, #0
|
|
8000bfc: d0f0 beq.n 8000be0 <HAL_RCC_OscConfig+0xe4>
|
|
8000bfe: e014 b.n 8000c2a <HAL_RCC_OscConfig+0x12e>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
8000c00: f7ff fce6 bl 80005d0 <HAL_GetTick>
|
|
8000c04: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till HSE is disabled */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
|
|
8000c06: e008 b.n 8000c1a <HAL_RCC_OscConfig+0x11e>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
|
|
8000c08: f7ff fce2 bl 80005d0 <HAL_GetTick>
|
|
8000c0c: 4602 mov r2, r0
|
|
8000c0e: 693b ldr r3, [r7, #16]
|
|
8000c10: 1ad3 subs r3, r2, r3
|
|
8000c12: 2b64 cmp r3, #100 ; 0x64
|
|
8000c14: d901 bls.n 8000c1a <HAL_RCC_OscConfig+0x11e>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8000c16: 2303 movs r3, #3
|
|
8000c18: e1ec b.n 8000ff4 <HAL_RCC_OscConfig+0x4f8>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
|
|
8000c1a: 4b53 ldr r3, [pc, #332] ; (8000d68 <HAL_RCC_OscConfig+0x26c>)
|
|
8000c1c: 681b ldr r3, [r3, #0]
|
|
8000c1e: f403 3300 and.w r3, r3, #131072 ; 0x20000
|
|
8000c22: 2b00 cmp r3, #0
|
|
8000c24: d1f0 bne.n 8000c08 <HAL_RCC_OscConfig+0x10c>
|
|
8000c26: e000 b.n 8000c2a <HAL_RCC_OscConfig+0x12e>
|
|
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
|
|
8000c28: bf00 nop
|
|
}
|
|
}
|
|
}
|
|
}
|
|
/*----------------------------- HSI Configuration --------------------------*/
|
|
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
|
|
8000c2a: 687b ldr r3, [r7, #4]
|
|
8000c2c: 681b ldr r3, [r3, #0]
|
|
8000c2e: f003 0302 and.w r3, r3, #2
|
|
8000c32: 2b00 cmp r3, #0
|
|
8000c34: d063 beq.n 8000cfe <HAL_RCC_OscConfig+0x202>
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
|
|
assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
|
|
|
|
/* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
|
|
if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)
|
|
8000c36: 4b4c ldr r3, [pc, #304] ; (8000d68 <HAL_RCC_OscConfig+0x26c>)
|
|
8000c38: 685b ldr r3, [r3, #4]
|
|
8000c3a: f003 030c and.w r3, r3, #12
|
|
8000c3e: 2b00 cmp r3, #0
|
|
8000c40: d00b beq.n 8000c5a <HAL_RCC_OscConfig+0x15e>
|
|
|| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI_DIV2)))
|
|
8000c42: 4b49 ldr r3, [pc, #292] ; (8000d68 <HAL_RCC_OscConfig+0x26c>)
|
|
8000c44: 685b ldr r3, [r3, #4]
|
|
8000c46: f003 030c and.w r3, r3, #12
|
|
8000c4a: 2b08 cmp r3, #8
|
|
8000c4c: d11c bne.n 8000c88 <HAL_RCC_OscConfig+0x18c>
|
|
8000c4e: 4b46 ldr r3, [pc, #280] ; (8000d68 <HAL_RCC_OscConfig+0x26c>)
|
|
8000c50: 685b ldr r3, [r3, #4]
|
|
8000c52: f403 3380 and.w r3, r3, #65536 ; 0x10000
|
|
8000c56: 2b00 cmp r3, #0
|
|
8000c58: d116 bne.n 8000c88 <HAL_RCC_OscConfig+0x18c>
|
|
{
|
|
/* When HSI is used as system clock it will not disabled */
|
|
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
|
|
8000c5a: 4b43 ldr r3, [pc, #268] ; (8000d68 <HAL_RCC_OscConfig+0x26c>)
|
|
8000c5c: 681b ldr r3, [r3, #0]
|
|
8000c5e: f003 0302 and.w r3, r3, #2
|
|
8000c62: 2b00 cmp r3, #0
|
|
8000c64: d005 beq.n 8000c72 <HAL_RCC_OscConfig+0x176>
|
|
8000c66: 687b ldr r3, [r7, #4]
|
|
8000c68: 691b ldr r3, [r3, #16]
|
|
8000c6a: 2b01 cmp r3, #1
|
|
8000c6c: d001 beq.n 8000c72 <HAL_RCC_OscConfig+0x176>
|
|
{
|
|
return HAL_ERROR;
|
|
8000c6e: 2301 movs r3, #1
|
|
8000c70: e1c0 b.n 8000ff4 <HAL_RCC_OscConfig+0x4f8>
|
|
}
|
|
/* Otherwise, just the calibration is allowed */
|
|
else
|
|
{
|
|
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
|
|
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
|
|
8000c72: 4b3d ldr r3, [pc, #244] ; (8000d68 <HAL_RCC_OscConfig+0x26c>)
|
|
8000c74: 681b ldr r3, [r3, #0]
|
|
8000c76: f023 02f8 bic.w r2, r3, #248 ; 0xf8
|
|
8000c7a: 687b ldr r3, [r7, #4]
|
|
8000c7c: 695b ldr r3, [r3, #20]
|
|
8000c7e: 00db lsls r3, r3, #3
|
|
8000c80: 4939 ldr r1, [pc, #228] ; (8000d68 <HAL_RCC_OscConfig+0x26c>)
|
|
8000c82: 4313 orrs r3, r2
|
|
8000c84: 600b str r3, [r1, #0]
|
|
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
|
|
8000c86: e03a b.n 8000cfe <HAL_RCC_OscConfig+0x202>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Check the HSI State */
|
|
if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
|
|
8000c88: 687b ldr r3, [r7, #4]
|
|
8000c8a: 691b ldr r3, [r3, #16]
|
|
8000c8c: 2b00 cmp r3, #0
|
|
8000c8e: d020 beq.n 8000cd2 <HAL_RCC_OscConfig+0x1d6>
|
|
{
|
|
/* Enable the Internal High Speed oscillator (HSI). */
|
|
__HAL_RCC_HSI_ENABLE();
|
|
8000c90: 4b36 ldr r3, [pc, #216] ; (8000d6c <HAL_RCC_OscConfig+0x270>)
|
|
8000c92: 2201 movs r2, #1
|
|
8000c94: 601a str r2, [r3, #0]
|
|
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
8000c96: f7ff fc9b bl 80005d0 <HAL_GetTick>
|
|
8000c9a: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till HSI is ready */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
|
|
8000c9c: e008 b.n 8000cb0 <HAL_RCC_OscConfig+0x1b4>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
|
|
8000c9e: f7ff fc97 bl 80005d0 <HAL_GetTick>
|
|
8000ca2: 4602 mov r2, r0
|
|
8000ca4: 693b ldr r3, [r7, #16]
|
|
8000ca6: 1ad3 subs r3, r2, r3
|
|
8000ca8: 2b02 cmp r3, #2
|
|
8000caa: d901 bls.n 8000cb0 <HAL_RCC_OscConfig+0x1b4>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8000cac: 2303 movs r3, #3
|
|
8000cae: e1a1 b.n 8000ff4 <HAL_RCC_OscConfig+0x4f8>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
|
|
8000cb0: 4b2d ldr r3, [pc, #180] ; (8000d68 <HAL_RCC_OscConfig+0x26c>)
|
|
8000cb2: 681b ldr r3, [r3, #0]
|
|
8000cb4: f003 0302 and.w r3, r3, #2
|
|
8000cb8: 2b00 cmp r3, #0
|
|
8000cba: d0f0 beq.n 8000c9e <HAL_RCC_OscConfig+0x1a2>
|
|
}
|
|
}
|
|
|
|
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
|
|
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
|
|
8000cbc: 4b2a ldr r3, [pc, #168] ; (8000d68 <HAL_RCC_OscConfig+0x26c>)
|
|
8000cbe: 681b ldr r3, [r3, #0]
|
|
8000cc0: f023 02f8 bic.w r2, r3, #248 ; 0xf8
|
|
8000cc4: 687b ldr r3, [r7, #4]
|
|
8000cc6: 695b ldr r3, [r3, #20]
|
|
8000cc8: 00db lsls r3, r3, #3
|
|
8000cca: 4927 ldr r1, [pc, #156] ; (8000d68 <HAL_RCC_OscConfig+0x26c>)
|
|
8000ccc: 4313 orrs r3, r2
|
|
8000cce: 600b str r3, [r1, #0]
|
|
8000cd0: e015 b.n 8000cfe <HAL_RCC_OscConfig+0x202>
|
|
}
|
|
else
|
|
{
|
|
/* Disable the Internal High Speed oscillator (HSI). */
|
|
__HAL_RCC_HSI_DISABLE();
|
|
8000cd2: 4b26 ldr r3, [pc, #152] ; (8000d6c <HAL_RCC_OscConfig+0x270>)
|
|
8000cd4: 2200 movs r2, #0
|
|
8000cd6: 601a str r2, [r3, #0]
|
|
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
8000cd8: f7ff fc7a bl 80005d0 <HAL_GetTick>
|
|
8000cdc: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till HSI is disabled */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
|
|
8000cde: e008 b.n 8000cf2 <HAL_RCC_OscConfig+0x1f6>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
|
|
8000ce0: f7ff fc76 bl 80005d0 <HAL_GetTick>
|
|
8000ce4: 4602 mov r2, r0
|
|
8000ce6: 693b ldr r3, [r7, #16]
|
|
8000ce8: 1ad3 subs r3, r2, r3
|
|
8000cea: 2b02 cmp r3, #2
|
|
8000cec: d901 bls.n 8000cf2 <HAL_RCC_OscConfig+0x1f6>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8000cee: 2303 movs r3, #3
|
|
8000cf0: e180 b.n 8000ff4 <HAL_RCC_OscConfig+0x4f8>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
|
|
8000cf2: 4b1d ldr r3, [pc, #116] ; (8000d68 <HAL_RCC_OscConfig+0x26c>)
|
|
8000cf4: 681b ldr r3, [r3, #0]
|
|
8000cf6: f003 0302 and.w r3, r3, #2
|
|
8000cfa: 2b00 cmp r3, #0
|
|
8000cfc: d1f0 bne.n 8000ce0 <HAL_RCC_OscConfig+0x1e4>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
/*------------------------------ LSI Configuration -------------------------*/
|
|
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
|
|
8000cfe: 687b ldr r3, [r7, #4]
|
|
8000d00: 681b ldr r3, [r3, #0]
|
|
8000d02: f003 0308 and.w r3, r3, #8
|
|
8000d06: 2b00 cmp r3, #0
|
|
8000d08: d03a beq.n 8000d80 <HAL_RCC_OscConfig+0x284>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
|
|
|
|
/* Check the LSI State */
|
|
if (RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
|
|
8000d0a: 687b ldr r3, [r7, #4]
|
|
8000d0c: 699b ldr r3, [r3, #24]
|
|
8000d0e: 2b00 cmp r3, #0
|
|
8000d10: d019 beq.n 8000d46 <HAL_RCC_OscConfig+0x24a>
|
|
{
|
|
/* Enable the Internal Low Speed oscillator (LSI). */
|
|
__HAL_RCC_LSI_ENABLE();
|
|
8000d12: 4b17 ldr r3, [pc, #92] ; (8000d70 <HAL_RCC_OscConfig+0x274>)
|
|
8000d14: 2201 movs r2, #1
|
|
8000d16: 601a str r2, [r3, #0]
|
|
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
8000d18: f7ff fc5a bl 80005d0 <HAL_GetTick>
|
|
8000d1c: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till LSI is ready */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
|
|
8000d1e: e008 b.n 8000d32 <HAL_RCC_OscConfig+0x236>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
|
|
8000d20: f7ff fc56 bl 80005d0 <HAL_GetTick>
|
|
8000d24: 4602 mov r2, r0
|
|
8000d26: 693b ldr r3, [r7, #16]
|
|
8000d28: 1ad3 subs r3, r2, r3
|
|
8000d2a: 2b02 cmp r3, #2
|
|
8000d2c: d901 bls.n 8000d32 <HAL_RCC_OscConfig+0x236>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8000d2e: 2303 movs r3, #3
|
|
8000d30: e160 b.n 8000ff4 <HAL_RCC_OscConfig+0x4f8>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
|
|
8000d32: 4b0d ldr r3, [pc, #52] ; (8000d68 <HAL_RCC_OscConfig+0x26c>)
|
|
8000d34: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
8000d36: f003 0302 and.w r3, r3, #2
|
|
8000d3a: 2b00 cmp r3, #0
|
|
8000d3c: d0f0 beq.n 8000d20 <HAL_RCC_OscConfig+0x224>
|
|
}
|
|
}
|
|
/* To have a fully stabilized clock in the specified range, a software delay of 1ms
|
|
should be added.*/
|
|
RCC_Delay(1);
|
|
8000d3e: 2001 movs r0, #1
|
|
8000d40: f000 faa6 bl 8001290 <RCC_Delay>
|
|
8000d44: e01c b.n 8000d80 <HAL_RCC_OscConfig+0x284>
|
|
}
|
|
else
|
|
{
|
|
/* Disable the Internal Low Speed oscillator (LSI). */
|
|
__HAL_RCC_LSI_DISABLE();
|
|
8000d46: 4b0a ldr r3, [pc, #40] ; (8000d70 <HAL_RCC_OscConfig+0x274>)
|
|
8000d48: 2200 movs r2, #0
|
|
8000d4a: 601a str r2, [r3, #0]
|
|
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
8000d4c: f7ff fc40 bl 80005d0 <HAL_GetTick>
|
|
8000d50: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till LSI is disabled */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
|
|
8000d52: e00f b.n 8000d74 <HAL_RCC_OscConfig+0x278>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
|
|
8000d54: f7ff fc3c bl 80005d0 <HAL_GetTick>
|
|
8000d58: 4602 mov r2, r0
|
|
8000d5a: 693b ldr r3, [r7, #16]
|
|
8000d5c: 1ad3 subs r3, r2, r3
|
|
8000d5e: 2b02 cmp r3, #2
|
|
8000d60: d908 bls.n 8000d74 <HAL_RCC_OscConfig+0x278>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8000d62: 2303 movs r3, #3
|
|
8000d64: e146 b.n 8000ff4 <HAL_RCC_OscConfig+0x4f8>
|
|
8000d66: bf00 nop
|
|
8000d68: 40021000 .word 0x40021000
|
|
8000d6c: 42420000 .word 0x42420000
|
|
8000d70: 42420480 .word 0x42420480
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
|
|
8000d74: 4b92 ldr r3, [pc, #584] ; (8000fc0 <HAL_RCC_OscConfig+0x4c4>)
|
|
8000d76: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
8000d78: f003 0302 and.w r3, r3, #2
|
|
8000d7c: 2b00 cmp r3, #0
|
|
8000d7e: d1e9 bne.n 8000d54 <HAL_RCC_OscConfig+0x258>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
/*------------------------------ LSE Configuration -------------------------*/
|
|
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
|
|
8000d80: 687b ldr r3, [r7, #4]
|
|
8000d82: 681b ldr r3, [r3, #0]
|
|
8000d84: f003 0304 and.w r3, r3, #4
|
|
8000d88: 2b00 cmp r3, #0
|
|
8000d8a: f000 80a6 beq.w 8000eda <HAL_RCC_OscConfig+0x3de>
|
|
{
|
|
FlagStatus pwrclkchanged = RESET;
|
|
8000d8e: 2300 movs r3, #0
|
|
8000d90: 75fb strb r3, [r7, #23]
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
|
|
|
|
/* Update LSE configuration in Backup Domain control register */
|
|
/* Requires to enable write access to Backup Domain of necessary */
|
|
if (__HAL_RCC_PWR_IS_CLK_DISABLED())
|
|
8000d92: 4b8b ldr r3, [pc, #556] ; (8000fc0 <HAL_RCC_OscConfig+0x4c4>)
|
|
8000d94: 69db ldr r3, [r3, #28]
|
|
8000d96: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
|
|
8000d9a: 2b00 cmp r3, #0
|
|
8000d9c: d10d bne.n 8000dba <HAL_RCC_OscConfig+0x2be>
|
|
{
|
|
__HAL_RCC_PWR_CLK_ENABLE();
|
|
8000d9e: 4b88 ldr r3, [pc, #544] ; (8000fc0 <HAL_RCC_OscConfig+0x4c4>)
|
|
8000da0: 69db ldr r3, [r3, #28]
|
|
8000da2: 4a87 ldr r2, [pc, #540] ; (8000fc0 <HAL_RCC_OscConfig+0x4c4>)
|
|
8000da4: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
|
|
8000da8: 61d3 str r3, [r2, #28]
|
|
8000daa: 4b85 ldr r3, [pc, #532] ; (8000fc0 <HAL_RCC_OscConfig+0x4c4>)
|
|
8000dac: 69db ldr r3, [r3, #28]
|
|
8000dae: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
|
|
8000db2: 60bb str r3, [r7, #8]
|
|
8000db4: 68bb ldr r3, [r7, #8]
|
|
pwrclkchanged = SET;
|
|
8000db6: 2301 movs r3, #1
|
|
8000db8: 75fb strb r3, [r7, #23]
|
|
}
|
|
|
|
if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
|
|
8000dba: 4b82 ldr r3, [pc, #520] ; (8000fc4 <HAL_RCC_OscConfig+0x4c8>)
|
|
8000dbc: 681b ldr r3, [r3, #0]
|
|
8000dbe: f403 7380 and.w r3, r3, #256 ; 0x100
|
|
8000dc2: 2b00 cmp r3, #0
|
|
8000dc4: d118 bne.n 8000df8 <HAL_RCC_OscConfig+0x2fc>
|
|
{
|
|
/* Enable write access to Backup domain */
|
|
SET_BIT(PWR->CR, PWR_CR_DBP);
|
|
8000dc6: 4b7f ldr r3, [pc, #508] ; (8000fc4 <HAL_RCC_OscConfig+0x4c8>)
|
|
8000dc8: 681b ldr r3, [r3, #0]
|
|
8000dca: 4a7e ldr r2, [pc, #504] ; (8000fc4 <HAL_RCC_OscConfig+0x4c8>)
|
|
8000dcc: f443 7380 orr.w r3, r3, #256 ; 0x100
|
|
8000dd0: 6013 str r3, [r2, #0]
|
|
|
|
/* Wait for Backup domain Write protection disable */
|
|
tickstart = HAL_GetTick();
|
|
8000dd2: f7ff fbfd bl 80005d0 <HAL_GetTick>
|
|
8000dd6: 6138 str r0, [r7, #16]
|
|
|
|
while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
|
|
8000dd8: e008 b.n 8000dec <HAL_RCC_OscConfig+0x2f0>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
|
|
8000dda: f7ff fbf9 bl 80005d0 <HAL_GetTick>
|
|
8000dde: 4602 mov r2, r0
|
|
8000de0: 693b ldr r3, [r7, #16]
|
|
8000de2: 1ad3 subs r3, r2, r3
|
|
8000de4: 2b64 cmp r3, #100 ; 0x64
|
|
8000de6: d901 bls.n 8000dec <HAL_RCC_OscConfig+0x2f0>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8000de8: 2303 movs r3, #3
|
|
8000dea: e103 b.n 8000ff4 <HAL_RCC_OscConfig+0x4f8>
|
|
while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
|
|
8000dec: 4b75 ldr r3, [pc, #468] ; (8000fc4 <HAL_RCC_OscConfig+0x4c8>)
|
|
8000dee: 681b ldr r3, [r3, #0]
|
|
8000df0: f403 7380 and.w r3, r3, #256 ; 0x100
|
|
8000df4: 2b00 cmp r3, #0
|
|
8000df6: d0f0 beq.n 8000dda <HAL_RCC_OscConfig+0x2de>
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Set the new LSE configuration -----------------------------------------*/
|
|
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
|
|
8000df8: 687b ldr r3, [r7, #4]
|
|
8000dfa: 68db ldr r3, [r3, #12]
|
|
8000dfc: 2b01 cmp r3, #1
|
|
8000dfe: d106 bne.n 8000e0e <HAL_RCC_OscConfig+0x312>
|
|
8000e00: 4b6f ldr r3, [pc, #444] ; (8000fc0 <HAL_RCC_OscConfig+0x4c4>)
|
|
8000e02: 6a1b ldr r3, [r3, #32]
|
|
8000e04: 4a6e ldr r2, [pc, #440] ; (8000fc0 <HAL_RCC_OscConfig+0x4c4>)
|
|
8000e06: f043 0301 orr.w r3, r3, #1
|
|
8000e0a: 6213 str r3, [r2, #32]
|
|
8000e0c: e02d b.n 8000e6a <HAL_RCC_OscConfig+0x36e>
|
|
8000e0e: 687b ldr r3, [r7, #4]
|
|
8000e10: 68db ldr r3, [r3, #12]
|
|
8000e12: 2b00 cmp r3, #0
|
|
8000e14: d10c bne.n 8000e30 <HAL_RCC_OscConfig+0x334>
|
|
8000e16: 4b6a ldr r3, [pc, #424] ; (8000fc0 <HAL_RCC_OscConfig+0x4c4>)
|
|
8000e18: 6a1b ldr r3, [r3, #32]
|
|
8000e1a: 4a69 ldr r2, [pc, #420] ; (8000fc0 <HAL_RCC_OscConfig+0x4c4>)
|
|
8000e1c: f023 0301 bic.w r3, r3, #1
|
|
8000e20: 6213 str r3, [r2, #32]
|
|
8000e22: 4b67 ldr r3, [pc, #412] ; (8000fc0 <HAL_RCC_OscConfig+0x4c4>)
|
|
8000e24: 6a1b ldr r3, [r3, #32]
|
|
8000e26: 4a66 ldr r2, [pc, #408] ; (8000fc0 <HAL_RCC_OscConfig+0x4c4>)
|
|
8000e28: f023 0304 bic.w r3, r3, #4
|
|
8000e2c: 6213 str r3, [r2, #32]
|
|
8000e2e: e01c b.n 8000e6a <HAL_RCC_OscConfig+0x36e>
|
|
8000e30: 687b ldr r3, [r7, #4]
|
|
8000e32: 68db ldr r3, [r3, #12]
|
|
8000e34: 2b05 cmp r3, #5
|
|
8000e36: d10c bne.n 8000e52 <HAL_RCC_OscConfig+0x356>
|
|
8000e38: 4b61 ldr r3, [pc, #388] ; (8000fc0 <HAL_RCC_OscConfig+0x4c4>)
|
|
8000e3a: 6a1b ldr r3, [r3, #32]
|
|
8000e3c: 4a60 ldr r2, [pc, #384] ; (8000fc0 <HAL_RCC_OscConfig+0x4c4>)
|
|
8000e3e: f043 0304 orr.w r3, r3, #4
|
|
8000e42: 6213 str r3, [r2, #32]
|
|
8000e44: 4b5e ldr r3, [pc, #376] ; (8000fc0 <HAL_RCC_OscConfig+0x4c4>)
|
|
8000e46: 6a1b ldr r3, [r3, #32]
|
|
8000e48: 4a5d ldr r2, [pc, #372] ; (8000fc0 <HAL_RCC_OscConfig+0x4c4>)
|
|
8000e4a: f043 0301 orr.w r3, r3, #1
|
|
8000e4e: 6213 str r3, [r2, #32]
|
|
8000e50: e00b b.n 8000e6a <HAL_RCC_OscConfig+0x36e>
|
|
8000e52: 4b5b ldr r3, [pc, #364] ; (8000fc0 <HAL_RCC_OscConfig+0x4c4>)
|
|
8000e54: 6a1b ldr r3, [r3, #32]
|
|
8000e56: 4a5a ldr r2, [pc, #360] ; (8000fc0 <HAL_RCC_OscConfig+0x4c4>)
|
|
8000e58: f023 0301 bic.w r3, r3, #1
|
|
8000e5c: 6213 str r3, [r2, #32]
|
|
8000e5e: 4b58 ldr r3, [pc, #352] ; (8000fc0 <HAL_RCC_OscConfig+0x4c4>)
|
|
8000e60: 6a1b ldr r3, [r3, #32]
|
|
8000e62: 4a57 ldr r2, [pc, #348] ; (8000fc0 <HAL_RCC_OscConfig+0x4c4>)
|
|
8000e64: f023 0304 bic.w r3, r3, #4
|
|
8000e68: 6213 str r3, [r2, #32]
|
|
/* Check the LSE State */
|
|
if (RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
|
|
8000e6a: 687b ldr r3, [r7, #4]
|
|
8000e6c: 68db ldr r3, [r3, #12]
|
|
8000e6e: 2b00 cmp r3, #0
|
|
8000e70: d015 beq.n 8000e9e <HAL_RCC_OscConfig+0x3a2>
|
|
{
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
8000e72: f7ff fbad bl 80005d0 <HAL_GetTick>
|
|
8000e76: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till LSE is ready */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
|
|
8000e78: e00a b.n 8000e90 <HAL_RCC_OscConfig+0x394>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
|
|
8000e7a: f7ff fba9 bl 80005d0 <HAL_GetTick>
|
|
8000e7e: 4602 mov r2, r0
|
|
8000e80: 693b ldr r3, [r7, #16]
|
|
8000e82: 1ad3 subs r3, r2, r3
|
|
8000e84: f241 3288 movw r2, #5000 ; 0x1388
|
|
8000e88: 4293 cmp r3, r2
|
|
8000e8a: d901 bls.n 8000e90 <HAL_RCC_OscConfig+0x394>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8000e8c: 2303 movs r3, #3
|
|
8000e8e: e0b1 b.n 8000ff4 <HAL_RCC_OscConfig+0x4f8>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
|
|
8000e90: 4b4b ldr r3, [pc, #300] ; (8000fc0 <HAL_RCC_OscConfig+0x4c4>)
|
|
8000e92: 6a1b ldr r3, [r3, #32]
|
|
8000e94: f003 0302 and.w r3, r3, #2
|
|
8000e98: 2b00 cmp r3, #0
|
|
8000e9a: d0ee beq.n 8000e7a <HAL_RCC_OscConfig+0x37e>
|
|
8000e9c: e014 b.n 8000ec8 <HAL_RCC_OscConfig+0x3cc>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
8000e9e: f7ff fb97 bl 80005d0 <HAL_GetTick>
|
|
8000ea2: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till LSE is disabled */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
|
|
8000ea4: e00a b.n 8000ebc <HAL_RCC_OscConfig+0x3c0>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
|
|
8000ea6: f7ff fb93 bl 80005d0 <HAL_GetTick>
|
|
8000eaa: 4602 mov r2, r0
|
|
8000eac: 693b ldr r3, [r7, #16]
|
|
8000eae: 1ad3 subs r3, r2, r3
|
|
8000eb0: f241 3288 movw r2, #5000 ; 0x1388
|
|
8000eb4: 4293 cmp r3, r2
|
|
8000eb6: d901 bls.n 8000ebc <HAL_RCC_OscConfig+0x3c0>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8000eb8: 2303 movs r3, #3
|
|
8000eba: e09b b.n 8000ff4 <HAL_RCC_OscConfig+0x4f8>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
|
|
8000ebc: 4b40 ldr r3, [pc, #256] ; (8000fc0 <HAL_RCC_OscConfig+0x4c4>)
|
|
8000ebe: 6a1b ldr r3, [r3, #32]
|
|
8000ec0: f003 0302 and.w r3, r3, #2
|
|
8000ec4: 2b00 cmp r3, #0
|
|
8000ec6: d1ee bne.n 8000ea6 <HAL_RCC_OscConfig+0x3aa>
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Require to disable power clock if necessary */
|
|
if (pwrclkchanged == SET)
|
|
8000ec8: 7dfb ldrb r3, [r7, #23]
|
|
8000eca: 2b01 cmp r3, #1
|
|
8000ecc: d105 bne.n 8000eda <HAL_RCC_OscConfig+0x3de>
|
|
{
|
|
__HAL_RCC_PWR_CLK_DISABLE();
|
|
8000ece: 4b3c ldr r3, [pc, #240] ; (8000fc0 <HAL_RCC_OscConfig+0x4c4>)
|
|
8000ed0: 69db ldr r3, [r3, #28]
|
|
8000ed2: 4a3b ldr r2, [pc, #236] ; (8000fc0 <HAL_RCC_OscConfig+0x4c4>)
|
|
8000ed4: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000
|
|
8000ed8: 61d3 str r3, [r2, #28]
|
|
|
|
#endif /* RCC_CR_PLL2ON */
|
|
/*-------------------------------- PLL Configuration -----------------------*/
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
|
|
if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
|
|
8000eda: 687b ldr r3, [r7, #4]
|
|
8000edc: 69db ldr r3, [r3, #28]
|
|
8000ede: 2b00 cmp r3, #0
|
|
8000ee0: f000 8087 beq.w 8000ff2 <HAL_RCC_OscConfig+0x4f6>
|
|
{
|
|
/* Check if the PLL is used as system clock or not */
|
|
if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
|
|
8000ee4: 4b36 ldr r3, [pc, #216] ; (8000fc0 <HAL_RCC_OscConfig+0x4c4>)
|
|
8000ee6: 685b ldr r3, [r3, #4]
|
|
8000ee8: f003 030c and.w r3, r3, #12
|
|
8000eec: 2b08 cmp r3, #8
|
|
8000eee: d061 beq.n 8000fb4 <HAL_RCC_OscConfig+0x4b8>
|
|
{
|
|
if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
|
|
8000ef0: 687b ldr r3, [r7, #4]
|
|
8000ef2: 69db ldr r3, [r3, #28]
|
|
8000ef4: 2b02 cmp r3, #2
|
|
8000ef6: d146 bne.n 8000f86 <HAL_RCC_OscConfig+0x48a>
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
|
|
assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL));
|
|
|
|
/* Disable the main PLL. */
|
|
__HAL_RCC_PLL_DISABLE();
|
|
8000ef8: 4b33 ldr r3, [pc, #204] ; (8000fc8 <HAL_RCC_OscConfig+0x4cc>)
|
|
8000efa: 2200 movs r2, #0
|
|
8000efc: 601a str r2, [r3, #0]
|
|
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
8000efe: f7ff fb67 bl 80005d0 <HAL_GetTick>
|
|
8000f02: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till PLL is disabled */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
|
|
8000f04: e008 b.n 8000f18 <HAL_RCC_OscConfig+0x41c>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
|
|
8000f06: f7ff fb63 bl 80005d0 <HAL_GetTick>
|
|
8000f0a: 4602 mov r2, r0
|
|
8000f0c: 693b ldr r3, [r7, #16]
|
|
8000f0e: 1ad3 subs r3, r2, r3
|
|
8000f10: 2b02 cmp r3, #2
|
|
8000f12: d901 bls.n 8000f18 <HAL_RCC_OscConfig+0x41c>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8000f14: 2303 movs r3, #3
|
|
8000f16: e06d b.n 8000ff4 <HAL_RCC_OscConfig+0x4f8>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
|
|
8000f18: 4b29 ldr r3, [pc, #164] ; (8000fc0 <HAL_RCC_OscConfig+0x4c4>)
|
|
8000f1a: 681b ldr r3, [r3, #0]
|
|
8000f1c: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
|
|
8000f20: 2b00 cmp r3, #0
|
|
8000f22: d1f0 bne.n 8000f06 <HAL_RCC_OscConfig+0x40a>
|
|
}
|
|
}
|
|
|
|
/* Configure the HSE prediv factor --------------------------------*/
|
|
/* It can be written only when the PLL is disabled. Not used in PLL source is different than HSE */
|
|
if (RCC_OscInitStruct->PLL.PLLSource == RCC_PLLSOURCE_HSE)
|
|
8000f24: 687b ldr r3, [r7, #4]
|
|
8000f26: 6a1b ldr r3, [r3, #32]
|
|
8000f28: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
|
|
8000f2c: d108 bne.n 8000f40 <HAL_RCC_OscConfig+0x444>
|
|
/* Set PREDIV1 source */
|
|
SET_BIT(RCC->CFGR2, RCC_OscInitStruct->Prediv1Source);
|
|
#endif /* RCC_CFGR2_PREDIV1SRC */
|
|
|
|
/* Set PREDIV1 Value */
|
|
__HAL_RCC_HSE_PREDIV_CONFIG(RCC_OscInitStruct->HSEPredivValue);
|
|
8000f2e: 4b24 ldr r3, [pc, #144] ; (8000fc0 <HAL_RCC_OscConfig+0x4c4>)
|
|
8000f30: 685b ldr r3, [r3, #4]
|
|
8000f32: f423 3200 bic.w r2, r3, #131072 ; 0x20000
|
|
8000f36: 687b ldr r3, [r7, #4]
|
|
8000f38: 689b ldr r3, [r3, #8]
|
|
8000f3a: 4921 ldr r1, [pc, #132] ; (8000fc0 <HAL_RCC_OscConfig+0x4c4>)
|
|
8000f3c: 4313 orrs r3, r2
|
|
8000f3e: 604b str r3, [r1, #4]
|
|
}
|
|
|
|
/* Configure the main PLL clock source and multiplication factors. */
|
|
__HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
|
|
8000f40: 4b1f ldr r3, [pc, #124] ; (8000fc0 <HAL_RCC_OscConfig+0x4c4>)
|
|
8000f42: 685b ldr r3, [r3, #4]
|
|
8000f44: f423 1274 bic.w r2, r3, #3997696 ; 0x3d0000
|
|
8000f48: 687b ldr r3, [r7, #4]
|
|
8000f4a: 6a19 ldr r1, [r3, #32]
|
|
8000f4c: 687b ldr r3, [r7, #4]
|
|
8000f4e: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
8000f50: 430b orrs r3, r1
|
|
8000f52: 491b ldr r1, [pc, #108] ; (8000fc0 <HAL_RCC_OscConfig+0x4c4>)
|
|
8000f54: 4313 orrs r3, r2
|
|
8000f56: 604b str r3, [r1, #4]
|
|
RCC_OscInitStruct->PLL.PLLMUL);
|
|
/* Enable the main PLL. */
|
|
__HAL_RCC_PLL_ENABLE();
|
|
8000f58: 4b1b ldr r3, [pc, #108] ; (8000fc8 <HAL_RCC_OscConfig+0x4cc>)
|
|
8000f5a: 2201 movs r2, #1
|
|
8000f5c: 601a str r2, [r3, #0]
|
|
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
8000f5e: f7ff fb37 bl 80005d0 <HAL_GetTick>
|
|
8000f62: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till PLL is ready */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
|
|
8000f64: e008 b.n 8000f78 <HAL_RCC_OscConfig+0x47c>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
|
|
8000f66: f7ff fb33 bl 80005d0 <HAL_GetTick>
|
|
8000f6a: 4602 mov r2, r0
|
|
8000f6c: 693b ldr r3, [r7, #16]
|
|
8000f6e: 1ad3 subs r3, r2, r3
|
|
8000f70: 2b02 cmp r3, #2
|
|
8000f72: d901 bls.n 8000f78 <HAL_RCC_OscConfig+0x47c>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8000f74: 2303 movs r3, #3
|
|
8000f76: e03d b.n 8000ff4 <HAL_RCC_OscConfig+0x4f8>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
|
|
8000f78: 4b11 ldr r3, [pc, #68] ; (8000fc0 <HAL_RCC_OscConfig+0x4c4>)
|
|
8000f7a: 681b ldr r3, [r3, #0]
|
|
8000f7c: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
|
|
8000f80: 2b00 cmp r3, #0
|
|
8000f82: d0f0 beq.n 8000f66 <HAL_RCC_OscConfig+0x46a>
|
|
8000f84: e035 b.n 8000ff2 <HAL_RCC_OscConfig+0x4f6>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Disable the main PLL. */
|
|
__HAL_RCC_PLL_DISABLE();
|
|
8000f86: 4b10 ldr r3, [pc, #64] ; (8000fc8 <HAL_RCC_OscConfig+0x4cc>)
|
|
8000f88: 2200 movs r2, #0
|
|
8000f8a: 601a str r2, [r3, #0]
|
|
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
8000f8c: f7ff fb20 bl 80005d0 <HAL_GetTick>
|
|
8000f90: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till PLL is disabled */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
|
|
8000f92: e008 b.n 8000fa6 <HAL_RCC_OscConfig+0x4aa>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
|
|
8000f94: f7ff fb1c bl 80005d0 <HAL_GetTick>
|
|
8000f98: 4602 mov r2, r0
|
|
8000f9a: 693b ldr r3, [r7, #16]
|
|
8000f9c: 1ad3 subs r3, r2, r3
|
|
8000f9e: 2b02 cmp r3, #2
|
|
8000fa0: d901 bls.n 8000fa6 <HAL_RCC_OscConfig+0x4aa>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8000fa2: 2303 movs r3, #3
|
|
8000fa4: e026 b.n 8000ff4 <HAL_RCC_OscConfig+0x4f8>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
|
|
8000fa6: 4b06 ldr r3, [pc, #24] ; (8000fc0 <HAL_RCC_OscConfig+0x4c4>)
|
|
8000fa8: 681b ldr r3, [r3, #0]
|
|
8000faa: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
|
|
8000fae: 2b00 cmp r3, #0
|
|
8000fb0: d1f0 bne.n 8000f94 <HAL_RCC_OscConfig+0x498>
|
|
8000fb2: e01e b.n 8000ff2 <HAL_RCC_OscConfig+0x4f6>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Check if there is a request to disable the PLL used as System clock source */
|
|
if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
|
|
8000fb4: 687b ldr r3, [r7, #4]
|
|
8000fb6: 69db ldr r3, [r3, #28]
|
|
8000fb8: 2b01 cmp r3, #1
|
|
8000fba: d107 bne.n 8000fcc <HAL_RCC_OscConfig+0x4d0>
|
|
{
|
|
return HAL_ERROR;
|
|
8000fbc: 2301 movs r3, #1
|
|
8000fbe: e019 b.n 8000ff4 <HAL_RCC_OscConfig+0x4f8>
|
|
8000fc0: 40021000 .word 0x40021000
|
|
8000fc4: 40007000 .word 0x40007000
|
|
8000fc8: 42420060 .word 0x42420060
|
|
}
|
|
else
|
|
{
|
|
/* Do not return HAL_ERROR if request repeats the current configuration */
|
|
pll_config = RCC->CFGR;
|
|
8000fcc: 4b0b ldr r3, [pc, #44] ; (8000ffc <HAL_RCC_OscConfig+0x500>)
|
|
8000fce: 685b ldr r3, [r3, #4]
|
|
8000fd0: 60fb str r3, [r7, #12]
|
|
if ((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
|
|
8000fd2: 68fb ldr r3, [r7, #12]
|
|
8000fd4: f403 3280 and.w r2, r3, #65536 ; 0x10000
|
|
8000fd8: 687b ldr r3, [r7, #4]
|
|
8000fda: 6a1b ldr r3, [r3, #32]
|
|
8000fdc: 429a cmp r2, r3
|
|
8000fde: d106 bne.n 8000fee <HAL_RCC_OscConfig+0x4f2>
|
|
(READ_BIT(pll_config, RCC_CFGR_PLLMULL) != RCC_OscInitStruct->PLL.PLLMUL))
|
|
8000fe0: 68fb ldr r3, [r7, #12]
|
|
8000fe2: f403 1270 and.w r2, r3, #3932160 ; 0x3c0000
|
|
8000fe6: 687b ldr r3, [r7, #4]
|
|
8000fe8: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
if ((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
|
|
8000fea: 429a cmp r2, r3
|
|
8000fec: d001 beq.n 8000ff2 <HAL_RCC_OscConfig+0x4f6>
|
|
{
|
|
return HAL_ERROR;
|
|
8000fee: 2301 movs r3, #1
|
|
8000ff0: e000 b.n 8000ff4 <HAL_RCC_OscConfig+0x4f8>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
return HAL_OK;
|
|
8000ff2: 2300 movs r3, #0
|
|
}
|
|
8000ff4: 4618 mov r0, r3
|
|
8000ff6: 3718 adds r7, #24
|
|
8000ff8: 46bd mov sp, r7
|
|
8000ffa: bd80 pop {r7, pc}
|
|
8000ffc: 40021000 .word 0x40021000
|
|
|
|
08001000 <HAL_RCC_ClockConfig>:
|
|
* You can use @ref HAL_RCC_GetClockConfig() function to know which clock is
|
|
* currently used as system clock source.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
|
|
{
|
|
8001000: b580 push {r7, lr}
|
|
8001002: b084 sub sp, #16
|
|
8001004: af00 add r7, sp, #0
|
|
8001006: 6078 str r0, [r7, #4]
|
|
8001008: 6039 str r1, [r7, #0]
|
|
uint32_t tickstart;
|
|
|
|
/* Check Null pointer */
|
|
if (RCC_ClkInitStruct == NULL)
|
|
800100a: 687b ldr r3, [r7, #4]
|
|
800100c: 2b00 cmp r3, #0
|
|
800100e: d101 bne.n 8001014 <HAL_RCC_ClockConfig+0x14>
|
|
{
|
|
return HAL_ERROR;
|
|
8001010: 2301 movs r3, #1
|
|
8001012: e0d0 b.n 80011b6 <HAL_RCC_ClockConfig+0x1b6>
|
|
must be correctly programmed according to the frequency of the CPU clock
|
|
(HCLK) of the device. */
|
|
|
|
#if defined(FLASH_ACR_LATENCY)
|
|
/* Increasing the number of wait states because of higher CPU frequency */
|
|
if (FLatency > __HAL_FLASH_GET_LATENCY())
|
|
8001014: 4b6a ldr r3, [pc, #424] ; (80011c0 <HAL_RCC_ClockConfig+0x1c0>)
|
|
8001016: 681b ldr r3, [r3, #0]
|
|
8001018: f003 0307 and.w r3, r3, #7
|
|
800101c: 683a ldr r2, [r7, #0]
|
|
800101e: 429a cmp r2, r3
|
|
8001020: d910 bls.n 8001044 <HAL_RCC_ClockConfig+0x44>
|
|
{
|
|
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
|
|
__HAL_FLASH_SET_LATENCY(FLatency);
|
|
8001022: 4b67 ldr r3, [pc, #412] ; (80011c0 <HAL_RCC_ClockConfig+0x1c0>)
|
|
8001024: 681b ldr r3, [r3, #0]
|
|
8001026: f023 0207 bic.w r2, r3, #7
|
|
800102a: 4965 ldr r1, [pc, #404] ; (80011c0 <HAL_RCC_ClockConfig+0x1c0>)
|
|
800102c: 683b ldr r3, [r7, #0]
|
|
800102e: 4313 orrs r3, r2
|
|
8001030: 600b str r3, [r1, #0]
|
|
|
|
/* Check that the new number of wait states is taken into account to access the Flash
|
|
memory by reading the FLASH_ACR register */
|
|
if (__HAL_FLASH_GET_LATENCY() != FLatency)
|
|
8001032: 4b63 ldr r3, [pc, #396] ; (80011c0 <HAL_RCC_ClockConfig+0x1c0>)
|
|
8001034: 681b ldr r3, [r3, #0]
|
|
8001036: f003 0307 and.w r3, r3, #7
|
|
800103a: 683a ldr r2, [r7, #0]
|
|
800103c: 429a cmp r2, r3
|
|
800103e: d001 beq.n 8001044 <HAL_RCC_ClockConfig+0x44>
|
|
{
|
|
return HAL_ERROR;
|
|
8001040: 2301 movs r3, #1
|
|
8001042: e0b8 b.n 80011b6 <HAL_RCC_ClockConfig+0x1b6>
|
|
}
|
|
}
|
|
|
|
#endif /* FLASH_ACR_LATENCY */
|
|
/*-------------------------- HCLK Configuration --------------------------*/
|
|
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
|
|
8001044: 687b ldr r3, [r7, #4]
|
|
8001046: 681b ldr r3, [r3, #0]
|
|
8001048: f003 0302 and.w r3, r3, #2
|
|
800104c: 2b00 cmp r3, #0
|
|
800104e: d020 beq.n 8001092 <HAL_RCC_ClockConfig+0x92>
|
|
{
|
|
/* Set the highest APBx dividers in order to ensure that we do not go through
|
|
a non-spec phase whatever we decrease or increase HCLK. */
|
|
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
|
|
8001050: 687b ldr r3, [r7, #4]
|
|
8001052: 681b ldr r3, [r3, #0]
|
|
8001054: f003 0304 and.w r3, r3, #4
|
|
8001058: 2b00 cmp r3, #0
|
|
800105a: d005 beq.n 8001068 <HAL_RCC_ClockConfig+0x68>
|
|
{
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16);
|
|
800105c: 4b59 ldr r3, [pc, #356] ; (80011c4 <HAL_RCC_ClockConfig+0x1c4>)
|
|
800105e: 685b ldr r3, [r3, #4]
|
|
8001060: 4a58 ldr r2, [pc, #352] ; (80011c4 <HAL_RCC_ClockConfig+0x1c4>)
|
|
8001062: f443 63e0 orr.w r3, r3, #1792 ; 0x700
|
|
8001066: 6053 str r3, [r2, #4]
|
|
}
|
|
|
|
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
|
|
8001068: 687b ldr r3, [r7, #4]
|
|
800106a: 681b ldr r3, [r3, #0]
|
|
800106c: f003 0308 and.w r3, r3, #8
|
|
8001070: 2b00 cmp r3, #0
|
|
8001072: d005 beq.n 8001080 <HAL_RCC_ClockConfig+0x80>
|
|
{
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3));
|
|
8001074: 4b53 ldr r3, [pc, #332] ; (80011c4 <HAL_RCC_ClockConfig+0x1c4>)
|
|
8001076: 685b ldr r3, [r3, #4]
|
|
8001078: 4a52 ldr r2, [pc, #328] ; (80011c4 <HAL_RCC_ClockConfig+0x1c4>)
|
|
800107a: f443 5360 orr.w r3, r3, #14336 ; 0x3800
|
|
800107e: 6053 str r3, [r2, #4]
|
|
}
|
|
|
|
/* Set the new HCLK clock divider */
|
|
assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
|
|
8001080: 4b50 ldr r3, [pc, #320] ; (80011c4 <HAL_RCC_ClockConfig+0x1c4>)
|
|
8001082: 685b ldr r3, [r3, #4]
|
|
8001084: f023 02f0 bic.w r2, r3, #240 ; 0xf0
|
|
8001088: 687b ldr r3, [r7, #4]
|
|
800108a: 689b ldr r3, [r3, #8]
|
|
800108c: 494d ldr r1, [pc, #308] ; (80011c4 <HAL_RCC_ClockConfig+0x1c4>)
|
|
800108e: 4313 orrs r3, r2
|
|
8001090: 604b str r3, [r1, #4]
|
|
}
|
|
|
|
/*------------------------- SYSCLK Configuration ---------------------------*/
|
|
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
|
|
8001092: 687b ldr r3, [r7, #4]
|
|
8001094: 681b ldr r3, [r3, #0]
|
|
8001096: f003 0301 and.w r3, r3, #1
|
|
800109a: 2b00 cmp r3, #0
|
|
800109c: d040 beq.n 8001120 <HAL_RCC_ClockConfig+0x120>
|
|
{
|
|
assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
|
|
|
|
/* HSE is selected as System Clock Source */
|
|
if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
|
|
800109e: 687b ldr r3, [r7, #4]
|
|
80010a0: 685b ldr r3, [r3, #4]
|
|
80010a2: 2b01 cmp r3, #1
|
|
80010a4: d107 bne.n 80010b6 <HAL_RCC_ClockConfig+0xb6>
|
|
{
|
|
/* Check the HSE ready flag */
|
|
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
|
|
80010a6: 4b47 ldr r3, [pc, #284] ; (80011c4 <HAL_RCC_ClockConfig+0x1c4>)
|
|
80010a8: 681b ldr r3, [r3, #0]
|
|
80010aa: f403 3300 and.w r3, r3, #131072 ; 0x20000
|
|
80010ae: 2b00 cmp r3, #0
|
|
80010b0: d115 bne.n 80010de <HAL_RCC_ClockConfig+0xde>
|
|
{
|
|
return HAL_ERROR;
|
|
80010b2: 2301 movs r3, #1
|
|
80010b4: e07f b.n 80011b6 <HAL_RCC_ClockConfig+0x1b6>
|
|
}
|
|
}
|
|
/* PLL is selected as System Clock Source */
|
|
else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
|
|
80010b6: 687b ldr r3, [r7, #4]
|
|
80010b8: 685b ldr r3, [r3, #4]
|
|
80010ba: 2b02 cmp r3, #2
|
|
80010bc: d107 bne.n 80010ce <HAL_RCC_ClockConfig+0xce>
|
|
{
|
|
/* Check the PLL ready flag */
|
|
if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
|
|
80010be: 4b41 ldr r3, [pc, #260] ; (80011c4 <HAL_RCC_ClockConfig+0x1c4>)
|
|
80010c0: 681b ldr r3, [r3, #0]
|
|
80010c2: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
|
|
80010c6: 2b00 cmp r3, #0
|
|
80010c8: d109 bne.n 80010de <HAL_RCC_ClockConfig+0xde>
|
|
{
|
|
return HAL_ERROR;
|
|
80010ca: 2301 movs r3, #1
|
|
80010cc: e073 b.n 80011b6 <HAL_RCC_ClockConfig+0x1b6>
|
|
}
|
|
/* HSI is selected as System Clock Source */
|
|
else
|
|
{
|
|
/* Check the HSI ready flag */
|
|
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
|
|
80010ce: 4b3d ldr r3, [pc, #244] ; (80011c4 <HAL_RCC_ClockConfig+0x1c4>)
|
|
80010d0: 681b ldr r3, [r3, #0]
|
|
80010d2: f003 0302 and.w r3, r3, #2
|
|
80010d6: 2b00 cmp r3, #0
|
|
80010d8: d101 bne.n 80010de <HAL_RCC_ClockConfig+0xde>
|
|
{
|
|
return HAL_ERROR;
|
|
80010da: 2301 movs r3, #1
|
|
80010dc: e06b b.n 80011b6 <HAL_RCC_ClockConfig+0x1b6>
|
|
}
|
|
}
|
|
__HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
|
|
80010de: 4b39 ldr r3, [pc, #228] ; (80011c4 <HAL_RCC_ClockConfig+0x1c4>)
|
|
80010e0: 685b ldr r3, [r3, #4]
|
|
80010e2: f023 0203 bic.w r2, r3, #3
|
|
80010e6: 687b ldr r3, [r7, #4]
|
|
80010e8: 685b ldr r3, [r3, #4]
|
|
80010ea: 4936 ldr r1, [pc, #216] ; (80011c4 <HAL_RCC_ClockConfig+0x1c4>)
|
|
80010ec: 4313 orrs r3, r2
|
|
80010ee: 604b str r3, [r1, #4]
|
|
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
80010f0: f7ff fa6e bl 80005d0 <HAL_GetTick>
|
|
80010f4: 60f8 str r0, [r7, #12]
|
|
|
|
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
|
|
80010f6: e00a b.n 800110e <HAL_RCC_ClockConfig+0x10e>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
|
|
80010f8: f7ff fa6a bl 80005d0 <HAL_GetTick>
|
|
80010fc: 4602 mov r2, r0
|
|
80010fe: 68fb ldr r3, [r7, #12]
|
|
8001100: 1ad3 subs r3, r2, r3
|
|
8001102: f241 3288 movw r2, #5000 ; 0x1388
|
|
8001106: 4293 cmp r3, r2
|
|
8001108: d901 bls.n 800110e <HAL_RCC_ClockConfig+0x10e>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
800110a: 2303 movs r3, #3
|
|
800110c: e053 b.n 80011b6 <HAL_RCC_ClockConfig+0x1b6>
|
|
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
|
|
800110e: 4b2d ldr r3, [pc, #180] ; (80011c4 <HAL_RCC_ClockConfig+0x1c4>)
|
|
8001110: 685b ldr r3, [r3, #4]
|
|
8001112: f003 020c and.w r2, r3, #12
|
|
8001116: 687b ldr r3, [r7, #4]
|
|
8001118: 685b ldr r3, [r3, #4]
|
|
800111a: 009b lsls r3, r3, #2
|
|
800111c: 429a cmp r2, r3
|
|
800111e: d1eb bne.n 80010f8 <HAL_RCC_ClockConfig+0xf8>
|
|
}
|
|
}
|
|
|
|
#if defined(FLASH_ACR_LATENCY)
|
|
/* Decreasing the number of wait states because of lower CPU frequency */
|
|
if (FLatency < __HAL_FLASH_GET_LATENCY())
|
|
8001120: 4b27 ldr r3, [pc, #156] ; (80011c0 <HAL_RCC_ClockConfig+0x1c0>)
|
|
8001122: 681b ldr r3, [r3, #0]
|
|
8001124: f003 0307 and.w r3, r3, #7
|
|
8001128: 683a ldr r2, [r7, #0]
|
|
800112a: 429a cmp r2, r3
|
|
800112c: d210 bcs.n 8001150 <HAL_RCC_ClockConfig+0x150>
|
|
{
|
|
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
|
|
__HAL_FLASH_SET_LATENCY(FLatency);
|
|
800112e: 4b24 ldr r3, [pc, #144] ; (80011c0 <HAL_RCC_ClockConfig+0x1c0>)
|
|
8001130: 681b ldr r3, [r3, #0]
|
|
8001132: f023 0207 bic.w r2, r3, #7
|
|
8001136: 4922 ldr r1, [pc, #136] ; (80011c0 <HAL_RCC_ClockConfig+0x1c0>)
|
|
8001138: 683b ldr r3, [r7, #0]
|
|
800113a: 4313 orrs r3, r2
|
|
800113c: 600b str r3, [r1, #0]
|
|
|
|
/* Check that the new number of wait states is taken into account to access the Flash
|
|
memory by reading the FLASH_ACR register */
|
|
if (__HAL_FLASH_GET_LATENCY() != FLatency)
|
|
800113e: 4b20 ldr r3, [pc, #128] ; (80011c0 <HAL_RCC_ClockConfig+0x1c0>)
|
|
8001140: 681b ldr r3, [r3, #0]
|
|
8001142: f003 0307 and.w r3, r3, #7
|
|
8001146: 683a ldr r2, [r7, #0]
|
|
8001148: 429a cmp r2, r3
|
|
800114a: d001 beq.n 8001150 <HAL_RCC_ClockConfig+0x150>
|
|
{
|
|
return HAL_ERROR;
|
|
800114c: 2301 movs r3, #1
|
|
800114e: e032 b.n 80011b6 <HAL_RCC_ClockConfig+0x1b6>
|
|
}
|
|
}
|
|
#endif /* FLASH_ACR_LATENCY */
|
|
|
|
/*-------------------------- PCLK1 Configuration ---------------------------*/
|
|
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
|
|
8001150: 687b ldr r3, [r7, #4]
|
|
8001152: 681b ldr r3, [r3, #0]
|
|
8001154: f003 0304 and.w r3, r3, #4
|
|
8001158: 2b00 cmp r3, #0
|
|
800115a: d008 beq.n 800116e <HAL_RCC_ClockConfig+0x16e>
|
|
{
|
|
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
|
|
800115c: 4b19 ldr r3, [pc, #100] ; (80011c4 <HAL_RCC_ClockConfig+0x1c4>)
|
|
800115e: 685b ldr r3, [r3, #4]
|
|
8001160: f423 62e0 bic.w r2, r3, #1792 ; 0x700
|
|
8001164: 687b ldr r3, [r7, #4]
|
|
8001166: 68db ldr r3, [r3, #12]
|
|
8001168: 4916 ldr r1, [pc, #88] ; (80011c4 <HAL_RCC_ClockConfig+0x1c4>)
|
|
800116a: 4313 orrs r3, r2
|
|
800116c: 604b str r3, [r1, #4]
|
|
}
|
|
|
|
/*-------------------------- PCLK2 Configuration ---------------------------*/
|
|
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
|
|
800116e: 687b ldr r3, [r7, #4]
|
|
8001170: 681b ldr r3, [r3, #0]
|
|
8001172: f003 0308 and.w r3, r3, #8
|
|
8001176: 2b00 cmp r3, #0
|
|
8001178: d009 beq.n 800118e <HAL_RCC_ClockConfig+0x18e>
|
|
{
|
|
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3));
|
|
800117a: 4b12 ldr r3, [pc, #72] ; (80011c4 <HAL_RCC_ClockConfig+0x1c4>)
|
|
800117c: 685b ldr r3, [r3, #4]
|
|
800117e: f423 5260 bic.w r2, r3, #14336 ; 0x3800
|
|
8001182: 687b ldr r3, [r7, #4]
|
|
8001184: 691b ldr r3, [r3, #16]
|
|
8001186: 00db lsls r3, r3, #3
|
|
8001188: 490e ldr r1, [pc, #56] ; (80011c4 <HAL_RCC_ClockConfig+0x1c4>)
|
|
800118a: 4313 orrs r3, r2
|
|
800118c: 604b str r3, [r1, #4]
|
|
}
|
|
|
|
/* Update the SystemCoreClock global variable */
|
|
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos];
|
|
800118e: f000 f821 bl 80011d4 <HAL_RCC_GetSysClockFreq>
|
|
8001192: 4602 mov r2, r0
|
|
8001194: 4b0b ldr r3, [pc, #44] ; (80011c4 <HAL_RCC_ClockConfig+0x1c4>)
|
|
8001196: 685b ldr r3, [r3, #4]
|
|
8001198: 091b lsrs r3, r3, #4
|
|
800119a: f003 030f and.w r3, r3, #15
|
|
800119e: 490a ldr r1, [pc, #40] ; (80011c8 <HAL_RCC_ClockConfig+0x1c8>)
|
|
80011a0: 5ccb ldrb r3, [r1, r3]
|
|
80011a2: fa22 f303 lsr.w r3, r2, r3
|
|
80011a6: 4a09 ldr r2, [pc, #36] ; (80011cc <HAL_RCC_ClockConfig+0x1cc>)
|
|
80011a8: 6013 str r3, [r2, #0]
|
|
|
|
/* Configure the source of time base considering new system clocks settings*/
|
|
HAL_InitTick(uwTickPrio);
|
|
80011aa: 4b09 ldr r3, [pc, #36] ; (80011d0 <HAL_RCC_ClockConfig+0x1d0>)
|
|
80011ac: 681b ldr r3, [r3, #0]
|
|
80011ae: 4618 mov r0, r3
|
|
80011b0: f7ff f9cc bl 800054c <HAL_InitTick>
|
|
|
|
return HAL_OK;
|
|
80011b4: 2300 movs r3, #0
|
|
}
|
|
80011b6: 4618 mov r0, r3
|
|
80011b8: 3710 adds r7, #16
|
|
80011ba: 46bd mov sp, r7
|
|
80011bc: bd80 pop {r7, pc}
|
|
80011be: bf00 nop
|
|
80011c0: 40022000 .word 0x40022000
|
|
80011c4: 40021000 .word 0x40021000
|
|
80011c8: 08001ee8 .word 0x08001ee8
|
|
80011cc: 20000000 .word 0x20000000
|
|
80011d0: 20000004 .word 0x20000004
|
|
|
|
080011d4 <HAL_RCC_GetSysClockFreq>:
|
|
* right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
|
|
*
|
|
* @retval SYSCLK frequency
|
|
*/
|
|
uint32_t HAL_RCC_GetSysClockFreq(void)
|
|
{
|
|
80011d4: b490 push {r4, r7}
|
|
80011d6: b08a sub sp, #40 ; 0x28
|
|
80011d8: af00 add r7, sp, #0
|
|
#if defined(RCC_CFGR2_PREDIV1SRC)
|
|
const uint8_t aPLLMULFactorTable[14] = {0, 0, 4, 5, 6, 7, 8, 9, 0, 0, 0, 0, 0, 13};
|
|
const uint8_t aPredivFactorTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16};
|
|
#else
|
|
const uint8_t aPLLMULFactorTable[16] = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16};
|
|
80011da: 4b29 ldr r3, [pc, #164] ; (8001280 <HAL_RCC_GetSysClockFreq+0xac>)
|
|
80011dc: 1d3c adds r4, r7, #4
|
|
80011de: cb0f ldmia r3, {r0, r1, r2, r3}
|
|
80011e0: e884 000f stmia.w r4, {r0, r1, r2, r3}
|
|
#if defined(RCC_CFGR2_PREDIV1)
|
|
const uint8_t aPredivFactorTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16};
|
|
#else
|
|
const uint8_t aPredivFactorTable[2] = {1, 2};
|
|
80011e4: f240 2301 movw r3, #513 ; 0x201
|
|
80011e8: 803b strh r3, [r7, #0]
|
|
#endif /*RCC_CFGR2_PREDIV1*/
|
|
|
|
#endif
|
|
uint32_t tmpreg = 0U, prediv = 0U, pllclk = 0U, pllmul = 0U;
|
|
80011ea: 2300 movs r3, #0
|
|
80011ec: 61fb str r3, [r7, #28]
|
|
80011ee: 2300 movs r3, #0
|
|
80011f0: 61bb str r3, [r7, #24]
|
|
80011f2: 2300 movs r3, #0
|
|
80011f4: 627b str r3, [r7, #36] ; 0x24
|
|
80011f6: 2300 movs r3, #0
|
|
80011f8: 617b str r3, [r7, #20]
|
|
uint32_t sysclockfreq = 0U;
|
|
80011fa: 2300 movs r3, #0
|
|
80011fc: 623b str r3, [r7, #32]
|
|
#if defined(RCC_CFGR2_PREDIV1SRC)
|
|
uint32_t prediv2 = 0U, pll2mul = 0U;
|
|
#endif /*RCC_CFGR2_PREDIV1SRC*/
|
|
|
|
tmpreg = RCC->CFGR;
|
|
80011fe: 4b21 ldr r3, [pc, #132] ; (8001284 <HAL_RCC_GetSysClockFreq+0xb0>)
|
|
8001200: 685b ldr r3, [r3, #4]
|
|
8001202: 61fb str r3, [r7, #28]
|
|
|
|
/* Get SYSCLK source -------------------------------------------------------*/
|
|
switch (tmpreg & RCC_CFGR_SWS)
|
|
8001204: 69fb ldr r3, [r7, #28]
|
|
8001206: f003 030c and.w r3, r3, #12
|
|
800120a: 2b04 cmp r3, #4
|
|
800120c: d002 beq.n 8001214 <HAL_RCC_GetSysClockFreq+0x40>
|
|
800120e: 2b08 cmp r3, #8
|
|
8001210: d003 beq.n 800121a <HAL_RCC_GetSysClockFreq+0x46>
|
|
8001212: e02b b.n 800126c <HAL_RCC_GetSysClockFreq+0x98>
|
|
{
|
|
case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */
|
|
{
|
|
sysclockfreq = HSE_VALUE;
|
|
8001214: 4b1c ldr r3, [pc, #112] ; (8001288 <HAL_RCC_GetSysClockFreq+0xb4>)
|
|
8001216: 623b str r3, [r7, #32]
|
|
break;
|
|
8001218: e02b b.n 8001272 <HAL_RCC_GetSysClockFreq+0x9e>
|
|
}
|
|
case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */
|
|
{
|
|
pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos];
|
|
800121a: 69fb ldr r3, [r7, #28]
|
|
800121c: 0c9b lsrs r3, r3, #18
|
|
800121e: f003 030f and.w r3, r3, #15
|
|
8001222: 3328 adds r3, #40 ; 0x28
|
|
8001224: 443b add r3, r7
|
|
8001226: f813 3c24 ldrb.w r3, [r3, #-36]
|
|
800122a: 617b str r3, [r7, #20]
|
|
if ((tmpreg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2)
|
|
800122c: 69fb ldr r3, [r7, #28]
|
|
800122e: f403 3380 and.w r3, r3, #65536 ; 0x10000
|
|
8001232: 2b00 cmp r3, #0
|
|
8001234: d012 beq.n 800125c <HAL_RCC_GetSysClockFreq+0x88>
|
|
{
|
|
#if defined(RCC_CFGR2_PREDIV1)
|
|
prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> RCC_CFGR2_PREDIV1_Pos];
|
|
#else
|
|
prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos];
|
|
8001236: 4b13 ldr r3, [pc, #76] ; (8001284 <HAL_RCC_GetSysClockFreq+0xb0>)
|
|
8001238: 685b ldr r3, [r3, #4]
|
|
800123a: 0c5b lsrs r3, r3, #17
|
|
800123c: f003 0301 and.w r3, r3, #1
|
|
8001240: 3328 adds r3, #40 ; 0x28
|
|
8001242: 443b add r3, r7
|
|
8001244: f813 3c28 ldrb.w r3, [r3, #-40]
|
|
8001248: 61bb str r3, [r7, #24]
|
|
{
|
|
pllclk = pllclk / 2;
|
|
}
|
|
#else
|
|
/* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */
|
|
pllclk = (uint32_t)((HSE_VALUE * pllmul) / prediv);
|
|
800124a: 697b ldr r3, [r7, #20]
|
|
800124c: 4a0e ldr r2, [pc, #56] ; (8001288 <HAL_RCC_GetSysClockFreq+0xb4>)
|
|
800124e: fb03 f202 mul.w r2, r3, r2
|
|
8001252: 69bb ldr r3, [r7, #24]
|
|
8001254: fbb2 f3f3 udiv r3, r2, r3
|
|
8001258: 627b str r3, [r7, #36] ; 0x24
|
|
800125a: e004 b.n 8001266 <HAL_RCC_GetSysClockFreq+0x92>
|
|
#endif /*RCC_CFGR2_PREDIV1SRC*/
|
|
}
|
|
else
|
|
{
|
|
/* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */
|
|
pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul);
|
|
800125c: 697b ldr r3, [r7, #20]
|
|
800125e: 4a0b ldr r2, [pc, #44] ; (800128c <HAL_RCC_GetSysClockFreq+0xb8>)
|
|
8001260: fb02 f303 mul.w r3, r2, r3
|
|
8001264: 627b str r3, [r7, #36] ; 0x24
|
|
}
|
|
sysclockfreq = pllclk;
|
|
8001266: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
8001268: 623b str r3, [r7, #32]
|
|
break;
|
|
800126a: e002 b.n 8001272 <HAL_RCC_GetSysClockFreq+0x9e>
|
|
}
|
|
case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
|
|
default: /* HSI used as system clock */
|
|
{
|
|
sysclockfreq = HSI_VALUE;
|
|
800126c: 4b06 ldr r3, [pc, #24] ; (8001288 <HAL_RCC_GetSysClockFreq+0xb4>)
|
|
800126e: 623b str r3, [r7, #32]
|
|
break;
|
|
8001270: bf00 nop
|
|
}
|
|
}
|
|
return sysclockfreq;
|
|
8001272: 6a3b ldr r3, [r7, #32]
|
|
}
|
|
8001274: 4618 mov r0, r3
|
|
8001276: 3728 adds r7, #40 ; 0x28
|
|
8001278: 46bd mov sp, r7
|
|
800127a: bc90 pop {r4, r7}
|
|
800127c: 4770 bx lr
|
|
800127e: bf00 nop
|
|
8001280: 08001ed8 .word 0x08001ed8
|
|
8001284: 40021000 .word 0x40021000
|
|
8001288: 007a1200 .word 0x007a1200
|
|
800128c: 003d0900 .word 0x003d0900
|
|
|
|
08001290 <RCC_Delay>:
|
|
* @brief This function provides delay (in milliseconds) based on CPU cycles method.
|
|
* @param mdelay: specifies the delay time length, in milliseconds.
|
|
* @retval None
|
|
*/
|
|
static void RCC_Delay(uint32_t mdelay)
|
|
{
|
|
8001290: b480 push {r7}
|
|
8001292: b085 sub sp, #20
|
|
8001294: af00 add r7, sp, #0
|
|
8001296: 6078 str r0, [r7, #4]
|
|
__IO uint32_t Delay = mdelay * (SystemCoreClock / 8U / 1000U);
|
|
8001298: 4b0a ldr r3, [pc, #40] ; (80012c4 <RCC_Delay+0x34>)
|
|
800129a: 681b ldr r3, [r3, #0]
|
|
800129c: 4a0a ldr r2, [pc, #40] ; (80012c8 <RCC_Delay+0x38>)
|
|
800129e: fba2 2303 umull r2, r3, r2, r3
|
|
80012a2: 0a5b lsrs r3, r3, #9
|
|
80012a4: 687a ldr r2, [r7, #4]
|
|
80012a6: fb02 f303 mul.w r3, r2, r3
|
|
80012aa: 60fb str r3, [r7, #12]
|
|
do
|
|
{
|
|
__NOP();
|
|
80012ac: bf00 nop
|
|
}
|
|
while (Delay --);
|
|
80012ae: 68fb ldr r3, [r7, #12]
|
|
80012b0: 1e5a subs r2, r3, #1
|
|
80012b2: 60fa str r2, [r7, #12]
|
|
80012b4: 2b00 cmp r3, #0
|
|
80012b6: d1f9 bne.n 80012ac <RCC_Delay+0x1c>
|
|
}
|
|
80012b8: bf00 nop
|
|
80012ba: bf00 nop
|
|
80012bc: 3714 adds r7, #20
|
|
80012be: 46bd mov sp, r7
|
|
80012c0: bc80 pop {r7}
|
|
80012c2: 4770 bx lr
|
|
80012c4: 20000000 .word 0x20000000
|
|
80012c8: 10624dd3 .word 0x10624dd3
|
|
|
|
080012cc <HAL_TIM_Base_Init>:
|
|
* Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
|
|
* @param htim TIM Base handle
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
|
|
{
|
|
80012cc: b580 push {r7, lr}
|
|
80012ce: b082 sub sp, #8
|
|
80012d0: af00 add r7, sp, #0
|
|
80012d2: 6078 str r0, [r7, #4]
|
|
/* Check the TIM handle allocation */
|
|
if (htim == NULL)
|
|
80012d4: 687b ldr r3, [r7, #4]
|
|
80012d6: 2b00 cmp r3, #0
|
|
80012d8: d101 bne.n 80012de <HAL_TIM_Base_Init+0x12>
|
|
{
|
|
return HAL_ERROR;
|
|
80012da: 2301 movs r3, #1
|
|
80012dc: e041 b.n 8001362 <HAL_TIM_Base_Init+0x96>
|
|
assert_param(IS_TIM_INSTANCE(htim->Instance));
|
|
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
|
|
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
|
|
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
|
|
|
|
if (htim->State == HAL_TIM_STATE_RESET)
|
|
80012de: 687b ldr r3, [r7, #4]
|
|
80012e0: f893 303d ldrb.w r3, [r3, #61] ; 0x3d
|
|
80012e4: b2db uxtb r3, r3
|
|
80012e6: 2b00 cmp r3, #0
|
|
80012e8: d106 bne.n 80012f8 <HAL_TIM_Base_Init+0x2c>
|
|
{
|
|
/* Allocate lock resource and initialize it */
|
|
htim->Lock = HAL_UNLOCKED;
|
|
80012ea: 687b ldr r3, [r7, #4]
|
|
80012ec: 2200 movs r2, #0
|
|
80012ee: f883 203c strb.w r2, [r3, #60] ; 0x3c
|
|
}
|
|
/* Init the low level hardware : GPIO, CLOCK, NVIC */
|
|
htim->Base_MspInitCallback(htim);
|
|
#else
|
|
/* Init the low level hardware : GPIO, CLOCK, NVIC */
|
|
HAL_TIM_Base_MspInit(htim);
|
|
80012f2: 6878 ldr r0, [r7, #4]
|
|
80012f4: f7ff f89c bl 8000430 <HAL_TIM_Base_MspInit>
|
|
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
|
|
}
|
|
|
|
/* Set the TIM state */
|
|
htim->State = HAL_TIM_STATE_BUSY;
|
|
80012f8: 687b ldr r3, [r7, #4]
|
|
80012fa: 2202 movs r2, #2
|
|
80012fc: f883 203d strb.w r2, [r3, #61] ; 0x3d
|
|
|
|
/* Set the Time Base configuration */
|
|
TIM_Base_SetConfig(htim->Instance, &htim->Init);
|
|
8001300: 687b ldr r3, [r7, #4]
|
|
8001302: 681a ldr r2, [r3, #0]
|
|
8001304: 687b ldr r3, [r7, #4]
|
|
8001306: 3304 adds r3, #4
|
|
8001308: 4619 mov r1, r3
|
|
800130a: 4610 mov r0, r2
|
|
800130c: f000 faaa bl 8001864 <TIM_Base_SetConfig>
|
|
|
|
/* Initialize the DMA burst operation state */
|
|
htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
|
|
8001310: 687b ldr r3, [r7, #4]
|
|
8001312: 2201 movs r2, #1
|
|
8001314: f883 2046 strb.w r2, [r3, #70] ; 0x46
|
|
|
|
/* Initialize the TIM channels state */
|
|
TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
|
|
8001318: 687b ldr r3, [r7, #4]
|
|
800131a: 2201 movs r2, #1
|
|
800131c: f883 203e strb.w r2, [r3, #62] ; 0x3e
|
|
8001320: 687b ldr r3, [r7, #4]
|
|
8001322: 2201 movs r2, #1
|
|
8001324: f883 203f strb.w r2, [r3, #63] ; 0x3f
|
|
8001328: 687b ldr r3, [r7, #4]
|
|
800132a: 2201 movs r2, #1
|
|
800132c: f883 2040 strb.w r2, [r3, #64] ; 0x40
|
|
8001330: 687b ldr r3, [r7, #4]
|
|
8001332: 2201 movs r2, #1
|
|
8001334: f883 2041 strb.w r2, [r3, #65] ; 0x41
|
|
TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
|
|
8001338: 687b ldr r3, [r7, #4]
|
|
800133a: 2201 movs r2, #1
|
|
800133c: f883 2042 strb.w r2, [r3, #66] ; 0x42
|
|
8001340: 687b ldr r3, [r7, #4]
|
|
8001342: 2201 movs r2, #1
|
|
8001344: f883 2043 strb.w r2, [r3, #67] ; 0x43
|
|
8001348: 687b ldr r3, [r7, #4]
|
|
800134a: 2201 movs r2, #1
|
|
800134c: f883 2044 strb.w r2, [r3, #68] ; 0x44
|
|
8001350: 687b ldr r3, [r7, #4]
|
|
8001352: 2201 movs r2, #1
|
|
8001354: f883 2045 strb.w r2, [r3, #69] ; 0x45
|
|
|
|
/* Initialize the TIM state*/
|
|
htim->State = HAL_TIM_STATE_READY;
|
|
8001358: 687b ldr r3, [r7, #4]
|
|
800135a: 2201 movs r2, #1
|
|
800135c: f883 203d strb.w r2, [r3, #61] ; 0x3d
|
|
|
|
return HAL_OK;
|
|
8001360: 2300 movs r3, #0
|
|
}
|
|
8001362: 4618 mov r0, r3
|
|
8001364: 3708 adds r7, #8
|
|
8001366: 46bd mov sp, r7
|
|
8001368: bd80 pop {r7, pc}
|
|
|
|
0800136a <HAL_TIM_PWM_Init>:
|
|
* Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init()
|
|
* @param htim TIM PWM handle
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
|
|
{
|
|
800136a: b580 push {r7, lr}
|
|
800136c: b082 sub sp, #8
|
|
800136e: af00 add r7, sp, #0
|
|
8001370: 6078 str r0, [r7, #4]
|
|
/* Check the TIM handle allocation */
|
|
if (htim == NULL)
|
|
8001372: 687b ldr r3, [r7, #4]
|
|
8001374: 2b00 cmp r3, #0
|
|
8001376: d101 bne.n 800137c <HAL_TIM_PWM_Init+0x12>
|
|
{
|
|
return HAL_ERROR;
|
|
8001378: 2301 movs r3, #1
|
|
800137a: e041 b.n 8001400 <HAL_TIM_PWM_Init+0x96>
|
|
assert_param(IS_TIM_INSTANCE(htim->Instance));
|
|
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
|
|
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
|
|
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
|
|
|
|
if (htim->State == HAL_TIM_STATE_RESET)
|
|
800137c: 687b ldr r3, [r7, #4]
|
|
800137e: f893 303d ldrb.w r3, [r3, #61] ; 0x3d
|
|
8001382: b2db uxtb r3, r3
|
|
8001384: 2b00 cmp r3, #0
|
|
8001386: d106 bne.n 8001396 <HAL_TIM_PWM_Init+0x2c>
|
|
{
|
|
/* Allocate lock resource and initialize it */
|
|
htim->Lock = HAL_UNLOCKED;
|
|
8001388: 687b ldr r3, [r7, #4]
|
|
800138a: 2200 movs r2, #0
|
|
800138c: f883 203c strb.w r2, [r3, #60] ; 0x3c
|
|
}
|
|
/* Init the low level hardware : GPIO, CLOCK, NVIC */
|
|
htim->PWM_MspInitCallback(htim);
|
|
#else
|
|
/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
|
|
HAL_TIM_PWM_MspInit(htim);
|
|
8001390: 6878 ldr r0, [r7, #4]
|
|
8001392: f000 f839 bl 8001408 <HAL_TIM_PWM_MspInit>
|
|
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
|
|
}
|
|
|
|
/* Set the TIM state */
|
|
htim->State = HAL_TIM_STATE_BUSY;
|
|
8001396: 687b ldr r3, [r7, #4]
|
|
8001398: 2202 movs r2, #2
|
|
800139a: f883 203d strb.w r2, [r3, #61] ; 0x3d
|
|
|
|
/* Init the base time for the PWM */
|
|
TIM_Base_SetConfig(htim->Instance, &htim->Init);
|
|
800139e: 687b ldr r3, [r7, #4]
|
|
80013a0: 681a ldr r2, [r3, #0]
|
|
80013a2: 687b ldr r3, [r7, #4]
|
|
80013a4: 3304 adds r3, #4
|
|
80013a6: 4619 mov r1, r3
|
|
80013a8: 4610 mov r0, r2
|
|
80013aa: f000 fa5b bl 8001864 <TIM_Base_SetConfig>
|
|
|
|
/* Initialize the DMA burst operation state */
|
|
htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
|
|
80013ae: 687b ldr r3, [r7, #4]
|
|
80013b0: 2201 movs r2, #1
|
|
80013b2: f883 2046 strb.w r2, [r3, #70] ; 0x46
|
|
|
|
/* Initialize the TIM channels state */
|
|
TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
|
|
80013b6: 687b ldr r3, [r7, #4]
|
|
80013b8: 2201 movs r2, #1
|
|
80013ba: f883 203e strb.w r2, [r3, #62] ; 0x3e
|
|
80013be: 687b ldr r3, [r7, #4]
|
|
80013c0: 2201 movs r2, #1
|
|
80013c2: f883 203f strb.w r2, [r3, #63] ; 0x3f
|
|
80013c6: 687b ldr r3, [r7, #4]
|
|
80013c8: 2201 movs r2, #1
|
|
80013ca: f883 2040 strb.w r2, [r3, #64] ; 0x40
|
|
80013ce: 687b ldr r3, [r7, #4]
|
|
80013d0: 2201 movs r2, #1
|
|
80013d2: f883 2041 strb.w r2, [r3, #65] ; 0x41
|
|
TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
|
|
80013d6: 687b ldr r3, [r7, #4]
|
|
80013d8: 2201 movs r2, #1
|
|
80013da: f883 2042 strb.w r2, [r3, #66] ; 0x42
|
|
80013de: 687b ldr r3, [r7, #4]
|
|
80013e0: 2201 movs r2, #1
|
|
80013e2: f883 2043 strb.w r2, [r3, #67] ; 0x43
|
|
80013e6: 687b ldr r3, [r7, #4]
|
|
80013e8: 2201 movs r2, #1
|
|
80013ea: f883 2044 strb.w r2, [r3, #68] ; 0x44
|
|
80013ee: 687b ldr r3, [r7, #4]
|
|
80013f0: 2201 movs r2, #1
|
|
80013f2: f883 2045 strb.w r2, [r3, #69] ; 0x45
|
|
|
|
/* Initialize the TIM state*/
|
|
htim->State = HAL_TIM_STATE_READY;
|
|
80013f6: 687b ldr r3, [r7, #4]
|
|
80013f8: 2201 movs r2, #1
|
|
80013fa: f883 203d strb.w r2, [r3, #61] ; 0x3d
|
|
|
|
return HAL_OK;
|
|
80013fe: 2300 movs r3, #0
|
|
}
|
|
8001400: 4618 mov r0, r3
|
|
8001402: 3708 adds r7, #8
|
|
8001404: 46bd mov sp, r7
|
|
8001406: bd80 pop {r7, pc}
|
|
|
|
08001408 <HAL_TIM_PWM_MspInit>:
|
|
* @brief Initializes the TIM PWM MSP.
|
|
* @param htim TIM PWM handle
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
|
|
{
|
|
8001408: b480 push {r7}
|
|
800140a: b083 sub sp, #12
|
|
800140c: af00 add r7, sp, #0
|
|
800140e: 6078 str r0, [r7, #4]
|
|
UNUSED(htim);
|
|
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
|
the HAL_TIM_PWM_MspInit could be implemented in the user file
|
|
*/
|
|
}
|
|
8001410: bf00 nop
|
|
8001412: 370c adds r7, #12
|
|
8001414: 46bd mov sp, r7
|
|
8001416: bc80 pop {r7}
|
|
8001418: 4770 bx lr
|
|
...
|
|
|
|
0800141c <HAL_TIM_PWM_Start>:
|
|
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
|
|
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
|
|
{
|
|
800141c: b580 push {r7, lr}
|
|
800141e: b084 sub sp, #16
|
|
8001420: af00 add r7, sp, #0
|
|
8001422: 6078 str r0, [r7, #4]
|
|
8001424: 6039 str r1, [r7, #0]
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
|
|
|
|
/* Check the TIM channel state */
|
|
if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
|
|
8001426: 683b ldr r3, [r7, #0]
|
|
8001428: 2b00 cmp r3, #0
|
|
800142a: d109 bne.n 8001440 <HAL_TIM_PWM_Start+0x24>
|
|
800142c: 687b ldr r3, [r7, #4]
|
|
800142e: f893 303e ldrb.w r3, [r3, #62] ; 0x3e
|
|
8001432: b2db uxtb r3, r3
|
|
8001434: 2b01 cmp r3, #1
|
|
8001436: bf14 ite ne
|
|
8001438: 2301 movne r3, #1
|
|
800143a: 2300 moveq r3, #0
|
|
800143c: b2db uxtb r3, r3
|
|
800143e: e022 b.n 8001486 <HAL_TIM_PWM_Start+0x6a>
|
|
8001440: 683b ldr r3, [r7, #0]
|
|
8001442: 2b04 cmp r3, #4
|
|
8001444: d109 bne.n 800145a <HAL_TIM_PWM_Start+0x3e>
|
|
8001446: 687b ldr r3, [r7, #4]
|
|
8001448: f893 303f ldrb.w r3, [r3, #63] ; 0x3f
|
|
800144c: b2db uxtb r3, r3
|
|
800144e: 2b01 cmp r3, #1
|
|
8001450: bf14 ite ne
|
|
8001452: 2301 movne r3, #1
|
|
8001454: 2300 moveq r3, #0
|
|
8001456: b2db uxtb r3, r3
|
|
8001458: e015 b.n 8001486 <HAL_TIM_PWM_Start+0x6a>
|
|
800145a: 683b ldr r3, [r7, #0]
|
|
800145c: 2b08 cmp r3, #8
|
|
800145e: d109 bne.n 8001474 <HAL_TIM_PWM_Start+0x58>
|
|
8001460: 687b ldr r3, [r7, #4]
|
|
8001462: f893 3040 ldrb.w r3, [r3, #64] ; 0x40
|
|
8001466: b2db uxtb r3, r3
|
|
8001468: 2b01 cmp r3, #1
|
|
800146a: bf14 ite ne
|
|
800146c: 2301 movne r3, #1
|
|
800146e: 2300 moveq r3, #0
|
|
8001470: b2db uxtb r3, r3
|
|
8001472: e008 b.n 8001486 <HAL_TIM_PWM_Start+0x6a>
|
|
8001474: 687b ldr r3, [r7, #4]
|
|
8001476: f893 3041 ldrb.w r3, [r3, #65] ; 0x41
|
|
800147a: b2db uxtb r3, r3
|
|
800147c: 2b01 cmp r3, #1
|
|
800147e: bf14 ite ne
|
|
8001480: 2301 movne r3, #1
|
|
8001482: 2300 moveq r3, #0
|
|
8001484: b2db uxtb r3, r3
|
|
8001486: 2b00 cmp r3, #0
|
|
8001488: d001 beq.n 800148e <HAL_TIM_PWM_Start+0x72>
|
|
{
|
|
return HAL_ERROR;
|
|
800148a: 2301 movs r3, #1
|
|
800148c: e05e b.n 800154c <HAL_TIM_PWM_Start+0x130>
|
|
}
|
|
|
|
/* Set the TIM channel state */
|
|
TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
|
|
800148e: 683b ldr r3, [r7, #0]
|
|
8001490: 2b00 cmp r3, #0
|
|
8001492: d104 bne.n 800149e <HAL_TIM_PWM_Start+0x82>
|
|
8001494: 687b ldr r3, [r7, #4]
|
|
8001496: 2202 movs r2, #2
|
|
8001498: f883 203e strb.w r2, [r3, #62] ; 0x3e
|
|
800149c: e013 b.n 80014c6 <HAL_TIM_PWM_Start+0xaa>
|
|
800149e: 683b ldr r3, [r7, #0]
|
|
80014a0: 2b04 cmp r3, #4
|
|
80014a2: d104 bne.n 80014ae <HAL_TIM_PWM_Start+0x92>
|
|
80014a4: 687b ldr r3, [r7, #4]
|
|
80014a6: 2202 movs r2, #2
|
|
80014a8: f883 203f strb.w r2, [r3, #63] ; 0x3f
|
|
80014ac: e00b b.n 80014c6 <HAL_TIM_PWM_Start+0xaa>
|
|
80014ae: 683b ldr r3, [r7, #0]
|
|
80014b0: 2b08 cmp r3, #8
|
|
80014b2: d104 bne.n 80014be <HAL_TIM_PWM_Start+0xa2>
|
|
80014b4: 687b ldr r3, [r7, #4]
|
|
80014b6: 2202 movs r2, #2
|
|
80014b8: f883 2040 strb.w r2, [r3, #64] ; 0x40
|
|
80014bc: e003 b.n 80014c6 <HAL_TIM_PWM_Start+0xaa>
|
|
80014be: 687b ldr r3, [r7, #4]
|
|
80014c0: 2202 movs r2, #2
|
|
80014c2: f883 2041 strb.w r2, [r3, #65] ; 0x41
|
|
|
|
/* Enable the Capture compare channel */
|
|
TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
|
|
80014c6: 687b ldr r3, [r7, #4]
|
|
80014c8: 681b ldr r3, [r3, #0]
|
|
80014ca: 2201 movs r2, #1
|
|
80014cc: 6839 ldr r1, [r7, #0]
|
|
80014ce: 4618 mov r0, r3
|
|
80014d0: f000 fc48 bl 8001d64 <TIM_CCxChannelCmd>
|
|
|
|
if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
|
|
80014d4: 687b ldr r3, [r7, #4]
|
|
80014d6: 681b ldr r3, [r3, #0]
|
|
80014d8: 4a1e ldr r2, [pc, #120] ; (8001554 <HAL_TIM_PWM_Start+0x138>)
|
|
80014da: 4293 cmp r3, r2
|
|
80014dc: d107 bne.n 80014ee <HAL_TIM_PWM_Start+0xd2>
|
|
{
|
|
/* Enable the main output */
|
|
__HAL_TIM_MOE_ENABLE(htim);
|
|
80014de: 687b ldr r3, [r7, #4]
|
|
80014e0: 681b ldr r3, [r3, #0]
|
|
80014e2: 6c5a ldr r2, [r3, #68] ; 0x44
|
|
80014e4: 687b ldr r3, [r7, #4]
|
|
80014e6: 681b ldr r3, [r3, #0]
|
|
80014e8: f442 4200 orr.w r2, r2, #32768 ; 0x8000
|
|
80014ec: 645a str r2, [r3, #68] ; 0x44
|
|
}
|
|
|
|
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
|
|
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
|
|
80014ee: 687b ldr r3, [r7, #4]
|
|
80014f0: 681b ldr r3, [r3, #0]
|
|
80014f2: 4a18 ldr r2, [pc, #96] ; (8001554 <HAL_TIM_PWM_Start+0x138>)
|
|
80014f4: 4293 cmp r3, r2
|
|
80014f6: d00e beq.n 8001516 <HAL_TIM_PWM_Start+0xfa>
|
|
80014f8: 687b ldr r3, [r7, #4]
|
|
80014fa: 681b ldr r3, [r3, #0]
|
|
80014fc: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
|
|
8001500: d009 beq.n 8001516 <HAL_TIM_PWM_Start+0xfa>
|
|
8001502: 687b ldr r3, [r7, #4]
|
|
8001504: 681b ldr r3, [r3, #0]
|
|
8001506: 4a14 ldr r2, [pc, #80] ; (8001558 <HAL_TIM_PWM_Start+0x13c>)
|
|
8001508: 4293 cmp r3, r2
|
|
800150a: d004 beq.n 8001516 <HAL_TIM_PWM_Start+0xfa>
|
|
800150c: 687b ldr r3, [r7, #4]
|
|
800150e: 681b ldr r3, [r3, #0]
|
|
8001510: 4a12 ldr r2, [pc, #72] ; (800155c <HAL_TIM_PWM_Start+0x140>)
|
|
8001512: 4293 cmp r3, r2
|
|
8001514: d111 bne.n 800153a <HAL_TIM_PWM_Start+0x11e>
|
|
{
|
|
tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
|
|
8001516: 687b ldr r3, [r7, #4]
|
|
8001518: 681b ldr r3, [r3, #0]
|
|
800151a: 689b ldr r3, [r3, #8]
|
|
800151c: f003 0307 and.w r3, r3, #7
|
|
8001520: 60fb str r3, [r7, #12]
|
|
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
|
|
8001522: 68fb ldr r3, [r7, #12]
|
|
8001524: 2b06 cmp r3, #6
|
|
8001526: d010 beq.n 800154a <HAL_TIM_PWM_Start+0x12e>
|
|
{
|
|
__HAL_TIM_ENABLE(htim);
|
|
8001528: 687b ldr r3, [r7, #4]
|
|
800152a: 681b ldr r3, [r3, #0]
|
|
800152c: 681a ldr r2, [r3, #0]
|
|
800152e: 687b ldr r3, [r7, #4]
|
|
8001530: 681b ldr r3, [r3, #0]
|
|
8001532: f042 0201 orr.w r2, r2, #1
|
|
8001536: 601a str r2, [r3, #0]
|
|
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
|
|
8001538: e007 b.n 800154a <HAL_TIM_PWM_Start+0x12e>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
__HAL_TIM_ENABLE(htim);
|
|
800153a: 687b ldr r3, [r7, #4]
|
|
800153c: 681b ldr r3, [r3, #0]
|
|
800153e: 681a ldr r2, [r3, #0]
|
|
8001540: 687b ldr r3, [r7, #4]
|
|
8001542: 681b ldr r3, [r3, #0]
|
|
8001544: f042 0201 orr.w r2, r2, #1
|
|
8001548: 601a str r2, [r3, #0]
|
|
}
|
|
|
|
/* Return function status */
|
|
return HAL_OK;
|
|
800154a: 2300 movs r3, #0
|
|
}
|
|
800154c: 4618 mov r0, r3
|
|
800154e: 3710 adds r7, #16
|
|
8001550: 46bd mov sp, r7
|
|
8001552: bd80 pop {r7, pc}
|
|
8001554: 40012c00 .word 0x40012c00
|
|
8001558: 40000400 .word 0x40000400
|
|
800155c: 40000800 .word 0x40000800
|
|
|
|
08001560 <HAL_TIM_PWM_ConfigChannel>:
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
|
|
TIM_OC_InitTypeDef *sConfig,
|
|
uint32_t Channel)
|
|
{
|
|
8001560: b580 push {r7, lr}
|
|
8001562: b084 sub sp, #16
|
|
8001564: af00 add r7, sp, #0
|
|
8001566: 60f8 str r0, [r7, #12]
|
|
8001568: 60b9 str r1, [r7, #8]
|
|
800156a: 607a str r2, [r7, #4]
|
|
assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
|
|
assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
|
|
assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
|
|
|
|
/* Process Locked */
|
|
__HAL_LOCK(htim);
|
|
800156c: 68fb ldr r3, [r7, #12]
|
|
800156e: f893 303c ldrb.w r3, [r3, #60] ; 0x3c
|
|
8001572: 2b01 cmp r3, #1
|
|
8001574: d101 bne.n 800157a <HAL_TIM_PWM_ConfigChannel+0x1a>
|
|
8001576: 2302 movs r3, #2
|
|
8001578: e0ac b.n 80016d4 <HAL_TIM_PWM_ConfigChannel+0x174>
|
|
800157a: 68fb ldr r3, [r7, #12]
|
|
800157c: 2201 movs r2, #1
|
|
800157e: f883 203c strb.w r2, [r3, #60] ; 0x3c
|
|
|
|
switch (Channel)
|
|
8001582: 687b ldr r3, [r7, #4]
|
|
8001584: 2b0c cmp r3, #12
|
|
8001586: f200 809f bhi.w 80016c8 <HAL_TIM_PWM_ConfigChannel+0x168>
|
|
800158a: a201 add r2, pc, #4 ; (adr r2, 8001590 <HAL_TIM_PWM_ConfigChannel+0x30>)
|
|
800158c: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
8001590: 080015c5 .word 0x080015c5
|
|
8001594: 080016c9 .word 0x080016c9
|
|
8001598: 080016c9 .word 0x080016c9
|
|
800159c: 080016c9 .word 0x080016c9
|
|
80015a0: 08001605 .word 0x08001605
|
|
80015a4: 080016c9 .word 0x080016c9
|
|
80015a8: 080016c9 .word 0x080016c9
|
|
80015ac: 080016c9 .word 0x080016c9
|
|
80015b0: 08001647 .word 0x08001647
|
|
80015b4: 080016c9 .word 0x080016c9
|
|
80015b8: 080016c9 .word 0x080016c9
|
|
80015bc: 080016c9 .word 0x080016c9
|
|
80015c0: 08001687 .word 0x08001687
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
|
|
|
|
/* Configure the Channel 1 in PWM mode */
|
|
TIM_OC1_SetConfig(htim->Instance, sConfig);
|
|
80015c4: 68fb ldr r3, [r7, #12]
|
|
80015c6: 681b ldr r3, [r3, #0]
|
|
80015c8: 68b9 ldr r1, [r7, #8]
|
|
80015ca: 4618 mov r0, r3
|
|
80015cc: f000 f9ac bl 8001928 <TIM_OC1_SetConfig>
|
|
|
|
/* Set the Preload enable bit for channel1 */
|
|
htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
|
|
80015d0: 68fb ldr r3, [r7, #12]
|
|
80015d2: 681b ldr r3, [r3, #0]
|
|
80015d4: 699a ldr r2, [r3, #24]
|
|
80015d6: 68fb ldr r3, [r7, #12]
|
|
80015d8: 681b ldr r3, [r3, #0]
|
|
80015da: f042 0208 orr.w r2, r2, #8
|
|
80015de: 619a str r2, [r3, #24]
|
|
|
|
/* Configure the Output Fast mode */
|
|
htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
|
|
80015e0: 68fb ldr r3, [r7, #12]
|
|
80015e2: 681b ldr r3, [r3, #0]
|
|
80015e4: 699a ldr r2, [r3, #24]
|
|
80015e6: 68fb ldr r3, [r7, #12]
|
|
80015e8: 681b ldr r3, [r3, #0]
|
|
80015ea: f022 0204 bic.w r2, r2, #4
|
|
80015ee: 619a str r2, [r3, #24]
|
|
htim->Instance->CCMR1 |= sConfig->OCFastMode;
|
|
80015f0: 68fb ldr r3, [r7, #12]
|
|
80015f2: 681b ldr r3, [r3, #0]
|
|
80015f4: 6999 ldr r1, [r3, #24]
|
|
80015f6: 68bb ldr r3, [r7, #8]
|
|
80015f8: 691a ldr r2, [r3, #16]
|
|
80015fa: 68fb ldr r3, [r7, #12]
|
|
80015fc: 681b ldr r3, [r3, #0]
|
|
80015fe: 430a orrs r2, r1
|
|
8001600: 619a str r2, [r3, #24]
|
|
break;
|
|
8001602: e062 b.n 80016ca <HAL_TIM_PWM_ConfigChannel+0x16a>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
|
|
|
|
/* Configure the Channel 2 in PWM mode */
|
|
TIM_OC2_SetConfig(htim->Instance, sConfig);
|
|
8001604: 68fb ldr r3, [r7, #12]
|
|
8001606: 681b ldr r3, [r3, #0]
|
|
8001608: 68b9 ldr r1, [r7, #8]
|
|
800160a: 4618 mov r0, r3
|
|
800160c: f000 f9f2 bl 80019f4 <TIM_OC2_SetConfig>
|
|
|
|
/* Set the Preload enable bit for channel2 */
|
|
htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
|
|
8001610: 68fb ldr r3, [r7, #12]
|
|
8001612: 681b ldr r3, [r3, #0]
|
|
8001614: 699a ldr r2, [r3, #24]
|
|
8001616: 68fb ldr r3, [r7, #12]
|
|
8001618: 681b ldr r3, [r3, #0]
|
|
800161a: f442 6200 orr.w r2, r2, #2048 ; 0x800
|
|
800161e: 619a str r2, [r3, #24]
|
|
|
|
/* Configure the Output Fast mode */
|
|
htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
|
|
8001620: 68fb ldr r3, [r7, #12]
|
|
8001622: 681b ldr r3, [r3, #0]
|
|
8001624: 699a ldr r2, [r3, #24]
|
|
8001626: 68fb ldr r3, [r7, #12]
|
|
8001628: 681b ldr r3, [r3, #0]
|
|
800162a: f422 6280 bic.w r2, r2, #1024 ; 0x400
|
|
800162e: 619a str r2, [r3, #24]
|
|
htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
|
|
8001630: 68fb ldr r3, [r7, #12]
|
|
8001632: 681b ldr r3, [r3, #0]
|
|
8001634: 6999 ldr r1, [r3, #24]
|
|
8001636: 68bb ldr r3, [r7, #8]
|
|
8001638: 691b ldr r3, [r3, #16]
|
|
800163a: 021a lsls r2, r3, #8
|
|
800163c: 68fb ldr r3, [r7, #12]
|
|
800163e: 681b ldr r3, [r3, #0]
|
|
8001640: 430a orrs r2, r1
|
|
8001642: 619a str r2, [r3, #24]
|
|
break;
|
|
8001644: e041 b.n 80016ca <HAL_TIM_PWM_ConfigChannel+0x16a>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
|
|
|
|
/* Configure the Channel 3 in PWM mode */
|
|
TIM_OC3_SetConfig(htim->Instance, sConfig);
|
|
8001646: 68fb ldr r3, [r7, #12]
|
|
8001648: 681b ldr r3, [r3, #0]
|
|
800164a: 68b9 ldr r1, [r7, #8]
|
|
800164c: 4618 mov r0, r3
|
|
800164e: f000 fa3b bl 8001ac8 <TIM_OC3_SetConfig>
|
|
|
|
/* Set the Preload enable bit for channel3 */
|
|
htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
|
|
8001652: 68fb ldr r3, [r7, #12]
|
|
8001654: 681b ldr r3, [r3, #0]
|
|
8001656: 69da ldr r2, [r3, #28]
|
|
8001658: 68fb ldr r3, [r7, #12]
|
|
800165a: 681b ldr r3, [r3, #0]
|
|
800165c: f042 0208 orr.w r2, r2, #8
|
|
8001660: 61da str r2, [r3, #28]
|
|
|
|
/* Configure the Output Fast mode */
|
|
htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
|
|
8001662: 68fb ldr r3, [r7, #12]
|
|
8001664: 681b ldr r3, [r3, #0]
|
|
8001666: 69da ldr r2, [r3, #28]
|
|
8001668: 68fb ldr r3, [r7, #12]
|
|
800166a: 681b ldr r3, [r3, #0]
|
|
800166c: f022 0204 bic.w r2, r2, #4
|
|
8001670: 61da str r2, [r3, #28]
|
|
htim->Instance->CCMR2 |= sConfig->OCFastMode;
|
|
8001672: 68fb ldr r3, [r7, #12]
|
|
8001674: 681b ldr r3, [r3, #0]
|
|
8001676: 69d9 ldr r1, [r3, #28]
|
|
8001678: 68bb ldr r3, [r7, #8]
|
|
800167a: 691a ldr r2, [r3, #16]
|
|
800167c: 68fb ldr r3, [r7, #12]
|
|
800167e: 681b ldr r3, [r3, #0]
|
|
8001680: 430a orrs r2, r1
|
|
8001682: 61da str r2, [r3, #28]
|
|
break;
|
|
8001684: e021 b.n 80016ca <HAL_TIM_PWM_ConfigChannel+0x16a>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
|
|
|
|
/* Configure the Channel 4 in PWM mode */
|
|
TIM_OC4_SetConfig(htim->Instance, sConfig);
|
|
8001686: 68fb ldr r3, [r7, #12]
|
|
8001688: 681b ldr r3, [r3, #0]
|
|
800168a: 68b9 ldr r1, [r7, #8]
|
|
800168c: 4618 mov r0, r3
|
|
800168e: f000 fa85 bl 8001b9c <TIM_OC4_SetConfig>
|
|
|
|
/* Set the Preload enable bit for channel4 */
|
|
htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
|
|
8001692: 68fb ldr r3, [r7, #12]
|
|
8001694: 681b ldr r3, [r3, #0]
|
|
8001696: 69da ldr r2, [r3, #28]
|
|
8001698: 68fb ldr r3, [r7, #12]
|
|
800169a: 681b ldr r3, [r3, #0]
|
|
800169c: f442 6200 orr.w r2, r2, #2048 ; 0x800
|
|
80016a0: 61da str r2, [r3, #28]
|
|
|
|
/* Configure the Output Fast mode */
|
|
htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
|
|
80016a2: 68fb ldr r3, [r7, #12]
|
|
80016a4: 681b ldr r3, [r3, #0]
|
|
80016a6: 69da ldr r2, [r3, #28]
|
|
80016a8: 68fb ldr r3, [r7, #12]
|
|
80016aa: 681b ldr r3, [r3, #0]
|
|
80016ac: f422 6280 bic.w r2, r2, #1024 ; 0x400
|
|
80016b0: 61da str r2, [r3, #28]
|
|
htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
|
|
80016b2: 68fb ldr r3, [r7, #12]
|
|
80016b4: 681b ldr r3, [r3, #0]
|
|
80016b6: 69d9 ldr r1, [r3, #28]
|
|
80016b8: 68bb ldr r3, [r7, #8]
|
|
80016ba: 691b ldr r3, [r3, #16]
|
|
80016bc: 021a lsls r2, r3, #8
|
|
80016be: 68fb ldr r3, [r7, #12]
|
|
80016c0: 681b ldr r3, [r3, #0]
|
|
80016c2: 430a orrs r2, r1
|
|
80016c4: 61da str r2, [r3, #28]
|
|
break;
|
|
80016c6: e000 b.n 80016ca <HAL_TIM_PWM_ConfigChannel+0x16a>
|
|
}
|
|
|
|
default:
|
|
break;
|
|
80016c8: bf00 nop
|
|
}
|
|
|
|
__HAL_UNLOCK(htim);
|
|
80016ca: 68fb ldr r3, [r7, #12]
|
|
80016cc: 2200 movs r2, #0
|
|
80016ce: f883 203c strb.w r2, [r3, #60] ; 0x3c
|
|
|
|
return HAL_OK;
|
|
80016d2: 2300 movs r3, #0
|
|
}
|
|
80016d4: 4618 mov r0, r3
|
|
80016d6: 3710 adds r7, #16
|
|
80016d8: 46bd mov sp, r7
|
|
80016da: bd80 pop {r7, pc}
|
|
|
|
080016dc <HAL_TIM_ConfigClockSource>:
|
|
* @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that
|
|
* contains the clock source information for the TIM peripheral.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig)
|
|
{
|
|
80016dc: b580 push {r7, lr}
|
|
80016de: b084 sub sp, #16
|
|
80016e0: af00 add r7, sp, #0
|
|
80016e2: 6078 str r0, [r7, #4]
|
|
80016e4: 6039 str r1, [r7, #0]
|
|
uint32_t tmpsmcr;
|
|
|
|
/* Process Locked */
|
|
__HAL_LOCK(htim);
|
|
80016e6: 687b ldr r3, [r7, #4]
|
|
80016e8: f893 303c ldrb.w r3, [r3, #60] ; 0x3c
|
|
80016ec: 2b01 cmp r3, #1
|
|
80016ee: d101 bne.n 80016f4 <HAL_TIM_ConfigClockSource+0x18>
|
|
80016f0: 2302 movs r3, #2
|
|
80016f2: e0b3 b.n 800185c <HAL_TIM_ConfigClockSource+0x180>
|
|
80016f4: 687b ldr r3, [r7, #4]
|
|
80016f6: 2201 movs r2, #1
|
|
80016f8: f883 203c strb.w r2, [r3, #60] ; 0x3c
|
|
|
|
htim->State = HAL_TIM_STATE_BUSY;
|
|
80016fc: 687b ldr r3, [r7, #4]
|
|
80016fe: 2202 movs r2, #2
|
|
8001700: f883 203d strb.w r2, [r3, #61] ; 0x3d
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
|
|
|
|
/* Reset the SMS, TS, ECE, ETPS and ETRF bits */
|
|
tmpsmcr = htim->Instance->SMCR;
|
|
8001704: 687b ldr r3, [r7, #4]
|
|
8001706: 681b ldr r3, [r3, #0]
|
|
8001708: 689b ldr r3, [r3, #8]
|
|
800170a: 60fb str r3, [r7, #12]
|
|
tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
|
|
800170c: 68fb ldr r3, [r7, #12]
|
|
800170e: f023 0377 bic.w r3, r3, #119 ; 0x77
|
|
8001712: 60fb str r3, [r7, #12]
|
|
tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
|
|
8001714: 68fb ldr r3, [r7, #12]
|
|
8001716: f423 437f bic.w r3, r3, #65280 ; 0xff00
|
|
800171a: 60fb str r3, [r7, #12]
|
|
htim->Instance->SMCR = tmpsmcr;
|
|
800171c: 687b ldr r3, [r7, #4]
|
|
800171e: 681b ldr r3, [r3, #0]
|
|
8001720: 68fa ldr r2, [r7, #12]
|
|
8001722: 609a str r2, [r3, #8]
|
|
|
|
switch (sClockSourceConfig->ClockSource)
|
|
8001724: 683b ldr r3, [r7, #0]
|
|
8001726: 681b ldr r3, [r3, #0]
|
|
8001728: f5b3 5f00 cmp.w r3, #8192 ; 0x2000
|
|
800172c: d03e beq.n 80017ac <HAL_TIM_ConfigClockSource+0xd0>
|
|
800172e: f5b3 5f00 cmp.w r3, #8192 ; 0x2000
|
|
8001732: f200 8087 bhi.w 8001844 <HAL_TIM_ConfigClockSource+0x168>
|
|
8001736: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
|
|
800173a: f000 8085 beq.w 8001848 <HAL_TIM_ConfigClockSource+0x16c>
|
|
800173e: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
|
|
8001742: d87f bhi.n 8001844 <HAL_TIM_ConfigClockSource+0x168>
|
|
8001744: 2b70 cmp r3, #112 ; 0x70
|
|
8001746: d01a beq.n 800177e <HAL_TIM_ConfigClockSource+0xa2>
|
|
8001748: 2b70 cmp r3, #112 ; 0x70
|
|
800174a: d87b bhi.n 8001844 <HAL_TIM_ConfigClockSource+0x168>
|
|
800174c: 2b60 cmp r3, #96 ; 0x60
|
|
800174e: d050 beq.n 80017f2 <HAL_TIM_ConfigClockSource+0x116>
|
|
8001750: 2b60 cmp r3, #96 ; 0x60
|
|
8001752: d877 bhi.n 8001844 <HAL_TIM_ConfigClockSource+0x168>
|
|
8001754: 2b50 cmp r3, #80 ; 0x50
|
|
8001756: d03c beq.n 80017d2 <HAL_TIM_ConfigClockSource+0xf6>
|
|
8001758: 2b50 cmp r3, #80 ; 0x50
|
|
800175a: d873 bhi.n 8001844 <HAL_TIM_ConfigClockSource+0x168>
|
|
800175c: 2b40 cmp r3, #64 ; 0x40
|
|
800175e: d058 beq.n 8001812 <HAL_TIM_ConfigClockSource+0x136>
|
|
8001760: 2b40 cmp r3, #64 ; 0x40
|
|
8001762: d86f bhi.n 8001844 <HAL_TIM_ConfigClockSource+0x168>
|
|
8001764: 2b30 cmp r3, #48 ; 0x30
|
|
8001766: d064 beq.n 8001832 <HAL_TIM_ConfigClockSource+0x156>
|
|
8001768: 2b30 cmp r3, #48 ; 0x30
|
|
800176a: d86b bhi.n 8001844 <HAL_TIM_ConfigClockSource+0x168>
|
|
800176c: 2b20 cmp r3, #32
|
|
800176e: d060 beq.n 8001832 <HAL_TIM_ConfigClockSource+0x156>
|
|
8001770: 2b20 cmp r3, #32
|
|
8001772: d867 bhi.n 8001844 <HAL_TIM_ConfigClockSource+0x168>
|
|
8001774: 2b00 cmp r3, #0
|
|
8001776: d05c beq.n 8001832 <HAL_TIM_ConfigClockSource+0x156>
|
|
8001778: 2b10 cmp r3, #16
|
|
800177a: d05a beq.n 8001832 <HAL_TIM_ConfigClockSource+0x156>
|
|
TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
|
|
break;
|
|
}
|
|
|
|
default:
|
|
break;
|
|
800177c: e062 b.n 8001844 <HAL_TIM_ConfigClockSource+0x168>
|
|
TIM_ETR_SetConfig(htim->Instance,
|
|
800177e: 687b ldr r3, [r7, #4]
|
|
8001780: 6818 ldr r0, [r3, #0]
|
|
8001782: 683b ldr r3, [r7, #0]
|
|
8001784: 6899 ldr r1, [r3, #8]
|
|
8001786: 683b ldr r3, [r7, #0]
|
|
8001788: 685a ldr r2, [r3, #4]
|
|
800178a: 683b ldr r3, [r7, #0]
|
|
800178c: 68db ldr r3, [r3, #12]
|
|
800178e: f000 faca bl 8001d26 <TIM_ETR_SetConfig>
|
|
tmpsmcr = htim->Instance->SMCR;
|
|
8001792: 687b ldr r3, [r7, #4]
|
|
8001794: 681b ldr r3, [r3, #0]
|
|
8001796: 689b ldr r3, [r3, #8]
|
|
8001798: 60fb str r3, [r7, #12]
|
|
tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
|
|
800179a: 68fb ldr r3, [r7, #12]
|
|
800179c: f043 0377 orr.w r3, r3, #119 ; 0x77
|
|
80017a0: 60fb str r3, [r7, #12]
|
|
htim->Instance->SMCR = tmpsmcr;
|
|
80017a2: 687b ldr r3, [r7, #4]
|
|
80017a4: 681b ldr r3, [r3, #0]
|
|
80017a6: 68fa ldr r2, [r7, #12]
|
|
80017a8: 609a str r2, [r3, #8]
|
|
break;
|
|
80017aa: e04e b.n 800184a <HAL_TIM_ConfigClockSource+0x16e>
|
|
TIM_ETR_SetConfig(htim->Instance,
|
|
80017ac: 687b ldr r3, [r7, #4]
|
|
80017ae: 6818 ldr r0, [r3, #0]
|
|
80017b0: 683b ldr r3, [r7, #0]
|
|
80017b2: 6899 ldr r1, [r3, #8]
|
|
80017b4: 683b ldr r3, [r7, #0]
|
|
80017b6: 685a ldr r2, [r3, #4]
|
|
80017b8: 683b ldr r3, [r7, #0]
|
|
80017ba: 68db ldr r3, [r3, #12]
|
|
80017bc: f000 fab3 bl 8001d26 <TIM_ETR_SetConfig>
|
|
htim->Instance->SMCR |= TIM_SMCR_ECE;
|
|
80017c0: 687b ldr r3, [r7, #4]
|
|
80017c2: 681b ldr r3, [r3, #0]
|
|
80017c4: 689a ldr r2, [r3, #8]
|
|
80017c6: 687b ldr r3, [r7, #4]
|
|
80017c8: 681b ldr r3, [r3, #0]
|
|
80017ca: f442 4280 orr.w r2, r2, #16384 ; 0x4000
|
|
80017ce: 609a str r2, [r3, #8]
|
|
break;
|
|
80017d0: e03b b.n 800184a <HAL_TIM_ConfigClockSource+0x16e>
|
|
TIM_TI1_ConfigInputStage(htim->Instance,
|
|
80017d2: 687b ldr r3, [r7, #4]
|
|
80017d4: 6818 ldr r0, [r3, #0]
|
|
80017d6: 683b ldr r3, [r7, #0]
|
|
80017d8: 6859 ldr r1, [r3, #4]
|
|
80017da: 683b ldr r3, [r7, #0]
|
|
80017dc: 68db ldr r3, [r3, #12]
|
|
80017de: 461a mov r2, r3
|
|
80017e0: f000 fa2a bl 8001c38 <TIM_TI1_ConfigInputStage>
|
|
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
|
|
80017e4: 687b ldr r3, [r7, #4]
|
|
80017e6: 681b ldr r3, [r3, #0]
|
|
80017e8: 2150 movs r1, #80 ; 0x50
|
|
80017ea: 4618 mov r0, r3
|
|
80017ec: f000 fa81 bl 8001cf2 <TIM_ITRx_SetConfig>
|
|
break;
|
|
80017f0: e02b b.n 800184a <HAL_TIM_ConfigClockSource+0x16e>
|
|
TIM_TI2_ConfigInputStage(htim->Instance,
|
|
80017f2: 687b ldr r3, [r7, #4]
|
|
80017f4: 6818 ldr r0, [r3, #0]
|
|
80017f6: 683b ldr r3, [r7, #0]
|
|
80017f8: 6859 ldr r1, [r3, #4]
|
|
80017fa: 683b ldr r3, [r7, #0]
|
|
80017fc: 68db ldr r3, [r3, #12]
|
|
80017fe: 461a mov r2, r3
|
|
8001800: f000 fa48 bl 8001c94 <TIM_TI2_ConfigInputStage>
|
|
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
|
|
8001804: 687b ldr r3, [r7, #4]
|
|
8001806: 681b ldr r3, [r3, #0]
|
|
8001808: 2160 movs r1, #96 ; 0x60
|
|
800180a: 4618 mov r0, r3
|
|
800180c: f000 fa71 bl 8001cf2 <TIM_ITRx_SetConfig>
|
|
break;
|
|
8001810: e01b b.n 800184a <HAL_TIM_ConfigClockSource+0x16e>
|
|
TIM_TI1_ConfigInputStage(htim->Instance,
|
|
8001812: 687b ldr r3, [r7, #4]
|
|
8001814: 6818 ldr r0, [r3, #0]
|
|
8001816: 683b ldr r3, [r7, #0]
|
|
8001818: 6859 ldr r1, [r3, #4]
|
|
800181a: 683b ldr r3, [r7, #0]
|
|
800181c: 68db ldr r3, [r3, #12]
|
|
800181e: 461a mov r2, r3
|
|
8001820: f000 fa0a bl 8001c38 <TIM_TI1_ConfigInputStage>
|
|
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
|
|
8001824: 687b ldr r3, [r7, #4]
|
|
8001826: 681b ldr r3, [r3, #0]
|
|
8001828: 2140 movs r1, #64 ; 0x40
|
|
800182a: 4618 mov r0, r3
|
|
800182c: f000 fa61 bl 8001cf2 <TIM_ITRx_SetConfig>
|
|
break;
|
|
8001830: e00b b.n 800184a <HAL_TIM_ConfigClockSource+0x16e>
|
|
TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
|
|
8001832: 687b ldr r3, [r7, #4]
|
|
8001834: 681a ldr r2, [r3, #0]
|
|
8001836: 683b ldr r3, [r7, #0]
|
|
8001838: 681b ldr r3, [r3, #0]
|
|
800183a: 4619 mov r1, r3
|
|
800183c: 4610 mov r0, r2
|
|
800183e: f000 fa58 bl 8001cf2 <TIM_ITRx_SetConfig>
|
|
break;
|
|
8001842: e002 b.n 800184a <HAL_TIM_ConfigClockSource+0x16e>
|
|
break;
|
|
8001844: bf00 nop
|
|
8001846: e000 b.n 800184a <HAL_TIM_ConfigClockSource+0x16e>
|
|
break;
|
|
8001848: bf00 nop
|
|
}
|
|
htim->State = HAL_TIM_STATE_READY;
|
|
800184a: 687b ldr r3, [r7, #4]
|
|
800184c: 2201 movs r2, #1
|
|
800184e: f883 203d strb.w r2, [r3, #61] ; 0x3d
|
|
|
|
__HAL_UNLOCK(htim);
|
|
8001852: 687b ldr r3, [r7, #4]
|
|
8001854: 2200 movs r2, #0
|
|
8001856: f883 203c strb.w r2, [r3, #60] ; 0x3c
|
|
|
|
return HAL_OK;
|
|
800185a: 2300 movs r3, #0
|
|
}
|
|
800185c: 4618 mov r0, r3
|
|
800185e: 3710 adds r7, #16
|
|
8001860: 46bd mov sp, r7
|
|
8001862: bd80 pop {r7, pc}
|
|
|
|
08001864 <TIM_Base_SetConfig>:
|
|
* @param TIMx TIM peripheral
|
|
* @param Structure TIM Base configuration structure
|
|
* @retval None
|
|
*/
|
|
void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
|
|
{
|
|
8001864: b480 push {r7}
|
|
8001866: b085 sub sp, #20
|
|
8001868: af00 add r7, sp, #0
|
|
800186a: 6078 str r0, [r7, #4]
|
|
800186c: 6039 str r1, [r7, #0]
|
|
uint32_t tmpcr1;
|
|
tmpcr1 = TIMx->CR1;
|
|
800186e: 687b ldr r3, [r7, #4]
|
|
8001870: 681b ldr r3, [r3, #0]
|
|
8001872: 60fb str r3, [r7, #12]
|
|
|
|
/* Set TIM Time Base Unit parameters ---------------------------------------*/
|
|
if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
|
|
8001874: 687b ldr r3, [r7, #4]
|
|
8001876: 4a29 ldr r2, [pc, #164] ; (800191c <TIM_Base_SetConfig+0xb8>)
|
|
8001878: 4293 cmp r3, r2
|
|
800187a: d00b beq.n 8001894 <TIM_Base_SetConfig+0x30>
|
|
800187c: 687b ldr r3, [r7, #4]
|
|
800187e: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
|
|
8001882: d007 beq.n 8001894 <TIM_Base_SetConfig+0x30>
|
|
8001884: 687b ldr r3, [r7, #4]
|
|
8001886: 4a26 ldr r2, [pc, #152] ; (8001920 <TIM_Base_SetConfig+0xbc>)
|
|
8001888: 4293 cmp r3, r2
|
|
800188a: d003 beq.n 8001894 <TIM_Base_SetConfig+0x30>
|
|
800188c: 687b ldr r3, [r7, #4]
|
|
800188e: 4a25 ldr r2, [pc, #148] ; (8001924 <TIM_Base_SetConfig+0xc0>)
|
|
8001890: 4293 cmp r3, r2
|
|
8001892: d108 bne.n 80018a6 <TIM_Base_SetConfig+0x42>
|
|
{
|
|
/* Select the Counter Mode */
|
|
tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
|
|
8001894: 68fb ldr r3, [r7, #12]
|
|
8001896: f023 0370 bic.w r3, r3, #112 ; 0x70
|
|
800189a: 60fb str r3, [r7, #12]
|
|
tmpcr1 |= Structure->CounterMode;
|
|
800189c: 683b ldr r3, [r7, #0]
|
|
800189e: 685b ldr r3, [r3, #4]
|
|
80018a0: 68fa ldr r2, [r7, #12]
|
|
80018a2: 4313 orrs r3, r2
|
|
80018a4: 60fb str r3, [r7, #12]
|
|
}
|
|
|
|
if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
|
|
80018a6: 687b ldr r3, [r7, #4]
|
|
80018a8: 4a1c ldr r2, [pc, #112] ; (800191c <TIM_Base_SetConfig+0xb8>)
|
|
80018aa: 4293 cmp r3, r2
|
|
80018ac: d00b beq.n 80018c6 <TIM_Base_SetConfig+0x62>
|
|
80018ae: 687b ldr r3, [r7, #4]
|
|
80018b0: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
|
|
80018b4: d007 beq.n 80018c6 <TIM_Base_SetConfig+0x62>
|
|
80018b6: 687b ldr r3, [r7, #4]
|
|
80018b8: 4a19 ldr r2, [pc, #100] ; (8001920 <TIM_Base_SetConfig+0xbc>)
|
|
80018ba: 4293 cmp r3, r2
|
|
80018bc: d003 beq.n 80018c6 <TIM_Base_SetConfig+0x62>
|
|
80018be: 687b ldr r3, [r7, #4]
|
|
80018c0: 4a18 ldr r2, [pc, #96] ; (8001924 <TIM_Base_SetConfig+0xc0>)
|
|
80018c2: 4293 cmp r3, r2
|
|
80018c4: d108 bne.n 80018d8 <TIM_Base_SetConfig+0x74>
|
|
{
|
|
/* Set the clock division */
|
|
tmpcr1 &= ~TIM_CR1_CKD;
|
|
80018c6: 68fb ldr r3, [r7, #12]
|
|
80018c8: f423 7340 bic.w r3, r3, #768 ; 0x300
|
|
80018cc: 60fb str r3, [r7, #12]
|
|
tmpcr1 |= (uint32_t)Structure->ClockDivision;
|
|
80018ce: 683b ldr r3, [r7, #0]
|
|
80018d0: 68db ldr r3, [r3, #12]
|
|
80018d2: 68fa ldr r2, [r7, #12]
|
|
80018d4: 4313 orrs r3, r2
|
|
80018d6: 60fb str r3, [r7, #12]
|
|
}
|
|
|
|
/* Set the auto-reload preload */
|
|
MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
|
|
80018d8: 68fb ldr r3, [r7, #12]
|
|
80018da: f023 0280 bic.w r2, r3, #128 ; 0x80
|
|
80018de: 683b ldr r3, [r7, #0]
|
|
80018e0: 695b ldr r3, [r3, #20]
|
|
80018e2: 4313 orrs r3, r2
|
|
80018e4: 60fb str r3, [r7, #12]
|
|
|
|
TIMx->CR1 = tmpcr1;
|
|
80018e6: 687b ldr r3, [r7, #4]
|
|
80018e8: 68fa ldr r2, [r7, #12]
|
|
80018ea: 601a str r2, [r3, #0]
|
|
|
|
/* Set the Autoreload value */
|
|
TIMx->ARR = (uint32_t)Structure->Period ;
|
|
80018ec: 683b ldr r3, [r7, #0]
|
|
80018ee: 689a ldr r2, [r3, #8]
|
|
80018f0: 687b ldr r3, [r7, #4]
|
|
80018f2: 62da str r2, [r3, #44] ; 0x2c
|
|
|
|
/* Set the Prescaler value */
|
|
TIMx->PSC = Structure->Prescaler;
|
|
80018f4: 683b ldr r3, [r7, #0]
|
|
80018f6: 681a ldr r2, [r3, #0]
|
|
80018f8: 687b ldr r3, [r7, #4]
|
|
80018fa: 629a str r2, [r3, #40] ; 0x28
|
|
|
|
if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
|
|
80018fc: 687b ldr r3, [r7, #4]
|
|
80018fe: 4a07 ldr r2, [pc, #28] ; (800191c <TIM_Base_SetConfig+0xb8>)
|
|
8001900: 4293 cmp r3, r2
|
|
8001902: d103 bne.n 800190c <TIM_Base_SetConfig+0xa8>
|
|
{
|
|
/* Set the Repetition Counter value */
|
|
TIMx->RCR = Structure->RepetitionCounter;
|
|
8001904: 683b ldr r3, [r7, #0]
|
|
8001906: 691a ldr r2, [r3, #16]
|
|
8001908: 687b ldr r3, [r7, #4]
|
|
800190a: 631a str r2, [r3, #48] ; 0x30
|
|
}
|
|
|
|
/* Generate an update event to reload the Prescaler
|
|
and the repetition counter (only for advanced timer) value immediately */
|
|
TIMx->EGR = TIM_EGR_UG;
|
|
800190c: 687b ldr r3, [r7, #4]
|
|
800190e: 2201 movs r2, #1
|
|
8001910: 615a str r2, [r3, #20]
|
|
}
|
|
8001912: bf00 nop
|
|
8001914: 3714 adds r7, #20
|
|
8001916: 46bd mov sp, r7
|
|
8001918: bc80 pop {r7}
|
|
800191a: 4770 bx lr
|
|
800191c: 40012c00 .word 0x40012c00
|
|
8001920: 40000400 .word 0x40000400
|
|
8001924: 40000800 .word 0x40000800
|
|
|
|
08001928 <TIM_OC1_SetConfig>:
|
|
* @param TIMx to select the TIM peripheral
|
|
* @param OC_Config The output configuration structure
|
|
* @retval None
|
|
*/
|
|
static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
|
|
{
|
|
8001928: b480 push {r7}
|
|
800192a: b087 sub sp, #28
|
|
800192c: af00 add r7, sp, #0
|
|
800192e: 6078 str r0, [r7, #4]
|
|
8001930: 6039 str r1, [r7, #0]
|
|
uint32_t tmpccmrx;
|
|
uint32_t tmpccer;
|
|
uint32_t tmpcr2;
|
|
|
|
/* Disable the Channel 1: Reset the CC1E Bit */
|
|
TIMx->CCER &= ~TIM_CCER_CC1E;
|
|
8001932: 687b ldr r3, [r7, #4]
|
|
8001934: 6a1b ldr r3, [r3, #32]
|
|
8001936: f023 0201 bic.w r2, r3, #1
|
|
800193a: 687b ldr r3, [r7, #4]
|
|
800193c: 621a str r2, [r3, #32]
|
|
|
|
/* Get the TIMx CCER register value */
|
|
tmpccer = TIMx->CCER;
|
|
800193e: 687b ldr r3, [r7, #4]
|
|
8001940: 6a1b ldr r3, [r3, #32]
|
|
8001942: 617b str r3, [r7, #20]
|
|
/* Get the TIMx CR2 register value */
|
|
tmpcr2 = TIMx->CR2;
|
|
8001944: 687b ldr r3, [r7, #4]
|
|
8001946: 685b ldr r3, [r3, #4]
|
|
8001948: 613b str r3, [r7, #16]
|
|
|
|
/* Get the TIMx CCMR1 register value */
|
|
tmpccmrx = TIMx->CCMR1;
|
|
800194a: 687b ldr r3, [r7, #4]
|
|
800194c: 699b ldr r3, [r3, #24]
|
|
800194e: 60fb str r3, [r7, #12]
|
|
|
|
/* Reset the Output Compare Mode Bits */
|
|
tmpccmrx &= ~TIM_CCMR1_OC1M;
|
|
8001950: 68fb ldr r3, [r7, #12]
|
|
8001952: f023 0370 bic.w r3, r3, #112 ; 0x70
|
|
8001956: 60fb str r3, [r7, #12]
|
|
tmpccmrx &= ~TIM_CCMR1_CC1S;
|
|
8001958: 68fb ldr r3, [r7, #12]
|
|
800195a: f023 0303 bic.w r3, r3, #3
|
|
800195e: 60fb str r3, [r7, #12]
|
|
/* Select the Output Compare Mode */
|
|
tmpccmrx |= OC_Config->OCMode;
|
|
8001960: 683b ldr r3, [r7, #0]
|
|
8001962: 681b ldr r3, [r3, #0]
|
|
8001964: 68fa ldr r2, [r7, #12]
|
|
8001966: 4313 orrs r3, r2
|
|
8001968: 60fb str r3, [r7, #12]
|
|
|
|
/* Reset the Output Polarity level */
|
|
tmpccer &= ~TIM_CCER_CC1P;
|
|
800196a: 697b ldr r3, [r7, #20]
|
|
800196c: f023 0302 bic.w r3, r3, #2
|
|
8001970: 617b str r3, [r7, #20]
|
|
/* Set the Output Compare Polarity */
|
|
tmpccer |= OC_Config->OCPolarity;
|
|
8001972: 683b ldr r3, [r7, #0]
|
|
8001974: 689b ldr r3, [r3, #8]
|
|
8001976: 697a ldr r2, [r7, #20]
|
|
8001978: 4313 orrs r3, r2
|
|
800197a: 617b str r3, [r7, #20]
|
|
|
|
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
|
|
800197c: 687b ldr r3, [r7, #4]
|
|
800197e: 4a1c ldr r2, [pc, #112] ; (80019f0 <TIM_OC1_SetConfig+0xc8>)
|
|
8001980: 4293 cmp r3, r2
|
|
8001982: d10c bne.n 800199e <TIM_OC1_SetConfig+0x76>
|
|
{
|
|
/* Check parameters */
|
|
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
|
|
|
|
/* Reset the Output N Polarity level */
|
|
tmpccer &= ~TIM_CCER_CC1NP;
|
|
8001984: 697b ldr r3, [r7, #20]
|
|
8001986: f023 0308 bic.w r3, r3, #8
|
|
800198a: 617b str r3, [r7, #20]
|
|
/* Set the Output N Polarity */
|
|
tmpccer |= OC_Config->OCNPolarity;
|
|
800198c: 683b ldr r3, [r7, #0]
|
|
800198e: 68db ldr r3, [r3, #12]
|
|
8001990: 697a ldr r2, [r7, #20]
|
|
8001992: 4313 orrs r3, r2
|
|
8001994: 617b str r3, [r7, #20]
|
|
/* Reset the Output N State */
|
|
tmpccer &= ~TIM_CCER_CC1NE;
|
|
8001996: 697b ldr r3, [r7, #20]
|
|
8001998: f023 0304 bic.w r3, r3, #4
|
|
800199c: 617b str r3, [r7, #20]
|
|
}
|
|
|
|
if (IS_TIM_BREAK_INSTANCE(TIMx))
|
|
800199e: 687b ldr r3, [r7, #4]
|
|
80019a0: 4a13 ldr r2, [pc, #76] ; (80019f0 <TIM_OC1_SetConfig+0xc8>)
|
|
80019a2: 4293 cmp r3, r2
|
|
80019a4: d111 bne.n 80019ca <TIM_OC1_SetConfig+0xa2>
|
|
/* Check parameters */
|
|
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
|
|
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
|
|
|
|
/* Reset the Output Compare and Output Compare N IDLE State */
|
|
tmpcr2 &= ~TIM_CR2_OIS1;
|
|
80019a6: 693b ldr r3, [r7, #16]
|
|
80019a8: f423 7380 bic.w r3, r3, #256 ; 0x100
|
|
80019ac: 613b str r3, [r7, #16]
|
|
tmpcr2 &= ~TIM_CR2_OIS1N;
|
|
80019ae: 693b ldr r3, [r7, #16]
|
|
80019b0: f423 7300 bic.w r3, r3, #512 ; 0x200
|
|
80019b4: 613b str r3, [r7, #16]
|
|
/* Set the Output Idle state */
|
|
tmpcr2 |= OC_Config->OCIdleState;
|
|
80019b6: 683b ldr r3, [r7, #0]
|
|
80019b8: 695b ldr r3, [r3, #20]
|
|
80019ba: 693a ldr r2, [r7, #16]
|
|
80019bc: 4313 orrs r3, r2
|
|
80019be: 613b str r3, [r7, #16]
|
|
/* Set the Output N Idle state */
|
|
tmpcr2 |= OC_Config->OCNIdleState;
|
|
80019c0: 683b ldr r3, [r7, #0]
|
|
80019c2: 699b ldr r3, [r3, #24]
|
|
80019c4: 693a ldr r2, [r7, #16]
|
|
80019c6: 4313 orrs r3, r2
|
|
80019c8: 613b str r3, [r7, #16]
|
|
}
|
|
|
|
/* Write to TIMx CR2 */
|
|
TIMx->CR2 = tmpcr2;
|
|
80019ca: 687b ldr r3, [r7, #4]
|
|
80019cc: 693a ldr r2, [r7, #16]
|
|
80019ce: 605a str r2, [r3, #4]
|
|
|
|
/* Write to TIMx CCMR1 */
|
|
TIMx->CCMR1 = tmpccmrx;
|
|
80019d0: 687b ldr r3, [r7, #4]
|
|
80019d2: 68fa ldr r2, [r7, #12]
|
|
80019d4: 619a str r2, [r3, #24]
|
|
|
|
/* Set the Capture Compare Register value */
|
|
TIMx->CCR1 = OC_Config->Pulse;
|
|
80019d6: 683b ldr r3, [r7, #0]
|
|
80019d8: 685a ldr r2, [r3, #4]
|
|
80019da: 687b ldr r3, [r7, #4]
|
|
80019dc: 635a str r2, [r3, #52] ; 0x34
|
|
|
|
/* Write to TIMx CCER */
|
|
TIMx->CCER = tmpccer;
|
|
80019de: 687b ldr r3, [r7, #4]
|
|
80019e0: 697a ldr r2, [r7, #20]
|
|
80019e2: 621a str r2, [r3, #32]
|
|
}
|
|
80019e4: bf00 nop
|
|
80019e6: 371c adds r7, #28
|
|
80019e8: 46bd mov sp, r7
|
|
80019ea: bc80 pop {r7}
|
|
80019ec: 4770 bx lr
|
|
80019ee: bf00 nop
|
|
80019f0: 40012c00 .word 0x40012c00
|
|
|
|
080019f4 <TIM_OC2_SetConfig>:
|
|
* @param TIMx to select the TIM peripheral
|
|
* @param OC_Config The output configuration structure
|
|
* @retval None
|
|
*/
|
|
void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
|
|
{
|
|
80019f4: b480 push {r7}
|
|
80019f6: b087 sub sp, #28
|
|
80019f8: af00 add r7, sp, #0
|
|
80019fa: 6078 str r0, [r7, #4]
|
|
80019fc: 6039 str r1, [r7, #0]
|
|
uint32_t tmpccmrx;
|
|
uint32_t tmpccer;
|
|
uint32_t tmpcr2;
|
|
|
|
/* Disable the Channel 2: Reset the CC2E Bit */
|
|
TIMx->CCER &= ~TIM_CCER_CC2E;
|
|
80019fe: 687b ldr r3, [r7, #4]
|
|
8001a00: 6a1b ldr r3, [r3, #32]
|
|
8001a02: f023 0210 bic.w r2, r3, #16
|
|
8001a06: 687b ldr r3, [r7, #4]
|
|
8001a08: 621a str r2, [r3, #32]
|
|
|
|
/* Get the TIMx CCER register value */
|
|
tmpccer = TIMx->CCER;
|
|
8001a0a: 687b ldr r3, [r7, #4]
|
|
8001a0c: 6a1b ldr r3, [r3, #32]
|
|
8001a0e: 617b str r3, [r7, #20]
|
|
/* Get the TIMx CR2 register value */
|
|
tmpcr2 = TIMx->CR2;
|
|
8001a10: 687b ldr r3, [r7, #4]
|
|
8001a12: 685b ldr r3, [r3, #4]
|
|
8001a14: 613b str r3, [r7, #16]
|
|
|
|
/* Get the TIMx CCMR1 register value */
|
|
tmpccmrx = TIMx->CCMR1;
|
|
8001a16: 687b ldr r3, [r7, #4]
|
|
8001a18: 699b ldr r3, [r3, #24]
|
|
8001a1a: 60fb str r3, [r7, #12]
|
|
|
|
/* Reset the Output Compare mode and Capture/Compare selection Bits */
|
|
tmpccmrx &= ~TIM_CCMR1_OC2M;
|
|
8001a1c: 68fb ldr r3, [r7, #12]
|
|
8001a1e: f423 43e0 bic.w r3, r3, #28672 ; 0x7000
|
|
8001a22: 60fb str r3, [r7, #12]
|
|
tmpccmrx &= ~TIM_CCMR1_CC2S;
|
|
8001a24: 68fb ldr r3, [r7, #12]
|
|
8001a26: f423 7340 bic.w r3, r3, #768 ; 0x300
|
|
8001a2a: 60fb str r3, [r7, #12]
|
|
|
|
/* Select the Output Compare Mode */
|
|
tmpccmrx |= (OC_Config->OCMode << 8U);
|
|
8001a2c: 683b ldr r3, [r7, #0]
|
|
8001a2e: 681b ldr r3, [r3, #0]
|
|
8001a30: 021b lsls r3, r3, #8
|
|
8001a32: 68fa ldr r2, [r7, #12]
|
|
8001a34: 4313 orrs r3, r2
|
|
8001a36: 60fb str r3, [r7, #12]
|
|
|
|
/* Reset the Output Polarity level */
|
|
tmpccer &= ~TIM_CCER_CC2P;
|
|
8001a38: 697b ldr r3, [r7, #20]
|
|
8001a3a: f023 0320 bic.w r3, r3, #32
|
|
8001a3e: 617b str r3, [r7, #20]
|
|
/* Set the Output Compare Polarity */
|
|
tmpccer |= (OC_Config->OCPolarity << 4U);
|
|
8001a40: 683b ldr r3, [r7, #0]
|
|
8001a42: 689b ldr r3, [r3, #8]
|
|
8001a44: 011b lsls r3, r3, #4
|
|
8001a46: 697a ldr r2, [r7, #20]
|
|
8001a48: 4313 orrs r3, r2
|
|
8001a4a: 617b str r3, [r7, #20]
|
|
|
|
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
|
|
8001a4c: 687b ldr r3, [r7, #4]
|
|
8001a4e: 4a1d ldr r2, [pc, #116] ; (8001ac4 <TIM_OC2_SetConfig+0xd0>)
|
|
8001a50: 4293 cmp r3, r2
|
|
8001a52: d10d bne.n 8001a70 <TIM_OC2_SetConfig+0x7c>
|
|
{
|
|
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
|
|
|
|
/* Reset the Output N Polarity level */
|
|
tmpccer &= ~TIM_CCER_CC2NP;
|
|
8001a54: 697b ldr r3, [r7, #20]
|
|
8001a56: f023 0380 bic.w r3, r3, #128 ; 0x80
|
|
8001a5a: 617b str r3, [r7, #20]
|
|
/* Set the Output N Polarity */
|
|
tmpccer |= (OC_Config->OCNPolarity << 4U);
|
|
8001a5c: 683b ldr r3, [r7, #0]
|
|
8001a5e: 68db ldr r3, [r3, #12]
|
|
8001a60: 011b lsls r3, r3, #4
|
|
8001a62: 697a ldr r2, [r7, #20]
|
|
8001a64: 4313 orrs r3, r2
|
|
8001a66: 617b str r3, [r7, #20]
|
|
/* Reset the Output N State */
|
|
tmpccer &= ~TIM_CCER_CC2NE;
|
|
8001a68: 697b ldr r3, [r7, #20]
|
|
8001a6a: f023 0340 bic.w r3, r3, #64 ; 0x40
|
|
8001a6e: 617b str r3, [r7, #20]
|
|
|
|
}
|
|
|
|
if (IS_TIM_BREAK_INSTANCE(TIMx))
|
|
8001a70: 687b ldr r3, [r7, #4]
|
|
8001a72: 4a14 ldr r2, [pc, #80] ; (8001ac4 <TIM_OC2_SetConfig+0xd0>)
|
|
8001a74: 4293 cmp r3, r2
|
|
8001a76: d113 bne.n 8001aa0 <TIM_OC2_SetConfig+0xac>
|
|
/* Check parameters */
|
|
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
|
|
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
|
|
|
|
/* Reset the Output Compare and Output Compare N IDLE State */
|
|
tmpcr2 &= ~TIM_CR2_OIS2;
|
|
8001a78: 693b ldr r3, [r7, #16]
|
|
8001a7a: f423 6380 bic.w r3, r3, #1024 ; 0x400
|
|
8001a7e: 613b str r3, [r7, #16]
|
|
tmpcr2 &= ~TIM_CR2_OIS2N;
|
|
8001a80: 693b ldr r3, [r7, #16]
|
|
8001a82: f423 6300 bic.w r3, r3, #2048 ; 0x800
|
|
8001a86: 613b str r3, [r7, #16]
|
|
/* Set the Output Idle state */
|
|
tmpcr2 |= (OC_Config->OCIdleState << 2U);
|
|
8001a88: 683b ldr r3, [r7, #0]
|
|
8001a8a: 695b ldr r3, [r3, #20]
|
|
8001a8c: 009b lsls r3, r3, #2
|
|
8001a8e: 693a ldr r2, [r7, #16]
|
|
8001a90: 4313 orrs r3, r2
|
|
8001a92: 613b str r3, [r7, #16]
|
|
/* Set the Output N Idle state */
|
|
tmpcr2 |= (OC_Config->OCNIdleState << 2U);
|
|
8001a94: 683b ldr r3, [r7, #0]
|
|
8001a96: 699b ldr r3, [r3, #24]
|
|
8001a98: 009b lsls r3, r3, #2
|
|
8001a9a: 693a ldr r2, [r7, #16]
|
|
8001a9c: 4313 orrs r3, r2
|
|
8001a9e: 613b str r3, [r7, #16]
|
|
}
|
|
|
|
/* Write to TIMx CR2 */
|
|
TIMx->CR2 = tmpcr2;
|
|
8001aa0: 687b ldr r3, [r7, #4]
|
|
8001aa2: 693a ldr r2, [r7, #16]
|
|
8001aa4: 605a str r2, [r3, #4]
|
|
|
|
/* Write to TIMx CCMR1 */
|
|
TIMx->CCMR1 = tmpccmrx;
|
|
8001aa6: 687b ldr r3, [r7, #4]
|
|
8001aa8: 68fa ldr r2, [r7, #12]
|
|
8001aaa: 619a str r2, [r3, #24]
|
|
|
|
/* Set the Capture Compare Register value */
|
|
TIMx->CCR2 = OC_Config->Pulse;
|
|
8001aac: 683b ldr r3, [r7, #0]
|
|
8001aae: 685a ldr r2, [r3, #4]
|
|
8001ab0: 687b ldr r3, [r7, #4]
|
|
8001ab2: 639a str r2, [r3, #56] ; 0x38
|
|
|
|
/* Write to TIMx CCER */
|
|
TIMx->CCER = tmpccer;
|
|
8001ab4: 687b ldr r3, [r7, #4]
|
|
8001ab6: 697a ldr r2, [r7, #20]
|
|
8001ab8: 621a str r2, [r3, #32]
|
|
}
|
|
8001aba: bf00 nop
|
|
8001abc: 371c adds r7, #28
|
|
8001abe: 46bd mov sp, r7
|
|
8001ac0: bc80 pop {r7}
|
|
8001ac2: 4770 bx lr
|
|
8001ac4: 40012c00 .word 0x40012c00
|
|
|
|
08001ac8 <TIM_OC3_SetConfig>:
|
|
* @param TIMx to select the TIM peripheral
|
|
* @param OC_Config The output configuration structure
|
|
* @retval None
|
|
*/
|
|
static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
|
|
{
|
|
8001ac8: b480 push {r7}
|
|
8001aca: b087 sub sp, #28
|
|
8001acc: af00 add r7, sp, #0
|
|
8001ace: 6078 str r0, [r7, #4]
|
|
8001ad0: 6039 str r1, [r7, #0]
|
|
uint32_t tmpccmrx;
|
|
uint32_t tmpccer;
|
|
uint32_t tmpcr2;
|
|
|
|
/* Disable the Channel 3: Reset the CC2E Bit */
|
|
TIMx->CCER &= ~TIM_CCER_CC3E;
|
|
8001ad2: 687b ldr r3, [r7, #4]
|
|
8001ad4: 6a1b ldr r3, [r3, #32]
|
|
8001ad6: f423 7280 bic.w r2, r3, #256 ; 0x100
|
|
8001ada: 687b ldr r3, [r7, #4]
|
|
8001adc: 621a str r2, [r3, #32]
|
|
|
|
/* Get the TIMx CCER register value */
|
|
tmpccer = TIMx->CCER;
|
|
8001ade: 687b ldr r3, [r7, #4]
|
|
8001ae0: 6a1b ldr r3, [r3, #32]
|
|
8001ae2: 617b str r3, [r7, #20]
|
|
/* Get the TIMx CR2 register value */
|
|
tmpcr2 = TIMx->CR2;
|
|
8001ae4: 687b ldr r3, [r7, #4]
|
|
8001ae6: 685b ldr r3, [r3, #4]
|
|
8001ae8: 613b str r3, [r7, #16]
|
|
|
|
/* Get the TIMx CCMR2 register value */
|
|
tmpccmrx = TIMx->CCMR2;
|
|
8001aea: 687b ldr r3, [r7, #4]
|
|
8001aec: 69db ldr r3, [r3, #28]
|
|
8001aee: 60fb str r3, [r7, #12]
|
|
|
|
/* Reset the Output Compare mode and Capture/Compare selection Bits */
|
|
tmpccmrx &= ~TIM_CCMR2_OC3M;
|
|
8001af0: 68fb ldr r3, [r7, #12]
|
|
8001af2: f023 0370 bic.w r3, r3, #112 ; 0x70
|
|
8001af6: 60fb str r3, [r7, #12]
|
|
tmpccmrx &= ~TIM_CCMR2_CC3S;
|
|
8001af8: 68fb ldr r3, [r7, #12]
|
|
8001afa: f023 0303 bic.w r3, r3, #3
|
|
8001afe: 60fb str r3, [r7, #12]
|
|
/* Select the Output Compare Mode */
|
|
tmpccmrx |= OC_Config->OCMode;
|
|
8001b00: 683b ldr r3, [r7, #0]
|
|
8001b02: 681b ldr r3, [r3, #0]
|
|
8001b04: 68fa ldr r2, [r7, #12]
|
|
8001b06: 4313 orrs r3, r2
|
|
8001b08: 60fb str r3, [r7, #12]
|
|
|
|
/* Reset the Output Polarity level */
|
|
tmpccer &= ~TIM_CCER_CC3P;
|
|
8001b0a: 697b ldr r3, [r7, #20]
|
|
8001b0c: f423 7300 bic.w r3, r3, #512 ; 0x200
|
|
8001b10: 617b str r3, [r7, #20]
|
|
/* Set the Output Compare Polarity */
|
|
tmpccer |= (OC_Config->OCPolarity << 8U);
|
|
8001b12: 683b ldr r3, [r7, #0]
|
|
8001b14: 689b ldr r3, [r3, #8]
|
|
8001b16: 021b lsls r3, r3, #8
|
|
8001b18: 697a ldr r2, [r7, #20]
|
|
8001b1a: 4313 orrs r3, r2
|
|
8001b1c: 617b str r3, [r7, #20]
|
|
|
|
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
|
|
8001b1e: 687b ldr r3, [r7, #4]
|
|
8001b20: 4a1d ldr r2, [pc, #116] ; (8001b98 <TIM_OC3_SetConfig+0xd0>)
|
|
8001b22: 4293 cmp r3, r2
|
|
8001b24: d10d bne.n 8001b42 <TIM_OC3_SetConfig+0x7a>
|
|
{
|
|
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
|
|
|
|
/* Reset the Output N Polarity level */
|
|
tmpccer &= ~TIM_CCER_CC3NP;
|
|
8001b26: 697b ldr r3, [r7, #20]
|
|
8001b28: f423 6300 bic.w r3, r3, #2048 ; 0x800
|
|
8001b2c: 617b str r3, [r7, #20]
|
|
/* Set the Output N Polarity */
|
|
tmpccer |= (OC_Config->OCNPolarity << 8U);
|
|
8001b2e: 683b ldr r3, [r7, #0]
|
|
8001b30: 68db ldr r3, [r3, #12]
|
|
8001b32: 021b lsls r3, r3, #8
|
|
8001b34: 697a ldr r2, [r7, #20]
|
|
8001b36: 4313 orrs r3, r2
|
|
8001b38: 617b str r3, [r7, #20]
|
|
/* Reset the Output N State */
|
|
tmpccer &= ~TIM_CCER_CC3NE;
|
|
8001b3a: 697b ldr r3, [r7, #20]
|
|
8001b3c: f423 6380 bic.w r3, r3, #1024 ; 0x400
|
|
8001b40: 617b str r3, [r7, #20]
|
|
}
|
|
|
|
if (IS_TIM_BREAK_INSTANCE(TIMx))
|
|
8001b42: 687b ldr r3, [r7, #4]
|
|
8001b44: 4a14 ldr r2, [pc, #80] ; (8001b98 <TIM_OC3_SetConfig+0xd0>)
|
|
8001b46: 4293 cmp r3, r2
|
|
8001b48: d113 bne.n 8001b72 <TIM_OC3_SetConfig+0xaa>
|
|
/* Check parameters */
|
|
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
|
|
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
|
|
|
|
/* Reset the Output Compare and Output Compare N IDLE State */
|
|
tmpcr2 &= ~TIM_CR2_OIS3;
|
|
8001b4a: 693b ldr r3, [r7, #16]
|
|
8001b4c: f423 5380 bic.w r3, r3, #4096 ; 0x1000
|
|
8001b50: 613b str r3, [r7, #16]
|
|
tmpcr2 &= ~TIM_CR2_OIS3N;
|
|
8001b52: 693b ldr r3, [r7, #16]
|
|
8001b54: f423 5300 bic.w r3, r3, #8192 ; 0x2000
|
|
8001b58: 613b str r3, [r7, #16]
|
|
/* Set the Output Idle state */
|
|
tmpcr2 |= (OC_Config->OCIdleState << 4U);
|
|
8001b5a: 683b ldr r3, [r7, #0]
|
|
8001b5c: 695b ldr r3, [r3, #20]
|
|
8001b5e: 011b lsls r3, r3, #4
|
|
8001b60: 693a ldr r2, [r7, #16]
|
|
8001b62: 4313 orrs r3, r2
|
|
8001b64: 613b str r3, [r7, #16]
|
|
/* Set the Output N Idle state */
|
|
tmpcr2 |= (OC_Config->OCNIdleState << 4U);
|
|
8001b66: 683b ldr r3, [r7, #0]
|
|
8001b68: 699b ldr r3, [r3, #24]
|
|
8001b6a: 011b lsls r3, r3, #4
|
|
8001b6c: 693a ldr r2, [r7, #16]
|
|
8001b6e: 4313 orrs r3, r2
|
|
8001b70: 613b str r3, [r7, #16]
|
|
}
|
|
|
|
/* Write to TIMx CR2 */
|
|
TIMx->CR2 = tmpcr2;
|
|
8001b72: 687b ldr r3, [r7, #4]
|
|
8001b74: 693a ldr r2, [r7, #16]
|
|
8001b76: 605a str r2, [r3, #4]
|
|
|
|
/* Write to TIMx CCMR2 */
|
|
TIMx->CCMR2 = tmpccmrx;
|
|
8001b78: 687b ldr r3, [r7, #4]
|
|
8001b7a: 68fa ldr r2, [r7, #12]
|
|
8001b7c: 61da str r2, [r3, #28]
|
|
|
|
/* Set the Capture Compare Register value */
|
|
TIMx->CCR3 = OC_Config->Pulse;
|
|
8001b7e: 683b ldr r3, [r7, #0]
|
|
8001b80: 685a ldr r2, [r3, #4]
|
|
8001b82: 687b ldr r3, [r7, #4]
|
|
8001b84: 63da str r2, [r3, #60] ; 0x3c
|
|
|
|
/* Write to TIMx CCER */
|
|
TIMx->CCER = tmpccer;
|
|
8001b86: 687b ldr r3, [r7, #4]
|
|
8001b88: 697a ldr r2, [r7, #20]
|
|
8001b8a: 621a str r2, [r3, #32]
|
|
}
|
|
8001b8c: bf00 nop
|
|
8001b8e: 371c adds r7, #28
|
|
8001b90: 46bd mov sp, r7
|
|
8001b92: bc80 pop {r7}
|
|
8001b94: 4770 bx lr
|
|
8001b96: bf00 nop
|
|
8001b98: 40012c00 .word 0x40012c00
|
|
|
|
08001b9c <TIM_OC4_SetConfig>:
|
|
* @param TIMx to select the TIM peripheral
|
|
* @param OC_Config The output configuration structure
|
|
* @retval None
|
|
*/
|
|
static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
|
|
{
|
|
8001b9c: b480 push {r7}
|
|
8001b9e: b087 sub sp, #28
|
|
8001ba0: af00 add r7, sp, #0
|
|
8001ba2: 6078 str r0, [r7, #4]
|
|
8001ba4: 6039 str r1, [r7, #0]
|
|
uint32_t tmpccmrx;
|
|
uint32_t tmpccer;
|
|
uint32_t tmpcr2;
|
|
|
|
/* Disable the Channel 4: Reset the CC4E Bit */
|
|
TIMx->CCER &= ~TIM_CCER_CC4E;
|
|
8001ba6: 687b ldr r3, [r7, #4]
|
|
8001ba8: 6a1b ldr r3, [r3, #32]
|
|
8001baa: f423 5280 bic.w r2, r3, #4096 ; 0x1000
|
|
8001bae: 687b ldr r3, [r7, #4]
|
|
8001bb0: 621a str r2, [r3, #32]
|
|
|
|
/* Get the TIMx CCER register value */
|
|
tmpccer = TIMx->CCER;
|
|
8001bb2: 687b ldr r3, [r7, #4]
|
|
8001bb4: 6a1b ldr r3, [r3, #32]
|
|
8001bb6: 613b str r3, [r7, #16]
|
|
/* Get the TIMx CR2 register value */
|
|
tmpcr2 = TIMx->CR2;
|
|
8001bb8: 687b ldr r3, [r7, #4]
|
|
8001bba: 685b ldr r3, [r3, #4]
|
|
8001bbc: 617b str r3, [r7, #20]
|
|
|
|
/* Get the TIMx CCMR2 register value */
|
|
tmpccmrx = TIMx->CCMR2;
|
|
8001bbe: 687b ldr r3, [r7, #4]
|
|
8001bc0: 69db ldr r3, [r3, #28]
|
|
8001bc2: 60fb str r3, [r7, #12]
|
|
|
|
/* Reset the Output Compare mode and Capture/Compare selection Bits */
|
|
tmpccmrx &= ~TIM_CCMR2_OC4M;
|
|
8001bc4: 68fb ldr r3, [r7, #12]
|
|
8001bc6: f423 43e0 bic.w r3, r3, #28672 ; 0x7000
|
|
8001bca: 60fb str r3, [r7, #12]
|
|
tmpccmrx &= ~TIM_CCMR2_CC4S;
|
|
8001bcc: 68fb ldr r3, [r7, #12]
|
|
8001bce: f423 7340 bic.w r3, r3, #768 ; 0x300
|
|
8001bd2: 60fb str r3, [r7, #12]
|
|
|
|
/* Select the Output Compare Mode */
|
|
tmpccmrx |= (OC_Config->OCMode << 8U);
|
|
8001bd4: 683b ldr r3, [r7, #0]
|
|
8001bd6: 681b ldr r3, [r3, #0]
|
|
8001bd8: 021b lsls r3, r3, #8
|
|
8001bda: 68fa ldr r2, [r7, #12]
|
|
8001bdc: 4313 orrs r3, r2
|
|
8001bde: 60fb str r3, [r7, #12]
|
|
|
|
/* Reset the Output Polarity level */
|
|
tmpccer &= ~TIM_CCER_CC4P;
|
|
8001be0: 693b ldr r3, [r7, #16]
|
|
8001be2: f423 5300 bic.w r3, r3, #8192 ; 0x2000
|
|
8001be6: 613b str r3, [r7, #16]
|
|
/* Set the Output Compare Polarity */
|
|
tmpccer |= (OC_Config->OCPolarity << 12U);
|
|
8001be8: 683b ldr r3, [r7, #0]
|
|
8001bea: 689b ldr r3, [r3, #8]
|
|
8001bec: 031b lsls r3, r3, #12
|
|
8001bee: 693a ldr r2, [r7, #16]
|
|
8001bf0: 4313 orrs r3, r2
|
|
8001bf2: 613b str r3, [r7, #16]
|
|
|
|
if (IS_TIM_BREAK_INSTANCE(TIMx))
|
|
8001bf4: 687b ldr r3, [r7, #4]
|
|
8001bf6: 4a0f ldr r2, [pc, #60] ; (8001c34 <TIM_OC4_SetConfig+0x98>)
|
|
8001bf8: 4293 cmp r3, r2
|
|
8001bfa: d109 bne.n 8001c10 <TIM_OC4_SetConfig+0x74>
|
|
{
|
|
/* Check parameters */
|
|
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
|
|
|
|
/* Reset the Output Compare IDLE State */
|
|
tmpcr2 &= ~TIM_CR2_OIS4;
|
|
8001bfc: 697b ldr r3, [r7, #20]
|
|
8001bfe: f423 4380 bic.w r3, r3, #16384 ; 0x4000
|
|
8001c02: 617b str r3, [r7, #20]
|
|
|
|
/* Set the Output Idle state */
|
|
tmpcr2 |= (OC_Config->OCIdleState << 6U);
|
|
8001c04: 683b ldr r3, [r7, #0]
|
|
8001c06: 695b ldr r3, [r3, #20]
|
|
8001c08: 019b lsls r3, r3, #6
|
|
8001c0a: 697a ldr r2, [r7, #20]
|
|
8001c0c: 4313 orrs r3, r2
|
|
8001c0e: 617b str r3, [r7, #20]
|
|
}
|
|
|
|
/* Write to TIMx CR2 */
|
|
TIMx->CR2 = tmpcr2;
|
|
8001c10: 687b ldr r3, [r7, #4]
|
|
8001c12: 697a ldr r2, [r7, #20]
|
|
8001c14: 605a str r2, [r3, #4]
|
|
|
|
/* Write to TIMx CCMR2 */
|
|
TIMx->CCMR2 = tmpccmrx;
|
|
8001c16: 687b ldr r3, [r7, #4]
|
|
8001c18: 68fa ldr r2, [r7, #12]
|
|
8001c1a: 61da str r2, [r3, #28]
|
|
|
|
/* Set the Capture Compare Register value */
|
|
TIMx->CCR4 = OC_Config->Pulse;
|
|
8001c1c: 683b ldr r3, [r7, #0]
|
|
8001c1e: 685a ldr r2, [r3, #4]
|
|
8001c20: 687b ldr r3, [r7, #4]
|
|
8001c22: 641a str r2, [r3, #64] ; 0x40
|
|
|
|
/* Write to TIMx CCER */
|
|
TIMx->CCER = tmpccer;
|
|
8001c24: 687b ldr r3, [r7, #4]
|
|
8001c26: 693a ldr r2, [r7, #16]
|
|
8001c28: 621a str r2, [r3, #32]
|
|
}
|
|
8001c2a: bf00 nop
|
|
8001c2c: 371c adds r7, #28
|
|
8001c2e: 46bd mov sp, r7
|
|
8001c30: bc80 pop {r7}
|
|
8001c32: 4770 bx lr
|
|
8001c34: 40012c00 .word 0x40012c00
|
|
|
|
08001c38 <TIM_TI1_ConfigInputStage>:
|
|
* @param TIM_ICFilter Specifies the Input Capture Filter.
|
|
* This parameter must be a value between 0x00 and 0x0F.
|
|
* @retval None
|
|
*/
|
|
static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
|
|
{
|
|
8001c38: b480 push {r7}
|
|
8001c3a: b087 sub sp, #28
|
|
8001c3c: af00 add r7, sp, #0
|
|
8001c3e: 60f8 str r0, [r7, #12]
|
|
8001c40: 60b9 str r1, [r7, #8]
|
|
8001c42: 607a str r2, [r7, #4]
|
|
uint32_t tmpccmr1;
|
|
uint32_t tmpccer;
|
|
|
|
/* Disable the Channel 1: Reset the CC1E Bit */
|
|
tmpccer = TIMx->CCER;
|
|
8001c44: 68fb ldr r3, [r7, #12]
|
|
8001c46: 6a1b ldr r3, [r3, #32]
|
|
8001c48: 617b str r3, [r7, #20]
|
|
TIMx->CCER &= ~TIM_CCER_CC1E;
|
|
8001c4a: 68fb ldr r3, [r7, #12]
|
|
8001c4c: 6a1b ldr r3, [r3, #32]
|
|
8001c4e: f023 0201 bic.w r2, r3, #1
|
|
8001c52: 68fb ldr r3, [r7, #12]
|
|
8001c54: 621a str r2, [r3, #32]
|
|
tmpccmr1 = TIMx->CCMR1;
|
|
8001c56: 68fb ldr r3, [r7, #12]
|
|
8001c58: 699b ldr r3, [r3, #24]
|
|
8001c5a: 613b str r3, [r7, #16]
|
|
|
|
/* Set the filter */
|
|
tmpccmr1 &= ~TIM_CCMR1_IC1F;
|
|
8001c5c: 693b ldr r3, [r7, #16]
|
|
8001c5e: f023 03f0 bic.w r3, r3, #240 ; 0xf0
|
|
8001c62: 613b str r3, [r7, #16]
|
|
tmpccmr1 |= (TIM_ICFilter << 4U);
|
|
8001c64: 687b ldr r3, [r7, #4]
|
|
8001c66: 011b lsls r3, r3, #4
|
|
8001c68: 693a ldr r2, [r7, #16]
|
|
8001c6a: 4313 orrs r3, r2
|
|
8001c6c: 613b str r3, [r7, #16]
|
|
|
|
/* Select the Polarity and set the CC1E Bit */
|
|
tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
|
|
8001c6e: 697b ldr r3, [r7, #20]
|
|
8001c70: f023 030a bic.w r3, r3, #10
|
|
8001c74: 617b str r3, [r7, #20]
|
|
tmpccer |= TIM_ICPolarity;
|
|
8001c76: 697a ldr r2, [r7, #20]
|
|
8001c78: 68bb ldr r3, [r7, #8]
|
|
8001c7a: 4313 orrs r3, r2
|
|
8001c7c: 617b str r3, [r7, #20]
|
|
|
|
/* Write to TIMx CCMR1 and CCER registers */
|
|
TIMx->CCMR1 = tmpccmr1;
|
|
8001c7e: 68fb ldr r3, [r7, #12]
|
|
8001c80: 693a ldr r2, [r7, #16]
|
|
8001c82: 619a str r2, [r3, #24]
|
|
TIMx->CCER = tmpccer;
|
|
8001c84: 68fb ldr r3, [r7, #12]
|
|
8001c86: 697a ldr r2, [r7, #20]
|
|
8001c88: 621a str r2, [r3, #32]
|
|
}
|
|
8001c8a: bf00 nop
|
|
8001c8c: 371c adds r7, #28
|
|
8001c8e: 46bd mov sp, r7
|
|
8001c90: bc80 pop {r7}
|
|
8001c92: 4770 bx lr
|
|
|
|
08001c94 <TIM_TI2_ConfigInputStage>:
|
|
* @param TIM_ICFilter Specifies the Input Capture Filter.
|
|
* This parameter must be a value between 0x00 and 0x0F.
|
|
* @retval None
|
|
*/
|
|
static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
|
|
{
|
|
8001c94: b480 push {r7}
|
|
8001c96: b087 sub sp, #28
|
|
8001c98: af00 add r7, sp, #0
|
|
8001c9a: 60f8 str r0, [r7, #12]
|
|
8001c9c: 60b9 str r1, [r7, #8]
|
|
8001c9e: 607a str r2, [r7, #4]
|
|
uint32_t tmpccmr1;
|
|
uint32_t tmpccer;
|
|
|
|
/* Disable the Channel 2: Reset the CC2E Bit */
|
|
TIMx->CCER &= ~TIM_CCER_CC2E;
|
|
8001ca0: 68fb ldr r3, [r7, #12]
|
|
8001ca2: 6a1b ldr r3, [r3, #32]
|
|
8001ca4: f023 0210 bic.w r2, r3, #16
|
|
8001ca8: 68fb ldr r3, [r7, #12]
|
|
8001caa: 621a str r2, [r3, #32]
|
|
tmpccmr1 = TIMx->CCMR1;
|
|
8001cac: 68fb ldr r3, [r7, #12]
|
|
8001cae: 699b ldr r3, [r3, #24]
|
|
8001cb0: 617b str r3, [r7, #20]
|
|
tmpccer = TIMx->CCER;
|
|
8001cb2: 68fb ldr r3, [r7, #12]
|
|
8001cb4: 6a1b ldr r3, [r3, #32]
|
|
8001cb6: 613b str r3, [r7, #16]
|
|
|
|
/* Set the filter */
|
|
tmpccmr1 &= ~TIM_CCMR1_IC2F;
|
|
8001cb8: 697b ldr r3, [r7, #20]
|
|
8001cba: f423 4370 bic.w r3, r3, #61440 ; 0xf000
|
|
8001cbe: 617b str r3, [r7, #20]
|
|
tmpccmr1 |= (TIM_ICFilter << 12U);
|
|
8001cc0: 687b ldr r3, [r7, #4]
|
|
8001cc2: 031b lsls r3, r3, #12
|
|
8001cc4: 697a ldr r2, [r7, #20]
|
|
8001cc6: 4313 orrs r3, r2
|
|
8001cc8: 617b str r3, [r7, #20]
|
|
|
|
/* Select the Polarity and set the CC2E Bit */
|
|
tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
|
|
8001cca: 693b ldr r3, [r7, #16]
|
|
8001ccc: f023 03a0 bic.w r3, r3, #160 ; 0xa0
|
|
8001cd0: 613b str r3, [r7, #16]
|
|
tmpccer |= (TIM_ICPolarity << 4U);
|
|
8001cd2: 68bb ldr r3, [r7, #8]
|
|
8001cd4: 011b lsls r3, r3, #4
|
|
8001cd6: 693a ldr r2, [r7, #16]
|
|
8001cd8: 4313 orrs r3, r2
|
|
8001cda: 613b str r3, [r7, #16]
|
|
|
|
/* Write to TIMx CCMR1 and CCER registers */
|
|
TIMx->CCMR1 = tmpccmr1 ;
|
|
8001cdc: 68fb ldr r3, [r7, #12]
|
|
8001cde: 697a ldr r2, [r7, #20]
|
|
8001ce0: 619a str r2, [r3, #24]
|
|
TIMx->CCER = tmpccer;
|
|
8001ce2: 68fb ldr r3, [r7, #12]
|
|
8001ce4: 693a ldr r2, [r7, #16]
|
|
8001ce6: 621a str r2, [r3, #32]
|
|
}
|
|
8001ce8: bf00 nop
|
|
8001cea: 371c adds r7, #28
|
|
8001cec: 46bd mov sp, r7
|
|
8001cee: bc80 pop {r7}
|
|
8001cf0: 4770 bx lr
|
|
|
|
08001cf2 <TIM_ITRx_SetConfig>:
|
|
* @arg TIM_TS_TI2FP2: Filtered Timer Input 2
|
|
* @arg TIM_TS_ETRF: External Trigger input
|
|
* @retval None
|
|
*/
|
|
static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource)
|
|
{
|
|
8001cf2: b480 push {r7}
|
|
8001cf4: b085 sub sp, #20
|
|
8001cf6: af00 add r7, sp, #0
|
|
8001cf8: 6078 str r0, [r7, #4]
|
|
8001cfa: 6039 str r1, [r7, #0]
|
|
uint32_t tmpsmcr;
|
|
|
|
/* Get the TIMx SMCR register value */
|
|
tmpsmcr = TIMx->SMCR;
|
|
8001cfc: 687b ldr r3, [r7, #4]
|
|
8001cfe: 689b ldr r3, [r3, #8]
|
|
8001d00: 60fb str r3, [r7, #12]
|
|
/* Reset the TS Bits */
|
|
tmpsmcr &= ~TIM_SMCR_TS;
|
|
8001d02: 68fb ldr r3, [r7, #12]
|
|
8001d04: f023 0370 bic.w r3, r3, #112 ; 0x70
|
|
8001d08: 60fb str r3, [r7, #12]
|
|
/* Set the Input Trigger source and the slave mode*/
|
|
tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1);
|
|
8001d0a: 683a ldr r2, [r7, #0]
|
|
8001d0c: 68fb ldr r3, [r7, #12]
|
|
8001d0e: 4313 orrs r3, r2
|
|
8001d10: f043 0307 orr.w r3, r3, #7
|
|
8001d14: 60fb str r3, [r7, #12]
|
|
/* Write to TIMx SMCR */
|
|
TIMx->SMCR = tmpsmcr;
|
|
8001d16: 687b ldr r3, [r7, #4]
|
|
8001d18: 68fa ldr r2, [r7, #12]
|
|
8001d1a: 609a str r2, [r3, #8]
|
|
}
|
|
8001d1c: bf00 nop
|
|
8001d1e: 3714 adds r7, #20
|
|
8001d20: 46bd mov sp, r7
|
|
8001d22: bc80 pop {r7}
|
|
8001d24: 4770 bx lr
|
|
|
|
08001d26 <TIM_ETR_SetConfig>:
|
|
* This parameter must be a value between 0x00 and 0x0F
|
|
* @retval None
|
|
*/
|
|
void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
|
|
uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
|
|
{
|
|
8001d26: b480 push {r7}
|
|
8001d28: b087 sub sp, #28
|
|
8001d2a: af00 add r7, sp, #0
|
|
8001d2c: 60f8 str r0, [r7, #12]
|
|
8001d2e: 60b9 str r1, [r7, #8]
|
|
8001d30: 607a str r2, [r7, #4]
|
|
8001d32: 603b str r3, [r7, #0]
|
|
uint32_t tmpsmcr;
|
|
|
|
tmpsmcr = TIMx->SMCR;
|
|
8001d34: 68fb ldr r3, [r7, #12]
|
|
8001d36: 689b ldr r3, [r3, #8]
|
|
8001d38: 617b str r3, [r7, #20]
|
|
|
|
/* Reset the ETR Bits */
|
|
tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
|
|
8001d3a: 697b ldr r3, [r7, #20]
|
|
8001d3c: f423 437f bic.w r3, r3, #65280 ; 0xff00
|
|
8001d40: 617b str r3, [r7, #20]
|
|
|
|
/* Set the Prescaler, the Filter value and the Polarity */
|
|
tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));
|
|
8001d42: 683b ldr r3, [r7, #0]
|
|
8001d44: 021a lsls r2, r3, #8
|
|
8001d46: 687b ldr r3, [r7, #4]
|
|
8001d48: 431a orrs r2, r3
|
|
8001d4a: 68bb ldr r3, [r7, #8]
|
|
8001d4c: 4313 orrs r3, r2
|
|
8001d4e: 697a ldr r2, [r7, #20]
|
|
8001d50: 4313 orrs r3, r2
|
|
8001d52: 617b str r3, [r7, #20]
|
|
|
|
/* Write to TIMx SMCR */
|
|
TIMx->SMCR = tmpsmcr;
|
|
8001d54: 68fb ldr r3, [r7, #12]
|
|
8001d56: 697a ldr r2, [r7, #20]
|
|
8001d58: 609a str r2, [r3, #8]
|
|
}
|
|
8001d5a: bf00 nop
|
|
8001d5c: 371c adds r7, #28
|
|
8001d5e: 46bd mov sp, r7
|
|
8001d60: bc80 pop {r7}
|
|
8001d62: 4770 bx lr
|
|
|
|
08001d64 <TIM_CCxChannelCmd>:
|
|
* @param ChannelState specifies the TIM Channel CCxE bit new state.
|
|
* This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE.
|
|
* @retval None
|
|
*/
|
|
void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)
|
|
{
|
|
8001d64: b480 push {r7}
|
|
8001d66: b087 sub sp, #28
|
|
8001d68: af00 add r7, sp, #0
|
|
8001d6a: 60f8 str r0, [r7, #12]
|
|
8001d6c: 60b9 str r1, [r7, #8]
|
|
8001d6e: 607a str r2, [r7, #4]
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_CC1_INSTANCE(TIMx));
|
|
assert_param(IS_TIM_CHANNELS(Channel));
|
|
|
|
tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */
|
|
8001d70: 68bb ldr r3, [r7, #8]
|
|
8001d72: f003 031f and.w r3, r3, #31
|
|
8001d76: 2201 movs r2, #1
|
|
8001d78: fa02 f303 lsl.w r3, r2, r3
|
|
8001d7c: 617b str r3, [r7, #20]
|
|
|
|
/* Reset the CCxE Bit */
|
|
TIMx->CCER &= ~tmp;
|
|
8001d7e: 68fb ldr r3, [r7, #12]
|
|
8001d80: 6a1a ldr r2, [r3, #32]
|
|
8001d82: 697b ldr r3, [r7, #20]
|
|
8001d84: 43db mvns r3, r3
|
|
8001d86: 401a ands r2, r3
|
|
8001d88: 68fb ldr r3, [r7, #12]
|
|
8001d8a: 621a str r2, [r3, #32]
|
|
|
|
/* Set or reset the CCxE Bit */
|
|
TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
|
|
8001d8c: 68fb ldr r3, [r7, #12]
|
|
8001d8e: 6a1a ldr r2, [r3, #32]
|
|
8001d90: 68bb ldr r3, [r7, #8]
|
|
8001d92: f003 031f and.w r3, r3, #31
|
|
8001d96: 6879 ldr r1, [r7, #4]
|
|
8001d98: fa01 f303 lsl.w r3, r1, r3
|
|
8001d9c: 431a orrs r2, r3
|
|
8001d9e: 68fb ldr r3, [r7, #12]
|
|
8001da0: 621a str r2, [r3, #32]
|
|
}
|
|
8001da2: bf00 nop
|
|
8001da4: 371c adds r7, #28
|
|
8001da6: 46bd mov sp, r7
|
|
8001da8: bc80 pop {r7}
|
|
8001daa: 4770 bx lr
|
|
|
|
08001dac <HAL_TIMEx_MasterConfigSynchronization>:
|
|
* mode.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
|
|
TIM_MasterConfigTypeDef *sMasterConfig)
|
|
{
|
|
8001dac: b480 push {r7}
|
|
8001dae: b085 sub sp, #20
|
|
8001db0: af00 add r7, sp, #0
|
|
8001db2: 6078 str r0, [r7, #4]
|
|
8001db4: 6039 str r1, [r7, #0]
|
|
assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
|
|
assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
|
|
assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
|
|
|
|
/* Check input state */
|
|
__HAL_LOCK(htim);
|
|
8001db6: 687b ldr r3, [r7, #4]
|
|
8001db8: f893 303c ldrb.w r3, [r3, #60] ; 0x3c
|
|
8001dbc: 2b01 cmp r3, #1
|
|
8001dbe: d101 bne.n 8001dc4 <HAL_TIMEx_MasterConfigSynchronization+0x18>
|
|
8001dc0: 2302 movs r3, #2
|
|
8001dc2: e046 b.n 8001e52 <HAL_TIMEx_MasterConfigSynchronization+0xa6>
|
|
8001dc4: 687b ldr r3, [r7, #4]
|
|
8001dc6: 2201 movs r2, #1
|
|
8001dc8: f883 203c strb.w r2, [r3, #60] ; 0x3c
|
|
|
|
/* Change the handler state */
|
|
htim->State = HAL_TIM_STATE_BUSY;
|
|
8001dcc: 687b ldr r3, [r7, #4]
|
|
8001dce: 2202 movs r2, #2
|
|
8001dd0: f883 203d strb.w r2, [r3, #61] ; 0x3d
|
|
|
|
/* Get the TIMx CR2 register value */
|
|
tmpcr2 = htim->Instance->CR2;
|
|
8001dd4: 687b ldr r3, [r7, #4]
|
|
8001dd6: 681b ldr r3, [r3, #0]
|
|
8001dd8: 685b ldr r3, [r3, #4]
|
|
8001dda: 60fb str r3, [r7, #12]
|
|
|
|
/* Get the TIMx SMCR register value */
|
|
tmpsmcr = htim->Instance->SMCR;
|
|
8001ddc: 687b ldr r3, [r7, #4]
|
|
8001dde: 681b ldr r3, [r3, #0]
|
|
8001de0: 689b ldr r3, [r3, #8]
|
|
8001de2: 60bb str r3, [r7, #8]
|
|
|
|
/* Reset the MMS Bits */
|
|
tmpcr2 &= ~TIM_CR2_MMS;
|
|
8001de4: 68fb ldr r3, [r7, #12]
|
|
8001de6: f023 0370 bic.w r3, r3, #112 ; 0x70
|
|
8001dea: 60fb str r3, [r7, #12]
|
|
/* Select the TRGO source */
|
|
tmpcr2 |= sMasterConfig->MasterOutputTrigger;
|
|
8001dec: 683b ldr r3, [r7, #0]
|
|
8001dee: 681b ldr r3, [r3, #0]
|
|
8001df0: 68fa ldr r2, [r7, #12]
|
|
8001df2: 4313 orrs r3, r2
|
|
8001df4: 60fb str r3, [r7, #12]
|
|
|
|
/* Update TIMx CR2 */
|
|
htim->Instance->CR2 = tmpcr2;
|
|
8001df6: 687b ldr r3, [r7, #4]
|
|
8001df8: 681b ldr r3, [r3, #0]
|
|
8001dfa: 68fa ldr r2, [r7, #12]
|
|
8001dfc: 605a str r2, [r3, #4]
|
|
|
|
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
|
|
8001dfe: 687b ldr r3, [r7, #4]
|
|
8001e00: 681b ldr r3, [r3, #0]
|
|
8001e02: 4a16 ldr r2, [pc, #88] ; (8001e5c <HAL_TIMEx_MasterConfigSynchronization+0xb0>)
|
|
8001e04: 4293 cmp r3, r2
|
|
8001e06: d00e beq.n 8001e26 <HAL_TIMEx_MasterConfigSynchronization+0x7a>
|
|
8001e08: 687b ldr r3, [r7, #4]
|
|
8001e0a: 681b ldr r3, [r3, #0]
|
|
8001e0c: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
|
|
8001e10: d009 beq.n 8001e26 <HAL_TIMEx_MasterConfigSynchronization+0x7a>
|
|
8001e12: 687b ldr r3, [r7, #4]
|
|
8001e14: 681b ldr r3, [r3, #0]
|
|
8001e16: 4a12 ldr r2, [pc, #72] ; (8001e60 <HAL_TIMEx_MasterConfigSynchronization+0xb4>)
|
|
8001e18: 4293 cmp r3, r2
|
|
8001e1a: d004 beq.n 8001e26 <HAL_TIMEx_MasterConfigSynchronization+0x7a>
|
|
8001e1c: 687b ldr r3, [r7, #4]
|
|
8001e1e: 681b ldr r3, [r3, #0]
|
|
8001e20: 4a10 ldr r2, [pc, #64] ; (8001e64 <HAL_TIMEx_MasterConfigSynchronization+0xb8>)
|
|
8001e22: 4293 cmp r3, r2
|
|
8001e24: d10c bne.n 8001e40 <HAL_TIMEx_MasterConfigSynchronization+0x94>
|
|
{
|
|
/* Reset the MSM Bit */
|
|
tmpsmcr &= ~TIM_SMCR_MSM;
|
|
8001e26: 68bb ldr r3, [r7, #8]
|
|
8001e28: f023 0380 bic.w r3, r3, #128 ; 0x80
|
|
8001e2c: 60bb str r3, [r7, #8]
|
|
/* Set master mode */
|
|
tmpsmcr |= sMasterConfig->MasterSlaveMode;
|
|
8001e2e: 683b ldr r3, [r7, #0]
|
|
8001e30: 685b ldr r3, [r3, #4]
|
|
8001e32: 68ba ldr r2, [r7, #8]
|
|
8001e34: 4313 orrs r3, r2
|
|
8001e36: 60bb str r3, [r7, #8]
|
|
|
|
/* Update TIMx SMCR */
|
|
htim->Instance->SMCR = tmpsmcr;
|
|
8001e38: 687b ldr r3, [r7, #4]
|
|
8001e3a: 681b ldr r3, [r3, #0]
|
|
8001e3c: 68ba ldr r2, [r7, #8]
|
|
8001e3e: 609a str r2, [r3, #8]
|
|
}
|
|
|
|
/* Change the htim state */
|
|
htim->State = HAL_TIM_STATE_READY;
|
|
8001e40: 687b ldr r3, [r7, #4]
|
|
8001e42: 2201 movs r2, #1
|
|
8001e44: f883 203d strb.w r2, [r3, #61] ; 0x3d
|
|
|
|
__HAL_UNLOCK(htim);
|
|
8001e48: 687b ldr r3, [r7, #4]
|
|
8001e4a: 2200 movs r2, #0
|
|
8001e4c: f883 203c strb.w r2, [r3, #60] ; 0x3c
|
|
|
|
return HAL_OK;
|
|
8001e50: 2300 movs r3, #0
|
|
}
|
|
8001e52: 4618 mov r0, r3
|
|
8001e54: 3714 adds r7, #20
|
|
8001e56: 46bd mov sp, r7
|
|
8001e58: bc80 pop {r7}
|
|
8001e5a: 4770 bx lr
|
|
8001e5c: 40012c00 .word 0x40012c00
|
|
8001e60: 40000400 .word 0x40000400
|
|
8001e64: 40000800 .word 0x40000800
|
|
|
|
08001e68 <__libc_init_array>:
|
|
8001e68: b570 push {r4, r5, r6, lr}
|
|
8001e6a: 2600 movs r6, #0
|
|
8001e6c: 4d0c ldr r5, [pc, #48] ; (8001ea0 <__libc_init_array+0x38>)
|
|
8001e6e: 4c0d ldr r4, [pc, #52] ; (8001ea4 <__libc_init_array+0x3c>)
|
|
8001e70: 1b64 subs r4, r4, r5
|
|
8001e72: 10a4 asrs r4, r4, #2
|
|
8001e74: 42a6 cmp r6, r4
|
|
8001e76: d109 bne.n 8001e8c <__libc_init_array+0x24>
|
|
8001e78: f000 f822 bl 8001ec0 <_init>
|
|
8001e7c: 2600 movs r6, #0
|
|
8001e7e: 4d0a ldr r5, [pc, #40] ; (8001ea8 <__libc_init_array+0x40>)
|
|
8001e80: 4c0a ldr r4, [pc, #40] ; (8001eac <__libc_init_array+0x44>)
|
|
8001e82: 1b64 subs r4, r4, r5
|
|
8001e84: 10a4 asrs r4, r4, #2
|
|
8001e86: 42a6 cmp r6, r4
|
|
8001e88: d105 bne.n 8001e96 <__libc_init_array+0x2e>
|
|
8001e8a: bd70 pop {r4, r5, r6, pc}
|
|
8001e8c: f855 3b04 ldr.w r3, [r5], #4
|
|
8001e90: 4798 blx r3
|
|
8001e92: 3601 adds r6, #1
|
|
8001e94: e7ee b.n 8001e74 <__libc_init_array+0xc>
|
|
8001e96: f855 3b04 ldr.w r3, [r5], #4
|
|
8001e9a: 4798 blx r3
|
|
8001e9c: 3601 adds r6, #1
|
|
8001e9e: e7f2 b.n 8001e86 <__libc_init_array+0x1e>
|
|
8001ea0: 08001ef8 .word 0x08001ef8
|
|
8001ea4: 08001ef8 .word 0x08001ef8
|
|
8001ea8: 08001ef8 .word 0x08001ef8
|
|
8001eac: 08001efc .word 0x08001efc
|
|
|
|
08001eb0 <memset>:
|
|
8001eb0: 4603 mov r3, r0
|
|
8001eb2: 4402 add r2, r0
|
|
8001eb4: 4293 cmp r3, r2
|
|
8001eb6: d100 bne.n 8001eba <memset+0xa>
|
|
8001eb8: 4770 bx lr
|
|
8001eba: f803 1b01 strb.w r1, [r3], #1
|
|
8001ebe: e7f9 b.n 8001eb4 <memset+0x4>
|
|
|
|
08001ec0 <_init>:
|
|
8001ec0: b5f8 push {r3, r4, r5, r6, r7, lr}
|
|
8001ec2: bf00 nop
|
|
8001ec4: bcf8 pop {r3, r4, r5, r6, r7}
|
|
8001ec6: bc08 pop {r3}
|
|
8001ec8: 469e mov lr, r3
|
|
8001eca: 4770 bx lr
|
|
|
|
08001ecc <_fini>:
|
|
8001ecc: b5f8 push {r3, r4, r5, r6, r7, lr}
|
|
8001ece: bf00 nop
|
|
8001ed0: bcf8 pop {r3, r4, r5, r6, r7}
|
|
8001ed2: bc08 pop {r3}
|
|
8001ed4: 469e mov lr, r3
|
|
8001ed6: 4770 bx lr
|