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RTC.elf: file format elf32-littlearm
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Sections:
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Idx Name Size VMA LMA File off Algn
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0 .isr_vector 0000010c 08000000 08000000 00010000 2**0
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CONTENTS, ALLOC, LOAD, READONLY, DATA
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1 .text 00002ad0 0800010c 0800010c 0001010c 2**2
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CONTENTS, ALLOC, LOAD, READONLY, CODE
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2 .rodata 00000080 08002bdc 08002bdc 00012bdc 2**2
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CONTENTS, ALLOC, LOAD, READONLY, DATA
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3 .ARM.extab 00000000 08002c5c 08002c5c 00020070 2**0
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CONTENTS
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4 .ARM 00000000 08002c5c 08002c5c 00020070 2**0
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CONTENTS
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5 .preinit_array 00000000 08002c5c 08002c5c 00020070 2**0
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CONTENTS, ALLOC, LOAD, DATA
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6 .init_array 00000004 08002c5c 08002c5c 00012c5c 2**2
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CONTENTS, ALLOC, LOAD, DATA
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7 .fini_array 00000004 08002c60 08002c60 00012c60 2**2
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CONTENTS, ALLOC, LOAD, DATA
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8 .data 00000070 20000000 08002c64 00020000 2**2
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CONTENTS, ALLOC, LOAD, DATA
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9 .bss 0000008c 20000070 08002cd4 00020070 2**2
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ALLOC
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10 ._user_heap_stack 00000604 200000fc 08002cd4 000200fc 2**0
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ALLOC
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11 .ARM.attributes 00000029 00000000 00000000 00020070 2**0
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CONTENTS, READONLY
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12 .debug_info 00006df5 00000000 00000000 00020099 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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13 .debug_abbrev 00001b0d 00000000 00000000 00026e8e 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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14 .debug_aranges 00000838 00000000 00000000 000289a0 2**3
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CONTENTS, READONLY, DEBUGGING, OCTETS
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15 .debug_ranges 00000760 00000000 00000000 000291d8 2**3
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CONTENTS, READONLY, DEBUGGING, OCTETS
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16 .debug_macro 00017adf 00000000 00000000 00029938 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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17 .debug_line 00009edb 00000000 00000000 00041417 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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18 .debug_str 000846d9 00000000 00000000 0004b2f2 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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19 .comment 00000050 00000000 00000000 000cf9cb 2**0
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CONTENTS, READONLY
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20 .debug_frame 000022e8 00000000 00000000 000cfa1c 2**2
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CONTENTS, READONLY, DEBUGGING, OCTETS
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Disassembly of section .text:
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0800010c <__do_global_dtors_aux>:
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800010c: b510 push {r4, lr}
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800010e: 4c05 ldr r4, [pc, #20] ; (8000124 <__do_global_dtors_aux+0x18>)
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8000110: 7823 ldrb r3, [r4, #0]
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8000112: b933 cbnz r3, 8000122 <__do_global_dtors_aux+0x16>
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8000114: 4b04 ldr r3, [pc, #16] ; (8000128 <__do_global_dtors_aux+0x1c>)
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8000116: b113 cbz r3, 800011e <__do_global_dtors_aux+0x12>
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8000118: 4804 ldr r0, [pc, #16] ; (800012c <__do_global_dtors_aux+0x20>)
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800011a: f3af 8000 nop.w
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800011e: 2301 movs r3, #1
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8000120: 7023 strb r3, [r4, #0]
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8000122: bd10 pop {r4, pc}
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8000124: 20000070 .word 0x20000070
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8000128: 00000000 .word 0x00000000
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800012c: 08002bc4 .word 0x08002bc4
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08000130 <frame_dummy>:
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8000130: b508 push {r3, lr}
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8000132: 4b03 ldr r3, [pc, #12] ; (8000140 <frame_dummy+0x10>)
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8000134: b11b cbz r3, 800013e <frame_dummy+0xe>
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8000136: 4903 ldr r1, [pc, #12] ; (8000144 <frame_dummy+0x14>)
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8000138: 4803 ldr r0, [pc, #12] ; (8000148 <frame_dummy+0x18>)
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800013a: f3af 8000 nop.w
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800013e: bd08 pop {r3, pc}
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8000140: 00000000 .word 0x00000000
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8000144: 20000074 .word 0x20000074
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8000148: 08002bc4 .word 0x08002bc4
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0800014c <strlen>:
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800014c: 4603 mov r3, r0
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800014e: f813 2b01 ldrb.w r2, [r3], #1
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8000152: 2a00 cmp r2, #0
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8000154: d1fb bne.n 800014e <strlen+0x2>
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8000156: 1a18 subs r0, r3, r0
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8000158: 3801 subs r0, #1
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800015a: 4770 bx lr
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0800015c <MX_GPIO_Init>:
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* Output
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* EVENT_OUT
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* EXTI
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*/
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void MX_GPIO_Init(void)
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{
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800015c: b480 push {r7}
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800015e: b083 sub sp, #12
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8000160: af00 add r7, sp, #0
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/* GPIO Ports Clock Enable */
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__HAL_RCC_GPIOC_CLK_ENABLE();
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8000162: 4b0e ldr r3, [pc, #56] ; (800019c <MX_GPIO_Init+0x40>)
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8000164: 699b ldr r3, [r3, #24]
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8000166: 4a0d ldr r2, [pc, #52] ; (800019c <MX_GPIO_Init+0x40>)
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8000168: f043 0310 orr.w r3, r3, #16
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800016c: 6193 str r3, [r2, #24]
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800016e: 4b0b ldr r3, [pc, #44] ; (800019c <MX_GPIO_Init+0x40>)
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8000170: 699b ldr r3, [r3, #24]
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8000172: f003 0310 and.w r3, r3, #16
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8000176: 607b str r3, [r7, #4]
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8000178: 687b ldr r3, [r7, #4]
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__HAL_RCC_GPIOA_CLK_ENABLE();
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800017a: 4b08 ldr r3, [pc, #32] ; (800019c <MX_GPIO_Init+0x40>)
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800017c: 699b ldr r3, [r3, #24]
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800017e: 4a07 ldr r2, [pc, #28] ; (800019c <MX_GPIO_Init+0x40>)
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8000180: f043 0304 orr.w r3, r3, #4
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8000184: 6193 str r3, [r2, #24]
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8000186: 4b05 ldr r3, [pc, #20] ; (800019c <MX_GPIO_Init+0x40>)
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8000188: 699b ldr r3, [r3, #24]
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800018a: f003 0304 and.w r3, r3, #4
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800018e: 603b str r3, [r7, #0]
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8000190: 683b ldr r3, [r7, #0]
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}
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8000192: bf00 nop
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8000194: 370c adds r7, #12
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8000196: 46bd mov sp, r7
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8000198: bc80 pop {r7}
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800019a: 4770 bx lr
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800019c: 40021000 .word 0x40021000
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080001a0 <main>:
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/**
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* @brief The application entry point.
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* @retval int
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*/
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int main(void)
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{
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80001a0: b580 push {r7, lr}
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80001a2: b090 sub sp, #64 ; 0x40
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80001a4: af02 add r7, sp, #8
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/* USER CODE END 1 */
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/* MCU Configuration--------------------------------------------------------*/
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/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
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HAL_Init();
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80001a6: f000 fa2d bl 8000604 <HAL_Init>
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/* USER CODE BEGIN Init */
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/* USER CODE END Init */
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/* Configure the system clock */
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SystemClock_Config();
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80001aa: f000 f859 bl 8000260 <SystemClock_Config>
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/* USER CODE BEGIN SysInit */
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/* USER CODE END SysInit */
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/* Initialize all configured peripherals */
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MX_GPIO_Init();
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80001ae: f7ff ffd5 bl 800015c <MX_GPIO_Init>
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MX_RTC_Init();
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80001b2: f000 f8ad bl 8000310 <MX_RTC_Init>
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MX_USART2_UART_Init();
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80001b6: f000 f98b bl 80004d0 <MX_USART2_UART_Init>
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/* USER CODE END 2 */
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/* Infinite loop */
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/* USER CODE BEGIN WHILE */
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uint8_t buf[50] = { 0 };
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80001ba: 2300 movs r3, #0
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80001bc: 607b str r3, [r7, #4]
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80001be: f107 0308 add.w r3, r7, #8
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80001c2: 222e movs r2, #46 ; 0x2e
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80001c4: 2100 movs r1, #0
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80001c6: 4618 mov r0, r3
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80001c8: f002 f87a bl 80022c0 <memset>
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RTC_TimeTypeDef currentTime; //存放获取到的时间
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while (1) {
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HAL_RTC_GetTime(&hrtc, ¤tTime, RTC_FORMAT_BCD); //读取当前时间
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80001cc: 463b mov r3, r7
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80001ce: 2201 movs r2, #1
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80001d0: 4619 mov r1, r3
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80001d2: 4820 ldr r0, [pc, #128] ; (8000254 <main+0xb4>)
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80001d4: f001 fb36 bl 8001844 <HAL_RTC_GetTime>
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//打印时间
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//注意：HAL_RTC_GetTime得到的是BCD码的格式，需<EFBC8C><E99C80>?/16*10+%16转换<E8BDAC><E68DA2>?10进制数字
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sprintf((char*) buf, "%02d:%02d:%02d\r\n",
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currentTime.Hours / 16 * 10 + currentTime.Hours % 16,
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80001d8: 783b ldrb r3, [r7, #0]
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80001da: 091b lsrs r3, r3, #4
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80001dc: b2db uxtb r3, r3
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80001de: 461a mov r2, r3
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80001e0: 4613 mov r3, r2
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80001e2: 009b lsls r3, r3, #2
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80001e4: 4413 add r3, r2
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80001e6: 005b lsls r3, r3, #1
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80001e8: 461a mov r2, r3
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80001ea: 783b ldrb r3, [r7, #0]
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80001ec: f003 030f and.w r3, r3, #15
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sprintf((char*) buf, "%02d:%02d:%02d\r\n",
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80001f0: 441a add r2, r3
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currentTime.Minutes / 16 * 10 + currentTime.Minutes % 16,
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80001f2: 787b ldrb r3, [r7, #1]
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80001f4: 091b lsrs r3, r3, #4
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80001f6: b2db uxtb r3, r3
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80001f8: 4619 mov r1, r3
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80001fa: 460b mov r3, r1
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80001fc: 009b lsls r3, r3, #2
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80001fe: 440b add r3, r1
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8000200: 005b lsls r3, r3, #1
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8000202: 4619 mov r1, r3
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8000204: 787b ldrb r3, [r7, #1]
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8000206: f003 030f and.w r3, r3, #15
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sprintf((char*) buf, "%02d:%02d:%02d\r\n",
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800020a: 4419 add r1, r3
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currentTime.Seconds / 16 * 10 + currentTime.Seconds % 16);
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800020c: 78bb ldrb r3, [r7, #2]
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800020e: 091b lsrs r3, r3, #4
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8000210: b2db uxtb r3, r3
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8000212: 4618 mov r0, r3
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8000214: 4603 mov r3, r0
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8000216: 009b lsls r3, r3, #2
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8000218: 4403 add r3, r0
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800021a: 005b lsls r3, r3, #1
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800021c: 4618 mov r0, r3
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800021e: 78bb ldrb r3, [r7, #2]
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8000220: f003 030f and.w r3, r3, #15
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sprintf((char*) buf, "%02d:%02d:%02d\r\n",
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8000224: 4403 add r3, r0
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8000226: 1d38 adds r0, r7, #4
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8000228: 9300 str r3, [sp, #0]
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800022a: 460b mov r3, r1
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800022c: 490a ldr r1, [pc, #40] ; (8000258 <main+0xb8>)
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800022e: f002 f84f bl 80022d0 <siprintf>
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HAL_UART_Transmit(&huart2, buf, strlen((const char*) buf), 10); //串口输出
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8000232: 1d3b adds r3, r7, #4
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8000234: 4618 mov r0, r3
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8000236: f7ff ff89 bl 800014c <strlen>
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800023a: 4603 mov r3, r0
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800023c: b29a uxth r2, r3
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800023e: 1d39 adds r1, r7, #4
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8000240: 230a movs r3, #10
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8000242: 4806 ldr r0, [pc, #24] ; (800025c <main+0xbc>)
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8000244: f001 fea7 bl 8001f96 <HAL_UART_Transmit>
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HAL_Delay(1000);
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8000248: f44f 707a mov.w r0, #1000 ; 0x3e8
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800024c: f000 fa3c bl 80006c8 <HAL_Delay>
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HAL_RTC_GetTime(&hrtc, ¤tTime, RTC_FORMAT_BCD); //读取当前时间
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8000250: e7bc b.n 80001cc <main+0x2c>
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8000252: bf00 nop
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8000254: 2000008c .word 0x2000008c
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8000258: 08002bdc .word 0x08002bdc
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800025c: 200000a4 .word 0x200000a4
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08000260 <SystemClock_Config>:
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/**
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* @brief System Clock Configuration
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* @retval None
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*/
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void SystemClock_Config(void)
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{
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8000260: b580 push {r7, lr}
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8000262: b094 sub sp, #80 ; 0x50
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8000264: af00 add r7, sp, #0
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RCC_OscInitTypeDef RCC_OscInitStruct = {0};
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8000266: f107 0328 add.w r3, r7, #40 ; 0x28
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800026a: 2228 movs r2, #40 ; 0x28
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800026c: 2100 movs r1, #0
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800026e: 4618 mov r0, r3
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8000270: f002 f826 bl 80022c0 <memset>
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RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
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8000274: f107 0314 add.w r3, r7, #20
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8000278: 2200 movs r2, #0
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800027a: 601a str r2, [r3, #0]
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800027c: 605a str r2, [r3, #4]
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800027e: 609a str r2, [r3, #8]
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8000280: 60da str r2, [r3, #12]
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8000282: 611a str r2, [r3, #16]
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RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
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8000284: 1d3b adds r3, r7, #4
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8000286: 2200 movs r2, #0
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8000288: 601a str r2, [r3, #0]
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800028a: 605a str r2, [r3, #4]
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800028c: 609a str r2, [r3, #8]
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800028e: 60da str r2, [r3, #12]
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/** Initializes the RCC Oscillators according to the specified parameters
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* in the RCC_OscInitTypeDef structure.
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*/
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RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI|RCC_OSCILLATORTYPE_LSE;
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8000290: 2306 movs r3, #6
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8000292: 62bb str r3, [r7, #40] ; 0x28
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RCC_OscInitStruct.LSEState = RCC_LSE_ON;
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8000294: 2301 movs r3, #1
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8000296: 637b str r3, [r7, #52] ; 0x34
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RCC_OscInitStruct.HSIState = RCC_HSI_ON;
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8000298: 2301 movs r3, #1
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800029a: 63bb str r3, [r7, #56] ; 0x38
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RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
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800029c: 2310 movs r3, #16
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800029e: 63fb str r3, [r7, #60] ; 0x3c
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RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
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80002a0: 2300 movs r3, #0
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80002a2: 647b str r3, [r7, #68] ; 0x44
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if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
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80002a4: f107 0328 add.w r3, r7, #40 ; 0x28
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80002a8: 4618 mov r0, r3
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80002aa: f000 fca5 bl 8000bf8 <HAL_RCC_OscConfig>
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80002ae: 4603 mov r3, r0
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80002b0: 2b00 cmp r3, #0
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80002b2: d001 beq.n 80002b8 <SystemClock_Config+0x58>
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{
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Error_Handler();
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80002b4: f000 f827 bl 8000306 <Error_Handler>
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}
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/** Initializes the CPU, AHB and APB buses clocks
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*/
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RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
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80002b8: 230f movs r3, #15
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80002ba: 617b str r3, [r7, #20]
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|
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
|
|
|
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;
|
|
|
80002bc: 2300 movs r3, #0
|
|
|
80002be: 61bb str r3, [r7, #24]
|
|
|
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
|
|
|
80002c0: 2300 movs r3, #0
|
|
|
80002c2: 61fb str r3, [r7, #28]
|
|
|
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
|
|
|
80002c4: 2300 movs r3, #0
|
|
|
80002c6: 623b str r3, [r7, #32]
|
|
|
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
|
|
|
80002c8: 2300 movs r3, #0
|
|
|
80002ca: 627b str r3, [r7, #36] ; 0x24
|
|
|
|
|
|
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK)
|
|
|
80002cc: f107 0314 add.w r3, r7, #20
|
|
|
80002d0: 2100 movs r1, #0
|
|
|
80002d2: 4618 mov r0, r3
|
|
|
80002d4: f000 ff12 bl 80010fc <HAL_RCC_ClockConfig>
|
|
|
80002d8: 4603 mov r3, r0
|
|
|
80002da: 2b00 cmp r3, #0
|
|
|
80002dc: d001 beq.n 80002e2 <SystemClock_Config+0x82>
|
|
|
{
|
|
|
Error_Handler();
|
|
|
80002de: f000 f812 bl 8000306 <Error_Handler>
|
|
|
}
|
|
|
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_RTC;
|
|
|
80002e2: 2301 movs r3, #1
|
|
|
80002e4: 607b str r3, [r7, #4]
|
|
|
PeriphClkInit.RTCClockSelection = RCC_RTCCLKSOURCE_LSE;
|
|
|
80002e6: f44f 7380 mov.w r3, #256 ; 0x100
|
|
|
80002ea: 60bb str r3, [r7, #8]
|
|
|
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
|
|
|
80002ec: 1d3b adds r3, r7, #4
|
|
|
80002ee: 4618 mov r0, r3
|
|
|
80002f0: f001 f89c bl 800142c <HAL_RCCEx_PeriphCLKConfig>
|
|
|
80002f4: 4603 mov r3, r0
|
|
|
80002f6: 2b00 cmp r3, #0
|
|
|
80002f8: d001 beq.n 80002fe <SystemClock_Config+0x9e>
|
|
|
{
|
|
|
Error_Handler();
|
|
|
80002fa: f000 f804 bl 8000306 <Error_Handler>
|
|
|
}
|
|
|
}
|
|
|
80002fe: bf00 nop
|
|
|
8000300: 3750 adds r7, #80 ; 0x50
|
|
|
8000302: 46bd mov sp, r7
|
|
|
8000304: bd80 pop {r7, pc}
|
|
|
|
|
|
08000306 <Error_Handler>:
|
|
|
/**
|
|
|
* @brief This function is executed in case of error occurrence.
|
|
|
* @retval None
|
|
|
*/
|
|
|
void Error_Handler(void)
|
|
|
{
|
|
|
8000306: b480 push {r7}
|
|
|
8000308: af00 add r7, sp, #0
|
|
|
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
|
|
|
Can only be executed in Privileged modes.
|
|
|
*/
|
|
|
__STATIC_FORCEINLINE void __disable_irq(void)
|
|
|
{
|
|
|
__ASM volatile ("cpsid i" : : : "memory");
|
|
|
800030a: b672 cpsid i
|
|
|
}
|
|
|
800030c: bf00 nop
|
|
|
/* USER CODE BEGIN Error_Handler_Debug */
|
|
|
/* User can add his own implementation to report the HAL error return state */
|
|
|
__disable_irq();
|
|
|
while (1) {
|
|
|
800030e: e7fe b.n 800030e <Error_Handler+0x8>
|
|
|
|
|
|
08000310 <MX_RTC_Init>:
|
|
|
/* USER CODE END 0 */
|
|
|
|
|
|
RTC_HandleTypeDef hrtc;
|
|
|
|
|
|
/* RTC init function */
|
|
|
void MX_RTC_Init(void) {
|
|
|
8000310: b580 push {r7, lr}
|
|
|
8000312: b082 sub sp, #8
|
|
|
8000314: af00 add r7, sp, #0
|
|
|
|
|
|
/* USER CODE BEGIN RTC_Init 0 */
|
|
|
|
|
|
/* USER CODE END RTC_Init 0 */
|
|
|
|
|
|
RTC_TimeTypeDef sTime = { 0 };
|
|
|
8000316: 1d3b adds r3, r7, #4
|
|
|
8000318: 2100 movs r1, #0
|
|
|
800031a: 460a mov r2, r1
|
|
|
800031c: 801a strh r2, [r3, #0]
|
|
|
800031e: 460a mov r2, r1
|
|
|
8000320: 709a strb r2, [r3, #2]
|
|
|
RTC_DateTypeDef DateToUpdate = { 0 };
|
|
|
8000322: 2300 movs r3, #0
|
|
|
8000324: 603b str r3, [r7, #0]
|
|
|
|
|
|
/* USER CODE END RTC_Init 1 */
|
|
|
|
|
|
/** Initialize RTC Only
|
|
|
*/
|
|
|
hrtc.Instance = RTC;
|
|
|
8000326: 4b0b ldr r3, [pc, #44] ; (8000354 <MX_RTC_Init+0x44>)
|
|
|
8000328: 4a0b ldr r2, [pc, #44] ; (8000358 <MX_RTC_Init+0x48>)
|
|
|
800032a: 601a str r2, [r3, #0]
|
|
|
hrtc.Init.AsynchPrediv = RTC_AUTO_1_SECOND;
|
|
|
800032c: 4b09 ldr r3, [pc, #36] ; (8000354 <MX_RTC_Init+0x44>)
|
|
|
800032e: f04f 32ff mov.w r2, #4294967295
|
|
|
8000332: 605a str r2, [r3, #4]
|
|
|
hrtc.Init.OutPut = RTC_OUTPUTSOURCE_ALARM;
|
|
|
8000334: 4b07 ldr r3, [pc, #28] ; (8000354 <MX_RTC_Init+0x44>)
|
|
|
8000336: f44f 7280 mov.w r2, #256 ; 0x100
|
|
|
800033a: 609a str r2, [r3, #8]
|
|
|
if (HAL_RTC_Init(&hrtc) != HAL_OK) {
|
|
|
800033c: 4805 ldr r0, [pc, #20] ; (8000354 <MX_RTC_Init+0x44>)
|
|
|
800033e: f001 f9eb bl 8001718 <HAL_RTC_Init>
|
|
|
8000342: 4603 mov r3, r0
|
|
|
8000344: 2b00 cmp r3, #0
|
|
|
8000346: d001 beq.n 800034c <MX_RTC_Init+0x3c>
|
|
|
Error_Handler();
|
|
|
8000348: f7ff ffdd bl 8000306 <Error_Handler>
|
|
|
}
|
|
|
/* USER CODE BEGIN RTC_Init 2 */
|
|
|
|
|
|
/* USER CODE END RTC_Init 2 */
|
|
|
|
|
|
}
|
|
|
800034c: 3708 adds r7, #8
|
|
|
800034e: 46bd mov sp, r7
|
|
|
8000350: bd80 pop {r7, pc}
|
|
|
8000352: bf00 nop
|
|
|
8000354: 2000008c .word 0x2000008c
|
|
|
8000358: 40002800 .word 0x40002800
|
|
|
|
|
|
0800035c <HAL_RTC_MspInit>:
|
|
|
|
|
|
void HAL_RTC_MspInit(RTC_HandleTypeDef *rtcHandle) {
|
|
|
800035c: b580 push {r7, lr}
|
|
|
800035e: b084 sub sp, #16
|
|
|
8000360: af00 add r7, sp, #0
|
|
|
8000362: 6078 str r0, [r7, #4]
|
|
|
|
|
|
if (rtcHandle->Instance == RTC) {
|
|
|
8000364: 687b ldr r3, [r7, #4]
|
|
|
8000366: 681b ldr r3, [r3, #0]
|
|
|
8000368: 4a0b ldr r2, [pc, #44] ; (8000398 <HAL_RTC_MspInit+0x3c>)
|
|
|
800036a: 4293 cmp r3, r2
|
|
|
800036c: d110 bne.n 8000390 <HAL_RTC_MspInit+0x34>
|
|
|
/* USER CODE BEGIN RTC_MspInit 0 */
|
|
|
|
|
|
/* USER CODE END RTC_MspInit 0 */
|
|
|
HAL_PWR_EnableBkUpAccess();
|
|
|
800036e: f000 fc37 bl 8000be0 <HAL_PWR_EnableBkUpAccess>
|
|
|
/* Enable BKP CLK enable for backup registers */
|
|
|
__HAL_RCC_BKP_CLK_ENABLE();
|
|
|
8000372: 4b0a ldr r3, [pc, #40] ; (800039c <HAL_RTC_MspInit+0x40>)
|
|
|
8000374: 69db ldr r3, [r3, #28]
|
|
|
8000376: 4a09 ldr r2, [pc, #36] ; (800039c <HAL_RTC_MspInit+0x40>)
|
|
|
8000378: f043 6300 orr.w r3, r3, #134217728 ; 0x8000000
|
|
|
800037c: 61d3 str r3, [r2, #28]
|
|
|
800037e: 4b07 ldr r3, [pc, #28] ; (800039c <HAL_RTC_MspInit+0x40>)
|
|
|
8000380: 69db ldr r3, [r3, #28]
|
|
|
8000382: f003 6300 and.w r3, r3, #134217728 ; 0x8000000
|
|
|
8000386: 60fb str r3, [r7, #12]
|
|
|
8000388: 68fb ldr r3, [r7, #12]
|
|
|
/* RTC clock enable */
|
|
|
__HAL_RCC_RTC_ENABLE();
|
|
|
800038a: 4b05 ldr r3, [pc, #20] ; (80003a0 <HAL_RTC_MspInit+0x44>)
|
|
|
800038c: 2201 movs r2, #1
|
|
|
800038e: 601a str r2, [r3, #0]
|
|
|
/* USER CODE BEGIN RTC_MspInit 1 */
|
|
|
|
|
|
/* USER CODE END RTC_MspInit 1 */
|
|
|
}
|
|
|
}
|
|
|
8000390: bf00 nop
|
|
|
8000392: 3710 adds r7, #16
|
|
|
8000394: 46bd mov sp, r7
|
|
|
8000396: bd80 pop {r7, pc}
|
|
|
8000398: 40002800 .word 0x40002800
|
|
|
800039c: 40021000 .word 0x40021000
|
|
|
80003a0: 4242043c .word 0x4242043c
|
|
|
|
|
|
080003a4 <HAL_MspInit>:
|
|
|
/* USER CODE END 0 */
|
|
|
/**
|
|
|
* Initializes the Global MSP.
|
|
|
*/
|
|
|
void HAL_MspInit(void)
|
|
|
{
|
|
|
80003a4: b480 push {r7}
|
|
|
80003a6: b085 sub sp, #20
|
|
|
80003a8: af00 add r7, sp, #0
|
|
|
/* USER CODE BEGIN MspInit 0 */
|
|
|
|
|
|
/* USER CODE END MspInit 0 */
|
|
|
|
|
|
__HAL_RCC_AFIO_CLK_ENABLE();
|
|
|
80003aa: 4b15 ldr r3, [pc, #84] ; (8000400 <HAL_MspInit+0x5c>)
|
|
|
80003ac: 699b ldr r3, [r3, #24]
|
|
|
80003ae: 4a14 ldr r2, [pc, #80] ; (8000400 <HAL_MspInit+0x5c>)
|
|
|
80003b0: f043 0301 orr.w r3, r3, #1
|
|
|
80003b4: 6193 str r3, [r2, #24]
|
|
|
80003b6: 4b12 ldr r3, [pc, #72] ; (8000400 <HAL_MspInit+0x5c>)
|
|
|
80003b8: 699b ldr r3, [r3, #24]
|
|
|
80003ba: f003 0301 and.w r3, r3, #1
|
|
|
80003be: 60bb str r3, [r7, #8]
|
|
|
80003c0: 68bb ldr r3, [r7, #8]
|
|
|
__HAL_RCC_PWR_CLK_ENABLE();
|
|
|
80003c2: 4b0f ldr r3, [pc, #60] ; (8000400 <HAL_MspInit+0x5c>)
|
|
|
80003c4: 69db ldr r3, [r3, #28]
|
|
|
80003c6: 4a0e ldr r2, [pc, #56] ; (8000400 <HAL_MspInit+0x5c>)
|
|
|
80003c8: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
|
|
|
80003cc: 61d3 str r3, [r2, #28]
|
|
|
80003ce: 4b0c ldr r3, [pc, #48] ; (8000400 <HAL_MspInit+0x5c>)
|
|
|
80003d0: 69db ldr r3, [r3, #28]
|
|
|
80003d2: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
|
|
|
80003d6: 607b str r3, [r7, #4]
|
|
|
80003d8: 687b ldr r3, [r7, #4]
|
|
|
|
|
|
/* System interrupt init*/
|
|
|
|
|
|
/** NOJTAG: JTAG-DP Disabled and SW-DP Enabled
|
|
|
*/
|
|
|
__HAL_AFIO_REMAP_SWJ_NOJTAG();
|
|
|
80003da: 4b0a ldr r3, [pc, #40] ; (8000404 <HAL_MspInit+0x60>)
|
|
|
80003dc: 685b ldr r3, [r3, #4]
|
|
|
80003de: 60fb str r3, [r7, #12]
|
|
|
80003e0: 68fb ldr r3, [r7, #12]
|
|
|
80003e2: f023 63e0 bic.w r3, r3, #117440512 ; 0x7000000
|
|
|
80003e6: 60fb str r3, [r7, #12]
|
|
|
80003e8: 68fb ldr r3, [r7, #12]
|
|
|
80003ea: f043 7300 orr.w r3, r3, #33554432 ; 0x2000000
|
|
|
80003ee: 60fb str r3, [r7, #12]
|
|
|
80003f0: 4a04 ldr r2, [pc, #16] ; (8000404 <HAL_MspInit+0x60>)
|
|
|
80003f2: 68fb ldr r3, [r7, #12]
|
|
|
80003f4: 6053 str r3, [r2, #4]
|
|
|
|
|
|
/* USER CODE BEGIN MspInit 1 */
|
|
|
|
|
|
/* USER CODE END MspInit 1 */
|
|
|
}
|
|
|
80003f6: bf00 nop
|
|
|
80003f8: 3714 adds r7, #20
|
|
|
80003fa: 46bd mov sp, r7
|
|
|
80003fc: bc80 pop {r7}
|
|
|
80003fe: 4770 bx lr
|
|
|
8000400: 40021000 .word 0x40021000
|
|
|
8000404: 40010000 .word 0x40010000
|
|
|
|
|
|
08000408 <NMI_Handler>:
|
|
|
/******************************************************************************/
|
|
|
/**
|
|
|
* @brief This function handles Non maskable interrupt.
|
|
|
*/
|
|
|
void NMI_Handler(void)
|
|
|
{
|
|
|
8000408: b480 push {r7}
|
|
|
800040a: af00 add r7, sp, #0
|
|
|
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
|
|
|
|
|
|
/* USER CODE END NonMaskableInt_IRQn 0 */
|
|
|
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
|
|
|
while (1)
|
|
|
800040c: e7fe b.n 800040c <NMI_Handler+0x4>
|
|
|
|
|
|
0800040e <HardFault_Handler>:
|
|
|
|
|
|
/**
|
|
|
* @brief This function handles Hard fault interrupt.
|
|
|
*/
|
|
|
void HardFault_Handler(void)
|
|
|
{
|
|
|
800040e: b480 push {r7}
|
|
|
8000410: af00 add r7, sp, #0
|
|
|
/* USER CODE BEGIN HardFault_IRQn 0 */
|
|
|
|
|
|
/* USER CODE END HardFault_IRQn 0 */
|
|
|
while (1)
|
|
|
8000412: e7fe b.n 8000412 <HardFault_Handler+0x4>
|
|
|
|
|
|
08000414 <MemManage_Handler>:
|
|
|
|
|
|
/**
|
|
|
* @brief This function handles Memory management fault.
|
|
|
*/
|
|
|
void MemManage_Handler(void)
|
|
|
{
|
|
|
8000414: b480 push {r7}
|
|
|
8000416: af00 add r7, sp, #0
|
|
|
/* USER CODE BEGIN MemoryManagement_IRQn 0 */
|
|
|
|
|
|
/* USER CODE END MemoryManagement_IRQn 0 */
|
|
|
while (1)
|
|
|
8000418: e7fe b.n 8000418 <MemManage_Handler+0x4>
|
|
|
|
|
|
0800041a <BusFault_Handler>:
|
|
|
|
|
|
/**
|
|
|
* @brief This function handles Prefetch fault, memory access fault.
|
|
|
*/
|
|
|
void BusFault_Handler(void)
|
|
|
{
|
|
|
800041a: b480 push {r7}
|
|
|
800041c: af00 add r7, sp, #0
|
|
|
/* USER CODE BEGIN BusFault_IRQn 0 */
|
|
|
|
|
|
/* USER CODE END BusFault_IRQn 0 */
|
|
|
while (1)
|
|
|
800041e: e7fe b.n 800041e <BusFault_Handler+0x4>
|
|
|
|
|
|
08000420 <UsageFault_Handler>:
|
|
|
|
|
|
/**
|
|
|
* @brief This function handles Undefined instruction or illegal state.
|
|
|
*/
|
|
|
void UsageFault_Handler(void)
|
|
|
{
|
|
|
8000420: b480 push {r7}
|
|
|
8000422: af00 add r7, sp, #0
|
|
|
/* USER CODE BEGIN UsageFault_IRQn 0 */
|
|
|
|
|
|
/* USER CODE END UsageFault_IRQn 0 */
|
|
|
while (1)
|
|
|
8000424: e7fe b.n 8000424 <UsageFault_Handler+0x4>
|
|
|
|
|
|
08000426 <SVC_Handler>:
|
|
|
|
|
|
/**
|
|
|
* @brief This function handles System service call via SWI instruction.
|
|
|
*/
|
|
|
void SVC_Handler(void)
|
|
|
{
|
|
|
8000426: b480 push {r7}
|
|
|
8000428: af00 add r7, sp, #0
|
|
|
|
|
|
/* USER CODE END SVCall_IRQn 0 */
|
|
|
/* USER CODE BEGIN SVCall_IRQn 1 */
|
|
|
|
|
|
/* USER CODE END SVCall_IRQn 1 */
|
|
|
}
|
|
|
800042a: bf00 nop
|
|
|
800042c: 46bd mov sp, r7
|
|
|
800042e: bc80 pop {r7}
|
|
|
8000430: 4770 bx lr
|
|
|
|
|
|
08000432 <DebugMon_Handler>:
|
|
|
|
|
|
/**
|
|
|
* @brief This function handles Debug monitor.
|
|
|
*/
|
|
|
void DebugMon_Handler(void)
|
|
|
{
|
|
|
8000432: b480 push {r7}
|
|
|
8000434: af00 add r7, sp, #0
|
|
|
|
|
|
/* USER CODE END DebugMonitor_IRQn 0 */
|
|
|
/* USER CODE BEGIN DebugMonitor_IRQn 1 */
|
|
|
|
|
|
/* USER CODE END DebugMonitor_IRQn 1 */
|
|
|
}
|
|
|
8000436: bf00 nop
|
|
|
8000438: 46bd mov sp, r7
|
|
|
800043a: bc80 pop {r7}
|
|
|
800043c: 4770 bx lr
|
|
|
|
|
|
0800043e <PendSV_Handler>:
|
|
|
|
|
|
/**
|
|
|
* @brief This function handles Pendable request for system service.
|
|
|
*/
|
|
|
void PendSV_Handler(void)
|
|
|
{
|
|
|
800043e: b480 push {r7}
|
|
|
8000440: af00 add r7, sp, #0
|
|
|
|
|
|
/* USER CODE END PendSV_IRQn 0 */
|
|
|
/* USER CODE BEGIN PendSV_IRQn 1 */
|
|
|
|
|
|
/* USER CODE END PendSV_IRQn 1 */
|
|
|
}
|
|
|
8000442: bf00 nop
|
|
|
8000444: 46bd mov sp, r7
|
|
|
8000446: bc80 pop {r7}
|
|
|
8000448: 4770 bx lr
|
|
|
|
|
|
0800044a <SysTick_Handler>:
|
|
|
|
|
|
/**
|
|
|
* @brief This function handles System tick timer.
|
|
|
*/
|
|
|
void SysTick_Handler(void)
|
|
|
{
|
|
|
800044a: b580 push {r7, lr}
|
|
|
800044c: af00 add r7, sp, #0
|
|
|
/* USER CODE BEGIN SysTick_IRQn 0 */
|
|
|
|
|
|
/* USER CODE END SysTick_IRQn 0 */
|
|
|
HAL_IncTick();
|
|
|
800044e: f000 f91f bl 8000690 <HAL_IncTick>
|
|
|
/* USER CODE BEGIN SysTick_IRQn 1 */
|
|
|
|
|
|
/* USER CODE END SysTick_IRQn 1 */
|
|
|
}
|
|
|
8000452: bf00 nop
|
|
|
8000454: bd80 pop {r7, pc}
|
|
|
...
|
|
|
|
|
|
08000458 <_sbrk>:
|
|
|
*
|
|
|
* @param incr Memory size
|
|
|
* @return Pointer to allocated memory
|
|
|
*/
|
|
|
void *_sbrk(ptrdiff_t incr)
|
|
|
{
|
|
|
8000458: b580 push {r7, lr}
|
|
|
800045a: b086 sub sp, #24
|
|
|
800045c: af00 add r7, sp, #0
|
|
|
800045e: 6078 str r0, [r7, #4]
|
|
|
extern uint8_t _end; /* Symbol defined in the linker script */
|
|
|
extern uint8_t _estack; /* Symbol defined in the linker script */
|
|
|
extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */
|
|
|
const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size;
|
|
|
8000460: 4a14 ldr r2, [pc, #80] ; (80004b4 <_sbrk+0x5c>)
|
|
|
8000462: 4b15 ldr r3, [pc, #84] ; (80004b8 <_sbrk+0x60>)
|
|
|
8000464: 1ad3 subs r3, r2, r3
|
|
|
8000466: 617b str r3, [r7, #20]
|
|
|
const uint8_t *max_heap = (uint8_t *)stack_limit;
|
|
|
8000468: 697b ldr r3, [r7, #20]
|
|
|
800046a: 613b str r3, [r7, #16]
|
|
|
uint8_t *prev_heap_end;
|
|
|
|
|
|
/* Initialize heap end at first call */
|
|
|
if (NULL == __sbrk_heap_end)
|
|
|
800046c: 4b13 ldr r3, [pc, #76] ; (80004bc <_sbrk+0x64>)
|
|
|
800046e: 681b ldr r3, [r3, #0]
|
|
|
8000470: 2b00 cmp r3, #0
|
|
|
8000472: d102 bne.n 800047a <_sbrk+0x22>
|
|
|
{
|
|
|
__sbrk_heap_end = &_end;
|
|
|
8000474: 4b11 ldr r3, [pc, #68] ; (80004bc <_sbrk+0x64>)
|
|
|
8000476: 4a12 ldr r2, [pc, #72] ; (80004c0 <_sbrk+0x68>)
|
|
|
8000478: 601a str r2, [r3, #0]
|
|
|
}
|
|
|
|
|
|
/* Protect heap from growing into the reserved MSP stack */
|
|
|
if (__sbrk_heap_end + incr > max_heap)
|
|
|
800047a: 4b10 ldr r3, [pc, #64] ; (80004bc <_sbrk+0x64>)
|
|
|
800047c: 681a ldr r2, [r3, #0]
|
|
|
800047e: 687b ldr r3, [r7, #4]
|
|
|
8000480: 4413 add r3, r2
|
|
|
8000482: 693a ldr r2, [r7, #16]
|
|
|
8000484: 429a cmp r2, r3
|
|
|
8000486: d207 bcs.n 8000498 <_sbrk+0x40>
|
|
|
{
|
|
|
errno = ENOMEM;
|
|
|
8000488: f001 fef0 bl 800226c <__errno>
|
|
|
800048c: 4603 mov r3, r0
|
|
|
800048e: 220c movs r2, #12
|
|
|
8000490: 601a str r2, [r3, #0]
|
|
|
return (void *)-1;
|
|
|
8000492: f04f 33ff mov.w r3, #4294967295
|
|
|
8000496: e009 b.n 80004ac <_sbrk+0x54>
|
|
|
}
|
|
|
|
|
|
prev_heap_end = __sbrk_heap_end;
|
|
|
8000498: 4b08 ldr r3, [pc, #32] ; (80004bc <_sbrk+0x64>)
|
|
|
800049a: 681b ldr r3, [r3, #0]
|
|
|
800049c: 60fb str r3, [r7, #12]
|
|
|
__sbrk_heap_end += incr;
|
|
|
800049e: 4b07 ldr r3, [pc, #28] ; (80004bc <_sbrk+0x64>)
|
|
|
80004a0: 681a ldr r2, [r3, #0]
|
|
|
80004a2: 687b ldr r3, [r7, #4]
|
|
|
80004a4: 4413 add r3, r2
|
|
|
80004a6: 4a05 ldr r2, [pc, #20] ; (80004bc <_sbrk+0x64>)
|
|
|
80004a8: 6013 str r3, [r2, #0]
|
|
|
|
|
|
return (void *)prev_heap_end;
|
|
|
80004aa: 68fb ldr r3, [r7, #12]
|
|
|
}
|
|
|
80004ac: 4618 mov r0, r3
|
|
|
80004ae: 3718 adds r7, #24
|
|
|
80004b0: 46bd mov sp, r7
|
|
|
80004b2: bd80 pop {r7, pc}
|
|
|
80004b4: 20005000 .word 0x20005000
|
|
|
80004b8: 00000400 .word 0x00000400
|
|
|
80004bc: 200000a0 .word 0x200000a0
|
|
|
80004c0: 20000100 .word 0x20000100
|
|
|
|
|
|
080004c4 <SystemInit>:
|
|
|
* @note This function should be used only after reset.
|
|
|
* @param None
|
|
|
* @retval None
|
|
|
*/
|
|
|
void SystemInit (void)
|
|
|
{
|
|
|
80004c4: b480 push {r7}
|
|
|
80004c6: af00 add r7, sp, #0
|
|
|
|
|
|
/* Configure the Vector Table location -------------------------------------*/
|
|
|
#if defined(USER_VECT_TAB_ADDRESS)
|
|
|
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
|
|
|
#endif /* USER_VECT_TAB_ADDRESS */
|
|
|
}
|
|
|
80004c8: bf00 nop
|
|
|
80004ca: 46bd mov sp, r7
|
|
|
80004cc: bc80 pop {r7}
|
|
|
80004ce: 4770 bx lr
|
|
|
|
|
|
080004d0 <MX_USART2_UART_Init>:
|
|
|
UART_HandleTypeDef huart2;
|
|
|
|
|
|
/* USART2 init function */
|
|
|
|
|
|
void MX_USART2_UART_Init(void)
|
|
|
{
|
|
|
80004d0: b580 push {r7, lr}
|
|
|
80004d2: af00 add r7, sp, #0
|
|
|
/* USER CODE END USART2_Init 0 */
|
|
|
|
|
|
/* USER CODE BEGIN USART2_Init 1 */
|
|
|
|
|
|
/* USER CODE END USART2_Init 1 */
|
|
|
huart2.Instance = USART2;
|
|
|
80004d4: 4b11 ldr r3, [pc, #68] ; (800051c <MX_USART2_UART_Init+0x4c>)
|
|
|
80004d6: 4a12 ldr r2, [pc, #72] ; (8000520 <MX_USART2_UART_Init+0x50>)
|
|
|
80004d8: 601a str r2, [r3, #0]
|
|
|
huart2.Init.BaudRate = 115200;
|
|
|
80004da: 4b10 ldr r3, [pc, #64] ; (800051c <MX_USART2_UART_Init+0x4c>)
|
|
|
80004dc: f44f 32e1 mov.w r2, #115200 ; 0x1c200
|
|
|
80004e0: 605a str r2, [r3, #4]
|
|
|
huart2.Init.WordLength = UART_WORDLENGTH_8B;
|
|
|
80004e2: 4b0e ldr r3, [pc, #56] ; (800051c <MX_USART2_UART_Init+0x4c>)
|
|
|
80004e4: 2200 movs r2, #0
|
|
|
80004e6: 609a str r2, [r3, #8]
|
|
|
huart2.Init.StopBits = UART_STOPBITS_1;
|
|
|
80004e8: 4b0c ldr r3, [pc, #48] ; (800051c <MX_USART2_UART_Init+0x4c>)
|
|
|
80004ea: 2200 movs r2, #0
|
|
|
80004ec: 60da str r2, [r3, #12]
|
|
|
huart2.Init.Parity = UART_PARITY_NONE;
|
|
|
80004ee: 4b0b ldr r3, [pc, #44] ; (800051c <MX_USART2_UART_Init+0x4c>)
|
|
|
80004f0: 2200 movs r2, #0
|
|
|
80004f2: 611a str r2, [r3, #16]
|
|
|
huart2.Init.Mode = UART_MODE_TX_RX;
|
|
|
80004f4: 4b09 ldr r3, [pc, #36] ; (800051c <MX_USART2_UART_Init+0x4c>)
|
|
|
80004f6: 220c movs r2, #12
|
|
|
80004f8: 615a str r2, [r3, #20]
|
|
|
huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE;
|
|
|
80004fa: 4b08 ldr r3, [pc, #32] ; (800051c <MX_USART2_UART_Init+0x4c>)
|
|
|
80004fc: 2200 movs r2, #0
|
|
|
80004fe: 619a str r2, [r3, #24]
|
|
|
huart2.Init.OverSampling = UART_OVERSAMPLING_16;
|
|
|
8000500: 4b06 ldr r3, [pc, #24] ; (800051c <MX_USART2_UART_Init+0x4c>)
|
|
|
8000502: 2200 movs r2, #0
|
|
|
8000504: 61da str r2, [r3, #28]
|
|
|
if (HAL_UART_Init(&huart2) != HAL_OK)
|
|
|
8000506: 4805 ldr r0, [pc, #20] ; (800051c <MX_USART2_UART_Init+0x4c>)
|
|
|
8000508: f001 fcf8 bl 8001efc <HAL_UART_Init>
|
|
|
800050c: 4603 mov r3, r0
|
|
|
800050e: 2b00 cmp r3, #0
|
|
|
8000510: d001 beq.n 8000516 <MX_USART2_UART_Init+0x46>
|
|
|
{
|
|
|
Error_Handler();
|
|
|
8000512: f7ff fef8 bl 8000306 <Error_Handler>
|
|
|
}
|
|
|
/* USER CODE BEGIN USART2_Init 2 */
|
|
|
|
|
|
/* USER CODE END USART2_Init 2 */
|
|
|
|
|
|
}
|
|
|
8000516: bf00 nop
|
|
|
8000518: bd80 pop {r7, pc}
|
|
|
800051a: bf00 nop
|
|
|
800051c: 200000a4 .word 0x200000a4
|
|
|
8000520: 40004400 .word 0x40004400
|
|
|
|
|
|
08000524 <HAL_UART_MspInit>:
|
|
|
|
|
|
void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle)
|
|
|
{
|
|
|
8000524: b580 push {r7, lr}
|
|
|
8000526: b088 sub sp, #32
|
|
|
8000528: af00 add r7, sp, #0
|
|
|
800052a: 6078 str r0, [r7, #4]
|
|
|
|
|
|
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
|
|
800052c: f107 0310 add.w r3, r7, #16
|
|
|
8000530: 2200 movs r2, #0
|
|
|
8000532: 601a str r2, [r3, #0]
|
|
|
8000534: 605a str r2, [r3, #4]
|
|
|
8000536: 609a str r2, [r3, #8]
|
|
|
8000538: 60da str r2, [r3, #12]
|
|
|
if(uartHandle->Instance==USART2)
|
|
|
800053a: 687b ldr r3, [r7, #4]
|
|
|
800053c: 681b ldr r3, [r3, #0]
|
|
|
800053e: 4a1b ldr r2, [pc, #108] ; (80005ac <HAL_UART_MspInit+0x88>)
|
|
|
8000540: 4293 cmp r3, r2
|
|
|
8000542: d12f bne.n 80005a4 <HAL_UART_MspInit+0x80>
|
|
|
{
|
|
|
/* USER CODE BEGIN USART2_MspInit 0 */
|
|
|
|
|
|
/* USER CODE END USART2_MspInit 0 */
|
|
|
/* USART2 clock enable */
|
|
|
__HAL_RCC_USART2_CLK_ENABLE();
|
|
|
8000544: 4b1a ldr r3, [pc, #104] ; (80005b0 <HAL_UART_MspInit+0x8c>)
|
|
|
8000546: 69db ldr r3, [r3, #28]
|
|
|
8000548: 4a19 ldr r2, [pc, #100] ; (80005b0 <HAL_UART_MspInit+0x8c>)
|
|
|
800054a: f443 3300 orr.w r3, r3, #131072 ; 0x20000
|
|
|
800054e: 61d3 str r3, [r2, #28]
|
|
|
8000550: 4b17 ldr r3, [pc, #92] ; (80005b0 <HAL_UART_MspInit+0x8c>)
|
|
|
8000552: 69db ldr r3, [r3, #28]
|
|
|
8000554: f403 3300 and.w r3, r3, #131072 ; 0x20000
|
|
|
8000558: 60fb str r3, [r7, #12]
|
|
|
800055a: 68fb ldr r3, [r7, #12]
|
|
|
|
|
|
__HAL_RCC_GPIOA_CLK_ENABLE();
|
|
|
800055c: 4b14 ldr r3, [pc, #80] ; (80005b0 <HAL_UART_MspInit+0x8c>)
|
|
|
800055e: 699b ldr r3, [r3, #24]
|
|
|
8000560: 4a13 ldr r2, [pc, #76] ; (80005b0 <HAL_UART_MspInit+0x8c>)
|
|
|
8000562: f043 0304 orr.w r3, r3, #4
|
|
|
8000566: 6193 str r3, [r2, #24]
|
|
|
8000568: 4b11 ldr r3, [pc, #68] ; (80005b0 <HAL_UART_MspInit+0x8c>)
|
|
|
800056a: 699b ldr r3, [r3, #24]
|
|
|
800056c: f003 0304 and.w r3, r3, #4
|
|
|
8000570: 60bb str r3, [r7, #8]
|
|
|
8000572: 68bb ldr r3, [r7, #8]
|
|
|
/**USART2 GPIO Configuration
|
|
|
PA2 ------> USART2_TX
|
|
|
PA3 ------> USART2_RX
|
|
|
*/
|
|
|
GPIO_InitStruct.Pin = GPIO_PIN_2;
|
|
|
8000574: 2304 movs r3, #4
|
|
|
8000576: 613b str r3, [r7, #16]
|
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
|
8000578: 2302 movs r3, #2
|
|
|
800057a: 617b str r3, [r7, #20]
|
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
|
|
|
800057c: 2303 movs r3, #3
|
|
|
800057e: 61fb str r3, [r7, #28]
|
|
|
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
|
|
8000580: f107 0310 add.w r3, r7, #16
|
|
|
8000584: 4619 mov r1, r3
|
|
|
8000586: 480b ldr r0, [pc, #44] ; (80005b4 <HAL_UART_MspInit+0x90>)
|
|
|
8000588: f000 f9a6 bl 80008d8 <HAL_GPIO_Init>
|
|
|
|
|
|
GPIO_InitStruct.Pin = GPIO_PIN_3;
|
|
|
800058c: 2308 movs r3, #8
|
|
|
800058e: 613b str r3, [r7, #16]
|
|
|
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
|
|
|
8000590: 2300 movs r3, #0
|
|
|
8000592: 617b str r3, [r7, #20]
|
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
|
8000594: 2300 movs r3, #0
|
|
|
8000596: 61bb str r3, [r7, #24]
|
|
|
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
|
|
8000598: f107 0310 add.w r3, r7, #16
|
|
|
800059c: 4619 mov r1, r3
|
|
|
800059e: 4805 ldr r0, [pc, #20] ; (80005b4 <HAL_UART_MspInit+0x90>)
|
|
|
80005a0: f000 f99a bl 80008d8 <HAL_GPIO_Init>
|
|
|
|
|
|
/* USER CODE BEGIN USART2_MspInit 1 */
|
|
|
|
|
|
/* USER CODE END USART2_MspInit 1 */
|
|
|
}
|
|
|
}
|
|
|
80005a4: bf00 nop
|
|
|
80005a6: 3720 adds r7, #32
|
|
|
80005a8: 46bd mov sp, r7
|
|
|
80005aa: bd80 pop {r7, pc}
|
|
|
80005ac: 40004400 .word 0x40004400
|
|
|
80005b0: 40021000 .word 0x40021000
|
|
|
80005b4: 40010800 .word 0x40010800
|
|
|
|
|
|
080005b8 <Reset_Handler>:
|
|
|
.weak Reset_Handler
|
|
|
.type Reset_Handler, %function
|
|
|
Reset_Handler:
|
|
|
|
|
|
/* Copy the data segment initializers from flash to SRAM */
|
|
|
ldr r0, =_sdata
|
|
|
80005b8: 480c ldr r0, [pc, #48] ; (80005ec <LoopFillZerobss+0x12>)
|
|
|
ldr r1, =_edata
|
|
|
80005ba: 490d ldr r1, [pc, #52] ; (80005f0 <LoopFillZerobss+0x16>)
|
|
|
ldr r2, =_sidata
|
|
|
80005bc: 4a0d ldr r2, [pc, #52] ; (80005f4 <LoopFillZerobss+0x1a>)
|
|
|
movs r3, #0
|
|
|
80005be: 2300 movs r3, #0
|
|
|
b LoopCopyDataInit
|
|
|
80005c0: e002 b.n 80005c8 <LoopCopyDataInit>
|
|
|
|
|
|
080005c2 <CopyDataInit>:
|
|
|
|
|
|
CopyDataInit:
|
|
|
ldr r4, [r2, r3]
|
|
|
80005c2: 58d4 ldr r4, [r2, r3]
|
|
|
str r4, [r0, r3]
|
|
|
80005c4: 50c4 str r4, [r0, r3]
|
|
|
adds r3, r3, #4
|
|
|
80005c6: 3304 adds r3, #4
|
|
|
|
|
|
080005c8 <LoopCopyDataInit>:
|
|
|
|
|
|
LoopCopyDataInit:
|
|
|
adds r4, r0, r3
|
|
|
80005c8: 18c4 adds r4, r0, r3
|
|
|
cmp r4, r1
|
|
|
80005ca: 428c cmp r4, r1
|
|
|
bcc CopyDataInit
|
|
|
80005cc: d3f9 bcc.n 80005c2 <CopyDataInit>
|
|
|
|
|
|
/* Zero fill the bss segment. */
|
|
|
ldr r2, =_sbss
|
|
|
80005ce: 4a0a ldr r2, [pc, #40] ; (80005f8 <LoopFillZerobss+0x1e>)
|
|
|
ldr r4, =_ebss
|
|
|
80005d0: 4c0a ldr r4, [pc, #40] ; (80005fc <LoopFillZerobss+0x22>)
|
|
|
movs r3, #0
|
|
|
80005d2: 2300 movs r3, #0
|
|
|
b LoopFillZerobss
|
|
|
80005d4: e001 b.n 80005da <LoopFillZerobss>
|
|
|
|
|
|
080005d6 <FillZerobss>:
|
|
|
|
|
|
FillZerobss:
|
|
|
str r3, [r2]
|
|
|
80005d6: 6013 str r3, [r2, #0]
|
|
|
adds r2, r2, #4
|
|
|
80005d8: 3204 adds r2, #4
|
|
|
|
|
|
080005da <LoopFillZerobss>:
|
|
|
|
|
|
LoopFillZerobss:
|
|
|
cmp r2, r4
|
|
|
80005da: 42a2 cmp r2, r4
|
|
|
bcc FillZerobss
|
|
|
80005dc: d3fb bcc.n 80005d6 <FillZerobss>
|
|
|
|
|
|
/* Call the clock system intitialization function.*/
|
|
|
bl SystemInit
|
|
|
80005de: f7ff ff71 bl 80004c4 <SystemInit>
|
|
|
/* Call static constructors */
|
|
|
bl __libc_init_array
|
|
|
80005e2: f001 fe49 bl 8002278 <__libc_init_array>
|
|
|
/* Call the application's entry point.*/
|
|
|
bl main
|
|
|
80005e6: f7ff fddb bl 80001a0 <main>
|
|
|
bx lr
|
|
|
80005ea: 4770 bx lr
|
|
|
ldr r0, =_sdata
|
|
|
80005ec: 20000000 .word 0x20000000
|
|
|
ldr r1, =_edata
|
|
|
80005f0: 20000070 .word 0x20000070
|
|
|
ldr r2, =_sidata
|
|
|
80005f4: 08002c64 .word 0x08002c64
|
|
|
ldr r2, =_sbss
|
|
|
80005f8: 20000070 .word 0x20000070
|
|
|
ldr r4, =_ebss
|
|
|
80005fc: 200000fc .word 0x200000fc
|
|
|
|
|
|
08000600 <ADC1_2_IRQHandler>:
|
|
|
* @retval : None
|
|
|
*/
|
|
|
.section .text.Default_Handler,"ax",%progbits
|
|
|
Default_Handler:
|
|
|
Infinite_Loop:
|
|
|
b Infinite_Loop
|
|
|
8000600: e7fe b.n 8000600 <ADC1_2_IRQHandler>
|
|
|
...
|
|
|
|
|
|
08000604 <HAL_Init>:
|
|
|
* need to ensure that the SysTick time base is always set to 1 millisecond
|
|
|
* to have correct HAL operation.
|
|
|
* @retval HAL status
|
|
|
*/
|
|
|
HAL_StatusTypeDef HAL_Init(void)
|
|
|
{
|
|
|
8000604: b580 push {r7, lr}
|
|
|
8000606: af00 add r7, sp, #0
|
|
|
defined(STM32F102x6) || defined(STM32F102xB) || \
|
|
|
defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || \
|
|
|
defined(STM32F105xC) || defined(STM32F107xC)
|
|
|
|
|
|
/* Prefetch buffer is not available on value line devices */
|
|
|
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
|
|
|
8000608: 4b08 ldr r3, [pc, #32] ; (800062c <HAL_Init+0x28>)
|
|
|
800060a: 681b ldr r3, [r3, #0]
|
|
|
800060c: 4a07 ldr r2, [pc, #28] ; (800062c <HAL_Init+0x28>)
|
|
|
800060e: f043 0310 orr.w r3, r3, #16
|
|
|
8000612: 6013 str r3, [r2, #0]
|
|
|
#endif
|
|
|
#endif /* PREFETCH_ENABLE */
|
|
|
|
|
|
/* Set Interrupt Group Priority */
|
|
|
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
|
|
|
8000614: 2003 movs r0, #3
|
|
|
8000616: f000 f92b bl 8000870 <HAL_NVIC_SetPriorityGrouping>
|
|
|
|
|
|
/* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
|
|
|
HAL_InitTick(TICK_INT_PRIORITY);
|
|
|
800061a: 200f movs r0, #15
|
|
|
800061c: f000 f808 bl 8000630 <HAL_InitTick>
|
|
|
|
|
|
/* Init the low level hardware */
|
|
|
HAL_MspInit();
|
|
|
8000620: f7ff fec0 bl 80003a4 <HAL_MspInit>
|
|
|
|
|
|
/* Return function status */
|
|
|
return HAL_OK;
|
|
|
8000624: 2300 movs r3, #0
|
|
|
}
|
|
|
8000626: 4618 mov r0, r3
|
|
|
8000628: bd80 pop {r7, pc}
|
|
|
800062a: bf00 nop
|
|
|
800062c: 40022000 .word 0x40022000
|
|
|
|
|
|
08000630 <HAL_InitTick>:
|
|
|
* implementation in user file.
|
|
|
* @param TickPriority Tick interrupt priority.
|
|
|
* @retval HAL status
|
|
|
*/
|
|
|
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
|
|
|
{
|
|
|
8000630: b580 push {r7, lr}
|
|
|
8000632: b082 sub sp, #8
|
|
|
8000634: af00 add r7, sp, #0
|
|
|
8000636: 6078 str r0, [r7, #4]
|
|
|
/* Configure the SysTick to have interrupt in 1ms time basis*/
|
|
|
if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U)
|
|
|
8000638: 4b12 ldr r3, [pc, #72] ; (8000684 <HAL_InitTick+0x54>)
|
|
|
800063a: 681a ldr r2, [r3, #0]
|
|
|
800063c: 4b12 ldr r3, [pc, #72] ; (8000688 <HAL_InitTick+0x58>)
|
|
|
800063e: 781b ldrb r3, [r3, #0]
|
|
|
8000640: 4619 mov r1, r3
|
|
|
8000642: f44f 737a mov.w r3, #1000 ; 0x3e8
|
|
|
8000646: fbb3 f3f1 udiv r3, r3, r1
|
|
|
800064a: fbb2 f3f3 udiv r3, r2, r3
|
|
|
800064e: 4618 mov r0, r3
|
|
|
8000650: f000 f935 bl 80008be <HAL_SYSTICK_Config>
|
|
|
8000654: 4603 mov r3, r0
|
|
|
8000656: 2b00 cmp r3, #0
|
|
|
8000658: d001 beq.n 800065e <HAL_InitTick+0x2e>
|
|
|
{
|
|
|
return HAL_ERROR;
|
|
|
800065a: 2301 movs r3, #1
|
|
|
800065c: e00e b.n 800067c <HAL_InitTick+0x4c>
|
|
|
}
|
|
|
|
|
|
/* Configure the SysTick IRQ priority */
|
|
|
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
|
|
|
800065e: 687b ldr r3, [r7, #4]
|
|
|
8000660: 2b0f cmp r3, #15
|
|
|
8000662: d80a bhi.n 800067a <HAL_InitTick+0x4a>
|
|
|
{
|
|
|
HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
|
|
|
8000664: 2200 movs r2, #0
|
|
|
8000666: 6879 ldr r1, [r7, #4]
|
|
|
8000668: f04f 30ff mov.w r0, #4294967295
|
|
|
800066c: f000 f90b bl 8000886 <HAL_NVIC_SetPriority>
|
|
|
uwTickPrio = TickPriority;
|
|
|
8000670: 4a06 ldr r2, [pc, #24] ; (800068c <HAL_InitTick+0x5c>)
|
|
|
8000672: 687b ldr r3, [r7, #4]
|
|
|
8000674: 6013 str r3, [r2, #0]
|
|
|
{
|
|
|
return HAL_ERROR;
|
|
|
}
|
|
|
|
|
|
/* Return function status */
|
|
|
return HAL_OK;
|
|
|
8000676: 2300 movs r3, #0
|
|
|
8000678: e000 b.n 800067c <HAL_InitTick+0x4c>
|
|
|
return HAL_ERROR;
|
|
|
800067a: 2301 movs r3, #1
|
|
|
}
|
|
|
800067c: 4618 mov r0, r3
|
|
|
800067e: 3708 adds r7, #8
|
|
|
8000680: 46bd mov sp, r7
|
|
|
8000682: bd80 pop {r7, pc}
|
|
|
8000684: 20000000 .word 0x20000000
|
|
|
8000688: 20000008 .word 0x20000008
|
|
|
800068c: 20000004 .word 0x20000004
|
|
|
|
|
|
08000690 <HAL_IncTick>:
|
|
|
* @note This function is declared as __weak to be overwritten in case of other
|
|
|
* implementations in user file.
|
|
|
* @retval None
|
|
|
*/
|
|
|
__weak void HAL_IncTick(void)
|
|
|
{
|
|
|
8000690: b480 push {r7}
|
|
|
8000692: af00 add r7, sp, #0
|
|
|
uwTick += uwTickFreq;
|
|
|
8000694: 4b05 ldr r3, [pc, #20] ; (80006ac <HAL_IncTick+0x1c>)
|
|
|
8000696: 781b ldrb r3, [r3, #0]
|
|
|
8000698: 461a mov r2, r3
|
|
|
800069a: 4b05 ldr r3, [pc, #20] ; (80006b0 <HAL_IncTick+0x20>)
|
|
|
800069c: 681b ldr r3, [r3, #0]
|
|
|
800069e: 4413 add r3, r2
|
|
|
80006a0: 4a03 ldr r2, [pc, #12] ; (80006b0 <HAL_IncTick+0x20>)
|
|
|
80006a2: 6013 str r3, [r2, #0]
|
|
|
}
|
|
|
80006a4: bf00 nop
|
|
|
80006a6: 46bd mov sp, r7
|
|
|
80006a8: bc80 pop {r7}
|
|
|
80006aa: 4770 bx lr
|
|
|
80006ac: 20000008 .word 0x20000008
|
|
|
80006b0: 200000e8 .word 0x200000e8
|
|
|
|
|
|
080006b4 <HAL_GetTick>:
|
|
|
* @note This function is declared as __weak to be overwritten in case of other
|
|
|
* implementations in user file.
|
|
|
* @retval tick value
|
|
|
*/
|
|
|
__weak uint32_t HAL_GetTick(void)
|
|
|
{
|
|
|
80006b4: b480 push {r7}
|
|
|
80006b6: af00 add r7, sp, #0
|
|
|
return uwTick;
|
|
|
80006b8: 4b02 ldr r3, [pc, #8] ; (80006c4 <HAL_GetTick+0x10>)
|
|
|
80006ba: 681b ldr r3, [r3, #0]
|
|
|
}
|
|
|
80006bc: 4618 mov r0, r3
|
|
|
80006be: 46bd mov sp, r7
|
|
|
80006c0: bc80 pop {r7}
|
|
|
80006c2: 4770 bx lr
|
|
|
80006c4: 200000e8 .word 0x200000e8
|
|
|
|
|
|
080006c8 <HAL_Delay>:
|
|
|
* implementations in user file.
|
|
|
* @param Delay specifies the delay time length, in milliseconds.
|
|
|
* @retval None
|
|
|
*/
|
|
|
__weak void HAL_Delay(uint32_t Delay)
|
|
|
{
|
|
|
80006c8: b580 push {r7, lr}
|
|
|
80006ca: b084 sub sp, #16
|
|
|
80006cc: af00 add r7, sp, #0
|
|
|
80006ce: 6078 str r0, [r7, #4]
|
|
|
uint32_t tickstart = HAL_GetTick();
|
|
|
80006d0: f7ff fff0 bl 80006b4 <HAL_GetTick>
|
|
|
80006d4: 60b8 str r0, [r7, #8]
|
|
|
uint32_t wait = Delay;
|
|
|
80006d6: 687b ldr r3, [r7, #4]
|
|
|
80006d8: 60fb str r3, [r7, #12]
|
|
|
|
|
|
/* Add a freq to guarantee minimum wait */
|
|
|
if (wait < HAL_MAX_DELAY)
|
|
|
80006da: 68fb ldr r3, [r7, #12]
|
|
|
80006dc: f1b3 3fff cmp.w r3, #4294967295
|
|
|
80006e0: d005 beq.n 80006ee <HAL_Delay+0x26>
|
|
|
{
|
|
|
wait += (uint32_t)(uwTickFreq);
|
|
|
80006e2: 4b0a ldr r3, [pc, #40] ; (800070c <HAL_Delay+0x44>)
|
|
|
80006e4: 781b ldrb r3, [r3, #0]
|
|
|
80006e6: 461a mov r2, r3
|
|
|
80006e8: 68fb ldr r3, [r7, #12]
|
|
|
80006ea: 4413 add r3, r2
|
|
|
80006ec: 60fb str r3, [r7, #12]
|
|
|
}
|
|
|
|
|
|
while ((HAL_GetTick() - tickstart) < wait)
|
|
|
80006ee: bf00 nop
|
|
|
80006f0: f7ff ffe0 bl 80006b4 <HAL_GetTick>
|
|
|
80006f4: 4602 mov r2, r0
|
|
|
80006f6: 68bb ldr r3, [r7, #8]
|
|
|
80006f8: 1ad3 subs r3, r2, r3
|
|
|
80006fa: 68fa ldr r2, [r7, #12]
|
|
|
80006fc: 429a cmp r2, r3
|
|
|
80006fe: d8f7 bhi.n 80006f0 <HAL_Delay+0x28>
|
|
|
{
|
|
|
}
|
|
|
}
|
|
|
8000700: bf00 nop
|
|
|
8000702: bf00 nop
|
|
|
8000704: 3710 adds r7, #16
|
|
|
8000706: 46bd mov sp, r7
|
|
|
8000708: bd80 pop {r7, pc}
|
|
|
800070a: bf00 nop
|
|
|
800070c: 20000008 .word 0x20000008
|
|
|
|
|
|
08000710 <__NVIC_SetPriorityGrouping>:
|
|
|
In case of a conflict between priority grouping and available
|
|
|
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
|
|
|
\param [in] PriorityGroup Priority grouping field.
|
|
|
*/
|
|
|
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
|
|
|
{
|
|
|
8000710: b480 push {r7}
|
|
|
8000712: b085 sub sp, #20
|
|
|
8000714: af00 add r7, sp, #0
|
|
|
8000716: 6078 str r0, [r7, #4]
|
|
|
uint32_t reg_value;
|
|
|
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
|
|
|
8000718: 687b ldr r3, [r7, #4]
|
|
|
800071a: f003 0307 and.w r3, r3, #7
|
|
|
800071e: 60fb str r3, [r7, #12]
|
|
|
|
|
|
reg_value = SCB->AIRCR; /* read old register configuration */
|
|
|
8000720: 4b0c ldr r3, [pc, #48] ; (8000754 <__NVIC_SetPriorityGrouping+0x44>)
|
|
|
8000722: 68db ldr r3, [r3, #12]
|
|
|
8000724: 60bb str r3, [r7, #8]
|
|
|
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
|
|
|
8000726: 68ba ldr r2, [r7, #8]
|
|
|
8000728: f64f 03ff movw r3, #63743 ; 0xf8ff
|
|
|
800072c: 4013 ands r3, r2
|
|
|
800072e: 60bb str r3, [r7, #8]
|
|
|
reg_value = (reg_value |
|
|
|
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
|
|
|
(PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
|
|
|
8000730: 68fb ldr r3, [r7, #12]
|
|
|
8000732: 021a lsls r2, r3, #8
|
|
|
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
|
|
|
8000734: 68bb ldr r3, [r7, #8]
|
|
|
8000736: 4313 orrs r3, r2
|
|
|
reg_value = (reg_value |
|
|
|
8000738: f043 63bf orr.w r3, r3, #100139008 ; 0x5f80000
|
|
|
800073c: f443 3300 orr.w r3, r3, #131072 ; 0x20000
|
|
|
8000740: 60bb str r3, [r7, #8]
|
|
|
SCB->AIRCR = reg_value;
|
|
|
8000742: 4a04 ldr r2, [pc, #16] ; (8000754 <__NVIC_SetPriorityGrouping+0x44>)
|
|
|
8000744: 68bb ldr r3, [r7, #8]
|
|
|
8000746: 60d3 str r3, [r2, #12]
|
|
|
}
|
|
|
8000748: bf00 nop
|
|
|
800074a: 3714 adds r7, #20
|
|
|
800074c: 46bd mov sp, r7
|
|
|
800074e: bc80 pop {r7}
|
|
|
8000750: 4770 bx lr
|
|
|
8000752: bf00 nop
|
|
|
8000754: e000ed00 .word 0xe000ed00
|
|
|
|
|
|
08000758 <__NVIC_GetPriorityGrouping>:
|
|
|
\brief Get Priority Grouping
|
|
|
\details Reads the priority grouping field from the NVIC Interrupt Controller.
|
|
|
\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
|
|
|
*/
|
|
|
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
|
|
|
{
|
|
|
8000758: b480 push {r7}
|
|
|
800075a: af00 add r7, sp, #0
|
|
|
return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
|
|
|
800075c: 4b04 ldr r3, [pc, #16] ; (8000770 <__NVIC_GetPriorityGrouping+0x18>)
|
|
|
800075e: 68db ldr r3, [r3, #12]
|
|
|
8000760: 0a1b lsrs r3, r3, #8
|
|
|
8000762: f003 0307 and.w r3, r3, #7
|
|
|
}
|
|
|
8000766: 4618 mov r0, r3
|
|
|
8000768: 46bd mov sp, r7
|
|
|
800076a: bc80 pop {r7}
|
|
|
800076c: 4770 bx lr
|
|
|
800076e: bf00 nop
|
|
|
8000770: e000ed00 .word 0xe000ed00
|
|
|
|
|
|
08000774 <__NVIC_SetPriority>:
|
|
|
\param [in] IRQn Interrupt number.
|
|
|
\param [in] priority Priority to set.
|
|
|
\note The priority cannot be set for every processor exception.
|
|
|
*/
|
|
|
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
|
|
|
{
|
|
|
8000774: b480 push {r7}
|
|
|
8000776: b083 sub sp, #12
|
|
|
8000778: af00 add r7, sp, #0
|
|
|
800077a: 4603 mov r3, r0
|
|
|
800077c: 6039 str r1, [r7, #0]
|
|
|
800077e: 71fb strb r3, [r7, #7]
|
|
|
if ((int32_t)(IRQn) >= 0)
|
|
|
8000780: f997 3007 ldrsb.w r3, [r7, #7]
|
|
|
8000784: 2b00 cmp r3, #0
|
|
|
8000786: db0a blt.n 800079e <__NVIC_SetPriority+0x2a>
|
|
|
{
|
|
|
NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
|
|
|
8000788: 683b ldr r3, [r7, #0]
|
|
|
800078a: b2da uxtb r2, r3
|
|
|
800078c: 490c ldr r1, [pc, #48] ; (80007c0 <__NVIC_SetPriority+0x4c>)
|
|
|
800078e: f997 3007 ldrsb.w r3, [r7, #7]
|
|
|
8000792: 0112 lsls r2, r2, #4
|
|
|
8000794: b2d2 uxtb r2, r2
|
|
|
8000796: 440b add r3, r1
|
|
|
8000798: f883 2300 strb.w r2, [r3, #768] ; 0x300
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
|
|
|
}
|
|
|
}
|
|
|
800079c: e00a b.n 80007b4 <__NVIC_SetPriority+0x40>
|
|
|
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
|
|
|
800079e: 683b ldr r3, [r7, #0]
|
|
|
80007a0: b2da uxtb r2, r3
|
|
|
80007a2: 4908 ldr r1, [pc, #32] ; (80007c4 <__NVIC_SetPriority+0x50>)
|
|
|
80007a4: 79fb ldrb r3, [r7, #7]
|
|
|
80007a6: f003 030f and.w r3, r3, #15
|
|
|
80007aa: 3b04 subs r3, #4
|
|
|
80007ac: 0112 lsls r2, r2, #4
|
|
|
80007ae: b2d2 uxtb r2, r2
|
|
|
80007b0: 440b add r3, r1
|
|
|
80007b2: 761a strb r2, [r3, #24]
|
|
|
}
|
|
|
80007b4: bf00 nop
|
|
|
80007b6: 370c adds r7, #12
|
|
|
80007b8: 46bd mov sp, r7
|
|
|
80007ba: bc80 pop {r7}
|
|
|
80007bc: 4770 bx lr
|
|
|
80007be: bf00 nop
|
|
|
80007c0: e000e100 .word 0xe000e100
|
|
|
80007c4: e000ed00 .word 0xe000ed00
|
|
|
|
|
|
080007c8 <NVIC_EncodePriority>:
|
|
|
\param [in] PreemptPriority Preemptive priority value (starting from 0).
|
|
|
\param [in] SubPriority Subpriority value (starting from 0).
|
|
|
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
|
|
|
*/
|
|
|
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
|
|
|
{
|
|
|
80007c8: b480 push {r7}
|
|
|
80007ca: b089 sub sp, #36 ; 0x24
|
|
|
80007cc: af00 add r7, sp, #0
|
|
|
80007ce: 60f8 str r0, [r7, #12]
|
|
|
80007d0: 60b9 str r1, [r7, #8]
|
|
|
80007d2: 607a str r2, [r7, #4]
|
|
|
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
|
|
|
80007d4: 68fb ldr r3, [r7, #12]
|
|
|
80007d6: f003 0307 and.w r3, r3, #7
|
|
|
80007da: 61fb str r3, [r7, #28]
|
|
|
uint32_t PreemptPriorityBits;
|
|
|
uint32_t SubPriorityBits;
|
|
|
|
|
|
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
|
|
|
80007dc: 69fb ldr r3, [r7, #28]
|
|
|
80007de: f1c3 0307 rsb r3, r3, #7
|
|
|
80007e2: 2b04 cmp r3, #4
|
|
|
80007e4: bf28 it cs
|
|
|
80007e6: 2304 movcs r3, #4
|
|
|
80007e8: 61bb str r3, [r7, #24]
|
|
|
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
|
|
|
80007ea: 69fb ldr r3, [r7, #28]
|
|
|
80007ec: 3304 adds r3, #4
|
|
|
80007ee: 2b06 cmp r3, #6
|
|
|
80007f0: d902 bls.n 80007f8 <NVIC_EncodePriority+0x30>
|
|
|
80007f2: 69fb ldr r3, [r7, #28]
|
|
|
80007f4: 3b03 subs r3, #3
|
|
|
80007f6: e000 b.n 80007fa <NVIC_EncodePriority+0x32>
|
|
|
80007f8: 2300 movs r3, #0
|
|
|
80007fa: 617b str r3, [r7, #20]
|
|
|
|
|
|
return (
|
|
|
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
|
|
|
80007fc: f04f 32ff mov.w r2, #4294967295
|
|
|
8000800: 69bb ldr r3, [r7, #24]
|
|
|
8000802: fa02 f303 lsl.w r3, r2, r3
|
|
|
8000806: 43da mvns r2, r3
|
|
|
8000808: 68bb ldr r3, [r7, #8]
|
|
|
800080a: 401a ands r2, r3
|
|
|
800080c: 697b ldr r3, [r7, #20]
|
|
|
800080e: 409a lsls r2, r3
|
|
|
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
|
|
|
8000810: f04f 31ff mov.w r1, #4294967295
|
|
|
8000814: 697b ldr r3, [r7, #20]
|
|
|
8000816: fa01 f303 lsl.w r3, r1, r3
|
|
|
800081a: 43d9 mvns r1, r3
|
|
|
800081c: 687b ldr r3, [r7, #4]
|
|
|
800081e: 400b ands r3, r1
|
|
|
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
|
|
|
8000820: 4313 orrs r3, r2
|
|
|
);
|
|
|
}
|
|
|
8000822: 4618 mov r0, r3
|
|
|
8000824: 3724 adds r7, #36 ; 0x24
|
|
|
8000826: 46bd mov sp, r7
|
|
|
8000828: bc80 pop {r7}
|
|
|
800082a: 4770 bx lr
|
|
|
|
|
|
0800082c <SysTick_Config>:
|
|
|
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
|
|
|
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
|
|
|
must contain a vendor-specific implementation of this function.
|
|
|
*/
|
|
|
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
|
|
|
{
|
|
|
800082c: b580 push {r7, lr}
|
|
|
800082e: b082 sub sp, #8
|
|
|
8000830: af00 add r7, sp, #0
|
|
|
8000832: 6078 str r0, [r7, #4]
|
|
|
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
|
|
|
8000834: 687b ldr r3, [r7, #4]
|
|
|
8000836: 3b01 subs r3, #1
|
|
|
8000838: f1b3 7f80 cmp.w r3, #16777216 ; 0x1000000
|
|
|
800083c: d301 bcc.n 8000842 <SysTick_Config+0x16>
|
|
|
{
|
|
|
return (1UL); /* Reload value impossible */
|
|
|
800083e: 2301 movs r3, #1
|
|
|
8000840: e00f b.n 8000862 <SysTick_Config+0x36>
|
|
|
}
|
|
|
|
|
|
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
|
|
|
8000842: 4a0a ldr r2, [pc, #40] ; (800086c <SysTick_Config+0x40>)
|
|
|
8000844: 687b ldr r3, [r7, #4]
|
|
|
8000846: 3b01 subs r3, #1
|
|
|
8000848: 6053 str r3, [r2, #4]
|
|
|
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
|
|
|
800084a: 210f movs r1, #15
|
|
|
800084c: f04f 30ff mov.w r0, #4294967295
|
|
|
8000850: f7ff ff90 bl 8000774 <__NVIC_SetPriority>
|
|
|
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
|
|
|
8000854: 4b05 ldr r3, [pc, #20] ; (800086c <SysTick_Config+0x40>)
|
|
|
8000856: 2200 movs r2, #0
|
|
|
8000858: 609a str r2, [r3, #8]
|
|
|
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
|
|
|
800085a: 4b04 ldr r3, [pc, #16] ; (800086c <SysTick_Config+0x40>)
|
|
|
800085c: 2207 movs r2, #7
|
|
|
800085e: 601a str r2, [r3, #0]
|
|
|
SysTick_CTRL_TICKINT_Msk |
|
|
|
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
|
|
|
return (0UL); /* Function successful */
|
|
|
8000860: 2300 movs r3, #0
|
|
|
}
|
|
|
8000862: 4618 mov r0, r3
|
|
|
8000864: 3708 adds r7, #8
|
|
|
8000866: 46bd mov sp, r7
|
|
|
8000868: bd80 pop {r7, pc}
|
|
|
800086a: bf00 nop
|
|
|
800086c: e000e010 .word 0xe000e010
|
|
|
|
|
|
08000870 <HAL_NVIC_SetPriorityGrouping>:
|
|
|
* @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible.
|
|
|
* The pending IRQ priority will be managed only by the subpriority.
|
|
|
* @retval None
|
|
|
*/
|
|
|
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
|
|
|
{
|
|
|
8000870: b580 push {r7, lr}
|
|
|
8000872: b082 sub sp, #8
|
|
|
8000874: af00 add r7, sp, #0
|
|
|
8000876: 6078 str r0, [r7, #4]
|
|
|
/* Check the parameters */
|
|
|
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
|
|
|
|
|
|
/* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
|
|
|
NVIC_SetPriorityGrouping(PriorityGroup);
|
|
|
8000878: 6878 ldr r0, [r7, #4]
|
|
|
800087a: f7ff ff49 bl 8000710 <__NVIC_SetPriorityGrouping>
|
|
|
}
|
|
|
800087e: bf00 nop
|
|
|
8000880: 3708 adds r7, #8
|
|
|
8000882: 46bd mov sp, r7
|
|
|
8000884: bd80 pop {r7, pc}
|
|
|
|
|
|
08000886 <HAL_NVIC_SetPriority>:
|
|
|
* This parameter can be a value between 0 and 15
|
|
|
* A lower priority value indicates a higher priority.
|
|
|
* @retval None
|
|
|
*/
|
|
|
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
|
|
|
{
|
|
|
8000886: b580 push {r7, lr}
|
|
|
8000888: b086 sub sp, #24
|
|
|
800088a: af00 add r7, sp, #0
|
|
|
800088c: 4603 mov r3, r0
|
|
|
800088e: 60b9 str r1, [r7, #8]
|
|
|
8000890: 607a str r2, [r7, #4]
|
|
|
8000892: 73fb strb r3, [r7, #15]
|
|
|
uint32_t prioritygroup = 0x00U;
|
|
|
8000894: 2300 movs r3, #0
|
|
|
8000896: 617b str r3, [r7, #20]
|
|
|
|
|
|
/* Check the parameters */
|
|
|
assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
|
|
|
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
|
|
|
|
|
|
prioritygroup = NVIC_GetPriorityGrouping();
|
|
|
8000898: f7ff ff5e bl 8000758 <__NVIC_GetPriorityGrouping>
|
|
|
800089c: 6178 str r0, [r7, #20]
|
|
|
|
|
|
NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
|
|
|
800089e: 687a ldr r2, [r7, #4]
|
|
|
80008a0: 68b9 ldr r1, [r7, #8]
|
|
|
80008a2: 6978 ldr r0, [r7, #20]
|
|
|
80008a4: f7ff ff90 bl 80007c8 <NVIC_EncodePriority>
|
|
|
80008a8: 4602 mov r2, r0
|
|
|
80008aa: f997 300f ldrsb.w r3, [r7, #15]
|
|
|
80008ae: 4611 mov r1, r2
|
|
|
80008b0: 4618 mov r0, r3
|
|
|
80008b2: f7ff ff5f bl 8000774 <__NVIC_SetPriority>
|
|
|
}
|
|
|
80008b6: bf00 nop
|
|
|
80008b8: 3718 adds r7, #24
|
|
|
80008ba: 46bd mov sp, r7
|
|
|
80008bc: bd80 pop {r7, pc}
|
|
|
|
|
|
080008be <HAL_SYSTICK_Config>:
|
|
|
* @param TicksNumb: Specifies the ticks Number of ticks between two interrupts.
|
|
|
* @retval status: - 0 Function succeeded.
|
|
|
* - 1 Function failed.
|
|
|
*/
|
|
|
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
|
|
|
{
|
|
|
80008be: b580 push {r7, lr}
|
|
|
80008c0: b082 sub sp, #8
|
|
|
80008c2: af00 add r7, sp, #0
|
|
|
80008c4: 6078 str r0, [r7, #4]
|
|
|
return SysTick_Config(TicksNumb);
|
|
|
80008c6: 6878 ldr r0, [r7, #4]
|
|
|
80008c8: f7ff ffb0 bl 800082c <SysTick_Config>
|
|
|
80008cc: 4603 mov r3, r0
|
|
|
}
|
|
|
80008ce: 4618 mov r0, r3
|
|
|
80008d0: 3708 adds r7, #8
|
|
|
80008d2: 46bd mov sp, r7
|
|
|
80008d4: bd80 pop {r7, pc}
|
|
|
...
|
|
|
|
|
|
080008d8 <HAL_GPIO_Init>:
|
|
|
* @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains
|
|
|
* the configuration information for the specified GPIO peripheral.
|
|
|
* @retval None
|
|
|
*/
|
|
|
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
|
|
|
{
|
|
|
80008d8: b480 push {r7}
|
|
|
80008da: b08b sub sp, #44 ; 0x2c
|
|
|
80008dc: af00 add r7, sp, #0
|
|
|
80008de: 6078 str r0, [r7, #4]
|
|
|
80008e0: 6039 str r1, [r7, #0]
|
|
|
uint32_t position = 0x00u;
|
|
|
80008e2: 2300 movs r3, #0
|
|
|
80008e4: 627b str r3, [r7, #36] ; 0x24
|
|
|
uint32_t ioposition;
|
|
|
uint32_t iocurrent;
|
|
|
uint32_t temp;
|
|
|
uint32_t config = 0x00u;
|
|
|
80008e6: 2300 movs r3, #0
|
|
|
80008e8: 623b str r3, [r7, #32]
|
|
|
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
|
|
|
assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
|
|
|
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
|
|
|
|
|
|
/* Configure the port pins */
|
|
|
while (((GPIO_Init->Pin) >> position) != 0x00u)
|
|
|
80008ea: e169 b.n 8000bc0 <HAL_GPIO_Init+0x2e8>
|
|
|
{
|
|
|
/* Get the IO position */
|
|
|
ioposition = (0x01uL << position);
|
|
|
80008ec: 2201 movs r2, #1
|
|
|
80008ee: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
|
80008f0: fa02 f303 lsl.w r3, r2, r3
|
|
|
80008f4: 61fb str r3, [r7, #28]
|
|
|
|
|
|
/* Get the current IO position */
|
|
|
iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition;
|
|
|
80008f6: 683b ldr r3, [r7, #0]
|
|
|
80008f8: 681b ldr r3, [r3, #0]
|
|
|
80008fa: 69fa ldr r2, [r7, #28]
|
|
|
80008fc: 4013 ands r3, r2
|
|
|
80008fe: 61bb str r3, [r7, #24]
|
|
|
|
|
|
if (iocurrent == ioposition)
|
|
|
8000900: 69ba ldr r2, [r7, #24]
|
|
|
8000902: 69fb ldr r3, [r7, #28]
|
|
|
8000904: 429a cmp r2, r3
|
|
|
8000906: f040 8158 bne.w 8000bba <HAL_GPIO_Init+0x2e2>
|
|
|
{
|
|
|
/* Check the Alternate function parameters */
|
|
|
assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
|
|
|
|
|
|
/* Based on the required mode, filling config variable with MODEy[1:0] and CNFy[3:2] corresponding bits */
|
|
|
switch (GPIO_Init->Mode)
|
|
|
800090a: 683b ldr r3, [r7, #0]
|
|
|
800090c: 685b ldr r3, [r3, #4]
|
|
|
800090e: 4a9a ldr r2, [pc, #616] ; (8000b78 <HAL_GPIO_Init+0x2a0>)
|
|
|
8000910: 4293 cmp r3, r2
|
|
|
8000912: d05e beq.n 80009d2 <HAL_GPIO_Init+0xfa>
|
|
|
8000914: 4a98 ldr r2, [pc, #608] ; (8000b78 <HAL_GPIO_Init+0x2a0>)
|
|
|
8000916: 4293 cmp r3, r2
|
|
|
8000918: d875 bhi.n 8000a06 <HAL_GPIO_Init+0x12e>
|
|
|
800091a: 4a98 ldr r2, [pc, #608] ; (8000b7c <HAL_GPIO_Init+0x2a4>)
|
|
|
800091c: 4293 cmp r3, r2
|
|
|
800091e: d058 beq.n 80009d2 <HAL_GPIO_Init+0xfa>
|
|
|
8000920: 4a96 ldr r2, [pc, #600] ; (8000b7c <HAL_GPIO_Init+0x2a4>)
|
|
|
8000922: 4293 cmp r3, r2
|
|
|
8000924: d86f bhi.n 8000a06 <HAL_GPIO_Init+0x12e>
|
|
|
8000926: 4a96 ldr r2, [pc, #600] ; (8000b80 <HAL_GPIO_Init+0x2a8>)
|
|
|
8000928: 4293 cmp r3, r2
|
|
|
800092a: d052 beq.n 80009d2 <HAL_GPIO_Init+0xfa>
|
|
|
800092c: 4a94 ldr r2, [pc, #592] ; (8000b80 <HAL_GPIO_Init+0x2a8>)
|
|
|
800092e: 4293 cmp r3, r2
|
|
|
8000930: d869 bhi.n 8000a06 <HAL_GPIO_Init+0x12e>
|
|
|
8000932: 4a94 ldr r2, [pc, #592] ; (8000b84 <HAL_GPIO_Init+0x2ac>)
|
|
|
8000934: 4293 cmp r3, r2
|
|
|
8000936: d04c beq.n 80009d2 <HAL_GPIO_Init+0xfa>
|
|
|
8000938: 4a92 ldr r2, [pc, #584] ; (8000b84 <HAL_GPIO_Init+0x2ac>)
|
|
|
800093a: 4293 cmp r3, r2
|
|
|
800093c: d863 bhi.n 8000a06 <HAL_GPIO_Init+0x12e>
|
|
|
800093e: 4a92 ldr r2, [pc, #584] ; (8000b88 <HAL_GPIO_Init+0x2b0>)
|
|
|
8000940: 4293 cmp r3, r2
|
|
|
8000942: d046 beq.n 80009d2 <HAL_GPIO_Init+0xfa>
|
|
|
8000944: 4a90 ldr r2, [pc, #576] ; (8000b88 <HAL_GPIO_Init+0x2b0>)
|
|
|
8000946: 4293 cmp r3, r2
|
|
|
8000948: d85d bhi.n 8000a06 <HAL_GPIO_Init+0x12e>
|
|
|
800094a: 2b12 cmp r3, #18
|
|
|
800094c: d82a bhi.n 80009a4 <HAL_GPIO_Init+0xcc>
|
|
|
800094e: 2b12 cmp r3, #18
|
|
|
8000950: d859 bhi.n 8000a06 <HAL_GPIO_Init+0x12e>
|
|
|
8000952: a201 add r2, pc, #4 ; (adr r2, 8000958 <HAL_GPIO_Init+0x80>)
|
|
|
8000954: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
|
8000958: 080009d3 .word 0x080009d3
|
|
|
800095c: 080009ad .word 0x080009ad
|
|
|
8000960: 080009bf .word 0x080009bf
|
|
|
8000964: 08000a01 .word 0x08000a01
|
|
|
8000968: 08000a07 .word 0x08000a07
|
|
|
800096c: 08000a07 .word 0x08000a07
|
|
|
8000970: 08000a07 .word 0x08000a07
|
|
|
8000974: 08000a07 .word 0x08000a07
|
|
|
8000978: 08000a07 .word 0x08000a07
|
|
|
800097c: 08000a07 .word 0x08000a07
|
|
|
8000980: 08000a07 .word 0x08000a07
|
|
|
8000984: 08000a07 .word 0x08000a07
|
|
|
8000988: 08000a07 .word 0x08000a07
|
|
|
800098c: 08000a07 .word 0x08000a07
|
|
|
8000990: 08000a07 .word 0x08000a07
|
|
|
8000994: 08000a07 .word 0x08000a07
|
|
|
8000998: 08000a07 .word 0x08000a07
|
|
|
800099c: 080009b5 .word 0x080009b5
|
|
|
80009a0: 080009c9 .word 0x080009c9
|
|
|
80009a4: 4a79 ldr r2, [pc, #484] ; (8000b8c <HAL_GPIO_Init+0x2b4>)
|
|
|
80009a6: 4293 cmp r3, r2
|
|
|
80009a8: d013 beq.n 80009d2 <HAL_GPIO_Init+0xfa>
|
|
|
config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG;
|
|
|
break;
|
|
|
|
|
|
/* Parameters are checked with assert_param */
|
|
|
default:
|
|
|
break;
|
|
|
80009aa: e02c b.n 8000a06 <HAL_GPIO_Init+0x12e>
|
|
|
config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_PP;
|
|
|
80009ac: 683b ldr r3, [r7, #0]
|
|
|
80009ae: 68db ldr r3, [r3, #12]
|
|
|
80009b0: 623b str r3, [r7, #32]
|
|
|
break;
|
|
|
80009b2: e029 b.n 8000a08 <HAL_GPIO_Init+0x130>
|
|
|
config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_OD;
|
|
|
80009b4: 683b ldr r3, [r7, #0]
|
|
|
80009b6: 68db ldr r3, [r3, #12]
|
|
|
80009b8: 3304 adds r3, #4
|
|
|
80009ba: 623b str r3, [r7, #32]
|
|
|
break;
|
|
|
80009bc: e024 b.n 8000a08 <HAL_GPIO_Init+0x130>
|
|
|
config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_PP;
|
|
|
80009be: 683b ldr r3, [r7, #0]
|
|
|
80009c0: 68db ldr r3, [r3, #12]
|
|
|
80009c2: 3308 adds r3, #8
|
|
|
80009c4: 623b str r3, [r7, #32]
|
|
|
break;
|
|
|
80009c6: e01f b.n 8000a08 <HAL_GPIO_Init+0x130>
|
|
|
config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_OD;
|
|
|
80009c8: 683b ldr r3, [r7, #0]
|
|
|
80009ca: 68db ldr r3, [r3, #12]
|
|
|
80009cc: 330c adds r3, #12
|
|
|
80009ce: 623b str r3, [r7, #32]
|
|
|
break;
|
|
|
80009d0: e01a b.n 8000a08 <HAL_GPIO_Init+0x130>
|
|
|
if (GPIO_Init->Pull == GPIO_NOPULL)
|
|
|
80009d2: 683b ldr r3, [r7, #0]
|
|
|
80009d4: 689b ldr r3, [r3, #8]
|
|
|
80009d6: 2b00 cmp r3, #0
|
|
|
80009d8: d102 bne.n 80009e0 <HAL_GPIO_Init+0x108>
|
|
|
config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_FLOATING;
|
|
|
80009da: 2304 movs r3, #4
|
|
|
80009dc: 623b str r3, [r7, #32]
|
|
|
break;
|
|
|
80009de: e013 b.n 8000a08 <HAL_GPIO_Init+0x130>
|
|
|
else if (GPIO_Init->Pull == GPIO_PULLUP)
|
|
|
80009e0: 683b ldr r3, [r7, #0]
|
|
|
80009e2: 689b ldr r3, [r3, #8]
|
|
|
80009e4: 2b01 cmp r3, #1
|
|
|
80009e6: d105 bne.n 80009f4 <HAL_GPIO_Init+0x11c>
|
|
|
config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD;
|
|
|
80009e8: 2308 movs r3, #8
|
|
|
80009ea: 623b str r3, [r7, #32]
|
|
|
GPIOx->BSRR = ioposition;
|
|
|
80009ec: 687b ldr r3, [r7, #4]
|
|
|
80009ee: 69fa ldr r2, [r7, #28]
|
|
|
80009f0: 611a str r2, [r3, #16]
|
|
|
break;
|
|
|
80009f2: e009 b.n 8000a08 <HAL_GPIO_Init+0x130>
|
|
|
config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD;
|
|
|
80009f4: 2308 movs r3, #8
|
|
|
80009f6: 623b str r3, [r7, #32]
|
|
|
GPIOx->BRR = ioposition;
|
|
|
80009f8: 687b ldr r3, [r7, #4]
|
|
|
80009fa: 69fa ldr r2, [r7, #28]
|
|
|
80009fc: 615a str r2, [r3, #20]
|
|
|
break;
|
|
|
80009fe: e003 b.n 8000a08 <HAL_GPIO_Init+0x130>
|
|
|
config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG;
|
|
|
8000a00: 2300 movs r3, #0
|
|
|
8000a02: 623b str r3, [r7, #32]
|
|
|
break;
|
|
|
8000a04: e000 b.n 8000a08 <HAL_GPIO_Init+0x130>
|
|
|
break;
|
|
|
8000a06: bf00 nop
|
|
|
}
|
|
|
|
|
|
/* Check if the current bit belongs to first half or last half of the pin count number
|
|
|
in order to address CRH or CRL register*/
|
|
|
configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL : &GPIOx->CRH;
|
|
|
8000a08: 69bb ldr r3, [r7, #24]
|
|
|
8000a0a: 2bff cmp r3, #255 ; 0xff
|
|
|
8000a0c: d801 bhi.n 8000a12 <HAL_GPIO_Init+0x13a>
|
|
|
8000a0e: 687b ldr r3, [r7, #4]
|
|
|
8000a10: e001 b.n 8000a16 <HAL_GPIO_Init+0x13e>
|
|
|
8000a12: 687b ldr r3, [r7, #4]
|
|
|
8000a14: 3304 adds r3, #4
|
|
|
8000a16: 617b str r3, [r7, #20]
|
|
|
registeroffset = (iocurrent < GPIO_PIN_8) ? (position << 2u) : ((position - 8u) << 2u);
|
|
|
8000a18: 69bb ldr r3, [r7, #24]
|
|
|
8000a1a: 2bff cmp r3, #255 ; 0xff
|
|
|
8000a1c: d802 bhi.n 8000a24 <HAL_GPIO_Init+0x14c>
|
|
|
8000a1e: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
|
8000a20: 009b lsls r3, r3, #2
|
|
|
8000a22: e002 b.n 8000a2a <HAL_GPIO_Init+0x152>
|
|
|
8000a24: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
|
8000a26: 3b08 subs r3, #8
|
|
|
8000a28: 009b lsls r3, r3, #2
|
|
|
8000a2a: 613b str r3, [r7, #16]
|
|
|
|
|
|
/* Apply the new configuration of the pin to the register */
|
|
|
MODIFY_REG((*configregister), ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset), (config << registeroffset));
|
|
|
8000a2c: 697b ldr r3, [r7, #20]
|
|
|
8000a2e: 681a ldr r2, [r3, #0]
|
|
|
8000a30: 210f movs r1, #15
|
|
|
8000a32: 693b ldr r3, [r7, #16]
|
|
|
8000a34: fa01 f303 lsl.w r3, r1, r3
|
|
|
8000a38: 43db mvns r3, r3
|
|
|
8000a3a: 401a ands r2, r3
|
|
|
8000a3c: 6a39 ldr r1, [r7, #32]
|
|
|
8000a3e: 693b ldr r3, [r7, #16]
|
|
|
8000a40: fa01 f303 lsl.w r3, r1, r3
|
|
|
8000a44: 431a orrs r2, r3
|
|
|
8000a46: 697b ldr r3, [r7, #20]
|
|
|
8000a48: 601a str r2, [r3, #0]
|
|
|
|
|
|
/*--------------------- EXTI Mode Configuration ------------------------*/
|
|
|
/* Configure the External Interrupt or event for the current IO */
|
|
|
if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
|
|
|
8000a4a: 683b ldr r3, [r7, #0]
|
|
|
8000a4c: 685b ldr r3, [r3, #4]
|
|
|
8000a4e: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
|
|
|
8000a52: 2b00 cmp r3, #0
|
|
|
8000a54: f000 80b1 beq.w 8000bba <HAL_GPIO_Init+0x2e2>
|
|
|
{
|
|
|
/* Enable AFIO Clock */
|
|
|
__HAL_RCC_AFIO_CLK_ENABLE();
|
|
|
8000a58: 4b4d ldr r3, [pc, #308] ; (8000b90 <HAL_GPIO_Init+0x2b8>)
|
|
|
8000a5a: 699b ldr r3, [r3, #24]
|
|
|
8000a5c: 4a4c ldr r2, [pc, #304] ; (8000b90 <HAL_GPIO_Init+0x2b8>)
|
|
|
8000a5e: f043 0301 orr.w r3, r3, #1
|
|
|
8000a62: 6193 str r3, [r2, #24]
|
|
|
8000a64: 4b4a ldr r3, [pc, #296] ; (8000b90 <HAL_GPIO_Init+0x2b8>)
|
|
|
8000a66: 699b ldr r3, [r3, #24]
|
|
|
8000a68: f003 0301 and.w r3, r3, #1
|
|
|
8000a6c: 60bb str r3, [r7, #8]
|
|
|
8000a6e: 68bb ldr r3, [r7, #8]
|
|
|
temp = AFIO->EXTICR[position >> 2u];
|
|
|
8000a70: 4a48 ldr r2, [pc, #288] ; (8000b94 <HAL_GPIO_Init+0x2bc>)
|
|
|
8000a72: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
|
8000a74: 089b lsrs r3, r3, #2
|
|
|
8000a76: 3302 adds r3, #2
|
|
|
8000a78: f852 3023 ldr.w r3, [r2, r3, lsl #2]
|
|
|
8000a7c: 60fb str r3, [r7, #12]
|
|
|
CLEAR_BIT(temp, (0x0Fu) << (4u * (position & 0x03u)));
|
|
|
8000a7e: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
|
8000a80: f003 0303 and.w r3, r3, #3
|
|
|
8000a84: 009b lsls r3, r3, #2
|
|
|
8000a86: 220f movs r2, #15
|
|
|
8000a88: fa02 f303 lsl.w r3, r2, r3
|
|
|
8000a8c: 43db mvns r3, r3
|
|
|
8000a8e: 68fa ldr r2, [r7, #12]
|
|
|
8000a90: 4013 ands r3, r2
|
|
|
8000a92: 60fb str r3, [r7, #12]
|
|
|
SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4u * (position & 0x03u)));
|
|
|
8000a94: 687b ldr r3, [r7, #4]
|
|
|
8000a96: 4a40 ldr r2, [pc, #256] ; (8000b98 <HAL_GPIO_Init+0x2c0>)
|
|
|
8000a98: 4293 cmp r3, r2
|
|
|
8000a9a: d013 beq.n 8000ac4 <HAL_GPIO_Init+0x1ec>
|
|
|
8000a9c: 687b ldr r3, [r7, #4]
|
|
|
8000a9e: 4a3f ldr r2, [pc, #252] ; (8000b9c <HAL_GPIO_Init+0x2c4>)
|
|
|
8000aa0: 4293 cmp r3, r2
|
|
|
8000aa2: d00d beq.n 8000ac0 <HAL_GPIO_Init+0x1e8>
|
|
|
8000aa4: 687b ldr r3, [r7, #4]
|
|
|
8000aa6: 4a3e ldr r2, [pc, #248] ; (8000ba0 <HAL_GPIO_Init+0x2c8>)
|
|
|
8000aa8: 4293 cmp r3, r2
|
|
|
8000aaa: d007 beq.n 8000abc <HAL_GPIO_Init+0x1e4>
|
|
|
8000aac: 687b ldr r3, [r7, #4]
|
|
|
8000aae: 4a3d ldr r2, [pc, #244] ; (8000ba4 <HAL_GPIO_Init+0x2cc>)
|
|
|
8000ab0: 4293 cmp r3, r2
|
|
|
8000ab2: d101 bne.n 8000ab8 <HAL_GPIO_Init+0x1e0>
|
|
|
8000ab4: 2303 movs r3, #3
|
|
|
8000ab6: e006 b.n 8000ac6 <HAL_GPIO_Init+0x1ee>
|
|
|
8000ab8: 2304 movs r3, #4
|
|
|
8000aba: e004 b.n 8000ac6 <HAL_GPIO_Init+0x1ee>
|
|
|
8000abc: 2302 movs r3, #2
|
|
|
8000abe: e002 b.n 8000ac6 <HAL_GPIO_Init+0x1ee>
|
|
|
8000ac0: 2301 movs r3, #1
|
|
|
8000ac2: e000 b.n 8000ac6 <HAL_GPIO_Init+0x1ee>
|
|
|
8000ac4: 2300 movs r3, #0
|
|
|
8000ac6: 6a7a ldr r2, [r7, #36] ; 0x24
|
|
|
8000ac8: f002 0203 and.w r2, r2, #3
|
|
|
8000acc: 0092 lsls r2, r2, #2
|
|
|
8000ace: 4093 lsls r3, r2
|
|
|
8000ad0: 68fa ldr r2, [r7, #12]
|
|
|
8000ad2: 4313 orrs r3, r2
|
|
|
8000ad4: 60fb str r3, [r7, #12]
|
|
|
AFIO->EXTICR[position >> 2u] = temp;
|
|
|
8000ad6: 492f ldr r1, [pc, #188] ; (8000b94 <HAL_GPIO_Init+0x2bc>)
|
|
|
8000ad8: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
|
8000ada: 089b lsrs r3, r3, #2
|
|
|
8000adc: 3302 adds r3, #2
|
|
|
8000ade: 68fa ldr r2, [r7, #12]
|
|
|
8000ae0: f841 2023 str.w r2, [r1, r3, lsl #2]
|
|
|
|
|
|
|
|
|
/* Configure the interrupt mask */
|
|
|
if ((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
|
|
|
8000ae4: 683b ldr r3, [r7, #0]
|
|
|
8000ae6: 685b ldr r3, [r3, #4]
|
|
|
8000ae8: f403 3380 and.w r3, r3, #65536 ; 0x10000
|
|
|
8000aec: 2b00 cmp r3, #0
|
|
|
8000aee: d006 beq.n 8000afe <HAL_GPIO_Init+0x226>
|
|
|
{
|
|
|
SET_BIT(EXTI->IMR, iocurrent);
|
|
|
8000af0: 4b2d ldr r3, [pc, #180] ; (8000ba8 <HAL_GPIO_Init+0x2d0>)
|
|
|
8000af2: 681a ldr r2, [r3, #0]
|
|
|
8000af4: 492c ldr r1, [pc, #176] ; (8000ba8 <HAL_GPIO_Init+0x2d0>)
|
|
|
8000af6: 69bb ldr r3, [r7, #24]
|
|
|
8000af8: 4313 orrs r3, r2
|
|
|
8000afa: 600b str r3, [r1, #0]
|
|
|
8000afc: e006 b.n 8000b0c <HAL_GPIO_Init+0x234>
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
CLEAR_BIT(EXTI->IMR, iocurrent);
|
|
|
8000afe: 4b2a ldr r3, [pc, #168] ; (8000ba8 <HAL_GPIO_Init+0x2d0>)
|
|
|
8000b00: 681a ldr r2, [r3, #0]
|
|
|
8000b02: 69bb ldr r3, [r7, #24]
|
|
|
8000b04: 43db mvns r3, r3
|
|
|
8000b06: 4928 ldr r1, [pc, #160] ; (8000ba8 <HAL_GPIO_Init+0x2d0>)
|
|
|
8000b08: 4013 ands r3, r2
|
|
|
8000b0a: 600b str r3, [r1, #0]
|
|
|
}
|
|
|
|
|
|
/* Configure the event mask */
|
|
|
if ((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
|
|
|
8000b0c: 683b ldr r3, [r7, #0]
|
|
|
8000b0e: 685b ldr r3, [r3, #4]
|
|
|
8000b10: f403 3300 and.w r3, r3, #131072 ; 0x20000
|
|
|
8000b14: 2b00 cmp r3, #0
|
|
|
8000b16: d006 beq.n 8000b26 <HAL_GPIO_Init+0x24e>
|
|
|
{
|
|
|
SET_BIT(EXTI->EMR, iocurrent);
|
|
|
8000b18: 4b23 ldr r3, [pc, #140] ; (8000ba8 <HAL_GPIO_Init+0x2d0>)
|
|
|
8000b1a: 685a ldr r2, [r3, #4]
|
|
|
8000b1c: 4922 ldr r1, [pc, #136] ; (8000ba8 <HAL_GPIO_Init+0x2d0>)
|
|
|
8000b1e: 69bb ldr r3, [r7, #24]
|
|
|
8000b20: 4313 orrs r3, r2
|
|
|
8000b22: 604b str r3, [r1, #4]
|
|
|
8000b24: e006 b.n 8000b34 <HAL_GPIO_Init+0x25c>
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
CLEAR_BIT(EXTI->EMR, iocurrent);
|
|
|
8000b26: 4b20 ldr r3, [pc, #128] ; (8000ba8 <HAL_GPIO_Init+0x2d0>)
|
|
|
8000b28: 685a ldr r2, [r3, #4]
|
|
|
8000b2a: 69bb ldr r3, [r7, #24]
|
|
|
8000b2c: 43db mvns r3, r3
|
|
|
8000b2e: 491e ldr r1, [pc, #120] ; (8000ba8 <HAL_GPIO_Init+0x2d0>)
|
|
|
8000b30: 4013 ands r3, r2
|
|
|
8000b32: 604b str r3, [r1, #4]
|
|
|
}
|
|
|
|
|
|
/* Enable or disable the rising trigger */
|
|
|
if ((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
|
|
|
8000b34: 683b ldr r3, [r7, #0]
|
|
|
8000b36: 685b ldr r3, [r3, #4]
|
|
|
8000b38: f403 1380 and.w r3, r3, #1048576 ; 0x100000
|
|
|
8000b3c: 2b00 cmp r3, #0
|
|
|
8000b3e: d006 beq.n 8000b4e <HAL_GPIO_Init+0x276>
|
|
|
{
|
|
|
SET_BIT(EXTI->RTSR, iocurrent);
|
|
|
8000b40: 4b19 ldr r3, [pc, #100] ; (8000ba8 <HAL_GPIO_Init+0x2d0>)
|
|
|
8000b42: 689a ldr r2, [r3, #8]
|
|
|
8000b44: 4918 ldr r1, [pc, #96] ; (8000ba8 <HAL_GPIO_Init+0x2d0>)
|
|
|
8000b46: 69bb ldr r3, [r7, #24]
|
|
|
8000b48: 4313 orrs r3, r2
|
|
|
8000b4a: 608b str r3, [r1, #8]
|
|
|
8000b4c: e006 b.n 8000b5c <HAL_GPIO_Init+0x284>
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
CLEAR_BIT(EXTI->RTSR, iocurrent);
|
|
|
8000b4e: 4b16 ldr r3, [pc, #88] ; (8000ba8 <HAL_GPIO_Init+0x2d0>)
|
|
|
8000b50: 689a ldr r2, [r3, #8]
|
|
|
8000b52: 69bb ldr r3, [r7, #24]
|
|
|
8000b54: 43db mvns r3, r3
|
|
|
8000b56: 4914 ldr r1, [pc, #80] ; (8000ba8 <HAL_GPIO_Init+0x2d0>)
|
|
|
8000b58: 4013 ands r3, r2
|
|
|
8000b5a: 608b str r3, [r1, #8]
|
|
|
}
|
|
|
|
|
|
/* Enable or disable the falling trigger */
|
|
|
if ((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
|
|
|
8000b5c: 683b ldr r3, [r7, #0]
|
|
|
8000b5e: 685b ldr r3, [r3, #4]
|
|
|
8000b60: f403 1300 and.w r3, r3, #2097152 ; 0x200000
|
|
|
8000b64: 2b00 cmp r3, #0
|
|
|
8000b66: d021 beq.n 8000bac <HAL_GPIO_Init+0x2d4>
|
|
|
{
|
|
|
SET_BIT(EXTI->FTSR, iocurrent);
|
|
|
8000b68: 4b0f ldr r3, [pc, #60] ; (8000ba8 <HAL_GPIO_Init+0x2d0>)
|
|
|
8000b6a: 68da ldr r2, [r3, #12]
|
|
|
8000b6c: 490e ldr r1, [pc, #56] ; (8000ba8 <HAL_GPIO_Init+0x2d0>)
|
|
|
8000b6e: 69bb ldr r3, [r7, #24]
|
|
|
8000b70: 4313 orrs r3, r2
|
|
|
8000b72: 60cb str r3, [r1, #12]
|
|
|
8000b74: e021 b.n 8000bba <HAL_GPIO_Init+0x2e2>
|
|
|
8000b76: bf00 nop
|
|
|
8000b78: 10320000 .word 0x10320000
|
|
|
8000b7c: 10310000 .word 0x10310000
|
|
|
8000b80: 10220000 .word 0x10220000
|
|
|
8000b84: 10210000 .word 0x10210000
|
|
|
8000b88: 10120000 .word 0x10120000
|
|
|
8000b8c: 10110000 .word 0x10110000
|
|
|
8000b90: 40021000 .word 0x40021000
|
|
|
8000b94: 40010000 .word 0x40010000
|
|
|
8000b98: 40010800 .word 0x40010800
|
|
|
8000b9c: 40010c00 .word 0x40010c00
|
|
|
8000ba0: 40011000 .word 0x40011000
|
|
|
8000ba4: 40011400 .word 0x40011400
|
|
|
8000ba8: 40010400 .word 0x40010400
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
CLEAR_BIT(EXTI->FTSR, iocurrent);
|
|
|
8000bac: 4b0b ldr r3, [pc, #44] ; (8000bdc <HAL_GPIO_Init+0x304>)
|
|
|
8000bae: 68da ldr r2, [r3, #12]
|
|
|
8000bb0: 69bb ldr r3, [r7, #24]
|
|
|
8000bb2: 43db mvns r3, r3
|
|
|
8000bb4: 4909 ldr r1, [pc, #36] ; (8000bdc <HAL_GPIO_Init+0x304>)
|
|
|
8000bb6: 4013 ands r3, r2
|
|
|
8000bb8: 60cb str r3, [r1, #12]
|
|
|
}
|
|
|
}
|
|
|
}
|
|
|
|
|
|
position++;
|
|
|
8000bba: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
|
8000bbc: 3301 adds r3, #1
|
|
|
8000bbe: 627b str r3, [r7, #36] ; 0x24
|
|
|
while (((GPIO_Init->Pin) >> position) != 0x00u)
|
|
|
8000bc0: 683b ldr r3, [r7, #0]
|
|
|
8000bc2: 681a ldr r2, [r3, #0]
|
|
|
8000bc4: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
|
8000bc6: fa22 f303 lsr.w r3, r2, r3
|
|
|
8000bca: 2b00 cmp r3, #0
|
|
|
8000bcc: f47f ae8e bne.w 80008ec <HAL_GPIO_Init+0x14>
|
|
|
}
|
|
|
}
|
|
|
8000bd0: bf00 nop
|
|
|
8000bd2: bf00 nop
|
|
|
8000bd4: 372c adds r7, #44 ; 0x2c
|
|
|
8000bd6: 46bd mov sp, r7
|
|
|
8000bd8: bc80 pop {r7}
|
|
|
8000bda: 4770 bx lr
|
|
|
8000bdc: 40010400 .word 0x40010400
|
|
|
|
|
|
08000be0 <HAL_PWR_EnableBkUpAccess>:
|
|
|
* @note If the HSE divided by 128 is used as the RTC clock, the
|
|
|
* Backup Domain Access should be kept enabled.
|
|
|
* @retval None
|
|
|
*/
|
|
|
void HAL_PWR_EnableBkUpAccess(void)
|
|
|
{
|
|
|
8000be0: b480 push {r7}
|
|
|
8000be2: af00 add r7, sp, #0
|
|
|
/* Enable access to RTC and backup registers */
|
|
|
*(__IO uint32_t *) CR_DBP_BB = (uint32_t)ENABLE;
|
|
|
8000be4: 4b03 ldr r3, [pc, #12] ; (8000bf4 <HAL_PWR_EnableBkUpAccess+0x14>)
|
|
|
8000be6: 2201 movs r2, #1
|
|
|
8000be8: 601a str r2, [r3, #0]
|
|
|
}
|
|
|
8000bea: bf00 nop
|
|
|
8000bec: 46bd mov sp, r7
|
|
|
8000bee: bc80 pop {r7}
|
|
|
8000bf0: 4770 bx lr
|
|
|
8000bf2: bf00 nop
|
|
|
8000bf4: 420e0020 .word 0x420e0020
|
|
|
|
|
|
08000bf8 <HAL_RCC_OscConfig>:
|
|
|
* supported by this macro. User should request a transition to HSE Off
|
|
|
* first and then HSE On or HSE Bypass.
|
|
|
* @retval HAL status
|
|
|
*/
|
|
|
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
|
|
|
{
|
|
|
8000bf8: b580 push {r7, lr}
|
|
|
8000bfa: b086 sub sp, #24
|
|
|
8000bfc: af00 add r7, sp, #0
|
|
|
8000bfe: 6078 str r0, [r7, #4]
|
|
|
uint32_t tickstart;
|
|
|
uint32_t pll_config;
|
|
|
|
|
|
/* Check Null pointer */
|
|
|
if (RCC_OscInitStruct == NULL)
|
|
|
8000c00: 687b ldr r3, [r7, #4]
|
|
|
8000c02: 2b00 cmp r3, #0
|
|
|
8000c04: d101 bne.n 8000c0a <HAL_RCC_OscConfig+0x12>
|
|
|
{
|
|
|
return HAL_ERROR;
|
|
|
8000c06: 2301 movs r3, #1
|
|
|
8000c08: e272 b.n 80010f0 <HAL_RCC_OscConfig+0x4f8>
|
|
|
|
|
|
/* Check the parameters */
|
|
|
assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
|
|
|
|
|
|
/*------------------------------- HSE Configuration ------------------------*/
|
|
|
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
|
|
|
8000c0a: 687b ldr r3, [r7, #4]
|
|
|
8000c0c: 681b ldr r3, [r3, #0]
|
|
|
8000c0e: f003 0301 and.w r3, r3, #1
|
|
|
8000c12: 2b00 cmp r3, #0
|
|
|
8000c14: f000 8087 beq.w 8000d26 <HAL_RCC_OscConfig+0x12e>
|
|
|
{
|
|
|
/* Check the parameters */
|
|
|
assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
|
|
|
|
|
|
/* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
|
|
|
if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)
|
|
|
8000c18: 4b92 ldr r3, [pc, #584] ; (8000e64 <HAL_RCC_OscConfig+0x26c>)
|
|
|
8000c1a: 685b ldr r3, [r3, #4]
|
|
|
8000c1c: f003 030c and.w r3, r3, #12
|
|
|
8000c20: 2b04 cmp r3, #4
|
|
|
8000c22: d00c beq.n 8000c3e <HAL_RCC_OscConfig+0x46>
|
|
|
|| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE)))
|
|
|
8000c24: 4b8f ldr r3, [pc, #572] ; (8000e64 <HAL_RCC_OscConfig+0x26c>)
|
|
|
8000c26: 685b ldr r3, [r3, #4]
|
|
|
8000c28: f003 030c and.w r3, r3, #12
|
|
|
8000c2c: 2b08 cmp r3, #8
|
|
|
8000c2e: d112 bne.n 8000c56 <HAL_RCC_OscConfig+0x5e>
|
|
|
8000c30: 4b8c ldr r3, [pc, #560] ; (8000e64 <HAL_RCC_OscConfig+0x26c>)
|
|
|
8000c32: 685b ldr r3, [r3, #4]
|
|
|
8000c34: f403 3380 and.w r3, r3, #65536 ; 0x10000
|
|
|
8000c38: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
|
|
|
8000c3c: d10b bne.n 8000c56 <HAL_RCC_OscConfig+0x5e>
|
|
|
{
|
|
|
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
|
|
|
8000c3e: 4b89 ldr r3, [pc, #548] ; (8000e64 <HAL_RCC_OscConfig+0x26c>)
|
|
|
8000c40: 681b ldr r3, [r3, #0]
|
|
|
8000c42: f403 3300 and.w r3, r3, #131072 ; 0x20000
|
|
|
8000c46: 2b00 cmp r3, #0
|
|
|
8000c48: d06c beq.n 8000d24 <HAL_RCC_OscConfig+0x12c>
|
|
|
8000c4a: 687b ldr r3, [r7, #4]
|
|
|
8000c4c: 685b ldr r3, [r3, #4]
|
|
|
8000c4e: 2b00 cmp r3, #0
|
|
|
8000c50: d168 bne.n 8000d24 <HAL_RCC_OscConfig+0x12c>
|
|
|
{
|
|
|
return HAL_ERROR;
|
|
|
8000c52: 2301 movs r3, #1
|
|
|
8000c54: e24c b.n 80010f0 <HAL_RCC_OscConfig+0x4f8>
|
|
|
}
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
/* Set the new HSE configuration ---------------------------------------*/
|
|
|
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
|
|
|
8000c56: 687b ldr r3, [r7, #4]
|
|
|
8000c58: 685b ldr r3, [r3, #4]
|
|
|
8000c5a: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
|
|
|
8000c5e: d106 bne.n 8000c6e <HAL_RCC_OscConfig+0x76>
|
|
|
8000c60: 4b80 ldr r3, [pc, #512] ; (8000e64 <HAL_RCC_OscConfig+0x26c>)
|
|
|
8000c62: 681b ldr r3, [r3, #0]
|
|
|
8000c64: 4a7f ldr r2, [pc, #508] ; (8000e64 <HAL_RCC_OscConfig+0x26c>)
|
|
|
8000c66: f443 3380 orr.w r3, r3, #65536 ; 0x10000
|
|
|
8000c6a: 6013 str r3, [r2, #0]
|
|
|
8000c6c: e02e b.n 8000ccc <HAL_RCC_OscConfig+0xd4>
|
|
|
8000c6e: 687b ldr r3, [r7, #4]
|
|
|
8000c70: 685b ldr r3, [r3, #4]
|
|
|
8000c72: 2b00 cmp r3, #0
|
|
|
8000c74: d10c bne.n 8000c90 <HAL_RCC_OscConfig+0x98>
|
|
|
8000c76: 4b7b ldr r3, [pc, #492] ; (8000e64 <HAL_RCC_OscConfig+0x26c>)
|
|
|
8000c78: 681b ldr r3, [r3, #0]
|
|
|
8000c7a: 4a7a ldr r2, [pc, #488] ; (8000e64 <HAL_RCC_OscConfig+0x26c>)
|
|
|
8000c7c: f423 3380 bic.w r3, r3, #65536 ; 0x10000
|
|
|
8000c80: 6013 str r3, [r2, #0]
|
|
|
8000c82: 4b78 ldr r3, [pc, #480] ; (8000e64 <HAL_RCC_OscConfig+0x26c>)
|
|
|
8000c84: 681b ldr r3, [r3, #0]
|
|
|
8000c86: 4a77 ldr r2, [pc, #476] ; (8000e64 <HAL_RCC_OscConfig+0x26c>)
|
|
|
8000c88: f423 2380 bic.w r3, r3, #262144 ; 0x40000
|
|
|
8000c8c: 6013 str r3, [r2, #0]
|
|
|
8000c8e: e01d b.n 8000ccc <HAL_RCC_OscConfig+0xd4>
|
|
|
8000c90: 687b ldr r3, [r7, #4]
|
|
|
8000c92: 685b ldr r3, [r3, #4]
|
|
|
8000c94: f5b3 2fa0 cmp.w r3, #327680 ; 0x50000
|
|
|
8000c98: d10c bne.n 8000cb4 <HAL_RCC_OscConfig+0xbc>
|
|
|
8000c9a: 4b72 ldr r3, [pc, #456] ; (8000e64 <HAL_RCC_OscConfig+0x26c>)
|
|
|
8000c9c: 681b ldr r3, [r3, #0]
|
|
|
8000c9e: 4a71 ldr r2, [pc, #452] ; (8000e64 <HAL_RCC_OscConfig+0x26c>)
|
|
|
8000ca0: f443 2380 orr.w r3, r3, #262144 ; 0x40000
|
|
|
8000ca4: 6013 str r3, [r2, #0]
|
|
|
8000ca6: 4b6f ldr r3, [pc, #444] ; (8000e64 <HAL_RCC_OscConfig+0x26c>)
|
|
|
8000ca8: 681b ldr r3, [r3, #0]
|
|
|
8000caa: 4a6e ldr r2, [pc, #440] ; (8000e64 <HAL_RCC_OscConfig+0x26c>)
|
|
|
8000cac: f443 3380 orr.w r3, r3, #65536 ; 0x10000
|
|
|
8000cb0: 6013 str r3, [r2, #0]
|
|
|
8000cb2: e00b b.n 8000ccc <HAL_RCC_OscConfig+0xd4>
|
|
|
8000cb4: 4b6b ldr r3, [pc, #428] ; (8000e64 <HAL_RCC_OscConfig+0x26c>)
|
|
|
8000cb6: 681b ldr r3, [r3, #0]
|
|
|
8000cb8: 4a6a ldr r2, [pc, #424] ; (8000e64 <HAL_RCC_OscConfig+0x26c>)
|
|
|
8000cba: f423 3380 bic.w r3, r3, #65536 ; 0x10000
|
|
|
8000cbe: 6013 str r3, [r2, #0]
|
|
|
8000cc0: 4b68 ldr r3, [pc, #416] ; (8000e64 <HAL_RCC_OscConfig+0x26c>)
|
|
|
8000cc2: 681b ldr r3, [r3, #0]
|
|
|
8000cc4: 4a67 ldr r2, [pc, #412] ; (8000e64 <HAL_RCC_OscConfig+0x26c>)
|
|
|
8000cc6: f423 2380 bic.w r3, r3, #262144 ; 0x40000
|
|
|
8000cca: 6013 str r3, [r2, #0]
|
|
|
|
|
|
|
|
|
/* Check the HSE State */
|
|
|
if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
|
|
|
8000ccc: 687b ldr r3, [r7, #4]
|
|
|
8000cce: 685b ldr r3, [r3, #4]
|
|
|
8000cd0: 2b00 cmp r3, #0
|
|
|
8000cd2: d013 beq.n 8000cfc <HAL_RCC_OscConfig+0x104>
|
|
|
{
|
|
|
/* Get Start Tick */
|
|
|
tickstart = HAL_GetTick();
|
|
|
8000cd4: f7ff fcee bl 80006b4 <HAL_GetTick>
|
|
|
8000cd8: 6138 str r0, [r7, #16]
|
|
|
|
|
|
/* Wait till HSE is ready */
|
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
|
|
|
8000cda: e008 b.n 8000cee <HAL_RCC_OscConfig+0xf6>
|
|
|
{
|
|
|
if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
|
|
|
8000cdc: f7ff fcea bl 80006b4 <HAL_GetTick>
|
|
|
8000ce0: 4602 mov r2, r0
|
|
|
8000ce2: 693b ldr r3, [r7, #16]
|
|
|
8000ce4: 1ad3 subs r3, r2, r3
|
|
|
8000ce6: 2b64 cmp r3, #100 ; 0x64
|
|
|
8000ce8: d901 bls.n 8000cee <HAL_RCC_OscConfig+0xf6>
|
|
|
{
|
|
|
return HAL_TIMEOUT;
|
|
|
8000cea: 2303 movs r3, #3
|
|
|
8000cec: e200 b.n 80010f0 <HAL_RCC_OscConfig+0x4f8>
|
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
|
|
|
8000cee: 4b5d ldr r3, [pc, #372] ; (8000e64 <HAL_RCC_OscConfig+0x26c>)
|
|
|
8000cf0: 681b ldr r3, [r3, #0]
|
|
|
8000cf2: f403 3300 and.w r3, r3, #131072 ; 0x20000
|
|
|
8000cf6: 2b00 cmp r3, #0
|
|
|
8000cf8: d0f0 beq.n 8000cdc <HAL_RCC_OscConfig+0xe4>
|
|
|
8000cfa: e014 b.n 8000d26 <HAL_RCC_OscConfig+0x12e>
|
|
|
}
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
/* Get Start Tick */
|
|
|
tickstart = HAL_GetTick();
|
|
|
8000cfc: f7ff fcda bl 80006b4 <HAL_GetTick>
|
|
|
8000d00: 6138 str r0, [r7, #16]
|
|
|
|
|
|
/* Wait till HSE is disabled */
|
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
|
|
|
8000d02: e008 b.n 8000d16 <HAL_RCC_OscConfig+0x11e>
|
|
|
{
|
|
|
if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
|
|
|
8000d04: f7ff fcd6 bl 80006b4 <HAL_GetTick>
|
|
|
8000d08: 4602 mov r2, r0
|
|
|
8000d0a: 693b ldr r3, [r7, #16]
|
|
|
8000d0c: 1ad3 subs r3, r2, r3
|
|
|
8000d0e: 2b64 cmp r3, #100 ; 0x64
|
|
|
8000d10: d901 bls.n 8000d16 <HAL_RCC_OscConfig+0x11e>
|
|
|
{
|
|
|
return HAL_TIMEOUT;
|
|
|
8000d12: 2303 movs r3, #3
|
|
|
8000d14: e1ec b.n 80010f0 <HAL_RCC_OscConfig+0x4f8>
|
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
|
|
|
8000d16: 4b53 ldr r3, [pc, #332] ; (8000e64 <HAL_RCC_OscConfig+0x26c>)
|
|
|
8000d18: 681b ldr r3, [r3, #0]
|
|
|
8000d1a: f403 3300 and.w r3, r3, #131072 ; 0x20000
|
|
|
8000d1e: 2b00 cmp r3, #0
|
|
|
8000d20: d1f0 bne.n 8000d04 <HAL_RCC_OscConfig+0x10c>
|
|
|
8000d22: e000 b.n 8000d26 <HAL_RCC_OscConfig+0x12e>
|
|
|
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
|
|
|
8000d24: bf00 nop
|
|
|
}
|
|
|
}
|
|
|
}
|
|
|
}
|
|
|
/*----------------------------- HSI Configuration --------------------------*/
|
|
|
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
|
|
|
8000d26: 687b ldr r3, [r7, #4]
|
|
|
8000d28: 681b ldr r3, [r3, #0]
|
|
|
8000d2a: f003 0302 and.w r3, r3, #2
|
|
|
8000d2e: 2b00 cmp r3, #0
|
|
|
8000d30: d063 beq.n 8000dfa <HAL_RCC_OscConfig+0x202>
|
|
|
/* Check the parameters */
|
|
|
assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
|
|
|
assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
|
|
|
|
|
|
/* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
|
|
|
if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)
|
|
|
8000d32: 4b4c ldr r3, [pc, #304] ; (8000e64 <HAL_RCC_OscConfig+0x26c>)
|
|
|
8000d34: 685b ldr r3, [r3, #4]
|
|
|
8000d36: f003 030c and.w r3, r3, #12
|
|
|
8000d3a: 2b00 cmp r3, #0
|
|
|
8000d3c: d00b beq.n 8000d56 <HAL_RCC_OscConfig+0x15e>
|
|
|
|| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI_DIV2)))
|
|
|
8000d3e: 4b49 ldr r3, [pc, #292] ; (8000e64 <HAL_RCC_OscConfig+0x26c>)
|
|
|
8000d40: 685b ldr r3, [r3, #4]
|
|
|
8000d42: f003 030c and.w r3, r3, #12
|
|
|
8000d46: 2b08 cmp r3, #8
|
|
|
8000d48: d11c bne.n 8000d84 <HAL_RCC_OscConfig+0x18c>
|
|
|
8000d4a: 4b46 ldr r3, [pc, #280] ; (8000e64 <HAL_RCC_OscConfig+0x26c>)
|
|
|
8000d4c: 685b ldr r3, [r3, #4]
|
|
|
8000d4e: f403 3380 and.w r3, r3, #65536 ; 0x10000
|
|
|
8000d52: 2b00 cmp r3, #0
|
|
|
8000d54: d116 bne.n 8000d84 <HAL_RCC_OscConfig+0x18c>
|
|
|
{
|
|
|
/* When HSI is used as system clock it will not disabled */
|
|
|
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
|
|
|
8000d56: 4b43 ldr r3, [pc, #268] ; (8000e64 <HAL_RCC_OscConfig+0x26c>)
|
|
|
8000d58: 681b ldr r3, [r3, #0]
|
|
|
8000d5a: f003 0302 and.w r3, r3, #2
|
|
|
8000d5e: 2b00 cmp r3, #0
|
|
|
8000d60: d005 beq.n 8000d6e <HAL_RCC_OscConfig+0x176>
|
|
|
8000d62: 687b ldr r3, [r7, #4]
|
|
|
8000d64: 691b ldr r3, [r3, #16]
|
|
|
8000d66: 2b01 cmp r3, #1
|
|
|
8000d68: d001 beq.n 8000d6e <HAL_RCC_OscConfig+0x176>
|
|
|
{
|
|
|
return HAL_ERROR;
|
|
|
8000d6a: 2301 movs r3, #1
|
|
|
8000d6c: e1c0 b.n 80010f0 <HAL_RCC_OscConfig+0x4f8>
|
|
|
}
|
|
|
/* Otherwise, just the calibration is allowed */
|
|
|
else
|
|
|
{
|
|
|
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
|
|
|
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
|
|
|
8000d6e: 4b3d ldr r3, [pc, #244] ; (8000e64 <HAL_RCC_OscConfig+0x26c>)
|
|
|
8000d70: 681b ldr r3, [r3, #0]
|
|
|
8000d72: f023 02f8 bic.w r2, r3, #248 ; 0xf8
|
|
|
8000d76: 687b ldr r3, [r7, #4]
|
|
|
8000d78: 695b ldr r3, [r3, #20]
|
|
|
8000d7a: 00db lsls r3, r3, #3
|
|
|
8000d7c: 4939 ldr r1, [pc, #228] ; (8000e64 <HAL_RCC_OscConfig+0x26c>)
|
|
|
8000d7e: 4313 orrs r3, r2
|
|
|
8000d80: 600b str r3, [r1, #0]
|
|
|
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
|
|
|
8000d82: e03a b.n 8000dfa <HAL_RCC_OscConfig+0x202>
|
|
|
}
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
/* Check the HSI State */
|
|
|
if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
|
|
|
8000d84: 687b ldr r3, [r7, #4]
|
|
|
8000d86: 691b ldr r3, [r3, #16]
|
|
|
8000d88: 2b00 cmp r3, #0
|
|
|
8000d8a: d020 beq.n 8000dce <HAL_RCC_OscConfig+0x1d6>
|
|
|
{
|
|
|
/* Enable the Internal High Speed oscillator (HSI). */
|
|
|
__HAL_RCC_HSI_ENABLE();
|
|
|
8000d8c: 4b36 ldr r3, [pc, #216] ; (8000e68 <HAL_RCC_OscConfig+0x270>)
|
|
|
8000d8e: 2201 movs r2, #1
|
|
|
8000d90: 601a str r2, [r3, #0]
|
|
|
|
|
|
/* Get Start Tick */
|
|
|
tickstart = HAL_GetTick();
|
|
|
8000d92: f7ff fc8f bl 80006b4 <HAL_GetTick>
|
|
|
8000d96: 6138 str r0, [r7, #16]
|
|
|
|
|
|
/* Wait till HSI is ready */
|
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
|
|
|
8000d98: e008 b.n 8000dac <HAL_RCC_OscConfig+0x1b4>
|
|
|
{
|
|
|
if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
|
|
|
8000d9a: f7ff fc8b bl 80006b4 <HAL_GetTick>
|
|
|
8000d9e: 4602 mov r2, r0
|
|
|
8000da0: 693b ldr r3, [r7, #16]
|
|
|
8000da2: 1ad3 subs r3, r2, r3
|
|
|
8000da4: 2b02 cmp r3, #2
|
|
|
8000da6: d901 bls.n 8000dac <HAL_RCC_OscConfig+0x1b4>
|
|
|
{
|
|
|
return HAL_TIMEOUT;
|
|
|
8000da8: 2303 movs r3, #3
|
|
|
8000daa: e1a1 b.n 80010f0 <HAL_RCC_OscConfig+0x4f8>
|
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
|
|
|
8000dac: 4b2d ldr r3, [pc, #180] ; (8000e64 <HAL_RCC_OscConfig+0x26c>)
|
|
|
8000dae: 681b ldr r3, [r3, #0]
|
|
|
8000db0: f003 0302 and.w r3, r3, #2
|
|
|
8000db4: 2b00 cmp r3, #0
|
|
|
8000db6: d0f0 beq.n 8000d9a <HAL_RCC_OscConfig+0x1a2>
|
|
|
}
|
|
|
}
|
|
|
|
|
|
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
|
|
|
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
|
|
|
8000db8: 4b2a ldr r3, [pc, #168] ; (8000e64 <HAL_RCC_OscConfig+0x26c>)
|
|
|
8000dba: 681b ldr r3, [r3, #0]
|
|
|
8000dbc: f023 02f8 bic.w r2, r3, #248 ; 0xf8
|
|
|
8000dc0: 687b ldr r3, [r7, #4]
|
|
|
8000dc2: 695b ldr r3, [r3, #20]
|
|
|
8000dc4: 00db lsls r3, r3, #3
|
|
|
8000dc6: 4927 ldr r1, [pc, #156] ; (8000e64 <HAL_RCC_OscConfig+0x26c>)
|
|
|
8000dc8: 4313 orrs r3, r2
|
|
|
8000dca: 600b str r3, [r1, #0]
|
|
|
8000dcc: e015 b.n 8000dfa <HAL_RCC_OscConfig+0x202>
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
/* Disable the Internal High Speed oscillator (HSI). */
|
|
|
__HAL_RCC_HSI_DISABLE();
|
|
|
8000dce: 4b26 ldr r3, [pc, #152] ; (8000e68 <HAL_RCC_OscConfig+0x270>)
|
|
|
8000dd0: 2200 movs r2, #0
|
|
|
8000dd2: 601a str r2, [r3, #0]
|
|
|
|
|
|
/* Get Start Tick */
|
|
|
tickstart = HAL_GetTick();
|
|
|
8000dd4: f7ff fc6e bl 80006b4 <HAL_GetTick>
|
|
|
8000dd8: 6138 str r0, [r7, #16]
|
|
|
|
|
|
/* Wait till HSI is disabled */
|
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
|
|
|
8000dda: e008 b.n 8000dee <HAL_RCC_OscConfig+0x1f6>
|
|
|
{
|
|
|
if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
|
|
|
8000ddc: f7ff fc6a bl 80006b4 <HAL_GetTick>
|
|
|
8000de0: 4602 mov r2, r0
|
|
|
8000de2: 693b ldr r3, [r7, #16]
|
|
|
8000de4: 1ad3 subs r3, r2, r3
|
|
|
8000de6: 2b02 cmp r3, #2
|
|
|
8000de8: d901 bls.n 8000dee <HAL_RCC_OscConfig+0x1f6>
|
|
|
{
|
|
|
return HAL_TIMEOUT;
|
|
|
8000dea: 2303 movs r3, #3
|
|
|
8000dec: e180 b.n 80010f0 <HAL_RCC_OscConfig+0x4f8>
|
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
|
|
|
8000dee: 4b1d ldr r3, [pc, #116] ; (8000e64 <HAL_RCC_OscConfig+0x26c>)
|
|
|
8000df0: 681b ldr r3, [r3, #0]
|
|
|
8000df2: f003 0302 and.w r3, r3, #2
|
|
|
8000df6: 2b00 cmp r3, #0
|
|
|
8000df8: d1f0 bne.n 8000ddc <HAL_RCC_OscConfig+0x1e4>
|
|
|
}
|
|
|
}
|
|
|
}
|
|
|
}
|
|
|
/*------------------------------ LSI Configuration -------------------------*/
|
|
|
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
|
|
|
8000dfa: 687b ldr r3, [r7, #4]
|
|
|
8000dfc: 681b ldr r3, [r3, #0]
|
|
|
8000dfe: f003 0308 and.w r3, r3, #8
|
|
|
8000e02: 2b00 cmp r3, #0
|
|
|
8000e04: d03a beq.n 8000e7c <HAL_RCC_OscConfig+0x284>
|
|
|
{
|
|
|
/* Check the parameters */
|
|
|
assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
|
|
|
|
|
|
/* Check the LSI State */
|
|
|
if (RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
|
|
|
8000e06: 687b ldr r3, [r7, #4]
|
|
|
8000e08: 699b ldr r3, [r3, #24]
|
|
|
8000e0a: 2b00 cmp r3, #0
|
|
|
8000e0c: d019 beq.n 8000e42 <HAL_RCC_OscConfig+0x24a>
|
|
|
{
|
|
|
/* Enable the Internal Low Speed oscillator (LSI). */
|
|
|
__HAL_RCC_LSI_ENABLE();
|
|
|
8000e0e: 4b17 ldr r3, [pc, #92] ; (8000e6c <HAL_RCC_OscConfig+0x274>)
|
|
|
8000e10: 2201 movs r2, #1
|
|
|
8000e12: 601a str r2, [r3, #0]
|
|
|
|
|
|
/* Get Start Tick */
|
|
|
tickstart = HAL_GetTick();
|
|
|
8000e14: f7ff fc4e bl 80006b4 <HAL_GetTick>
|
|
|
8000e18: 6138 str r0, [r7, #16]
|
|
|
|
|
|
/* Wait till LSI is ready */
|
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
|
|
|
8000e1a: e008 b.n 8000e2e <HAL_RCC_OscConfig+0x236>
|
|
|
{
|
|
|
if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
|
|
|
8000e1c: f7ff fc4a bl 80006b4 <HAL_GetTick>
|
|
|
8000e20: 4602 mov r2, r0
|
|
|
8000e22: 693b ldr r3, [r7, #16]
|
|
|
8000e24: 1ad3 subs r3, r2, r3
|
|
|
8000e26: 2b02 cmp r3, #2
|
|
|
8000e28: d901 bls.n 8000e2e <HAL_RCC_OscConfig+0x236>
|
|
|
{
|
|
|
return HAL_TIMEOUT;
|
|
|
8000e2a: 2303 movs r3, #3
|
|
|
8000e2c: e160 b.n 80010f0 <HAL_RCC_OscConfig+0x4f8>
|
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
|
|
|
8000e2e: 4b0d ldr r3, [pc, #52] ; (8000e64 <HAL_RCC_OscConfig+0x26c>)
|
|
|
8000e30: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
|
8000e32: f003 0302 and.w r3, r3, #2
|
|
|
8000e36: 2b00 cmp r3, #0
|
|
|
8000e38: d0f0 beq.n 8000e1c <HAL_RCC_OscConfig+0x224>
|
|
|
}
|
|
|
}
|
|
|
/* To have a fully stabilized clock in the specified range, a software delay of 1ms
|
|
|
should be added.*/
|
|
|
RCC_Delay(1);
|
|
|
8000e3a: 2001 movs r0, #1
|
|
|
8000e3c: f000 fad8 bl 80013f0 <RCC_Delay>
|
|
|
8000e40: e01c b.n 8000e7c <HAL_RCC_OscConfig+0x284>
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
/* Disable the Internal Low Speed oscillator (LSI). */
|
|
|
__HAL_RCC_LSI_DISABLE();
|
|
|
8000e42: 4b0a ldr r3, [pc, #40] ; (8000e6c <HAL_RCC_OscConfig+0x274>)
|
|
|
8000e44: 2200 movs r2, #0
|
|
|
8000e46: 601a str r2, [r3, #0]
|
|
|
|
|
|
/* Get Start Tick */
|
|
|
tickstart = HAL_GetTick();
|
|
|
8000e48: f7ff fc34 bl 80006b4 <HAL_GetTick>
|
|
|
8000e4c: 6138 str r0, [r7, #16]
|
|
|
|
|
|
/* Wait till LSI is disabled */
|
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
|
|
|
8000e4e: e00f b.n 8000e70 <HAL_RCC_OscConfig+0x278>
|
|
|
{
|
|
|
if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
|
|
|
8000e50: f7ff fc30 bl 80006b4 <HAL_GetTick>
|
|
|
8000e54: 4602 mov r2, r0
|
|
|
8000e56: 693b ldr r3, [r7, #16]
|
|
|
8000e58: 1ad3 subs r3, r2, r3
|
|
|
8000e5a: 2b02 cmp r3, #2
|
|
|
8000e5c: d908 bls.n 8000e70 <HAL_RCC_OscConfig+0x278>
|
|
|
{
|
|
|
return HAL_TIMEOUT;
|
|
|
8000e5e: 2303 movs r3, #3
|
|
|
8000e60: e146 b.n 80010f0 <HAL_RCC_OscConfig+0x4f8>
|
|
|
8000e62: bf00 nop
|
|
|
8000e64: 40021000 .word 0x40021000
|
|
|
8000e68: 42420000 .word 0x42420000
|
|
|
8000e6c: 42420480 .word 0x42420480
|
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
|
|
|
8000e70: 4b92 ldr r3, [pc, #584] ; (80010bc <HAL_RCC_OscConfig+0x4c4>)
|
|
|
8000e72: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
|
8000e74: f003 0302 and.w r3, r3, #2
|
|
|
8000e78: 2b00 cmp r3, #0
|
|
|
8000e7a: d1e9 bne.n 8000e50 <HAL_RCC_OscConfig+0x258>
|
|
|
}
|
|
|
}
|
|
|
}
|
|
|
}
|
|
|
/*------------------------------ LSE Configuration -------------------------*/
|
|
|
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
|
|
|
8000e7c: 687b ldr r3, [r7, #4]
|
|
|
8000e7e: 681b ldr r3, [r3, #0]
|
|
|
8000e80: f003 0304 and.w r3, r3, #4
|
|
|
8000e84: 2b00 cmp r3, #0
|
|
|
8000e86: f000 80a6 beq.w 8000fd6 <HAL_RCC_OscConfig+0x3de>
|
|
|
{
|
|
|
FlagStatus pwrclkchanged = RESET;
|
|
|
8000e8a: 2300 movs r3, #0
|
|
|
8000e8c: 75fb strb r3, [r7, #23]
|
|
|
/* Check the parameters */
|
|
|
assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
|
|
|
|
|
|
/* Update LSE configuration in Backup Domain control register */
|
|
|
/* Requires to enable write access to Backup Domain of necessary */
|
|
|
if (__HAL_RCC_PWR_IS_CLK_DISABLED())
|
|
|
8000e8e: 4b8b ldr r3, [pc, #556] ; (80010bc <HAL_RCC_OscConfig+0x4c4>)
|
|
|
8000e90: 69db ldr r3, [r3, #28]
|
|
|
8000e92: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
|
|
|
8000e96: 2b00 cmp r3, #0
|
|
|
8000e98: d10d bne.n 8000eb6 <HAL_RCC_OscConfig+0x2be>
|
|
|
{
|
|
|
__HAL_RCC_PWR_CLK_ENABLE();
|
|
|
8000e9a: 4b88 ldr r3, [pc, #544] ; (80010bc <HAL_RCC_OscConfig+0x4c4>)
|
|
|
8000e9c: 69db ldr r3, [r3, #28]
|
|
|
8000e9e: 4a87 ldr r2, [pc, #540] ; (80010bc <HAL_RCC_OscConfig+0x4c4>)
|
|
|
8000ea0: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
|
|
|
8000ea4: 61d3 str r3, [r2, #28]
|
|
|
8000ea6: 4b85 ldr r3, [pc, #532] ; (80010bc <HAL_RCC_OscConfig+0x4c4>)
|
|
|
8000ea8: 69db ldr r3, [r3, #28]
|
|
|
8000eaa: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
|
|
|
8000eae: 60bb str r3, [r7, #8]
|
|
|
8000eb0: 68bb ldr r3, [r7, #8]
|
|
|
pwrclkchanged = SET;
|
|
|
8000eb2: 2301 movs r3, #1
|
|
|
8000eb4: 75fb strb r3, [r7, #23]
|
|
|
}
|
|
|
|
|
|
if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
|
|
|
8000eb6: 4b82 ldr r3, [pc, #520] ; (80010c0 <HAL_RCC_OscConfig+0x4c8>)
|
|
|
8000eb8: 681b ldr r3, [r3, #0]
|
|
|
8000eba: f403 7380 and.w r3, r3, #256 ; 0x100
|
|
|
8000ebe: 2b00 cmp r3, #0
|
|
|
8000ec0: d118 bne.n 8000ef4 <HAL_RCC_OscConfig+0x2fc>
|
|
|
{
|
|
|
/* Enable write access to Backup domain */
|
|
|
SET_BIT(PWR->CR, PWR_CR_DBP);
|
|
|
8000ec2: 4b7f ldr r3, [pc, #508] ; (80010c0 <HAL_RCC_OscConfig+0x4c8>)
|
|
|
8000ec4: 681b ldr r3, [r3, #0]
|
|
|
8000ec6: 4a7e ldr r2, [pc, #504] ; (80010c0 <HAL_RCC_OscConfig+0x4c8>)
|
|
|
8000ec8: f443 7380 orr.w r3, r3, #256 ; 0x100
|
|
|
8000ecc: 6013 str r3, [r2, #0]
|
|
|
|
|
|
/* Wait for Backup domain Write protection disable */
|
|
|
tickstart = HAL_GetTick();
|
|
|
8000ece: f7ff fbf1 bl 80006b4 <HAL_GetTick>
|
|
|
8000ed2: 6138 str r0, [r7, #16]
|
|
|
|
|
|
while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
|
|
|
8000ed4: e008 b.n 8000ee8 <HAL_RCC_OscConfig+0x2f0>
|
|
|
{
|
|
|
if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
|
|
|
8000ed6: f7ff fbed bl 80006b4 <HAL_GetTick>
|
|
|
8000eda: 4602 mov r2, r0
|
|
|
8000edc: 693b ldr r3, [r7, #16]
|
|
|
8000ede: 1ad3 subs r3, r2, r3
|
|
|
8000ee0: 2b64 cmp r3, #100 ; 0x64
|
|
|
8000ee2: d901 bls.n 8000ee8 <HAL_RCC_OscConfig+0x2f0>
|
|
|
{
|
|
|
return HAL_TIMEOUT;
|
|
|
8000ee4: 2303 movs r3, #3
|
|
|
8000ee6: e103 b.n 80010f0 <HAL_RCC_OscConfig+0x4f8>
|
|
|
while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
|
|
|
8000ee8: 4b75 ldr r3, [pc, #468] ; (80010c0 <HAL_RCC_OscConfig+0x4c8>)
|
|
|
8000eea: 681b ldr r3, [r3, #0]
|
|
|
8000eec: f403 7380 and.w r3, r3, #256 ; 0x100
|
|
|
8000ef0: 2b00 cmp r3, #0
|
|
|
8000ef2: d0f0 beq.n 8000ed6 <HAL_RCC_OscConfig+0x2de>
|
|
|
}
|
|
|
}
|
|
|
}
|
|
|
|
|
|
/* Set the new LSE configuration -----------------------------------------*/
|
|
|
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
|
|
|
8000ef4: 687b ldr r3, [r7, #4]
|
|
|
8000ef6: 68db ldr r3, [r3, #12]
|
|
|
8000ef8: 2b01 cmp r3, #1
|
|
|
8000efa: d106 bne.n 8000f0a <HAL_RCC_OscConfig+0x312>
|
|
|
8000efc: 4b6f ldr r3, [pc, #444] ; (80010bc <HAL_RCC_OscConfig+0x4c4>)
|
|
|
8000efe: 6a1b ldr r3, [r3, #32]
|
|
|
8000f00: 4a6e ldr r2, [pc, #440] ; (80010bc <HAL_RCC_OscConfig+0x4c4>)
|
|
|
8000f02: f043 0301 orr.w r3, r3, #1
|
|
|
8000f06: 6213 str r3, [r2, #32]
|
|
|
8000f08: e02d b.n 8000f66 <HAL_RCC_OscConfig+0x36e>
|
|
|
8000f0a: 687b ldr r3, [r7, #4]
|
|
|
8000f0c: 68db ldr r3, [r3, #12]
|
|
|
8000f0e: 2b00 cmp r3, #0
|
|
|
8000f10: d10c bne.n 8000f2c <HAL_RCC_OscConfig+0x334>
|
|
|
8000f12: 4b6a ldr r3, [pc, #424] ; (80010bc <HAL_RCC_OscConfig+0x4c4>)
|
|
|
8000f14: 6a1b ldr r3, [r3, #32]
|
|
|
8000f16: 4a69 ldr r2, [pc, #420] ; (80010bc <HAL_RCC_OscConfig+0x4c4>)
|
|
|
8000f18: f023 0301 bic.w r3, r3, #1
|
|
|
8000f1c: 6213 str r3, [r2, #32]
|
|
|
8000f1e: 4b67 ldr r3, [pc, #412] ; (80010bc <HAL_RCC_OscConfig+0x4c4>)
|
|
|
8000f20: 6a1b ldr r3, [r3, #32]
|
|
|
8000f22: 4a66 ldr r2, [pc, #408] ; (80010bc <HAL_RCC_OscConfig+0x4c4>)
|
|
|
8000f24: f023 0304 bic.w r3, r3, #4
|
|
|
8000f28: 6213 str r3, [r2, #32]
|
|
|
8000f2a: e01c b.n 8000f66 <HAL_RCC_OscConfig+0x36e>
|
|
|
8000f2c: 687b ldr r3, [r7, #4]
|
|
|
8000f2e: 68db ldr r3, [r3, #12]
|
|
|
8000f30: 2b05 cmp r3, #5
|
|
|
8000f32: d10c bne.n 8000f4e <HAL_RCC_OscConfig+0x356>
|
|
|
8000f34: 4b61 ldr r3, [pc, #388] ; (80010bc <HAL_RCC_OscConfig+0x4c4>)
|
|
|
8000f36: 6a1b ldr r3, [r3, #32]
|
|
|
8000f38: 4a60 ldr r2, [pc, #384] ; (80010bc <HAL_RCC_OscConfig+0x4c4>)
|
|
|
8000f3a: f043 0304 orr.w r3, r3, #4
|
|
|
8000f3e: 6213 str r3, [r2, #32]
|
|
|
8000f40: 4b5e ldr r3, [pc, #376] ; (80010bc <HAL_RCC_OscConfig+0x4c4>)
|
|
|
8000f42: 6a1b ldr r3, [r3, #32]
|
|
|
8000f44: 4a5d ldr r2, [pc, #372] ; (80010bc <HAL_RCC_OscConfig+0x4c4>)
|
|
|
8000f46: f043 0301 orr.w r3, r3, #1
|
|
|
8000f4a: 6213 str r3, [r2, #32]
|
|
|
8000f4c: e00b b.n 8000f66 <HAL_RCC_OscConfig+0x36e>
|
|
|
8000f4e: 4b5b ldr r3, [pc, #364] ; (80010bc <HAL_RCC_OscConfig+0x4c4>)
|
|
|
8000f50: 6a1b ldr r3, [r3, #32]
|
|
|
8000f52: 4a5a ldr r2, [pc, #360] ; (80010bc <HAL_RCC_OscConfig+0x4c4>)
|
|
|
8000f54: f023 0301 bic.w r3, r3, #1
|
|
|
8000f58: 6213 str r3, [r2, #32]
|
|
|
8000f5a: 4b58 ldr r3, [pc, #352] ; (80010bc <HAL_RCC_OscConfig+0x4c4>)
|
|
|
8000f5c: 6a1b ldr r3, [r3, #32]
|
|
|
8000f5e: 4a57 ldr r2, [pc, #348] ; (80010bc <HAL_RCC_OscConfig+0x4c4>)
|
|
|
8000f60: f023 0304 bic.w r3, r3, #4
|
|
|
8000f64: 6213 str r3, [r2, #32]
|
|
|
/* Check the LSE State */
|
|
|
if (RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
|
|
|
8000f66: 687b ldr r3, [r7, #4]
|
|
|
8000f68: 68db ldr r3, [r3, #12]
|
|
|
8000f6a: 2b00 cmp r3, #0
|
|
|
8000f6c: d015 beq.n 8000f9a <HAL_RCC_OscConfig+0x3a2>
|
|
|
{
|
|
|
/* Get Start Tick */
|
|
|
tickstart = HAL_GetTick();
|
|
|
8000f6e: f7ff fba1 bl 80006b4 <HAL_GetTick>
|
|
|
8000f72: 6138 str r0, [r7, #16]
|
|
|
|
|
|
/* Wait till LSE is ready */
|
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
|
|
|
8000f74: e00a b.n 8000f8c <HAL_RCC_OscConfig+0x394>
|
|
|
{
|
|
|
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
|
|
|
8000f76: f7ff fb9d bl 80006b4 <HAL_GetTick>
|
|
|
8000f7a: 4602 mov r2, r0
|
|
|
8000f7c: 693b ldr r3, [r7, #16]
|
|
|
8000f7e: 1ad3 subs r3, r2, r3
|
|
|
8000f80: f241 3288 movw r2, #5000 ; 0x1388
|
|
|
8000f84: 4293 cmp r3, r2
|
|
|
8000f86: d901 bls.n 8000f8c <HAL_RCC_OscConfig+0x394>
|
|
|
{
|
|
|
return HAL_TIMEOUT;
|
|
|
8000f88: 2303 movs r3, #3
|
|
|
8000f8a: e0b1 b.n 80010f0 <HAL_RCC_OscConfig+0x4f8>
|
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
|
|
|
8000f8c: 4b4b ldr r3, [pc, #300] ; (80010bc <HAL_RCC_OscConfig+0x4c4>)
|
|
|
8000f8e: 6a1b ldr r3, [r3, #32]
|
|
|
8000f90: f003 0302 and.w r3, r3, #2
|
|
|
8000f94: 2b00 cmp r3, #0
|
|
|
8000f96: d0ee beq.n 8000f76 <HAL_RCC_OscConfig+0x37e>
|
|
|
8000f98: e014 b.n 8000fc4 <HAL_RCC_OscConfig+0x3cc>
|
|
|
}
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
/* Get Start Tick */
|
|
|
tickstart = HAL_GetTick();
|
|
|
8000f9a: f7ff fb8b bl 80006b4 <HAL_GetTick>
|
|
|
8000f9e: 6138 str r0, [r7, #16]
|
|
|
|
|
|
/* Wait till LSE is disabled */
|
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
|
|
|
8000fa0: e00a b.n 8000fb8 <HAL_RCC_OscConfig+0x3c0>
|
|
|
{
|
|
|
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
|
|
|
8000fa2: f7ff fb87 bl 80006b4 <HAL_GetTick>
|
|
|
8000fa6: 4602 mov r2, r0
|
|
|
8000fa8: 693b ldr r3, [r7, #16]
|
|
|
8000faa: 1ad3 subs r3, r2, r3
|
|
|
8000fac: f241 3288 movw r2, #5000 ; 0x1388
|
|
|
8000fb0: 4293 cmp r3, r2
|
|
|
8000fb2: d901 bls.n 8000fb8 <HAL_RCC_OscConfig+0x3c0>
|
|
|
{
|
|
|
return HAL_TIMEOUT;
|
|
|
8000fb4: 2303 movs r3, #3
|
|
|
8000fb6: e09b b.n 80010f0 <HAL_RCC_OscConfig+0x4f8>
|
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
|
|
|
8000fb8: 4b40 ldr r3, [pc, #256] ; (80010bc <HAL_RCC_OscConfig+0x4c4>)
|
|
|
8000fba: 6a1b ldr r3, [r3, #32]
|
|
|
8000fbc: f003 0302 and.w r3, r3, #2
|
|
|
8000fc0: 2b00 cmp r3, #0
|
|
|
8000fc2: d1ee bne.n 8000fa2 <HAL_RCC_OscConfig+0x3aa>
|
|
|
}
|
|
|
}
|
|
|
}
|
|
|
|
|
|
/* Require to disable power clock if necessary */
|
|
|
if (pwrclkchanged == SET)
|
|
|
8000fc4: 7dfb ldrb r3, [r7, #23]
|
|
|
8000fc6: 2b01 cmp r3, #1
|
|
|
8000fc8: d105 bne.n 8000fd6 <HAL_RCC_OscConfig+0x3de>
|
|
|
{
|
|
|
__HAL_RCC_PWR_CLK_DISABLE();
|
|
|
8000fca: 4b3c ldr r3, [pc, #240] ; (80010bc <HAL_RCC_OscConfig+0x4c4>)
|
|
|
8000fcc: 69db ldr r3, [r3, #28]
|
|
|
8000fce: 4a3b ldr r2, [pc, #236] ; (80010bc <HAL_RCC_OscConfig+0x4c4>)
|
|
|
8000fd0: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000
|
|
|
8000fd4: 61d3 str r3, [r2, #28]
|
|
|
|
|
|
#endif /* RCC_CR_PLL2ON */
|
|
|
/*-------------------------------- PLL Configuration -----------------------*/
|
|
|
/* Check the parameters */
|
|
|
assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
|
|
|
if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
|
|
|
8000fd6: 687b ldr r3, [r7, #4]
|
|
|
8000fd8: 69db ldr r3, [r3, #28]
|
|
|
8000fda: 2b00 cmp r3, #0
|
|
|
8000fdc: f000 8087 beq.w 80010ee <HAL_RCC_OscConfig+0x4f6>
|
|
|
{
|
|
|
/* Check if the PLL is used as system clock or not */
|
|
|
if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
|
|
|
8000fe0: 4b36 ldr r3, [pc, #216] ; (80010bc <HAL_RCC_OscConfig+0x4c4>)
|
|
|
8000fe2: 685b ldr r3, [r3, #4]
|
|
|
8000fe4: f003 030c and.w r3, r3, #12
|
|
|
8000fe8: 2b08 cmp r3, #8
|
|
|
8000fea: d061 beq.n 80010b0 <HAL_RCC_OscConfig+0x4b8>
|
|
|
{
|
|
|
if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
|
|
|
8000fec: 687b ldr r3, [r7, #4]
|
|
|
8000fee: 69db ldr r3, [r3, #28]
|
|
|
8000ff0: 2b02 cmp r3, #2
|
|
|
8000ff2: d146 bne.n 8001082 <HAL_RCC_OscConfig+0x48a>
|
|
|
/* Check the parameters */
|
|
|
assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
|
|
|
assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL));
|
|
|
|
|
|
/* Disable the main PLL. */
|
|
|
__HAL_RCC_PLL_DISABLE();
|
|
|
8000ff4: 4b33 ldr r3, [pc, #204] ; (80010c4 <HAL_RCC_OscConfig+0x4cc>)
|
|
|
8000ff6: 2200 movs r2, #0
|
|
|
8000ff8: 601a str r2, [r3, #0]
|
|
|
|
|
|
/* Get Start Tick */
|
|
|
tickstart = HAL_GetTick();
|
|
|
8000ffa: f7ff fb5b bl 80006b4 <HAL_GetTick>
|
|
|
8000ffe: 6138 str r0, [r7, #16]
|
|
|
|
|
|
/* Wait till PLL is disabled */
|
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
|
|
|
8001000: e008 b.n 8001014 <HAL_RCC_OscConfig+0x41c>
|
|
|
{
|
|
|
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
|
|
|
8001002: f7ff fb57 bl 80006b4 <HAL_GetTick>
|
|
|
8001006: 4602 mov r2, r0
|
|
|
8001008: 693b ldr r3, [r7, #16]
|
|
|
800100a: 1ad3 subs r3, r2, r3
|
|
|
800100c: 2b02 cmp r3, #2
|
|
|
800100e: d901 bls.n 8001014 <HAL_RCC_OscConfig+0x41c>
|
|
|
{
|
|
|
return HAL_TIMEOUT;
|
|
|
8001010: 2303 movs r3, #3
|
|
|
8001012: e06d b.n 80010f0 <HAL_RCC_OscConfig+0x4f8>
|
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
|
|
|
8001014: 4b29 ldr r3, [pc, #164] ; (80010bc <HAL_RCC_OscConfig+0x4c4>)
|
|
|
8001016: 681b ldr r3, [r3, #0]
|
|
|
8001018: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
|
|
|
800101c: 2b00 cmp r3, #0
|
|
|
800101e: d1f0 bne.n 8001002 <HAL_RCC_OscConfig+0x40a>
|
|
|
}
|
|
|
}
|
|
|
|
|
|
/* Configure the HSE prediv factor --------------------------------*/
|
|
|
/* It can be written only when the PLL is disabled. Not used in PLL source is different than HSE */
|
|
|
if (RCC_OscInitStruct->PLL.PLLSource == RCC_PLLSOURCE_HSE)
|
|
|
8001020: 687b ldr r3, [r7, #4]
|
|
|
8001022: 6a1b ldr r3, [r3, #32]
|
|
|
8001024: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
|
|
|
8001028: d108 bne.n 800103c <HAL_RCC_OscConfig+0x444>
|
|
|
/* Set PREDIV1 source */
|
|
|
SET_BIT(RCC->CFGR2, RCC_OscInitStruct->Prediv1Source);
|
|
|
#endif /* RCC_CFGR2_PREDIV1SRC */
|
|
|
|
|
|
/* Set PREDIV1 Value */
|
|
|
__HAL_RCC_HSE_PREDIV_CONFIG(RCC_OscInitStruct->HSEPredivValue);
|
|
|
800102a: 4b24 ldr r3, [pc, #144] ; (80010bc <HAL_RCC_OscConfig+0x4c4>)
|
|
|
800102c: 685b ldr r3, [r3, #4]
|
|
|
800102e: f423 3200 bic.w r2, r3, #131072 ; 0x20000
|
|
|
8001032: 687b ldr r3, [r7, #4]
|
|
|
8001034: 689b ldr r3, [r3, #8]
|
|
|
8001036: 4921 ldr r1, [pc, #132] ; (80010bc <HAL_RCC_OscConfig+0x4c4>)
|
|
|
8001038: 4313 orrs r3, r2
|
|
|
800103a: 604b str r3, [r1, #4]
|
|
|
}
|
|
|
|
|
|
/* Configure the main PLL clock source and multiplication factors. */
|
|
|
__HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
|
|
|
800103c: 4b1f ldr r3, [pc, #124] ; (80010bc <HAL_RCC_OscConfig+0x4c4>)
|
|
|
800103e: 685b ldr r3, [r3, #4]
|
|
|
8001040: f423 1274 bic.w r2, r3, #3997696 ; 0x3d0000
|
|
|
8001044: 687b ldr r3, [r7, #4]
|
|
|
8001046: 6a19 ldr r1, [r3, #32]
|
|
|
8001048: 687b ldr r3, [r7, #4]
|
|
|
800104a: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
|
800104c: 430b orrs r3, r1
|
|
|
800104e: 491b ldr r1, [pc, #108] ; (80010bc <HAL_RCC_OscConfig+0x4c4>)
|
|
|
8001050: 4313 orrs r3, r2
|
|
|
8001052: 604b str r3, [r1, #4]
|
|
|
RCC_OscInitStruct->PLL.PLLMUL);
|
|
|
/* Enable the main PLL. */
|
|
|
__HAL_RCC_PLL_ENABLE();
|
|
|
8001054: 4b1b ldr r3, [pc, #108] ; (80010c4 <HAL_RCC_OscConfig+0x4cc>)
|
|
|
8001056: 2201 movs r2, #1
|
|
|
8001058: 601a str r2, [r3, #0]
|
|
|
|
|
|
/* Get Start Tick */
|
|
|
tickstart = HAL_GetTick();
|
|
|
800105a: f7ff fb2b bl 80006b4 <HAL_GetTick>
|
|
|
800105e: 6138 str r0, [r7, #16]
|
|
|
|
|
|
/* Wait till PLL is ready */
|
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
|
|
|
8001060: e008 b.n 8001074 <HAL_RCC_OscConfig+0x47c>
|
|
|
{
|
|
|
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
|
|
|
8001062: f7ff fb27 bl 80006b4 <HAL_GetTick>
|
|
|
8001066: 4602 mov r2, r0
|
|
|
8001068: 693b ldr r3, [r7, #16]
|
|
|
800106a: 1ad3 subs r3, r2, r3
|
|
|
800106c: 2b02 cmp r3, #2
|
|
|
800106e: d901 bls.n 8001074 <HAL_RCC_OscConfig+0x47c>
|
|
|
{
|
|
|
return HAL_TIMEOUT;
|
|
|
8001070: 2303 movs r3, #3
|
|
|
8001072: e03d b.n 80010f0 <HAL_RCC_OscConfig+0x4f8>
|
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
|
|
|
8001074: 4b11 ldr r3, [pc, #68] ; (80010bc <HAL_RCC_OscConfig+0x4c4>)
|
|
|
8001076: 681b ldr r3, [r3, #0]
|
|
|
8001078: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
|
|
|
800107c: 2b00 cmp r3, #0
|
|
|
800107e: d0f0 beq.n 8001062 <HAL_RCC_OscConfig+0x46a>
|
|
|
8001080: e035 b.n 80010ee <HAL_RCC_OscConfig+0x4f6>
|
|
|
}
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
/* Disable the main PLL. */
|
|
|
__HAL_RCC_PLL_DISABLE();
|
|
|
8001082: 4b10 ldr r3, [pc, #64] ; (80010c4 <HAL_RCC_OscConfig+0x4cc>)
|
|
|
8001084: 2200 movs r2, #0
|
|
|
8001086: 601a str r2, [r3, #0]
|
|
|
|
|
|
/* Get Start Tick */
|
|
|
tickstart = HAL_GetTick();
|
|
|
8001088: f7ff fb14 bl 80006b4 <HAL_GetTick>
|
|
|
800108c: 6138 str r0, [r7, #16]
|
|
|
|
|
|
/* Wait till PLL is disabled */
|
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
|
|
|
800108e: e008 b.n 80010a2 <HAL_RCC_OscConfig+0x4aa>
|
|
|
{
|
|
|
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
|
|
|
8001090: f7ff fb10 bl 80006b4 <HAL_GetTick>
|
|
|
8001094: 4602 mov r2, r0
|
|
|
8001096: 693b ldr r3, [r7, #16]
|
|
|
8001098: 1ad3 subs r3, r2, r3
|
|
|
800109a: 2b02 cmp r3, #2
|
|
|
800109c: d901 bls.n 80010a2 <HAL_RCC_OscConfig+0x4aa>
|
|
|
{
|
|
|
return HAL_TIMEOUT;
|
|
|
800109e: 2303 movs r3, #3
|
|
|
80010a0: e026 b.n 80010f0 <HAL_RCC_OscConfig+0x4f8>
|
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
|
|
|
80010a2: 4b06 ldr r3, [pc, #24] ; (80010bc <HAL_RCC_OscConfig+0x4c4>)
|
|
|
80010a4: 681b ldr r3, [r3, #0]
|
|
|
80010a6: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
|
|
|
80010aa: 2b00 cmp r3, #0
|
|
|
80010ac: d1f0 bne.n 8001090 <HAL_RCC_OscConfig+0x498>
|
|
|
80010ae: e01e b.n 80010ee <HAL_RCC_OscConfig+0x4f6>
|
|
|
}
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
/* Check if there is a request to disable the PLL used as System clock source */
|
|
|
if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
|
|
|
80010b0: 687b ldr r3, [r7, #4]
|
|
|
80010b2: 69db ldr r3, [r3, #28]
|
|
|
80010b4: 2b01 cmp r3, #1
|
|
|
80010b6: d107 bne.n 80010c8 <HAL_RCC_OscConfig+0x4d0>
|
|
|
{
|
|
|
return HAL_ERROR;
|
|
|
80010b8: 2301 movs r3, #1
|
|
|
80010ba: e019 b.n 80010f0 <HAL_RCC_OscConfig+0x4f8>
|
|
|
80010bc: 40021000 .word 0x40021000
|
|
|
80010c0: 40007000 .word 0x40007000
|
|
|
80010c4: 42420060 .word 0x42420060
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
/* Do not return HAL_ERROR if request repeats the current configuration */
|
|
|
pll_config = RCC->CFGR;
|
|
|
80010c8: 4b0b ldr r3, [pc, #44] ; (80010f8 <HAL_RCC_OscConfig+0x500>)
|
|
|
80010ca: 685b ldr r3, [r3, #4]
|
|
|
80010cc: 60fb str r3, [r7, #12]
|
|
|
if ((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
|
|
|
80010ce: 68fb ldr r3, [r7, #12]
|
|
|
80010d0: f403 3280 and.w r2, r3, #65536 ; 0x10000
|
|
|
80010d4: 687b ldr r3, [r7, #4]
|
|
|
80010d6: 6a1b ldr r3, [r3, #32]
|
|
|
80010d8: 429a cmp r2, r3
|
|
|
80010da: d106 bne.n 80010ea <HAL_RCC_OscConfig+0x4f2>
|
|
|
(READ_BIT(pll_config, RCC_CFGR_PLLMULL) != RCC_OscInitStruct->PLL.PLLMUL))
|
|
|
80010dc: 68fb ldr r3, [r7, #12]
|
|
|
80010de: f403 1270 and.w r2, r3, #3932160 ; 0x3c0000
|
|
|
80010e2: 687b ldr r3, [r7, #4]
|
|
|
80010e4: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
|
if ((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
|
|
|
80010e6: 429a cmp r2, r3
|
|
|
80010e8: d001 beq.n 80010ee <HAL_RCC_OscConfig+0x4f6>
|
|
|
{
|
|
|
return HAL_ERROR;
|
|
|
80010ea: 2301 movs r3, #1
|
|
|
80010ec: e000 b.n 80010f0 <HAL_RCC_OscConfig+0x4f8>
|
|
|
}
|
|
|
}
|
|
|
}
|
|
|
}
|
|
|
|
|
|
return HAL_OK;
|
|
|
80010ee: 2300 movs r3, #0
|
|
|
}
|
|
|
80010f0: 4618 mov r0, r3
|
|
|
80010f2: 3718 adds r7, #24
|
|
|
80010f4: 46bd mov sp, r7
|
|
|
80010f6: bd80 pop {r7, pc}
|
|
|
80010f8: 40021000 .word 0x40021000
|
|
|
|
|
|
080010fc <HAL_RCC_ClockConfig>:
|
|
|
* You can use @ref HAL_RCC_GetClockConfig() function to know which clock is
|
|
|
* currently used as system clock source.
|
|
|
* @retval HAL status
|
|
|
*/
|
|
|
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
|
|
|
{
|
|
|
80010fc: b580 push {r7, lr}
|
|
|
80010fe: b084 sub sp, #16
|
|
|
8001100: af00 add r7, sp, #0
|
|
|
8001102: 6078 str r0, [r7, #4]
|
|
|
8001104: 6039 str r1, [r7, #0]
|
|
|
uint32_t tickstart;
|
|
|
|
|
|
/* Check Null pointer */
|
|
|
if (RCC_ClkInitStruct == NULL)
|
|
|
8001106: 687b ldr r3, [r7, #4]
|
|
|
8001108: 2b00 cmp r3, #0
|
|
|
800110a: d101 bne.n 8001110 <HAL_RCC_ClockConfig+0x14>
|
|
|
{
|
|
|
return HAL_ERROR;
|
|
|
800110c: 2301 movs r3, #1
|
|
|
800110e: e0d0 b.n 80012b2 <HAL_RCC_ClockConfig+0x1b6>
|
|
|
must be correctly programmed according to the frequency of the CPU clock
|
|
|
(HCLK) of the device. */
|
|
|
|
|
|
#if defined(FLASH_ACR_LATENCY)
|
|
|
/* Increasing the number of wait states because of higher CPU frequency */
|
|
|
if (FLatency > __HAL_FLASH_GET_LATENCY())
|
|
|
8001110: 4b6a ldr r3, [pc, #424] ; (80012bc <HAL_RCC_ClockConfig+0x1c0>)
|
|
|
8001112: 681b ldr r3, [r3, #0]
|
|
|
8001114: f003 0307 and.w r3, r3, #7
|
|
|
8001118: 683a ldr r2, [r7, #0]
|
|
|
800111a: 429a cmp r2, r3
|
|
|
800111c: d910 bls.n 8001140 <HAL_RCC_ClockConfig+0x44>
|
|
|
{
|
|
|
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
|
|
|
__HAL_FLASH_SET_LATENCY(FLatency);
|
|
|
800111e: 4b67 ldr r3, [pc, #412] ; (80012bc <HAL_RCC_ClockConfig+0x1c0>)
|
|
|
8001120: 681b ldr r3, [r3, #0]
|
|
|
8001122: f023 0207 bic.w r2, r3, #7
|
|
|
8001126: 4965 ldr r1, [pc, #404] ; (80012bc <HAL_RCC_ClockConfig+0x1c0>)
|
|
|
8001128: 683b ldr r3, [r7, #0]
|
|
|
800112a: 4313 orrs r3, r2
|
|
|
800112c: 600b str r3, [r1, #0]
|
|
|
|
|
|
/* Check that the new number of wait states is taken into account to access the Flash
|
|
|
memory by reading the FLASH_ACR register */
|
|
|
if (__HAL_FLASH_GET_LATENCY() != FLatency)
|
|
|
800112e: 4b63 ldr r3, [pc, #396] ; (80012bc <HAL_RCC_ClockConfig+0x1c0>)
|
|
|
8001130: 681b ldr r3, [r3, #0]
|
|
|
8001132: f003 0307 and.w r3, r3, #7
|
|
|
8001136: 683a ldr r2, [r7, #0]
|
|
|
8001138: 429a cmp r2, r3
|
|
|
800113a: d001 beq.n 8001140 <HAL_RCC_ClockConfig+0x44>
|
|
|
{
|
|
|
return HAL_ERROR;
|
|
|
800113c: 2301 movs r3, #1
|
|
|
800113e: e0b8 b.n 80012b2 <HAL_RCC_ClockConfig+0x1b6>
|
|
|
}
|
|
|
}
|
|
|
|
|
|
#endif /* FLASH_ACR_LATENCY */
|
|
|
/*-------------------------- HCLK Configuration --------------------------*/
|
|
|
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
|
|
|
8001140: 687b ldr r3, [r7, #4]
|
|
|
8001142: 681b ldr r3, [r3, #0]
|
|
|
8001144: f003 0302 and.w r3, r3, #2
|
|
|
8001148: 2b00 cmp r3, #0
|
|
|
800114a: d020 beq.n 800118e <HAL_RCC_ClockConfig+0x92>
|
|
|
{
|
|
|
/* Set the highest APBx dividers in order to ensure that we do not go through
|
|
|
a non-spec phase whatever we decrease or increase HCLK. */
|
|
|
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
|
|
|
800114c: 687b ldr r3, [r7, #4]
|
|
|
800114e: 681b ldr r3, [r3, #0]
|
|
|
8001150: f003 0304 and.w r3, r3, #4
|
|
|
8001154: 2b00 cmp r3, #0
|
|
|
8001156: d005 beq.n 8001164 <HAL_RCC_ClockConfig+0x68>
|
|
|
{
|
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16);
|
|
|
8001158: 4b59 ldr r3, [pc, #356] ; (80012c0 <HAL_RCC_ClockConfig+0x1c4>)
|
|
|
800115a: 685b ldr r3, [r3, #4]
|
|
|
800115c: 4a58 ldr r2, [pc, #352] ; (80012c0 <HAL_RCC_ClockConfig+0x1c4>)
|
|
|
800115e: f443 63e0 orr.w r3, r3, #1792 ; 0x700
|
|
|
8001162: 6053 str r3, [r2, #4]
|
|
|
}
|
|
|
|
|
|
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
|
|
|
8001164: 687b ldr r3, [r7, #4]
|
|
|
8001166: 681b ldr r3, [r3, #0]
|
|
|
8001168: f003 0308 and.w r3, r3, #8
|
|
|
800116c: 2b00 cmp r3, #0
|
|
|
800116e: d005 beq.n 800117c <HAL_RCC_ClockConfig+0x80>
|
|
|
{
|
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3));
|
|
|
8001170: 4b53 ldr r3, [pc, #332] ; (80012c0 <HAL_RCC_ClockConfig+0x1c4>)
|
|
|
8001172: 685b ldr r3, [r3, #4]
|
|
|
8001174: 4a52 ldr r2, [pc, #328] ; (80012c0 <HAL_RCC_ClockConfig+0x1c4>)
|
|
|
8001176: f443 5360 orr.w r3, r3, #14336 ; 0x3800
|
|
|
800117a: 6053 str r3, [r2, #4]
|
|
|
}
|
|
|
|
|
|
/* Set the new HCLK clock divider */
|
|
|
assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
|
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
|
|
|
800117c: 4b50 ldr r3, [pc, #320] ; (80012c0 <HAL_RCC_ClockConfig+0x1c4>)
|
|
|
800117e: 685b ldr r3, [r3, #4]
|
|
|
8001180: f023 02f0 bic.w r2, r3, #240 ; 0xf0
|
|
|
8001184: 687b ldr r3, [r7, #4]
|
|
|
8001186: 689b ldr r3, [r3, #8]
|
|
|
8001188: 494d ldr r1, [pc, #308] ; (80012c0 <HAL_RCC_ClockConfig+0x1c4>)
|
|
|
800118a: 4313 orrs r3, r2
|
|
|
800118c: 604b str r3, [r1, #4]
|
|
|
}
|
|
|
|
|
|
/*------------------------- SYSCLK Configuration ---------------------------*/
|
|
|
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
|
|
|
800118e: 687b ldr r3, [r7, #4]
|
|
|
8001190: 681b ldr r3, [r3, #0]
|
|
|
8001192: f003 0301 and.w r3, r3, #1
|
|
|
8001196: 2b00 cmp r3, #0
|
|
|
8001198: d040 beq.n 800121c <HAL_RCC_ClockConfig+0x120>
|
|
|
{
|
|
|
assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
|
|
|
|
|
|
/* HSE is selected as System Clock Source */
|
|
|
if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
|
|
|
800119a: 687b ldr r3, [r7, #4]
|
|
|
800119c: 685b ldr r3, [r3, #4]
|
|
|
800119e: 2b01 cmp r3, #1
|
|
|
80011a0: d107 bne.n 80011b2 <HAL_RCC_ClockConfig+0xb6>
|
|
|
{
|
|
|
/* Check the HSE ready flag */
|
|
|
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
|
|
|
80011a2: 4b47 ldr r3, [pc, #284] ; (80012c0 <HAL_RCC_ClockConfig+0x1c4>)
|
|
|
80011a4: 681b ldr r3, [r3, #0]
|
|
|
80011a6: f403 3300 and.w r3, r3, #131072 ; 0x20000
|
|
|
80011aa: 2b00 cmp r3, #0
|
|
|
80011ac: d115 bne.n 80011da <HAL_RCC_ClockConfig+0xde>
|
|
|
{
|
|
|
return HAL_ERROR;
|
|
|
80011ae: 2301 movs r3, #1
|
|
|
80011b0: e07f b.n 80012b2 <HAL_RCC_ClockConfig+0x1b6>
|
|
|
}
|
|
|
}
|
|
|
/* PLL is selected as System Clock Source */
|
|
|
else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
|
|
|
80011b2: 687b ldr r3, [r7, #4]
|
|
|
80011b4: 685b ldr r3, [r3, #4]
|
|
|
80011b6: 2b02 cmp r3, #2
|
|
|
80011b8: d107 bne.n 80011ca <HAL_RCC_ClockConfig+0xce>
|
|
|
{
|
|
|
/* Check the PLL ready flag */
|
|
|
if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
|
|
|
80011ba: 4b41 ldr r3, [pc, #260] ; (80012c0 <HAL_RCC_ClockConfig+0x1c4>)
|
|
|
80011bc: 681b ldr r3, [r3, #0]
|
|
|
80011be: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
|
|
|
80011c2: 2b00 cmp r3, #0
|
|
|
80011c4: d109 bne.n 80011da <HAL_RCC_ClockConfig+0xde>
|
|
|
{
|
|
|
return HAL_ERROR;
|
|
|
80011c6: 2301 movs r3, #1
|
|
|
80011c8: e073 b.n 80012b2 <HAL_RCC_ClockConfig+0x1b6>
|
|
|
}
|
|
|
/* HSI is selected as System Clock Source */
|
|
|
else
|
|
|
{
|
|
|
/* Check the HSI ready flag */
|
|
|
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
|
|
|
80011ca: 4b3d ldr r3, [pc, #244] ; (80012c0 <HAL_RCC_ClockConfig+0x1c4>)
|
|
|
80011cc: 681b ldr r3, [r3, #0]
|
|
|
80011ce: f003 0302 and.w r3, r3, #2
|
|
|
80011d2: 2b00 cmp r3, #0
|
|
|
80011d4: d101 bne.n 80011da <HAL_RCC_ClockConfig+0xde>
|
|
|
{
|
|
|
return HAL_ERROR;
|
|
|
80011d6: 2301 movs r3, #1
|
|
|
80011d8: e06b b.n 80012b2 <HAL_RCC_ClockConfig+0x1b6>
|
|
|
}
|
|
|
}
|
|
|
__HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
|
|
|
80011da: 4b39 ldr r3, [pc, #228] ; (80012c0 <HAL_RCC_ClockConfig+0x1c4>)
|
|
|
80011dc: 685b ldr r3, [r3, #4]
|
|
|
80011de: f023 0203 bic.w r2, r3, #3
|
|
|
80011e2: 687b ldr r3, [r7, #4]
|
|
|
80011e4: 685b ldr r3, [r3, #4]
|
|
|
80011e6: 4936 ldr r1, [pc, #216] ; (80012c0 <HAL_RCC_ClockConfig+0x1c4>)
|
|
|
80011e8: 4313 orrs r3, r2
|
|
|
80011ea: 604b str r3, [r1, #4]
|
|
|
|
|
|
/* Get Start Tick */
|
|
|
tickstart = HAL_GetTick();
|
|
|
80011ec: f7ff fa62 bl 80006b4 <HAL_GetTick>
|
|
|
80011f0: 60f8 str r0, [r7, #12]
|
|
|
|
|
|
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
|
|
|
80011f2: e00a b.n 800120a <HAL_RCC_ClockConfig+0x10e>
|
|
|
{
|
|
|
if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
|
|
|
80011f4: f7ff fa5e bl 80006b4 <HAL_GetTick>
|
|
|
80011f8: 4602 mov r2, r0
|
|
|
80011fa: 68fb ldr r3, [r7, #12]
|
|
|
80011fc: 1ad3 subs r3, r2, r3
|
|
|
80011fe: f241 3288 movw r2, #5000 ; 0x1388
|
|
|
8001202: 4293 cmp r3, r2
|
|
|
8001204: d901 bls.n 800120a <HAL_RCC_ClockConfig+0x10e>
|
|
|
{
|
|
|
return HAL_TIMEOUT;
|
|
|
8001206: 2303 movs r3, #3
|
|
|
8001208: e053 b.n 80012b2 <HAL_RCC_ClockConfig+0x1b6>
|
|
|
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
|
|
|
800120a: 4b2d ldr r3, [pc, #180] ; (80012c0 <HAL_RCC_ClockConfig+0x1c4>)
|
|
|
800120c: 685b ldr r3, [r3, #4]
|
|
|
800120e: f003 020c and.w r2, r3, #12
|
|
|
8001212: 687b ldr r3, [r7, #4]
|
|
|
8001214: 685b ldr r3, [r3, #4]
|
|
|
8001216: 009b lsls r3, r3, #2
|
|
|
8001218: 429a cmp r2, r3
|
|
|
800121a: d1eb bne.n 80011f4 <HAL_RCC_ClockConfig+0xf8>
|
|
|
}
|
|
|
}
|
|
|
|
|
|
#if defined(FLASH_ACR_LATENCY)
|
|
|
/* Decreasing the number of wait states because of lower CPU frequency */
|
|
|
if (FLatency < __HAL_FLASH_GET_LATENCY())
|
|
|
800121c: 4b27 ldr r3, [pc, #156] ; (80012bc <HAL_RCC_ClockConfig+0x1c0>)
|
|
|
800121e: 681b ldr r3, [r3, #0]
|
|
|
8001220: f003 0307 and.w r3, r3, #7
|
|
|
8001224: 683a ldr r2, [r7, #0]
|
|
|
8001226: 429a cmp r2, r3
|
|
|
8001228: d210 bcs.n 800124c <HAL_RCC_ClockConfig+0x150>
|
|
|
{
|
|
|
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
|
|
|
__HAL_FLASH_SET_LATENCY(FLatency);
|
|
|
800122a: 4b24 ldr r3, [pc, #144] ; (80012bc <HAL_RCC_ClockConfig+0x1c0>)
|
|
|
800122c: 681b ldr r3, [r3, #0]
|
|
|
800122e: f023 0207 bic.w r2, r3, #7
|
|
|
8001232: 4922 ldr r1, [pc, #136] ; (80012bc <HAL_RCC_ClockConfig+0x1c0>)
|
|
|
8001234: 683b ldr r3, [r7, #0]
|
|
|
8001236: 4313 orrs r3, r2
|
|
|
8001238: 600b str r3, [r1, #0]
|
|
|
|
|
|
/* Check that the new number of wait states is taken into account to access the Flash
|
|
|
memory by reading the FLASH_ACR register */
|
|
|
if (__HAL_FLASH_GET_LATENCY() != FLatency)
|
|
|
800123a: 4b20 ldr r3, [pc, #128] ; (80012bc <HAL_RCC_ClockConfig+0x1c0>)
|
|
|
800123c: 681b ldr r3, [r3, #0]
|
|
|
800123e: f003 0307 and.w r3, r3, #7
|
|
|
8001242: 683a ldr r2, [r7, #0]
|
|
|
8001244: 429a cmp r2, r3
|
|
|
8001246: d001 beq.n 800124c <HAL_RCC_ClockConfig+0x150>
|
|
|
{
|
|
|
return HAL_ERROR;
|
|
|
8001248: 2301 movs r3, #1
|
|
|
800124a: e032 b.n 80012b2 <HAL_RCC_ClockConfig+0x1b6>
|
|
|
}
|
|
|
}
|
|
|
#endif /* FLASH_ACR_LATENCY */
|
|
|
|
|
|
/*-------------------------- PCLK1 Configuration ---------------------------*/
|
|
|
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
|
|
|
800124c: 687b ldr r3, [r7, #4]
|
|
|
800124e: 681b ldr r3, [r3, #0]
|
|
|
8001250: f003 0304 and.w r3, r3, #4
|
|
|
8001254: 2b00 cmp r3, #0
|
|
|
8001256: d008 beq.n 800126a <HAL_RCC_ClockConfig+0x16e>
|
|
|
{
|
|
|
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
|
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
|
|
|
8001258: 4b19 ldr r3, [pc, #100] ; (80012c0 <HAL_RCC_ClockConfig+0x1c4>)
|
|
|
800125a: 685b ldr r3, [r3, #4]
|
|
|
800125c: f423 62e0 bic.w r2, r3, #1792 ; 0x700
|
|
|
8001260: 687b ldr r3, [r7, #4]
|
|
|
8001262: 68db ldr r3, [r3, #12]
|
|
|
8001264: 4916 ldr r1, [pc, #88] ; (80012c0 <HAL_RCC_ClockConfig+0x1c4>)
|
|
|
8001266: 4313 orrs r3, r2
|
|
|
8001268: 604b str r3, [r1, #4]
|
|
|
}
|
|
|
|
|
|
/*-------------------------- PCLK2 Configuration ---------------------------*/
|
|
|
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
|
|
|
800126a: 687b ldr r3, [r7, #4]
|
|
|
800126c: 681b ldr r3, [r3, #0]
|
|
|
800126e: f003 0308 and.w r3, r3, #8
|
|
|
8001272: 2b00 cmp r3, #0
|
|
|
8001274: d009 beq.n 800128a <HAL_RCC_ClockConfig+0x18e>
|
|
|
{
|
|
|
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
|
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3));
|
|
|
8001276: 4b12 ldr r3, [pc, #72] ; (80012c0 <HAL_RCC_ClockConfig+0x1c4>)
|
|
|
8001278: 685b ldr r3, [r3, #4]
|
|
|
800127a: f423 5260 bic.w r2, r3, #14336 ; 0x3800
|
|
|
800127e: 687b ldr r3, [r7, #4]
|
|
|
8001280: 691b ldr r3, [r3, #16]
|
|
|
8001282: 00db lsls r3, r3, #3
|
|
|
8001284: 490e ldr r1, [pc, #56] ; (80012c0 <HAL_RCC_ClockConfig+0x1c4>)
|
|
|
8001286: 4313 orrs r3, r2
|
|
|
8001288: 604b str r3, [r1, #4]
|
|
|
}
|
|
|
|
|
|
/* Update the SystemCoreClock global variable */
|
|
|
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos];
|
|
|
800128a: f000 f821 bl 80012d0 <HAL_RCC_GetSysClockFreq>
|
|
|
800128e: 4602 mov r2, r0
|
|
|
8001290: 4b0b ldr r3, [pc, #44] ; (80012c0 <HAL_RCC_ClockConfig+0x1c4>)
|
|
|
8001292: 685b ldr r3, [r3, #4]
|
|
|
8001294: 091b lsrs r3, r3, #4
|
|
|
8001296: f003 030f and.w r3, r3, #15
|
|
|
800129a: 490a ldr r1, [pc, #40] ; (80012c4 <HAL_RCC_ClockConfig+0x1c8>)
|
|
|
800129c: 5ccb ldrb r3, [r1, r3]
|
|
|
800129e: fa22 f303 lsr.w r3, r2, r3
|
|
|
80012a2: 4a09 ldr r2, [pc, #36] ; (80012c8 <HAL_RCC_ClockConfig+0x1cc>)
|
|
|
80012a4: 6013 str r3, [r2, #0]
|
|
|
|
|
|
/* Configure the source of time base considering new system clocks settings*/
|
|
|
HAL_InitTick(uwTickPrio);
|
|
|
80012a6: 4b09 ldr r3, [pc, #36] ; (80012cc <HAL_RCC_ClockConfig+0x1d0>)
|
|
|
80012a8: 681b ldr r3, [r3, #0]
|
|
|
80012aa: 4618 mov r0, r3
|
|
|
80012ac: f7ff f9c0 bl 8000630 <HAL_InitTick>
|
|
|
|
|
|
return HAL_OK;
|
|
|
80012b0: 2300 movs r3, #0
|
|
|
}
|
|
|
80012b2: 4618 mov r0, r3
|
|
|
80012b4: 3710 adds r7, #16
|
|
|
80012b6: 46bd mov sp, r7
|
|
|
80012b8: bd80 pop {r7, pc}
|
|
|
80012ba: bf00 nop
|
|
|
80012bc: 40022000 .word 0x40022000
|
|
|
80012c0: 40021000 .word 0x40021000
|
|
|
80012c4: 08002c10 .word 0x08002c10
|
|
|
80012c8: 20000000 .word 0x20000000
|
|
|
80012cc: 20000004 .word 0x20000004
|
|
|
|
|
|
080012d0 <HAL_RCC_GetSysClockFreq>:
|
|
|
* right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
|
|
|
*
|
|
|
* @retval SYSCLK frequency
|
|
|
*/
|
|
|
uint32_t HAL_RCC_GetSysClockFreq(void)
|
|
|
{
|
|
|
80012d0: b490 push {r4, r7}
|
|
|
80012d2: b08a sub sp, #40 ; 0x28
|
|
|
80012d4: af00 add r7, sp, #0
|
|
|
#if defined(RCC_CFGR2_PREDIV1SRC)
|
|
|
const uint8_t aPLLMULFactorTable[14] = {0, 0, 4, 5, 6, 7, 8, 9, 0, 0, 0, 0, 0, 13};
|
|
|
const uint8_t aPredivFactorTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16};
|
|
|
#else
|
|
|
const uint8_t aPLLMULFactorTable[16] = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16};
|
|
|
80012d6: 4b29 ldr r3, [pc, #164] ; (800137c <HAL_RCC_GetSysClockFreq+0xac>)
|
|
|
80012d8: 1d3c adds r4, r7, #4
|
|
|
80012da: cb0f ldmia r3, {r0, r1, r2, r3}
|
|
|
80012dc: e884 000f stmia.w r4, {r0, r1, r2, r3}
|
|
|
#if defined(RCC_CFGR2_PREDIV1)
|
|
|
const uint8_t aPredivFactorTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16};
|
|
|
#else
|
|
|
const uint8_t aPredivFactorTable[2] = {1, 2};
|
|
|
80012e0: f240 2301 movw r3, #513 ; 0x201
|
|
|
80012e4: 803b strh r3, [r7, #0]
|
|
|
#endif /*RCC_CFGR2_PREDIV1*/
|
|
|
|
|
|
#endif
|
|
|
uint32_t tmpreg = 0U, prediv = 0U, pllclk = 0U, pllmul = 0U;
|
|
|
80012e6: 2300 movs r3, #0
|
|
|
80012e8: 61fb str r3, [r7, #28]
|
|
|
80012ea: 2300 movs r3, #0
|
|
|
80012ec: 61bb str r3, [r7, #24]
|
|
|
80012ee: 2300 movs r3, #0
|
|
|
80012f0: 627b str r3, [r7, #36] ; 0x24
|
|
|
80012f2: 2300 movs r3, #0
|
|
|
80012f4: 617b str r3, [r7, #20]
|
|
|
uint32_t sysclockfreq = 0U;
|
|
|
80012f6: 2300 movs r3, #0
|
|
|
80012f8: 623b str r3, [r7, #32]
|
|
|
#if defined(RCC_CFGR2_PREDIV1SRC)
|
|
|
uint32_t prediv2 = 0U, pll2mul = 0U;
|
|
|
#endif /*RCC_CFGR2_PREDIV1SRC*/
|
|
|
|
|
|
tmpreg = RCC->CFGR;
|
|
|
80012fa: 4b21 ldr r3, [pc, #132] ; (8001380 <HAL_RCC_GetSysClockFreq+0xb0>)
|
|
|
80012fc: 685b ldr r3, [r3, #4]
|
|
|
80012fe: 61fb str r3, [r7, #28]
|
|
|
|
|
|
/* Get SYSCLK source -------------------------------------------------------*/
|
|
|
switch (tmpreg & RCC_CFGR_SWS)
|
|
|
8001300: 69fb ldr r3, [r7, #28]
|
|
|
8001302: f003 030c and.w r3, r3, #12
|
|
|
8001306: 2b04 cmp r3, #4
|
|
|
8001308: d002 beq.n 8001310 <HAL_RCC_GetSysClockFreq+0x40>
|
|
|
800130a: 2b08 cmp r3, #8
|
|
|
800130c: d003 beq.n 8001316 <HAL_RCC_GetSysClockFreq+0x46>
|
|
|
800130e: e02b b.n 8001368 <HAL_RCC_GetSysClockFreq+0x98>
|
|
|
{
|
|
|
case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */
|
|
|
{
|
|
|
sysclockfreq = HSE_VALUE;
|
|
|
8001310: 4b1c ldr r3, [pc, #112] ; (8001384 <HAL_RCC_GetSysClockFreq+0xb4>)
|
|
|
8001312: 623b str r3, [r7, #32]
|
|
|
break;
|
|
|
8001314: e02b b.n 800136e <HAL_RCC_GetSysClockFreq+0x9e>
|
|
|
}
|
|
|
case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */
|
|
|
{
|
|
|
pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos];
|
|
|
8001316: 69fb ldr r3, [r7, #28]
|
|
|
8001318: 0c9b lsrs r3, r3, #18
|
|
|
800131a: f003 030f and.w r3, r3, #15
|
|
|
800131e: 3328 adds r3, #40 ; 0x28
|
|
|
8001320: 443b add r3, r7
|
|
|
8001322: f813 3c24 ldrb.w r3, [r3, #-36]
|
|
|
8001326: 617b str r3, [r7, #20]
|
|
|
if ((tmpreg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2)
|
|
|
8001328: 69fb ldr r3, [r7, #28]
|
|
|
800132a: f403 3380 and.w r3, r3, #65536 ; 0x10000
|
|
|
800132e: 2b00 cmp r3, #0
|
|
|
8001330: d012 beq.n 8001358 <HAL_RCC_GetSysClockFreq+0x88>
|
|
|
{
|
|
|
#if defined(RCC_CFGR2_PREDIV1)
|
|
|
prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> RCC_CFGR2_PREDIV1_Pos];
|
|
|
#else
|
|
|
prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos];
|
|
|
8001332: 4b13 ldr r3, [pc, #76] ; (8001380 <HAL_RCC_GetSysClockFreq+0xb0>)
|
|
|
8001334: 685b ldr r3, [r3, #4]
|
|
|
8001336: 0c5b lsrs r3, r3, #17
|
|
|
8001338: f003 0301 and.w r3, r3, #1
|
|
|
800133c: 3328 adds r3, #40 ; 0x28
|
|
|
800133e: 443b add r3, r7
|
|
|
8001340: f813 3c28 ldrb.w r3, [r3, #-40]
|
|
|
8001344: 61bb str r3, [r7, #24]
|
|
|
{
|
|
|
pllclk = pllclk / 2;
|
|
|
}
|
|
|
#else
|
|
|
/* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */
|
|
|
pllclk = (uint32_t)((HSE_VALUE * pllmul) / prediv);
|
|
|
8001346: 697b ldr r3, [r7, #20]
|
|
|
8001348: 4a0e ldr r2, [pc, #56] ; (8001384 <HAL_RCC_GetSysClockFreq+0xb4>)
|
|
|
800134a: fb03 f202 mul.w r2, r3, r2
|
|
|
800134e: 69bb ldr r3, [r7, #24]
|
|
|
8001350: fbb2 f3f3 udiv r3, r2, r3
|
|
|
8001354: 627b str r3, [r7, #36] ; 0x24
|
|
|
8001356: e004 b.n 8001362 <HAL_RCC_GetSysClockFreq+0x92>
|
|
|
#endif /*RCC_CFGR2_PREDIV1SRC*/
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
/* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */
|
|
|
pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul);
|
|
|
8001358: 697b ldr r3, [r7, #20]
|
|
|
800135a: 4a0b ldr r2, [pc, #44] ; (8001388 <HAL_RCC_GetSysClockFreq+0xb8>)
|
|
|
800135c: fb02 f303 mul.w r3, r2, r3
|
|
|
8001360: 627b str r3, [r7, #36] ; 0x24
|
|
|
}
|
|
|
sysclockfreq = pllclk;
|
|
|
8001362: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
|
8001364: 623b str r3, [r7, #32]
|
|
|
break;
|
|
|
8001366: e002 b.n 800136e <HAL_RCC_GetSysClockFreq+0x9e>
|
|
|
}
|
|
|
case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
|
|
|
default: /* HSI used as system clock */
|
|
|
{
|
|
|
sysclockfreq = HSI_VALUE;
|
|
|
8001368: 4b06 ldr r3, [pc, #24] ; (8001384 <HAL_RCC_GetSysClockFreq+0xb4>)
|
|
|
800136a: 623b str r3, [r7, #32]
|
|
|
break;
|
|
|
800136c: bf00 nop
|
|
|
}
|
|
|
}
|
|
|
return sysclockfreq;
|
|
|
800136e: 6a3b ldr r3, [r7, #32]
|
|
|
}
|
|
|
8001370: 4618 mov r0, r3
|
|
|
8001372: 3728 adds r7, #40 ; 0x28
|
|
|
8001374: 46bd mov sp, r7
|
|
|
8001376: bc90 pop {r4, r7}
|
|
|
8001378: 4770 bx lr
|
|
|
800137a: bf00 nop
|
|
|
800137c: 08002bf0 .word 0x08002bf0
|
|
|
8001380: 40021000 .word 0x40021000
|
|
|
8001384: 007a1200 .word 0x007a1200
|
|
|
8001388: 003d0900 .word 0x003d0900
|
|
|
|
|
|
0800138c <HAL_RCC_GetHCLKFreq>:
|
|
|
* @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
|
|
|
* and updated within this function
|
|
|
* @retval HCLK frequency
|
|
|
*/
|
|
|
uint32_t HAL_RCC_GetHCLKFreq(void)
|
|
|
{
|
|
|
800138c: b480 push {r7}
|
|
|
800138e: af00 add r7, sp, #0
|
|
|
return SystemCoreClock;
|
|
|
8001390: 4b02 ldr r3, [pc, #8] ; (800139c <HAL_RCC_GetHCLKFreq+0x10>)
|
|
|
8001392: 681b ldr r3, [r3, #0]
|
|
|
}
|
|
|
8001394: 4618 mov r0, r3
|
|
|
8001396: 46bd mov sp, r7
|
|
|
8001398: bc80 pop {r7}
|
|
|
800139a: 4770 bx lr
|
|
|
800139c: 20000000 .word 0x20000000
|
|
|
|
|
|
080013a0 <HAL_RCC_GetPCLK1Freq>:
|
|
|
* @note Each time PCLK1 changes, this function must be called to update the
|
|
|
* right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
|
|
|
* @retval PCLK1 frequency
|
|
|
*/
|
|
|
uint32_t HAL_RCC_GetPCLK1Freq(void)
|
|
|
{
|
|
|
80013a0: b580 push {r7, lr}
|
|
|
80013a2: af00 add r7, sp, #0
|
|
|
/* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
|
|
|
return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]);
|
|
|
80013a4: f7ff fff2 bl 800138c <HAL_RCC_GetHCLKFreq>
|
|
|
80013a8: 4602 mov r2, r0
|
|
|
80013aa: 4b05 ldr r3, [pc, #20] ; (80013c0 <HAL_RCC_GetPCLK1Freq+0x20>)
|
|
|
80013ac: 685b ldr r3, [r3, #4]
|
|
|
80013ae: 0a1b lsrs r3, r3, #8
|
|
|
80013b0: f003 0307 and.w r3, r3, #7
|
|
|
80013b4: 4903 ldr r1, [pc, #12] ; (80013c4 <HAL_RCC_GetPCLK1Freq+0x24>)
|
|
|
80013b6: 5ccb ldrb r3, [r1, r3]
|
|
|
80013b8: fa22 f303 lsr.w r3, r2, r3
|
|
|
}
|
|
|
80013bc: 4618 mov r0, r3
|
|
|
80013be: bd80 pop {r7, pc}
|
|
|
80013c0: 40021000 .word 0x40021000
|
|
|
80013c4: 08002c20 .word 0x08002c20
|
|
|
|
|
|
080013c8 <HAL_RCC_GetPCLK2Freq>:
|
|
|
* @note Each time PCLK2 changes, this function must be called to update the
|
|
|
* right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
|
|
|
* @retval PCLK2 frequency
|
|
|
*/
|
|
|
uint32_t HAL_RCC_GetPCLK2Freq(void)
|
|
|
{
|
|
|
80013c8: b580 push {r7, lr}
|
|
|
80013ca: af00 add r7, sp, #0
|
|
|
/* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
|
|
|
return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]);
|
|
|
80013cc: f7ff ffde bl 800138c <HAL_RCC_GetHCLKFreq>
|
|
|
80013d0: 4602 mov r2, r0
|
|
|
80013d2: 4b05 ldr r3, [pc, #20] ; (80013e8 <HAL_RCC_GetPCLK2Freq+0x20>)
|
|
|
80013d4: 685b ldr r3, [r3, #4]
|
|
|
80013d6: 0adb lsrs r3, r3, #11
|
|
|
80013d8: f003 0307 and.w r3, r3, #7
|
|
|
80013dc: 4903 ldr r1, [pc, #12] ; (80013ec <HAL_RCC_GetPCLK2Freq+0x24>)
|
|
|
80013de: 5ccb ldrb r3, [r1, r3]
|
|
|
80013e0: fa22 f303 lsr.w r3, r2, r3
|
|
|
}
|
|
|
80013e4: 4618 mov r0, r3
|
|
|
80013e6: bd80 pop {r7, pc}
|
|
|
80013e8: 40021000 .word 0x40021000
|
|
|
80013ec: 08002c20 .word 0x08002c20
|
|
|
|
|
|
080013f0 <RCC_Delay>:
|
|
|
* @brief This function provides delay (in milliseconds) based on CPU cycles method.
|
|
|
* @param mdelay: specifies the delay time length, in milliseconds.
|
|
|
* @retval None
|
|
|
*/
|
|
|
static void RCC_Delay(uint32_t mdelay)
|
|
|
{
|
|
|
80013f0: b480 push {r7}
|
|
|
80013f2: b085 sub sp, #20
|
|
|
80013f4: af00 add r7, sp, #0
|
|
|
80013f6: 6078 str r0, [r7, #4]
|
|
|
__IO uint32_t Delay = mdelay * (SystemCoreClock / 8U / 1000U);
|
|
|
80013f8: 4b0a ldr r3, [pc, #40] ; (8001424 <RCC_Delay+0x34>)
|
|
|
80013fa: 681b ldr r3, [r3, #0]
|
|
|
80013fc: 4a0a ldr r2, [pc, #40] ; (8001428 <RCC_Delay+0x38>)
|
|
|
80013fe: fba2 2303 umull r2, r3, r2, r3
|
|
|
8001402: 0a5b lsrs r3, r3, #9
|
|
|
8001404: 687a ldr r2, [r7, #4]
|
|
|
8001406: fb02 f303 mul.w r3, r2, r3
|
|
|
800140a: 60fb str r3, [r7, #12]
|
|
|
do
|
|
|
{
|
|
|
__NOP();
|
|
|
800140c: bf00 nop
|
|
|
}
|
|
|
while (Delay --);
|
|
|
800140e: 68fb ldr r3, [r7, #12]
|
|
|
8001410: 1e5a subs r2, r3, #1
|
|
|
8001412: 60fa str r2, [r7, #12]
|
|
|
8001414: 2b00 cmp r3, #0
|
|
|
8001416: d1f9 bne.n 800140c <RCC_Delay+0x1c>
|
|
|
}
|
|
|
8001418: bf00 nop
|
|
|
800141a: bf00 nop
|
|
|
800141c: 3714 adds r7, #20
|
|
|
800141e: 46bd mov sp, r7
|
|
|
8001420: bc80 pop {r7}
|
|
|
8001422: 4770 bx lr
|
|
|
8001424: 20000000 .word 0x20000000
|
|
|
8001428: 10624dd3 .word 0x10624dd3
|
|
|
|
|
|
0800142c <HAL_RCCEx_PeriphCLKConfig>:
|
|
|
* manually disable it.
|
|
|
*
|
|
|
* @retval HAL status
|
|
|
*/
|
|
|
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
|
|
|
{
|
|
|
800142c: b580 push {r7, lr}
|
|
|
800142e: b086 sub sp, #24
|
|
|
8001430: af00 add r7, sp, #0
|
|
|
8001432: 6078 str r0, [r7, #4]
|
|
|
uint32_t tickstart = 0U, temp_reg = 0U;
|
|
|
8001434: 2300 movs r3, #0
|
|
|
8001436: 613b str r3, [r7, #16]
|
|
|
8001438: 2300 movs r3, #0
|
|
|
800143a: 60fb str r3, [r7, #12]
|
|
|
|
|
|
/* Check the parameters */
|
|
|
assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
|
|
|
|
|
|
/*------------------------------- RTC/LCD Configuration ------------------------*/
|
|
|
if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
|
|
|
800143c: 687b ldr r3, [r7, #4]
|
|
|
800143e: 681b ldr r3, [r3, #0]
|
|
|
8001440: f003 0301 and.w r3, r3, #1
|
|
|
8001444: 2b00 cmp r3, #0
|
|
|
8001446: d07d beq.n 8001544 <HAL_RCCEx_PeriphCLKConfig+0x118>
|
|
|
{
|
|
|
FlagStatus pwrclkchanged = RESET;
|
|
|
8001448: 2300 movs r3, #0
|
|
|
800144a: 75fb strb r3, [r7, #23]
|
|
|
assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
|
|
|
|
|
|
/* As soon as function is called to change RTC clock source, activation of the
|
|
|
power domain is done. */
|
|
|
/* Requires to enable write access to Backup Domain of necessary */
|
|
|
if (__HAL_RCC_PWR_IS_CLK_DISABLED())
|
|
|
800144c: 4b4f ldr r3, [pc, #316] ; (800158c <HAL_RCCEx_PeriphCLKConfig+0x160>)
|
|
|
800144e: 69db ldr r3, [r3, #28]
|
|
|
8001450: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
|
|
|
8001454: 2b00 cmp r3, #0
|
|
|
8001456: d10d bne.n 8001474 <HAL_RCCEx_PeriphCLKConfig+0x48>
|
|
|
{
|
|
|
__HAL_RCC_PWR_CLK_ENABLE();
|
|
|
8001458: 4b4c ldr r3, [pc, #304] ; (800158c <HAL_RCCEx_PeriphCLKConfig+0x160>)
|
|
|
800145a: 69db ldr r3, [r3, #28]
|
|
|
800145c: 4a4b ldr r2, [pc, #300] ; (800158c <HAL_RCCEx_PeriphCLKConfig+0x160>)
|
|
|
800145e: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
|
|
|
8001462: 61d3 str r3, [r2, #28]
|
|
|
8001464: 4b49 ldr r3, [pc, #292] ; (800158c <HAL_RCCEx_PeriphCLKConfig+0x160>)
|
|
|
8001466: 69db ldr r3, [r3, #28]
|
|
|
8001468: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
|
|
|
800146c: 60bb str r3, [r7, #8]
|
|
|
800146e: 68bb ldr r3, [r7, #8]
|
|
|
pwrclkchanged = SET;
|
|
|
8001470: 2301 movs r3, #1
|
|
|
8001472: 75fb strb r3, [r7, #23]
|
|
|
}
|
|
|
|
|
|
if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
|
|
|
8001474: 4b46 ldr r3, [pc, #280] ; (8001590 <HAL_RCCEx_PeriphCLKConfig+0x164>)
|
|
|
8001476: 681b ldr r3, [r3, #0]
|
|
|
8001478: f403 7380 and.w r3, r3, #256 ; 0x100
|
|
|
800147c: 2b00 cmp r3, #0
|
|
|
800147e: d118 bne.n 80014b2 <HAL_RCCEx_PeriphCLKConfig+0x86>
|
|
|
{
|
|
|
/* Enable write access to Backup domain */
|
|
|
SET_BIT(PWR->CR, PWR_CR_DBP);
|
|
|
8001480: 4b43 ldr r3, [pc, #268] ; (8001590 <HAL_RCCEx_PeriphCLKConfig+0x164>)
|
|
|
8001482: 681b ldr r3, [r3, #0]
|
|
|
8001484: 4a42 ldr r2, [pc, #264] ; (8001590 <HAL_RCCEx_PeriphCLKConfig+0x164>)
|
|
|
8001486: f443 7380 orr.w r3, r3, #256 ; 0x100
|
|
|
800148a: 6013 str r3, [r2, #0]
|
|
|
|
|
|
/* Wait for Backup domain Write protection disable */
|
|
|
tickstart = HAL_GetTick();
|
|
|
800148c: f7ff f912 bl 80006b4 <HAL_GetTick>
|
|
|
8001490: 6138 str r0, [r7, #16]
|
|
|
|
|
|
while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
|
|
|
8001492: e008 b.n 80014a6 <HAL_RCCEx_PeriphCLKConfig+0x7a>
|
|
|
{
|
|
|
if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
|
|
|
8001494: f7ff f90e bl 80006b4 <HAL_GetTick>
|
|
|
8001498: 4602 mov r2, r0
|
|
|
800149a: 693b ldr r3, [r7, #16]
|
|
|
800149c: 1ad3 subs r3, r2, r3
|
|
|
800149e: 2b64 cmp r3, #100 ; 0x64
|
|
|
80014a0: d901 bls.n 80014a6 <HAL_RCCEx_PeriphCLKConfig+0x7a>
|
|
|
{
|
|
|
return HAL_TIMEOUT;
|
|
|
80014a2: 2303 movs r3, #3
|
|
|
80014a4: e06d b.n 8001582 <HAL_RCCEx_PeriphCLKConfig+0x156>
|
|
|
while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
|
|
|
80014a6: 4b3a ldr r3, [pc, #232] ; (8001590 <HAL_RCCEx_PeriphCLKConfig+0x164>)
|
|
|
80014a8: 681b ldr r3, [r3, #0]
|
|
|
80014aa: f403 7380 and.w r3, r3, #256 ; 0x100
|
|
|
80014ae: 2b00 cmp r3, #0
|
|
|
80014b0: d0f0 beq.n 8001494 <HAL_RCCEx_PeriphCLKConfig+0x68>
|
|
|
}
|
|
|
}
|
|
|
}
|
|
|
|
|
|
/* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */
|
|
|
temp_reg = (RCC->BDCR & RCC_BDCR_RTCSEL);
|
|
|
80014b2: 4b36 ldr r3, [pc, #216] ; (800158c <HAL_RCCEx_PeriphCLKConfig+0x160>)
|
|
|
80014b4: 6a1b ldr r3, [r3, #32]
|
|
|
80014b6: f403 7340 and.w r3, r3, #768 ; 0x300
|
|
|
80014ba: 60fb str r3, [r7, #12]
|
|
|
if ((temp_reg != 0x00000000U) && (temp_reg != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
|
|
|
80014bc: 68fb ldr r3, [r7, #12]
|
|
|
80014be: 2b00 cmp r3, #0
|
|
|
80014c0: d02e beq.n 8001520 <HAL_RCCEx_PeriphCLKConfig+0xf4>
|
|
|
80014c2: 687b ldr r3, [r7, #4]
|
|
|
80014c4: 685b ldr r3, [r3, #4]
|
|
|
80014c6: f403 7340 and.w r3, r3, #768 ; 0x300
|
|
|
80014ca: 68fa ldr r2, [r7, #12]
|
|
|
80014cc: 429a cmp r2, r3
|
|
|
80014ce: d027 beq.n 8001520 <HAL_RCCEx_PeriphCLKConfig+0xf4>
|
|
|
{
|
|
|
/* Store the content of BDCR register before the reset of Backup Domain */
|
|
|
temp_reg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
|
|
|
80014d0: 4b2e ldr r3, [pc, #184] ; (800158c <HAL_RCCEx_PeriphCLKConfig+0x160>)
|
|
|
80014d2: 6a1b ldr r3, [r3, #32]
|
|
|
80014d4: f423 7340 bic.w r3, r3, #768 ; 0x300
|
|
|
80014d8: 60fb str r3, [r7, #12]
|
|
|
/* RTC Clock selection can be changed only if the Backup Domain is reset */
|
|
|
__HAL_RCC_BACKUPRESET_FORCE();
|
|
|
80014da: 4b2e ldr r3, [pc, #184] ; (8001594 <HAL_RCCEx_PeriphCLKConfig+0x168>)
|
|
|
80014dc: 2201 movs r2, #1
|
|
|
80014de: 601a str r2, [r3, #0]
|
|
|
__HAL_RCC_BACKUPRESET_RELEASE();
|
|
|
80014e0: 4b2c ldr r3, [pc, #176] ; (8001594 <HAL_RCCEx_PeriphCLKConfig+0x168>)
|
|
|
80014e2: 2200 movs r2, #0
|
|
|
80014e4: 601a str r2, [r3, #0]
|
|
|
/* Restore the Content of BDCR register */
|
|
|
RCC->BDCR = temp_reg;
|
|
|
80014e6: 4a29 ldr r2, [pc, #164] ; (800158c <HAL_RCCEx_PeriphCLKConfig+0x160>)
|
|
|
80014e8: 68fb ldr r3, [r7, #12]
|
|
|
80014ea: 6213 str r3, [r2, #32]
|
|
|
|
|
|
/* Wait for LSERDY if LSE was enabled */
|
|
|
if (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSEON))
|
|
|
80014ec: 68fb ldr r3, [r7, #12]
|
|
|
80014ee: f003 0301 and.w r3, r3, #1
|
|
|
80014f2: 2b00 cmp r3, #0
|
|
|
80014f4: d014 beq.n 8001520 <HAL_RCCEx_PeriphCLKConfig+0xf4>
|
|
|
{
|
|
|
/* Get Start Tick */
|
|
|
tickstart = HAL_GetTick();
|
|
|
80014f6: f7ff f8dd bl 80006b4 <HAL_GetTick>
|
|
|
80014fa: 6138 str r0, [r7, #16]
|
|
|
|
|
|
/* Wait till LSE is ready */
|
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
|
|
|
80014fc: e00a b.n 8001514 <HAL_RCCEx_PeriphCLKConfig+0xe8>
|
|
|
{
|
|
|
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
|
|
|
80014fe: f7ff f8d9 bl 80006b4 <HAL_GetTick>
|
|
|
8001502: 4602 mov r2, r0
|
|
|
8001504: 693b ldr r3, [r7, #16]
|
|
|
8001506: 1ad3 subs r3, r2, r3
|
|
|
8001508: f241 3288 movw r2, #5000 ; 0x1388
|
|
|
800150c: 4293 cmp r3, r2
|
|
|
800150e: d901 bls.n 8001514 <HAL_RCCEx_PeriphCLKConfig+0xe8>
|
|
|
{
|
|
|
return HAL_TIMEOUT;
|
|
|
8001510: 2303 movs r3, #3
|
|
|
8001512: e036 b.n 8001582 <HAL_RCCEx_PeriphCLKConfig+0x156>
|
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
|
|
|
8001514: 4b1d ldr r3, [pc, #116] ; (800158c <HAL_RCCEx_PeriphCLKConfig+0x160>)
|
|
|
8001516: 6a1b ldr r3, [r3, #32]
|
|
|
8001518: f003 0302 and.w r3, r3, #2
|
|
|
800151c: 2b00 cmp r3, #0
|
|
|
800151e: d0ee beq.n 80014fe <HAL_RCCEx_PeriphCLKConfig+0xd2>
|
|
|
}
|
|
|
}
|
|
|
}
|
|
|
}
|
|
|
__HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
|
|
|
8001520: 4b1a ldr r3, [pc, #104] ; (800158c <HAL_RCCEx_PeriphCLKConfig+0x160>)
|
|
|
8001522: 6a1b ldr r3, [r3, #32]
|
|
|
8001524: f423 7240 bic.w r2, r3, #768 ; 0x300
|
|
|
8001528: 687b ldr r3, [r7, #4]
|
|
|
800152a: 685b ldr r3, [r3, #4]
|
|
|
800152c: 4917 ldr r1, [pc, #92] ; (800158c <HAL_RCCEx_PeriphCLKConfig+0x160>)
|
|
|
800152e: 4313 orrs r3, r2
|
|
|
8001530: 620b str r3, [r1, #32]
|
|
|
|
|
|
/* Require to disable power clock if necessary */
|
|
|
if (pwrclkchanged == SET)
|
|
|
8001532: 7dfb ldrb r3, [r7, #23]
|
|
|
8001534: 2b01 cmp r3, #1
|
|
|
8001536: d105 bne.n 8001544 <HAL_RCCEx_PeriphCLKConfig+0x118>
|
|
|
{
|
|
|
__HAL_RCC_PWR_CLK_DISABLE();
|
|
|
8001538: 4b14 ldr r3, [pc, #80] ; (800158c <HAL_RCCEx_PeriphCLKConfig+0x160>)
|
|
|
800153a: 69db ldr r3, [r3, #28]
|
|
|
800153c: 4a13 ldr r2, [pc, #76] ; (800158c <HAL_RCCEx_PeriphCLKConfig+0x160>)
|
|
|
800153e: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000
|
|
|
8001542: 61d3 str r3, [r2, #28]
|
|
|
}
|
|
|
}
|
|
|
|
|
|
/*------------------------------ ADC clock Configuration ------------------*/
|
|
|
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC)
|
|
|
8001544: 687b ldr r3, [r7, #4]
|
|
|
8001546: 681b ldr r3, [r3, #0]
|
|
|
8001548: f003 0302 and.w r3, r3, #2
|
|
|
800154c: 2b00 cmp r3, #0
|
|
|
800154e: d008 beq.n 8001562 <HAL_RCCEx_PeriphCLKConfig+0x136>
|
|
|
{
|
|
|
/* Check the parameters */
|
|
|
assert_param(IS_RCC_ADCPLLCLK_DIV(PeriphClkInit->AdcClockSelection));
|
|
|
|
|
|
/* Configure the ADC clock source */
|
|
|
__HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection);
|
|
|
8001550: 4b0e ldr r3, [pc, #56] ; (800158c <HAL_RCCEx_PeriphCLKConfig+0x160>)
|
|
|
8001552: 685b ldr r3, [r3, #4]
|
|
|
8001554: f423 4240 bic.w r2, r3, #49152 ; 0xc000
|
|
|
8001558: 687b ldr r3, [r7, #4]
|
|
|
800155a: 689b ldr r3, [r3, #8]
|
|
|
800155c: 490b ldr r1, [pc, #44] ; (800158c <HAL_RCCEx_PeriphCLKConfig+0x160>)
|
|
|
800155e: 4313 orrs r3, r2
|
|
|
8001560: 604b str r3, [r1, #4]
|
|
|
|
|
|
#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
|
|
|
|| defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\
|
|
|
|| defined(STM32F105xC) || defined(STM32F107xC)
|
|
|
/*------------------------------ USB clock Configuration ------------------*/
|
|
|
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB)
|
|
|
8001562: 687b ldr r3, [r7, #4]
|
|
|
8001564: 681b ldr r3, [r3, #0]
|
|
|
8001566: f003 0310 and.w r3, r3, #16
|
|
|
800156a: 2b00 cmp r3, #0
|
|
|
800156c: d008 beq.n 8001580 <HAL_RCCEx_PeriphCLKConfig+0x154>
|
|
|
{
|
|
|
/* Check the parameters */
|
|
|
assert_param(IS_RCC_USBPLLCLK_DIV(PeriphClkInit->UsbClockSelection));
|
|
|
|
|
|
/* Configure the USB clock source */
|
|
|
__HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection);
|
|
|
800156e: 4b07 ldr r3, [pc, #28] ; (800158c <HAL_RCCEx_PeriphCLKConfig+0x160>)
|
|
|
8001570: 685b ldr r3, [r3, #4]
|
|
|
8001572: f423 0280 bic.w r2, r3, #4194304 ; 0x400000
|
|
|
8001576: 687b ldr r3, [r7, #4]
|
|
|
8001578: 68db ldr r3, [r3, #12]
|
|
|
800157a: 4904 ldr r1, [pc, #16] ; (800158c <HAL_RCCEx_PeriphCLKConfig+0x160>)
|
|
|
800157c: 4313 orrs r3, r2
|
|
|
800157e: 604b str r3, [r1, #4]
|
|
|
}
|
|
|
#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
|
|
|
|
|
|
return HAL_OK;
|
|
|
8001580: 2300 movs r3, #0
|
|
|
}
|
|
|
8001582: 4618 mov r0, r3
|
|
|
8001584: 3718 adds r7, #24
|
|
|
8001586: 46bd mov sp, r7
|
|
|
8001588: bd80 pop {r7, pc}
|
|
|
800158a: bf00 nop
|
|
|
800158c: 40021000 .word 0x40021000
|
|
|
8001590: 40007000 .word 0x40007000
|
|
|
8001594: 42420440 .word 0x42420440
|
|
|
|
|
|
08001598 <HAL_RCCEx_GetPeriphCLKFreq>:
|
|
|
* @arg @ref RCC_PERIPHCLK_USB USB peripheral clock
|
|
|
@endif
|
|
|
* @retval Frequency in Hz (0: means that no available frequency for the peripheral)
|
|
|
*/
|
|
|
uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
|
|
|
{
|
|
|
8001598: b590 push {r4, r7, lr}
|
|
|
800159a: b08d sub sp, #52 ; 0x34
|
|
|
800159c: af00 add r7, sp, #0
|
|
|
800159e: 6078 str r0, [r7, #4]
|
|
|
uint32_t prediv1 = 0U, pllclk = 0U, pllmul = 0U;
|
|
|
uint32_t pll2mul = 0U, pll3mul = 0U, prediv2 = 0U;
|
|
|
#endif /* STM32F105xC || STM32F107xC */
|
|
|
#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) || \
|
|
|
defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)
|
|
|
const uint8_t aPLLMULFactorTable[16] = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16};
|
|
|
80015a0: 4b58 ldr r3, [pc, #352] ; (8001704 <HAL_RCCEx_GetPeriphCLKFreq+0x16c>)
|
|
|
80015a2: f107 040c add.w r4, r7, #12
|
|
|
80015a6: cb0f ldmia r3, {r0, r1, r2, r3}
|
|
|
80015a8: e884 000f stmia.w r4, {r0, r1, r2, r3}
|
|
|
const uint8_t aPredivFactorTable[2] = {1, 2};
|
|
|
80015ac: f240 2301 movw r3, #513 ; 0x201
|
|
|
80015b0: 813b strh r3, [r7, #8]
|
|
|
|
|
|
uint32_t prediv1 = 0U, pllclk = 0U, pllmul = 0U;
|
|
|
80015b2: 2300 movs r3, #0
|
|
|
80015b4: 627b str r3, [r7, #36] ; 0x24
|
|
|
80015b6: 2300 movs r3, #0
|
|
|
80015b8: 62fb str r3, [r7, #44] ; 0x2c
|
|
|
80015ba: 2300 movs r3, #0
|
|
|
80015bc: 623b str r3, [r7, #32]
|
|
|
#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */
|
|
|
uint32_t temp_reg = 0U, frequency = 0U;
|
|
|
80015be: 2300 movs r3, #0
|
|
|
80015c0: 61fb str r3, [r7, #28]
|
|
|
80015c2: 2300 movs r3, #0
|
|
|
80015c4: 62bb str r3, [r7, #40] ; 0x28
|
|
|
|
|
|
/* Check the parameters */
|
|
|
assert_param(IS_RCC_PERIPHCLOCK(PeriphClk));
|
|
|
|
|
|
switch (PeriphClk)
|
|
|
80015c6: 687b ldr r3, [r7, #4]
|
|
|
80015c8: 2b10 cmp r3, #16
|
|
|
80015ca: d00a beq.n 80015e2 <HAL_RCCEx_GetPeriphCLKFreq+0x4a>
|
|
|
80015cc: 687b ldr r3, [r7, #4]
|
|
|
80015ce: 2b10 cmp r3, #16
|
|
|
80015d0: f200 808e bhi.w 80016f0 <HAL_RCCEx_GetPeriphCLKFreq+0x158>
|
|
|
80015d4: 687b ldr r3, [r7, #4]
|
|
|
80015d6: 2b01 cmp r3, #1
|
|
|
80015d8: d049 beq.n 800166e <HAL_RCCEx_GetPeriphCLKFreq+0xd6>
|
|
|
80015da: 687b ldr r3, [r7, #4]
|
|
|
80015dc: 2b02 cmp r3, #2
|
|
|
80015de: d079 beq.n 80016d4 <HAL_RCCEx_GetPeriphCLKFreq+0x13c>
|
|
|
frequency = HAL_RCC_GetPCLK2Freq() / (((__HAL_RCC_GET_ADC_SOURCE() >> RCC_CFGR_ADCPRE_Pos) + 1) * 2);
|
|
|
break;
|
|
|
}
|
|
|
default:
|
|
|
{
|
|
|
break;
|
|
|
80015e0: e086 b.n 80016f0 <HAL_RCCEx_GetPeriphCLKFreq+0x158>
|
|
|
temp_reg = RCC->CFGR;
|
|
|
80015e2: 4b49 ldr r3, [pc, #292] ; (8001708 <HAL_RCCEx_GetPeriphCLKFreq+0x170>)
|
|
|
80015e4: 685b ldr r3, [r3, #4]
|
|
|
80015e6: 61fb str r3, [r7, #28]
|
|
|
if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLON))
|
|
|
80015e8: 4b47 ldr r3, [pc, #284] ; (8001708 <HAL_RCCEx_GetPeriphCLKFreq+0x170>)
|
|
|
80015ea: 681b ldr r3, [r3, #0]
|
|
|
80015ec: f003 7380 and.w r3, r3, #16777216 ; 0x1000000
|
|
|
80015f0: 2b00 cmp r3, #0
|
|
|
80015f2: d07f beq.n 80016f4 <HAL_RCCEx_GetPeriphCLKFreq+0x15c>
|
|
|
pllmul = aPLLMULFactorTable[(uint32_t)(temp_reg & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos];
|
|
|
80015f4: 69fb ldr r3, [r7, #28]
|
|
|
80015f6: 0c9b lsrs r3, r3, #18
|
|
|
80015f8: f003 030f and.w r3, r3, #15
|
|
|
80015fc: 3330 adds r3, #48 ; 0x30
|
|
|
80015fe: 443b add r3, r7
|
|
|
8001600: f813 3c24 ldrb.w r3, [r3, #-36]
|
|
|
8001604: 623b str r3, [r7, #32]
|
|
|
if ((temp_reg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2)
|
|
|
8001606: 69fb ldr r3, [r7, #28]
|
|
|
8001608: f403 3380 and.w r3, r3, #65536 ; 0x10000
|
|
|
800160c: 2b00 cmp r3, #0
|
|
|
800160e: d017 beq.n 8001640 <HAL_RCCEx_GetPeriphCLKFreq+0xa8>
|
|
|
prediv1 = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos];
|
|
|
8001610: 4b3d ldr r3, [pc, #244] ; (8001708 <HAL_RCCEx_GetPeriphCLKFreq+0x170>)
|
|
|
8001612: 685b ldr r3, [r3, #4]
|
|
|
8001614: 0c5b lsrs r3, r3, #17
|
|
|
8001616: f003 0301 and.w r3, r3, #1
|
|
|
800161a: 3330 adds r3, #48 ; 0x30
|
|
|
800161c: 443b add r3, r7
|
|
|
800161e: f813 3c28 ldrb.w r3, [r3, #-40]
|
|
|
8001622: 627b str r3, [r7, #36] ; 0x24
|
|
|
if ((temp_reg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2)
|
|
|
8001624: 69fb ldr r3, [r7, #28]
|
|
|
8001626: f403 3380 and.w r3, r3, #65536 ; 0x10000
|
|
|
800162a: 2b00 cmp r3, #0
|
|
|
800162c: d00d beq.n 800164a <HAL_RCCEx_GetPeriphCLKFreq+0xb2>
|
|
|
pllclk = (uint32_t)((HSE_VALUE / prediv1) * pllmul);
|
|
|
800162e: 4a37 ldr r2, [pc, #220] ; (800170c <HAL_RCCEx_GetPeriphCLKFreq+0x174>)
|
|
|
8001630: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
|
8001632: fbb2 f2f3 udiv r2, r2, r3
|
|
|
8001636: 6a3b ldr r3, [r7, #32]
|
|
|
8001638: fb02 f303 mul.w r3, r2, r3
|
|
|
800163c: 62fb str r3, [r7, #44] ; 0x2c
|
|
|
800163e: e004 b.n 800164a <HAL_RCCEx_GetPeriphCLKFreq+0xb2>
|
|
|
pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul);
|
|
|
8001640: 6a3b ldr r3, [r7, #32]
|
|
|
8001642: 4a33 ldr r2, [pc, #204] ; (8001710 <HAL_RCCEx_GetPeriphCLKFreq+0x178>)
|
|
|
8001644: fb02 f303 mul.w r3, r2, r3
|
|
|
8001648: 62fb str r3, [r7, #44] ; 0x2c
|
|
|
if (__HAL_RCC_GET_USB_SOURCE() == RCC_USBCLKSOURCE_PLL)
|
|
|
800164a: 4b2f ldr r3, [pc, #188] ; (8001708 <HAL_RCCEx_GetPeriphCLKFreq+0x170>)
|
|
|
800164c: 685b ldr r3, [r3, #4]
|
|
|
800164e: f403 0380 and.w r3, r3, #4194304 ; 0x400000
|
|
|
8001652: f5b3 0f80 cmp.w r3, #4194304 ; 0x400000
|
|
|
8001656: d102 bne.n 800165e <HAL_RCCEx_GetPeriphCLKFreq+0xc6>
|
|
|
frequency = pllclk;
|
|
|
8001658: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
|
800165a: 62bb str r3, [r7, #40] ; 0x28
|
|
|
break;
|
|
|
800165c: e04a b.n 80016f4 <HAL_RCCEx_GetPeriphCLKFreq+0x15c>
|
|
|
frequency = (pllclk * 2) / 3;
|
|
|
800165e: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
|
8001660: 005b lsls r3, r3, #1
|
|
|
8001662: 4a2c ldr r2, [pc, #176] ; (8001714 <HAL_RCCEx_GetPeriphCLKFreq+0x17c>)
|
|
|
8001664: fba2 2303 umull r2, r3, r2, r3
|
|
|
8001668: 085b lsrs r3, r3, #1
|
|
|
800166a: 62bb str r3, [r7, #40] ; 0x28
|
|
|
break;
|
|
|
800166c: e042 b.n 80016f4 <HAL_RCCEx_GetPeriphCLKFreq+0x15c>
|
|
|
temp_reg = RCC->BDCR;
|
|
|
800166e: 4b26 ldr r3, [pc, #152] ; (8001708 <HAL_RCCEx_GetPeriphCLKFreq+0x170>)
|
|
|
8001670: 6a1b ldr r3, [r3, #32]
|
|
|
8001672: 61fb str r3, [r7, #28]
|
|
|
if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_LSE) && (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSERDY)))
|
|
|
8001674: 69fb ldr r3, [r7, #28]
|
|
|
8001676: f403 7340 and.w r3, r3, #768 ; 0x300
|
|
|
800167a: f5b3 7f80 cmp.w r3, #256 ; 0x100
|
|
|
800167e: d108 bne.n 8001692 <HAL_RCCEx_GetPeriphCLKFreq+0xfa>
|
|
|
8001680: 69fb ldr r3, [r7, #28]
|
|
|
8001682: f003 0302 and.w r3, r3, #2
|
|
|
8001686: 2b00 cmp r3, #0
|
|
|
8001688: d003 beq.n 8001692 <HAL_RCCEx_GetPeriphCLKFreq+0xfa>
|
|
|
frequency = LSE_VALUE;
|
|
|
800168a: f44f 4300 mov.w r3, #32768 ; 0x8000
|
|
|
800168e: 62bb str r3, [r7, #40] ; 0x28
|
|
|
8001690: e01f b.n 80016d2 <HAL_RCCEx_GetPeriphCLKFreq+0x13a>
|
|
|
else if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_LSI) && (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY)))
|
|
|
8001692: 69fb ldr r3, [r7, #28]
|
|
|
8001694: f403 7340 and.w r3, r3, #768 ; 0x300
|
|
|
8001698: f5b3 7f00 cmp.w r3, #512 ; 0x200
|
|
|
800169c: d109 bne.n 80016b2 <HAL_RCCEx_GetPeriphCLKFreq+0x11a>
|
|
|
800169e: 4b1a ldr r3, [pc, #104] ; (8001708 <HAL_RCCEx_GetPeriphCLKFreq+0x170>)
|
|
|
80016a0: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
|
80016a2: f003 0302 and.w r3, r3, #2
|
|
|
80016a6: 2b00 cmp r3, #0
|
|
|
80016a8: d003 beq.n 80016b2 <HAL_RCCEx_GetPeriphCLKFreq+0x11a>
|
|
|
frequency = LSI_VALUE;
|
|
|
80016aa: f649 4340 movw r3, #40000 ; 0x9c40
|
|
|
80016ae: 62bb str r3, [r7, #40] ; 0x28
|
|
|
80016b0: e00f b.n 80016d2 <HAL_RCCEx_GetPeriphCLKFreq+0x13a>
|
|
|
else if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_HSE_DIV128) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)))
|
|
|
80016b2: 69fb ldr r3, [r7, #28]
|
|
|
80016b4: f403 7340 and.w r3, r3, #768 ; 0x300
|
|
|
80016b8: f5b3 7f40 cmp.w r3, #768 ; 0x300
|
|
|
80016bc: d11c bne.n 80016f8 <HAL_RCCEx_GetPeriphCLKFreq+0x160>
|
|
|
80016be: 4b12 ldr r3, [pc, #72] ; (8001708 <HAL_RCCEx_GetPeriphCLKFreq+0x170>)
|
|
|
80016c0: 681b ldr r3, [r3, #0]
|
|
|
80016c2: f403 3300 and.w r3, r3, #131072 ; 0x20000
|
|
|
80016c6: 2b00 cmp r3, #0
|
|
|
80016c8: d016 beq.n 80016f8 <HAL_RCCEx_GetPeriphCLKFreq+0x160>
|
|
|
frequency = HSE_VALUE / 128U;
|
|
|
80016ca: f24f 4324 movw r3, #62500 ; 0xf424
|
|
|
80016ce: 62bb str r3, [r7, #40] ; 0x28
|
|
|
break;
|
|
|
80016d0: e012 b.n 80016f8 <HAL_RCCEx_GetPeriphCLKFreq+0x160>
|
|
|
80016d2: e011 b.n 80016f8 <HAL_RCCEx_GetPeriphCLKFreq+0x160>
|
|
|
frequency = HAL_RCC_GetPCLK2Freq() / (((__HAL_RCC_GET_ADC_SOURCE() >> RCC_CFGR_ADCPRE_Pos) + 1) * 2);
|
|
|
80016d4: f7ff fe78 bl 80013c8 <HAL_RCC_GetPCLK2Freq>
|
|
|
80016d8: 4602 mov r2, r0
|
|
|
80016da: 4b0b ldr r3, [pc, #44] ; (8001708 <HAL_RCCEx_GetPeriphCLKFreq+0x170>)
|
|
|
80016dc: 685b ldr r3, [r3, #4]
|
|
|
80016de: 0b9b lsrs r3, r3, #14
|
|
|
80016e0: f003 0303 and.w r3, r3, #3
|
|
|
80016e4: 3301 adds r3, #1
|
|
|
80016e6: 005b lsls r3, r3, #1
|
|
|
80016e8: fbb2 f3f3 udiv r3, r2, r3
|
|
|
80016ec: 62bb str r3, [r7, #40] ; 0x28
|
|
|
break;
|
|
|
80016ee: e004 b.n 80016fa <HAL_RCCEx_GetPeriphCLKFreq+0x162>
|
|
|
break;
|
|
|
80016f0: bf00 nop
|
|
|
80016f2: e002 b.n 80016fa <HAL_RCCEx_GetPeriphCLKFreq+0x162>
|
|
|
break;
|
|
|
80016f4: bf00 nop
|
|
|
80016f6: e000 b.n 80016fa <HAL_RCCEx_GetPeriphCLKFreq+0x162>
|
|
|
break;
|
|
|
80016f8: bf00 nop
|
|
|
}
|
|
|
}
|
|
|
return (frequency);
|
|
|
80016fa: 6abb ldr r3, [r7, #40] ; 0x28
|
|
|
}
|
|
|
80016fc: 4618 mov r0, r3
|
|
|
80016fe: 3734 adds r7, #52 ; 0x34
|
|
|
8001700: 46bd mov sp, r7
|
|
|
8001702: bd90 pop {r4, r7, pc}
|
|
|
8001704: 08002c00 .word 0x08002c00
|
|
|
8001708: 40021000 .word 0x40021000
|
|
|
800170c: 007a1200 .word 0x007a1200
|
|
|
8001710: 003d0900 .word 0x003d0900
|
|
|
8001714: aaaaaaab .word 0xaaaaaaab
|
|
|
|
|
|
08001718 <HAL_RTC_Init>:
|
|
|
* @param hrtc pointer to a RTC_HandleTypeDef structure that contains
|
|
|
* the configuration information for RTC.
|
|
|
* @retval HAL status
|
|
|
*/
|
|
|
HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc)
|
|
|
{
|
|
|
8001718: b580 push {r7, lr}
|
|
|
800171a: b084 sub sp, #16
|
|
|
800171c: af00 add r7, sp, #0
|
|
|
800171e: 6078 str r0, [r7, #4]
|
|
|
uint32_t prescaler = 0U;
|
|
|
8001720: 2300 movs r3, #0
|
|
|
8001722: 60fb str r3, [r7, #12]
|
|
|
/* Check input parameters */
|
|
|
if (hrtc == NULL)
|
|
|
8001724: 687b ldr r3, [r7, #4]
|
|
|
8001726: 2b00 cmp r3, #0
|
|
|
8001728: d101 bne.n 800172e <HAL_RTC_Init+0x16>
|
|
|
{
|
|
|
return HAL_ERROR;
|
|
|
800172a: 2301 movs r3, #1
|
|
|
800172c: e084 b.n 8001838 <HAL_RTC_Init+0x120>
|
|
|
{
|
|
|
hrtc->MspDeInitCallback = HAL_RTC_MspDeInit;
|
|
|
}
|
|
|
}
|
|
|
#else
|
|
|
if (hrtc->State == HAL_RTC_STATE_RESET)
|
|
|
800172e: 687b ldr r3, [r7, #4]
|
|
|
8001730: 7c5b ldrb r3, [r3, #17]
|
|
|
8001732: b2db uxtb r3, r3
|
|
|
8001734: 2b00 cmp r3, #0
|
|
|
8001736: d105 bne.n 8001744 <HAL_RTC_Init+0x2c>
|
|
|
{
|
|
|
/* Allocate lock resource and initialize it */
|
|
|
hrtc->Lock = HAL_UNLOCKED;
|
|
|
8001738: 687b ldr r3, [r7, #4]
|
|
|
800173a: 2200 movs r2, #0
|
|
|
800173c: 741a strb r2, [r3, #16]
|
|
|
|
|
|
/* Initialize RTC MSP */
|
|
|
HAL_RTC_MspInit(hrtc);
|
|
|
800173e: 6878 ldr r0, [r7, #4]
|
|
|
8001740: f7fe fe0c bl 800035c <HAL_RTC_MspInit>
|
|
|
}
|
|
|
#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */
|
|
|
|
|
|
/* Set RTC state */
|
|
|
hrtc->State = HAL_RTC_STATE_BUSY;
|
|
|
8001744: 687b ldr r3, [r7, #4]
|
|
|
8001746: 2202 movs r2, #2
|
|
|
8001748: 745a strb r2, [r3, #17]
|
|
|
|
|
|
/* Waiting for synchro */
|
|
|
if (HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
|
|
|
800174a: 6878 ldr r0, [r7, #4]
|
|
|
800174c: f000 f952 bl 80019f4 <HAL_RTC_WaitForSynchro>
|
|
|
8001750: 4603 mov r3, r0
|
|
|
8001752: 2b00 cmp r3, #0
|
|
|
8001754: d004 beq.n 8001760 <HAL_RTC_Init+0x48>
|
|
|
{
|
|
|
/* Set RTC state */
|
|
|
hrtc->State = HAL_RTC_STATE_ERROR;
|
|
|
8001756: 687b ldr r3, [r7, #4]
|
|
|
8001758: 2204 movs r2, #4
|
|
|
800175a: 745a strb r2, [r3, #17]
|
|
|
|
|
|
return HAL_ERROR;
|
|
|
800175c: 2301 movs r3, #1
|
|
|
800175e: e06b b.n 8001838 <HAL_RTC_Init+0x120>
|
|
|
}
|
|
|
|
|
|
/* Set Initialization mode */
|
|
|
if (RTC_EnterInitMode(hrtc) != HAL_OK)
|
|
|
8001760: 6878 ldr r0, [r7, #4]
|
|
|
8001762: f000 fa0b bl 8001b7c <RTC_EnterInitMode>
|
|
|
8001766: 4603 mov r3, r0
|
|
|
8001768: 2b00 cmp r3, #0
|
|
|
800176a: d004 beq.n 8001776 <HAL_RTC_Init+0x5e>
|
|
|
{
|
|
|
/* Set RTC state */
|
|
|
hrtc->State = HAL_RTC_STATE_ERROR;
|
|
|
800176c: 687b ldr r3, [r7, #4]
|
|
|
800176e: 2204 movs r2, #4
|
|
|
8001770: 745a strb r2, [r3, #17]
|
|
|
|
|
|
return HAL_ERROR;
|
|
|
8001772: 2301 movs r3, #1
|
|
|
8001774: e060 b.n 8001838 <HAL_RTC_Init+0x120>
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
/* Clear Flags Bits */
|
|
|
CLEAR_BIT(hrtc->Instance->CRL, (RTC_FLAG_OW | RTC_FLAG_ALRAF | RTC_FLAG_SEC));
|
|
|
8001776: 687b ldr r3, [r7, #4]
|
|
|
8001778: 681b ldr r3, [r3, #0]
|
|
|
800177a: 685a ldr r2, [r3, #4]
|
|
|
800177c: 687b ldr r3, [r7, #4]
|
|
|
800177e: 681b ldr r3, [r3, #0]
|
|
|
8001780: f022 0207 bic.w r2, r2, #7
|
|
|
8001784: 605a str r2, [r3, #4]
|
|
|
|
|
|
if (hrtc->Init.OutPut != RTC_OUTPUTSOURCE_NONE)
|
|
|
8001786: 687b ldr r3, [r7, #4]
|
|
|
8001788: 689b ldr r3, [r3, #8]
|
|
|
800178a: 2b00 cmp r3, #0
|
|
|
800178c: d005 beq.n 800179a <HAL_RTC_Init+0x82>
|
|
|
{
|
|
|
/* Disable the selected Tamper pin */
|
|
|
CLEAR_BIT(BKP->CR, BKP_CR_TPE);
|
|
|
800178e: 4b2c ldr r3, [pc, #176] ; (8001840 <HAL_RTC_Init+0x128>)
|
|
|
8001790: 6b1b ldr r3, [r3, #48] ; 0x30
|
|
|
8001792: 4a2b ldr r2, [pc, #172] ; (8001840 <HAL_RTC_Init+0x128>)
|
|
|
8001794: f023 0301 bic.w r3, r3, #1
|
|
|
8001798: 6313 str r3, [r2, #48] ; 0x30
|
|
|
}
|
|
|
|
|
|
/* Set the signal which will be routed to RTC Tamper pin*/
|
|
|
MODIFY_REG(BKP->RTCCR, (BKP_RTCCR_CCO | BKP_RTCCR_ASOE | BKP_RTCCR_ASOS), hrtc->Init.OutPut);
|
|
|
800179a: 4b29 ldr r3, [pc, #164] ; (8001840 <HAL_RTC_Init+0x128>)
|
|
|
800179c: 6adb ldr r3, [r3, #44] ; 0x2c
|
|
|
800179e: f423 7260 bic.w r2, r3, #896 ; 0x380
|
|
|
80017a2: 687b ldr r3, [r7, #4]
|
|
|
80017a4: 689b ldr r3, [r3, #8]
|
|
|
80017a6: 4926 ldr r1, [pc, #152] ; (8001840 <HAL_RTC_Init+0x128>)
|
|
|
80017a8: 4313 orrs r3, r2
|
|
|
80017aa: 62cb str r3, [r1, #44] ; 0x2c
|
|
|
|
|
|
if (hrtc->Init.AsynchPrediv != RTC_AUTO_1_SECOND)
|
|
|
80017ac: 687b ldr r3, [r7, #4]
|
|
|
80017ae: 685b ldr r3, [r3, #4]
|
|
|
80017b0: f1b3 3fff cmp.w r3, #4294967295
|
|
|
80017b4: d003 beq.n 80017be <HAL_RTC_Init+0xa6>
|
|
|
{
|
|
|
/* RTC Prescaler provided directly by end-user*/
|
|
|
prescaler = hrtc->Init.AsynchPrediv;
|
|
|
80017b6: 687b ldr r3, [r7, #4]
|
|
|
80017b8: 685b ldr r3, [r3, #4]
|
|
|
80017ba: 60fb str r3, [r7, #12]
|
|
|
80017bc: e00e b.n 80017dc <HAL_RTC_Init+0xc4>
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
/* RTC Prescaler will be automatically calculated to get 1 second timebase */
|
|
|
/* Get the RTCCLK frequency */
|
|
|
prescaler = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_RTC);
|
|
|
80017be: 2001 movs r0, #1
|
|
|
80017c0: f7ff feea bl 8001598 <HAL_RCCEx_GetPeriphCLKFreq>
|
|
|
80017c4: 60f8 str r0, [r7, #12]
|
|
|
|
|
|
/* Check that RTC clock is enabled*/
|
|
|
if (prescaler == 0U)
|
|
|
80017c6: 68fb ldr r3, [r7, #12]
|
|
|
80017c8: 2b00 cmp r3, #0
|
|
|
80017ca: d104 bne.n 80017d6 <HAL_RTC_Init+0xbe>
|
|
|
{
|
|
|
/* Should not happen. Frequency is not available*/
|
|
|
hrtc->State = HAL_RTC_STATE_ERROR;
|
|
|
80017cc: 687b ldr r3, [r7, #4]
|
|
|
80017ce: 2204 movs r2, #4
|
|
|
80017d0: 745a strb r2, [r3, #17]
|
|
|
return HAL_ERROR;
|
|
|
80017d2: 2301 movs r3, #1
|
|
|
80017d4: e030 b.n 8001838 <HAL_RTC_Init+0x120>
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
/* RTC period = RTCCLK/(RTC_PR + 1) */
|
|
|
prescaler = prescaler - 1U;
|
|
|
80017d6: 68fb ldr r3, [r7, #12]
|
|
|
80017d8: 3b01 subs r3, #1
|
|
|
80017da: 60fb str r3, [r7, #12]
|
|
|
}
|
|
|
}
|
|
|
|
|
|
/* Configure the RTC_PRLH / RTC_PRLL */
|
|
|
MODIFY_REG(hrtc->Instance->PRLH, RTC_PRLH_PRL, (prescaler >> 16U));
|
|
|
80017dc: 687b ldr r3, [r7, #4]
|
|
|
80017de: 681b ldr r3, [r3, #0]
|
|
|
80017e0: 689b ldr r3, [r3, #8]
|
|
|
80017e2: f023 010f bic.w r1, r3, #15
|
|
|
80017e6: 68fb ldr r3, [r7, #12]
|
|
|
80017e8: 0c1a lsrs r2, r3, #16
|
|
|
80017ea: 687b ldr r3, [r7, #4]
|
|
|
80017ec: 681b ldr r3, [r3, #0]
|
|
|
80017ee: 430a orrs r2, r1
|
|
|
80017f0: 609a str r2, [r3, #8]
|
|
|
MODIFY_REG(hrtc->Instance->PRLL, RTC_PRLL_PRL, (prescaler & RTC_PRLL_PRL));
|
|
|
80017f2: 687b ldr r3, [r7, #4]
|
|
|
80017f4: 681b ldr r3, [r3, #0]
|
|
|
80017f6: 68db ldr r3, [r3, #12]
|
|
|
80017f8: 0c1b lsrs r3, r3, #16
|
|
|
80017fa: 041b lsls r3, r3, #16
|
|
|
80017fc: 68fa ldr r2, [r7, #12]
|
|
|
80017fe: b291 uxth r1, r2
|
|
|
8001800: 687a ldr r2, [r7, #4]
|
|
|
8001802: 6812 ldr r2, [r2, #0]
|
|
|
8001804: 430b orrs r3, r1
|
|
|
8001806: 60d3 str r3, [r2, #12]
|
|
|
|
|
|
/* Wait for synchro */
|
|
|
if (RTC_ExitInitMode(hrtc) != HAL_OK)
|
|
|
8001808: 6878 ldr r0, [r7, #4]
|
|
|
800180a: f000 f9df bl 8001bcc <RTC_ExitInitMode>
|
|
|
800180e: 4603 mov r3, r0
|
|
|
8001810: 2b00 cmp r3, #0
|
|
|
8001812: d004 beq.n 800181e <HAL_RTC_Init+0x106>
|
|
|
{
|
|
|
hrtc->State = HAL_RTC_STATE_ERROR;
|
|
|
8001814: 687b ldr r3, [r7, #4]
|
|
|
8001816: 2204 movs r2, #4
|
|
|
8001818: 745a strb r2, [r3, #17]
|
|
|
|
|
|
return HAL_ERROR;
|
|
|
800181a: 2301 movs r3, #1
|
|
|
800181c: e00c b.n 8001838 <HAL_RTC_Init+0x120>
|
|
|
}
|
|
|
|
|
|
/* Initialize date to 1st of January 2000 */
|
|
|
hrtc->DateToUpdate.Year = 0x00U;
|
|
|
800181e: 687b ldr r3, [r7, #4]
|
|
|
8001820: 2200 movs r2, #0
|
|
|
8001822: 73da strb r2, [r3, #15]
|
|
|
hrtc->DateToUpdate.Month = RTC_MONTH_JANUARY;
|
|
|
8001824: 687b ldr r3, [r7, #4]
|
|
|
8001826: 2201 movs r2, #1
|
|
|
8001828: 735a strb r2, [r3, #13]
|
|
|
hrtc->DateToUpdate.Date = 0x01U;
|
|
|
800182a: 687b ldr r3, [r7, #4]
|
|
|
800182c: 2201 movs r2, #1
|
|
|
800182e: 739a strb r2, [r3, #14]
|
|
|
|
|
|
/* Set RTC state */
|
|
|
hrtc->State = HAL_RTC_STATE_READY;
|
|
|
8001830: 687b ldr r3, [r7, #4]
|
|
|
8001832: 2201 movs r2, #1
|
|
|
8001834: 745a strb r2, [r3, #17]
|
|
|
|
|
|
return HAL_OK;
|
|
|
8001836: 2300 movs r3, #0
|
|
|
}
|
|
|
}
|
|
|
8001838: 4618 mov r0, r3
|
|
|
800183a: 3710 adds r7, #16
|
|
|
800183c: 46bd mov sp, r7
|
|
|
800183e: bd80 pop {r7, pc}
|
|
|
8001840: 40006c00 .word 0x40006c00
|
|
|
|
|
|
08001844 <HAL_RTC_GetTime>:
|
|
|
* @arg RTC_FORMAT_BIN: Binary data format
|
|
|
* @arg RTC_FORMAT_BCD: BCD data format
|
|
|
* @retval HAL status
|
|
|
*/
|
|
|
HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
|
|
|
{
|
|
|
8001844: b580 push {r7, lr}
|
|
|
8001846: b088 sub sp, #32
|
|
|
8001848: af00 add r7, sp, #0
|
|
|
800184a: 60f8 str r0, [r7, #12]
|
|
|
800184c: 60b9 str r1, [r7, #8]
|
|
|
800184e: 607a str r2, [r7, #4]
|
|
|
uint32_t counter_time = 0U, counter_alarm = 0U, days_elapsed = 0U, hours = 0U;
|
|
|
8001850: 2300 movs r3, #0
|
|
|
8001852: 61bb str r3, [r7, #24]
|
|
|
8001854: 2300 movs r3, #0
|
|
|
8001856: 61fb str r3, [r7, #28]
|
|
|
8001858: 2300 movs r3, #0
|
|
|
800185a: 617b str r3, [r7, #20]
|
|
|
800185c: 2300 movs r3, #0
|
|
|
800185e: 613b str r3, [r7, #16]
|
|
|
|
|
|
/* Check input parameters */
|
|
|
if ((hrtc == NULL) || (sTime == NULL))
|
|
|
8001860: 68fb ldr r3, [r7, #12]
|
|
|
8001862: 2b00 cmp r3, #0
|
|
|
8001864: d002 beq.n 800186c <HAL_RTC_GetTime+0x28>
|
|
|
8001866: 68bb ldr r3, [r7, #8]
|
|
|
8001868: 2b00 cmp r3, #0
|
|
|
800186a: d101 bne.n 8001870 <HAL_RTC_GetTime+0x2c>
|
|
|
{
|
|
|
return HAL_ERROR;
|
|
|
800186c: 2301 movs r3, #1
|
|
|
800186e: e0b5 b.n 80019dc <HAL_RTC_GetTime+0x198>
|
|
|
|
|
|
/* Check the parameters */
|
|
|
assert_param(IS_RTC_FORMAT(Format));
|
|
|
|
|
|
/* Check if counter overflow occurred */
|
|
|
if (__HAL_RTC_OVERFLOW_GET_FLAG(hrtc, RTC_FLAG_OW))
|
|
|
8001870: 68fb ldr r3, [r7, #12]
|
|
|
8001872: 681b ldr r3, [r3, #0]
|
|
|
8001874: 685b ldr r3, [r3, #4]
|
|
|
8001876: f003 0304 and.w r3, r3, #4
|
|
|
800187a: 2b00 cmp r3, #0
|
|
|
800187c: d001 beq.n 8001882 <HAL_RTC_GetTime+0x3e>
|
|
|
{
|
|
|
return HAL_ERROR;
|
|
|
800187e: 2301 movs r3, #1
|
|
|
8001880: e0ac b.n 80019dc <HAL_RTC_GetTime+0x198>
|
|
|
}
|
|
|
|
|
|
/* Read the time counter*/
|
|
|
counter_time = RTC_ReadTimeCounter(hrtc);
|
|
|
8001882: 68f8 ldr r0, [r7, #12]
|
|
|
8001884: f000 f8e3 bl 8001a4e <RTC_ReadTimeCounter>
|
|
|
8001888: 61b8 str r0, [r7, #24]
|
|
|
|
|
|
/* Fill the structure fields with the read parameters */
|
|
|
hours = counter_time / 3600U;
|
|
|
800188a: 69bb ldr r3, [r7, #24]
|
|
|
800188c: 4a55 ldr r2, [pc, #340] ; (80019e4 <HAL_RTC_GetTime+0x1a0>)
|
|
|
800188e: fba2 2303 umull r2, r3, r2, r3
|
|
|
8001892: 0adb lsrs r3, r3, #11
|
|
|
8001894: 613b str r3, [r7, #16]
|
|
|
sTime->Minutes = (uint8_t)((counter_time % 3600U) / 60U);
|
|
|
8001896: 69ba ldr r2, [r7, #24]
|
|
|
8001898: 4b52 ldr r3, [pc, #328] ; (80019e4 <HAL_RTC_GetTime+0x1a0>)
|
|
|
800189a: fba3 1302 umull r1, r3, r3, r2
|
|
|
800189e: 0adb lsrs r3, r3, #11
|
|
|
80018a0: f44f 6161 mov.w r1, #3600 ; 0xe10
|
|
|
80018a4: fb01 f303 mul.w r3, r1, r3
|
|
|
80018a8: 1ad3 subs r3, r2, r3
|
|
|
80018aa: 4a4f ldr r2, [pc, #316] ; (80019e8 <HAL_RTC_GetTime+0x1a4>)
|
|
|
80018ac: fba2 2303 umull r2, r3, r2, r3
|
|
|
80018b0: 095b lsrs r3, r3, #5
|
|
|
80018b2: b2da uxtb r2, r3
|
|
|
80018b4: 68bb ldr r3, [r7, #8]
|
|
|
80018b6: 705a strb r2, [r3, #1]
|
|
|
sTime->Seconds = (uint8_t)((counter_time % 3600U) % 60U);
|
|
|
80018b8: 69bb ldr r3, [r7, #24]
|
|
|
80018ba: 4a4a ldr r2, [pc, #296] ; (80019e4 <HAL_RTC_GetTime+0x1a0>)
|
|
|
80018bc: fba2 1203 umull r1, r2, r2, r3
|
|
|
80018c0: 0ad2 lsrs r2, r2, #11
|
|
|
80018c2: f44f 6161 mov.w r1, #3600 ; 0xe10
|
|
|
80018c6: fb01 f202 mul.w r2, r1, r2
|
|
|
80018ca: 1a9a subs r2, r3, r2
|
|
|
80018cc: 4b46 ldr r3, [pc, #280] ; (80019e8 <HAL_RTC_GetTime+0x1a4>)
|
|
|
80018ce: fba3 1302 umull r1, r3, r3, r2
|
|
|
80018d2: 0959 lsrs r1, r3, #5
|
|
|
80018d4: 460b mov r3, r1
|
|
|
80018d6: 011b lsls r3, r3, #4
|
|
|
80018d8: 1a5b subs r3, r3, r1
|
|
|
80018da: 009b lsls r3, r3, #2
|
|
|
80018dc: 1ad1 subs r1, r2, r3
|
|
|
80018de: b2ca uxtb r2, r1
|
|
|
80018e0: 68bb ldr r3, [r7, #8]
|
|
|
80018e2: 709a strb r2, [r3, #2]
|
|
|
|
|
|
if (hours >= 24U)
|
|
|
80018e4: 693b ldr r3, [r7, #16]
|
|
|
80018e6: 2b17 cmp r3, #23
|
|
|
80018e8: d955 bls.n 8001996 <HAL_RTC_GetTime+0x152>
|
|
|
{
|
|
|
/* Get number of days elapsed from last calculation */
|
|
|
days_elapsed = (hours / 24U);
|
|
|
80018ea: 693b ldr r3, [r7, #16]
|
|
|
80018ec: 4a3f ldr r2, [pc, #252] ; (80019ec <HAL_RTC_GetTime+0x1a8>)
|
|
|
80018ee: fba2 2303 umull r2, r3, r2, r3
|
|
|
80018f2: 091b lsrs r3, r3, #4
|
|
|
80018f4: 617b str r3, [r7, #20]
|
|
|
|
|
|
/* Set Hours in RTC_TimeTypeDef structure*/
|
|
|
sTime->Hours = (hours % 24U);
|
|
|
80018f6: 6939 ldr r1, [r7, #16]
|
|
|
80018f8: 4b3c ldr r3, [pc, #240] ; (80019ec <HAL_RTC_GetTime+0x1a8>)
|
|
|
80018fa: fba3 2301 umull r2, r3, r3, r1
|
|
|
80018fe: 091a lsrs r2, r3, #4
|
|
|
8001900: 4613 mov r3, r2
|
|
|
8001902: 005b lsls r3, r3, #1
|
|
|
8001904: 4413 add r3, r2
|
|
|
8001906: 00db lsls r3, r3, #3
|
|
|
8001908: 1aca subs r2, r1, r3
|
|
|
800190a: b2d2 uxtb r2, r2
|
|
|
800190c: 68bb ldr r3, [r7, #8]
|
|
|
800190e: 701a strb r2, [r3, #0]
|
|
|
|
|
|
/* Read Alarm counter in RTC registers */
|
|
|
counter_alarm = RTC_ReadAlarmCounter(hrtc);
|
|
|
8001910: 68f8 ldr r0, [r7, #12]
|
|
|
8001912: f000 f8f3 bl 8001afc <RTC_ReadAlarmCounter>
|
|
|
8001916: 61f8 str r0, [r7, #28]
|
|
|
|
|
|
/* Calculate remaining time to reach alarm (only if set and not yet expired)*/
|
|
|
if ((counter_alarm != RTC_ALARM_RESETVALUE) && (counter_alarm > counter_time))
|
|
|
8001918: 69fb ldr r3, [r7, #28]
|
|
|
800191a: f1b3 3fff cmp.w r3, #4294967295
|
|
|
800191e: d008 beq.n 8001932 <HAL_RTC_GetTime+0xee>
|
|
|
8001920: 69fa ldr r2, [r7, #28]
|
|
|
8001922: 69bb ldr r3, [r7, #24]
|
|
|
8001924: 429a cmp r2, r3
|
|
|
8001926: d904 bls.n 8001932 <HAL_RTC_GetTime+0xee>
|
|
|
{
|
|
|
counter_alarm -= counter_time;
|
|
|
8001928: 69fa ldr r2, [r7, #28]
|
|
|
800192a: 69bb ldr r3, [r7, #24]
|
|
|
800192c: 1ad3 subs r3, r2, r3
|
|
|
800192e: 61fb str r3, [r7, #28]
|
|
|
8001930: e002 b.n 8001938 <HAL_RTC_GetTime+0xf4>
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
/* In case of counter_alarm < counter_time */
|
|
|
/* Alarm expiration already occurred but alarm not deactivated */
|
|
|
counter_alarm = RTC_ALARM_RESETVALUE;
|
|
|
8001932: f04f 33ff mov.w r3, #4294967295
|
|
|
8001936: 61fb str r3, [r7, #28]
|
|
|
}
|
|
|
|
|
|
/* Set updated time in decreasing counter by number of days elapsed */
|
|
|
counter_time -= (days_elapsed * 24U * 3600U);
|
|
|
8001938: 697b ldr r3, [r7, #20]
|
|
|
800193a: 4a2d ldr r2, [pc, #180] ; (80019f0 <HAL_RTC_GetTime+0x1ac>)
|
|
|
800193c: fb02 f303 mul.w r3, r2, r3
|
|
|
8001940: 69ba ldr r2, [r7, #24]
|
|
|
8001942: 1ad3 subs r3, r2, r3
|
|
|
8001944: 61bb str r3, [r7, #24]
|
|
|
|
|
|
/* Write time counter in RTC registers */
|
|
|
if (RTC_WriteTimeCounter(hrtc, counter_time) != HAL_OK)
|
|
|
8001946: 69b9 ldr r1, [r7, #24]
|
|
|
8001948: 68f8 ldr r0, [r7, #12]
|
|
|
800194a: f000 f8b0 bl 8001aae <RTC_WriteTimeCounter>
|
|
|
800194e: 4603 mov r3, r0
|
|
|
8001950: 2b00 cmp r3, #0
|
|
|
8001952: d001 beq.n 8001958 <HAL_RTC_GetTime+0x114>
|
|
|
{
|
|
|
return HAL_ERROR;
|
|
|
8001954: 2301 movs r3, #1
|
|
|
8001956: e041 b.n 80019dc <HAL_RTC_GetTime+0x198>
|
|
|
}
|
|
|
|
|
|
/* Set updated alarm to be set */
|
|
|
if (counter_alarm != RTC_ALARM_RESETVALUE)
|
|
|
8001958: 69fb ldr r3, [r7, #28]
|
|
|
800195a: f1b3 3fff cmp.w r3, #4294967295
|
|
|
800195e: d00c beq.n 800197a <HAL_RTC_GetTime+0x136>
|
|
|
{
|
|
|
counter_alarm += counter_time;
|
|
|
8001960: 69fa ldr r2, [r7, #28]
|
|
|
8001962: 69bb ldr r3, [r7, #24]
|
|
|
8001964: 4413 add r3, r2
|
|
|
8001966: 61fb str r3, [r7, #28]
|
|
|
|
|
|
/* Write time counter in RTC registers */
|
|
|
if (RTC_WriteAlarmCounter(hrtc, counter_alarm) != HAL_OK)
|
|
|
8001968: 69f9 ldr r1, [r7, #28]
|
|
|
800196a: 68f8 ldr r0, [r7, #12]
|
|
|
800196c: f000 f8df bl 8001b2e <RTC_WriteAlarmCounter>
|
|
|
8001970: 4603 mov r3, r0
|
|
|
8001972: 2b00 cmp r3, #0
|
|
|
8001974: d00a beq.n 800198c <HAL_RTC_GetTime+0x148>
|
|
|
{
|
|
|
return HAL_ERROR;
|
|
|
8001976: 2301 movs r3, #1
|
|
|
8001978: e030 b.n 80019dc <HAL_RTC_GetTime+0x198>
|
|
|
}
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
/* Alarm already occurred. Set it to reset values to avoid unexpected expiration */
|
|
|
if (RTC_WriteAlarmCounter(hrtc, counter_alarm) != HAL_OK)
|
|
|
800197a: 69f9 ldr r1, [r7, #28]
|
|
|
800197c: 68f8 ldr r0, [r7, #12]
|
|
|
800197e: f000 f8d6 bl 8001b2e <RTC_WriteAlarmCounter>
|
|
|
8001982: 4603 mov r3, r0
|
|
|
8001984: 2b00 cmp r3, #0
|
|
|
8001986: d001 beq.n 800198c <HAL_RTC_GetTime+0x148>
|
|
|
{
|
|
|
return HAL_ERROR;
|
|
|
8001988: 2301 movs r3, #1
|
|
|
800198a: e027 b.n 80019dc <HAL_RTC_GetTime+0x198>
|
|
|
}
|
|
|
}
|
|
|
|
|
|
/* Update date */
|
|
|
RTC_DateUpdate(hrtc, days_elapsed);
|
|
|
800198c: 6979 ldr r1, [r7, #20]
|
|
|
800198e: 68f8 ldr r0, [r7, #12]
|
|
|
8001990: f000 f961 bl 8001c56 <RTC_DateUpdate>
|
|
|
8001994: e003 b.n 800199e <HAL_RTC_GetTime+0x15a>
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
sTime->Hours = hours;
|
|
|
8001996: 693b ldr r3, [r7, #16]
|
|
|
8001998: b2da uxtb r2, r3
|
|
|
800199a: 68bb ldr r3, [r7, #8]
|
|
|
800199c: 701a strb r2, [r3, #0]
|
|
|
}
|
|
|
|
|
|
/* Check the input parameters format */
|
|
|
if (Format != RTC_FORMAT_BIN)
|
|
|
800199e: 687b ldr r3, [r7, #4]
|
|
|
80019a0: 2b00 cmp r3, #0
|
|
|
80019a2: d01a beq.n 80019da <HAL_RTC_GetTime+0x196>
|
|
|
{
|
|
|
/* Convert the time structure parameters to BCD format */
|
|
|
sTime->Hours = (uint8_t)RTC_ByteToBcd2(sTime->Hours);
|
|
|
80019a4: 68bb ldr r3, [r7, #8]
|
|
|
80019a6: 781b ldrb r3, [r3, #0]
|
|
|
80019a8: 4618 mov r0, r3
|
|
|
80019aa: f000 f937 bl 8001c1c <RTC_ByteToBcd2>
|
|
|
80019ae: 4603 mov r3, r0
|
|
|
80019b0: 461a mov r2, r3
|
|
|
80019b2: 68bb ldr r3, [r7, #8]
|
|
|
80019b4: 701a strb r2, [r3, #0]
|
|
|
sTime->Minutes = (uint8_t)RTC_ByteToBcd2(sTime->Minutes);
|
|
|
80019b6: 68bb ldr r3, [r7, #8]
|
|
|
80019b8: 785b ldrb r3, [r3, #1]
|
|
|
80019ba: 4618 mov r0, r3
|
|
|
80019bc: f000 f92e bl 8001c1c <RTC_ByteToBcd2>
|
|
|
80019c0: 4603 mov r3, r0
|
|
|
80019c2: 461a mov r2, r3
|
|
|
80019c4: 68bb ldr r3, [r7, #8]
|
|
|
80019c6: 705a strb r2, [r3, #1]
|
|
|
sTime->Seconds = (uint8_t)RTC_ByteToBcd2(sTime->Seconds);
|
|
|
80019c8: 68bb ldr r3, [r7, #8]
|
|
|
80019ca: 789b ldrb r3, [r3, #2]
|
|
|
80019cc: 4618 mov r0, r3
|
|
|
80019ce: f000 f925 bl 8001c1c <RTC_ByteToBcd2>
|
|
|
80019d2: 4603 mov r3, r0
|
|
|
80019d4: 461a mov r2, r3
|
|
|
80019d6: 68bb ldr r3, [r7, #8]
|
|
|
80019d8: 709a strb r2, [r3, #2]
|
|
|
}
|
|
|
|
|
|
return HAL_OK;
|
|
|
80019da: 2300 movs r3, #0
|
|
|
}
|
|
|
80019dc: 4618 mov r0, r3
|
|
|
80019de: 3720 adds r7, #32
|
|
|
80019e0: 46bd mov sp, r7
|
|
|
80019e2: bd80 pop {r7, pc}
|
|
|
80019e4: 91a2b3c5 .word 0x91a2b3c5
|
|
|
80019e8: 88888889 .word 0x88888889
|
|
|
80019ec: aaaaaaab .word 0xaaaaaaab
|
|
|
80019f0: 00015180 .word 0x00015180
|
|
|
|
|
|
080019f4 <HAL_RTC_WaitForSynchro>:
|
|
|
* @param hrtc pointer to a RTC_HandleTypeDef structure that contains
|
|
|
* the configuration information for RTC.
|
|
|
* @retval HAL status
|
|
|
*/
|
|
|
HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef *hrtc)
|
|
|
{
|
|
|
80019f4: b580 push {r7, lr}
|
|
|
80019f6: b084 sub sp, #16
|
|
|
80019f8: af00 add r7, sp, #0
|
|
|
80019fa: 6078 str r0, [r7, #4]
|
|
|
uint32_t tickstart = 0U;
|
|
|
80019fc: 2300 movs r3, #0
|
|
|
80019fe: 60fb str r3, [r7, #12]
|
|
|
|
|
|
/* Check input parameters */
|
|
|
if (hrtc == NULL)
|
|
|
8001a00: 687b ldr r3, [r7, #4]
|
|
|
8001a02: 2b00 cmp r3, #0
|
|
|
8001a04: d101 bne.n 8001a0a <HAL_RTC_WaitForSynchro+0x16>
|
|
|
{
|
|
|
return HAL_ERROR;
|
|
|
8001a06: 2301 movs r3, #1
|
|
|
8001a08: e01d b.n 8001a46 <HAL_RTC_WaitForSynchro+0x52>
|
|
|
}
|
|
|
|
|
|
/* Clear RSF flag */
|
|
|
CLEAR_BIT(hrtc->Instance->CRL, RTC_FLAG_RSF);
|
|
|
8001a0a: 687b ldr r3, [r7, #4]
|
|
|
8001a0c: 681b ldr r3, [r3, #0]
|
|
|
8001a0e: 685a ldr r2, [r3, #4]
|
|
|
8001a10: 687b ldr r3, [r7, #4]
|
|
|
8001a12: 681b ldr r3, [r3, #0]
|
|
|
8001a14: f022 0208 bic.w r2, r2, #8
|
|
|
8001a18: 605a str r2, [r3, #4]
|
|
|
|
|
|
tickstart = HAL_GetTick();
|
|
|
8001a1a: f7fe fe4b bl 80006b4 <HAL_GetTick>
|
|
|
8001a1e: 60f8 str r0, [r7, #12]
|
|
|
|
|
|
/* Wait the registers to be synchronised */
|
|
|
while ((hrtc->Instance->CRL & RTC_FLAG_RSF) == (uint32_t)RESET)
|
|
|
8001a20: e009 b.n 8001a36 <HAL_RTC_WaitForSynchro+0x42>
|
|
|
{
|
|
|
if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
|
|
|
8001a22: f7fe fe47 bl 80006b4 <HAL_GetTick>
|
|
|
8001a26: 4602 mov r2, r0
|
|
|
8001a28: 68fb ldr r3, [r7, #12]
|
|
|
8001a2a: 1ad3 subs r3, r2, r3
|
|
|
8001a2c: f5b3 7f7a cmp.w r3, #1000 ; 0x3e8
|
|
|
8001a30: d901 bls.n 8001a36 <HAL_RTC_WaitForSynchro+0x42>
|
|
|
{
|
|
|
return HAL_TIMEOUT;
|
|
|
8001a32: 2303 movs r3, #3
|
|
|
8001a34: e007 b.n 8001a46 <HAL_RTC_WaitForSynchro+0x52>
|
|
|
while ((hrtc->Instance->CRL & RTC_FLAG_RSF) == (uint32_t)RESET)
|
|
|
8001a36: 687b ldr r3, [r7, #4]
|
|
|
8001a38: 681b ldr r3, [r3, #0]
|
|
|
8001a3a: 685b ldr r3, [r3, #4]
|
|
|
8001a3c: f003 0308 and.w r3, r3, #8
|
|
|
8001a40: 2b00 cmp r3, #0
|
|
|
8001a42: d0ee beq.n 8001a22 <HAL_RTC_WaitForSynchro+0x2e>
|
|
|
}
|
|
|
}
|
|
|
|
|
|
return HAL_OK;
|
|
|
8001a44: 2300 movs r3, #0
|
|
|
}
|
|
|
8001a46: 4618 mov r0, r3
|
|
|
8001a48: 3710 adds r7, #16
|
|
|
8001a4a: 46bd mov sp, r7
|
|
|
8001a4c: bd80 pop {r7, pc}
|
|
|
|
|
|
08001a4e <RTC_ReadTimeCounter>:
|
|
|
* @param hrtc pointer to a RTC_HandleTypeDef structure that contains
|
|
|
* the configuration information for RTC.
|
|
|
* @retval Time counter
|
|
|
*/
|
|
|
static uint32_t RTC_ReadTimeCounter(RTC_HandleTypeDef *hrtc)
|
|
|
{
|
|
|
8001a4e: b480 push {r7}
|
|
|
8001a50: b087 sub sp, #28
|
|
|
8001a52: af00 add r7, sp, #0
|
|
|
8001a54: 6078 str r0, [r7, #4]
|
|
|
uint16_t high1 = 0U, high2 = 0U, low = 0U;
|
|
|
8001a56: 2300 movs r3, #0
|
|
|
8001a58: 827b strh r3, [r7, #18]
|
|
|
8001a5a: 2300 movs r3, #0
|
|
|
8001a5c: 823b strh r3, [r7, #16]
|
|
|
8001a5e: 2300 movs r3, #0
|
|
|
8001a60: 81fb strh r3, [r7, #14]
|
|
|
uint32_t timecounter = 0U;
|
|
|
8001a62: 2300 movs r3, #0
|
|
|
8001a64: 617b str r3, [r7, #20]
|
|
|
|
|
|
high1 = READ_REG(hrtc->Instance->CNTH & RTC_CNTH_RTC_CNT);
|
|
|
8001a66: 687b ldr r3, [r7, #4]
|
|
|
8001a68: 681b ldr r3, [r3, #0]
|
|
|
8001a6a: 699b ldr r3, [r3, #24]
|
|
|
8001a6c: 827b strh r3, [r7, #18]
|
|
|
low = READ_REG(hrtc->Instance->CNTL & RTC_CNTL_RTC_CNT);
|
|
|
8001a6e: 687b ldr r3, [r7, #4]
|
|
|
8001a70: 681b ldr r3, [r3, #0]
|
|
|
8001a72: 69db ldr r3, [r3, #28]
|
|
|
8001a74: 81fb strh r3, [r7, #14]
|
|
|
high2 = READ_REG(hrtc->Instance->CNTH & RTC_CNTH_RTC_CNT);
|
|
|
8001a76: 687b ldr r3, [r7, #4]
|
|
|
8001a78: 681b ldr r3, [r3, #0]
|
|
|
8001a7a: 699b ldr r3, [r3, #24]
|
|
|
8001a7c: 823b strh r3, [r7, #16]
|
|
|
|
|
|
if (high1 != high2)
|
|
|
8001a7e: 8a7a ldrh r2, [r7, #18]
|
|
|
8001a80: 8a3b ldrh r3, [r7, #16]
|
|
|
8001a82: 429a cmp r2, r3
|
|
|
8001a84: d008 beq.n 8001a98 <RTC_ReadTimeCounter+0x4a>
|
|
|
{
|
|
|
/* In this case the counter roll over during reading of CNTL and CNTH registers,
|
|
|
read again CNTL register then return the counter value */
|
|
|
timecounter = (((uint32_t) high2 << 16U) | READ_REG(hrtc->Instance->CNTL & RTC_CNTL_RTC_CNT));
|
|
|
8001a86: 8a3b ldrh r3, [r7, #16]
|
|
|
8001a88: 041a lsls r2, r3, #16
|
|
|
8001a8a: 687b ldr r3, [r7, #4]
|
|
|
8001a8c: 681b ldr r3, [r3, #0]
|
|
|
8001a8e: 69db ldr r3, [r3, #28]
|
|
|
8001a90: b29b uxth r3, r3
|
|
|
8001a92: 4313 orrs r3, r2
|
|
|
8001a94: 617b str r3, [r7, #20]
|
|
|
8001a96: e004 b.n 8001aa2 <RTC_ReadTimeCounter+0x54>
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
/* No counter roll over during reading of CNTL and CNTH registers, counter
|
|
|
value is equal to first value of CNTL and CNTH */
|
|
|
timecounter = (((uint32_t) high1 << 16U) | low);
|
|
|
8001a98: 8a7b ldrh r3, [r7, #18]
|
|
|
8001a9a: 041a lsls r2, r3, #16
|
|
|
8001a9c: 89fb ldrh r3, [r7, #14]
|
|
|
8001a9e: 4313 orrs r3, r2
|
|
|
8001aa0: 617b str r3, [r7, #20]
|
|
|
}
|
|
|
|
|
|
return timecounter;
|
|
|
8001aa2: 697b ldr r3, [r7, #20]
|
|
|
}
|
|
|
8001aa4: 4618 mov r0, r3
|
|
|
8001aa6: 371c adds r7, #28
|
|
|
8001aa8: 46bd mov sp, r7
|
|
|
8001aaa: bc80 pop {r7}
|
|
|
8001aac: 4770 bx lr
|
|
|
|
|
|
08001aae <RTC_WriteTimeCounter>:
|
|
|
* the configuration information for RTC.
|
|
|
* @param TimeCounter: Counter to write in RTC_CNT registers
|
|
|
* @retval HAL status
|
|
|
*/
|
|
|
static HAL_StatusTypeDef RTC_WriteTimeCounter(RTC_HandleTypeDef *hrtc, uint32_t TimeCounter)
|
|
|
{
|
|
|
8001aae: b580 push {r7, lr}
|
|
|
8001ab0: b084 sub sp, #16
|
|
|
8001ab2: af00 add r7, sp, #0
|
|
|
8001ab4: 6078 str r0, [r7, #4]
|
|
|
8001ab6: 6039 str r1, [r7, #0]
|
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|
|
8001ab8: 2300 movs r3, #0
|
|
|
8001aba: 73fb strb r3, [r7, #15]
|
|
|
|
|
|
/* Set Initialization mode */
|
|
|
if (RTC_EnterInitMode(hrtc) != HAL_OK)
|
|
|
8001abc: 6878 ldr r0, [r7, #4]
|
|
|
8001abe: f000 f85d bl 8001b7c <RTC_EnterInitMode>
|
|
|
8001ac2: 4603 mov r3, r0
|
|
|
8001ac4: 2b00 cmp r3, #0
|
|
|
8001ac6: d002 beq.n 8001ace <RTC_WriteTimeCounter+0x20>
|
|
|
{
|
|
|
status = HAL_ERROR;
|
|
|
8001ac8: 2301 movs r3, #1
|
|
|
8001aca: 73fb strb r3, [r7, #15]
|
|
|
8001acc: e011 b.n 8001af2 <RTC_WriteTimeCounter+0x44>
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
/* Set RTC COUNTER MSB word */
|
|
|
WRITE_REG(hrtc->Instance->CNTH, (TimeCounter >> 16U));
|
|
|
8001ace: 687b ldr r3, [r7, #4]
|
|
|
8001ad0: 681b ldr r3, [r3, #0]
|
|
|
8001ad2: 683a ldr r2, [r7, #0]
|
|
|
8001ad4: 0c12 lsrs r2, r2, #16
|
|
|
8001ad6: 619a str r2, [r3, #24]
|
|
|
/* Set RTC COUNTER LSB word */
|
|
|
WRITE_REG(hrtc->Instance->CNTL, (TimeCounter & RTC_CNTL_RTC_CNT));
|
|
|
8001ad8: 687b ldr r3, [r7, #4]
|
|
|
8001ada: 681b ldr r3, [r3, #0]
|
|
|
8001adc: 683a ldr r2, [r7, #0]
|
|
|
8001ade: b292 uxth r2, r2
|
|
|
8001ae0: 61da str r2, [r3, #28]
|
|
|
|
|
|
/* Wait for synchro */
|
|
|
if (RTC_ExitInitMode(hrtc) != HAL_OK)
|
|
|
8001ae2: 6878 ldr r0, [r7, #4]
|
|
|
8001ae4: f000 f872 bl 8001bcc <RTC_ExitInitMode>
|
|
|
8001ae8: 4603 mov r3, r0
|
|
|
8001aea: 2b00 cmp r3, #0
|
|
|
8001aec: d001 beq.n 8001af2 <RTC_WriteTimeCounter+0x44>
|
|
|
{
|
|
|
status = HAL_ERROR;
|
|
|
8001aee: 2301 movs r3, #1
|
|
|
8001af0: 73fb strb r3, [r7, #15]
|
|
|
}
|
|
|
}
|
|
|
|
|
|
return status;
|
|
|
8001af2: 7bfb ldrb r3, [r7, #15]
|
|
|
}
|
|
|
8001af4: 4618 mov r0, r3
|
|
|
8001af6: 3710 adds r7, #16
|
|
|
8001af8: 46bd mov sp, r7
|
|
|
8001afa: bd80 pop {r7, pc}
|
|
|
|
|
|
08001afc <RTC_ReadAlarmCounter>:
|
|
|
* @param hrtc pointer to a RTC_HandleTypeDef structure that contains
|
|
|
* the configuration information for RTC.
|
|
|
* @retval Time counter
|
|
|
*/
|
|
|
static uint32_t RTC_ReadAlarmCounter(RTC_HandleTypeDef *hrtc)
|
|
|
{
|
|
|
8001afc: b480 push {r7}
|
|
|
8001afe: b085 sub sp, #20
|
|
|
8001b00: af00 add r7, sp, #0
|
|
|
8001b02: 6078 str r0, [r7, #4]
|
|
|
uint16_t high1 = 0U, low = 0U;
|
|
|
8001b04: 2300 movs r3, #0
|
|
|
8001b06: 81fb strh r3, [r7, #14]
|
|
|
8001b08: 2300 movs r3, #0
|
|
|
8001b0a: 81bb strh r3, [r7, #12]
|
|
|
|
|
|
high1 = READ_REG(hrtc->Instance->ALRH & RTC_CNTH_RTC_CNT);
|
|
|
8001b0c: 687b ldr r3, [r7, #4]
|
|
|
8001b0e: 681b ldr r3, [r3, #0]
|
|
|
8001b10: 6a1b ldr r3, [r3, #32]
|
|
|
8001b12: 81fb strh r3, [r7, #14]
|
|
|
low = READ_REG(hrtc->Instance->ALRL & RTC_CNTL_RTC_CNT);
|
|
|
8001b14: 687b ldr r3, [r7, #4]
|
|
|
8001b16: 681b ldr r3, [r3, #0]
|
|
|
8001b18: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
|
8001b1a: 81bb strh r3, [r7, #12]
|
|
|
|
|
|
return (((uint32_t) high1 << 16U) | low);
|
|
|
8001b1c: 89fb ldrh r3, [r7, #14]
|
|
|
8001b1e: 041a lsls r2, r3, #16
|
|
|
8001b20: 89bb ldrh r3, [r7, #12]
|
|
|
8001b22: 4313 orrs r3, r2
|
|
|
}
|
|
|
8001b24: 4618 mov r0, r3
|
|
|
8001b26: 3714 adds r7, #20
|
|
|
8001b28: 46bd mov sp, r7
|
|
|
8001b2a: bc80 pop {r7}
|
|
|
8001b2c: 4770 bx lr
|
|
|
|
|
|
08001b2e <RTC_WriteAlarmCounter>:
|
|
|
* the configuration information for RTC.
|
|
|
* @param AlarmCounter: Counter to write in RTC_ALR registers
|
|
|
* @retval HAL status
|
|
|
*/
|
|
|
static HAL_StatusTypeDef RTC_WriteAlarmCounter(RTC_HandleTypeDef *hrtc, uint32_t AlarmCounter)
|
|
|
{
|
|
|
8001b2e: b580 push {r7, lr}
|
|
|
8001b30: b084 sub sp, #16
|
|
|
8001b32: af00 add r7, sp, #0
|
|
|
8001b34: 6078 str r0, [r7, #4]
|
|
|
8001b36: 6039 str r1, [r7, #0]
|
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|
|
8001b38: 2300 movs r3, #0
|
|
|
8001b3a: 73fb strb r3, [r7, #15]
|
|
|
|
|
|
/* Set Initialization mode */
|
|
|
if (RTC_EnterInitMode(hrtc) != HAL_OK)
|
|
|
8001b3c: 6878 ldr r0, [r7, #4]
|
|
|
8001b3e: f000 f81d bl 8001b7c <RTC_EnterInitMode>
|
|
|
8001b42: 4603 mov r3, r0
|
|
|
8001b44: 2b00 cmp r3, #0
|
|
|
8001b46: d002 beq.n 8001b4e <RTC_WriteAlarmCounter+0x20>
|
|
|
{
|
|
|
status = HAL_ERROR;
|
|
|
8001b48: 2301 movs r3, #1
|
|
|
8001b4a: 73fb strb r3, [r7, #15]
|
|
|
8001b4c: e011 b.n 8001b72 <RTC_WriteAlarmCounter+0x44>
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
/* Set RTC COUNTER MSB word */
|
|
|
WRITE_REG(hrtc->Instance->ALRH, (AlarmCounter >> 16U));
|
|
|
8001b4e: 687b ldr r3, [r7, #4]
|
|
|
8001b50: 681b ldr r3, [r3, #0]
|
|
|
8001b52: 683a ldr r2, [r7, #0]
|
|
|
8001b54: 0c12 lsrs r2, r2, #16
|
|
|
8001b56: 621a str r2, [r3, #32]
|
|
|
/* Set RTC COUNTER LSB word */
|
|
|
WRITE_REG(hrtc->Instance->ALRL, (AlarmCounter & RTC_ALRL_RTC_ALR));
|
|
|
8001b58: 687b ldr r3, [r7, #4]
|
|
|
8001b5a: 681b ldr r3, [r3, #0]
|
|
|
8001b5c: 683a ldr r2, [r7, #0]
|
|
|
8001b5e: b292 uxth r2, r2
|
|
|
8001b60: 625a str r2, [r3, #36] ; 0x24
|
|
|
|
|
|
/* Wait for synchro */
|
|
|
if (RTC_ExitInitMode(hrtc) != HAL_OK)
|
|
|
8001b62: 6878 ldr r0, [r7, #4]
|
|
|
8001b64: f000 f832 bl 8001bcc <RTC_ExitInitMode>
|
|
|
8001b68: 4603 mov r3, r0
|
|
|
8001b6a: 2b00 cmp r3, #0
|
|
|
8001b6c: d001 beq.n 8001b72 <RTC_WriteAlarmCounter+0x44>
|
|
|
{
|
|
|
status = HAL_ERROR;
|
|
|
8001b6e: 2301 movs r3, #1
|
|
|
8001b70: 73fb strb r3, [r7, #15]
|
|
|
}
|
|
|
}
|
|
|
|
|
|
return status;
|
|
|
8001b72: 7bfb ldrb r3, [r7, #15]
|
|
|
}
|
|
|
8001b74: 4618 mov r0, r3
|
|
|
8001b76: 3710 adds r7, #16
|
|
|
8001b78: 46bd mov sp, r7
|
|
|
8001b7a: bd80 pop {r7, pc}
|
|
|
|
|
|
08001b7c <RTC_EnterInitMode>:
|
|
|
* @param hrtc pointer to a RTC_HandleTypeDef structure that contains
|
|
|
* the configuration information for RTC.
|
|
|
* @retval HAL status
|
|
|
*/
|
|
|
static HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef *hrtc)
|
|
|
{
|
|
|
8001b7c: b580 push {r7, lr}
|
|
|
8001b7e: b084 sub sp, #16
|
|
|
8001b80: af00 add r7, sp, #0
|
|
|
8001b82: 6078 str r0, [r7, #4]
|
|
|
uint32_t tickstart = 0U;
|
|
|
8001b84: 2300 movs r3, #0
|
|
|
8001b86: 60fb str r3, [r7, #12]
|
|
|
|
|
|
tickstart = HAL_GetTick();
|
|
|
8001b88: f7fe fd94 bl 80006b4 <HAL_GetTick>
|
|
|
8001b8c: 60f8 str r0, [r7, #12]
|
|
|
/* Wait till RTC is in INIT state and if Time out is reached exit */
|
|
|
while ((hrtc->Instance->CRL & RTC_CRL_RTOFF) == (uint32_t)RESET)
|
|
|
8001b8e: e009 b.n 8001ba4 <RTC_EnterInitMode+0x28>
|
|
|
{
|
|
|
if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
|
|
|
8001b90: f7fe fd90 bl 80006b4 <HAL_GetTick>
|
|
|
8001b94: 4602 mov r2, r0
|
|
|
8001b96: 68fb ldr r3, [r7, #12]
|
|
|
8001b98: 1ad3 subs r3, r2, r3
|
|
|
8001b9a: f5b3 7f7a cmp.w r3, #1000 ; 0x3e8
|
|
|
8001b9e: d901 bls.n 8001ba4 <RTC_EnterInitMode+0x28>
|
|
|
{
|
|
|
return HAL_TIMEOUT;
|
|
|
8001ba0: 2303 movs r3, #3
|
|
|
8001ba2: e00f b.n 8001bc4 <RTC_EnterInitMode+0x48>
|
|
|
while ((hrtc->Instance->CRL & RTC_CRL_RTOFF) == (uint32_t)RESET)
|
|
|
8001ba4: 687b ldr r3, [r7, #4]
|
|
|
8001ba6: 681b ldr r3, [r3, #0]
|
|
|
8001ba8: 685b ldr r3, [r3, #4]
|
|
|
8001baa: f003 0320 and.w r3, r3, #32
|
|
|
8001bae: 2b00 cmp r3, #0
|
|
|
8001bb0: d0ee beq.n 8001b90 <RTC_EnterInitMode+0x14>
|
|
|
}
|
|
|
}
|
|
|
|
|
|
/* Disable the write protection for RTC registers */
|
|
|
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
|
|
|
8001bb2: 687b ldr r3, [r7, #4]
|
|
|
8001bb4: 681b ldr r3, [r3, #0]
|
|
|
8001bb6: 685a ldr r2, [r3, #4]
|
|
|
8001bb8: 687b ldr r3, [r7, #4]
|
|
|
8001bba: 681b ldr r3, [r3, #0]
|
|
|
8001bbc: f042 0210 orr.w r2, r2, #16
|
|
|
8001bc0: 605a str r2, [r3, #4]
|
|
|
|
|
|
|
|
|
return HAL_OK;
|
|
|
8001bc2: 2300 movs r3, #0
|
|
|
}
|
|
|
8001bc4: 4618 mov r0, r3
|
|
|
8001bc6: 3710 adds r7, #16
|
|
|
8001bc8: 46bd mov sp, r7
|
|
|
8001bca: bd80 pop {r7, pc}
|
|
|
|
|
|
08001bcc <RTC_ExitInitMode>:
|
|
|
* @param hrtc pointer to a RTC_HandleTypeDef structure that contains
|
|
|
* the configuration information for RTC.
|
|
|
* @retval HAL status
|
|
|
*/
|
|
|
static HAL_StatusTypeDef RTC_ExitInitMode(RTC_HandleTypeDef *hrtc)
|
|
|
{
|
|
|
8001bcc: b580 push {r7, lr}
|
|
|
8001bce: b084 sub sp, #16
|
|
|
8001bd0: af00 add r7, sp, #0
|
|
|
8001bd2: 6078 str r0, [r7, #4]
|
|
|
uint32_t tickstart = 0U;
|
|
|
8001bd4: 2300 movs r3, #0
|
|
|
8001bd6: 60fb str r3, [r7, #12]
|
|
|
|
|
|
/* Disable the write protection for RTC registers */
|
|
|
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
|
|
|
8001bd8: 687b ldr r3, [r7, #4]
|
|
|
8001bda: 681b ldr r3, [r3, #0]
|
|
|
8001bdc: 685a ldr r2, [r3, #4]
|
|
|
8001bde: 687b ldr r3, [r7, #4]
|
|
|
8001be0: 681b ldr r3, [r3, #0]
|
|
|
8001be2: f022 0210 bic.w r2, r2, #16
|
|
|
8001be6: 605a str r2, [r3, #4]
|
|
|
|
|
|
tickstart = HAL_GetTick();
|
|
|
8001be8: f7fe fd64 bl 80006b4 <HAL_GetTick>
|
|
|
8001bec: 60f8 str r0, [r7, #12]
|
|
|
/* Wait till RTC is in INIT state and if Time out is reached exit */
|
|
|
while ((hrtc->Instance->CRL & RTC_CRL_RTOFF) == (uint32_t)RESET)
|
|
|
8001bee: e009 b.n 8001c04 <RTC_ExitInitMode+0x38>
|
|
|
{
|
|
|
if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
|
|
|
8001bf0: f7fe fd60 bl 80006b4 <HAL_GetTick>
|
|
|
8001bf4: 4602 mov r2, r0
|
|
|
8001bf6: 68fb ldr r3, [r7, #12]
|
|
|
8001bf8: 1ad3 subs r3, r2, r3
|
|
|
8001bfa: f5b3 7f7a cmp.w r3, #1000 ; 0x3e8
|
|
|
8001bfe: d901 bls.n 8001c04 <RTC_ExitInitMode+0x38>
|
|
|
{
|
|
|
return HAL_TIMEOUT;
|
|
|
8001c00: 2303 movs r3, #3
|
|
|
8001c02: e007 b.n 8001c14 <RTC_ExitInitMode+0x48>
|
|
|
while ((hrtc->Instance->CRL & RTC_CRL_RTOFF) == (uint32_t)RESET)
|
|
|
8001c04: 687b ldr r3, [r7, #4]
|
|
|
8001c06: 681b ldr r3, [r3, #0]
|
|
|
8001c08: 685b ldr r3, [r3, #4]
|
|
|
8001c0a: f003 0320 and.w r3, r3, #32
|
|
|
8001c0e: 2b00 cmp r3, #0
|
|
|
8001c10: d0ee beq.n 8001bf0 <RTC_ExitInitMode+0x24>
|
|
|
}
|
|
|
}
|
|
|
|
|
|
return HAL_OK;
|
|
|
8001c12: 2300 movs r3, #0
|
|
|
}
|
|
|
8001c14: 4618 mov r0, r3
|
|
|
8001c16: 3710 adds r7, #16
|
|
|
8001c18: 46bd mov sp, r7
|
|
|
8001c1a: bd80 pop {r7, pc}
|
|
|
|
|
|
08001c1c <RTC_ByteToBcd2>:
|
|
|
* @brief Converts a 2 digit decimal to BCD format.
|
|
|
* @param Value: Byte to be converted
|
|
|
* @retval Converted byte
|
|
|
*/
|
|
|
static uint8_t RTC_ByteToBcd2(uint8_t Value)
|
|
|
{
|
|
|
8001c1c: b480 push {r7}
|
|
|
8001c1e: b085 sub sp, #20
|
|
|
8001c20: af00 add r7, sp, #0
|
|
|
8001c22: 4603 mov r3, r0
|
|
|
8001c24: 71fb strb r3, [r7, #7]
|
|
|
uint32_t bcdhigh = 0U;
|
|
|
8001c26: 2300 movs r3, #0
|
|
|
8001c28: 60fb str r3, [r7, #12]
|
|
|
|
|
|
while (Value >= 10U)
|
|
|
8001c2a: e005 b.n 8001c38 <RTC_ByteToBcd2+0x1c>
|
|
|
{
|
|
|
bcdhigh++;
|
|
|
8001c2c: 68fb ldr r3, [r7, #12]
|
|
|
8001c2e: 3301 adds r3, #1
|
|
|
8001c30: 60fb str r3, [r7, #12]
|
|
|
Value -= 10U;
|
|
|
8001c32: 79fb ldrb r3, [r7, #7]
|
|
|
8001c34: 3b0a subs r3, #10
|
|
|
8001c36: 71fb strb r3, [r7, #7]
|
|
|
while (Value >= 10U)
|
|
|
8001c38: 79fb ldrb r3, [r7, #7]
|
|
|
8001c3a: 2b09 cmp r3, #9
|
|
|
8001c3c: d8f6 bhi.n 8001c2c <RTC_ByteToBcd2+0x10>
|
|
|
}
|
|
|
|
|
|
return ((uint8_t)(bcdhigh << 4U) | Value);
|
|
|
8001c3e: 68fb ldr r3, [r7, #12]
|
|
|
8001c40: b2db uxtb r3, r3
|
|
|
8001c42: 011b lsls r3, r3, #4
|
|
|
8001c44: b2da uxtb r2, r3
|
|
|
8001c46: 79fb ldrb r3, [r7, #7]
|
|
|
8001c48: 4313 orrs r3, r2
|
|
|
8001c4a: b2db uxtb r3, r3
|
|
|
}
|
|
|
8001c4c: 4618 mov r0, r3
|
|
|
8001c4e: 3714 adds r7, #20
|
|
|
8001c50: 46bd mov sp, r7
|
|
|
8001c52: bc80 pop {r7}
|
|
|
8001c54: 4770 bx lr
|
|
|
|
|
|
08001c56 <RTC_DateUpdate>:
|
|
|
* the configuration information for RTC.
|
|
|
* @param DayElapsed: Number of days elapsed from last date update
|
|
|
* @retval None
|
|
|
*/
|
|
|
static void RTC_DateUpdate(RTC_HandleTypeDef *hrtc, uint32_t DayElapsed)
|
|
|
{
|
|
|
8001c56: b580 push {r7, lr}
|
|
|
8001c58: b086 sub sp, #24
|
|
|
8001c5a: af00 add r7, sp, #0
|
|
|
8001c5c: 6078 str r0, [r7, #4]
|
|
|
8001c5e: 6039 str r1, [r7, #0]
|
|
|
uint32_t year = 0U, month = 0U, day = 0U;
|
|
|
8001c60: 2300 movs r3, #0
|
|
|
8001c62: 617b str r3, [r7, #20]
|
|
|
8001c64: 2300 movs r3, #0
|
|
|
8001c66: 613b str r3, [r7, #16]
|
|
|
8001c68: 2300 movs r3, #0
|
|
|
8001c6a: 60fb str r3, [r7, #12]
|
|
|
uint32_t loop = 0U;
|
|
|
8001c6c: 2300 movs r3, #0
|
|
|
8001c6e: 60bb str r3, [r7, #8]
|
|
|
|
|
|
/* Get the current year*/
|
|
|
year = hrtc->DateToUpdate.Year;
|
|
|
8001c70: 687b ldr r3, [r7, #4]
|
|
|
8001c72: 7bdb ldrb r3, [r3, #15]
|
|
|
8001c74: 617b str r3, [r7, #20]
|
|
|
|
|
|
/* Get the current month and day */
|
|
|
month = hrtc->DateToUpdate.Month;
|
|
|
8001c76: 687b ldr r3, [r7, #4]
|
|
|
8001c78: 7b5b ldrb r3, [r3, #13]
|
|
|
8001c7a: 613b str r3, [r7, #16]
|
|
|
day = hrtc->DateToUpdate.Date;
|
|
|
8001c7c: 687b ldr r3, [r7, #4]
|
|
|
8001c7e: 7b9b ldrb r3, [r3, #14]
|
|
|
8001c80: 60fb str r3, [r7, #12]
|
|
|
|
|
|
for (loop = 0U; loop < DayElapsed; loop++)
|
|
|
8001c82: 2300 movs r3, #0
|
|
|
8001c84: 60bb str r3, [r7, #8]
|
|
|
8001c86: e06f b.n 8001d68 <RTC_DateUpdate+0x112>
|
|
|
{
|
|
|
if ((month == 1U) || (month == 3U) || (month == 5U) || (month == 7U) || \
|
|
|
8001c88: 693b ldr r3, [r7, #16]
|
|
|
8001c8a: 2b01 cmp r3, #1
|
|
|
8001c8c: d011 beq.n 8001cb2 <RTC_DateUpdate+0x5c>
|
|
|
8001c8e: 693b ldr r3, [r7, #16]
|
|
|
8001c90: 2b03 cmp r3, #3
|
|
|
8001c92: d00e beq.n 8001cb2 <RTC_DateUpdate+0x5c>
|
|
|
8001c94: 693b ldr r3, [r7, #16]
|
|
|
8001c96: 2b05 cmp r3, #5
|
|
|
8001c98: d00b beq.n 8001cb2 <RTC_DateUpdate+0x5c>
|
|
|
8001c9a: 693b ldr r3, [r7, #16]
|
|
|
8001c9c: 2b07 cmp r3, #7
|
|
|
8001c9e: d008 beq.n 8001cb2 <RTC_DateUpdate+0x5c>
|
|
|
8001ca0: 693b ldr r3, [r7, #16]
|
|
|
8001ca2: 2b08 cmp r3, #8
|
|
|
8001ca4: d005 beq.n 8001cb2 <RTC_DateUpdate+0x5c>
|
|
|
(month == 8U) || (month == 10U) || (month == 12U))
|
|
|
8001ca6: 693b ldr r3, [r7, #16]
|
|
|
8001ca8: 2b0a cmp r3, #10
|
|
|
8001caa: d002 beq.n 8001cb2 <RTC_DateUpdate+0x5c>
|
|
|
8001cac: 693b ldr r3, [r7, #16]
|
|
|
8001cae: 2b0c cmp r3, #12
|
|
|
8001cb0: d117 bne.n 8001ce2 <RTC_DateUpdate+0x8c>
|
|
|
{
|
|
|
if (day < 31U)
|
|
|
8001cb2: 68fb ldr r3, [r7, #12]
|
|
|
8001cb4: 2b1e cmp r3, #30
|
|
|
8001cb6: d803 bhi.n 8001cc0 <RTC_DateUpdate+0x6a>
|
|
|
{
|
|
|
day++;
|
|
|
8001cb8: 68fb ldr r3, [r7, #12]
|
|
|
8001cba: 3301 adds r3, #1
|
|
|
8001cbc: 60fb str r3, [r7, #12]
|
|
|
if (day < 31U)
|
|
|
8001cbe: e050 b.n 8001d62 <RTC_DateUpdate+0x10c>
|
|
|
}
|
|
|
/* Date structure member: day = 31 */
|
|
|
else
|
|
|
{
|
|
|
if (month != 12U)
|
|
|
8001cc0: 693b ldr r3, [r7, #16]
|
|
|
8001cc2: 2b0c cmp r3, #12
|
|
|
8001cc4: d005 beq.n 8001cd2 <RTC_DateUpdate+0x7c>
|
|
|
{
|
|
|
month++;
|
|
|
8001cc6: 693b ldr r3, [r7, #16]
|
|
|
8001cc8: 3301 adds r3, #1
|
|
|
8001cca: 613b str r3, [r7, #16]
|
|
|
day = 1U;
|
|
|
8001ccc: 2301 movs r3, #1
|
|
|
8001cce: 60fb str r3, [r7, #12]
|
|
|
if (day < 31U)
|
|
|
8001cd0: e047 b.n 8001d62 <RTC_DateUpdate+0x10c>
|
|
|
}
|
|
|
/* Date structure member: day = 31 & month =12 */
|
|
|
else
|
|
|
{
|
|
|
month = 1U;
|
|
|
8001cd2: 2301 movs r3, #1
|
|
|
8001cd4: 613b str r3, [r7, #16]
|
|
|
day = 1U;
|
|
|
8001cd6: 2301 movs r3, #1
|
|
|
8001cd8: 60fb str r3, [r7, #12]
|
|
|
year++;
|
|
|
8001cda: 697b ldr r3, [r7, #20]
|
|
|
8001cdc: 3301 adds r3, #1
|
|
|
8001cde: 617b str r3, [r7, #20]
|
|
|
if (day < 31U)
|
|
|
8001ce0: e03f b.n 8001d62 <RTC_DateUpdate+0x10c>
|
|
|
}
|
|
|
}
|
|
|
}
|
|
|
else if ((month == 4U) || (month == 6U) || (month == 9U) || (month == 11U))
|
|
|
8001ce2: 693b ldr r3, [r7, #16]
|
|
|
8001ce4: 2b04 cmp r3, #4
|
|
|
8001ce6: d008 beq.n 8001cfa <RTC_DateUpdate+0xa4>
|
|
|
8001ce8: 693b ldr r3, [r7, #16]
|
|
|
8001cea: 2b06 cmp r3, #6
|
|
|
8001cec: d005 beq.n 8001cfa <RTC_DateUpdate+0xa4>
|
|
|
8001cee: 693b ldr r3, [r7, #16]
|
|
|
8001cf0: 2b09 cmp r3, #9
|
|
|
8001cf2: d002 beq.n 8001cfa <RTC_DateUpdate+0xa4>
|
|
|
8001cf4: 693b ldr r3, [r7, #16]
|
|
|
8001cf6: 2b0b cmp r3, #11
|
|
|
8001cf8: d10c bne.n 8001d14 <RTC_DateUpdate+0xbe>
|
|
|
{
|
|
|
if (day < 30U)
|
|
|
8001cfa: 68fb ldr r3, [r7, #12]
|
|
|
8001cfc: 2b1d cmp r3, #29
|
|
|
8001cfe: d803 bhi.n 8001d08 <RTC_DateUpdate+0xb2>
|
|
|
{
|
|
|
day++;
|
|
|
8001d00: 68fb ldr r3, [r7, #12]
|
|
|
8001d02: 3301 adds r3, #1
|
|
|
8001d04: 60fb str r3, [r7, #12]
|
|
|
if (day < 30U)
|
|
|
8001d06: e02c b.n 8001d62 <RTC_DateUpdate+0x10c>
|
|
|
}
|
|
|
/* Date structure member: day = 30 */
|
|
|
else
|
|
|
{
|
|
|
month++;
|
|
|
8001d08: 693b ldr r3, [r7, #16]
|
|
|
8001d0a: 3301 adds r3, #1
|
|
|
8001d0c: 613b str r3, [r7, #16]
|
|
|
day = 1U;
|
|
|
8001d0e: 2301 movs r3, #1
|
|
|
8001d10: 60fb str r3, [r7, #12]
|
|
|
if (day < 30U)
|
|
|
8001d12: e026 b.n 8001d62 <RTC_DateUpdate+0x10c>
|
|
|
}
|
|
|
}
|
|
|
else if (month == 2U)
|
|
|
8001d14: 693b ldr r3, [r7, #16]
|
|
|
8001d16: 2b02 cmp r3, #2
|
|
|
8001d18: d123 bne.n 8001d62 <RTC_DateUpdate+0x10c>
|
|
|
{
|
|
|
if (day < 28U)
|
|
|
8001d1a: 68fb ldr r3, [r7, #12]
|
|
|
8001d1c: 2b1b cmp r3, #27
|
|
|
8001d1e: d803 bhi.n 8001d28 <RTC_DateUpdate+0xd2>
|
|
|
{
|
|
|
day++;
|
|
|
8001d20: 68fb ldr r3, [r7, #12]
|
|
|
8001d22: 3301 adds r3, #1
|
|
|
8001d24: 60fb str r3, [r7, #12]
|
|
|
8001d26: e01c b.n 8001d62 <RTC_DateUpdate+0x10c>
|
|
|
}
|
|
|
else if (day == 28U)
|
|
|
8001d28: 68fb ldr r3, [r7, #12]
|
|
|
8001d2a: 2b1c cmp r3, #28
|
|
|
8001d2c: d111 bne.n 8001d52 <RTC_DateUpdate+0xfc>
|
|
|
{
|
|
|
/* Leap year */
|
|
|
if (RTC_IsLeapYear(year))
|
|
|
8001d2e: 697b ldr r3, [r7, #20]
|
|
|
8001d30: b29b uxth r3, r3
|
|
|
8001d32: 4618 mov r0, r3
|
|
|
8001d34: f000 f838 bl 8001da8 <RTC_IsLeapYear>
|
|
|
8001d38: 4603 mov r3, r0
|
|
|
8001d3a: 2b00 cmp r3, #0
|
|
|
8001d3c: d003 beq.n 8001d46 <RTC_DateUpdate+0xf0>
|
|
|
{
|
|
|
day++;
|
|
|
8001d3e: 68fb ldr r3, [r7, #12]
|
|
|
8001d40: 3301 adds r3, #1
|
|
|
8001d42: 60fb str r3, [r7, #12]
|
|
|
8001d44: e00d b.n 8001d62 <RTC_DateUpdate+0x10c>
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
month++;
|
|
|
8001d46: 693b ldr r3, [r7, #16]
|
|
|
8001d48: 3301 adds r3, #1
|
|
|
8001d4a: 613b str r3, [r7, #16]
|
|
|
day = 1U;
|
|
|
8001d4c: 2301 movs r3, #1
|
|
|
8001d4e: 60fb str r3, [r7, #12]
|
|
|
8001d50: e007 b.n 8001d62 <RTC_DateUpdate+0x10c>
|
|
|
}
|
|
|
}
|
|
|
else if (day == 29U)
|
|
|
8001d52: 68fb ldr r3, [r7, #12]
|
|
|
8001d54: 2b1d cmp r3, #29
|
|
|
8001d56: d104 bne.n 8001d62 <RTC_DateUpdate+0x10c>
|
|
|
{
|
|
|
month++;
|
|
|
8001d58: 693b ldr r3, [r7, #16]
|
|
|
8001d5a: 3301 adds r3, #1
|
|
|
8001d5c: 613b str r3, [r7, #16]
|
|
|
day = 1U;
|
|
|
8001d5e: 2301 movs r3, #1
|
|
|
8001d60: 60fb str r3, [r7, #12]
|
|
|
for (loop = 0U; loop < DayElapsed; loop++)
|
|
|
8001d62: 68bb ldr r3, [r7, #8]
|
|
|
8001d64: 3301 adds r3, #1
|
|
|
8001d66: 60bb str r3, [r7, #8]
|
|
|
8001d68: 68ba ldr r2, [r7, #8]
|
|
|
8001d6a: 683b ldr r3, [r7, #0]
|
|
|
8001d6c: 429a cmp r2, r3
|
|
|
8001d6e: d38b bcc.n 8001c88 <RTC_DateUpdate+0x32>
|
|
|
}
|
|
|
}
|
|
|
}
|
|
|
|
|
|
/* Update year */
|
|
|
hrtc->DateToUpdate.Year = year;
|
|
|
8001d70: 697b ldr r3, [r7, #20]
|
|
|
8001d72: b2da uxtb r2, r3
|
|
|
8001d74: 687b ldr r3, [r7, #4]
|
|
|
8001d76: 73da strb r2, [r3, #15]
|
|
|
|
|
|
/* Update day and month */
|
|
|
hrtc->DateToUpdate.Month = month;
|
|
|
8001d78: 693b ldr r3, [r7, #16]
|
|
|
8001d7a: b2da uxtb r2, r3
|
|
|
8001d7c: 687b ldr r3, [r7, #4]
|
|
|
8001d7e: 735a strb r2, [r3, #13]
|
|
|
hrtc->DateToUpdate.Date = day;
|
|
|
8001d80: 68fb ldr r3, [r7, #12]
|
|
|
8001d82: b2da uxtb r2, r3
|
|
|
8001d84: 687b ldr r3, [r7, #4]
|
|
|
8001d86: 739a strb r2, [r3, #14]
|
|
|
|
|
|
/* Update day of the week */
|
|
|
hrtc->DateToUpdate.WeekDay = RTC_WeekDayNum(year, month, day);
|
|
|
8001d88: 693b ldr r3, [r7, #16]
|
|
|
8001d8a: b2db uxtb r3, r3
|
|
|
8001d8c: 68fa ldr r2, [r7, #12]
|
|
|
8001d8e: b2d2 uxtb r2, r2
|
|
|
8001d90: 4619 mov r1, r3
|
|
|
8001d92: 6978 ldr r0, [r7, #20]
|
|
|
8001d94: f000 f83a bl 8001e0c <RTC_WeekDayNum>
|
|
|
8001d98: 4603 mov r3, r0
|
|
|
8001d9a: 461a mov r2, r3
|
|
|
8001d9c: 687b ldr r3, [r7, #4]
|
|
|
8001d9e: 731a strb r2, [r3, #12]
|
|
|
}
|
|
|
8001da0: bf00 nop
|
|
|
8001da2: 3718 adds r7, #24
|
|
|
8001da4: 46bd mov sp, r7
|
|
|
8001da6: bd80 pop {r7, pc}
|
|
|
|
|
|
08001da8 <RTC_IsLeapYear>:
|
|
|
* @param nYear year to check
|
|
|
* @retval 1: leap year
|
|
|
* 0: not leap year
|
|
|
*/
|
|
|
static uint8_t RTC_IsLeapYear(uint16_t nYear)
|
|
|
{
|
|
|
8001da8: b480 push {r7}
|
|
|
8001daa: b083 sub sp, #12
|
|
|
8001dac: af00 add r7, sp, #0
|
|
|
8001dae: 4603 mov r3, r0
|
|
|
8001db0: 80fb strh r3, [r7, #6]
|
|
|
if ((nYear % 4U) != 0U)
|
|
|
8001db2: 88fb ldrh r3, [r7, #6]
|
|
|
8001db4: f003 0303 and.w r3, r3, #3
|
|
|
8001db8: b29b uxth r3, r3
|
|
|
8001dba: 2b00 cmp r3, #0
|
|
|
8001dbc: d001 beq.n 8001dc2 <RTC_IsLeapYear+0x1a>
|
|
|
{
|
|
|
return 0U;
|
|
|
8001dbe: 2300 movs r3, #0
|
|
|
8001dc0: e01d b.n 8001dfe <RTC_IsLeapYear+0x56>
|
|
|
}
|
|
|
|
|
|
if ((nYear % 100U) != 0U)
|
|
|
8001dc2: 88fb ldrh r3, [r7, #6]
|
|
|
8001dc4: 4a10 ldr r2, [pc, #64] ; (8001e08 <RTC_IsLeapYear+0x60>)
|
|
|
8001dc6: fba2 1203 umull r1, r2, r2, r3
|
|
|
8001dca: 0952 lsrs r2, r2, #5
|
|
|
8001dcc: 2164 movs r1, #100 ; 0x64
|
|
|
8001dce: fb01 f202 mul.w r2, r1, r2
|
|
|
8001dd2: 1a9b subs r3, r3, r2
|
|
|
8001dd4: b29b uxth r3, r3
|
|
|
8001dd6: 2b00 cmp r3, #0
|
|
|
8001dd8: d001 beq.n 8001dde <RTC_IsLeapYear+0x36>
|
|
|
{
|
|
|
return 1U;
|
|
|
8001dda: 2301 movs r3, #1
|
|
|
8001ddc: e00f b.n 8001dfe <RTC_IsLeapYear+0x56>
|
|
|
}
|
|
|
|
|
|
if ((nYear % 400U) == 0U)
|
|
|
8001dde: 88fb ldrh r3, [r7, #6]
|
|
|
8001de0: 4a09 ldr r2, [pc, #36] ; (8001e08 <RTC_IsLeapYear+0x60>)
|
|
|
8001de2: fba2 1203 umull r1, r2, r2, r3
|
|
|
8001de6: 09d2 lsrs r2, r2, #7
|
|
|
8001de8: f44f 71c8 mov.w r1, #400 ; 0x190
|
|
|
8001dec: fb01 f202 mul.w r2, r1, r2
|
|
|
8001df0: 1a9b subs r3, r3, r2
|
|
|
8001df2: b29b uxth r3, r3
|
|
|
8001df4: 2b00 cmp r3, #0
|
|
|
8001df6: d101 bne.n 8001dfc <RTC_IsLeapYear+0x54>
|
|
|
{
|
|
|
return 1U;
|
|
|
8001df8: 2301 movs r3, #1
|
|
|
8001dfa: e000 b.n 8001dfe <RTC_IsLeapYear+0x56>
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
return 0U;
|
|
|
8001dfc: 2300 movs r3, #0
|
|
|
}
|
|
|
}
|
|
|
8001dfe: 4618 mov r0, r3
|
|
|
8001e00: 370c adds r7, #12
|
|
|
8001e02: 46bd mov sp, r7
|
|
|
8001e04: bc80 pop {r7}
|
|
|
8001e06: 4770 bx lr
|
|
|
8001e08: 51eb851f .word 0x51eb851f
|
|
|
|
|
|
08001e0c <RTC_WeekDayNum>:
|
|
|
* @arg RTC_WEEKDAY_FRIDAY
|
|
|
* @arg RTC_WEEKDAY_SATURDAY
|
|
|
* @arg RTC_WEEKDAY_SUNDAY
|
|
|
*/
|
|
|
static uint8_t RTC_WeekDayNum(uint32_t nYear, uint8_t nMonth, uint8_t nDay)
|
|
|
{
|
|
|
8001e0c: b480 push {r7}
|
|
|
8001e0e: b085 sub sp, #20
|
|
|
8001e10: af00 add r7, sp, #0
|
|
|
8001e12: 6078 str r0, [r7, #4]
|
|
|
8001e14: 460b mov r3, r1
|
|
|
8001e16: 70fb strb r3, [r7, #3]
|
|
|
8001e18: 4613 mov r3, r2
|
|
|
8001e1a: 70bb strb r3, [r7, #2]
|
|
|
uint32_t year = 0U, weekday = 0U;
|
|
|
8001e1c: 2300 movs r3, #0
|
|
|
8001e1e: 60bb str r3, [r7, #8]
|
|
|
8001e20: 2300 movs r3, #0
|
|
|
8001e22: 60fb str r3, [r7, #12]
|
|
|
|
|
|
year = 2000U + nYear;
|
|
|
8001e24: 687b ldr r3, [r7, #4]
|
|
|
8001e26: f503 63fa add.w r3, r3, #2000 ; 0x7d0
|
|
|
8001e2a: 60bb str r3, [r7, #8]
|
|
|
|
|
|
if (nMonth < 3U)
|
|
|
8001e2c: 78fb ldrb r3, [r7, #3]
|
|
|
8001e2e: 2b02 cmp r3, #2
|
|
|
8001e30: d82d bhi.n 8001e8e <RTC_WeekDayNum+0x82>
|
|
|
{
|
|
|
/*D = { [(23 x month)/9] + day + 4 + year + [(year-1)/4] - [(year-1)/100] + [(year-1)/400] } mod 7*/
|
|
|
weekday = (((23U * nMonth) / 9U) + nDay + 4U + year + ((year - 1U) / 4U) - ((year - 1U) / 100U) + ((year - 1U) / 400U)) % 7U;
|
|
|
8001e32: 78fa ldrb r2, [r7, #3]
|
|
|
8001e34: 4613 mov r3, r2
|
|
|
8001e36: 005b lsls r3, r3, #1
|
|
|
8001e38: 4413 add r3, r2
|
|
|
8001e3a: 00db lsls r3, r3, #3
|
|
|
8001e3c: 1a9b subs r3, r3, r2
|
|
|
8001e3e: 4a2c ldr r2, [pc, #176] ; (8001ef0 <RTC_WeekDayNum+0xe4>)
|
|
|
8001e40: fba2 2303 umull r2, r3, r2, r3
|
|
|
8001e44: 085a lsrs r2, r3, #1
|
|
|
8001e46: 78bb ldrb r3, [r7, #2]
|
|
|
8001e48: 441a add r2, r3
|
|
|
8001e4a: 68bb ldr r3, [r7, #8]
|
|
|
8001e4c: 441a add r2, r3
|
|
|
8001e4e: 68bb ldr r3, [r7, #8]
|
|
|
8001e50: 3b01 subs r3, #1
|
|
|
8001e52: 089b lsrs r3, r3, #2
|
|
|
8001e54: 441a add r2, r3
|
|
|
8001e56: 68bb ldr r3, [r7, #8]
|
|
|
8001e58: 3b01 subs r3, #1
|
|
|
8001e5a: 4926 ldr r1, [pc, #152] ; (8001ef4 <RTC_WeekDayNum+0xe8>)
|
|
|
8001e5c: fba1 1303 umull r1, r3, r1, r3
|
|
|
8001e60: 095b lsrs r3, r3, #5
|
|
|
8001e62: 1ad2 subs r2, r2, r3
|
|
|
8001e64: 68bb ldr r3, [r7, #8]
|
|
|
8001e66: 3b01 subs r3, #1
|
|
|
8001e68: 4922 ldr r1, [pc, #136] ; (8001ef4 <RTC_WeekDayNum+0xe8>)
|
|
|
8001e6a: fba1 1303 umull r1, r3, r1, r3
|
|
|
8001e6e: 09db lsrs r3, r3, #7
|
|
|
8001e70: 4413 add r3, r2
|
|
|
8001e72: 1d1a adds r2, r3, #4
|
|
|
8001e74: 4b20 ldr r3, [pc, #128] ; (8001ef8 <RTC_WeekDayNum+0xec>)
|
|
|
8001e76: fba3 1302 umull r1, r3, r3, r2
|
|
|
8001e7a: 1ad1 subs r1, r2, r3
|
|
|
8001e7c: 0849 lsrs r1, r1, #1
|
|
|
8001e7e: 440b add r3, r1
|
|
|
8001e80: 0899 lsrs r1, r3, #2
|
|
|
8001e82: 460b mov r3, r1
|
|
|
8001e84: 00db lsls r3, r3, #3
|
|
|
8001e86: 1a5b subs r3, r3, r1
|
|
|
8001e88: 1ad3 subs r3, r2, r3
|
|
|
8001e8a: 60fb str r3, [r7, #12]
|
|
|
8001e8c: e029 b.n 8001ee2 <RTC_WeekDayNum+0xd6>
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
/*D = { [(23 x month)/9] + day + 4 + year + [year/4] - [year/100] + [year/400] - 2 } mod 7*/
|
|
|
weekday = (((23U * nMonth) / 9U) + nDay + 4U + year + (year / 4U) - (year / 100U) + (year / 400U) - 2U) % 7U;
|
|
|
8001e8e: 78fa ldrb r2, [r7, #3]
|
|
|
8001e90: 4613 mov r3, r2
|
|
|
8001e92: 005b lsls r3, r3, #1
|
|
|
8001e94: 4413 add r3, r2
|
|
|
8001e96: 00db lsls r3, r3, #3
|
|
|
8001e98: 1a9b subs r3, r3, r2
|
|
|
8001e9a: 4a15 ldr r2, [pc, #84] ; (8001ef0 <RTC_WeekDayNum+0xe4>)
|
|
|
8001e9c: fba2 2303 umull r2, r3, r2, r3
|
|
|
8001ea0: 085a lsrs r2, r3, #1
|
|
|
8001ea2: 78bb ldrb r3, [r7, #2]
|
|
|
8001ea4: 441a add r2, r3
|
|
|
8001ea6: 68bb ldr r3, [r7, #8]
|
|
|
8001ea8: 441a add r2, r3
|
|
|
8001eaa: 68bb ldr r3, [r7, #8]
|
|
|
8001eac: 089b lsrs r3, r3, #2
|
|
|
8001eae: 441a add r2, r3
|
|
|
8001eb0: 68bb ldr r3, [r7, #8]
|
|
|
8001eb2: 4910 ldr r1, [pc, #64] ; (8001ef4 <RTC_WeekDayNum+0xe8>)
|
|
|
8001eb4: fba1 1303 umull r1, r3, r1, r3
|
|
|
8001eb8: 095b lsrs r3, r3, #5
|
|
|
8001eba: 1ad2 subs r2, r2, r3
|
|
|
8001ebc: 68bb ldr r3, [r7, #8]
|
|
|
8001ebe: 490d ldr r1, [pc, #52] ; (8001ef4 <RTC_WeekDayNum+0xe8>)
|
|
|
8001ec0: fba1 1303 umull r1, r3, r1, r3
|
|
|
8001ec4: 09db lsrs r3, r3, #7
|
|
|
8001ec6: 4413 add r3, r2
|
|
|
8001ec8: 1c9a adds r2, r3, #2
|
|
|
8001eca: 4b0b ldr r3, [pc, #44] ; (8001ef8 <RTC_WeekDayNum+0xec>)
|
|
|
8001ecc: fba3 1302 umull r1, r3, r3, r2
|
|
|
8001ed0: 1ad1 subs r1, r2, r3
|
|
|
8001ed2: 0849 lsrs r1, r1, #1
|
|
|
8001ed4: 440b add r3, r1
|
|
|
8001ed6: 0899 lsrs r1, r3, #2
|
|
|
8001ed8: 460b mov r3, r1
|
|
|
8001eda: 00db lsls r3, r3, #3
|
|
|
8001edc: 1a5b subs r3, r3, r1
|
|
|
8001ede: 1ad3 subs r3, r2, r3
|
|
|
8001ee0: 60fb str r3, [r7, #12]
|
|
|
}
|
|
|
|
|
|
return (uint8_t)weekday;
|
|
|
8001ee2: 68fb ldr r3, [r7, #12]
|
|
|
8001ee4: b2db uxtb r3, r3
|
|
|
}
|
|
|
8001ee6: 4618 mov r0, r3
|
|
|
8001ee8: 3714 adds r7, #20
|
|
|
8001eea: 46bd mov sp, r7
|
|
|
8001eec: bc80 pop {r7}
|
|
|
8001eee: 4770 bx lr
|
|
|
8001ef0: 38e38e39 .word 0x38e38e39
|
|
|
8001ef4: 51eb851f .word 0x51eb851f
|
|
|
8001ef8: 24924925 .word 0x24924925
|
|
|
|
|
|
08001efc <HAL_UART_Init>:
|
|
|
* @param huart Pointer to a UART_HandleTypeDef structure that contains
|
|
|
* the configuration information for the specified UART module.
|
|
|
* @retval HAL status
|
|
|
*/
|
|
|
HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
|
|
|
{
|
|
|
8001efc: b580 push {r7, lr}
|
|
|
8001efe: b082 sub sp, #8
|
|
|
8001f00: af00 add r7, sp, #0
|
|
|
8001f02: 6078 str r0, [r7, #4]
|
|
|
/* Check the UART handle allocation */
|
|
|
if (huart == NULL)
|
|
|
8001f04: 687b ldr r3, [r7, #4]
|
|
|
8001f06: 2b00 cmp r3, #0
|
|
|
8001f08: d101 bne.n 8001f0e <HAL_UART_Init+0x12>
|
|
|
{
|
|
|
return HAL_ERROR;
|
|
|
8001f0a: 2301 movs r3, #1
|
|
|
8001f0c: e03f b.n 8001f8e <HAL_UART_Init+0x92>
|
|
|
assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));
|
|
|
#if defined(USART_CR1_OVER8)
|
|
|
assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling));
|
|
|
#endif /* USART_CR1_OVER8 */
|
|
|
|
|
|
if (huart->gState == HAL_UART_STATE_RESET)
|
|
|
8001f0e: 687b ldr r3, [r7, #4]
|
|
|
8001f10: f893 303d ldrb.w r3, [r3, #61] ; 0x3d
|
|
|
8001f14: b2db uxtb r3, r3
|
|
|
8001f16: 2b00 cmp r3, #0
|
|
|
8001f18: d106 bne.n 8001f28 <HAL_UART_Init+0x2c>
|
|
|
{
|
|
|
/* Allocate lock resource and initialize it */
|
|
|
huart->Lock = HAL_UNLOCKED;
|
|
|
8001f1a: 687b ldr r3, [r7, #4]
|
|
|
8001f1c: 2200 movs r2, #0
|
|
|
8001f1e: f883 203c strb.w r2, [r3, #60] ; 0x3c
|
|
|
|
|
|
/* Init the low level hardware */
|
|
|
huart->MspInitCallback(huart);
|
|
|
#else
|
|
|
/* Init the low level hardware : GPIO, CLOCK */
|
|
|
HAL_UART_MspInit(huart);
|
|
|
8001f22: 6878 ldr r0, [r7, #4]
|
|
|
8001f24: f7fe fafe bl 8000524 <HAL_UART_MspInit>
|
|
|
#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
|
|
|
}
|
|
|
|
|
|
huart->gState = HAL_UART_STATE_BUSY;
|
|
|
8001f28: 687b ldr r3, [r7, #4]
|
|
|
8001f2a: 2224 movs r2, #36 ; 0x24
|
|
|
8001f2c: f883 203d strb.w r2, [r3, #61] ; 0x3d
|
|
|
|
|
|
/* Disable the peripheral */
|
|
|
__HAL_UART_DISABLE(huart);
|
|
|
8001f30: 687b ldr r3, [r7, #4]
|
|
|
8001f32: 681b ldr r3, [r3, #0]
|
|
|
8001f34: 68da ldr r2, [r3, #12]
|
|
|
8001f36: 687b ldr r3, [r7, #4]
|
|
|
8001f38: 681b ldr r3, [r3, #0]
|
|
|
8001f3a: f422 5200 bic.w r2, r2, #8192 ; 0x2000
|
|
|
8001f3e: 60da str r2, [r3, #12]
|
|
|
|
|
|
/* Set the UART Communication parameters */
|
|
|
UART_SetConfig(huart);
|
|
|
8001f40: 6878 ldr r0, [r7, #4]
|
|
|
8001f42: f000 f905 bl 8002150 <UART_SetConfig>
|
|
|
|
|
|
/* In asynchronous mode, the following bits must be kept cleared:
|
|
|
- LINEN and CLKEN bits in the USART_CR2 register,
|
|
|
- SCEN, HDSEL and IREN bits in the USART_CR3 register.*/
|
|
|
CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
|
|
|
8001f46: 687b ldr r3, [r7, #4]
|
|
|
8001f48: 681b ldr r3, [r3, #0]
|
|
|
8001f4a: 691a ldr r2, [r3, #16]
|
|
|
8001f4c: 687b ldr r3, [r7, #4]
|
|
|
8001f4e: 681b ldr r3, [r3, #0]
|
|
|
8001f50: f422 4290 bic.w r2, r2, #18432 ; 0x4800
|
|
|
8001f54: 611a str r2, [r3, #16]
|
|
|
CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
|
|
|
8001f56: 687b ldr r3, [r7, #4]
|
|
|
8001f58: 681b ldr r3, [r3, #0]
|
|
|
8001f5a: 695a ldr r2, [r3, #20]
|
|
|
8001f5c: 687b ldr r3, [r7, #4]
|
|
|
8001f5e: 681b ldr r3, [r3, #0]
|
|
|
8001f60: f022 022a bic.w r2, r2, #42 ; 0x2a
|
|
|
8001f64: 615a str r2, [r3, #20]
|
|
|
|
|
|
/* Enable the peripheral */
|
|
|
__HAL_UART_ENABLE(huart);
|
|
|
8001f66: 687b ldr r3, [r7, #4]
|
|
|
8001f68: 681b ldr r3, [r3, #0]
|
|
|
8001f6a: 68da ldr r2, [r3, #12]
|
|
|
8001f6c: 687b ldr r3, [r7, #4]
|
|
|
8001f6e: 681b ldr r3, [r3, #0]
|
|
|
8001f70: f442 5200 orr.w r2, r2, #8192 ; 0x2000
|
|
|
8001f74: 60da str r2, [r3, #12]
|
|
|
|
|
|
/* Initialize the UART state */
|
|
|
huart->ErrorCode = HAL_UART_ERROR_NONE;
|
|
|
8001f76: 687b ldr r3, [r7, #4]
|
|
|
8001f78: 2200 movs r2, #0
|
|
|
8001f7a: 641a str r2, [r3, #64] ; 0x40
|
|
|
huart->gState = HAL_UART_STATE_READY;
|
|
|
8001f7c: 687b ldr r3, [r7, #4]
|
|
|
8001f7e: 2220 movs r2, #32
|
|
|
8001f80: f883 203d strb.w r2, [r3, #61] ; 0x3d
|
|
|
huart->RxState = HAL_UART_STATE_READY;
|
|
|
8001f84: 687b ldr r3, [r7, #4]
|
|
|
8001f86: 2220 movs r2, #32
|
|
|
8001f88: f883 203e strb.w r2, [r3, #62] ; 0x3e
|
|
|
|
|
|
return HAL_OK;
|
|
|
8001f8c: 2300 movs r3, #0
|
|
|
}
|
|
|
8001f8e: 4618 mov r0, r3
|
|
|
8001f90: 3708 adds r7, #8
|
|
|
8001f92: 46bd mov sp, r7
|
|
|
8001f94: bd80 pop {r7, pc}
|
|
|
|
|
|
08001f96 <HAL_UART_Transmit>:
|
|
|
* @param Size Amount of data elements (u8 or u16) to be sent
|
|
|
* @param Timeout Timeout duration
|
|
|
* @retval HAL status
|
|
|
*/
|
|
|
HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
|
|
|
{
|
|
|
8001f96: b580 push {r7, lr}
|
|
|
8001f98: b08a sub sp, #40 ; 0x28
|
|
|
8001f9a: af02 add r7, sp, #8
|
|
|
8001f9c: 60f8 str r0, [r7, #12]
|
|
|
8001f9e: 60b9 str r1, [r7, #8]
|
|
|
8001fa0: 603b str r3, [r7, #0]
|
|
|
8001fa2: 4613 mov r3, r2
|
|
|
8001fa4: 80fb strh r3, [r7, #6]
|
|
|
uint8_t *pdata8bits;
|
|
|
uint16_t *pdata16bits;
|
|
|
uint32_t tickstart = 0U;
|
|
|
8001fa6: 2300 movs r3, #0
|
|
|
8001fa8: 617b str r3, [r7, #20]
|
|
|
|
|
|
/* Check that a Tx process is not already ongoing */
|
|
|
if (huart->gState == HAL_UART_STATE_READY)
|
|
|
8001faa: 68fb ldr r3, [r7, #12]
|
|
|
8001fac: f893 303d ldrb.w r3, [r3, #61] ; 0x3d
|
|
|
8001fb0: b2db uxtb r3, r3
|
|
|
8001fb2: 2b20 cmp r3, #32
|
|
|
8001fb4: d17c bne.n 80020b0 <HAL_UART_Transmit+0x11a>
|
|
|
{
|
|
|
if ((pData == NULL) || (Size == 0U))
|
|
|
8001fb6: 68bb ldr r3, [r7, #8]
|
|
|
8001fb8: 2b00 cmp r3, #0
|
|
|
8001fba: d002 beq.n 8001fc2 <HAL_UART_Transmit+0x2c>
|
|
|
8001fbc: 88fb ldrh r3, [r7, #6]
|
|
|
8001fbe: 2b00 cmp r3, #0
|
|
|
8001fc0: d101 bne.n 8001fc6 <HAL_UART_Transmit+0x30>
|
|
|
{
|
|
|
return HAL_ERROR;
|
|
|
8001fc2: 2301 movs r3, #1
|
|
|
8001fc4: e075 b.n 80020b2 <HAL_UART_Transmit+0x11c>
|
|
|
}
|
|
|
|
|
|
/* Process Locked */
|
|
|
__HAL_LOCK(huart);
|
|
|
8001fc6: 68fb ldr r3, [r7, #12]
|
|
|
8001fc8: f893 303c ldrb.w r3, [r3, #60] ; 0x3c
|
|
|
8001fcc: 2b01 cmp r3, #1
|
|
|
8001fce: d101 bne.n 8001fd4 <HAL_UART_Transmit+0x3e>
|
|
|
8001fd0: 2302 movs r3, #2
|
|
|
8001fd2: e06e b.n 80020b2 <HAL_UART_Transmit+0x11c>
|
|
|
8001fd4: 68fb ldr r3, [r7, #12]
|
|
|
8001fd6: 2201 movs r2, #1
|
|
|
8001fd8: f883 203c strb.w r2, [r3, #60] ; 0x3c
|
|
|
|
|
|
huart->ErrorCode = HAL_UART_ERROR_NONE;
|
|
|
8001fdc: 68fb ldr r3, [r7, #12]
|
|
|
8001fde: 2200 movs r2, #0
|
|
|
8001fe0: 641a str r2, [r3, #64] ; 0x40
|
|
|
huart->gState = HAL_UART_STATE_BUSY_TX;
|
|
|
8001fe2: 68fb ldr r3, [r7, #12]
|
|
|
8001fe4: 2221 movs r2, #33 ; 0x21
|
|
|
8001fe6: f883 203d strb.w r2, [r3, #61] ; 0x3d
|
|
|
|
|
|
/* Init tickstart for timeout management */
|
|
|
tickstart = HAL_GetTick();
|
|
|
8001fea: f7fe fb63 bl 80006b4 <HAL_GetTick>
|
|
|
8001fee: 6178 str r0, [r7, #20]
|
|
|
|
|
|
huart->TxXferSize = Size;
|
|
|
8001ff0: 68fb ldr r3, [r7, #12]
|
|
|
8001ff2: 88fa ldrh r2, [r7, #6]
|
|
|
8001ff4: 849a strh r2, [r3, #36] ; 0x24
|
|
|
huart->TxXferCount = Size;
|
|
|
8001ff6: 68fb ldr r3, [r7, #12]
|
|
|
8001ff8: 88fa ldrh r2, [r7, #6]
|
|
|
8001ffa: 84da strh r2, [r3, #38] ; 0x26
|
|
|
|
|
|
/* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */
|
|
|
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
|
|
|
8001ffc: 68fb ldr r3, [r7, #12]
|
|
|
8001ffe: 689b ldr r3, [r3, #8]
|
|
|
8002000: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
|
|
|
8002004: d108 bne.n 8002018 <HAL_UART_Transmit+0x82>
|
|
|
8002006: 68fb ldr r3, [r7, #12]
|
|
|
8002008: 691b ldr r3, [r3, #16]
|
|
|
800200a: 2b00 cmp r3, #0
|
|
|
800200c: d104 bne.n 8002018 <HAL_UART_Transmit+0x82>
|
|
|
{
|
|
|
pdata8bits = NULL;
|
|
|
800200e: 2300 movs r3, #0
|
|
|
8002010: 61fb str r3, [r7, #28]
|
|
|
pdata16bits = (uint16_t *) pData;
|
|
|
8002012: 68bb ldr r3, [r7, #8]
|
|
|
8002014: 61bb str r3, [r7, #24]
|
|
|
8002016: e003 b.n 8002020 <HAL_UART_Transmit+0x8a>
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
pdata8bits = pData;
|
|
|
8002018: 68bb ldr r3, [r7, #8]
|
|
|
800201a: 61fb str r3, [r7, #28]
|
|
|
pdata16bits = NULL;
|
|
|
800201c: 2300 movs r3, #0
|
|
|
800201e: 61bb str r3, [r7, #24]
|
|
|
}
|
|
|
|
|
|
/* Process Unlocked */
|
|
|
__HAL_UNLOCK(huart);
|
|
|
8002020: 68fb ldr r3, [r7, #12]
|
|
|
8002022: 2200 movs r2, #0
|
|
|
8002024: f883 203c strb.w r2, [r3, #60] ; 0x3c
|
|
|
|
|
|
while (huart->TxXferCount > 0U)
|
|
|
8002028: e02a b.n 8002080 <HAL_UART_Transmit+0xea>
|
|
|
{
|
|
|
if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
|
|
|
800202a: 683b ldr r3, [r7, #0]
|
|
|
800202c: 9300 str r3, [sp, #0]
|
|
|
800202e: 697b ldr r3, [r7, #20]
|
|
|
8002030: 2200 movs r2, #0
|
|
|
8002032: 2180 movs r1, #128 ; 0x80
|
|
|
8002034: 68f8 ldr r0, [r7, #12]
|
|
|
8002036: f000 f840 bl 80020ba <UART_WaitOnFlagUntilTimeout>
|
|
|
800203a: 4603 mov r3, r0
|
|
|
800203c: 2b00 cmp r3, #0
|
|
|
800203e: d001 beq.n 8002044 <HAL_UART_Transmit+0xae>
|
|
|
{
|
|
|
return HAL_TIMEOUT;
|
|
|
8002040: 2303 movs r3, #3
|
|
|
8002042: e036 b.n 80020b2 <HAL_UART_Transmit+0x11c>
|
|
|
}
|
|
|
if (pdata8bits == NULL)
|
|
|
8002044: 69fb ldr r3, [r7, #28]
|
|
|
8002046: 2b00 cmp r3, #0
|
|
|
8002048: d10b bne.n 8002062 <HAL_UART_Transmit+0xcc>
|
|
|
{
|
|
|
huart->Instance->DR = (uint16_t)(*pdata16bits & 0x01FFU);
|
|
|
800204a: 69bb ldr r3, [r7, #24]
|
|
|
800204c: 881b ldrh r3, [r3, #0]
|
|
|
800204e: 461a mov r2, r3
|
|
|
8002050: 68fb ldr r3, [r7, #12]
|
|
|
8002052: 681b ldr r3, [r3, #0]
|
|
|
8002054: f3c2 0208 ubfx r2, r2, #0, #9
|
|
|
8002058: 605a str r2, [r3, #4]
|
|
|
pdata16bits++;
|
|
|
800205a: 69bb ldr r3, [r7, #24]
|
|
|
800205c: 3302 adds r3, #2
|
|
|
800205e: 61bb str r3, [r7, #24]
|
|
|
8002060: e007 b.n 8002072 <HAL_UART_Transmit+0xdc>
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
huart->Instance->DR = (uint8_t)(*pdata8bits & 0xFFU);
|
|
|
8002062: 69fb ldr r3, [r7, #28]
|
|
|
8002064: 781a ldrb r2, [r3, #0]
|
|
|
8002066: 68fb ldr r3, [r7, #12]
|
|
|
8002068: 681b ldr r3, [r3, #0]
|
|
|
800206a: 605a str r2, [r3, #4]
|
|
|
pdata8bits++;
|
|
|
800206c: 69fb ldr r3, [r7, #28]
|
|
|
800206e: 3301 adds r3, #1
|
|
|
8002070: 61fb str r3, [r7, #28]
|
|
|
}
|
|
|
huart->TxXferCount--;
|
|
|
8002072: 68fb ldr r3, [r7, #12]
|
|
|
8002074: 8cdb ldrh r3, [r3, #38] ; 0x26
|
|
|
8002076: b29b uxth r3, r3
|
|
|
8002078: 3b01 subs r3, #1
|
|
|
800207a: b29a uxth r2, r3
|
|
|
800207c: 68fb ldr r3, [r7, #12]
|
|
|
800207e: 84da strh r2, [r3, #38] ; 0x26
|
|
|
while (huart->TxXferCount > 0U)
|
|
|
8002080: 68fb ldr r3, [r7, #12]
|
|
|
8002082: 8cdb ldrh r3, [r3, #38] ; 0x26
|
|
|
8002084: b29b uxth r3, r3
|
|
|
8002086: 2b00 cmp r3, #0
|
|
|
8002088: d1cf bne.n 800202a <HAL_UART_Transmit+0x94>
|
|
|
}
|
|
|
|
|
|
if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
|
|
|
800208a: 683b ldr r3, [r7, #0]
|
|
|
800208c: 9300 str r3, [sp, #0]
|
|
|
800208e: 697b ldr r3, [r7, #20]
|
|
|
8002090: 2200 movs r2, #0
|
|
|
8002092: 2140 movs r1, #64 ; 0x40
|
|
|
8002094: 68f8 ldr r0, [r7, #12]
|
|
|
8002096: f000 f810 bl 80020ba <UART_WaitOnFlagUntilTimeout>
|
|
|
800209a: 4603 mov r3, r0
|
|
|
800209c: 2b00 cmp r3, #0
|
|
|
800209e: d001 beq.n 80020a4 <HAL_UART_Transmit+0x10e>
|
|
|
{
|
|
|
return HAL_TIMEOUT;
|
|
|
80020a0: 2303 movs r3, #3
|
|
|
80020a2: e006 b.n 80020b2 <HAL_UART_Transmit+0x11c>
|
|
|
}
|
|
|
|
|
|
/* At end of Tx process, restore huart->gState to Ready */
|
|
|
huart->gState = HAL_UART_STATE_READY;
|
|
|
80020a4: 68fb ldr r3, [r7, #12]
|
|
|
80020a6: 2220 movs r2, #32
|
|
|
80020a8: f883 203d strb.w r2, [r3, #61] ; 0x3d
|
|
|
|
|
|
return HAL_OK;
|
|
|
80020ac: 2300 movs r3, #0
|
|
|
80020ae: e000 b.n 80020b2 <HAL_UART_Transmit+0x11c>
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
return HAL_BUSY;
|
|
|
80020b0: 2302 movs r3, #2
|
|
|
}
|
|
|
}
|
|
|
80020b2: 4618 mov r0, r3
|
|
|
80020b4: 3720 adds r7, #32
|
|
|
80020b6: 46bd mov sp, r7
|
|
|
80020b8: bd80 pop {r7, pc}
|
|
|
|
|
|
080020ba <UART_WaitOnFlagUntilTimeout>:
|
|
|
* @param Tickstart Tick start value
|
|
|
* @param Timeout Timeout duration
|
|
|
* @retval HAL status
|
|
|
*/
|
|
|
static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
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{
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80020ba: b580 push {r7, lr}
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80020bc: b084 sub sp, #16
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80020be: af00 add r7, sp, #0
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80020c0: 60f8 str r0, [r7, #12]
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80020c2: 60b9 str r1, [r7, #8]
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80020c4: 603b str r3, [r7, #0]
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80020c6: 4613 mov r3, r2
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80020c8: 71fb strb r3, [r7, #7]
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/* Wait until flag is set */
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while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
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80020ca: e02c b.n 8002126 <UART_WaitOnFlagUntilTimeout+0x6c>
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{
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/* Check for the Timeout */
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if (Timeout != HAL_MAX_DELAY)
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80020cc: 69bb ldr r3, [r7, #24]
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80020ce: f1b3 3fff cmp.w r3, #4294967295
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80020d2: d028 beq.n 8002126 <UART_WaitOnFlagUntilTimeout+0x6c>
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{
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if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout))
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80020d4: 69bb ldr r3, [r7, #24]
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80020d6: 2b00 cmp r3, #0
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80020d8: d007 beq.n 80020ea <UART_WaitOnFlagUntilTimeout+0x30>
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80020da: f7fe faeb bl 80006b4 <HAL_GetTick>
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80020de: 4602 mov r2, r0
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80020e0: 683b ldr r3, [r7, #0]
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80020e2: 1ad3 subs r3, r2, r3
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80020e4: 69ba ldr r2, [r7, #24]
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80020e6: 429a cmp r2, r3
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80020e8: d21d bcs.n 8002126 <UART_WaitOnFlagUntilTimeout+0x6c>
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{
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/* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
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CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
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80020ea: 68fb ldr r3, [r7, #12]
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80020ec: 681b ldr r3, [r3, #0]
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80020ee: 68da ldr r2, [r3, #12]
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80020f0: 68fb ldr r3, [r7, #12]
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80020f2: 681b ldr r3, [r3, #0]
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80020f4: f422 72d0 bic.w r2, r2, #416 ; 0x1a0
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80020f8: 60da str r2, [r3, #12]
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CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
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80020fa: 68fb ldr r3, [r7, #12]
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80020fc: 681b ldr r3, [r3, #0]
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80020fe: 695a ldr r2, [r3, #20]
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8002100: 68fb ldr r3, [r7, #12]
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8002102: 681b ldr r3, [r3, #0]
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8002104: f022 0201 bic.w r2, r2, #1
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8002108: 615a str r2, [r3, #20]
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huart->gState = HAL_UART_STATE_READY;
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800210a: 68fb ldr r3, [r7, #12]
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800210c: 2220 movs r2, #32
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800210e: f883 203d strb.w r2, [r3, #61] ; 0x3d
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huart->RxState = HAL_UART_STATE_READY;
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8002112: 68fb ldr r3, [r7, #12]
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8002114: 2220 movs r2, #32
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8002116: f883 203e strb.w r2, [r3, #62] ; 0x3e
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/* Process Unlocked */
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__HAL_UNLOCK(huart);
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800211a: 68fb ldr r3, [r7, #12]
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800211c: 2200 movs r2, #0
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800211e: f883 203c strb.w r2, [r3, #60] ; 0x3c
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return HAL_TIMEOUT;
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8002122: 2303 movs r3, #3
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8002124: e00f b.n 8002146 <UART_WaitOnFlagUntilTimeout+0x8c>
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while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
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8002126: 68fb ldr r3, [r7, #12]
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8002128: 681b ldr r3, [r3, #0]
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800212a: 681a ldr r2, [r3, #0]
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800212c: 68bb ldr r3, [r7, #8]
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800212e: 4013 ands r3, r2
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8002130: 68ba ldr r2, [r7, #8]
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8002132: 429a cmp r2, r3
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8002134: bf0c ite eq
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8002136: 2301 moveq r3, #1
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8002138: 2300 movne r3, #0
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800213a: b2db uxtb r3, r3
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800213c: 461a mov r2, r3
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800213e: 79fb ldrb r3, [r7, #7]
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8002140: 429a cmp r2, r3
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8002142: d0c3 beq.n 80020cc <UART_WaitOnFlagUntilTimeout+0x12>
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|
|
}
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|
|
}
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|
|
}
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|
|
return HAL_OK;
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|
8002144: 2300 movs r3, #0
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|
|
}
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8002146: 4618 mov r0, r3
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8002148: 3710 adds r7, #16
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800214a: 46bd mov sp, r7
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800214c: bd80 pop {r7, pc}
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|
|
...
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|
|
|
|
|
08002150 <UART_SetConfig>:
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|
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* @param huart Pointer to a UART_HandleTypeDef structure that contains
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|
* the configuration information for the specified UART module.
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|
* @retval None
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|
|
*/
|
|
|
static void UART_SetConfig(UART_HandleTypeDef *huart)
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|
|
{
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|
|
8002150: b580 push {r7, lr}
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8002152: b084 sub sp, #16
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|
8002154: af00 add r7, sp, #0
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8002156: 6078 str r0, [r7, #4]
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|
|
assert_param(IS_UART_MODE(huart->Init.Mode));
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|
|
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|
|
/*-------------------------- USART CR2 Configuration -----------------------*/
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|
|
/* Configure the UART Stop Bits: Set STOP[13:12] bits
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|
|
according to huart->Init.StopBits value */
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|
|
MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
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|
8002158: 687b ldr r3, [r7, #4]
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800215a: 681b ldr r3, [r3, #0]
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800215c: 691b ldr r3, [r3, #16]
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800215e: f423 5140 bic.w r1, r3, #12288 ; 0x3000
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|
8002162: 687b ldr r3, [r7, #4]
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8002164: 68da ldr r2, [r3, #12]
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|
8002166: 687b ldr r3, [r7, #4]
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8002168: 681b ldr r3, [r3, #0]
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|
800216a: 430a orrs r2, r1
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|
800216c: 611a str r2, [r3, #16]
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|
|
tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling;
|
|
|
MODIFY_REG(huart->Instance->CR1,
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|
|
(uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8),
|
|
|
tmpreg);
|
|
|
#else
|
|
|
tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode;
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|
|
800216e: 687b ldr r3, [r7, #4]
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|
8002170: 689a ldr r2, [r3, #8]
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|
8002172: 687b ldr r3, [r7, #4]
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|
8002174: 691b ldr r3, [r3, #16]
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|
8002176: 431a orrs r2, r3
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|
8002178: 687b ldr r3, [r7, #4]
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|
800217a: 695b ldr r3, [r3, #20]
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|
|
800217c: 4313 orrs r3, r2
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|
|
800217e: 60bb str r3, [r7, #8]
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|
|
MODIFY_REG(huart->Instance->CR1,
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|
|
8002180: 687b ldr r3, [r7, #4]
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|
8002182: 681b ldr r3, [r3, #0]
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|
8002184: 68db ldr r3, [r3, #12]
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|
|
8002186: f423 53b0 bic.w r3, r3, #5632 ; 0x1600
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|
|
800218a: f023 030c bic.w r3, r3, #12
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|
800218e: 687a ldr r2, [r7, #4]
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|
8002190: 6812 ldr r2, [r2, #0]
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|
8002192: 68b9 ldr r1, [r7, #8]
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|
|
8002194: 430b orrs r3, r1
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|
|
8002196: 60d3 str r3, [r2, #12]
|
|
|
tmpreg);
|
|
|
#endif /* USART_CR1_OVER8 */
|
|
|
|
|
|
/*-------------------------- USART CR3 Configuration -----------------------*/
|
|
|
/* Configure the UART HFC: Set CTSE and RTSE bits according to huart->Init.HwFlowCtl value */
|
|
|
MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE), huart->Init.HwFlowCtl);
|
|
|
8002198: 687b ldr r3, [r7, #4]
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|
800219a: 681b ldr r3, [r3, #0]
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|
800219c: 695b ldr r3, [r3, #20]
|
|
|
800219e: f423 7140 bic.w r1, r3, #768 ; 0x300
|
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|
80021a2: 687b ldr r3, [r7, #4]
|
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|
80021a4: 699a ldr r2, [r3, #24]
|
|
|
80021a6: 687b ldr r3, [r7, #4]
|
|
|
80021a8: 681b ldr r3, [r3, #0]
|
|
|
80021aa: 430a orrs r2, r1
|
|
|
80021ac: 615a str r2, [r3, #20]
|
|
|
|
|
|
|
|
|
if(huart->Instance == USART1)
|
|
|
80021ae: 687b ldr r3, [r7, #4]
|
|
|
80021b0: 681b ldr r3, [r3, #0]
|
|
|
80021b2: 4a2c ldr r2, [pc, #176] ; (8002264 <UART_SetConfig+0x114>)
|
|
|
80021b4: 4293 cmp r3, r2
|
|
|
80021b6: d103 bne.n 80021c0 <UART_SetConfig+0x70>
|
|
|
{
|
|
|
pclk = HAL_RCC_GetPCLK2Freq();
|
|
|
80021b8: f7ff f906 bl 80013c8 <HAL_RCC_GetPCLK2Freq>
|
|
|
80021bc: 60f8 str r0, [r7, #12]
|
|
|
80021be: e002 b.n 80021c6 <UART_SetConfig+0x76>
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
pclk = HAL_RCC_GetPCLK1Freq();
|
|
|
80021c0: f7ff f8ee bl 80013a0 <HAL_RCC_GetPCLK1Freq>
|
|
|
80021c4: 60f8 str r0, [r7, #12]
|
|
|
else
|
|
|
{
|
|
|
huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate);
|
|
|
}
|
|
|
#else
|
|
|
huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate);
|
|
|
80021c6: 68fa ldr r2, [r7, #12]
|
|
|
80021c8: 4613 mov r3, r2
|
|
|
80021ca: 009b lsls r3, r3, #2
|
|
|
80021cc: 4413 add r3, r2
|
|
|
80021ce: 009a lsls r2, r3, #2
|
|
|
80021d0: 441a add r2, r3
|
|
|
80021d2: 687b ldr r3, [r7, #4]
|
|
|
80021d4: 685b ldr r3, [r3, #4]
|
|
|
80021d6: 009b lsls r3, r3, #2
|
|
|
80021d8: fbb2 f3f3 udiv r3, r2, r3
|
|
|
80021dc: 4a22 ldr r2, [pc, #136] ; (8002268 <UART_SetConfig+0x118>)
|
|
|
80021de: fba2 2303 umull r2, r3, r2, r3
|
|
|
80021e2: 095b lsrs r3, r3, #5
|
|
|
80021e4: 0119 lsls r1, r3, #4
|
|
|
80021e6: 68fa ldr r2, [r7, #12]
|
|
|
80021e8: 4613 mov r3, r2
|
|
|
80021ea: 009b lsls r3, r3, #2
|
|
|
80021ec: 4413 add r3, r2
|
|
|
80021ee: 009a lsls r2, r3, #2
|
|
|
80021f0: 441a add r2, r3
|
|
|
80021f2: 687b ldr r3, [r7, #4]
|
|
|
80021f4: 685b ldr r3, [r3, #4]
|
|
|
80021f6: 009b lsls r3, r3, #2
|
|
|
80021f8: fbb2 f2f3 udiv r2, r2, r3
|
|
|
80021fc: 4b1a ldr r3, [pc, #104] ; (8002268 <UART_SetConfig+0x118>)
|
|
|
80021fe: fba3 0302 umull r0, r3, r3, r2
|
|
|
8002202: 095b lsrs r3, r3, #5
|
|
|
8002204: 2064 movs r0, #100 ; 0x64
|
|
|
8002206: fb00 f303 mul.w r3, r0, r3
|
|
|
800220a: 1ad3 subs r3, r2, r3
|
|
|
800220c: 011b lsls r3, r3, #4
|
|
|
800220e: 3332 adds r3, #50 ; 0x32
|
|
|
8002210: 4a15 ldr r2, [pc, #84] ; (8002268 <UART_SetConfig+0x118>)
|
|
|
8002212: fba2 2303 umull r2, r3, r2, r3
|
|
|
8002216: 095b lsrs r3, r3, #5
|
|
|
8002218: f003 03f0 and.w r3, r3, #240 ; 0xf0
|
|
|
800221c: 4419 add r1, r3
|
|
|
800221e: 68fa ldr r2, [r7, #12]
|
|
|
8002220: 4613 mov r3, r2
|
|
|
8002222: 009b lsls r3, r3, #2
|
|
|
8002224: 4413 add r3, r2
|
|
|
8002226: 009a lsls r2, r3, #2
|
|
|
8002228: 441a add r2, r3
|
|
|
800222a: 687b ldr r3, [r7, #4]
|
|
|
800222c: 685b ldr r3, [r3, #4]
|
|
|
800222e: 009b lsls r3, r3, #2
|
|
|
8002230: fbb2 f2f3 udiv r2, r2, r3
|
|
|
8002234: 4b0c ldr r3, [pc, #48] ; (8002268 <UART_SetConfig+0x118>)
|
|
|
8002236: fba3 0302 umull r0, r3, r3, r2
|
|
|
800223a: 095b lsrs r3, r3, #5
|
|
|
800223c: 2064 movs r0, #100 ; 0x64
|
|
|
800223e: fb00 f303 mul.w r3, r0, r3
|
|
|
8002242: 1ad3 subs r3, r2, r3
|
|
|
8002244: 011b lsls r3, r3, #4
|
|
|
8002246: 3332 adds r3, #50 ; 0x32
|
|
|
8002248: 4a07 ldr r2, [pc, #28] ; (8002268 <UART_SetConfig+0x118>)
|
|
|
800224a: fba2 2303 umull r2, r3, r2, r3
|
|
|
800224e: 095b lsrs r3, r3, #5
|
|
|
8002250: f003 020f and.w r2, r3, #15
|
|
|
8002254: 687b ldr r3, [r7, #4]
|
|
|
8002256: 681b ldr r3, [r3, #0]
|
|
|
8002258: 440a add r2, r1
|
|
|
800225a: 609a str r2, [r3, #8]
|
|
|
#endif /* USART_CR1_OVER8 */
|
|
|
}
|
|
|
800225c: bf00 nop
|
|
|
800225e: 3710 adds r7, #16
|
|
|
8002260: 46bd mov sp, r7
|
|
|
8002262: bd80 pop {r7, pc}
|
|
|
8002264: 40013800 .word 0x40013800
|
|
|
8002268: 51eb851f .word 0x51eb851f
|
|
|
|
|
|
0800226c <__errno>:
|
|
|
800226c: 4b01 ldr r3, [pc, #4] ; (8002274 <__errno+0x8>)
|
|
|
800226e: 6818 ldr r0, [r3, #0]
|
|
|
8002270: 4770 bx lr
|
|
|
8002272: bf00 nop
|
|
|
8002274: 2000000c .word 0x2000000c
|
|
|
|
|
|
08002278 <__libc_init_array>:
|
|
|
8002278: b570 push {r4, r5, r6, lr}
|
|
|
800227a: 2600 movs r6, #0
|
|
|
800227c: 4d0c ldr r5, [pc, #48] ; (80022b0 <__libc_init_array+0x38>)
|
|
|
800227e: 4c0d ldr r4, [pc, #52] ; (80022b4 <__libc_init_array+0x3c>)
|
|
|
8002280: 1b64 subs r4, r4, r5
|
|
|
8002282: 10a4 asrs r4, r4, #2
|
|
|
8002284: 42a6 cmp r6, r4
|
|
|
8002286: d109 bne.n 800229c <__libc_init_array+0x24>
|
|
|
8002288: f000 fc9c bl 8002bc4 <_init>
|
|
|
800228c: 2600 movs r6, #0
|
|
|
800228e: 4d0a ldr r5, [pc, #40] ; (80022b8 <__libc_init_array+0x40>)
|
|
|
8002290: 4c0a ldr r4, [pc, #40] ; (80022bc <__libc_init_array+0x44>)
|
|
|
8002292: 1b64 subs r4, r4, r5
|
|
|
8002294: 10a4 asrs r4, r4, #2
|
|
|
8002296: 42a6 cmp r6, r4
|
|
|
8002298: d105 bne.n 80022a6 <__libc_init_array+0x2e>
|
|
|
800229a: bd70 pop {r4, r5, r6, pc}
|
|
|
800229c: f855 3b04 ldr.w r3, [r5], #4
|
|
|
80022a0: 4798 blx r3
|
|
|
80022a2: 3601 adds r6, #1
|
|
|
80022a4: e7ee b.n 8002284 <__libc_init_array+0xc>
|
|
|
80022a6: f855 3b04 ldr.w r3, [r5], #4
|
|
|
80022aa: 4798 blx r3
|
|
|
80022ac: 3601 adds r6, #1
|
|
|
80022ae: e7f2 b.n 8002296 <__libc_init_array+0x1e>
|
|
|
80022b0: 08002c5c .word 0x08002c5c
|
|
|
80022b4: 08002c5c .word 0x08002c5c
|
|
|
80022b8: 08002c5c .word 0x08002c5c
|
|
|
80022bc: 08002c60 .word 0x08002c60
|
|
|
|
|
|
080022c0 <memset>:
|
|
|
80022c0: 4603 mov r3, r0
|
|
|
80022c2: 4402 add r2, r0
|
|
|
80022c4: 4293 cmp r3, r2
|
|
|
80022c6: d100 bne.n 80022ca <memset+0xa>
|
|
|
80022c8: 4770 bx lr
|
|
|
80022ca: f803 1b01 strb.w r1, [r3], #1
|
|
|
80022ce: e7f9 b.n 80022c4 <memset+0x4>
|
|
|
|
|
|
080022d0 <siprintf>:
|
|
|
80022d0: b40e push {r1, r2, r3}
|
|
|
80022d2: f06f 4100 mvn.w r1, #2147483648 ; 0x80000000
|
|
|
80022d6: b500 push {lr}
|
|
|
80022d8: b09c sub sp, #112 ; 0x70
|
|
|
80022da: ab1d add r3, sp, #116 ; 0x74
|
|
|
80022dc: 9002 str r0, [sp, #8]
|
|
|
80022de: 9006 str r0, [sp, #24]
|
|
|
80022e0: 9107 str r1, [sp, #28]
|
|
|
80022e2: 9104 str r1, [sp, #16]
|
|
|
80022e4: 4808 ldr r0, [pc, #32] ; (8002308 <siprintf+0x38>)
|
|
|
80022e6: 4909 ldr r1, [pc, #36] ; (800230c <siprintf+0x3c>)
|
|
|
80022e8: f853 2b04 ldr.w r2, [r3], #4
|
|
|
80022ec: 9105 str r1, [sp, #20]
|
|
|
80022ee: 6800 ldr r0, [r0, #0]
|
|
|
80022f0: a902 add r1, sp, #8
|
|
|
80022f2: 9301 str r3, [sp, #4]
|
|
|
80022f4: f000 f868 bl 80023c8 <_svfiprintf_r>
|
|
|
80022f8: 2200 movs r2, #0
|
|
|
80022fa: 9b02 ldr r3, [sp, #8]
|
|
|
80022fc: 701a strb r2, [r3, #0]
|
|
|
80022fe: b01c add sp, #112 ; 0x70
|
|
|
8002300: f85d eb04 ldr.w lr, [sp], #4
|
|
|
8002304: b003 add sp, #12
|
|
|
8002306: 4770 bx lr
|
|
|
8002308: 2000000c .word 0x2000000c
|
|
|
800230c: ffff0208 .word 0xffff0208
|
|
|
|
|
|
08002310 <__ssputs_r>:
|
|
|
8002310: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
|
|
|
8002314: 688e ldr r6, [r1, #8]
|
|
|
8002316: 4682 mov sl, r0
|
|
|
8002318: 429e cmp r6, r3
|
|
|
800231a: 460c mov r4, r1
|
|
|
800231c: 4690 mov r8, r2
|
|
|
800231e: 461f mov r7, r3
|
|
|
8002320: d838 bhi.n 8002394 <__ssputs_r+0x84>
|
|
|
8002322: 898a ldrh r2, [r1, #12]
|
|
|
8002324: f412 6f90 tst.w r2, #1152 ; 0x480
|
|
|
8002328: d032 beq.n 8002390 <__ssputs_r+0x80>
|
|
|
800232a: 6825 ldr r5, [r4, #0]
|
|
|
800232c: 6909 ldr r1, [r1, #16]
|
|
|
800232e: 3301 adds r3, #1
|
|
|
8002330: eba5 0901 sub.w r9, r5, r1
|
|
|
8002334: 6965 ldr r5, [r4, #20]
|
|
|
8002336: 444b add r3, r9
|
|
|
8002338: eb05 0545 add.w r5, r5, r5, lsl #1
|
|
|
800233c: eb05 75d5 add.w r5, r5, r5, lsr #31
|
|
|
8002340: 106d asrs r5, r5, #1
|
|
|
8002342: 429d cmp r5, r3
|
|
|
8002344: bf38 it cc
|
|
|
8002346: 461d movcc r5, r3
|
|
|
8002348: 0553 lsls r3, r2, #21
|
|
|
800234a: d531 bpl.n 80023b0 <__ssputs_r+0xa0>
|
|
|
800234c: 4629 mov r1, r5
|
|
|
800234e: f000 fb6f bl 8002a30 <_malloc_r>
|
|
|
8002352: 4606 mov r6, r0
|
|
|
8002354: b950 cbnz r0, 800236c <__ssputs_r+0x5c>
|
|
|
8002356: 230c movs r3, #12
|
|
|
8002358: f04f 30ff mov.w r0, #4294967295
|
|
|
800235c: f8ca 3000 str.w r3, [sl]
|
|
|
8002360: 89a3 ldrh r3, [r4, #12]
|
|
|
8002362: f043 0340 orr.w r3, r3, #64 ; 0x40
|
|
|
8002366: 81a3 strh r3, [r4, #12]
|
|
|
8002368: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
|
|
|
800236c: 464a mov r2, r9
|
|
|
800236e: 6921 ldr r1, [r4, #16]
|
|
|
8002370: f000 face bl 8002910 <memcpy>
|
|
|
8002374: 89a3 ldrh r3, [r4, #12]
|
|
|
8002376: f423 6390 bic.w r3, r3, #1152 ; 0x480
|
|
|
800237a: f043 0380 orr.w r3, r3, #128 ; 0x80
|
|
|
800237e: 81a3 strh r3, [r4, #12]
|
|
|
8002380: 6126 str r6, [r4, #16]
|
|
|
8002382: 444e add r6, r9
|
|
|
8002384: 6026 str r6, [r4, #0]
|
|
|
8002386: 463e mov r6, r7
|
|
|
8002388: 6165 str r5, [r4, #20]
|
|
|
800238a: eba5 0509 sub.w r5, r5, r9
|
|
|
800238e: 60a5 str r5, [r4, #8]
|
|
|
8002390: 42be cmp r6, r7
|
|
|
8002392: d900 bls.n 8002396 <__ssputs_r+0x86>
|
|
|
8002394: 463e mov r6, r7
|
|
|
8002396: 4632 mov r2, r6
|
|
|
8002398: 4641 mov r1, r8
|
|
|
800239a: 6820 ldr r0, [r4, #0]
|
|
|
800239c: f000 fac6 bl 800292c <memmove>
|
|
|
80023a0: 68a3 ldr r3, [r4, #8]
|
|
|
80023a2: 2000 movs r0, #0
|
|
|
80023a4: 1b9b subs r3, r3, r6
|
|
|
80023a6: 60a3 str r3, [r4, #8]
|
|
|
80023a8: 6823 ldr r3, [r4, #0]
|
|
|
80023aa: 4433 add r3, r6
|
|
|
80023ac: 6023 str r3, [r4, #0]
|
|
|
80023ae: e7db b.n 8002368 <__ssputs_r+0x58>
|
|
|
80023b0: 462a mov r2, r5
|
|
|
80023b2: f000 fbb1 bl 8002b18 <_realloc_r>
|
|
|
80023b6: 4606 mov r6, r0
|
|
|
80023b8: 2800 cmp r0, #0
|
|
|
80023ba: d1e1 bne.n 8002380 <__ssputs_r+0x70>
|
|
|
80023bc: 4650 mov r0, sl
|
|
|
80023be: 6921 ldr r1, [r4, #16]
|
|
|
80023c0: f000 face bl 8002960 <_free_r>
|
|
|
80023c4: e7c7 b.n 8002356 <__ssputs_r+0x46>
|
|
|
...
|
|
|
|
|
|
080023c8 <_svfiprintf_r>:
|
|
|
80023c8: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
|
|
|
80023cc: 4698 mov r8, r3
|
|
|
80023ce: 898b ldrh r3, [r1, #12]
|
|
|
80023d0: 4607 mov r7, r0
|
|
|
80023d2: 061b lsls r3, r3, #24
|
|
|
80023d4: 460d mov r5, r1
|
|
|
80023d6: 4614 mov r4, r2
|
|
|
80023d8: b09d sub sp, #116 ; 0x74
|
|
|
80023da: d50e bpl.n 80023fa <_svfiprintf_r+0x32>
|
|
|
80023dc: 690b ldr r3, [r1, #16]
|
|
|
80023de: b963 cbnz r3, 80023fa <_svfiprintf_r+0x32>
|
|
|
80023e0: 2140 movs r1, #64 ; 0x40
|
|
|
80023e2: f000 fb25 bl 8002a30 <_malloc_r>
|
|
|
80023e6: 6028 str r0, [r5, #0]
|
|
|
80023e8: 6128 str r0, [r5, #16]
|
|
|
80023ea: b920 cbnz r0, 80023f6 <_svfiprintf_r+0x2e>
|
|
|
80023ec: 230c movs r3, #12
|
|
|
80023ee: 603b str r3, [r7, #0]
|
|
|
80023f0: f04f 30ff mov.w r0, #4294967295
|
|
|
80023f4: e0d1 b.n 800259a <_svfiprintf_r+0x1d2>
|
|
|
80023f6: 2340 movs r3, #64 ; 0x40
|
|
|
80023f8: 616b str r3, [r5, #20]
|
|
|
80023fa: 2300 movs r3, #0
|
|
|
80023fc: 9309 str r3, [sp, #36] ; 0x24
|
|
|
80023fe: 2320 movs r3, #32
|
|
|
8002400: f88d 3029 strb.w r3, [sp, #41] ; 0x29
|
|
|
8002404: 2330 movs r3, #48 ; 0x30
|
|
|
8002406: f04f 0901 mov.w r9, #1
|
|
|
800240a: f8cd 800c str.w r8, [sp, #12]
|
|
|
800240e: f8df 81a4 ldr.w r8, [pc, #420] ; 80025b4 <_svfiprintf_r+0x1ec>
|
|
|
8002412: f88d 302a strb.w r3, [sp, #42] ; 0x2a
|
|
|
8002416: 4623 mov r3, r4
|
|
|
8002418: 469a mov sl, r3
|
|
|
800241a: f813 2b01 ldrb.w r2, [r3], #1
|
|
|
800241e: b10a cbz r2, 8002424 <_svfiprintf_r+0x5c>
|
|
|
8002420: 2a25 cmp r2, #37 ; 0x25
|
|
|
8002422: d1f9 bne.n 8002418 <_svfiprintf_r+0x50>
|
|
|
8002424: ebba 0b04 subs.w fp, sl, r4
|
|
|
8002428: d00b beq.n 8002442 <_svfiprintf_r+0x7a>
|
|
|
800242a: 465b mov r3, fp
|
|
|
800242c: 4622 mov r2, r4
|
|
|
800242e: 4629 mov r1, r5
|
|
|
8002430: 4638 mov r0, r7
|
|
|
8002432: f7ff ff6d bl 8002310 <__ssputs_r>
|
|
|
8002436: 3001 adds r0, #1
|
|
|
8002438: f000 80aa beq.w 8002590 <_svfiprintf_r+0x1c8>
|
|
|
800243c: 9a09 ldr r2, [sp, #36] ; 0x24
|
|
|
800243e: 445a add r2, fp
|
|
|
8002440: 9209 str r2, [sp, #36] ; 0x24
|
|
|
8002442: f89a 3000 ldrb.w r3, [sl]
|
|
|
8002446: 2b00 cmp r3, #0
|
|
|
8002448: f000 80a2 beq.w 8002590 <_svfiprintf_r+0x1c8>
|
|
|
800244c: 2300 movs r3, #0
|
|
|
800244e: f04f 32ff mov.w r2, #4294967295
|
|
|
8002452: e9cd 2305 strd r2, r3, [sp, #20]
|
|
|
8002456: f10a 0a01 add.w sl, sl, #1
|
|
|
800245a: 9304 str r3, [sp, #16]
|
|
|
800245c: 9307 str r3, [sp, #28]
|
|
|
800245e: f88d 3053 strb.w r3, [sp, #83] ; 0x53
|
|
|
8002462: 931a str r3, [sp, #104] ; 0x68
|
|
|
8002464: 4654 mov r4, sl
|
|
|
8002466: 2205 movs r2, #5
|
|
|
8002468: f814 1b01 ldrb.w r1, [r4], #1
|
|
|
800246c: 4851 ldr r0, [pc, #324] ; (80025b4 <_svfiprintf_r+0x1ec>)
|
|
|
800246e: f000 fa41 bl 80028f4 <memchr>
|
|
|
8002472: 9a04 ldr r2, [sp, #16]
|
|
|
8002474: b9d8 cbnz r0, 80024ae <_svfiprintf_r+0xe6>
|
|
|
8002476: 06d0 lsls r0, r2, #27
|
|
|
8002478: bf44 itt mi
|
|
|
800247a: 2320 movmi r3, #32
|
|
|
800247c: f88d 3053 strbmi.w r3, [sp, #83] ; 0x53
|
|
|
8002480: 0711 lsls r1, r2, #28
|
|
|
8002482: bf44 itt mi
|
|
|
8002484: 232b movmi r3, #43 ; 0x2b
|
|
|
8002486: f88d 3053 strbmi.w r3, [sp, #83] ; 0x53
|
|
|
800248a: f89a 3000 ldrb.w r3, [sl]
|
|
|
800248e: 2b2a cmp r3, #42 ; 0x2a
|
|
|
8002490: d015 beq.n 80024be <_svfiprintf_r+0xf6>
|
|
|
8002492: 4654 mov r4, sl
|
|
|
8002494: 2000 movs r0, #0
|
|
|
8002496: f04f 0c0a mov.w ip, #10
|
|
|
800249a: 9a07 ldr r2, [sp, #28]
|
|
|
800249c: 4621 mov r1, r4
|
|
|
800249e: f811 3b01 ldrb.w r3, [r1], #1
|
|
|
80024a2: 3b30 subs r3, #48 ; 0x30
|
|
|
80024a4: 2b09 cmp r3, #9
|
|
|
80024a6: d94e bls.n 8002546 <_svfiprintf_r+0x17e>
|
|
|
80024a8: b1b0 cbz r0, 80024d8 <_svfiprintf_r+0x110>
|
|
|
80024aa: 9207 str r2, [sp, #28]
|
|
|
80024ac: e014 b.n 80024d8 <_svfiprintf_r+0x110>
|
|
|
80024ae: eba0 0308 sub.w r3, r0, r8
|
|
|
80024b2: fa09 f303 lsl.w r3, r9, r3
|
|
|
80024b6: 4313 orrs r3, r2
|
|
|
80024b8: 46a2 mov sl, r4
|
|
|
80024ba: 9304 str r3, [sp, #16]
|
|
|
80024bc: e7d2 b.n 8002464 <_svfiprintf_r+0x9c>
|
|
|
80024be: 9b03 ldr r3, [sp, #12]
|
|
|
80024c0: 1d19 adds r1, r3, #4
|
|
|
80024c2: 681b ldr r3, [r3, #0]
|
|
|
80024c4: 9103 str r1, [sp, #12]
|
|
|
80024c6: 2b00 cmp r3, #0
|
|
|
80024c8: bfbb ittet lt
|
|
|
80024ca: 425b neglt r3, r3
|
|
|
80024cc: f042 0202 orrlt.w r2, r2, #2
|
|
|
80024d0: 9307 strge r3, [sp, #28]
|
|
|
80024d2: 9307 strlt r3, [sp, #28]
|
|
|
80024d4: bfb8 it lt
|
|
|
80024d6: 9204 strlt r2, [sp, #16]
|
|
|
80024d8: 7823 ldrb r3, [r4, #0]
|
|
|
80024da: 2b2e cmp r3, #46 ; 0x2e
|
|
|
80024dc: d10c bne.n 80024f8 <_svfiprintf_r+0x130>
|
|
|
80024de: 7863 ldrb r3, [r4, #1]
|
|
|
80024e0: 2b2a cmp r3, #42 ; 0x2a
|
|
|
80024e2: d135 bne.n 8002550 <_svfiprintf_r+0x188>
|
|
|
80024e4: 9b03 ldr r3, [sp, #12]
|
|
|
80024e6: 3402 adds r4, #2
|
|
|
80024e8: 1d1a adds r2, r3, #4
|
|
|
80024ea: 681b ldr r3, [r3, #0]
|
|
|
80024ec: 9203 str r2, [sp, #12]
|
|
|
80024ee: 2b00 cmp r3, #0
|
|
|
80024f0: bfb8 it lt
|
|
|
80024f2: f04f 33ff movlt.w r3, #4294967295
|
|
|
80024f6: 9305 str r3, [sp, #20]
|
|
|
80024f8: f8df a0bc ldr.w sl, [pc, #188] ; 80025b8 <_svfiprintf_r+0x1f0>
|
|
|
80024fc: 2203 movs r2, #3
|
|
|
80024fe: 4650 mov r0, sl
|
|
|
8002500: 7821 ldrb r1, [r4, #0]
|
|
|
8002502: f000 f9f7 bl 80028f4 <memchr>
|
|
|
8002506: b140 cbz r0, 800251a <_svfiprintf_r+0x152>
|
|
|
8002508: 2340 movs r3, #64 ; 0x40
|
|
|
800250a: eba0 000a sub.w r0, r0, sl
|
|
|
800250e: fa03 f000 lsl.w r0, r3, r0
|
|
|
8002512: 9b04 ldr r3, [sp, #16]
|
|
|
8002514: 3401 adds r4, #1
|
|
|
8002516: 4303 orrs r3, r0
|
|
|
8002518: 9304 str r3, [sp, #16]
|
|
|
800251a: f814 1b01 ldrb.w r1, [r4], #1
|
|
|
800251e: 2206 movs r2, #6
|
|
|
8002520: 4826 ldr r0, [pc, #152] ; (80025bc <_svfiprintf_r+0x1f4>)
|
|
|
8002522: f88d 1028 strb.w r1, [sp, #40] ; 0x28
|
|
|
8002526: f000 f9e5 bl 80028f4 <memchr>
|
|
|
800252a: 2800 cmp r0, #0
|
|
|
800252c: d038 beq.n 80025a0 <_svfiprintf_r+0x1d8>
|
|
|
800252e: 4b24 ldr r3, [pc, #144] ; (80025c0 <_svfiprintf_r+0x1f8>)
|
|
|
8002530: bb1b cbnz r3, 800257a <_svfiprintf_r+0x1b2>
|
|
|
8002532: 9b03 ldr r3, [sp, #12]
|
|
|
8002534: 3307 adds r3, #7
|
|
|
8002536: f023 0307 bic.w r3, r3, #7
|
|
|
800253a: 3308 adds r3, #8
|
|
|
800253c: 9303 str r3, [sp, #12]
|
|
|
800253e: 9b09 ldr r3, [sp, #36] ; 0x24
|
|
|
8002540: 4433 add r3, r6
|
|
|
8002542: 9309 str r3, [sp, #36] ; 0x24
|
|
|
8002544: e767 b.n 8002416 <_svfiprintf_r+0x4e>
|
|
|
8002546: 460c mov r4, r1
|
|
|
8002548: 2001 movs r0, #1
|
|
|
800254a: fb0c 3202 mla r2, ip, r2, r3
|
|
|
800254e: e7a5 b.n 800249c <_svfiprintf_r+0xd4>
|
|
|
8002550: 2300 movs r3, #0
|
|
|
8002552: f04f 0c0a mov.w ip, #10
|
|
|
8002556: 4619 mov r1, r3
|
|
|
8002558: 3401 adds r4, #1
|
|
|
800255a: 9305 str r3, [sp, #20]
|
|
|
800255c: 4620 mov r0, r4
|
|
|
800255e: f810 2b01 ldrb.w r2, [r0], #1
|
|
|
8002562: 3a30 subs r2, #48 ; 0x30
|
|
|
8002564: 2a09 cmp r2, #9
|
|
|
8002566: d903 bls.n 8002570 <_svfiprintf_r+0x1a8>
|
|
|
8002568: 2b00 cmp r3, #0
|
|
|
800256a: d0c5 beq.n 80024f8 <_svfiprintf_r+0x130>
|
|
|
800256c: 9105 str r1, [sp, #20]
|
|
|
800256e: e7c3 b.n 80024f8 <_svfiprintf_r+0x130>
|
|
|
8002570: 4604 mov r4, r0
|
|
|
8002572: 2301 movs r3, #1
|
|
|
8002574: fb0c 2101 mla r1, ip, r1, r2
|
|
|
8002578: e7f0 b.n 800255c <_svfiprintf_r+0x194>
|
|
|
800257a: ab03 add r3, sp, #12
|
|
|
800257c: 9300 str r3, [sp, #0]
|
|
|
800257e: 462a mov r2, r5
|
|
|
8002580: 4638 mov r0, r7
|
|
|
8002582: 4b10 ldr r3, [pc, #64] ; (80025c4 <_svfiprintf_r+0x1fc>)
|
|
|
8002584: a904 add r1, sp, #16
|
|
|
8002586: f3af 8000 nop.w
|
|
|
800258a: 1c42 adds r2, r0, #1
|
|
|
800258c: 4606 mov r6, r0
|
|
|
800258e: d1d6 bne.n 800253e <_svfiprintf_r+0x176>
|
|
|
8002590: 89ab ldrh r3, [r5, #12]
|
|
|
8002592: 065b lsls r3, r3, #25
|
|
|
8002594: f53f af2c bmi.w 80023f0 <_svfiprintf_r+0x28>
|
|
|
8002598: 9809 ldr r0, [sp, #36] ; 0x24
|
|
|
800259a: b01d add sp, #116 ; 0x74
|
|
|
800259c: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
|
|
|
80025a0: ab03 add r3, sp, #12
|
|
|
80025a2: 9300 str r3, [sp, #0]
|
|
|
80025a4: 462a mov r2, r5
|
|
|
80025a6: 4638 mov r0, r7
|
|
|
80025a8: 4b06 ldr r3, [pc, #24] ; (80025c4 <_svfiprintf_r+0x1fc>)
|
|
|
80025aa: a904 add r1, sp, #16
|
|
|
80025ac: f000 f87c bl 80026a8 <_printf_i>
|
|
|
80025b0: e7eb b.n 800258a <_svfiprintf_r+0x1c2>
|
|
|
80025b2: bf00 nop
|
|
|
80025b4: 08002c28 .word 0x08002c28
|
|
|
80025b8: 08002c2e .word 0x08002c2e
|
|
|
80025bc: 08002c32 .word 0x08002c32
|
|
|
80025c0: 00000000 .word 0x00000000
|
|
|
80025c4: 08002311 .word 0x08002311
|
|
|
|
|
|
080025c8 <_printf_common>:
|
|
|
80025c8: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
|
|
|
80025cc: 4616 mov r6, r2
|
|
|
80025ce: 4699 mov r9, r3
|
|
|
80025d0: 688a ldr r2, [r1, #8]
|
|
|
80025d2: 690b ldr r3, [r1, #16]
|
|
|
80025d4: 4607 mov r7, r0
|
|
|
80025d6: 4293 cmp r3, r2
|
|
|
80025d8: bfb8 it lt
|
|
|
80025da: 4613 movlt r3, r2
|
|
|
80025dc: 6033 str r3, [r6, #0]
|
|
|
80025de: f891 2043 ldrb.w r2, [r1, #67] ; 0x43
|
|
|
80025e2: 460c mov r4, r1
|
|
|
80025e4: f8dd 8020 ldr.w r8, [sp, #32]
|
|
|
80025e8: b10a cbz r2, 80025ee <_printf_common+0x26>
|
|
|
80025ea: 3301 adds r3, #1
|
|
|
80025ec: 6033 str r3, [r6, #0]
|
|
|
80025ee: 6823 ldr r3, [r4, #0]
|
|
|
80025f0: 0699 lsls r1, r3, #26
|
|
|
80025f2: bf42 ittt mi
|
|
|
80025f4: 6833 ldrmi r3, [r6, #0]
|
|
|
80025f6: 3302 addmi r3, #2
|
|
|
80025f8: 6033 strmi r3, [r6, #0]
|
|
|
80025fa: 6825 ldr r5, [r4, #0]
|
|
|
80025fc: f015 0506 ands.w r5, r5, #6
|
|
|
8002600: d106 bne.n 8002610 <_printf_common+0x48>
|
|
|
8002602: f104 0a19 add.w sl, r4, #25
|
|
|
8002606: 68e3 ldr r3, [r4, #12]
|
|
|
8002608: 6832 ldr r2, [r6, #0]
|
|
|
800260a: 1a9b subs r3, r3, r2
|
|
|
800260c: 42ab cmp r3, r5
|
|
|
800260e: dc28 bgt.n 8002662 <_printf_common+0x9a>
|
|
|
8002610: f894 2043 ldrb.w r2, [r4, #67] ; 0x43
|
|
|
8002614: 1e13 subs r3, r2, #0
|
|
|
8002616: 6822 ldr r2, [r4, #0]
|
|
|
8002618: bf18 it ne
|
|
|
800261a: 2301 movne r3, #1
|
|
|
800261c: 0692 lsls r2, r2, #26
|
|
|
800261e: d42d bmi.n 800267c <_printf_common+0xb4>
|
|
|
8002620: 4649 mov r1, r9
|
|
|
8002622: 4638 mov r0, r7
|
|
|
8002624: f104 0243 add.w r2, r4, #67 ; 0x43
|
|
|
8002628: 47c0 blx r8
|
|
|
800262a: 3001 adds r0, #1
|
|
|
800262c: d020 beq.n 8002670 <_printf_common+0xa8>
|
|
|
800262e: 6823 ldr r3, [r4, #0]
|
|
|
8002630: 68e5 ldr r5, [r4, #12]
|
|
|
8002632: f003 0306 and.w r3, r3, #6
|
|
|
8002636: 2b04 cmp r3, #4
|
|
|
8002638: bf18 it ne
|
|
|
800263a: 2500 movne r5, #0
|
|
|
800263c: 6832 ldr r2, [r6, #0]
|
|
|
800263e: f04f 0600 mov.w r6, #0
|
|
|
8002642: 68a3 ldr r3, [r4, #8]
|
|
|
8002644: bf08 it eq
|
|
|
8002646: 1aad subeq r5, r5, r2
|
|
|
8002648: 6922 ldr r2, [r4, #16]
|
|
|
800264a: bf08 it eq
|
|
|
800264c: ea25 75e5 biceq.w r5, r5, r5, asr #31
|
|
|
8002650: 4293 cmp r3, r2
|
|
|
8002652: bfc4 itt gt
|
|
|
8002654: 1a9b subgt r3, r3, r2
|
|
|
8002656: 18ed addgt r5, r5, r3
|
|
|
8002658: 341a adds r4, #26
|
|
|
800265a: 42b5 cmp r5, r6
|
|
|
800265c: d11a bne.n 8002694 <_printf_common+0xcc>
|
|
|
800265e: 2000 movs r0, #0
|
|
|
8002660: e008 b.n 8002674 <_printf_common+0xac>
|
|
|
8002662: 2301 movs r3, #1
|
|
|
8002664: 4652 mov r2, sl
|
|
|
8002666: 4649 mov r1, r9
|
|
|
8002668: 4638 mov r0, r7
|
|
|
800266a: 47c0 blx r8
|
|
|
800266c: 3001 adds r0, #1
|
|
|
800266e: d103 bne.n 8002678 <_printf_common+0xb0>
|
|
|
8002670: f04f 30ff mov.w r0, #4294967295
|
|
|
8002674: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
|
|
|
8002678: 3501 adds r5, #1
|
|
|
800267a: e7c4 b.n 8002606 <_printf_common+0x3e>
|
|
|
800267c: 2030 movs r0, #48 ; 0x30
|
|
|
800267e: 18e1 adds r1, r4, r3
|
|
|
8002680: f881 0043 strb.w r0, [r1, #67] ; 0x43
|
|
|
8002684: 1c5a adds r2, r3, #1
|
|
|
8002686: f894 1045 ldrb.w r1, [r4, #69] ; 0x45
|
|
|
800268a: 4422 add r2, r4
|
|
|
800268c: 3302 adds r3, #2
|
|
|
800268e: f882 1043 strb.w r1, [r2, #67] ; 0x43
|
|
|
8002692: e7c5 b.n 8002620 <_printf_common+0x58>
|
|
|
8002694: 2301 movs r3, #1
|
|
|
8002696: 4622 mov r2, r4
|
|
|
8002698: 4649 mov r1, r9
|
|
|
800269a: 4638 mov r0, r7
|
|
|
800269c: 47c0 blx r8
|
|
|
800269e: 3001 adds r0, #1
|
|
|
80026a0: d0e6 beq.n 8002670 <_printf_common+0xa8>
|
|
|
80026a2: 3601 adds r6, #1
|
|
|
80026a4: e7d9 b.n 800265a <_printf_common+0x92>
|
|
|
...
|
|
|
|
|
|
080026a8 <_printf_i>:
|
|
|
80026a8: e92d 47ff stmdb sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, lr}
|
|
|
80026ac: 7e0f ldrb r7, [r1, #24]
|
|
|
80026ae: 4691 mov r9, r2
|
|
|
80026b0: 2f78 cmp r7, #120 ; 0x78
|
|
|
80026b2: 4680 mov r8, r0
|
|
|
80026b4: 460c mov r4, r1
|
|
|
80026b6: 469a mov sl, r3
|
|
|
80026b8: 9d0c ldr r5, [sp, #48] ; 0x30
|
|
|
80026ba: f101 0243 add.w r2, r1, #67 ; 0x43
|
|
|
80026be: d807 bhi.n 80026d0 <_printf_i+0x28>
|
|
|
80026c0: 2f62 cmp r7, #98 ; 0x62
|
|
|
80026c2: d80a bhi.n 80026da <_printf_i+0x32>
|
|
|
80026c4: 2f00 cmp r7, #0
|
|
|
80026c6: f000 80d9 beq.w 800287c <_printf_i+0x1d4>
|
|
|
80026ca: 2f58 cmp r7, #88 ; 0x58
|
|
|
80026cc: f000 80a4 beq.w 8002818 <_printf_i+0x170>
|
|
|
80026d0: f104 0542 add.w r5, r4, #66 ; 0x42
|
|
|
80026d4: f884 7042 strb.w r7, [r4, #66] ; 0x42
|
|
|
80026d8: e03a b.n 8002750 <_printf_i+0xa8>
|
|
|
80026da: f1a7 0363 sub.w r3, r7, #99 ; 0x63
|
|
|
80026de: 2b15 cmp r3, #21
|
|
|
80026e0: d8f6 bhi.n 80026d0 <_printf_i+0x28>
|
|
|
80026e2: a101 add r1, pc, #4 ; (adr r1, 80026e8 <_printf_i+0x40>)
|
|
|
80026e4: f851 f023 ldr.w pc, [r1, r3, lsl #2]
|
|
|
80026e8: 08002741 .word 0x08002741
|
|
|
80026ec: 08002755 .word 0x08002755
|
|
|
80026f0: 080026d1 .word 0x080026d1
|
|
|
80026f4: 080026d1 .word 0x080026d1
|
|
|
80026f8: 080026d1 .word 0x080026d1
|
|
|
80026fc: 080026d1 .word 0x080026d1
|
|
|
8002700: 08002755 .word 0x08002755
|
|
|
8002704: 080026d1 .word 0x080026d1
|
|
|
8002708: 080026d1 .word 0x080026d1
|
|
|
800270c: 080026d1 .word 0x080026d1
|
|
|
8002710: 080026d1 .word 0x080026d1
|
|
|
8002714: 08002863 .word 0x08002863
|
|
|
8002718: 08002785 .word 0x08002785
|
|
|
800271c: 08002845 .word 0x08002845
|
|
|
8002720: 080026d1 .word 0x080026d1
|
|
|
8002724: 080026d1 .word 0x080026d1
|
|
|
8002728: 08002885 .word 0x08002885
|
|
|
800272c: 080026d1 .word 0x080026d1
|
|
|
8002730: 08002785 .word 0x08002785
|
|
|
8002734: 080026d1 .word 0x080026d1
|
|
|
8002738: 080026d1 .word 0x080026d1
|
|
|
800273c: 0800284d .word 0x0800284d
|
|
|
8002740: 682b ldr r3, [r5, #0]
|
|
|
8002742: 1d1a adds r2, r3, #4
|
|
|
8002744: 681b ldr r3, [r3, #0]
|
|
|
8002746: 602a str r2, [r5, #0]
|
|
|
8002748: f104 0542 add.w r5, r4, #66 ; 0x42
|
|
|
800274c: f884 3042 strb.w r3, [r4, #66] ; 0x42
|
|
|
8002750: 2301 movs r3, #1
|
|
|
8002752: e0a4 b.n 800289e <_printf_i+0x1f6>
|
|
|
8002754: 6820 ldr r0, [r4, #0]
|
|
|
8002756: 6829 ldr r1, [r5, #0]
|
|
|
8002758: 0606 lsls r6, r0, #24
|
|
|
800275a: f101 0304 add.w r3, r1, #4
|
|
|
800275e: d50a bpl.n 8002776 <_printf_i+0xce>
|
|
|
8002760: 680e ldr r6, [r1, #0]
|
|
|
8002762: 602b str r3, [r5, #0]
|
|
|
8002764: 2e00 cmp r6, #0
|
|
|
8002766: da03 bge.n 8002770 <_printf_i+0xc8>
|
|
|
8002768: 232d movs r3, #45 ; 0x2d
|
|
|
800276a: 4276 negs r6, r6
|
|
|
800276c: f884 3043 strb.w r3, [r4, #67] ; 0x43
|
|
|
8002770: 230a movs r3, #10
|
|
|
8002772: 485e ldr r0, [pc, #376] ; (80028ec <_printf_i+0x244>)
|
|
|
8002774: e019 b.n 80027aa <_printf_i+0x102>
|
|
|
8002776: 680e ldr r6, [r1, #0]
|
|
|
8002778: f010 0f40 tst.w r0, #64 ; 0x40
|
|
|
800277c: 602b str r3, [r5, #0]
|
|
|
800277e: bf18 it ne
|
|
|
8002780: b236 sxthne r6, r6
|
|
|
8002782: e7ef b.n 8002764 <_printf_i+0xbc>
|
|
|
8002784: 682b ldr r3, [r5, #0]
|
|
|
8002786: 6820 ldr r0, [r4, #0]
|
|
|
8002788: 1d19 adds r1, r3, #4
|
|
|
800278a: 6029 str r1, [r5, #0]
|
|
|
800278c: 0601 lsls r1, r0, #24
|
|
|
800278e: d501 bpl.n 8002794 <_printf_i+0xec>
|
|
|
8002790: 681e ldr r6, [r3, #0]
|
|
|
8002792: e002 b.n 800279a <_printf_i+0xf2>
|
|
|
8002794: 0646 lsls r6, r0, #25
|
|
|
8002796: d5fb bpl.n 8002790 <_printf_i+0xe8>
|
|
|
8002798: 881e ldrh r6, [r3, #0]
|
|
|
800279a: 2f6f cmp r7, #111 ; 0x6f
|
|
|
800279c: bf0c ite eq
|
|
|
800279e: 2308 moveq r3, #8
|
|
|
80027a0: 230a movne r3, #10
|
|
|
80027a2: 4852 ldr r0, [pc, #328] ; (80028ec <_printf_i+0x244>)
|
|
|
80027a4: 2100 movs r1, #0
|
|
|
80027a6: f884 1043 strb.w r1, [r4, #67] ; 0x43
|
|
|
80027aa: 6865 ldr r5, [r4, #4]
|
|
|
80027ac: 2d00 cmp r5, #0
|
|
|
80027ae: bfa8 it ge
|
|
|
80027b0: 6821 ldrge r1, [r4, #0]
|
|
|
80027b2: 60a5 str r5, [r4, #8]
|
|
|
80027b4: bfa4 itt ge
|
|
|
80027b6: f021 0104 bicge.w r1, r1, #4
|
|
|
80027ba: 6021 strge r1, [r4, #0]
|
|
|
80027bc: b90e cbnz r6, 80027c2 <_printf_i+0x11a>
|
|
|
80027be: 2d00 cmp r5, #0
|
|
|
80027c0: d04d beq.n 800285e <_printf_i+0x1b6>
|
|
|
80027c2: 4615 mov r5, r2
|
|
|
80027c4: fbb6 f1f3 udiv r1, r6, r3
|
|
|
80027c8: fb03 6711 mls r7, r3, r1, r6
|
|
|
80027cc: 5dc7 ldrb r7, [r0, r7]
|
|
|
80027ce: f805 7d01 strb.w r7, [r5, #-1]!
|
|
|
80027d2: 4637 mov r7, r6
|
|
|
80027d4: 42bb cmp r3, r7
|
|
|
80027d6: 460e mov r6, r1
|
|
|
80027d8: d9f4 bls.n 80027c4 <_printf_i+0x11c>
|
|
|
80027da: 2b08 cmp r3, #8
|
|
|
80027dc: d10b bne.n 80027f6 <_printf_i+0x14e>
|
|
|
80027de: 6823 ldr r3, [r4, #0]
|
|
|
80027e0: 07de lsls r6, r3, #31
|
|
|
80027e2: d508 bpl.n 80027f6 <_printf_i+0x14e>
|
|
|
80027e4: 6923 ldr r3, [r4, #16]
|
|
|
80027e6: 6861 ldr r1, [r4, #4]
|
|
|
80027e8: 4299 cmp r1, r3
|
|
|
80027ea: bfde ittt le
|
|
|
80027ec: 2330 movle r3, #48 ; 0x30
|
|
|
80027ee: f805 3c01 strble.w r3, [r5, #-1]
|
|
|
80027f2: f105 35ff addle.w r5, r5, #4294967295
|
|
|
80027f6: 1b52 subs r2, r2, r5
|
|
|
80027f8: 6122 str r2, [r4, #16]
|
|
|
80027fa: 464b mov r3, r9
|
|
|
80027fc: 4621 mov r1, r4
|
|
|
80027fe: 4640 mov r0, r8
|
|
|
8002800: f8cd a000 str.w sl, [sp]
|
|
|
8002804: aa03 add r2, sp, #12
|
|
|
8002806: f7ff fedf bl 80025c8 <_printf_common>
|
|
|
800280a: 3001 adds r0, #1
|
|
|
800280c: d14c bne.n 80028a8 <_printf_i+0x200>
|
|
|
800280e: f04f 30ff mov.w r0, #4294967295
|
|
|
8002812: b004 add sp, #16
|
|
|
8002814: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
|
|
|
8002818: 4834 ldr r0, [pc, #208] ; (80028ec <_printf_i+0x244>)
|
|
|
800281a: f881 7045 strb.w r7, [r1, #69] ; 0x45
|
|
|
800281e: 6829 ldr r1, [r5, #0]
|
|
|
8002820: 6823 ldr r3, [r4, #0]
|
|
|
8002822: f851 6b04 ldr.w r6, [r1], #4
|
|
|
8002826: 6029 str r1, [r5, #0]
|
|
|
8002828: 061d lsls r5, r3, #24
|
|
|
800282a: d514 bpl.n 8002856 <_printf_i+0x1ae>
|
|
|
800282c: 07df lsls r7, r3, #31
|
|
|
800282e: bf44 itt mi
|
|
|
8002830: f043 0320 orrmi.w r3, r3, #32
|
|
|
8002834: 6023 strmi r3, [r4, #0]
|
|
|
8002836: b91e cbnz r6, 8002840 <_printf_i+0x198>
|
|
|
8002838: 6823 ldr r3, [r4, #0]
|
|
|
800283a: f023 0320 bic.w r3, r3, #32
|
|
|
800283e: 6023 str r3, [r4, #0]
|
|
|
8002840: 2310 movs r3, #16
|
|
|
8002842: e7af b.n 80027a4 <_printf_i+0xfc>
|
|
|
8002844: 6823 ldr r3, [r4, #0]
|
|
|
8002846: f043 0320 orr.w r3, r3, #32
|
|
|
800284a: 6023 str r3, [r4, #0]
|
|
|
800284c: 2378 movs r3, #120 ; 0x78
|
|
|
800284e: 4828 ldr r0, [pc, #160] ; (80028f0 <_printf_i+0x248>)
|
|
|
8002850: f884 3045 strb.w r3, [r4, #69] ; 0x45
|
|
|
8002854: e7e3 b.n 800281e <_printf_i+0x176>
|
|
|
8002856: 0659 lsls r1, r3, #25
|
|
|
8002858: bf48 it mi
|
|
|
800285a: b2b6 uxthmi r6, r6
|
|
|
800285c: e7e6 b.n 800282c <_printf_i+0x184>
|
|
|
800285e: 4615 mov r5, r2
|
|
|
8002860: e7bb b.n 80027da <_printf_i+0x132>
|
|
|
8002862: 682b ldr r3, [r5, #0]
|
|
|
8002864: 6826 ldr r6, [r4, #0]
|
|
|
8002866: 1d18 adds r0, r3, #4
|
|
|
8002868: 6961 ldr r1, [r4, #20]
|
|
|
800286a: 6028 str r0, [r5, #0]
|
|
|
800286c: 0635 lsls r5, r6, #24
|
|
|
800286e: 681b ldr r3, [r3, #0]
|
|
|
8002870: d501 bpl.n 8002876 <_printf_i+0x1ce>
|
|
|
8002872: 6019 str r1, [r3, #0]
|
|
|
8002874: e002 b.n 800287c <_printf_i+0x1d4>
|
|
|
8002876: 0670 lsls r0, r6, #25
|
|
|
8002878: d5fb bpl.n 8002872 <_printf_i+0x1ca>
|
|
|
800287a: 8019 strh r1, [r3, #0]
|
|
|
800287c: 2300 movs r3, #0
|
|
|
800287e: 4615 mov r5, r2
|
|
|
8002880: 6123 str r3, [r4, #16]
|
|
|
8002882: e7ba b.n 80027fa <_printf_i+0x152>
|
|
|
8002884: 682b ldr r3, [r5, #0]
|
|
|
8002886: 2100 movs r1, #0
|
|
|
8002888: 1d1a adds r2, r3, #4
|
|
|
800288a: 602a str r2, [r5, #0]
|
|
|
800288c: 681d ldr r5, [r3, #0]
|
|
|
800288e: 6862 ldr r2, [r4, #4]
|
|
|
8002890: 4628 mov r0, r5
|
|
|
8002892: f000 f82f bl 80028f4 <memchr>
|
|
|
8002896: b108 cbz r0, 800289c <_printf_i+0x1f4>
|
|
|
8002898: 1b40 subs r0, r0, r5
|
|
|
800289a: 6060 str r0, [r4, #4]
|
|
|
800289c: 6863 ldr r3, [r4, #4]
|
|
|
800289e: 6123 str r3, [r4, #16]
|
|
|
80028a0: 2300 movs r3, #0
|
|
|
80028a2: f884 3043 strb.w r3, [r4, #67] ; 0x43
|
|
|
80028a6: e7a8 b.n 80027fa <_printf_i+0x152>
|
|
|
80028a8: 462a mov r2, r5
|
|
|
80028aa: 4649 mov r1, r9
|
|
|
80028ac: 4640 mov r0, r8
|
|
|
80028ae: 6923 ldr r3, [r4, #16]
|
|
|
80028b0: 47d0 blx sl
|
|
|
80028b2: 3001 adds r0, #1
|
|
|
80028b4: d0ab beq.n 800280e <_printf_i+0x166>
|
|
|
80028b6: 6823 ldr r3, [r4, #0]
|
|
|
80028b8: 079b lsls r3, r3, #30
|
|
|
80028ba: d413 bmi.n 80028e4 <_printf_i+0x23c>
|
|
|
80028bc: 68e0 ldr r0, [r4, #12]
|
|
|
80028be: 9b03 ldr r3, [sp, #12]
|
|
|
80028c0: 4298 cmp r0, r3
|
|
|
80028c2: bfb8 it lt
|
|
|
80028c4: 4618 movlt r0, r3
|
|
|
80028c6: e7a4 b.n 8002812 <_printf_i+0x16a>
|
|
|
80028c8: 2301 movs r3, #1
|
|
|
80028ca: 4632 mov r2, r6
|
|
|
80028cc: 4649 mov r1, r9
|
|
|
80028ce: 4640 mov r0, r8
|
|
|
80028d0: 47d0 blx sl
|
|
|
80028d2: 3001 adds r0, #1
|
|
|
80028d4: d09b beq.n 800280e <_printf_i+0x166>
|
|
|
80028d6: 3501 adds r5, #1
|
|
|
80028d8: 68e3 ldr r3, [r4, #12]
|
|
|
80028da: 9903 ldr r1, [sp, #12]
|
|
|
80028dc: 1a5b subs r3, r3, r1
|
|
|
80028de: 42ab cmp r3, r5
|
|
|
80028e0: dcf2 bgt.n 80028c8 <_printf_i+0x220>
|
|
|
80028e2: e7eb b.n 80028bc <_printf_i+0x214>
|
|
|
80028e4: 2500 movs r5, #0
|
|
|
80028e6: f104 0619 add.w r6, r4, #25
|
|
|
80028ea: e7f5 b.n 80028d8 <_printf_i+0x230>
|
|
|
80028ec: 08002c39 .word 0x08002c39
|
|
|
80028f0: 08002c4a .word 0x08002c4a
|
|
|
|
|
|
080028f4 <memchr>:
|
|
|
80028f4: 4603 mov r3, r0
|
|
|
80028f6: b510 push {r4, lr}
|
|
|
80028f8: b2c9 uxtb r1, r1
|
|
|
80028fa: 4402 add r2, r0
|
|
|
80028fc: 4293 cmp r3, r2
|
|
|
80028fe: 4618 mov r0, r3
|
|
|
8002900: d101 bne.n 8002906 <memchr+0x12>
|
|
|
8002902: 2000 movs r0, #0
|
|
|
8002904: e003 b.n 800290e <memchr+0x1a>
|
|
|
8002906: 7804 ldrb r4, [r0, #0]
|
|
|
8002908: 3301 adds r3, #1
|
|
|
800290a: 428c cmp r4, r1
|
|
|
800290c: d1f6 bne.n 80028fc <memchr+0x8>
|
|
|
800290e: bd10 pop {r4, pc}
|
|
|
|
|
|
08002910 <memcpy>:
|
|
|
8002910: 440a add r2, r1
|
|
|
8002912: 4291 cmp r1, r2
|
|
|
8002914: f100 33ff add.w r3, r0, #4294967295
|
|
|
8002918: d100 bne.n 800291c <memcpy+0xc>
|
|
|
800291a: 4770 bx lr
|
|
|
800291c: b510 push {r4, lr}
|
|
|
800291e: f811 4b01 ldrb.w r4, [r1], #1
|
|
|
8002922: 4291 cmp r1, r2
|
|
|
8002924: f803 4f01 strb.w r4, [r3, #1]!
|
|
|
8002928: d1f9 bne.n 800291e <memcpy+0xe>
|
|
|
800292a: bd10 pop {r4, pc}
|
|
|
|
|
|
0800292c <memmove>:
|
|
|
800292c: 4288 cmp r0, r1
|
|
|
800292e: b510 push {r4, lr}
|
|
|
8002930: eb01 0402 add.w r4, r1, r2
|
|
|
8002934: d902 bls.n 800293c <memmove+0x10>
|
|
|
8002936: 4284 cmp r4, r0
|
|
|
8002938: 4623 mov r3, r4
|
|
|
800293a: d807 bhi.n 800294c <memmove+0x20>
|
|
|
800293c: 1e43 subs r3, r0, #1
|
|
|
800293e: 42a1 cmp r1, r4
|
|
|
8002940: d008 beq.n 8002954 <memmove+0x28>
|
|
|
8002942: f811 2b01 ldrb.w r2, [r1], #1
|
|
|
8002946: f803 2f01 strb.w r2, [r3, #1]!
|
|
|
800294a: e7f8 b.n 800293e <memmove+0x12>
|
|
|
800294c: 4601 mov r1, r0
|
|
|
800294e: 4402 add r2, r0
|
|
|
8002950: 428a cmp r2, r1
|
|
|
8002952: d100 bne.n 8002956 <memmove+0x2a>
|
|
|
8002954: bd10 pop {r4, pc}
|
|
|
8002956: f813 4d01 ldrb.w r4, [r3, #-1]!
|
|
|
800295a: f802 4d01 strb.w r4, [r2, #-1]!
|
|
|
800295e: e7f7 b.n 8002950 <memmove+0x24>
|
|
|
|
|
|
08002960 <_free_r>:
|
|
|
8002960: b538 push {r3, r4, r5, lr}
|
|
|
8002962: 4605 mov r5, r0
|
|
|
8002964: 2900 cmp r1, #0
|
|
|
8002966: d040 beq.n 80029ea <_free_r+0x8a>
|
|
|
8002968: f851 3c04 ldr.w r3, [r1, #-4]
|
|
|
800296c: 1f0c subs r4, r1, #4
|
|
|
800296e: 2b00 cmp r3, #0
|
|
|
8002970: bfb8 it lt
|
|
|
8002972: 18e4 addlt r4, r4, r3
|
|
|
8002974: f000 f910 bl 8002b98 <__malloc_lock>
|
|
|
8002978: 4a1c ldr r2, [pc, #112] ; (80029ec <_free_r+0x8c>)
|
|
|
800297a: 6813 ldr r3, [r2, #0]
|
|
|
800297c: b933 cbnz r3, 800298c <_free_r+0x2c>
|
|
|
800297e: 6063 str r3, [r4, #4]
|
|
|
8002980: 6014 str r4, [r2, #0]
|
|
|
8002982: 4628 mov r0, r5
|
|
|
8002984: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr}
|
|
|
8002988: f000 b90c b.w 8002ba4 <__malloc_unlock>
|
|
|
800298c: 42a3 cmp r3, r4
|
|
|
800298e: d908 bls.n 80029a2 <_free_r+0x42>
|
|
|
8002990: 6820 ldr r0, [r4, #0]
|
|
|
8002992: 1821 adds r1, r4, r0
|
|
|
8002994: 428b cmp r3, r1
|
|
|
8002996: bf01 itttt eq
|
|
|
8002998: 6819 ldreq r1, [r3, #0]
|
|
|
800299a: 685b ldreq r3, [r3, #4]
|
|
|
800299c: 1809 addeq r1, r1, r0
|
|
|
800299e: 6021 streq r1, [r4, #0]
|
|
|
80029a0: e7ed b.n 800297e <_free_r+0x1e>
|
|
|
80029a2: 461a mov r2, r3
|
|
|
80029a4: 685b ldr r3, [r3, #4]
|
|
|
80029a6: b10b cbz r3, 80029ac <_free_r+0x4c>
|
|
|
80029a8: 42a3 cmp r3, r4
|
|
|
80029aa: d9fa bls.n 80029a2 <_free_r+0x42>
|
|
|
80029ac: 6811 ldr r1, [r2, #0]
|
|
|
80029ae: 1850 adds r0, r2, r1
|
|
|
80029b0: 42a0 cmp r0, r4
|
|
|
80029b2: d10b bne.n 80029cc <_free_r+0x6c>
|
|
|
80029b4: 6820 ldr r0, [r4, #0]
|
|
|
80029b6: 4401 add r1, r0
|
|
|
80029b8: 1850 adds r0, r2, r1
|
|
|
80029ba: 4283 cmp r3, r0
|
|
|
80029bc: 6011 str r1, [r2, #0]
|
|
|
80029be: d1e0 bne.n 8002982 <_free_r+0x22>
|
|
|
80029c0: 6818 ldr r0, [r3, #0]
|
|
|
80029c2: 685b ldr r3, [r3, #4]
|
|
|
80029c4: 4401 add r1, r0
|
|
|
80029c6: 6011 str r1, [r2, #0]
|
|
|
80029c8: 6053 str r3, [r2, #4]
|
|
|
80029ca: e7da b.n 8002982 <_free_r+0x22>
|
|
|
80029cc: d902 bls.n 80029d4 <_free_r+0x74>
|
|
|
80029ce: 230c movs r3, #12
|
|
|
80029d0: 602b str r3, [r5, #0]
|
|
|
80029d2: e7d6 b.n 8002982 <_free_r+0x22>
|
|
|
80029d4: 6820 ldr r0, [r4, #0]
|
|
|
80029d6: 1821 adds r1, r4, r0
|
|
|
80029d8: 428b cmp r3, r1
|
|
|
80029da: bf01 itttt eq
|
|
|
80029dc: 6819 ldreq r1, [r3, #0]
|
|
|
80029de: 685b ldreq r3, [r3, #4]
|
|
|
80029e0: 1809 addeq r1, r1, r0
|
|
|
80029e2: 6021 streq r1, [r4, #0]
|
|
|
80029e4: 6063 str r3, [r4, #4]
|
|
|
80029e6: 6054 str r4, [r2, #4]
|
|
|
80029e8: e7cb b.n 8002982 <_free_r+0x22>
|
|
|
80029ea: bd38 pop {r3, r4, r5, pc}
|
|
|
80029ec: 200000ec .word 0x200000ec
|
|
|
|
|
|
080029f0 <sbrk_aligned>:
|
|
|
80029f0: b570 push {r4, r5, r6, lr}
|
|
|
80029f2: 4e0e ldr r6, [pc, #56] ; (8002a2c <sbrk_aligned+0x3c>)
|
|
|
80029f4: 460c mov r4, r1
|
|
|
80029f6: 6831 ldr r1, [r6, #0]
|
|
|
80029f8: 4605 mov r5, r0
|
|
|
80029fa: b911 cbnz r1, 8002a02 <sbrk_aligned+0x12>
|
|
|
80029fc: f000 f8bc bl 8002b78 <_sbrk_r>
|
|
|
8002a00: 6030 str r0, [r6, #0]
|
|
|
8002a02: 4621 mov r1, r4
|
|
|
8002a04: 4628 mov r0, r5
|
|
|
8002a06: f000 f8b7 bl 8002b78 <_sbrk_r>
|
|
|
8002a0a: 1c43 adds r3, r0, #1
|
|
|
8002a0c: d00a beq.n 8002a24 <sbrk_aligned+0x34>
|
|
|
8002a0e: 1cc4 adds r4, r0, #3
|
|
|
8002a10: f024 0403 bic.w r4, r4, #3
|
|
|
8002a14: 42a0 cmp r0, r4
|
|
|
8002a16: d007 beq.n 8002a28 <sbrk_aligned+0x38>
|
|
|
8002a18: 1a21 subs r1, r4, r0
|
|
|
8002a1a: 4628 mov r0, r5
|
|
|
8002a1c: f000 f8ac bl 8002b78 <_sbrk_r>
|
|
|
8002a20: 3001 adds r0, #1
|
|
|
8002a22: d101 bne.n 8002a28 <sbrk_aligned+0x38>
|
|
|
8002a24: f04f 34ff mov.w r4, #4294967295
|
|
|
8002a28: 4620 mov r0, r4
|
|
|
8002a2a: bd70 pop {r4, r5, r6, pc}
|
|
|
8002a2c: 200000f0 .word 0x200000f0
|
|
|
|
|
|
08002a30 <_malloc_r>:
|
|
|
8002a30: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr}
|
|
|
8002a34: 1ccd adds r5, r1, #3
|
|
|
8002a36: f025 0503 bic.w r5, r5, #3
|
|
|
8002a3a: 3508 adds r5, #8
|
|
|
8002a3c: 2d0c cmp r5, #12
|
|
|
8002a3e: bf38 it cc
|
|
|
8002a40: 250c movcc r5, #12
|
|
|
8002a42: 2d00 cmp r5, #0
|
|
|
8002a44: 4607 mov r7, r0
|
|
|
8002a46: db01 blt.n 8002a4c <_malloc_r+0x1c>
|
|
|
8002a48: 42a9 cmp r1, r5
|
|
|
8002a4a: d905 bls.n 8002a58 <_malloc_r+0x28>
|
|
|
8002a4c: 230c movs r3, #12
|
|
|
8002a4e: 2600 movs r6, #0
|
|
|
8002a50: 603b str r3, [r7, #0]
|
|
|
8002a52: 4630 mov r0, r6
|
|
|
8002a54: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc}
|
|
|
8002a58: 4e2e ldr r6, [pc, #184] ; (8002b14 <_malloc_r+0xe4>)
|
|
|
8002a5a: f000 f89d bl 8002b98 <__malloc_lock>
|
|
|
8002a5e: 6833 ldr r3, [r6, #0]
|
|
|
8002a60: 461c mov r4, r3
|
|
|
8002a62: bb34 cbnz r4, 8002ab2 <_malloc_r+0x82>
|
|
|
8002a64: 4629 mov r1, r5
|
|
|
8002a66: 4638 mov r0, r7
|
|
|
8002a68: f7ff ffc2 bl 80029f0 <sbrk_aligned>
|
|
|
8002a6c: 1c43 adds r3, r0, #1
|
|
|
8002a6e: 4604 mov r4, r0
|
|
|
8002a70: d14d bne.n 8002b0e <_malloc_r+0xde>
|
|
|
8002a72: 6834 ldr r4, [r6, #0]
|
|
|
8002a74: 4626 mov r6, r4
|
|
|
8002a76: 2e00 cmp r6, #0
|
|
|
8002a78: d140 bne.n 8002afc <_malloc_r+0xcc>
|
|
|
8002a7a: 6823 ldr r3, [r4, #0]
|
|
|
8002a7c: 4631 mov r1, r6
|
|
|
8002a7e: 4638 mov r0, r7
|
|
|
8002a80: eb04 0803 add.w r8, r4, r3
|
|
|
8002a84: f000 f878 bl 8002b78 <_sbrk_r>
|
|
|
8002a88: 4580 cmp r8, r0
|
|
|
8002a8a: d13a bne.n 8002b02 <_malloc_r+0xd2>
|
|
|
8002a8c: 6821 ldr r1, [r4, #0]
|
|
|
8002a8e: 3503 adds r5, #3
|
|
|
8002a90: 1a6d subs r5, r5, r1
|
|
|
8002a92: f025 0503 bic.w r5, r5, #3
|
|
|
8002a96: 3508 adds r5, #8
|
|
|
8002a98: 2d0c cmp r5, #12
|
|
|
8002a9a: bf38 it cc
|
|
|
8002a9c: 250c movcc r5, #12
|
|
|
8002a9e: 4638 mov r0, r7
|
|
|
8002aa0: 4629 mov r1, r5
|
|
|
8002aa2: f7ff ffa5 bl 80029f0 <sbrk_aligned>
|
|
|
8002aa6: 3001 adds r0, #1
|
|
|
8002aa8: d02b beq.n 8002b02 <_malloc_r+0xd2>
|
|
|
8002aaa: 6823 ldr r3, [r4, #0]
|
|
|
8002aac: 442b add r3, r5
|
|
|
8002aae: 6023 str r3, [r4, #0]
|
|
|
8002ab0: e00e b.n 8002ad0 <_malloc_r+0xa0>
|
|
|
8002ab2: 6822 ldr r2, [r4, #0]
|
|
|
8002ab4: 1b52 subs r2, r2, r5
|
|
|
8002ab6: d41e bmi.n 8002af6 <_malloc_r+0xc6>
|
|
|
8002ab8: 2a0b cmp r2, #11
|
|
|
8002aba: d916 bls.n 8002aea <_malloc_r+0xba>
|
|
|
8002abc: 1961 adds r1, r4, r5
|
|
|
8002abe: 42a3 cmp r3, r4
|
|
|
8002ac0: 6025 str r5, [r4, #0]
|
|
|
8002ac2: bf18 it ne
|
|
|
8002ac4: 6059 strne r1, [r3, #4]
|
|
|
8002ac6: 6863 ldr r3, [r4, #4]
|
|
|
8002ac8: bf08 it eq
|
|
|
8002aca: 6031 streq r1, [r6, #0]
|
|
|
8002acc: 5162 str r2, [r4, r5]
|
|
|
8002ace: 604b str r3, [r1, #4]
|
|
|
8002ad0: 4638 mov r0, r7
|
|
|
8002ad2: f104 060b add.w r6, r4, #11
|
|
|
8002ad6: f000 f865 bl 8002ba4 <__malloc_unlock>
|
|
|
8002ada: f026 0607 bic.w r6, r6, #7
|
|
|
8002ade: 1d23 adds r3, r4, #4
|
|
|
8002ae0: 1af2 subs r2, r6, r3
|
|
|
8002ae2: d0b6 beq.n 8002a52 <_malloc_r+0x22>
|
|
|
8002ae4: 1b9b subs r3, r3, r6
|
|
|
8002ae6: 50a3 str r3, [r4, r2]
|
|
|
8002ae8: e7b3 b.n 8002a52 <_malloc_r+0x22>
|
|
|
8002aea: 6862 ldr r2, [r4, #4]
|
|
|
8002aec: 42a3 cmp r3, r4
|
|
|
8002aee: bf0c ite eq
|
|
|
8002af0: 6032 streq r2, [r6, #0]
|
|
|
8002af2: 605a strne r2, [r3, #4]
|
|
|
8002af4: e7ec b.n 8002ad0 <_malloc_r+0xa0>
|
|
|
8002af6: 4623 mov r3, r4
|
|
|
8002af8: 6864 ldr r4, [r4, #4]
|
|
|
8002afa: e7b2 b.n 8002a62 <_malloc_r+0x32>
|
|
|
8002afc: 4634 mov r4, r6
|
|
|
8002afe: 6876 ldr r6, [r6, #4]
|
|
|
8002b00: e7b9 b.n 8002a76 <_malloc_r+0x46>
|
|
|
8002b02: 230c movs r3, #12
|
|
|
8002b04: 4638 mov r0, r7
|
|
|
8002b06: 603b str r3, [r7, #0]
|
|
|
8002b08: f000 f84c bl 8002ba4 <__malloc_unlock>
|
|
|
8002b0c: e7a1 b.n 8002a52 <_malloc_r+0x22>
|
|
|
8002b0e: 6025 str r5, [r4, #0]
|
|
|
8002b10: e7de b.n 8002ad0 <_malloc_r+0xa0>
|
|
|
8002b12: bf00 nop
|
|
|
8002b14: 200000ec .word 0x200000ec
|
|
|
|
|
|
08002b18 <_realloc_r>:
|
|
|
8002b18: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr}
|
|
|
8002b1c: 4680 mov r8, r0
|
|
|
8002b1e: 4614 mov r4, r2
|
|
|
8002b20: 460e mov r6, r1
|
|
|
8002b22: b921 cbnz r1, 8002b2e <_realloc_r+0x16>
|
|
|
8002b24: 4611 mov r1, r2
|
|
|
8002b26: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr}
|
|
|
8002b2a: f7ff bf81 b.w 8002a30 <_malloc_r>
|
|
|
8002b2e: b92a cbnz r2, 8002b3c <_realloc_r+0x24>
|
|
|
8002b30: f7ff ff16 bl 8002960 <_free_r>
|
|
|
8002b34: 4625 mov r5, r4
|
|
|
8002b36: 4628 mov r0, r5
|
|
|
8002b38: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc}
|
|
|
8002b3c: f000 f838 bl 8002bb0 <_malloc_usable_size_r>
|
|
|
8002b40: 4284 cmp r4, r0
|
|
|
8002b42: 4607 mov r7, r0
|
|
|
8002b44: d802 bhi.n 8002b4c <_realloc_r+0x34>
|
|
|
8002b46: ebb4 0f50 cmp.w r4, r0, lsr #1
|
|
|
8002b4a: d812 bhi.n 8002b72 <_realloc_r+0x5a>
|
|
|
8002b4c: 4621 mov r1, r4
|
|
|
8002b4e: 4640 mov r0, r8
|
|
|
8002b50: f7ff ff6e bl 8002a30 <_malloc_r>
|
|
|
8002b54: 4605 mov r5, r0
|
|
|
8002b56: 2800 cmp r0, #0
|
|
|
8002b58: d0ed beq.n 8002b36 <_realloc_r+0x1e>
|
|
|
8002b5a: 42bc cmp r4, r7
|
|
|
8002b5c: 4622 mov r2, r4
|
|
|
8002b5e: 4631 mov r1, r6
|
|
|
8002b60: bf28 it cs
|
|
|
8002b62: 463a movcs r2, r7
|
|
|
8002b64: f7ff fed4 bl 8002910 <memcpy>
|
|
|
8002b68: 4631 mov r1, r6
|
|
|
8002b6a: 4640 mov r0, r8
|
|
|
8002b6c: f7ff fef8 bl 8002960 <_free_r>
|
|
|
8002b70: e7e1 b.n 8002b36 <_realloc_r+0x1e>
|
|
|
8002b72: 4635 mov r5, r6
|
|
|
8002b74: e7df b.n 8002b36 <_realloc_r+0x1e>
|
|
|
...
|
|
|
|
|
|
08002b78 <_sbrk_r>:
|
|
|
8002b78: b538 push {r3, r4, r5, lr}
|
|
|
8002b7a: 2300 movs r3, #0
|
|
|
8002b7c: 4d05 ldr r5, [pc, #20] ; (8002b94 <_sbrk_r+0x1c>)
|
|
|
8002b7e: 4604 mov r4, r0
|
|
|
8002b80: 4608 mov r0, r1
|
|
|
8002b82: 602b str r3, [r5, #0]
|
|
|
8002b84: f7fd fc68 bl 8000458 <_sbrk>
|
|
|
8002b88: 1c43 adds r3, r0, #1
|
|
|
8002b8a: d102 bne.n 8002b92 <_sbrk_r+0x1a>
|
|
|
8002b8c: 682b ldr r3, [r5, #0]
|
|
|
8002b8e: b103 cbz r3, 8002b92 <_sbrk_r+0x1a>
|
|
|
8002b90: 6023 str r3, [r4, #0]
|
|
|
8002b92: bd38 pop {r3, r4, r5, pc}
|
|
|
8002b94: 200000f4 .word 0x200000f4
|
|
|
|
|
|
08002b98 <__malloc_lock>:
|
|
|
8002b98: 4801 ldr r0, [pc, #4] ; (8002ba0 <__malloc_lock+0x8>)
|
|
|
8002b9a: f000 b811 b.w 8002bc0 <__retarget_lock_acquire_recursive>
|
|
|
8002b9e: bf00 nop
|
|
|
8002ba0: 200000f8 .word 0x200000f8
|
|
|
|
|
|
08002ba4 <__malloc_unlock>:
|
|
|
8002ba4: 4801 ldr r0, [pc, #4] ; (8002bac <__malloc_unlock+0x8>)
|
|
|
8002ba6: f000 b80c b.w 8002bc2 <__retarget_lock_release_recursive>
|
|
|
8002baa: bf00 nop
|
|
|
8002bac: 200000f8 .word 0x200000f8
|
|
|
|
|
|
08002bb0 <_malloc_usable_size_r>:
|
|
|
8002bb0: f851 3c04 ldr.w r3, [r1, #-4]
|
|
|
8002bb4: 1f18 subs r0, r3, #4
|
|
|
8002bb6: 2b00 cmp r3, #0
|
|
|
8002bb8: bfbc itt lt
|
|
|
8002bba: 580b ldrlt r3, [r1, r0]
|
|
|
8002bbc: 18c0 addlt r0, r0, r3
|
|
|
8002bbe: 4770 bx lr
|
|
|
|
|
|
08002bc0 <__retarget_lock_acquire_recursive>:
|
|
|
8002bc0: 4770 bx lr
|
|
|
|
|
|
08002bc2 <__retarget_lock_release_recursive>:
|
|
|
8002bc2: 4770 bx lr
|
|
|
|
|
|
08002bc4 <_init>:
|
|
|
8002bc4: b5f8 push {r3, r4, r5, r6, r7, lr}
|
|
|
8002bc6: bf00 nop
|
|
|
8002bc8: bcf8 pop {r3, r4, r5, r6, r7}
|
|
|
8002bca: bc08 pop {r3}
|
|
|
8002bcc: 469e mov lr, r3
|
|
|
8002bce: 4770 bx lr
|
|
|
|
|
|
08002bd0 <_fini>:
|
|
|
8002bd0: b5f8 push {r3, r4, r5, r6, r7, lr}
|
|
|
8002bd2: bf00 nop
|
|
|
8002bd4: bcf8 pop {r3, r4, r5, r6, r7}
|
|
|
8002bd6: bc08 pop {r3}
|
|
|
8002bd8: 469e mov lr, r3
|
|
|
8002bda: 4770 bx lr
|