ADC_Potentiometer.elf: file format elf32-littlearm Sections: Idx Name Size VMA LMA File off Algn 0 .isr_vector 0000010c 08000000 08000000 00010000 2**0 CONTENTS, ALLOC, LOAD, READONLY, DATA 1 .text 000027d0 0800010c 0800010c 0001010c 2**2 CONTENTS, ALLOC, LOAD, READONLY, CODE 2 .rodata 00000064 080028dc 080028dc 000128dc 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 3 .ARM.extab 00000000 08002940 08002940 00020070 2**0 CONTENTS 4 .ARM 00000000 08002940 08002940 00020070 2**0 CONTENTS 5 .preinit_array 00000000 08002940 08002940 00020070 2**0 CONTENTS, ALLOC, LOAD, DATA 6 .init_array 00000004 08002940 08002940 00012940 2**2 CONTENTS, ALLOC, LOAD, DATA 7 .fini_array 00000004 08002944 08002944 00012944 2**2 CONTENTS, ALLOC, LOAD, DATA 8 .data 00000070 20000000 08002948 00020000 2**2 CONTENTS, ALLOC, LOAD, DATA 9 .bss 000000a8 20000070 080029b8 00020070 2**2 ALLOC 10 ._user_heap_stack 00000600 20000118 080029b8 00020118 2**0 ALLOC 11 .ARM.attributes 00000029 00000000 00000000 00020070 2**0 CONTENTS, READONLY 12 .debug_info 00006ad0 00000000 00000000 00020099 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 13 .debug_abbrev 00001929 00000000 00000000 00026b69 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 14 .debug_aranges 00000788 00000000 00000000 00028498 2**3 CONTENTS, READONLY, DEBUGGING, OCTETS 15 .debug_ranges 000006c0 00000000 00000000 00028c20 2**3 CONTENTS, READONLY, DEBUGGING, OCTETS 16 .debug_macro 00017c2f 00000000 00000000 000292e0 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 17 .debug_line 000094f6 00000000 00000000 00040f0f 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 18 .debug_str 000871f6 00000000 00000000 0004a405 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 19 .comment 00000050 00000000 00000000 000d15fb 2**0 CONTENTS, READONLY 20 .debug_frame 0000204c 00000000 00000000 000d164c 2**2 CONTENTS, READONLY, DEBUGGING, OCTETS Disassembly of section .text: 0800010c <__do_global_dtors_aux>: 800010c: b510 push {r4, lr} 800010e: 4c05 ldr r4, [pc, #20] ; (8000124 <__do_global_dtors_aux+0x18>) 8000110: 7823 ldrb r3, [r4, #0] 8000112: b933 cbnz r3, 8000122 <__do_global_dtors_aux+0x16> 8000114: 4b04 ldr r3, [pc, #16] ; (8000128 <__do_global_dtors_aux+0x1c>) 8000116: b113 cbz r3, 800011e <__do_global_dtors_aux+0x12> 8000118: 4804 ldr r0, [pc, #16] ; (800012c <__do_global_dtors_aux+0x20>) 800011a: f3af 8000 nop.w 800011e: 2301 movs r3, #1 8000120: 7023 strb r3, [r4, #0] 8000122: bd10 pop {r4, pc} 8000124: 20000070 .word 0x20000070 8000128: 00000000 .word 0x00000000 800012c: 080028c4 .word 0x080028c4 08000130 : 8000130: b508 push {r3, lr} 8000132: 4b03 ldr r3, [pc, #12] ; (8000140 ) 8000134: b11b cbz r3, 800013e 8000136: 4903 ldr r1, [pc, #12] ; (8000144 ) 8000138: 4803 ldr r0, [pc, #12] ; (8000148 ) 800013a: f3af 8000 nop.w 800013e: bd08 pop {r3, pc} 8000140: 00000000 .word 0x00000000 8000144: 20000074 .word 0x20000074 8000148: 080028c4 .word 0x080028c4 0800014c : 800014c: 4603 mov r3, r0 800014e: f813 2b01 ldrb.w r2, [r3], #1 8000152: 2a00 cmp r2, #0 8000154: d1fb bne.n 800014e 8000156: 1a18 subs r0, r3, r0 8000158: 3801 subs r0, #1 800015a: 4770 bx lr 0800015c : ADC_HandleTypeDef hadc1; /* ADC1 init function */ void MX_ADC1_Init(void) { 800015c: b580 push {r7, lr} 800015e: b084 sub sp, #16 8000160: af00 add r7, sp, #0 /* USER CODE BEGIN ADC1_Init 0 */ /* USER CODE END ADC1_Init 0 */ ADC_ChannelConfTypeDef sConfig = {0}; 8000162: 1d3b adds r3, r7, #4 8000164: 2200 movs r2, #0 8000166: 601a str r2, [r3, #0] 8000168: 605a str r2, [r3, #4] 800016a: 609a str r2, [r3, #8] /* USER CODE END ADC1_Init 1 */ /** Common config */ hadc1.Instance = ADC1; 800016c: 4b18 ldr r3, [pc, #96] ; (80001d0 ) 800016e: 4a19 ldr r2, [pc, #100] ; (80001d4 ) 8000170: 601a str r2, [r3, #0] hadc1.Init.ScanConvMode = ADC_SCAN_DISABLE; 8000172: 4b17 ldr r3, [pc, #92] ; (80001d0 ) 8000174: 2200 movs r2, #0 8000176: 609a str r2, [r3, #8] hadc1.Init.ContinuousConvMode = ENABLE; 8000178: 4b15 ldr r3, [pc, #84] ; (80001d0 ) 800017a: 2201 movs r2, #1 800017c: 731a strb r2, [r3, #12] hadc1.Init.DiscontinuousConvMode = DISABLE; 800017e: 4b14 ldr r3, [pc, #80] ; (80001d0 ) 8000180: 2200 movs r2, #0 8000182: 751a strb r2, [r3, #20] hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START; 8000184: 4b12 ldr r3, [pc, #72] ; (80001d0 ) 8000186: f44f 2260 mov.w r2, #917504 ; 0xe0000 800018a: 61da str r2, [r3, #28] hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT; 800018c: 4b10 ldr r3, [pc, #64] ; (80001d0 ) 800018e: 2200 movs r2, #0 8000190: 605a str r2, [r3, #4] hadc1.Init.NbrOfConversion = 1; 8000192: 4b0f ldr r3, [pc, #60] ; (80001d0 ) 8000194: 2201 movs r2, #1 8000196: 611a str r2, [r3, #16] if (HAL_ADC_Init(&hadc1) != HAL_OK) 8000198: 480d ldr r0, [pc, #52] ; (80001d0 ) 800019a: f000 fad1 bl 8000740 800019e: 4603 mov r3, r0 80001a0: 2b00 cmp r3, #0 80001a2: d001 beq.n 80001a8 { Error_Handler(); 80001a4: f000 f911 bl 80003ca } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_5; 80001a8: 2305 movs r3, #5 80001aa: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_1; 80001ac: 2301 movs r3, #1 80001ae: 60bb str r3, [r7, #8] sConfig.SamplingTime = ADC_SAMPLETIME_239CYCLES_5; 80001b0: 2307 movs r3, #7 80001b2: 60fb str r3, [r7, #12] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 80001b4: 1d3b adds r3, r7, #4 80001b6: 4619 mov r1, r3 80001b8: 4805 ldr r0, [pc, #20] ; (80001d0 ) 80001ba: f000 fc53 bl 8000a64 80001be: 4603 mov r3, r0 80001c0: 2b00 cmp r3, #0 80001c2: d001 beq.n 80001c8 { Error_Handler(); 80001c4: f000 f901 bl 80003ca } /* USER CODE BEGIN ADC1_Init 2 */ /* USER CODE END ADC1_Init 2 */ } 80001c8: bf00 nop 80001ca: 3710 adds r7, #16 80001cc: 46bd mov sp, r7 80001ce: bd80 pop {r7, pc} 80001d0: 2000008c .word 0x2000008c 80001d4: 40012400 .word 0x40012400 080001d8 : void HAL_ADC_MspInit(ADC_HandleTypeDef* adcHandle) { 80001d8: b580 push {r7, lr} 80001da: b088 sub sp, #32 80001dc: af00 add r7, sp, #0 80001de: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 80001e0: f107 0310 add.w r3, r7, #16 80001e4: 2200 movs r2, #0 80001e6: 601a str r2, [r3, #0] 80001e8: 605a str r2, [r3, #4] 80001ea: 609a str r2, [r3, #8] 80001ec: 60da str r2, [r3, #12] if(adcHandle->Instance==ADC1) 80001ee: 687b ldr r3, [r7, #4] 80001f0: 681b ldr r3, [r3, #0] 80001f2: 4a14 ldr r2, [pc, #80] ; (8000244 ) 80001f4: 4293 cmp r3, r2 80001f6: d121 bne.n 800023c { /* USER CODE BEGIN ADC1_MspInit 0 */ /* USER CODE END ADC1_MspInit 0 */ /* ADC1 clock enable */ __HAL_RCC_ADC1_CLK_ENABLE(); 80001f8: 4b13 ldr r3, [pc, #76] ; (8000248 ) 80001fa: 699b ldr r3, [r3, #24] 80001fc: 4a12 ldr r2, [pc, #72] ; (8000248 ) 80001fe: f443 7300 orr.w r3, r3, #512 ; 0x200 8000202: 6193 str r3, [r2, #24] 8000204: 4b10 ldr r3, [pc, #64] ; (8000248 ) 8000206: 699b ldr r3, [r3, #24] 8000208: f403 7300 and.w r3, r3, #512 ; 0x200 800020c: 60fb str r3, [r7, #12] 800020e: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOA_CLK_ENABLE(); 8000210: 4b0d ldr r3, [pc, #52] ; (8000248 ) 8000212: 699b ldr r3, [r3, #24] 8000214: 4a0c ldr r2, [pc, #48] ; (8000248 ) 8000216: f043 0304 orr.w r3, r3, #4 800021a: 6193 str r3, [r2, #24] 800021c: 4b0a ldr r3, [pc, #40] ; (8000248 ) 800021e: 699b ldr r3, [r3, #24] 8000220: f003 0304 and.w r3, r3, #4 8000224: 60bb str r3, [r7, #8] 8000226: 68bb ldr r3, [r7, #8] /**ADC1 GPIO Configuration PA5 ------> ADC1_IN5 */ GPIO_InitStruct.Pin = GPIO_PIN_5; 8000228: 2320 movs r3, #32 800022a: 613b str r3, [r7, #16] GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 800022c: 2303 movs r3, #3 800022e: 617b str r3, [r7, #20] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8000230: f107 0310 add.w r3, r7, #16 8000234: 4619 mov r1, r3 8000236: 4805 ldr r0, [pc, #20] ; (800024c ) 8000238: f000 fe8c bl 8000f54 /* USER CODE BEGIN ADC1_MspInit 1 */ /* USER CODE END ADC1_MspInit 1 */ } } 800023c: bf00 nop 800023e: 3720 adds r7, #32 8000240: 46bd mov sp, r7 8000242: bd80 pop {r7, pc} 8000244: 40012400 .word 0x40012400 8000248: 40021000 .word 0x40021000 800024c: 40010800 .word 0x40010800 08000250 : * Output * EVENT_OUT * EXTI */ void MX_GPIO_Init(void) { 8000250: b480 push {r7} 8000252: b083 sub sp, #12 8000254: af00 add r7, sp, #0 /* GPIO Ports Clock Enable */ __HAL_RCC_GPIOD_CLK_ENABLE(); 8000256: 4b0e ldr r3, [pc, #56] ; (8000290 ) 8000258: 699b ldr r3, [r3, #24] 800025a: 4a0d ldr r2, [pc, #52] ; (8000290 ) 800025c: f043 0320 orr.w r3, r3, #32 8000260: 6193 str r3, [r2, #24] 8000262: 4b0b ldr r3, [pc, #44] ; (8000290 ) 8000264: 699b ldr r3, [r3, #24] 8000266: f003 0320 and.w r3, r3, #32 800026a: 607b str r3, [r7, #4] 800026c: 687b ldr r3, [r7, #4] __HAL_RCC_GPIOA_CLK_ENABLE(); 800026e: 4b08 ldr r3, [pc, #32] ; (8000290 ) 8000270: 699b ldr r3, [r3, #24] 8000272: 4a07 ldr r2, [pc, #28] ; (8000290 ) 8000274: f043 0304 orr.w r3, r3, #4 8000278: 6193 str r3, [r2, #24] 800027a: 4b05 ldr r3, [pc, #20] ; (8000290 ) 800027c: 699b ldr r3, [r3, #24] 800027e: f003 0304 and.w r3, r3, #4 8000282: 603b str r3, [r7, #0] 8000284: 683b ldr r3, [r7, #0] } 8000286: bf00 nop 8000288: 370c adds r7, #12 800028a: 46bd mov sp, r7 800028c: bc80 pop {r7} 800028e: 4770 bx lr 8000290: 40021000 .word 0x40021000 08000294
: /** * @brief The application entry point. * @retval int */ int main(void) { 8000294: b580 push {r7, lr} 8000296: b088 sub sp, #32 8000298: af00 add r7, sp, #0 /* USER CODE END 1 */ /* MCU Configuration--------------------------------------------------------*/ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ HAL_Init(); 800029a: f000 f9cb bl 8000634 /* USER CODE BEGIN Init */ /* USER CODE END Init */ /* Configure the system clock */ SystemClock_Config(); 800029e: f000 f839 bl 8000314 /* USER CODE BEGIN SysInit */ /* USER CODE END SysInit */ /* Initialize all configured peripherals */ MX_GPIO_Init(); 80002a2: f7ff ffd5 bl 8000250 MX_ADC1_Init(); 80002a6: f7ff ff59 bl 800015c MX_USART2_UART_Init(); 80002aa: f000 f929 bl 8000500 /* USER CODE END 2 */ /* Infinite loop */ /* USER CODE BEGIN WHILE */ char send_buf[30] = { 0 }; 80002ae: 2300 movs r3, #0 80002b0: 603b str r3, [r7, #0] 80002b2: 1d3b adds r3, r7, #4 80002b4: 2200 movs r2, #0 80002b6: 601a str r2, [r3, #0] 80002b8: 605a str r2, [r3, #4] 80002ba: 609a str r2, [r3, #8] 80002bc: 60da str r2, [r3, #12] 80002be: 611a str r2, [r3, #16] 80002c0: 615a str r2, [r3, #20] 80002c2: 831a strh r2, [r3, #24] //打开ADC HAL_ADC_Start(&hadc1); 80002c4: 4810 ldr r0, [pc, #64] ; (8000308 ) 80002c6: f000 fb13 bl 80008f0 //等待ADC稳定 HAL_Delay(500); 80002ca: f44f 70fa mov.w r0, #500 ; 0x1f4 80002ce: f000 fa13 bl 80006f8 while (1) { sprintf(send_buf, "%u\r\n", (uint16_t) HAL_ADC_GetValue(&hadc1)); 80002d2: 480d ldr r0, [pc, #52] ; (8000308 ) 80002d4: f000 fbba bl 8000a4c 80002d8: 4603 mov r3, r0 80002da: b29b uxth r3, r3 80002dc: 461a mov r2, r3 80002de: 463b mov r3, r7 80002e0: 490a ldr r1, [pc, #40] ; (800030c ) 80002e2: 4618 mov r0, r3 80002e4: f001 fe74 bl 8001fd0 HAL_UART_Transmit(&huart2, (uint8_t*) send_buf, strlen(send_buf), 10); 80002e8: 463b mov r3, r7 80002ea: 4618 mov r0, r3 80002ec: f7ff ff2e bl 800014c 80002f0: 4603 mov r3, r0 80002f2: b29a uxth r2, r3 80002f4: 4639 mov r1, r7 80002f6: 230a movs r3, #10 80002f8: 4805 ldr r0, [pc, #20] ; (8000310 ) 80002fa: f001 fccc bl 8001c96 HAL_Delay(100); 80002fe: 2064 movs r0, #100 ; 0x64 8000300: f000 f9fa bl 80006f8 sprintf(send_buf, "%u\r\n", (uint16_t) HAL_ADC_GetValue(&hadc1)); 8000304: e7e5 b.n 80002d2 8000306: bf00 nop 8000308: 2000008c .word 0x2000008c 800030c: 080028dc .word 0x080028dc 8000310: 200000c0 .word 0x200000c0 08000314 : /** * @brief System Clock Configuration * @retval None */ void SystemClock_Config(void) { 8000314: b580 push {r7, lr} 8000316: b094 sub sp, #80 ; 0x50 8000318: af00 add r7, sp, #0 RCC_OscInitTypeDef RCC_OscInitStruct = { 0 }; 800031a: f107 0328 add.w r3, r7, #40 ; 0x28 800031e: 2228 movs r2, #40 ; 0x28 8000320: 2100 movs r1, #0 8000322: 4618 mov r0, r3 8000324: f001 fe4c bl 8001fc0 RCC_ClkInitTypeDef RCC_ClkInitStruct = { 0 }; 8000328: f107 0314 add.w r3, r7, #20 800032c: 2200 movs r2, #0 800032e: 601a str r2, [r3, #0] 8000330: 605a str r2, [r3, #4] 8000332: 609a str r2, [r3, #8] 8000334: 60da str r2, [r3, #12] 8000336: 611a str r2, [r3, #16] RCC_PeriphCLKInitTypeDef PeriphClkInit = { 0 }; 8000338: 1d3b adds r3, r7, #4 800033a: 2200 movs r2, #0 800033c: 601a str r2, [r3, #0] 800033e: 605a str r2, [r3, #4] 8000340: 609a str r2, [r3, #8] 8000342: 60da str r2, [r3, #12] /** Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; 8000344: 2301 movs r3, #1 8000346: 62bb str r3, [r7, #40] ; 0x28 RCC_OscInitStruct.HSEState = RCC_HSE_ON; 8000348: f44f 3380 mov.w r3, #65536 ; 0x10000 800034c: 62fb str r3, [r7, #44] ; 0x2c RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV1; 800034e: 2300 movs r3, #0 8000350: 633b str r3, [r7, #48] ; 0x30 RCC_OscInitStruct.HSIState = RCC_HSI_ON; 8000352: 2301 movs r3, #1 8000354: 63bb str r3, [r7, #56] ; 0x38 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; 8000356: 2302 movs r3, #2 8000358: 647b str r3, [r7, #68] ; 0x44 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; 800035a: f44f 3380 mov.w r3, #65536 ; 0x10000 800035e: 64bb str r3, [r7, #72] ; 0x48 RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9; 8000360: f44f 13e0 mov.w r3, #1835008 ; 0x1c0000 8000364: 64fb str r3, [r7, #76] ; 0x4c if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { 8000366: f107 0328 add.w r3, r7, #40 ; 0x28 800036a: 4618 mov r0, r3 800036c: f000 ff76 bl 800125c 8000370: 4603 mov r3, r0 8000372: 2b00 cmp r3, #0 8000374: d001 beq.n 800037a Error_Handler(); 8000376: f000 f828 bl 80003ca } /** Initializes the CPU, AHB and APB buses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK 800037a: 230f movs r3, #15 800037c: 617b str r3, [r7, #20] | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; 800037e: 2302 movs r3, #2 8000380: 61bb str r3, [r7, #24] RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; 8000382: 2300 movs r3, #0 8000384: 61fb str r3, [r7, #28] RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; 8000386: f44f 6380 mov.w r3, #1024 ; 0x400 800038a: 623b str r3, [r7, #32] RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; 800038c: 2300 movs r3, #0 800038e: 627b str r3, [r7, #36] ; 0x24 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) { 8000390: f107 0314 add.w r3, r7, #20 8000394: 2102 movs r1, #2 8000396: 4618 mov r0, r3 8000398: f001 f9e2 bl 8001760 800039c: 4603 mov r3, r0 800039e: 2b00 cmp r3, #0 80003a0: d001 beq.n 80003a6 Error_Handler(); 80003a2: f000 f812 bl 80003ca } PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC; 80003a6: 2302 movs r3, #2 80003a8: 607b str r3, [r7, #4] PeriphClkInit.AdcClockSelection = RCC_ADCPCLK2_DIV6; 80003aa: f44f 4300 mov.w r3, #32768 ; 0x8000 80003ae: 60fb str r3, [r7, #12] if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) { 80003b0: 1d3b adds r3, r7, #4 80003b2: 4618 mov r0, r3 80003b4: f001 fb6c bl 8001a90 80003b8: 4603 mov r3, r0 80003ba: 2b00 cmp r3, #0 80003bc: d001 beq.n 80003c2 Error_Handler(); 80003be: f000 f804 bl 80003ca } } 80003c2: bf00 nop 80003c4: 3750 adds r7, #80 ; 0x50 80003c6: 46bd mov sp, r7 80003c8: bd80 pop {r7, pc} 080003ca : /** * @brief This function is executed in case of error occurrence. * @retval None */ void Error_Handler(void) { 80003ca: b480 push {r7} 80003cc: af00 add r7, sp, #0 \details Disables IRQ interrupts by setting the I-bit in the CPSR. Can only be executed in Privileged modes. */ __STATIC_FORCEINLINE void __disable_irq(void) { __ASM volatile ("cpsid i" : : : "memory"); 80003ce: b672 cpsid i } 80003d0: bf00 nop /* USER CODE BEGIN Error_Handler_Debug */ /* User can add his own implementation to report the HAL error return state */ __disable_irq(); while (1) { 80003d2: e7fe b.n 80003d2 080003d4 : /* USER CODE END 0 */ /** * Initializes the Global MSP. */ void HAL_MspInit(void) { 80003d4: b480 push {r7} 80003d6: b085 sub sp, #20 80003d8: af00 add r7, sp, #0 /* USER CODE BEGIN MspInit 0 */ /* USER CODE END MspInit 0 */ __HAL_RCC_AFIO_CLK_ENABLE(); 80003da: 4b15 ldr r3, [pc, #84] ; (8000430 ) 80003dc: 699b ldr r3, [r3, #24] 80003de: 4a14 ldr r2, [pc, #80] ; (8000430 ) 80003e0: f043 0301 orr.w r3, r3, #1 80003e4: 6193 str r3, [r2, #24] 80003e6: 4b12 ldr r3, [pc, #72] ; (8000430 ) 80003e8: 699b ldr r3, [r3, #24] 80003ea: f003 0301 and.w r3, r3, #1 80003ee: 60bb str r3, [r7, #8] 80003f0: 68bb ldr r3, [r7, #8] __HAL_RCC_PWR_CLK_ENABLE(); 80003f2: 4b0f ldr r3, [pc, #60] ; (8000430 ) 80003f4: 69db ldr r3, [r3, #28] 80003f6: 4a0e ldr r2, [pc, #56] ; (8000430 ) 80003f8: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 80003fc: 61d3 str r3, [r2, #28] 80003fe: 4b0c ldr r3, [pc, #48] ; (8000430 ) 8000400: 69db ldr r3, [r3, #28] 8000402: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 8000406: 607b str r3, [r7, #4] 8000408: 687b ldr r3, [r7, #4] /* System interrupt init*/ /** NOJTAG: JTAG-DP Disabled and SW-DP Enabled */ __HAL_AFIO_REMAP_SWJ_NOJTAG(); 800040a: 4b0a ldr r3, [pc, #40] ; (8000434 ) 800040c: 685b ldr r3, [r3, #4] 800040e: 60fb str r3, [r7, #12] 8000410: 68fb ldr r3, [r7, #12] 8000412: f023 63e0 bic.w r3, r3, #117440512 ; 0x7000000 8000416: 60fb str r3, [r7, #12] 8000418: 68fb ldr r3, [r7, #12] 800041a: f043 7300 orr.w r3, r3, #33554432 ; 0x2000000 800041e: 60fb str r3, [r7, #12] 8000420: 4a04 ldr r2, [pc, #16] ; (8000434 ) 8000422: 68fb ldr r3, [r7, #12] 8000424: 6053 str r3, [r2, #4] /* USER CODE BEGIN MspInit 1 */ /* USER CODE END MspInit 1 */ } 8000426: bf00 nop 8000428: 3714 adds r7, #20 800042a: 46bd mov sp, r7 800042c: bc80 pop {r7} 800042e: 4770 bx lr 8000430: 40021000 .word 0x40021000 8000434: 40010000 .word 0x40010000 08000438 : /******************************************************************************/ /** * @brief This function handles Non maskable interrupt. */ void NMI_Handler(void) { 8000438: b480 push {r7} 800043a: af00 add r7, sp, #0 /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ /* USER CODE END NonMaskableInt_IRQn 0 */ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ while (1) 800043c: e7fe b.n 800043c 0800043e : /** * @brief This function handles Hard fault interrupt. */ void HardFault_Handler(void) { 800043e: b480 push {r7} 8000440: af00 add r7, sp, #0 /* USER CODE BEGIN HardFault_IRQn 0 */ /* USER CODE END HardFault_IRQn 0 */ while (1) 8000442: e7fe b.n 8000442 08000444 : /** * @brief This function handles Memory management fault. */ void MemManage_Handler(void) { 8000444: b480 push {r7} 8000446: af00 add r7, sp, #0 /* USER CODE BEGIN MemoryManagement_IRQn 0 */ /* USER CODE END MemoryManagement_IRQn 0 */ while (1) 8000448: e7fe b.n 8000448 0800044a : /** * @brief This function handles Prefetch fault, memory access fault. */ void BusFault_Handler(void) { 800044a: b480 push {r7} 800044c: af00 add r7, sp, #0 /* USER CODE BEGIN BusFault_IRQn 0 */ /* USER CODE END BusFault_IRQn 0 */ while (1) 800044e: e7fe b.n 800044e 08000450 : /** * @brief This function handles Undefined instruction or illegal state. */ void UsageFault_Handler(void) { 8000450: b480 push {r7} 8000452: af00 add r7, sp, #0 /* USER CODE BEGIN UsageFault_IRQn 0 */ /* USER CODE END UsageFault_IRQn 0 */ while (1) 8000454: e7fe b.n 8000454 08000456 : /** * @brief This function handles System service call via SWI instruction. */ void SVC_Handler(void) { 8000456: b480 push {r7} 8000458: af00 add r7, sp, #0 /* USER CODE END SVCall_IRQn 0 */ /* USER CODE BEGIN SVCall_IRQn 1 */ /* USER CODE END SVCall_IRQn 1 */ } 800045a: bf00 nop 800045c: 46bd mov sp, r7 800045e: bc80 pop {r7} 8000460: 4770 bx lr 08000462 : /** * @brief This function handles Debug monitor. */ void DebugMon_Handler(void) { 8000462: b480 push {r7} 8000464: af00 add r7, sp, #0 /* USER CODE END DebugMonitor_IRQn 0 */ /* USER CODE BEGIN DebugMonitor_IRQn 1 */ /* USER CODE END DebugMonitor_IRQn 1 */ } 8000466: bf00 nop 8000468: 46bd mov sp, r7 800046a: bc80 pop {r7} 800046c: 4770 bx lr 0800046e : /** * @brief This function handles Pendable request for system service. */ void PendSV_Handler(void) { 800046e: b480 push {r7} 8000470: af00 add r7, sp, #0 /* USER CODE END PendSV_IRQn 0 */ /* USER CODE BEGIN PendSV_IRQn 1 */ /* USER CODE END PendSV_IRQn 1 */ } 8000472: bf00 nop 8000474: 46bd mov sp, r7 8000476: bc80 pop {r7} 8000478: 4770 bx lr 0800047a : /** * @brief This function handles System tick timer. */ void SysTick_Handler(void) { 800047a: b580 push {r7, lr} 800047c: af00 add r7, sp, #0 /* USER CODE BEGIN SysTick_IRQn 0 */ /* USER CODE END SysTick_IRQn 0 */ HAL_IncTick(); 800047e: f000 f91f bl 80006c0 /* USER CODE BEGIN SysTick_IRQn 1 */ /* USER CODE END SysTick_IRQn 1 */ } 8000482: bf00 nop 8000484: bd80 pop {r7, pc} ... 08000488 <_sbrk>: * * @param incr Memory size * @return Pointer to allocated memory */ void *_sbrk(ptrdiff_t incr) { 8000488: b580 push {r7, lr} 800048a: b086 sub sp, #24 800048c: af00 add r7, sp, #0 800048e: 6078 str r0, [r7, #4] extern uint8_t _end; /* Symbol defined in the linker script */ extern uint8_t _estack; /* Symbol defined in the linker script */ extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */ const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size; 8000490: 4a14 ldr r2, [pc, #80] ; (80004e4 <_sbrk+0x5c>) 8000492: 4b15 ldr r3, [pc, #84] ; (80004e8 <_sbrk+0x60>) 8000494: 1ad3 subs r3, r2, r3 8000496: 617b str r3, [r7, #20] const uint8_t *max_heap = (uint8_t *)stack_limit; 8000498: 697b ldr r3, [r7, #20] 800049a: 613b str r3, [r7, #16] uint8_t *prev_heap_end; /* Initialize heap end at first call */ if (NULL == __sbrk_heap_end) 800049c: 4b13 ldr r3, [pc, #76] ; (80004ec <_sbrk+0x64>) 800049e: 681b ldr r3, [r3, #0] 80004a0: 2b00 cmp r3, #0 80004a2: d102 bne.n 80004aa <_sbrk+0x22> { __sbrk_heap_end = &_end; 80004a4: 4b11 ldr r3, [pc, #68] ; (80004ec <_sbrk+0x64>) 80004a6: 4a12 ldr r2, [pc, #72] ; (80004f0 <_sbrk+0x68>) 80004a8: 601a str r2, [r3, #0] } /* Protect heap from growing into the reserved MSP stack */ if (__sbrk_heap_end + incr > max_heap) 80004aa: 4b10 ldr r3, [pc, #64] ; (80004ec <_sbrk+0x64>) 80004ac: 681a ldr r2, [r3, #0] 80004ae: 687b ldr r3, [r7, #4] 80004b0: 4413 add r3, r2 80004b2: 693a ldr r2, [r7, #16] 80004b4: 429a cmp r2, r3 80004b6: d207 bcs.n 80004c8 <_sbrk+0x40> { errno = ENOMEM; 80004b8: f001 fd58 bl 8001f6c <__errno> 80004bc: 4603 mov r3, r0 80004be: 220c movs r2, #12 80004c0: 601a str r2, [r3, #0] return (void *)-1; 80004c2: f04f 33ff mov.w r3, #4294967295 80004c6: e009 b.n 80004dc <_sbrk+0x54> } prev_heap_end = __sbrk_heap_end; 80004c8: 4b08 ldr r3, [pc, #32] ; (80004ec <_sbrk+0x64>) 80004ca: 681b ldr r3, [r3, #0] 80004cc: 60fb str r3, [r7, #12] __sbrk_heap_end += incr; 80004ce: 4b07 ldr r3, [pc, #28] ; (80004ec <_sbrk+0x64>) 80004d0: 681a ldr r2, [r3, #0] 80004d2: 687b ldr r3, [r7, #4] 80004d4: 4413 add r3, r2 80004d6: 4a05 ldr r2, [pc, #20] ; (80004ec <_sbrk+0x64>) 80004d8: 6013 str r3, [r2, #0] return (void *)prev_heap_end; 80004da: 68fb ldr r3, [r7, #12] } 80004dc: 4618 mov r0, r3 80004de: 3718 adds r7, #24 80004e0: 46bd mov sp, r7 80004e2: bd80 pop {r7, pc} 80004e4: 20005000 .word 0x20005000 80004e8: 00000400 .word 0x00000400 80004ec: 200000bc .word 0x200000bc 80004f0: 20000118 .word 0x20000118 080004f4 : * @note This function should be used only after reset. * @param None * @retval None */ void SystemInit (void) { 80004f4: b480 push {r7} 80004f6: af00 add r7, sp, #0 /* Configure the Vector Table location -------------------------------------*/ #if defined(USER_VECT_TAB_ADDRESS) SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ #endif /* USER_VECT_TAB_ADDRESS */ } 80004f8: bf00 nop 80004fa: 46bd mov sp, r7 80004fc: bc80 pop {r7} 80004fe: 4770 bx lr 08000500 : UART_HandleTypeDef huart2; /* USART2 init function */ void MX_USART2_UART_Init(void) { 8000500: b580 push {r7, lr} 8000502: af00 add r7, sp, #0 /* USER CODE END USART2_Init 0 */ /* USER CODE BEGIN USART2_Init 1 */ /* USER CODE END USART2_Init 1 */ huart2.Instance = USART2; 8000504: 4b11 ldr r3, [pc, #68] ; (800054c ) 8000506: 4a12 ldr r2, [pc, #72] ; (8000550 ) 8000508: 601a str r2, [r3, #0] huart2.Init.BaudRate = 115200; 800050a: 4b10 ldr r3, [pc, #64] ; (800054c ) 800050c: f44f 32e1 mov.w r2, #115200 ; 0x1c200 8000510: 605a str r2, [r3, #4] huart2.Init.WordLength = UART_WORDLENGTH_8B; 8000512: 4b0e ldr r3, [pc, #56] ; (800054c ) 8000514: 2200 movs r2, #0 8000516: 609a str r2, [r3, #8] huart2.Init.StopBits = UART_STOPBITS_1; 8000518: 4b0c ldr r3, [pc, #48] ; (800054c ) 800051a: 2200 movs r2, #0 800051c: 60da str r2, [r3, #12] huart2.Init.Parity = UART_PARITY_NONE; 800051e: 4b0b ldr r3, [pc, #44] ; (800054c ) 8000520: 2200 movs r2, #0 8000522: 611a str r2, [r3, #16] huart2.Init.Mode = UART_MODE_TX_RX; 8000524: 4b09 ldr r3, [pc, #36] ; (800054c ) 8000526: 220c movs r2, #12 8000528: 615a str r2, [r3, #20] huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE; 800052a: 4b08 ldr r3, [pc, #32] ; (800054c ) 800052c: 2200 movs r2, #0 800052e: 619a str r2, [r3, #24] huart2.Init.OverSampling = UART_OVERSAMPLING_16; 8000530: 4b06 ldr r3, [pc, #24] ; (800054c ) 8000532: 2200 movs r2, #0 8000534: 61da str r2, [r3, #28] if (HAL_UART_Init(&huart2) != HAL_OK) 8000536: 4805 ldr r0, [pc, #20] ; (800054c ) 8000538: f001 fb60 bl 8001bfc 800053c: 4603 mov r3, r0 800053e: 2b00 cmp r3, #0 8000540: d001 beq.n 8000546 { Error_Handler(); 8000542: f7ff ff42 bl 80003ca } /* USER CODE BEGIN USART2_Init 2 */ /* USER CODE END USART2_Init 2 */ } 8000546: bf00 nop 8000548: bd80 pop {r7, pc} 800054a: bf00 nop 800054c: 200000c0 .word 0x200000c0 8000550: 40004400 .word 0x40004400 08000554 : void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle) { 8000554: b580 push {r7, lr} 8000556: b088 sub sp, #32 8000558: af00 add r7, sp, #0 800055a: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 800055c: f107 0310 add.w r3, r7, #16 8000560: 2200 movs r2, #0 8000562: 601a str r2, [r3, #0] 8000564: 605a str r2, [r3, #4] 8000566: 609a str r2, [r3, #8] 8000568: 60da str r2, [r3, #12] if(uartHandle->Instance==USART2) 800056a: 687b ldr r3, [r7, #4] 800056c: 681b ldr r3, [r3, #0] 800056e: 4a1b ldr r2, [pc, #108] ; (80005dc ) 8000570: 4293 cmp r3, r2 8000572: d12f bne.n 80005d4 { /* USER CODE BEGIN USART2_MspInit 0 */ /* USER CODE END USART2_MspInit 0 */ /* USART2 clock enable */ __HAL_RCC_USART2_CLK_ENABLE(); 8000574: 4b1a ldr r3, [pc, #104] ; (80005e0 ) 8000576: 69db ldr r3, [r3, #28] 8000578: 4a19 ldr r2, [pc, #100] ; (80005e0 ) 800057a: f443 3300 orr.w r3, r3, #131072 ; 0x20000 800057e: 61d3 str r3, [r2, #28] 8000580: 4b17 ldr r3, [pc, #92] ; (80005e0 ) 8000582: 69db ldr r3, [r3, #28] 8000584: f403 3300 and.w r3, r3, #131072 ; 0x20000 8000588: 60fb str r3, [r7, #12] 800058a: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOA_CLK_ENABLE(); 800058c: 4b14 ldr r3, [pc, #80] ; (80005e0 ) 800058e: 699b ldr r3, [r3, #24] 8000590: 4a13 ldr r2, [pc, #76] ; (80005e0 ) 8000592: f043 0304 orr.w r3, r3, #4 8000596: 6193 str r3, [r2, #24] 8000598: 4b11 ldr r3, [pc, #68] ; (80005e0 ) 800059a: 699b ldr r3, [r3, #24] 800059c: f003 0304 and.w r3, r3, #4 80005a0: 60bb str r3, [r7, #8] 80005a2: 68bb ldr r3, [r7, #8] /**USART2 GPIO Configuration PA2 ------> USART2_TX PA3 ------> USART2_RX */ GPIO_InitStruct.Pin = GPIO_PIN_2; 80005a4: 2304 movs r3, #4 80005a6: 613b str r3, [r7, #16] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 80005a8: 2302 movs r3, #2 80005aa: 617b str r3, [r7, #20] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 80005ac: 2303 movs r3, #3 80005ae: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 80005b0: f107 0310 add.w r3, r7, #16 80005b4: 4619 mov r1, r3 80005b6: 480b ldr r0, [pc, #44] ; (80005e4 ) 80005b8: f000 fccc bl 8000f54 GPIO_InitStruct.Pin = GPIO_PIN_3; 80005bc: 2308 movs r3, #8 80005be: 613b str r3, [r7, #16] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 80005c0: 2300 movs r3, #0 80005c2: 617b str r3, [r7, #20] GPIO_InitStruct.Pull = GPIO_NOPULL; 80005c4: 2300 movs r3, #0 80005c6: 61bb str r3, [r7, #24] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 80005c8: f107 0310 add.w r3, r7, #16 80005cc: 4619 mov r1, r3 80005ce: 4805 ldr r0, [pc, #20] ; (80005e4 ) 80005d0: f000 fcc0 bl 8000f54 /* USER CODE BEGIN USART2_MspInit 1 */ /* USER CODE END USART2_MspInit 1 */ } } 80005d4: bf00 nop 80005d6: 3720 adds r7, #32 80005d8: 46bd mov sp, r7 80005da: bd80 pop {r7, pc} 80005dc: 40004400 .word 0x40004400 80005e0: 40021000 .word 0x40021000 80005e4: 40010800 .word 0x40010800 080005e8 : .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata 80005e8: 480c ldr r0, [pc, #48] ; (800061c ) ldr r1, =_edata 80005ea: 490d ldr r1, [pc, #52] ; (8000620 ) ldr r2, =_sidata 80005ec: 4a0d ldr r2, [pc, #52] ; (8000624 ) movs r3, #0 80005ee: 2300 movs r3, #0 b LoopCopyDataInit 80005f0: e002 b.n 80005f8 080005f2 : CopyDataInit: ldr r4, [r2, r3] 80005f2: 58d4 ldr r4, [r2, r3] str r4, [r0, r3] 80005f4: 50c4 str r4, [r0, r3] adds r3, r3, #4 80005f6: 3304 adds r3, #4 080005f8 : LoopCopyDataInit: adds r4, r0, r3 80005f8: 18c4 adds r4, r0, r3 cmp r4, r1 80005fa: 428c cmp r4, r1 bcc CopyDataInit 80005fc: d3f9 bcc.n 80005f2 /* Zero fill the bss segment. */ ldr r2, =_sbss 80005fe: 4a0a ldr r2, [pc, #40] ; (8000628 ) ldr r4, =_ebss 8000600: 4c0a ldr r4, [pc, #40] ; (800062c ) movs r3, #0 8000602: 2300 movs r3, #0 b LoopFillZerobss 8000604: e001 b.n 800060a 08000606 : FillZerobss: str r3, [r2] 8000606: 6013 str r3, [r2, #0] adds r2, r2, #4 8000608: 3204 adds r2, #4 0800060a : LoopFillZerobss: cmp r2, r4 800060a: 42a2 cmp r2, r4 bcc FillZerobss 800060c: d3fb bcc.n 8000606 /* Call the clock system intitialization function.*/ bl SystemInit 800060e: f7ff ff71 bl 80004f4 /* Call static constructors */ bl __libc_init_array 8000612: f001 fcb1 bl 8001f78 <__libc_init_array> /* Call the application's entry point.*/ bl main 8000616: f7ff fe3d bl 8000294
bx lr 800061a: 4770 bx lr ldr r0, =_sdata 800061c: 20000000 .word 0x20000000 ldr r1, =_edata 8000620: 20000070 .word 0x20000070 ldr r2, =_sidata 8000624: 08002948 .word 0x08002948 ldr r2, =_sbss 8000628: 20000070 .word 0x20000070 ldr r4, =_ebss 800062c: 20000118 .word 0x20000118 08000630 : * @retval : None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop 8000630: e7fe b.n 8000630 ... 08000634 : * need to ensure that the SysTick time base is always set to 1 millisecond * to have correct HAL operation. * @retval HAL status */ HAL_StatusTypeDef HAL_Init(void) { 8000634: b580 push {r7, lr} 8000636: af00 add r7, sp, #0 defined(STM32F102x6) || defined(STM32F102xB) || \ defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || \ defined(STM32F105xC) || defined(STM32F107xC) /* Prefetch buffer is not available on value line devices */ __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); 8000638: 4b08 ldr r3, [pc, #32] ; (800065c ) 800063a: 681b ldr r3, [r3, #0] 800063c: 4a07 ldr r2, [pc, #28] ; (800065c ) 800063e: f043 0310 orr.w r3, r3, #16 8000642: 6013 str r3, [r2, #0] #endif #endif /* PREFETCH_ENABLE */ /* Set Interrupt Group Priority */ HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); 8000644: 2003 movs r0, #3 8000646: f000 fc51 bl 8000eec /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ HAL_InitTick(TICK_INT_PRIORITY); 800064a: 200f movs r0, #15 800064c: f000 f808 bl 8000660 /* Init the low level hardware */ HAL_MspInit(); 8000650: f7ff fec0 bl 80003d4 /* Return function status */ return HAL_OK; 8000654: 2300 movs r3, #0 } 8000656: 4618 mov r0, r3 8000658: bd80 pop {r7, pc} 800065a: bf00 nop 800065c: 40022000 .word 0x40022000 08000660 : * implementation in user file. * @param TickPriority Tick interrupt priority. * @retval HAL status */ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { 8000660: b580 push {r7, lr} 8000662: b082 sub sp, #8 8000664: af00 add r7, sp, #0 8000666: 6078 str r0, [r7, #4] /* Configure the SysTick to have interrupt in 1ms time basis*/ if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U) 8000668: 4b12 ldr r3, [pc, #72] ; (80006b4 ) 800066a: 681a ldr r2, [r3, #0] 800066c: 4b12 ldr r3, [pc, #72] ; (80006b8 ) 800066e: 781b ldrb r3, [r3, #0] 8000670: 4619 mov r1, r3 8000672: f44f 737a mov.w r3, #1000 ; 0x3e8 8000676: fbb3 f3f1 udiv r3, r3, r1 800067a: fbb2 f3f3 udiv r3, r2, r3 800067e: 4618 mov r0, r3 8000680: f000 fc5b bl 8000f3a 8000684: 4603 mov r3, r0 8000686: 2b00 cmp r3, #0 8000688: d001 beq.n 800068e { return HAL_ERROR; 800068a: 2301 movs r3, #1 800068c: e00e b.n 80006ac } /* Configure the SysTick IRQ priority */ if (TickPriority < (1UL << __NVIC_PRIO_BITS)) 800068e: 687b ldr r3, [r7, #4] 8000690: 2b0f cmp r3, #15 8000692: d80a bhi.n 80006aa { HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); 8000694: 2200 movs r2, #0 8000696: 6879 ldr r1, [r7, #4] 8000698: f04f 30ff mov.w r0, #4294967295 800069c: f000 fc31 bl 8000f02 uwTickPrio = TickPriority; 80006a0: 4a06 ldr r2, [pc, #24] ; (80006bc ) 80006a2: 687b ldr r3, [r7, #4] 80006a4: 6013 str r3, [r2, #0] { return HAL_ERROR; } /* Return function status */ return HAL_OK; 80006a6: 2300 movs r3, #0 80006a8: e000 b.n 80006ac return HAL_ERROR; 80006aa: 2301 movs r3, #1 } 80006ac: 4618 mov r0, r3 80006ae: 3708 adds r7, #8 80006b0: 46bd mov sp, r7 80006b2: bd80 pop {r7, pc} 80006b4: 20000000 .word 0x20000000 80006b8: 20000008 .word 0x20000008 80006bc: 20000004 .word 0x20000004 080006c0 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ __weak void HAL_IncTick(void) { 80006c0: b480 push {r7} 80006c2: af00 add r7, sp, #0 uwTick += uwTickFreq; 80006c4: 4b05 ldr r3, [pc, #20] ; (80006dc ) 80006c6: 781b ldrb r3, [r3, #0] 80006c8: 461a mov r2, r3 80006ca: 4b05 ldr r3, [pc, #20] ; (80006e0 ) 80006cc: 681b ldr r3, [r3, #0] 80006ce: 4413 add r3, r2 80006d0: 4a03 ldr r2, [pc, #12] ; (80006e0 ) 80006d2: 6013 str r3, [r2, #0] } 80006d4: bf00 nop 80006d6: 46bd mov sp, r7 80006d8: bc80 pop {r7} 80006da: 4770 bx lr 80006dc: 20000008 .word 0x20000008 80006e0: 20000104 .word 0x20000104 080006e4 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval tick value */ __weak uint32_t HAL_GetTick(void) { 80006e4: b480 push {r7} 80006e6: af00 add r7, sp, #0 return uwTick; 80006e8: 4b02 ldr r3, [pc, #8] ; (80006f4 ) 80006ea: 681b ldr r3, [r3, #0] } 80006ec: 4618 mov r0, r3 80006ee: 46bd mov sp, r7 80006f0: bc80 pop {r7} 80006f2: 4770 bx lr 80006f4: 20000104 .word 0x20000104 080006f8 : * implementations in user file. * @param Delay specifies the delay time length, in milliseconds. * @retval None */ __weak void HAL_Delay(uint32_t Delay) { 80006f8: b580 push {r7, lr} 80006fa: b084 sub sp, #16 80006fc: af00 add r7, sp, #0 80006fe: 6078 str r0, [r7, #4] uint32_t tickstart = HAL_GetTick(); 8000700: f7ff fff0 bl 80006e4 8000704: 60b8 str r0, [r7, #8] uint32_t wait = Delay; 8000706: 687b ldr r3, [r7, #4] 8000708: 60fb str r3, [r7, #12] /* Add a freq to guarantee minimum wait */ if (wait < HAL_MAX_DELAY) 800070a: 68fb ldr r3, [r7, #12] 800070c: f1b3 3fff cmp.w r3, #4294967295 8000710: d005 beq.n 800071e { wait += (uint32_t)(uwTickFreq); 8000712: 4b0a ldr r3, [pc, #40] ; (800073c ) 8000714: 781b ldrb r3, [r3, #0] 8000716: 461a mov r2, r3 8000718: 68fb ldr r3, [r7, #12] 800071a: 4413 add r3, r2 800071c: 60fb str r3, [r7, #12] } while ((HAL_GetTick() - tickstart) < wait) 800071e: bf00 nop 8000720: f7ff ffe0 bl 80006e4 8000724: 4602 mov r2, r0 8000726: 68bb ldr r3, [r7, #8] 8000728: 1ad3 subs r3, r2, r3 800072a: 68fa ldr r2, [r7, #12] 800072c: 429a cmp r2, r3 800072e: d8f7 bhi.n 8000720 { } } 8000730: bf00 nop 8000732: bf00 nop 8000734: 3710 adds r7, #16 8000736: 46bd mov sp, r7 8000738: bd80 pop {r7, pc} 800073a: bf00 nop 800073c: 20000008 .word 0x20000008 08000740 : * of structure "ADC_InitTypeDef". * @param hadc: ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) { 8000740: b580 push {r7, lr} 8000742: b086 sub sp, #24 8000744: af00 add r7, sp, #0 8000746: 6078 str r0, [r7, #4] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 8000748: 2300 movs r3, #0 800074a: 75fb strb r3, [r7, #23] uint32_t tmp_cr1 = 0U; 800074c: 2300 movs r3, #0 800074e: 613b str r3, [r7, #16] uint32_t tmp_cr2 = 0U; 8000750: 2300 movs r3, #0 8000752: 60bb str r3, [r7, #8] uint32_t tmp_sqr1 = 0U; 8000754: 2300 movs r3, #0 8000756: 60fb str r3, [r7, #12] /* Check ADC handle */ if(hadc == NULL) 8000758: 687b ldr r3, [r7, #4] 800075a: 2b00 cmp r3, #0 800075c: d101 bne.n 8000762 { return HAL_ERROR; 800075e: 2301 movs r3, #1 8000760: e0be b.n 80008e0 assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign)); assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode)); assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); assert_param(IS_ADC_EXTTRIG(hadc->Init.ExternalTrigConv)); if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE) 8000762: 687b ldr r3, [r7, #4] 8000764: 689b ldr r3, [r3, #8] 8000766: 2b00 cmp r3, #0 /* Refer to header of this file for more details on clock enabling */ /* procedure. */ /* Actions performed only if ADC is coming from state reset: */ /* - Initialization of ADC MSP */ if (hadc->State == HAL_ADC_STATE_RESET) 8000768: 687b ldr r3, [r7, #4] 800076a: 6a9b ldr r3, [r3, #40] ; 0x28 800076c: 2b00 cmp r3, #0 800076e: d109 bne.n 8000784 { /* Initialize ADC error code */ ADC_CLEAR_ERRORCODE(hadc); 8000770: 687b ldr r3, [r7, #4] 8000772: 2200 movs r2, #0 8000774: 62da str r2, [r3, #44] ; 0x2c /* Allocate lock resource and initialize it */ hadc->Lock = HAL_UNLOCKED; 8000776: 687b ldr r3, [r7, #4] 8000778: 2200 movs r2, #0 800077a: f883 2024 strb.w r2, [r3, #36] ; 0x24 /* Init the low level hardware */ hadc->MspInitCallback(hadc); #else /* Init the low level hardware */ HAL_ADC_MspInit(hadc); 800077e: 6878 ldr r0, [r7, #4] 8000780: f7ff fd2a bl 80001d8 /* Stop potential conversion on going, on regular and injected groups */ /* Disable ADC peripheral */ /* Note: In case of ADC already enabled, precaution to not launch an */ /* unwanted conversion while modifying register CR2 by writing 1 to */ /* bit ADON. */ tmp_hal_status = ADC_ConversionStop_Disable(hadc); 8000784: 6878 ldr r0, [r7, #4] 8000786: f000 fabf bl 8000d08 800078a: 4603 mov r3, r0 800078c: 75fb strb r3, [r7, #23] /* Configuration of ADC parameters if previous preliminary actions are */ /* correctly completed. */ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) && 800078e: 687b ldr r3, [r7, #4] 8000790: 6a9b ldr r3, [r3, #40] ; 0x28 8000792: f003 0310 and.w r3, r3, #16 8000796: 2b00 cmp r3, #0 8000798: f040 8099 bne.w 80008ce 800079c: 7dfb ldrb r3, [r7, #23] 800079e: 2b00 cmp r3, #0 80007a0: f040 8095 bne.w 80008ce (tmp_hal_status == HAL_OK) ) { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, 80007a4: 687b ldr r3, [r7, #4] 80007a6: 6a9b ldr r3, [r3, #40] ; 0x28 80007a8: f423 5388 bic.w r3, r3, #4352 ; 0x1100 80007ac: f023 0302 bic.w r3, r3, #2 80007b0: f043 0202 orr.w r2, r3, #2 80007b4: 687b ldr r3, [r7, #4] 80007b6: 629a str r2, [r3, #40] ; 0x28 /* - continuous conversion mode */ /* Note: External trigger polarity (ADC_CR2_EXTTRIG) is set into */ /* HAL_ADC_Start_xxx functions because if set in this function, */ /* a conversion on injected group would start a conversion also on */ /* regular group after ADC enabling. */ tmp_cr2 |= (hadc->Init.DataAlign | 80007b8: 687b ldr r3, [r7, #4] 80007ba: 685a ldr r2, [r3, #4] ADC_CFGR_EXTSEL(hadc, hadc->Init.ExternalTrigConv) | 80007bc: 687b ldr r3, [r7, #4] 80007be: 69db ldr r3, [r3, #28] tmp_cr2 |= (hadc->Init.DataAlign | 80007c0: 431a orrs r2, r3 ADC_CR2_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) ); 80007c2: 687b ldr r3, [r7, #4] 80007c4: 7b1b ldrb r3, [r3, #12] 80007c6: 005b lsls r3, r3, #1 ADC_CFGR_EXTSEL(hadc, hadc->Init.ExternalTrigConv) | 80007c8: 4313 orrs r3, r2 tmp_cr2 |= (hadc->Init.DataAlign | 80007ca: 68ba ldr r2, [r7, #8] 80007cc: 4313 orrs r3, r2 80007ce: 60bb str r3, [r7, #8] /* Configuration of ADC: */ /* - scan mode */ /* - discontinuous mode disable/enable */ /* - discontinuous mode number of conversions */ tmp_cr1 |= (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode)); 80007d0: 687b ldr r3, [r7, #4] 80007d2: 689b ldr r3, [r3, #8] 80007d4: f5b3 7f80 cmp.w r3, #256 ; 0x100 80007d8: d003 beq.n 80007e2 80007da: 687b ldr r3, [r7, #4] 80007dc: 689b ldr r3, [r3, #8] 80007de: 2b01 cmp r3, #1 80007e0: d102 bne.n 80007e8 80007e2: f44f 7380 mov.w r3, #256 ; 0x100 80007e6: e000 b.n 80007ea 80007e8: 2300 movs r3, #0 80007ea: 693a ldr r2, [r7, #16] 80007ec: 4313 orrs r3, r2 80007ee: 613b str r3, [r7, #16] /* Enable discontinuous mode only if continuous mode is disabled */ /* Note: If parameter "Init.ScanConvMode" is set to disable, parameter */ /* discontinuous is set anyway, but will have no effect on ADC HW. */ if (hadc->Init.DiscontinuousConvMode == ENABLE) 80007f0: 687b ldr r3, [r7, #4] 80007f2: 7d1b ldrb r3, [r3, #20] 80007f4: 2b01 cmp r3, #1 80007f6: d119 bne.n 800082c { if (hadc->Init.ContinuousConvMode == DISABLE) 80007f8: 687b ldr r3, [r7, #4] 80007fa: 7b1b ldrb r3, [r3, #12] 80007fc: 2b00 cmp r3, #0 80007fe: d109 bne.n 8000814 { /* Enable the selected ADC regular discontinuous mode */ /* Set the number of channels to be converted in discontinuous mode */ SET_BIT(tmp_cr1, ADC_CR1_DISCEN | 8000800: 687b ldr r3, [r7, #4] 8000802: 699b ldr r3, [r3, #24] 8000804: 3b01 subs r3, #1 8000806: 035a lsls r2, r3, #13 8000808: 693b ldr r3, [r7, #16] 800080a: 4313 orrs r3, r2 800080c: f443 6300 orr.w r3, r3, #2048 ; 0x800 8000810: 613b str r3, [r7, #16] 8000812: e00b b.n 800082c { /* ADC regular group settings continuous and sequencer discontinuous*/ /* cannot be enabled simultaneously. */ /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 8000814: 687b ldr r3, [r7, #4] 8000816: 6a9b ldr r3, [r3, #40] ; 0x28 8000818: f043 0220 orr.w r2, r3, #32 800081c: 687b ldr r3, [r7, #4] 800081e: 629a str r2, [r3, #40] ; 0x28 /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 8000820: 687b ldr r3, [r7, #4] 8000822: 6adb ldr r3, [r3, #44] ; 0x2c 8000824: f043 0201 orr.w r2, r3, #1 8000828: 687b ldr r3, [r7, #4] 800082a: 62da str r2, [r3, #44] ; 0x2c } } /* Update ADC configuration register CR1 with previous settings */ MODIFY_REG(hadc->Instance->CR1, 800082c: 687b ldr r3, [r7, #4] 800082e: 681b ldr r3, [r3, #0] 8000830: 685b ldr r3, [r3, #4] 8000832: f423 4169 bic.w r1, r3, #59648 ; 0xe900 8000836: 687b ldr r3, [r7, #4] 8000838: 681b ldr r3, [r3, #0] 800083a: 693a ldr r2, [r7, #16] 800083c: 430a orrs r2, r1 800083e: 605a str r2, [r3, #4] ADC_CR1_DISCEN | ADC_CR1_DISCNUM , tmp_cr1 ); /* Update ADC configuration register CR2 with previous settings */ MODIFY_REG(hadc->Instance->CR2, 8000840: 687b ldr r3, [r7, #4] 8000842: 681b ldr r3, [r3, #0] 8000844: 689a ldr r2, [r3, #8] 8000846: 4b28 ldr r3, [pc, #160] ; (80008e8 ) 8000848: 4013 ands r3, r2 800084a: 687a ldr r2, [r7, #4] 800084c: 6812 ldr r2, [r2, #0] 800084e: 68b9 ldr r1, [r7, #8] 8000850: 430b orrs r3, r1 8000852: 6093 str r3, [r2, #8] /* Note: Scan mode is present by hardware on this device and, if */ /* disabled, discards automatically nb of conversions. Anyway, nb of */ /* conversions is forced to 0x00 for alignment over all STM32 devices. */ /* - if scan mode is enabled, regular channels sequence length is set to */ /* parameter "NbrOfConversion" */ if (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode) == ADC_SCAN_ENABLE) 8000854: 687b ldr r3, [r7, #4] 8000856: 689b ldr r3, [r3, #8] 8000858: f5b3 7f80 cmp.w r3, #256 ; 0x100 800085c: d003 beq.n 8000866 800085e: 687b ldr r3, [r7, #4] 8000860: 689b ldr r3, [r3, #8] 8000862: 2b01 cmp r3, #1 8000864: d104 bne.n 8000870 { tmp_sqr1 = ADC_SQR1_L_SHIFT(hadc->Init.NbrOfConversion); 8000866: 687b ldr r3, [r7, #4] 8000868: 691b ldr r3, [r3, #16] 800086a: 3b01 subs r3, #1 800086c: 051b lsls r3, r3, #20 800086e: 60fb str r3, [r7, #12] } MODIFY_REG(hadc->Instance->SQR1, 8000870: 687b ldr r3, [r7, #4] 8000872: 681b ldr r3, [r3, #0] 8000874: 6adb ldr r3, [r3, #44] ; 0x2c 8000876: f423 0170 bic.w r1, r3, #15728640 ; 0xf00000 800087a: 687b ldr r3, [r7, #4] 800087c: 681b ldr r3, [r3, #0] 800087e: 68fa ldr r2, [r7, #12] 8000880: 430a orrs r2, r1 8000882: 62da str r2, [r3, #44] ; 0x2c /* ensure of no potential problem of ADC core IP clocking. */ /* Check through register CR2 (excluding bits set in other functions: */ /* execution control bits (ADON, JSWSTART, SWSTART), regular group bits */ /* (DMA), injected group bits (JEXTTRIG and JEXTSEL), channel internal */ /* measurement path bit (TSVREFE). */ if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA | 8000884: 687b ldr r3, [r7, #4] 8000886: 681b ldr r3, [r3, #0] 8000888: 689a ldr r2, [r3, #8] 800088a: 4b18 ldr r3, [pc, #96] ; (80008ec ) 800088c: 4013 ands r3, r2 800088e: 68ba ldr r2, [r7, #8] 8000890: 429a cmp r2, r3 8000892: d10b bne.n 80008ac ADC_CR2_JEXTTRIG | ADC_CR2_JEXTSEL | ADC_CR2_TSVREFE )) == tmp_cr2) { /* Set ADC error code to none */ ADC_CLEAR_ERRORCODE(hadc); 8000894: 687b ldr r3, [r7, #4] 8000896: 2200 movs r2, #0 8000898: 62da str r2, [r3, #44] ; 0x2c /* Set the ADC state */ ADC_STATE_CLR_SET(hadc->State, 800089a: 687b ldr r3, [r7, #4] 800089c: 6a9b ldr r3, [r3, #40] ; 0x28 800089e: f023 0303 bic.w r3, r3, #3 80008a2: f043 0201 orr.w r2, r3, #1 80008a6: 687b ldr r3, [r7, #4] 80008a8: 629a str r2, [r3, #40] ; 0x28 if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA | 80008aa: e018 b.n 80008de HAL_ADC_STATE_READY); } else { /* Update ADC state machine to error */ ADC_STATE_CLR_SET(hadc->State, 80008ac: 687b ldr r3, [r7, #4] 80008ae: 6a9b ldr r3, [r3, #40] ; 0x28 80008b0: f023 0312 bic.w r3, r3, #18 80008b4: f043 0210 orr.w r2, r3, #16 80008b8: 687b ldr r3, [r7, #4] 80008ba: 629a str r2, [r3, #40] ; 0x28 HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL); /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 80008bc: 687b ldr r3, [r7, #4] 80008be: 6adb ldr r3, [r3, #44] ; 0x2c 80008c0: f043 0201 orr.w r2, r3, #1 80008c4: 687b ldr r3, [r7, #4] 80008c6: 62da str r2, [r3, #44] ; 0x2c tmp_hal_status = HAL_ERROR; 80008c8: 2301 movs r3, #1 80008ca: 75fb strb r3, [r7, #23] if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA | 80008cc: e007 b.n 80008de } else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 80008ce: 687b ldr r3, [r7, #4] 80008d0: 6a9b ldr r3, [r3, #40] ; 0x28 80008d2: f043 0210 orr.w r2, r3, #16 80008d6: 687b ldr r3, [r7, #4] 80008d8: 629a str r2, [r3, #40] ; 0x28 tmp_hal_status = HAL_ERROR; 80008da: 2301 movs r3, #1 80008dc: 75fb strb r3, [r7, #23] } /* Return function status */ return tmp_hal_status; 80008de: 7dfb ldrb r3, [r7, #23] } 80008e0: 4618 mov r0, r3 80008e2: 3718 adds r7, #24 80008e4: 46bd mov sp, r7 80008e6: bd80 pop {r7, pc} 80008e8: ffe1f7fd .word 0xffe1f7fd 80008ec: ff1f0efe .word 0xff1f0efe 080008f0 : * Interruptions enabled in this function: None. * @param hadc: ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc) { 80008f0: b580 push {r7, lr} 80008f2: b084 sub sp, #16 80008f4: af00 add r7, sp, #0 80008f6: 6078 str r0, [r7, #4] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 80008f8: 2300 movs r3, #0 80008fa: 73fb strb r3, [r7, #15] /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Process locked */ __HAL_LOCK(hadc); 80008fc: 687b ldr r3, [r7, #4] 80008fe: f893 3024 ldrb.w r3, [r3, #36] ; 0x24 8000902: 2b01 cmp r3, #1 8000904: d101 bne.n 800090a 8000906: 2302 movs r3, #2 8000908: e098 b.n 8000a3c 800090a: 687b ldr r3, [r7, #4] 800090c: 2201 movs r2, #1 800090e: f883 2024 strb.w r2, [r3, #36] ; 0x24 /* Enable the ADC peripheral */ tmp_hal_status = ADC_Enable(hadc); 8000912: 6878 ldr r0, [r7, #4] 8000914: f000 f99e bl 8000c54 8000918: 4603 mov r3, r0 800091a: 73fb strb r3, [r7, #15] /* Start conversion if ADC is effectively enabled */ if (tmp_hal_status == HAL_OK) 800091c: 7bfb ldrb r3, [r7, #15] 800091e: 2b00 cmp r3, #0 8000920: f040 8087 bne.w 8000a32 { /* Set ADC state */ /* - Clear state bitfield related to regular group conversion results */ /* - Set state bitfield related to regular operation */ ADC_STATE_CLR_SET(hadc->State, 8000924: 687b ldr r3, [r7, #4] 8000926: 6a9b ldr r3, [r3, #40] ; 0x28 8000928: f423 7340 bic.w r3, r3, #768 ; 0x300 800092c: f023 0301 bic.w r3, r3, #1 8000930: f443 7280 orr.w r2, r3, #256 ; 0x100 8000934: 687b ldr r3, [r7, #4] 8000936: 629a str r2, [r3, #40] ; 0x28 HAL_ADC_STATE_REG_BUSY); /* Set group injected state (from auto-injection) and multimode state */ /* for all cases of multimode: independent mode, multimode ADC master */ /* or multimode ADC slave (for devices with several ADCs): */ if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc)) 8000938: 687b ldr r3, [r7, #4] 800093a: 681b ldr r3, [r3, #0] 800093c: 4a41 ldr r2, [pc, #260] ; (8000a44 ) 800093e: 4293 cmp r3, r2 8000940: d105 bne.n 800094e 8000942: 4b41 ldr r3, [pc, #260] ; (8000a48 ) 8000944: 685b ldr r3, [r3, #4] 8000946: f403 2370 and.w r3, r3, #983040 ; 0xf0000 800094a: 2b00 cmp r3, #0 800094c: d115 bne.n 800097a { /* Set ADC state (ADC independent or master) */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); 800094e: 687b ldr r3, [r7, #4] 8000950: 6a9b ldr r3, [r3, #40] ; 0x28 8000952: f423 1280 bic.w r2, r3, #1048576 ; 0x100000 8000956: 687b ldr r3, [r7, #4] 8000958: 629a str r2, [r3, #40] ; 0x28 /* If conversions on group regular are also triggering group injected, */ /* update ADC state. */ if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET) 800095a: 687b ldr r3, [r7, #4] 800095c: 681b ldr r3, [r3, #0] 800095e: 685b ldr r3, [r3, #4] 8000960: f403 6380 and.w r3, r3, #1024 ; 0x400 8000964: 2b00 cmp r3, #0 8000966: d026 beq.n 80009b6 { ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); 8000968: 687b ldr r3, [r7, #4] 800096a: 6a9b ldr r3, [r3, #40] ; 0x28 800096c: f423 5340 bic.w r3, r3, #12288 ; 0x3000 8000970: f443 5280 orr.w r2, r3, #4096 ; 0x1000 8000974: 687b ldr r3, [r7, #4] 8000976: 629a str r2, [r3, #40] ; 0x28 if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET) 8000978: e01d b.n 80009b6 } } else { /* Set ADC state (ADC slave) */ SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); 800097a: 687b ldr r3, [r7, #4] 800097c: 6a9b ldr r3, [r3, #40] ; 0x28 800097e: f443 1280 orr.w r2, r3, #1048576 ; 0x100000 8000982: 687b ldr r3, [r7, #4] 8000984: 629a str r2, [r3, #40] ; 0x28 /* If conversions on group regular are also triggering group injected, */ /* update ADC state. */ if (ADC_MULTIMODE_AUTO_INJECTED(hadc)) 8000986: 687b ldr r3, [r7, #4] 8000988: 681b ldr r3, [r3, #0] 800098a: 4a2f ldr r2, [pc, #188] ; (8000a48 ) 800098c: 4293 cmp r3, r2 800098e: d004 beq.n 800099a 8000990: 687b ldr r3, [r7, #4] 8000992: 681b ldr r3, [r3, #0] 8000994: 4a2b ldr r2, [pc, #172] ; (8000a44 ) 8000996: 4293 cmp r3, r2 8000998: d10d bne.n 80009b6 800099a: 4b2b ldr r3, [pc, #172] ; (8000a48 ) 800099c: 685b ldr r3, [r3, #4] 800099e: f403 6380 and.w r3, r3, #1024 ; 0x400 80009a2: 2b00 cmp r3, #0 80009a4: d007 beq.n 80009b6 { ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); 80009a6: 687b ldr r3, [r7, #4] 80009a8: 6a9b ldr r3, [r3, #40] ; 0x28 80009aa: f423 5340 bic.w r3, r3, #12288 ; 0x3000 80009ae: f443 5280 orr.w r2, r3, #4096 ; 0x1000 80009b2: 687b ldr r3, [r7, #4] 80009b4: 629a str r2, [r3, #40] ; 0x28 } } /* State machine update: Check if an injected conversion is ongoing */ if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) 80009b6: 687b ldr r3, [r7, #4] 80009b8: 6a9b ldr r3, [r3, #40] ; 0x28 80009ba: f403 5380 and.w r3, r3, #4096 ; 0x1000 80009be: 2b00 cmp r3, #0 80009c0: d006 beq.n 80009d0 { /* Reset ADC error code fields related to conversions on group regular */ CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); 80009c2: 687b ldr r3, [r7, #4] 80009c4: 6adb ldr r3, [r3, #44] ; 0x2c 80009c6: f023 0206 bic.w r2, r3, #6 80009ca: 687b ldr r3, [r7, #4] 80009cc: 62da str r2, [r3, #44] ; 0x2c 80009ce: e002 b.n 80009d6 } else { /* Reset ADC all error code fields */ ADC_CLEAR_ERRORCODE(hadc); 80009d0: 687b ldr r3, [r7, #4] 80009d2: 2200 movs r2, #0 80009d4: 62da str r2, [r3, #44] ; 0x2c } /* Process unlocked */ /* Unlock before starting ADC conversions: in case of potential */ /* interruption, to let the process to ADC IRQ Handler. */ __HAL_UNLOCK(hadc); 80009d6: 687b ldr r3, [r7, #4] 80009d8: 2200 movs r2, #0 80009da: f883 2024 strb.w r2, [r3, #36] ; 0x24 /* Clear regular group conversion flag */ /* (To ensure of no unknown state from potential previous ADC operations) */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC); 80009de: 687b ldr r3, [r7, #4] 80009e0: 681b ldr r3, [r3, #0] 80009e2: f06f 0202 mvn.w r2, #2 80009e6: 601a str r2, [r3, #0] /* - if ADC is slave, ADC is enabled only (conversion is not started). */ /* - if ADC is master, ADC is enabled and conversion is started. */ /* If ADC is master, ADC is enabled and conversion is started. */ /* Note: Alternate trigger for single conversion could be to force an */ /* additional set of bit ADON "hadc->Instance->CR2 |= ADC_CR2_ADON;"*/ if (ADC_IS_SOFTWARE_START_REGULAR(hadc) && 80009e8: 687b ldr r3, [r7, #4] 80009ea: 681b ldr r3, [r3, #0] 80009ec: 689b ldr r3, [r3, #8] 80009ee: f403 2360 and.w r3, r3, #917504 ; 0xe0000 80009f2: f5b3 2f60 cmp.w r3, #917504 ; 0xe0000 80009f6: d113 bne.n 8000a20 ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc) ) 80009f8: 687b ldr r3, [r7, #4] 80009fa: 681b ldr r3, [r3, #0] if (ADC_IS_SOFTWARE_START_REGULAR(hadc) && 80009fc: 4a11 ldr r2, [pc, #68] ; (8000a44 ) 80009fe: 4293 cmp r3, r2 8000a00: d105 bne.n 8000a0e ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc) ) 8000a02: 4b11 ldr r3, [pc, #68] ; (8000a48 ) 8000a04: 685b ldr r3, [r3, #4] 8000a06: f403 2370 and.w r3, r3, #983040 ; 0xf0000 if (ADC_IS_SOFTWARE_START_REGULAR(hadc) && 8000a0a: 2b00 cmp r3, #0 8000a0c: d108 bne.n 8000a20 { /* Start ADC conversion on regular group with SW start */ SET_BIT(hadc->Instance->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTTRIG)); 8000a0e: 687b ldr r3, [r7, #4] 8000a10: 681b ldr r3, [r3, #0] 8000a12: 689a ldr r2, [r3, #8] 8000a14: 687b ldr r3, [r7, #4] 8000a16: 681b ldr r3, [r3, #0] 8000a18: f442 02a0 orr.w r2, r2, #5242880 ; 0x500000 8000a1c: 609a str r2, [r3, #8] 8000a1e: e00c b.n 8000a3a } else { /* Start ADC conversion on regular group with external trigger */ SET_BIT(hadc->Instance->CR2, ADC_CR2_EXTTRIG); 8000a20: 687b ldr r3, [r7, #4] 8000a22: 681b ldr r3, [r3, #0] 8000a24: 689a ldr r2, [r3, #8] 8000a26: 687b ldr r3, [r7, #4] 8000a28: 681b ldr r3, [r3, #0] 8000a2a: f442 1280 orr.w r2, r2, #1048576 ; 0x100000 8000a2e: 609a str r2, [r3, #8] 8000a30: e003 b.n 8000a3a } } else { /* Process unlocked */ __HAL_UNLOCK(hadc); 8000a32: 687b ldr r3, [r7, #4] 8000a34: 2200 movs r2, #0 8000a36: f883 2024 strb.w r2, [r3, #36] ; 0x24 } /* Return function status */ return tmp_hal_status; 8000a3a: 7bfb ldrb r3, [r7, #15] } 8000a3c: 4618 mov r0, r3 8000a3e: 3710 adds r7, #16 8000a40: 46bd mov sp, r7 8000a42: bd80 pop {r7, pc} 8000a44: 40012800 .word 0x40012800 8000a48: 40012400 .word 0x40012400 08000a4c : * or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_EOS). * @param hadc: ADC handle * @retval ADC group regular conversion data */ uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc) { 8000a4c: b480 push {r7} 8000a4e: b083 sub sp, #12 8000a50: af00 add r7, sp, #0 8000a52: 6078 str r0, [r7, #4] /* Note: EOC flag is not cleared here by software because automatically */ /* cleared by hardware when reading register DR. */ /* Return ADC converted value */ return hadc->Instance->DR; 8000a54: 687b ldr r3, [r7, #4] 8000a56: 681b ldr r3, [r3, #0] 8000a58: 6cdb ldr r3, [r3, #76] ; 0x4c } 8000a5a: 4618 mov r0, r3 8000a5c: 370c adds r7, #12 8000a5e: 46bd mov sp, r7 8000a60: bc80 pop {r7} 8000a62: 4770 bx lr 08000a64 : * @param hadc: ADC handle * @param sConfig: Structure of ADC channel for regular group. * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig) { 8000a64: b480 push {r7} 8000a66: b085 sub sp, #20 8000a68: af00 add r7, sp, #0 8000a6a: 6078 str r0, [r7, #4] 8000a6c: 6039 str r1, [r7, #0] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 8000a6e: 2300 movs r3, #0 8000a70: 73fb strb r3, [r7, #15] __IO uint32_t wait_loop_index = 0U; 8000a72: 2300 movs r3, #0 8000a74: 60bb str r3, [r7, #8] assert_param(IS_ADC_CHANNEL(sConfig->Channel)); assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank)); assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime)); /* Process locked */ __HAL_LOCK(hadc); 8000a76: 687b ldr r3, [r7, #4] 8000a78: f893 3024 ldrb.w r3, [r3, #36] ; 0x24 8000a7c: 2b01 cmp r3, #1 8000a7e: d101 bne.n 8000a84 8000a80: 2302 movs r3, #2 8000a82: e0dc b.n 8000c3e 8000a84: 687b ldr r3, [r7, #4] 8000a86: 2201 movs r2, #1 8000a88: f883 2024 strb.w r2, [r3, #36] ; 0x24 /* Regular sequence configuration */ /* For Rank 1 to 6 */ if (sConfig->Rank < 7U) 8000a8c: 683b ldr r3, [r7, #0] 8000a8e: 685b ldr r3, [r3, #4] 8000a90: 2b06 cmp r3, #6 8000a92: d81c bhi.n 8000ace { MODIFY_REG(hadc->Instance->SQR3 , 8000a94: 687b ldr r3, [r7, #4] 8000a96: 681b ldr r3, [r3, #0] 8000a98: 6b59 ldr r1, [r3, #52] ; 0x34 8000a9a: 683b ldr r3, [r7, #0] 8000a9c: 685a ldr r2, [r3, #4] 8000a9e: 4613 mov r3, r2 8000aa0: 009b lsls r3, r3, #2 8000aa2: 4413 add r3, r2 8000aa4: 3b05 subs r3, #5 8000aa6: 221f movs r2, #31 8000aa8: fa02 f303 lsl.w r3, r2, r3 8000aac: 43db mvns r3, r3 8000aae: 4019 ands r1, r3 8000ab0: 683b ldr r3, [r7, #0] 8000ab2: 6818 ldr r0, [r3, #0] 8000ab4: 683b ldr r3, [r7, #0] 8000ab6: 685a ldr r2, [r3, #4] 8000ab8: 4613 mov r3, r2 8000aba: 009b lsls r3, r3, #2 8000abc: 4413 add r3, r2 8000abe: 3b05 subs r3, #5 8000ac0: fa00 f203 lsl.w r2, r0, r3 8000ac4: 687b ldr r3, [r7, #4] 8000ac6: 681b ldr r3, [r3, #0] 8000ac8: 430a orrs r2, r1 8000aca: 635a str r2, [r3, #52] ; 0x34 8000acc: e03c b.n 8000b48 ADC_SQR3_RK(ADC_SQR3_SQ1, sConfig->Rank) , ADC_SQR3_RK(sConfig->Channel, sConfig->Rank) ); } /* For Rank 7 to 12 */ else if (sConfig->Rank < 13U) 8000ace: 683b ldr r3, [r7, #0] 8000ad0: 685b ldr r3, [r3, #4] 8000ad2: 2b0c cmp r3, #12 8000ad4: d81c bhi.n 8000b10 { MODIFY_REG(hadc->Instance->SQR2 , 8000ad6: 687b ldr r3, [r7, #4] 8000ad8: 681b ldr r3, [r3, #0] 8000ada: 6b19 ldr r1, [r3, #48] ; 0x30 8000adc: 683b ldr r3, [r7, #0] 8000ade: 685a ldr r2, [r3, #4] 8000ae0: 4613 mov r3, r2 8000ae2: 009b lsls r3, r3, #2 8000ae4: 4413 add r3, r2 8000ae6: 3b23 subs r3, #35 ; 0x23 8000ae8: 221f movs r2, #31 8000aea: fa02 f303 lsl.w r3, r2, r3 8000aee: 43db mvns r3, r3 8000af0: 4019 ands r1, r3 8000af2: 683b ldr r3, [r7, #0] 8000af4: 6818 ldr r0, [r3, #0] 8000af6: 683b ldr r3, [r7, #0] 8000af8: 685a ldr r2, [r3, #4] 8000afa: 4613 mov r3, r2 8000afc: 009b lsls r3, r3, #2 8000afe: 4413 add r3, r2 8000b00: 3b23 subs r3, #35 ; 0x23 8000b02: fa00 f203 lsl.w r2, r0, r3 8000b06: 687b ldr r3, [r7, #4] 8000b08: 681b ldr r3, [r3, #0] 8000b0a: 430a orrs r2, r1 8000b0c: 631a str r2, [r3, #48] ; 0x30 8000b0e: e01b b.n 8000b48 ADC_SQR2_RK(sConfig->Channel, sConfig->Rank) ); } /* For Rank 13 to 16 */ else { MODIFY_REG(hadc->Instance->SQR1 , 8000b10: 687b ldr r3, [r7, #4] 8000b12: 681b ldr r3, [r3, #0] 8000b14: 6ad9 ldr r1, [r3, #44] ; 0x2c 8000b16: 683b ldr r3, [r7, #0] 8000b18: 685a ldr r2, [r3, #4] 8000b1a: 4613 mov r3, r2 8000b1c: 009b lsls r3, r3, #2 8000b1e: 4413 add r3, r2 8000b20: 3b41 subs r3, #65 ; 0x41 8000b22: 221f movs r2, #31 8000b24: fa02 f303 lsl.w r3, r2, r3 8000b28: 43db mvns r3, r3 8000b2a: 4019 ands r1, r3 8000b2c: 683b ldr r3, [r7, #0] 8000b2e: 6818 ldr r0, [r3, #0] 8000b30: 683b ldr r3, [r7, #0] 8000b32: 685a ldr r2, [r3, #4] 8000b34: 4613 mov r3, r2 8000b36: 009b lsls r3, r3, #2 8000b38: 4413 add r3, r2 8000b3a: 3b41 subs r3, #65 ; 0x41 8000b3c: fa00 f203 lsl.w r2, r0, r3 8000b40: 687b ldr r3, [r7, #4] 8000b42: 681b ldr r3, [r3, #0] 8000b44: 430a orrs r2, r1 8000b46: 62da str r2, [r3, #44] ; 0x2c } /* Channel sampling time configuration */ /* For channels 10 to 17 */ if (sConfig->Channel >= ADC_CHANNEL_10) 8000b48: 683b ldr r3, [r7, #0] 8000b4a: 681b ldr r3, [r3, #0] 8000b4c: 2b09 cmp r3, #9 8000b4e: d91c bls.n 8000b8a { MODIFY_REG(hadc->Instance->SMPR1 , 8000b50: 687b ldr r3, [r7, #4] 8000b52: 681b ldr r3, [r3, #0] 8000b54: 68d9 ldr r1, [r3, #12] 8000b56: 683b ldr r3, [r7, #0] 8000b58: 681a ldr r2, [r3, #0] 8000b5a: 4613 mov r3, r2 8000b5c: 005b lsls r3, r3, #1 8000b5e: 4413 add r3, r2 8000b60: 3b1e subs r3, #30 8000b62: 2207 movs r2, #7 8000b64: fa02 f303 lsl.w r3, r2, r3 8000b68: 43db mvns r3, r3 8000b6a: 4019 ands r1, r3 8000b6c: 683b ldr r3, [r7, #0] 8000b6e: 6898 ldr r0, [r3, #8] 8000b70: 683b ldr r3, [r7, #0] 8000b72: 681a ldr r2, [r3, #0] 8000b74: 4613 mov r3, r2 8000b76: 005b lsls r3, r3, #1 8000b78: 4413 add r3, r2 8000b7a: 3b1e subs r3, #30 8000b7c: fa00 f203 lsl.w r2, r0, r3 8000b80: 687b ldr r3, [r7, #4] 8000b82: 681b ldr r3, [r3, #0] 8000b84: 430a orrs r2, r1 8000b86: 60da str r2, [r3, #12] 8000b88: e019 b.n 8000bbe ADC_SMPR1(ADC_SMPR1_SMP10, sConfig->Channel) , ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel) ); } else /* For channels 0 to 9 */ { MODIFY_REG(hadc->Instance->SMPR2 , 8000b8a: 687b ldr r3, [r7, #4] 8000b8c: 681b ldr r3, [r3, #0] 8000b8e: 6919 ldr r1, [r3, #16] 8000b90: 683b ldr r3, [r7, #0] 8000b92: 681a ldr r2, [r3, #0] 8000b94: 4613 mov r3, r2 8000b96: 005b lsls r3, r3, #1 8000b98: 4413 add r3, r2 8000b9a: 2207 movs r2, #7 8000b9c: fa02 f303 lsl.w r3, r2, r3 8000ba0: 43db mvns r3, r3 8000ba2: 4019 ands r1, r3 8000ba4: 683b ldr r3, [r7, #0] 8000ba6: 6898 ldr r0, [r3, #8] 8000ba8: 683b ldr r3, [r7, #0] 8000baa: 681a ldr r2, [r3, #0] 8000bac: 4613 mov r3, r2 8000bae: 005b lsls r3, r3, #1 8000bb0: 4413 add r3, r2 8000bb2: fa00 f203 lsl.w r2, r0, r3 8000bb6: 687b ldr r3, [r7, #4] 8000bb8: 681b ldr r3, [r3, #0] 8000bba: 430a orrs r2, r1 8000bbc: 611a str r2, [r3, #16] ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel) ); } /* If ADC1 Channel_16 or Channel_17 is selected, enable Temperature sensor */ /* and VREFINT measurement path. */ if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) || 8000bbe: 683b ldr r3, [r7, #0] 8000bc0: 681b ldr r3, [r3, #0] 8000bc2: 2b10 cmp r3, #16 8000bc4: d003 beq.n 8000bce (sConfig->Channel == ADC_CHANNEL_VREFINT) ) 8000bc6: 683b ldr r3, [r7, #0] 8000bc8: 681b ldr r3, [r3, #0] if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) || 8000bca: 2b11 cmp r3, #17 8000bcc: d132 bne.n 8000c34 { /* For STM32F1 devices with several ADC: Only ADC1 can access internal */ /* measurement channels (VrefInt/TempSensor). If these channels are */ /* intended to be set on other ADC instances, an error is reported. */ if (hadc->Instance == ADC1) 8000bce: 687b ldr r3, [r7, #4] 8000bd0: 681b ldr r3, [r3, #0] 8000bd2: 4a1d ldr r2, [pc, #116] ; (8000c48 ) 8000bd4: 4293 cmp r3, r2 8000bd6: d125 bne.n 8000c24 { if (READ_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE) == RESET) 8000bd8: 687b ldr r3, [r7, #4] 8000bda: 681b ldr r3, [r3, #0] 8000bdc: 689b ldr r3, [r3, #8] 8000bde: f403 0300 and.w r3, r3, #8388608 ; 0x800000 8000be2: 2b00 cmp r3, #0 8000be4: d126 bne.n 8000c34 { SET_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE); 8000be6: 687b ldr r3, [r7, #4] 8000be8: 681b ldr r3, [r3, #0] 8000bea: 689a ldr r2, [r3, #8] 8000bec: 687b ldr r3, [r7, #4] 8000bee: 681b ldr r3, [r3, #0] 8000bf0: f442 0200 orr.w r2, r2, #8388608 ; 0x800000 8000bf4: 609a str r2, [r3, #8] if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) 8000bf6: 683b ldr r3, [r7, #0] 8000bf8: 681b ldr r3, [r3, #0] 8000bfa: 2b10 cmp r3, #16 8000bfc: d11a bne.n 8000c34 { /* Delay for temperature sensor stabilization time */ /* Compute number of CPU cycles to wait for */ wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U)); 8000bfe: 4b13 ldr r3, [pc, #76] ; (8000c4c ) 8000c00: 681b ldr r3, [r3, #0] 8000c02: 4a13 ldr r2, [pc, #76] ; (8000c50 ) 8000c04: fba2 2303 umull r2, r3, r2, r3 8000c08: 0c9a lsrs r2, r3, #18 8000c0a: 4613 mov r3, r2 8000c0c: 009b lsls r3, r3, #2 8000c0e: 4413 add r3, r2 8000c10: 005b lsls r3, r3, #1 8000c12: 60bb str r3, [r7, #8] while(wait_loop_index != 0U) 8000c14: e002 b.n 8000c1c { wait_loop_index--; 8000c16: 68bb ldr r3, [r7, #8] 8000c18: 3b01 subs r3, #1 8000c1a: 60bb str r3, [r7, #8] while(wait_loop_index != 0U) 8000c1c: 68bb ldr r3, [r7, #8] 8000c1e: 2b00 cmp r3, #0 8000c20: d1f9 bne.n 8000c16 8000c22: e007 b.n 8000c34 } } else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 8000c24: 687b ldr r3, [r7, #4] 8000c26: 6a9b ldr r3, [r3, #40] ; 0x28 8000c28: f043 0220 orr.w r2, r3, #32 8000c2c: 687b ldr r3, [r7, #4] 8000c2e: 629a str r2, [r3, #40] ; 0x28 tmp_hal_status = HAL_ERROR; 8000c30: 2301 movs r3, #1 8000c32: 73fb strb r3, [r7, #15] } } /* Process unlocked */ __HAL_UNLOCK(hadc); 8000c34: 687b ldr r3, [r7, #4] 8000c36: 2200 movs r2, #0 8000c38: f883 2024 strb.w r2, [r3, #36] ; 0x24 /* Return function status */ return tmp_hal_status; 8000c3c: 7bfb ldrb r3, [r7, #15] } 8000c3e: 4618 mov r0, r3 8000c40: 3714 adds r7, #20 8000c42: 46bd mov sp, r7 8000c44: bc80 pop {r7} 8000c46: 4770 bx lr 8000c48: 40012400 .word 0x40012400 8000c4c: 20000000 .word 0x20000000 8000c50: 431bde83 .word 0x431bde83 08000c54 : * and voltage regulator must be enabled (done into HAL_ADC_Init()). * @param hadc: ADC handle * @retval HAL status. */ HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc) { 8000c54: b580 push {r7, lr} 8000c56: b084 sub sp, #16 8000c58: af00 add r7, sp, #0 8000c5a: 6078 str r0, [r7, #4] uint32_t tickstart = 0U; 8000c5c: 2300 movs r3, #0 8000c5e: 60fb str r3, [r7, #12] __IO uint32_t wait_loop_index = 0U; 8000c60: 2300 movs r3, #0 8000c62: 60bb str r3, [r7, #8] /* ADC enable and wait for ADC ready (in case of ADC is disabled or */ /* enabling phase not yet completed: flag ADC ready not yet set). */ /* Timeout implemented to not be stuck if ADC cannot be enabled (possible */ /* causes: ADC clock not running, ...). */ if (ADC_IS_ENABLE(hadc) == RESET) 8000c64: 687b ldr r3, [r7, #4] 8000c66: 681b ldr r3, [r3, #0] 8000c68: 689b ldr r3, [r3, #8] 8000c6a: f003 0301 and.w r3, r3, #1 8000c6e: 2b01 cmp r3, #1 8000c70: d040 beq.n 8000cf4 { /* Enable the Peripheral */ __HAL_ADC_ENABLE(hadc); 8000c72: 687b ldr r3, [r7, #4] 8000c74: 681b ldr r3, [r3, #0] 8000c76: 689a ldr r2, [r3, #8] 8000c78: 687b ldr r3, [r7, #4] 8000c7a: 681b ldr r3, [r3, #0] 8000c7c: f042 0201 orr.w r2, r2, #1 8000c80: 609a str r2, [r3, #8] /* Delay for ADC stabilization time */ /* Compute number of CPU cycles to wait for */ wait_loop_index = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U)); 8000c82: 4b1f ldr r3, [pc, #124] ; (8000d00 ) 8000c84: 681b ldr r3, [r3, #0] 8000c86: 4a1f ldr r2, [pc, #124] ; (8000d04 ) 8000c88: fba2 2303 umull r2, r3, r2, r3 8000c8c: 0c9b lsrs r3, r3, #18 8000c8e: 60bb str r3, [r7, #8] while(wait_loop_index != 0U) 8000c90: e002 b.n 8000c98 { wait_loop_index--; 8000c92: 68bb ldr r3, [r7, #8] 8000c94: 3b01 subs r3, #1 8000c96: 60bb str r3, [r7, #8] while(wait_loop_index != 0U) 8000c98: 68bb ldr r3, [r7, #8] 8000c9a: 2b00 cmp r3, #0 8000c9c: d1f9 bne.n 8000c92 } /* Get tick count */ tickstart = HAL_GetTick(); 8000c9e: f7ff fd21 bl 80006e4 8000ca2: 60f8 str r0, [r7, #12] /* Wait for ADC effectively enabled */ while(ADC_IS_ENABLE(hadc) == RESET) 8000ca4: e01f b.n 8000ce6 { if((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT) 8000ca6: f7ff fd1d bl 80006e4 8000caa: 4602 mov r2, r0 8000cac: 68fb ldr r3, [r7, #12] 8000cae: 1ad3 subs r3, r2, r3 8000cb0: 2b02 cmp r3, #2 8000cb2: d918 bls.n 8000ce6 { /* New check to avoid false timeout detection in case of preemption */ if(ADC_IS_ENABLE(hadc) == RESET) 8000cb4: 687b ldr r3, [r7, #4] 8000cb6: 681b ldr r3, [r3, #0] 8000cb8: 689b ldr r3, [r3, #8] 8000cba: f003 0301 and.w r3, r3, #1 8000cbe: 2b01 cmp r3, #1 8000cc0: d011 beq.n 8000ce6 { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 8000cc2: 687b ldr r3, [r7, #4] 8000cc4: 6a9b ldr r3, [r3, #40] ; 0x28 8000cc6: f043 0210 orr.w r2, r3, #16 8000cca: 687b ldr r3, [r7, #4] 8000ccc: 629a str r2, [r3, #40] ; 0x28 /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 8000cce: 687b ldr r3, [r7, #4] 8000cd0: 6adb ldr r3, [r3, #44] ; 0x2c 8000cd2: f043 0201 orr.w r2, r3, #1 8000cd6: 687b ldr r3, [r7, #4] 8000cd8: 62da str r2, [r3, #44] ; 0x2c /* Process unlocked */ __HAL_UNLOCK(hadc); 8000cda: 687b ldr r3, [r7, #4] 8000cdc: 2200 movs r2, #0 8000cde: f883 2024 strb.w r2, [r3, #36] ; 0x24 return HAL_ERROR; 8000ce2: 2301 movs r3, #1 8000ce4: e007 b.n 8000cf6 while(ADC_IS_ENABLE(hadc) == RESET) 8000ce6: 687b ldr r3, [r7, #4] 8000ce8: 681b ldr r3, [r3, #0] 8000cea: 689b ldr r3, [r3, #8] 8000cec: f003 0301 and.w r3, r3, #1 8000cf0: 2b01 cmp r3, #1 8000cf2: d1d8 bne.n 8000ca6 } } } /* Return HAL status */ return HAL_OK; 8000cf4: 2300 movs r3, #0 } 8000cf6: 4618 mov r0, r3 8000cf8: 3710 adds r7, #16 8000cfa: 46bd mov sp, r7 8000cfc: bd80 pop {r7, pc} 8000cfe: bf00 nop 8000d00: 20000000 .word 0x20000000 8000d04: 431bde83 .word 0x431bde83 08000d08 : * stopped to disable the ADC. * @param hadc: ADC handle * @retval HAL status. */ HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef* hadc) { 8000d08: b580 push {r7, lr} 8000d0a: b084 sub sp, #16 8000d0c: af00 add r7, sp, #0 8000d0e: 6078 str r0, [r7, #4] uint32_t tickstart = 0U; 8000d10: 2300 movs r3, #0 8000d12: 60fb str r3, [r7, #12] /* Verification if ADC is not already disabled */ if (ADC_IS_ENABLE(hadc) != RESET) 8000d14: 687b ldr r3, [r7, #4] 8000d16: 681b ldr r3, [r3, #0] 8000d18: 689b ldr r3, [r3, #8] 8000d1a: f003 0301 and.w r3, r3, #1 8000d1e: 2b01 cmp r3, #1 8000d20: d12e bne.n 8000d80 { /* Disable the ADC peripheral */ __HAL_ADC_DISABLE(hadc); 8000d22: 687b ldr r3, [r7, #4] 8000d24: 681b ldr r3, [r3, #0] 8000d26: 689a ldr r2, [r3, #8] 8000d28: 687b ldr r3, [r7, #4] 8000d2a: 681b ldr r3, [r3, #0] 8000d2c: f022 0201 bic.w r2, r2, #1 8000d30: 609a str r2, [r3, #8] /* Get tick count */ tickstart = HAL_GetTick(); 8000d32: f7ff fcd7 bl 80006e4 8000d36: 60f8 str r0, [r7, #12] /* Wait for ADC effectively disabled */ while(ADC_IS_ENABLE(hadc) != RESET) 8000d38: e01b b.n 8000d72 { if((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT) 8000d3a: f7ff fcd3 bl 80006e4 8000d3e: 4602 mov r2, r0 8000d40: 68fb ldr r3, [r7, #12] 8000d42: 1ad3 subs r3, r2, r3 8000d44: 2b02 cmp r3, #2 8000d46: d914 bls.n 8000d72 { /* New check to avoid false timeout detection in case of preemption */ if(ADC_IS_ENABLE(hadc) != RESET) 8000d48: 687b ldr r3, [r7, #4] 8000d4a: 681b ldr r3, [r3, #0] 8000d4c: 689b ldr r3, [r3, #8] 8000d4e: f003 0301 and.w r3, r3, #1 8000d52: 2b01 cmp r3, #1 8000d54: d10d bne.n 8000d72 { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 8000d56: 687b ldr r3, [r7, #4] 8000d58: 6a9b ldr r3, [r3, #40] ; 0x28 8000d5a: f043 0210 orr.w r2, r3, #16 8000d5e: 687b ldr r3, [r7, #4] 8000d60: 629a str r2, [r3, #40] ; 0x28 /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 8000d62: 687b ldr r3, [r7, #4] 8000d64: 6adb ldr r3, [r3, #44] ; 0x2c 8000d66: f043 0201 orr.w r2, r3, #1 8000d6a: 687b ldr r3, [r7, #4] 8000d6c: 62da str r2, [r3, #44] ; 0x2c return HAL_ERROR; 8000d6e: 2301 movs r3, #1 8000d70: e007 b.n 8000d82 while(ADC_IS_ENABLE(hadc) != RESET) 8000d72: 687b ldr r3, [r7, #4] 8000d74: 681b ldr r3, [r3, #0] 8000d76: 689b ldr r3, [r3, #8] 8000d78: f003 0301 and.w r3, r3, #1 8000d7c: 2b01 cmp r3, #1 8000d7e: d0dc beq.n 8000d3a } } } /* Return HAL status */ return HAL_OK; 8000d80: 2300 movs r3, #0 } 8000d82: 4618 mov r0, r3 8000d84: 3710 adds r7, #16 8000d86: 46bd mov sp, r7 8000d88: bd80 pop {r7, pc} ... 08000d8c <__NVIC_SetPriorityGrouping>: In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 8000d8c: b480 push {r7} 8000d8e: b085 sub sp, #20 8000d90: af00 add r7, sp, #0 8000d92: 6078 str r0, [r7, #4] uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 8000d94: 687b ldr r3, [r7, #4] 8000d96: f003 0307 and.w r3, r3, #7 8000d9a: 60fb str r3, [r7, #12] reg_value = SCB->AIRCR; /* read old register configuration */ 8000d9c: 4b0c ldr r3, [pc, #48] ; (8000dd0 <__NVIC_SetPriorityGrouping+0x44>) 8000d9e: 68db ldr r3, [r3, #12] 8000da0: 60bb str r3, [r7, #8] reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ 8000da2: 68ba ldr r2, [r7, #8] 8000da4: f64f 03ff movw r3, #63743 ; 0xf8ff 8000da8: 4013 ands r3, r2 8000daa: 60bb str r3, [r7, #8] reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ 8000dac: 68fb ldr r3, [r7, #12] 8000dae: 021a lsls r2, r3, #8 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 8000db0: 68bb ldr r3, [r7, #8] 8000db2: 4313 orrs r3, r2 reg_value = (reg_value | 8000db4: f043 63bf orr.w r3, r3, #100139008 ; 0x5f80000 8000db8: f443 3300 orr.w r3, r3, #131072 ; 0x20000 8000dbc: 60bb str r3, [r7, #8] SCB->AIRCR = reg_value; 8000dbe: 4a04 ldr r2, [pc, #16] ; (8000dd0 <__NVIC_SetPriorityGrouping+0x44>) 8000dc0: 68bb ldr r3, [r7, #8] 8000dc2: 60d3 str r3, [r2, #12] } 8000dc4: bf00 nop 8000dc6: 3714 adds r7, #20 8000dc8: 46bd mov sp, r7 8000dca: bc80 pop {r7} 8000dcc: 4770 bx lr 8000dce: bf00 nop 8000dd0: e000ed00 .word 0xe000ed00 08000dd4 <__NVIC_GetPriorityGrouping>: \brief Get Priority Grouping \details Reads the priority grouping field from the NVIC Interrupt Controller. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) { 8000dd4: b480 push {r7} 8000dd6: af00 add r7, sp, #0 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); 8000dd8: 4b04 ldr r3, [pc, #16] ; (8000dec <__NVIC_GetPriorityGrouping+0x18>) 8000dda: 68db ldr r3, [r3, #12] 8000ddc: 0a1b lsrs r3, r3, #8 8000dde: f003 0307 and.w r3, r3, #7 } 8000de2: 4618 mov r0, r3 8000de4: 46bd mov sp, r7 8000de6: bc80 pop {r7} 8000de8: 4770 bx lr 8000dea: bf00 nop 8000dec: e000ed00 .word 0xe000ed00 08000df0 <__NVIC_SetPriority>: \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { 8000df0: b480 push {r7} 8000df2: b083 sub sp, #12 8000df4: af00 add r7, sp, #0 8000df6: 4603 mov r3, r0 8000df8: 6039 str r1, [r7, #0] 8000dfa: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) 8000dfc: f997 3007 ldrsb.w r3, [r7, #7] 8000e00: 2b00 cmp r3, #0 8000e02: db0a blt.n 8000e1a <__NVIC_SetPriority+0x2a> { NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 8000e04: 683b ldr r3, [r7, #0] 8000e06: b2da uxtb r2, r3 8000e08: 490c ldr r1, [pc, #48] ; (8000e3c <__NVIC_SetPriority+0x4c>) 8000e0a: f997 3007 ldrsb.w r3, [r7, #7] 8000e0e: 0112 lsls r2, r2, #4 8000e10: b2d2 uxtb r2, r2 8000e12: 440b add r3, r1 8000e14: f883 2300 strb.w r2, [r3, #768] ; 0x300 } else { SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } 8000e18: e00a b.n 8000e30 <__NVIC_SetPriority+0x40> SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 8000e1a: 683b ldr r3, [r7, #0] 8000e1c: b2da uxtb r2, r3 8000e1e: 4908 ldr r1, [pc, #32] ; (8000e40 <__NVIC_SetPriority+0x50>) 8000e20: 79fb ldrb r3, [r7, #7] 8000e22: f003 030f and.w r3, r3, #15 8000e26: 3b04 subs r3, #4 8000e28: 0112 lsls r2, r2, #4 8000e2a: b2d2 uxtb r2, r2 8000e2c: 440b add r3, r1 8000e2e: 761a strb r2, [r3, #24] } 8000e30: bf00 nop 8000e32: 370c adds r7, #12 8000e34: 46bd mov sp, r7 8000e36: bc80 pop {r7} 8000e38: 4770 bx lr 8000e3a: bf00 nop 8000e3c: e000e100 .word 0xe000e100 8000e40: e000ed00 .word 0xe000ed00 08000e44 : \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { 8000e44: b480 push {r7} 8000e46: b089 sub sp, #36 ; 0x24 8000e48: af00 add r7, sp, #0 8000e4a: 60f8 str r0, [r7, #12] 8000e4c: 60b9 str r1, [r7, #8] 8000e4e: 607a str r2, [r7, #4] uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 8000e50: 68fb ldr r3, [r7, #12] 8000e52: f003 0307 and.w r3, r3, #7 8000e56: 61fb str r3, [r7, #28] uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 8000e58: 69fb ldr r3, [r7, #28] 8000e5a: f1c3 0307 rsb r3, r3, #7 8000e5e: 2b04 cmp r3, #4 8000e60: bf28 it cs 8000e62: 2304 movcs r3, #4 8000e64: 61bb str r3, [r7, #24] SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 8000e66: 69fb ldr r3, [r7, #28] 8000e68: 3304 adds r3, #4 8000e6a: 2b06 cmp r3, #6 8000e6c: d902 bls.n 8000e74 8000e6e: 69fb ldr r3, [r7, #28] 8000e70: 3b03 subs r3, #3 8000e72: e000 b.n 8000e76 8000e74: 2300 movs r3, #0 8000e76: 617b str r3, [r7, #20] return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 8000e78: f04f 32ff mov.w r2, #4294967295 8000e7c: 69bb ldr r3, [r7, #24] 8000e7e: fa02 f303 lsl.w r3, r2, r3 8000e82: 43da mvns r2, r3 8000e84: 68bb ldr r3, [r7, #8] 8000e86: 401a ands r2, r3 8000e88: 697b ldr r3, [r7, #20] 8000e8a: 409a lsls r2, r3 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) 8000e8c: f04f 31ff mov.w r1, #4294967295 8000e90: 697b ldr r3, [r7, #20] 8000e92: fa01 f303 lsl.w r3, r1, r3 8000e96: 43d9 mvns r1, r3 8000e98: 687b ldr r3, [r7, #4] 8000e9a: 400b ands r3, r1 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 8000e9c: 4313 orrs r3, r2 ); } 8000e9e: 4618 mov r0, r3 8000ea0: 3724 adds r7, #36 ; 0x24 8000ea2: 46bd mov sp, r7 8000ea4: bc80 pop {r7} 8000ea6: 4770 bx lr 08000ea8 : \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { 8000ea8: b580 push {r7, lr} 8000eaa: b082 sub sp, #8 8000eac: af00 add r7, sp, #0 8000eae: 6078 str r0, [r7, #4] if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) 8000eb0: 687b ldr r3, [r7, #4] 8000eb2: 3b01 subs r3, #1 8000eb4: f1b3 7f80 cmp.w r3, #16777216 ; 0x1000000 8000eb8: d301 bcc.n 8000ebe { return (1UL); /* Reload value impossible */ 8000eba: 2301 movs r3, #1 8000ebc: e00f b.n 8000ede } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 8000ebe: 4a0a ldr r2, [pc, #40] ; (8000ee8 ) 8000ec0: 687b ldr r3, [r7, #4] 8000ec2: 3b01 subs r3, #1 8000ec4: 6053 str r3, [r2, #4] NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ 8000ec6: 210f movs r1, #15 8000ec8: f04f 30ff mov.w r0, #4294967295 8000ecc: f7ff ff90 bl 8000df0 <__NVIC_SetPriority> SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ 8000ed0: 4b05 ldr r3, [pc, #20] ; (8000ee8 ) 8000ed2: 2200 movs r2, #0 8000ed4: 609a str r2, [r3, #8] SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 8000ed6: 4b04 ldr r3, [pc, #16] ; (8000ee8 ) 8000ed8: 2207 movs r2, #7 8000eda: 601a str r2, [r3, #0] SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ 8000edc: 2300 movs r3, #0 } 8000ede: 4618 mov r0, r3 8000ee0: 3708 adds r7, #8 8000ee2: 46bd mov sp, r7 8000ee4: bd80 pop {r7, pc} 8000ee6: bf00 nop 8000ee8: e000e010 .word 0xe000e010 08000eec : * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. * The pending IRQ priority will be managed only by the subpriority. * @retval None */ void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 8000eec: b580 push {r7, lr} 8000eee: b082 sub sp, #8 8000ef0: af00 add r7, sp, #0 8000ef2: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ NVIC_SetPriorityGrouping(PriorityGroup); 8000ef4: 6878 ldr r0, [r7, #4] 8000ef6: f7ff ff49 bl 8000d8c <__NVIC_SetPriorityGrouping> } 8000efa: bf00 nop 8000efc: 3708 adds r7, #8 8000efe: 46bd mov sp, r7 8000f00: bd80 pop {r7, pc} 08000f02 : * This parameter can be a value between 0 and 15 * A lower priority value indicates a higher priority. * @retval None */ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) { 8000f02: b580 push {r7, lr} 8000f04: b086 sub sp, #24 8000f06: af00 add r7, sp, #0 8000f08: 4603 mov r3, r0 8000f0a: 60b9 str r1, [r7, #8] 8000f0c: 607a str r2, [r7, #4] 8000f0e: 73fb strb r3, [r7, #15] uint32_t prioritygroup = 0x00U; 8000f10: 2300 movs r3, #0 8000f12: 617b str r3, [r7, #20] /* Check the parameters */ assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); prioritygroup = NVIC_GetPriorityGrouping(); 8000f14: f7ff ff5e bl 8000dd4 <__NVIC_GetPriorityGrouping> 8000f18: 6178 str r0, [r7, #20] NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); 8000f1a: 687a ldr r2, [r7, #4] 8000f1c: 68b9 ldr r1, [r7, #8] 8000f1e: 6978 ldr r0, [r7, #20] 8000f20: f7ff ff90 bl 8000e44 8000f24: 4602 mov r2, r0 8000f26: f997 300f ldrsb.w r3, [r7, #15] 8000f2a: 4611 mov r1, r2 8000f2c: 4618 mov r0, r3 8000f2e: f7ff ff5f bl 8000df0 <__NVIC_SetPriority> } 8000f32: bf00 nop 8000f34: 3718 adds r7, #24 8000f36: 46bd mov sp, r7 8000f38: bd80 pop {r7, pc} 08000f3a : * @param TicksNumb: Specifies the ticks Number of ticks between two interrupts. * @retval status: - 0 Function succeeded. * - 1 Function failed. */ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) { 8000f3a: b580 push {r7, lr} 8000f3c: b082 sub sp, #8 8000f3e: af00 add r7, sp, #0 8000f40: 6078 str r0, [r7, #4] return SysTick_Config(TicksNumb); 8000f42: 6878 ldr r0, [r7, #4] 8000f44: f7ff ffb0 bl 8000ea8 8000f48: 4603 mov r3, r0 } 8000f4a: 4618 mov r0, r3 8000f4c: 3708 adds r7, #8 8000f4e: 46bd mov sp, r7 8000f50: bd80 pop {r7, pc} ... 08000f54 : * @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains * the configuration information for the specified GPIO peripheral. * @retval None */ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) { 8000f54: b480 push {r7} 8000f56: b08b sub sp, #44 ; 0x2c 8000f58: af00 add r7, sp, #0 8000f5a: 6078 str r0, [r7, #4] 8000f5c: 6039 str r1, [r7, #0] uint32_t position = 0x00u; 8000f5e: 2300 movs r3, #0 8000f60: 627b str r3, [r7, #36] ; 0x24 uint32_t ioposition; uint32_t iocurrent; uint32_t temp; uint32_t config = 0x00u; 8000f62: 2300 movs r3, #0 8000f64: 623b str r3, [r7, #32] assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); /* Configure the port pins */ while (((GPIO_Init->Pin) >> position) != 0x00u) 8000f66: e169 b.n 800123c { /* Get the IO position */ ioposition = (0x01uL << position); 8000f68: 2201 movs r2, #1 8000f6a: 6a7b ldr r3, [r7, #36] ; 0x24 8000f6c: fa02 f303 lsl.w r3, r2, r3 8000f70: 61fb str r3, [r7, #28] /* Get the current IO position */ iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition; 8000f72: 683b ldr r3, [r7, #0] 8000f74: 681b ldr r3, [r3, #0] 8000f76: 69fa ldr r2, [r7, #28] 8000f78: 4013 ands r3, r2 8000f7a: 61bb str r3, [r7, #24] if (iocurrent == ioposition) 8000f7c: 69ba ldr r2, [r7, #24] 8000f7e: 69fb ldr r3, [r7, #28] 8000f80: 429a cmp r2, r3 8000f82: f040 8158 bne.w 8001236 { /* Check the Alternate function parameters */ assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); /* Based on the required mode, filling config variable with MODEy[1:0] and CNFy[3:2] corresponding bits */ switch (GPIO_Init->Mode) 8000f86: 683b ldr r3, [r7, #0] 8000f88: 685b ldr r3, [r3, #4] 8000f8a: 4a9a ldr r2, [pc, #616] ; (80011f4 ) 8000f8c: 4293 cmp r3, r2 8000f8e: d05e beq.n 800104e 8000f90: 4a98 ldr r2, [pc, #608] ; (80011f4 ) 8000f92: 4293 cmp r3, r2 8000f94: d875 bhi.n 8001082 8000f96: 4a98 ldr r2, [pc, #608] ; (80011f8 ) 8000f98: 4293 cmp r3, r2 8000f9a: d058 beq.n 800104e 8000f9c: 4a96 ldr r2, [pc, #600] ; (80011f8 ) 8000f9e: 4293 cmp r3, r2 8000fa0: d86f bhi.n 8001082 8000fa2: 4a96 ldr r2, [pc, #600] ; (80011fc ) 8000fa4: 4293 cmp r3, r2 8000fa6: d052 beq.n 800104e 8000fa8: 4a94 ldr r2, [pc, #592] ; (80011fc ) 8000faa: 4293 cmp r3, r2 8000fac: d869 bhi.n 8001082 8000fae: 4a94 ldr r2, [pc, #592] ; (8001200 ) 8000fb0: 4293 cmp r3, r2 8000fb2: d04c beq.n 800104e 8000fb4: 4a92 ldr r2, [pc, #584] ; (8001200 ) 8000fb6: 4293 cmp r3, r2 8000fb8: d863 bhi.n 8001082 8000fba: 4a92 ldr r2, [pc, #584] ; (8001204 ) 8000fbc: 4293 cmp r3, r2 8000fbe: d046 beq.n 800104e 8000fc0: 4a90 ldr r2, [pc, #576] ; (8001204 ) 8000fc2: 4293 cmp r3, r2 8000fc4: d85d bhi.n 8001082 8000fc6: 2b12 cmp r3, #18 8000fc8: d82a bhi.n 8001020 8000fca: 2b12 cmp r3, #18 8000fcc: d859 bhi.n 8001082 8000fce: a201 add r2, pc, #4 ; (adr r2, 8000fd4 ) 8000fd0: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8000fd4: 0800104f .word 0x0800104f 8000fd8: 08001029 .word 0x08001029 8000fdc: 0800103b .word 0x0800103b 8000fe0: 0800107d .word 0x0800107d 8000fe4: 08001083 .word 0x08001083 8000fe8: 08001083 .word 0x08001083 8000fec: 08001083 .word 0x08001083 8000ff0: 08001083 .word 0x08001083 8000ff4: 08001083 .word 0x08001083 8000ff8: 08001083 .word 0x08001083 8000ffc: 08001083 .word 0x08001083 8001000: 08001083 .word 0x08001083 8001004: 08001083 .word 0x08001083 8001008: 08001083 .word 0x08001083 800100c: 08001083 .word 0x08001083 8001010: 08001083 .word 0x08001083 8001014: 08001083 .word 0x08001083 8001018: 08001031 .word 0x08001031 800101c: 08001045 .word 0x08001045 8001020: 4a79 ldr r2, [pc, #484] ; (8001208 ) 8001022: 4293 cmp r3, r2 8001024: d013 beq.n 800104e config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG; break; /* Parameters are checked with assert_param */ default: break; 8001026: e02c b.n 8001082 config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_PP; 8001028: 683b ldr r3, [r7, #0] 800102a: 68db ldr r3, [r3, #12] 800102c: 623b str r3, [r7, #32] break; 800102e: e029 b.n 8001084 config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_OD; 8001030: 683b ldr r3, [r7, #0] 8001032: 68db ldr r3, [r3, #12] 8001034: 3304 adds r3, #4 8001036: 623b str r3, [r7, #32] break; 8001038: e024 b.n 8001084 config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_PP; 800103a: 683b ldr r3, [r7, #0] 800103c: 68db ldr r3, [r3, #12] 800103e: 3308 adds r3, #8 8001040: 623b str r3, [r7, #32] break; 8001042: e01f b.n 8001084 config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_OD; 8001044: 683b ldr r3, [r7, #0] 8001046: 68db ldr r3, [r3, #12] 8001048: 330c adds r3, #12 800104a: 623b str r3, [r7, #32] break; 800104c: e01a b.n 8001084 if (GPIO_Init->Pull == GPIO_NOPULL) 800104e: 683b ldr r3, [r7, #0] 8001050: 689b ldr r3, [r3, #8] 8001052: 2b00 cmp r3, #0 8001054: d102 bne.n 800105c config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_FLOATING; 8001056: 2304 movs r3, #4 8001058: 623b str r3, [r7, #32] break; 800105a: e013 b.n 8001084 else if (GPIO_Init->Pull == GPIO_PULLUP) 800105c: 683b ldr r3, [r7, #0] 800105e: 689b ldr r3, [r3, #8] 8001060: 2b01 cmp r3, #1 8001062: d105 bne.n 8001070 config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD; 8001064: 2308 movs r3, #8 8001066: 623b str r3, [r7, #32] GPIOx->BSRR = ioposition; 8001068: 687b ldr r3, [r7, #4] 800106a: 69fa ldr r2, [r7, #28] 800106c: 611a str r2, [r3, #16] break; 800106e: e009 b.n 8001084 config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD; 8001070: 2308 movs r3, #8 8001072: 623b str r3, [r7, #32] GPIOx->BRR = ioposition; 8001074: 687b ldr r3, [r7, #4] 8001076: 69fa ldr r2, [r7, #28] 8001078: 615a str r2, [r3, #20] break; 800107a: e003 b.n 8001084 config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG; 800107c: 2300 movs r3, #0 800107e: 623b str r3, [r7, #32] break; 8001080: e000 b.n 8001084 break; 8001082: bf00 nop } /* Check if the current bit belongs to first half or last half of the pin count number in order to address CRH or CRL register*/ configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL : &GPIOx->CRH; 8001084: 69bb ldr r3, [r7, #24] 8001086: 2bff cmp r3, #255 ; 0xff 8001088: d801 bhi.n 800108e 800108a: 687b ldr r3, [r7, #4] 800108c: e001 b.n 8001092 800108e: 687b ldr r3, [r7, #4] 8001090: 3304 adds r3, #4 8001092: 617b str r3, [r7, #20] registeroffset = (iocurrent < GPIO_PIN_8) ? (position << 2u) : ((position - 8u) << 2u); 8001094: 69bb ldr r3, [r7, #24] 8001096: 2bff cmp r3, #255 ; 0xff 8001098: d802 bhi.n 80010a0 800109a: 6a7b ldr r3, [r7, #36] ; 0x24 800109c: 009b lsls r3, r3, #2 800109e: e002 b.n 80010a6 80010a0: 6a7b ldr r3, [r7, #36] ; 0x24 80010a2: 3b08 subs r3, #8 80010a4: 009b lsls r3, r3, #2 80010a6: 613b str r3, [r7, #16] /* Apply the new configuration of the pin to the register */ MODIFY_REG((*configregister), ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset), (config << registeroffset)); 80010a8: 697b ldr r3, [r7, #20] 80010aa: 681a ldr r2, [r3, #0] 80010ac: 210f movs r1, #15 80010ae: 693b ldr r3, [r7, #16] 80010b0: fa01 f303 lsl.w r3, r1, r3 80010b4: 43db mvns r3, r3 80010b6: 401a ands r2, r3 80010b8: 6a39 ldr r1, [r7, #32] 80010ba: 693b ldr r3, [r7, #16] 80010bc: fa01 f303 lsl.w r3, r1, r3 80010c0: 431a orrs r2, r3 80010c2: 697b ldr r3, [r7, #20] 80010c4: 601a str r2, [r3, #0] /*--------------------- EXTI Mode Configuration ------------------------*/ /* Configure the External Interrupt or event for the current IO */ if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE) 80010c6: 683b ldr r3, [r7, #0] 80010c8: 685b ldr r3, [r3, #4] 80010ca: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 80010ce: 2b00 cmp r3, #0 80010d0: f000 80b1 beq.w 8001236 { /* Enable AFIO Clock */ __HAL_RCC_AFIO_CLK_ENABLE(); 80010d4: 4b4d ldr r3, [pc, #308] ; (800120c ) 80010d6: 699b ldr r3, [r3, #24] 80010d8: 4a4c ldr r2, [pc, #304] ; (800120c ) 80010da: f043 0301 orr.w r3, r3, #1 80010de: 6193 str r3, [r2, #24] 80010e0: 4b4a ldr r3, [pc, #296] ; (800120c ) 80010e2: 699b ldr r3, [r3, #24] 80010e4: f003 0301 and.w r3, r3, #1 80010e8: 60bb str r3, [r7, #8] 80010ea: 68bb ldr r3, [r7, #8] temp = AFIO->EXTICR[position >> 2u]; 80010ec: 4a48 ldr r2, [pc, #288] ; (8001210 ) 80010ee: 6a7b ldr r3, [r7, #36] ; 0x24 80010f0: 089b lsrs r3, r3, #2 80010f2: 3302 adds r3, #2 80010f4: f852 3023 ldr.w r3, [r2, r3, lsl #2] 80010f8: 60fb str r3, [r7, #12] CLEAR_BIT(temp, (0x0Fu) << (4u * (position & 0x03u))); 80010fa: 6a7b ldr r3, [r7, #36] ; 0x24 80010fc: f003 0303 and.w r3, r3, #3 8001100: 009b lsls r3, r3, #2 8001102: 220f movs r2, #15 8001104: fa02 f303 lsl.w r3, r2, r3 8001108: 43db mvns r3, r3 800110a: 68fa ldr r2, [r7, #12] 800110c: 4013 ands r3, r2 800110e: 60fb str r3, [r7, #12] SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4u * (position & 0x03u))); 8001110: 687b ldr r3, [r7, #4] 8001112: 4a40 ldr r2, [pc, #256] ; (8001214 ) 8001114: 4293 cmp r3, r2 8001116: d013 beq.n 8001140 8001118: 687b ldr r3, [r7, #4] 800111a: 4a3f ldr r2, [pc, #252] ; (8001218 ) 800111c: 4293 cmp r3, r2 800111e: d00d beq.n 800113c 8001120: 687b ldr r3, [r7, #4] 8001122: 4a3e ldr r2, [pc, #248] ; (800121c ) 8001124: 4293 cmp r3, r2 8001126: d007 beq.n 8001138 8001128: 687b ldr r3, [r7, #4] 800112a: 4a3d ldr r2, [pc, #244] ; (8001220 ) 800112c: 4293 cmp r3, r2 800112e: d101 bne.n 8001134 8001130: 2303 movs r3, #3 8001132: e006 b.n 8001142 8001134: 2304 movs r3, #4 8001136: e004 b.n 8001142 8001138: 2302 movs r3, #2 800113a: e002 b.n 8001142 800113c: 2301 movs r3, #1 800113e: e000 b.n 8001142 8001140: 2300 movs r3, #0 8001142: 6a7a ldr r2, [r7, #36] ; 0x24 8001144: f002 0203 and.w r2, r2, #3 8001148: 0092 lsls r2, r2, #2 800114a: 4093 lsls r3, r2 800114c: 68fa ldr r2, [r7, #12] 800114e: 4313 orrs r3, r2 8001150: 60fb str r3, [r7, #12] AFIO->EXTICR[position >> 2u] = temp; 8001152: 492f ldr r1, [pc, #188] ; (8001210 ) 8001154: 6a7b ldr r3, [r7, #36] ; 0x24 8001156: 089b lsrs r3, r3, #2 8001158: 3302 adds r3, #2 800115a: 68fa ldr r2, [r7, #12] 800115c: f841 2023 str.w r2, [r1, r3, lsl #2] /* Configure the interrupt mask */ if ((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT) 8001160: 683b ldr r3, [r7, #0] 8001162: 685b ldr r3, [r3, #4] 8001164: f403 3380 and.w r3, r3, #65536 ; 0x10000 8001168: 2b00 cmp r3, #0 800116a: d006 beq.n 800117a { SET_BIT(EXTI->IMR, iocurrent); 800116c: 4b2d ldr r3, [pc, #180] ; (8001224 ) 800116e: 681a ldr r2, [r3, #0] 8001170: 492c ldr r1, [pc, #176] ; (8001224 ) 8001172: 69bb ldr r3, [r7, #24] 8001174: 4313 orrs r3, r2 8001176: 600b str r3, [r1, #0] 8001178: e006 b.n 8001188 } else { CLEAR_BIT(EXTI->IMR, iocurrent); 800117a: 4b2a ldr r3, [pc, #168] ; (8001224 ) 800117c: 681a ldr r2, [r3, #0] 800117e: 69bb ldr r3, [r7, #24] 8001180: 43db mvns r3, r3 8001182: 4928 ldr r1, [pc, #160] ; (8001224 ) 8001184: 4013 ands r3, r2 8001186: 600b str r3, [r1, #0] } /* Configure the event mask */ if ((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT) 8001188: 683b ldr r3, [r7, #0] 800118a: 685b ldr r3, [r3, #4] 800118c: f403 3300 and.w r3, r3, #131072 ; 0x20000 8001190: 2b00 cmp r3, #0 8001192: d006 beq.n 80011a2 { SET_BIT(EXTI->EMR, iocurrent); 8001194: 4b23 ldr r3, [pc, #140] ; (8001224 ) 8001196: 685a ldr r2, [r3, #4] 8001198: 4922 ldr r1, [pc, #136] ; (8001224 ) 800119a: 69bb ldr r3, [r7, #24] 800119c: 4313 orrs r3, r2 800119e: 604b str r3, [r1, #4] 80011a0: e006 b.n 80011b0 } else { CLEAR_BIT(EXTI->EMR, iocurrent); 80011a2: 4b20 ldr r3, [pc, #128] ; (8001224 ) 80011a4: 685a ldr r2, [r3, #4] 80011a6: 69bb ldr r3, [r7, #24] 80011a8: 43db mvns r3, r3 80011aa: 491e ldr r1, [pc, #120] ; (8001224 ) 80011ac: 4013 ands r3, r2 80011ae: 604b str r3, [r1, #4] } /* Enable or disable the rising trigger */ if ((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE) 80011b0: 683b ldr r3, [r7, #0] 80011b2: 685b ldr r3, [r3, #4] 80011b4: f403 1380 and.w r3, r3, #1048576 ; 0x100000 80011b8: 2b00 cmp r3, #0 80011ba: d006 beq.n 80011ca { SET_BIT(EXTI->RTSR, iocurrent); 80011bc: 4b19 ldr r3, [pc, #100] ; (8001224 ) 80011be: 689a ldr r2, [r3, #8] 80011c0: 4918 ldr r1, [pc, #96] ; (8001224 ) 80011c2: 69bb ldr r3, [r7, #24] 80011c4: 4313 orrs r3, r2 80011c6: 608b str r3, [r1, #8] 80011c8: e006 b.n 80011d8 } else { CLEAR_BIT(EXTI->RTSR, iocurrent); 80011ca: 4b16 ldr r3, [pc, #88] ; (8001224 ) 80011cc: 689a ldr r2, [r3, #8] 80011ce: 69bb ldr r3, [r7, #24] 80011d0: 43db mvns r3, r3 80011d2: 4914 ldr r1, [pc, #80] ; (8001224 ) 80011d4: 4013 ands r3, r2 80011d6: 608b str r3, [r1, #8] } /* Enable or disable the falling trigger */ if ((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE) 80011d8: 683b ldr r3, [r7, #0] 80011da: 685b ldr r3, [r3, #4] 80011dc: f403 1300 and.w r3, r3, #2097152 ; 0x200000 80011e0: 2b00 cmp r3, #0 80011e2: d021 beq.n 8001228 { SET_BIT(EXTI->FTSR, iocurrent); 80011e4: 4b0f ldr r3, [pc, #60] ; (8001224 ) 80011e6: 68da ldr r2, [r3, #12] 80011e8: 490e ldr r1, [pc, #56] ; (8001224 ) 80011ea: 69bb ldr r3, [r7, #24] 80011ec: 4313 orrs r3, r2 80011ee: 60cb str r3, [r1, #12] 80011f0: e021 b.n 8001236 80011f2: bf00 nop 80011f4: 10320000 .word 0x10320000 80011f8: 10310000 .word 0x10310000 80011fc: 10220000 .word 0x10220000 8001200: 10210000 .word 0x10210000 8001204: 10120000 .word 0x10120000 8001208: 10110000 .word 0x10110000 800120c: 40021000 .word 0x40021000 8001210: 40010000 .word 0x40010000 8001214: 40010800 .word 0x40010800 8001218: 40010c00 .word 0x40010c00 800121c: 40011000 .word 0x40011000 8001220: 40011400 .word 0x40011400 8001224: 40010400 .word 0x40010400 } else { CLEAR_BIT(EXTI->FTSR, iocurrent); 8001228: 4b0b ldr r3, [pc, #44] ; (8001258 ) 800122a: 68da ldr r2, [r3, #12] 800122c: 69bb ldr r3, [r7, #24] 800122e: 43db mvns r3, r3 8001230: 4909 ldr r1, [pc, #36] ; (8001258 ) 8001232: 4013 ands r3, r2 8001234: 60cb str r3, [r1, #12] } } } position++; 8001236: 6a7b ldr r3, [r7, #36] ; 0x24 8001238: 3301 adds r3, #1 800123a: 627b str r3, [r7, #36] ; 0x24 while (((GPIO_Init->Pin) >> position) != 0x00u) 800123c: 683b ldr r3, [r7, #0] 800123e: 681a ldr r2, [r3, #0] 8001240: 6a7b ldr r3, [r7, #36] ; 0x24 8001242: fa22 f303 lsr.w r3, r2, r3 8001246: 2b00 cmp r3, #0 8001248: f47f ae8e bne.w 8000f68 } } 800124c: bf00 nop 800124e: bf00 nop 8001250: 372c adds r7, #44 ; 0x2c 8001252: 46bd mov sp, r7 8001254: bc80 pop {r7} 8001256: 4770 bx lr 8001258: 40010400 .word 0x40010400 0800125c : * supported by this macro. User should request a transition to HSE Off * first and then HSE On or HSE Bypass. * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { 800125c: b580 push {r7, lr} 800125e: b086 sub sp, #24 8001260: af00 add r7, sp, #0 8001262: 6078 str r0, [r7, #4] uint32_t tickstart; uint32_t pll_config; /* Check Null pointer */ if (RCC_OscInitStruct == NULL) 8001264: 687b ldr r3, [r7, #4] 8001266: 2b00 cmp r3, #0 8001268: d101 bne.n 800126e { return HAL_ERROR; 800126a: 2301 movs r3, #1 800126c: e272 b.n 8001754 /* Check the parameters */ assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); /*------------------------------- HSE Configuration ------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) 800126e: 687b ldr r3, [r7, #4] 8001270: 681b ldr r3, [r3, #0] 8001272: f003 0301 and.w r3, r3, #1 8001276: 2b00 cmp r3, #0 8001278: f000 8087 beq.w 800138a { /* Check the parameters */ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */ if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE) 800127c: 4b92 ldr r3, [pc, #584] ; (80014c8 ) 800127e: 685b ldr r3, [r3, #4] 8001280: f003 030c and.w r3, r3, #12 8001284: 2b04 cmp r3, #4 8001286: d00c beq.n 80012a2 || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE))) 8001288: 4b8f ldr r3, [pc, #572] ; (80014c8 ) 800128a: 685b ldr r3, [r3, #4] 800128c: f003 030c and.w r3, r3, #12 8001290: 2b08 cmp r3, #8 8001292: d112 bne.n 80012ba 8001294: 4b8c ldr r3, [pc, #560] ; (80014c8 ) 8001296: 685b ldr r3, [r3, #4] 8001298: f403 3380 and.w r3, r3, #65536 ; 0x10000 800129c: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 80012a0: d10b bne.n 80012ba { if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 80012a2: 4b89 ldr r3, [pc, #548] ; (80014c8 ) 80012a4: 681b ldr r3, [r3, #0] 80012a6: f403 3300 and.w r3, r3, #131072 ; 0x20000 80012aa: 2b00 cmp r3, #0 80012ac: d06c beq.n 8001388 80012ae: 687b ldr r3, [r7, #4] 80012b0: 685b ldr r3, [r3, #4] 80012b2: 2b00 cmp r3, #0 80012b4: d168 bne.n 8001388 { return HAL_ERROR; 80012b6: 2301 movs r3, #1 80012b8: e24c b.n 8001754 } } else { /* Set the new HSE configuration ---------------------------------------*/ __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); 80012ba: 687b ldr r3, [r7, #4] 80012bc: 685b ldr r3, [r3, #4] 80012be: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 80012c2: d106 bne.n 80012d2 80012c4: 4b80 ldr r3, [pc, #512] ; (80014c8 ) 80012c6: 681b ldr r3, [r3, #0] 80012c8: 4a7f ldr r2, [pc, #508] ; (80014c8 ) 80012ca: f443 3380 orr.w r3, r3, #65536 ; 0x10000 80012ce: 6013 str r3, [r2, #0] 80012d0: e02e b.n 8001330 80012d2: 687b ldr r3, [r7, #4] 80012d4: 685b ldr r3, [r3, #4] 80012d6: 2b00 cmp r3, #0 80012d8: d10c bne.n 80012f4 80012da: 4b7b ldr r3, [pc, #492] ; (80014c8 ) 80012dc: 681b ldr r3, [r3, #0] 80012de: 4a7a ldr r2, [pc, #488] ; (80014c8 ) 80012e0: f423 3380 bic.w r3, r3, #65536 ; 0x10000 80012e4: 6013 str r3, [r2, #0] 80012e6: 4b78 ldr r3, [pc, #480] ; (80014c8 ) 80012e8: 681b ldr r3, [r3, #0] 80012ea: 4a77 ldr r2, [pc, #476] ; (80014c8 ) 80012ec: f423 2380 bic.w r3, r3, #262144 ; 0x40000 80012f0: 6013 str r3, [r2, #0] 80012f2: e01d b.n 8001330 80012f4: 687b ldr r3, [r7, #4] 80012f6: 685b ldr r3, [r3, #4] 80012f8: f5b3 2fa0 cmp.w r3, #327680 ; 0x50000 80012fc: d10c bne.n 8001318 80012fe: 4b72 ldr r3, [pc, #456] ; (80014c8 ) 8001300: 681b ldr r3, [r3, #0] 8001302: 4a71 ldr r2, [pc, #452] ; (80014c8 ) 8001304: f443 2380 orr.w r3, r3, #262144 ; 0x40000 8001308: 6013 str r3, [r2, #0] 800130a: 4b6f ldr r3, [pc, #444] ; (80014c8 ) 800130c: 681b ldr r3, [r3, #0] 800130e: 4a6e ldr r2, [pc, #440] ; (80014c8 ) 8001310: f443 3380 orr.w r3, r3, #65536 ; 0x10000 8001314: 6013 str r3, [r2, #0] 8001316: e00b b.n 8001330 8001318: 4b6b ldr r3, [pc, #428] ; (80014c8 ) 800131a: 681b ldr r3, [r3, #0] 800131c: 4a6a ldr r2, [pc, #424] ; (80014c8 ) 800131e: f423 3380 bic.w r3, r3, #65536 ; 0x10000 8001322: 6013 str r3, [r2, #0] 8001324: 4b68 ldr r3, [pc, #416] ; (80014c8 ) 8001326: 681b ldr r3, [r3, #0] 8001328: 4a67 ldr r2, [pc, #412] ; (80014c8 ) 800132a: f423 2380 bic.w r3, r3, #262144 ; 0x40000 800132e: 6013 str r3, [r2, #0] /* Check the HSE State */ if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF) 8001330: 687b ldr r3, [r7, #4] 8001332: 685b ldr r3, [r3, #4] 8001334: 2b00 cmp r3, #0 8001336: d013 beq.n 8001360 { /* Get Start Tick */ tickstart = HAL_GetTick(); 8001338: f7ff f9d4 bl 80006e4 800133c: 6138 str r0, [r7, #16] /* Wait till HSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 800133e: e008 b.n 8001352 { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 8001340: f7ff f9d0 bl 80006e4 8001344: 4602 mov r2, r0 8001346: 693b ldr r3, [r7, #16] 8001348: 1ad3 subs r3, r2, r3 800134a: 2b64 cmp r3, #100 ; 0x64 800134c: d901 bls.n 8001352 { return HAL_TIMEOUT; 800134e: 2303 movs r3, #3 8001350: e200 b.n 8001754 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 8001352: 4b5d ldr r3, [pc, #372] ; (80014c8 ) 8001354: 681b ldr r3, [r3, #0] 8001356: f403 3300 and.w r3, r3, #131072 ; 0x20000 800135a: 2b00 cmp r3, #0 800135c: d0f0 beq.n 8001340 800135e: e014 b.n 800138a } } else { /* Get Start Tick */ tickstart = HAL_GetTick(); 8001360: f7ff f9c0 bl 80006e4 8001364: 6138 str r0, [r7, #16] /* Wait till HSE is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) 8001366: e008 b.n 800137a { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 8001368: f7ff f9bc bl 80006e4 800136c: 4602 mov r2, r0 800136e: 693b ldr r3, [r7, #16] 8001370: 1ad3 subs r3, r2, r3 8001372: 2b64 cmp r3, #100 ; 0x64 8001374: d901 bls.n 800137a { return HAL_TIMEOUT; 8001376: 2303 movs r3, #3 8001378: e1ec b.n 8001754 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) 800137a: 4b53 ldr r3, [pc, #332] ; (80014c8 ) 800137c: 681b ldr r3, [r3, #0] 800137e: f403 3300 and.w r3, r3, #131072 ; 0x20000 8001382: 2b00 cmp r3, #0 8001384: d1f0 bne.n 8001368 8001386: e000 b.n 800138a if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 8001388: bf00 nop } } } } /*----------------------------- HSI Configuration --------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) 800138a: 687b ldr r3, [r7, #4] 800138c: 681b ldr r3, [r3, #0] 800138e: f003 0302 and.w r3, r3, #2 8001392: 2b00 cmp r3, #0 8001394: d063 beq.n 800145e /* Check the parameters */ assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI) 8001396: 4b4c ldr r3, [pc, #304] ; (80014c8 ) 8001398: 685b ldr r3, [r3, #4] 800139a: f003 030c and.w r3, r3, #12 800139e: 2b00 cmp r3, #0 80013a0: d00b beq.n 80013ba || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI_DIV2))) 80013a2: 4b49 ldr r3, [pc, #292] ; (80014c8 ) 80013a4: 685b ldr r3, [r3, #4] 80013a6: f003 030c and.w r3, r3, #12 80013aa: 2b08 cmp r3, #8 80013ac: d11c bne.n 80013e8 80013ae: 4b46 ldr r3, [pc, #280] ; (80014c8 ) 80013b0: 685b ldr r3, [r3, #4] 80013b2: f403 3380 and.w r3, r3, #65536 ; 0x10000 80013b6: 2b00 cmp r3, #0 80013b8: d116 bne.n 80013e8 { /* When HSI is used as system clock it will not disabled */ if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) 80013ba: 4b43 ldr r3, [pc, #268] ; (80014c8 ) 80013bc: 681b ldr r3, [r3, #0] 80013be: f003 0302 and.w r3, r3, #2 80013c2: 2b00 cmp r3, #0 80013c4: d005 beq.n 80013d2 80013c6: 687b ldr r3, [r7, #4] 80013c8: 691b ldr r3, [r3, #16] 80013ca: 2b01 cmp r3, #1 80013cc: d001 beq.n 80013d2 { return HAL_ERROR; 80013ce: 2301 movs r3, #1 80013d0: e1c0 b.n 8001754 } /* Otherwise, just the calibration is allowed */ else { /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 80013d2: 4b3d ldr r3, [pc, #244] ; (80014c8 ) 80013d4: 681b ldr r3, [r3, #0] 80013d6: f023 02f8 bic.w r2, r3, #248 ; 0xf8 80013da: 687b ldr r3, [r7, #4] 80013dc: 695b ldr r3, [r3, #20] 80013de: 00db lsls r3, r3, #3 80013e0: 4939 ldr r1, [pc, #228] ; (80014c8 ) 80013e2: 4313 orrs r3, r2 80013e4: 600b str r3, [r1, #0] if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) 80013e6: e03a b.n 800145e } } else { /* Check the HSI State */ if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF) 80013e8: 687b ldr r3, [r7, #4] 80013ea: 691b ldr r3, [r3, #16] 80013ec: 2b00 cmp r3, #0 80013ee: d020 beq.n 8001432 { /* Enable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_ENABLE(); 80013f0: 4b36 ldr r3, [pc, #216] ; (80014cc ) 80013f2: 2201 movs r2, #1 80013f4: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 80013f6: f7ff f975 bl 80006e4 80013fa: 6138 str r0, [r7, #16] /* Wait till HSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 80013fc: e008 b.n 8001410 { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 80013fe: f7ff f971 bl 80006e4 8001402: 4602 mov r2, r0 8001404: 693b ldr r3, [r7, #16] 8001406: 1ad3 subs r3, r2, r3 8001408: 2b02 cmp r3, #2 800140a: d901 bls.n 8001410 { return HAL_TIMEOUT; 800140c: 2303 movs r3, #3 800140e: e1a1 b.n 8001754 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 8001410: 4b2d ldr r3, [pc, #180] ; (80014c8 ) 8001412: 681b ldr r3, [r3, #0] 8001414: f003 0302 and.w r3, r3, #2 8001418: 2b00 cmp r3, #0 800141a: d0f0 beq.n 80013fe } } /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 800141c: 4b2a ldr r3, [pc, #168] ; (80014c8 ) 800141e: 681b ldr r3, [r3, #0] 8001420: f023 02f8 bic.w r2, r3, #248 ; 0xf8 8001424: 687b ldr r3, [r7, #4] 8001426: 695b ldr r3, [r3, #20] 8001428: 00db lsls r3, r3, #3 800142a: 4927 ldr r1, [pc, #156] ; (80014c8 ) 800142c: 4313 orrs r3, r2 800142e: 600b str r3, [r1, #0] 8001430: e015 b.n 800145e } else { /* Disable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_DISABLE(); 8001432: 4b26 ldr r3, [pc, #152] ; (80014cc ) 8001434: 2200 movs r2, #0 8001436: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8001438: f7ff f954 bl 80006e4 800143c: 6138 str r0, [r7, #16] /* Wait till HSI is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) 800143e: e008 b.n 8001452 { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 8001440: f7ff f950 bl 80006e4 8001444: 4602 mov r2, r0 8001446: 693b ldr r3, [r7, #16] 8001448: 1ad3 subs r3, r2, r3 800144a: 2b02 cmp r3, #2 800144c: d901 bls.n 8001452 { return HAL_TIMEOUT; 800144e: 2303 movs r3, #3 8001450: e180 b.n 8001754 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) 8001452: 4b1d ldr r3, [pc, #116] ; (80014c8 ) 8001454: 681b ldr r3, [r3, #0] 8001456: f003 0302 and.w r3, r3, #2 800145a: 2b00 cmp r3, #0 800145c: d1f0 bne.n 8001440 } } } } /*------------------------------ LSI Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) 800145e: 687b ldr r3, [r7, #4] 8001460: 681b ldr r3, [r3, #0] 8001462: f003 0308 and.w r3, r3, #8 8001466: 2b00 cmp r3, #0 8001468: d03a beq.n 80014e0 { /* Check the parameters */ assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); /* Check the LSI State */ if (RCC_OscInitStruct->LSIState != RCC_LSI_OFF) 800146a: 687b ldr r3, [r7, #4] 800146c: 699b ldr r3, [r3, #24] 800146e: 2b00 cmp r3, #0 8001470: d019 beq.n 80014a6 { /* Enable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_ENABLE(); 8001472: 4b17 ldr r3, [pc, #92] ; (80014d0 ) 8001474: 2201 movs r2, #1 8001476: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8001478: f7ff f934 bl 80006e4 800147c: 6138 str r0, [r7, #16] /* Wait till LSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) 800147e: e008 b.n 8001492 { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 8001480: f7ff f930 bl 80006e4 8001484: 4602 mov r2, r0 8001486: 693b ldr r3, [r7, #16] 8001488: 1ad3 subs r3, r2, r3 800148a: 2b02 cmp r3, #2 800148c: d901 bls.n 8001492 { return HAL_TIMEOUT; 800148e: 2303 movs r3, #3 8001490: e160 b.n 8001754 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) 8001492: 4b0d ldr r3, [pc, #52] ; (80014c8 ) 8001494: 6a5b ldr r3, [r3, #36] ; 0x24 8001496: f003 0302 and.w r3, r3, #2 800149a: 2b00 cmp r3, #0 800149c: d0f0 beq.n 8001480 } } /* To have a fully stabilized clock in the specified range, a software delay of 1ms should be added.*/ RCC_Delay(1); 800149e: 2001 movs r0, #1 80014a0: f000 fad8 bl 8001a54 80014a4: e01c b.n 80014e0 } else { /* Disable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_DISABLE(); 80014a6: 4b0a ldr r3, [pc, #40] ; (80014d0 ) 80014a8: 2200 movs r2, #0 80014aa: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 80014ac: f7ff f91a bl 80006e4 80014b0: 6138 str r0, [r7, #16] /* Wait till LSI is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) 80014b2: e00f b.n 80014d4 { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 80014b4: f7ff f916 bl 80006e4 80014b8: 4602 mov r2, r0 80014ba: 693b ldr r3, [r7, #16] 80014bc: 1ad3 subs r3, r2, r3 80014be: 2b02 cmp r3, #2 80014c0: d908 bls.n 80014d4 { return HAL_TIMEOUT; 80014c2: 2303 movs r3, #3 80014c4: e146 b.n 8001754 80014c6: bf00 nop 80014c8: 40021000 .word 0x40021000 80014cc: 42420000 .word 0x42420000 80014d0: 42420480 .word 0x42420480 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) 80014d4: 4b92 ldr r3, [pc, #584] ; (8001720 ) 80014d6: 6a5b ldr r3, [r3, #36] ; 0x24 80014d8: f003 0302 and.w r3, r3, #2 80014dc: 2b00 cmp r3, #0 80014de: d1e9 bne.n 80014b4 } } } } /*------------------------------ LSE Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) 80014e0: 687b ldr r3, [r7, #4] 80014e2: 681b ldr r3, [r3, #0] 80014e4: f003 0304 and.w r3, r3, #4 80014e8: 2b00 cmp r3, #0 80014ea: f000 80a6 beq.w 800163a { FlagStatus pwrclkchanged = RESET; 80014ee: 2300 movs r3, #0 80014f0: 75fb strb r3, [r7, #23] /* Check the parameters */ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); /* Update LSE configuration in Backup Domain control register */ /* Requires to enable write access to Backup Domain of necessary */ if (__HAL_RCC_PWR_IS_CLK_DISABLED()) 80014f2: 4b8b ldr r3, [pc, #556] ; (8001720 ) 80014f4: 69db ldr r3, [r3, #28] 80014f6: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 80014fa: 2b00 cmp r3, #0 80014fc: d10d bne.n 800151a { __HAL_RCC_PWR_CLK_ENABLE(); 80014fe: 4b88 ldr r3, [pc, #544] ; (8001720 ) 8001500: 69db ldr r3, [r3, #28] 8001502: 4a87 ldr r2, [pc, #540] ; (8001720 ) 8001504: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 8001508: 61d3 str r3, [r2, #28] 800150a: 4b85 ldr r3, [pc, #532] ; (8001720 ) 800150c: 69db ldr r3, [r3, #28] 800150e: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 8001512: 60bb str r3, [r7, #8] 8001514: 68bb ldr r3, [r7, #8] pwrclkchanged = SET; 8001516: 2301 movs r3, #1 8001518: 75fb strb r3, [r7, #23] } if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 800151a: 4b82 ldr r3, [pc, #520] ; (8001724 ) 800151c: 681b ldr r3, [r3, #0] 800151e: f403 7380 and.w r3, r3, #256 ; 0x100 8001522: 2b00 cmp r3, #0 8001524: d118 bne.n 8001558 { /* Enable write access to Backup domain */ SET_BIT(PWR->CR, PWR_CR_DBP); 8001526: 4b7f ldr r3, [pc, #508] ; (8001724 ) 8001528: 681b ldr r3, [r3, #0] 800152a: 4a7e ldr r2, [pc, #504] ; (8001724 ) 800152c: f443 7380 orr.w r3, r3, #256 ; 0x100 8001530: 6013 str r3, [r2, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 8001532: f7ff f8d7 bl 80006e4 8001536: 6138 str r0, [r7, #16] while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8001538: e008 b.n 800154c { if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 800153a: f7ff f8d3 bl 80006e4 800153e: 4602 mov r2, r0 8001540: 693b ldr r3, [r7, #16] 8001542: 1ad3 subs r3, r2, r3 8001544: 2b64 cmp r3, #100 ; 0x64 8001546: d901 bls.n 800154c { return HAL_TIMEOUT; 8001548: 2303 movs r3, #3 800154a: e103 b.n 8001754 while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 800154c: 4b75 ldr r3, [pc, #468] ; (8001724 ) 800154e: 681b ldr r3, [r3, #0] 8001550: f403 7380 and.w r3, r3, #256 ; 0x100 8001554: 2b00 cmp r3, #0 8001556: d0f0 beq.n 800153a } } } /* Set the new LSE configuration -----------------------------------------*/ __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); 8001558: 687b ldr r3, [r7, #4] 800155a: 68db ldr r3, [r3, #12] 800155c: 2b01 cmp r3, #1 800155e: d106 bne.n 800156e 8001560: 4b6f ldr r3, [pc, #444] ; (8001720 ) 8001562: 6a1b ldr r3, [r3, #32] 8001564: 4a6e ldr r2, [pc, #440] ; (8001720 ) 8001566: f043 0301 orr.w r3, r3, #1 800156a: 6213 str r3, [r2, #32] 800156c: e02d b.n 80015ca 800156e: 687b ldr r3, [r7, #4] 8001570: 68db ldr r3, [r3, #12] 8001572: 2b00 cmp r3, #0 8001574: d10c bne.n 8001590 8001576: 4b6a ldr r3, [pc, #424] ; (8001720 ) 8001578: 6a1b ldr r3, [r3, #32] 800157a: 4a69 ldr r2, [pc, #420] ; (8001720 ) 800157c: f023 0301 bic.w r3, r3, #1 8001580: 6213 str r3, [r2, #32] 8001582: 4b67 ldr r3, [pc, #412] ; (8001720 ) 8001584: 6a1b ldr r3, [r3, #32] 8001586: 4a66 ldr r2, [pc, #408] ; (8001720 ) 8001588: f023 0304 bic.w r3, r3, #4 800158c: 6213 str r3, [r2, #32] 800158e: e01c b.n 80015ca 8001590: 687b ldr r3, [r7, #4] 8001592: 68db ldr r3, [r3, #12] 8001594: 2b05 cmp r3, #5 8001596: d10c bne.n 80015b2 8001598: 4b61 ldr r3, [pc, #388] ; (8001720 ) 800159a: 6a1b ldr r3, [r3, #32] 800159c: 4a60 ldr r2, [pc, #384] ; (8001720 ) 800159e: f043 0304 orr.w r3, r3, #4 80015a2: 6213 str r3, [r2, #32] 80015a4: 4b5e ldr r3, [pc, #376] ; (8001720 ) 80015a6: 6a1b ldr r3, [r3, #32] 80015a8: 4a5d ldr r2, [pc, #372] ; (8001720 ) 80015aa: f043 0301 orr.w r3, r3, #1 80015ae: 6213 str r3, [r2, #32] 80015b0: e00b b.n 80015ca 80015b2: 4b5b ldr r3, [pc, #364] ; (8001720 ) 80015b4: 6a1b ldr r3, [r3, #32] 80015b6: 4a5a ldr r2, [pc, #360] ; (8001720 ) 80015b8: f023 0301 bic.w r3, r3, #1 80015bc: 6213 str r3, [r2, #32] 80015be: 4b58 ldr r3, [pc, #352] ; (8001720 ) 80015c0: 6a1b ldr r3, [r3, #32] 80015c2: 4a57 ldr r2, [pc, #348] ; (8001720 ) 80015c4: f023 0304 bic.w r3, r3, #4 80015c8: 6213 str r3, [r2, #32] /* Check the LSE State */ if (RCC_OscInitStruct->LSEState != RCC_LSE_OFF) 80015ca: 687b ldr r3, [r7, #4] 80015cc: 68db ldr r3, [r3, #12] 80015ce: 2b00 cmp r3, #0 80015d0: d015 beq.n 80015fe { /* Get Start Tick */ tickstart = HAL_GetTick(); 80015d2: f7ff f887 bl 80006e4 80015d6: 6138 str r0, [r7, #16] /* Wait till LSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 80015d8: e00a b.n 80015f0 { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 80015da: f7ff f883 bl 80006e4 80015de: 4602 mov r2, r0 80015e0: 693b ldr r3, [r7, #16] 80015e2: 1ad3 subs r3, r2, r3 80015e4: f241 3288 movw r2, #5000 ; 0x1388 80015e8: 4293 cmp r3, r2 80015ea: d901 bls.n 80015f0 { return HAL_TIMEOUT; 80015ec: 2303 movs r3, #3 80015ee: e0b1 b.n 8001754 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 80015f0: 4b4b ldr r3, [pc, #300] ; (8001720 ) 80015f2: 6a1b ldr r3, [r3, #32] 80015f4: f003 0302 and.w r3, r3, #2 80015f8: 2b00 cmp r3, #0 80015fa: d0ee beq.n 80015da 80015fc: e014 b.n 8001628 } } else { /* Get Start Tick */ tickstart = HAL_GetTick(); 80015fe: f7ff f871 bl 80006e4 8001602: 6138 str r0, [r7, #16] /* Wait till LSE is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) 8001604: e00a b.n 800161c { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 8001606: f7ff f86d bl 80006e4 800160a: 4602 mov r2, r0 800160c: 693b ldr r3, [r7, #16] 800160e: 1ad3 subs r3, r2, r3 8001610: f241 3288 movw r2, #5000 ; 0x1388 8001614: 4293 cmp r3, r2 8001616: d901 bls.n 800161c { return HAL_TIMEOUT; 8001618: 2303 movs r3, #3 800161a: e09b b.n 8001754 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) 800161c: 4b40 ldr r3, [pc, #256] ; (8001720 ) 800161e: 6a1b ldr r3, [r3, #32] 8001620: f003 0302 and.w r3, r3, #2 8001624: 2b00 cmp r3, #0 8001626: d1ee bne.n 8001606 } } } /* Require to disable power clock if necessary */ if (pwrclkchanged == SET) 8001628: 7dfb ldrb r3, [r7, #23] 800162a: 2b01 cmp r3, #1 800162c: d105 bne.n 800163a { __HAL_RCC_PWR_CLK_DISABLE(); 800162e: 4b3c ldr r3, [pc, #240] ; (8001720 ) 8001630: 69db ldr r3, [r3, #28] 8001632: 4a3b ldr r2, [pc, #236] ; (8001720 ) 8001634: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000 8001638: 61d3 str r3, [r2, #28] #endif /* RCC_CR_PLL2ON */ /*-------------------------------- PLL Configuration -----------------------*/ /* Check the parameters */ assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) 800163a: 687b ldr r3, [r7, #4] 800163c: 69db ldr r3, [r3, #28] 800163e: 2b00 cmp r3, #0 8001640: f000 8087 beq.w 8001752 { /* Check if the PLL is used as system clock or not */ if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) 8001644: 4b36 ldr r3, [pc, #216] ; (8001720 ) 8001646: 685b ldr r3, [r3, #4] 8001648: f003 030c and.w r3, r3, #12 800164c: 2b08 cmp r3, #8 800164e: d061 beq.n 8001714 { if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) 8001650: 687b ldr r3, [r7, #4] 8001652: 69db ldr r3, [r3, #28] 8001654: 2b02 cmp r3, #2 8001656: d146 bne.n 80016e6 /* Check the parameters */ assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource)); assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL)); /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 8001658: 4b33 ldr r3, [pc, #204] ; (8001728 ) 800165a: 2200 movs r2, #0 800165c: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 800165e: f7ff f841 bl 80006e4 8001662: 6138 str r0, [r7, #16] /* Wait till PLL is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 8001664: e008 b.n 8001678 { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 8001666: f7ff f83d bl 80006e4 800166a: 4602 mov r2, r0 800166c: 693b ldr r3, [r7, #16] 800166e: 1ad3 subs r3, r2, r3 8001670: 2b02 cmp r3, #2 8001672: d901 bls.n 8001678 { return HAL_TIMEOUT; 8001674: 2303 movs r3, #3 8001676: e06d b.n 8001754 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 8001678: 4b29 ldr r3, [pc, #164] ; (8001720 ) 800167a: 681b ldr r3, [r3, #0] 800167c: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 8001680: 2b00 cmp r3, #0 8001682: d1f0 bne.n 8001666 } } /* Configure the HSE prediv factor --------------------------------*/ /* It can be written only when the PLL is disabled. Not used in PLL source is different than HSE */ if (RCC_OscInitStruct->PLL.PLLSource == RCC_PLLSOURCE_HSE) 8001684: 687b ldr r3, [r7, #4] 8001686: 6a1b ldr r3, [r3, #32] 8001688: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 800168c: d108 bne.n 80016a0 /* Set PREDIV1 source */ SET_BIT(RCC->CFGR2, RCC_OscInitStruct->Prediv1Source); #endif /* RCC_CFGR2_PREDIV1SRC */ /* Set PREDIV1 Value */ __HAL_RCC_HSE_PREDIV_CONFIG(RCC_OscInitStruct->HSEPredivValue); 800168e: 4b24 ldr r3, [pc, #144] ; (8001720 ) 8001690: 685b ldr r3, [r3, #4] 8001692: f423 3200 bic.w r2, r3, #131072 ; 0x20000 8001696: 687b ldr r3, [r7, #4] 8001698: 689b ldr r3, [r3, #8] 800169a: 4921 ldr r1, [pc, #132] ; (8001720 ) 800169c: 4313 orrs r3, r2 800169e: 604b str r3, [r1, #4] } /* Configure the main PLL clock source and multiplication factors. */ __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, 80016a0: 4b1f ldr r3, [pc, #124] ; (8001720 ) 80016a2: 685b ldr r3, [r3, #4] 80016a4: f423 1274 bic.w r2, r3, #3997696 ; 0x3d0000 80016a8: 687b ldr r3, [r7, #4] 80016aa: 6a19 ldr r1, [r3, #32] 80016ac: 687b ldr r3, [r7, #4] 80016ae: 6a5b ldr r3, [r3, #36] ; 0x24 80016b0: 430b orrs r3, r1 80016b2: 491b ldr r1, [pc, #108] ; (8001720 ) 80016b4: 4313 orrs r3, r2 80016b6: 604b str r3, [r1, #4] RCC_OscInitStruct->PLL.PLLMUL); /* Enable the main PLL. */ __HAL_RCC_PLL_ENABLE(); 80016b8: 4b1b ldr r3, [pc, #108] ; (8001728 ) 80016ba: 2201 movs r2, #1 80016bc: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 80016be: f7ff f811 bl 80006e4 80016c2: 6138 str r0, [r7, #16] /* Wait till PLL is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 80016c4: e008 b.n 80016d8 { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 80016c6: f7ff f80d bl 80006e4 80016ca: 4602 mov r2, r0 80016cc: 693b ldr r3, [r7, #16] 80016ce: 1ad3 subs r3, r2, r3 80016d0: 2b02 cmp r3, #2 80016d2: d901 bls.n 80016d8 { return HAL_TIMEOUT; 80016d4: 2303 movs r3, #3 80016d6: e03d b.n 8001754 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 80016d8: 4b11 ldr r3, [pc, #68] ; (8001720 ) 80016da: 681b ldr r3, [r3, #0] 80016dc: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 80016e0: 2b00 cmp r3, #0 80016e2: d0f0 beq.n 80016c6 80016e4: e035 b.n 8001752 } } else { /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 80016e6: 4b10 ldr r3, [pc, #64] ; (8001728 ) 80016e8: 2200 movs r2, #0 80016ea: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 80016ec: f7fe fffa bl 80006e4 80016f0: 6138 str r0, [r7, #16] /* Wait till PLL is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 80016f2: e008 b.n 8001706 { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 80016f4: f7fe fff6 bl 80006e4 80016f8: 4602 mov r2, r0 80016fa: 693b ldr r3, [r7, #16] 80016fc: 1ad3 subs r3, r2, r3 80016fe: 2b02 cmp r3, #2 8001700: d901 bls.n 8001706 { return HAL_TIMEOUT; 8001702: 2303 movs r3, #3 8001704: e026 b.n 8001754 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 8001706: 4b06 ldr r3, [pc, #24] ; (8001720 ) 8001708: 681b ldr r3, [r3, #0] 800170a: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 800170e: 2b00 cmp r3, #0 8001710: d1f0 bne.n 80016f4 8001712: e01e b.n 8001752 } } else { /* Check if there is a request to disable the PLL used as System clock source */ if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) 8001714: 687b ldr r3, [r7, #4] 8001716: 69db ldr r3, [r3, #28] 8001718: 2b01 cmp r3, #1 800171a: d107 bne.n 800172c { return HAL_ERROR; 800171c: 2301 movs r3, #1 800171e: e019 b.n 8001754 8001720: 40021000 .word 0x40021000 8001724: 40007000 .word 0x40007000 8001728: 42420060 .word 0x42420060 } else { /* Do not return HAL_ERROR if request repeats the current configuration */ pll_config = RCC->CFGR; 800172c: 4b0b ldr r3, [pc, #44] ; (800175c ) 800172e: 685b ldr r3, [r3, #4] 8001730: 60fb str r3, [r7, #12] if ((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 8001732: 68fb ldr r3, [r7, #12] 8001734: f403 3280 and.w r2, r3, #65536 ; 0x10000 8001738: 687b ldr r3, [r7, #4] 800173a: 6a1b ldr r3, [r3, #32] 800173c: 429a cmp r2, r3 800173e: d106 bne.n 800174e (READ_BIT(pll_config, RCC_CFGR_PLLMULL) != RCC_OscInitStruct->PLL.PLLMUL)) 8001740: 68fb ldr r3, [r7, #12] 8001742: f403 1270 and.w r2, r3, #3932160 ; 0x3c0000 8001746: 687b ldr r3, [r7, #4] 8001748: 6a5b ldr r3, [r3, #36] ; 0x24 if ((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 800174a: 429a cmp r2, r3 800174c: d001 beq.n 8001752 { return HAL_ERROR; 800174e: 2301 movs r3, #1 8001750: e000 b.n 8001754 } } } } return HAL_OK; 8001752: 2300 movs r3, #0 } 8001754: 4618 mov r0, r3 8001756: 3718 adds r7, #24 8001758: 46bd mov sp, r7 800175a: bd80 pop {r7, pc} 800175c: 40021000 .word 0x40021000 08001760 : * You can use @ref HAL_RCC_GetClockConfig() function to know which clock is * currently used as system clock source. * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) { 8001760: b580 push {r7, lr} 8001762: b084 sub sp, #16 8001764: af00 add r7, sp, #0 8001766: 6078 str r0, [r7, #4] 8001768: 6039 str r1, [r7, #0] uint32_t tickstart; /* Check Null pointer */ if (RCC_ClkInitStruct == NULL) 800176a: 687b ldr r3, [r7, #4] 800176c: 2b00 cmp r3, #0 800176e: d101 bne.n 8001774 { return HAL_ERROR; 8001770: 2301 movs r3, #1 8001772: e0d0 b.n 8001916 must be correctly programmed according to the frequency of the CPU clock (HCLK) of the device. */ #if defined(FLASH_ACR_LATENCY) /* Increasing the number of wait states because of higher CPU frequency */ if (FLatency > __HAL_FLASH_GET_LATENCY()) 8001774: 4b6a ldr r3, [pc, #424] ; (8001920 ) 8001776: 681b ldr r3, [r3, #0] 8001778: f003 0307 and.w r3, r3, #7 800177c: 683a ldr r2, [r7, #0] 800177e: 429a cmp r2, r3 8001780: d910 bls.n 80017a4 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 8001782: 4b67 ldr r3, [pc, #412] ; (8001920 ) 8001784: 681b ldr r3, [r3, #0] 8001786: f023 0207 bic.w r2, r3, #7 800178a: 4965 ldr r1, [pc, #404] ; (8001920 ) 800178c: 683b ldr r3, [r7, #0] 800178e: 4313 orrs r3, r2 8001790: 600b str r3, [r1, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if (__HAL_FLASH_GET_LATENCY() != FLatency) 8001792: 4b63 ldr r3, [pc, #396] ; (8001920 ) 8001794: 681b ldr r3, [r3, #0] 8001796: f003 0307 and.w r3, r3, #7 800179a: 683a ldr r2, [r7, #0] 800179c: 429a cmp r2, r3 800179e: d001 beq.n 80017a4 { return HAL_ERROR; 80017a0: 2301 movs r3, #1 80017a2: e0b8 b.n 8001916 } } #endif /* FLASH_ACR_LATENCY */ /*-------------------------- HCLK Configuration --------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) 80017a4: 687b ldr r3, [r7, #4] 80017a6: 681b ldr r3, [r3, #0] 80017a8: f003 0302 and.w r3, r3, #2 80017ac: 2b00 cmp r3, #0 80017ae: d020 beq.n 80017f2 { /* Set the highest APBx dividers in order to ensure that we do not go through a non-spec phase whatever we decrease or increase HCLK. */ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 80017b0: 687b ldr r3, [r7, #4] 80017b2: 681b ldr r3, [r3, #0] 80017b4: f003 0304 and.w r3, r3, #4 80017b8: 2b00 cmp r3, #0 80017ba: d005 beq.n 80017c8 { MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16); 80017bc: 4b59 ldr r3, [pc, #356] ; (8001924 ) 80017be: 685b ldr r3, [r3, #4] 80017c0: 4a58 ldr r2, [pc, #352] ; (8001924 ) 80017c2: f443 63e0 orr.w r3, r3, #1792 ; 0x700 80017c6: 6053 str r3, [r2, #4] } if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 80017c8: 687b ldr r3, [r7, #4] 80017ca: 681b ldr r3, [r3, #0] 80017cc: f003 0308 and.w r3, r3, #8 80017d0: 2b00 cmp r3, #0 80017d2: d005 beq.n 80017e0 { MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3)); 80017d4: 4b53 ldr r3, [pc, #332] ; (8001924 ) 80017d6: 685b ldr r3, [r3, #4] 80017d8: 4a52 ldr r2, [pc, #328] ; (8001924 ) 80017da: f443 5360 orr.w r3, r3, #14336 ; 0x3800 80017de: 6053 str r3, [r2, #4] } /* Set the new HCLK clock divider */ assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); 80017e0: 4b50 ldr r3, [pc, #320] ; (8001924 ) 80017e2: 685b ldr r3, [r3, #4] 80017e4: f023 02f0 bic.w r2, r3, #240 ; 0xf0 80017e8: 687b ldr r3, [r7, #4] 80017ea: 689b ldr r3, [r3, #8] 80017ec: 494d ldr r1, [pc, #308] ; (8001924 ) 80017ee: 4313 orrs r3, r2 80017f0: 604b str r3, [r1, #4] } /*------------------------- SYSCLK Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) 80017f2: 687b ldr r3, [r7, #4] 80017f4: 681b ldr r3, [r3, #0] 80017f6: f003 0301 and.w r3, r3, #1 80017fa: 2b00 cmp r3, #0 80017fc: d040 beq.n 8001880 { assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); /* HSE is selected as System Clock Source */ if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) 80017fe: 687b ldr r3, [r7, #4] 8001800: 685b ldr r3, [r3, #4] 8001802: 2b01 cmp r3, #1 8001804: d107 bne.n 8001816 { /* Check the HSE ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 8001806: 4b47 ldr r3, [pc, #284] ; (8001924 ) 8001808: 681b ldr r3, [r3, #0] 800180a: f403 3300 and.w r3, r3, #131072 ; 0x20000 800180e: 2b00 cmp r3, #0 8001810: d115 bne.n 800183e { return HAL_ERROR; 8001812: 2301 movs r3, #1 8001814: e07f b.n 8001916 } } /* PLL is selected as System Clock Source */ else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) 8001816: 687b ldr r3, [r7, #4] 8001818: 685b ldr r3, [r3, #4] 800181a: 2b02 cmp r3, #2 800181c: d107 bne.n 800182e { /* Check the PLL ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 800181e: 4b41 ldr r3, [pc, #260] ; (8001924 ) 8001820: 681b ldr r3, [r3, #0] 8001822: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 8001826: 2b00 cmp r3, #0 8001828: d109 bne.n 800183e { return HAL_ERROR; 800182a: 2301 movs r3, #1 800182c: e073 b.n 8001916 } /* HSI is selected as System Clock Source */ else { /* Check the HSI ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 800182e: 4b3d ldr r3, [pc, #244] ; (8001924 ) 8001830: 681b ldr r3, [r3, #0] 8001832: f003 0302 and.w r3, r3, #2 8001836: 2b00 cmp r3, #0 8001838: d101 bne.n 800183e { return HAL_ERROR; 800183a: 2301 movs r3, #1 800183c: e06b b.n 8001916 } } __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource); 800183e: 4b39 ldr r3, [pc, #228] ; (8001924 ) 8001840: 685b ldr r3, [r3, #4] 8001842: f023 0203 bic.w r2, r3, #3 8001846: 687b ldr r3, [r7, #4] 8001848: 685b ldr r3, [r3, #4] 800184a: 4936 ldr r1, [pc, #216] ; (8001924 ) 800184c: 4313 orrs r3, r2 800184e: 604b str r3, [r1, #4] /* Get Start Tick */ tickstart = HAL_GetTick(); 8001850: f7fe ff48 bl 80006e4 8001854: 60f8 str r0, [r7, #12] while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 8001856: e00a b.n 800186e { if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) 8001858: f7fe ff44 bl 80006e4 800185c: 4602 mov r2, r0 800185e: 68fb ldr r3, [r7, #12] 8001860: 1ad3 subs r3, r2, r3 8001862: f241 3288 movw r2, #5000 ; 0x1388 8001866: 4293 cmp r3, r2 8001868: d901 bls.n 800186e { return HAL_TIMEOUT; 800186a: 2303 movs r3, #3 800186c: e053 b.n 8001916 while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 800186e: 4b2d ldr r3, [pc, #180] ; (8001924 ) 8001870: 685b ldr r3, [r3, #4] 8001872: f003 020c and.w r2, r3, #12 8001876: 687b ldr r3, [r7, #4] 8001878: 685b ldr r3, [r3, #4] 800187a: 009b lsls r3, r3, #2 800187c: 429a cmp r2, r3 800187e: d1eb bne.n 8001858 } } #if defined(FLASH_ACR_LATENCY) /* Decreasing the number of wait states because of lower CPU frequency */ if (FLatency < __HAL_FLASH_GET_LATENCY()) 8001880: 4b27 ldr r3, [pc, #156] ; (8001920 ) 8001882: 681b ldr r3, [r3, #0] 8001884: f003 0307 and.w r3, r3, #7 8001888: 683a ldr r2, [r7, #0] 800188a: 429a cmp r2, r3 800188c: d210 bcs.n 80018b0 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 800188e: 4b24 ldr r3, [pc, #144] ; (8001920 ) 8001890: 681b ldr r3, [r3, #0] 8001892: f023 0207 bic.w r2, r3, #7 8001896: 4922 ldr r1, [pc, #136] ; (8001920 ) 8001898: 683b ldr r3, [r7, #0] 800189a: 4313 orrs r3, r2 800189c: 600b str r3, [r1, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if (__HAL_FLASH_GET_LATENCY() != FLatency) 800189e: 4b20 ldr r3, [pc, #128] ; (8001920 ) 80018a0: 681b ldr r3, [r3, #0] 80018a2: f003 0307 and.w r3, r3, #7 80018a6: 683a ldr r2, [r7, #0] 80018a8: 429a cmp r2, r3 80018aa: d001 beq.n 80018b0 { return HAL_ERROR; 80018ac: 2301 movs r3, #1 80018ae: e032 b.n 8001916 } } #endif /* FLASH_ACR_LATENCY */ /*-------------------------- PCLK1 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 80018b0: 687b ldr r3, [r7, #4] 80018b2: 681b ldr r3, [r3, #0] 80018b4: f003 0304 and.w r3, r3, #4 80018b8: 2b00 cmp r3, #0 80018ba: d008 beq.n 80018ce { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider); 80018bc: 4b19 ldr r3, [pc, #100] ; (8001924 ) 80018be: 685b ldr r3, [r3, #4] 80018c0: f423 62e0 bic.w r2, r3, #1792 ; 0x700 80018c4: 687b ldr r3, [r7, #4] 80018c6: 68db ldr r3, [r3, #12] 80018c8: 4916 ldr r1, [pc, #88] ; (8001924 ) 80018ca: 4313 orrs r3, r2 80018cc: 604b str r3, [r1, #4] } /*-------------------------- PCLK2 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 80018ce: 687b ldr r3, [r7, #4] 80018d0: 681b ldr r3, [r3, #0] 80018d2: f003 0308 and.w r3, r3, #8 80018d6: 2b00 cmp r3, #0 80018d8: d009 beq.n 80018ee { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3)); 80018da: 4b12 ldr r3, [pc, #72] ; (8001924 ) 80018dc: 685b ldr r3, [r3, #4] 80018de: f423 5260 bic.w r2, r3, #14336 ; 0x3800 80018e2: 687b ldr r3, [r7, #4] 80018e4: 691b ldr r3, [r3, #16] 80018e6: 00db lsls r3, r3, #3 80018e8: 490e ldr r1, [pc, #56] ; (8001924 ) 80018ea: 4313 orrs r3, r2 80018ec: 604b str r3, [r1, #4] } /* Update the SystemCoreClock global variable */ SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]; 80018ee: f000 f821 bl 8001934 80018f2: 4602 mov r2, r0 80018f4: 4b0b ldr r3, [pc, #44] ; (8001924 ) 80018f6: 685b ldr r3, [r3, #4] 80018f8: 091b lsrs r3, r3, #4 80018fa: f003 030f and.w r3, r3, #15 80018fe: 490a ldr r1, [pc, #40] ; (8001928 ) 8001900: 5ccb ldrb r3, [r1, r3] 8001902: fa22 f303 lsr.w r3, r2, r3 8001906: 4a09 ldr r2, [pc, #36] ; (800192c ) 8001908: 6013 str r3, [r2, #0] /* Configure the source of time base considering new system clocks settings*/ HAL_InitTick(uwTickPrio); 800190a: 4b09 ldr r3, [pc, #36] ; (8001930 ) 800190c: 681b ldr r3, [r3, #0] 800190e: 4618 mov r0, r3 8001910: f7fe fea6 bl 8000660 return HAL_OK; 8001914: 2300 movs r3, #0 } 8001916: 4618 mov r0, r3 8001918: 3710 adds r7, #16 800191a: 46bd mov sp, r7 800191c: bd80 pop {r7, pc} 800191e: bf00 nop 8001920: 40022000 .word 0x40022000 8001924: 40021000 .word 0x40021000 8001928: 080028f4 .word 0x080028f4 800192c: 20000000 .word 0x20000000 8001930: 20000004 .word 0x20000004 08001934 : * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect. * * @retval SYSCLK frequency */ uint32_t HAL_RCC_GetSysClockFreq(void) { 8001934: b490 push {r4, r7} 8001936: b08a sub sp, #40 ; 0x28 8001938: af00 add r7, sp, #0 #if defined(RCC_CFGR2_PREDIV1SRC) const uint8_t aPLLMULFactorTable[14] = {0, 0, 4, 5, 6, 7, 8, 9, 0, 0, 0, 0, 0, 13}; const uint8_t aPredivFactorTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}; #else const uint8_t aPLLMULFactorTable[16] = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16}; 800193a: 4b29 ldr r3, [pc, #164] ; (80019e0 ) 800193c: 1d3c adds r4, r7, #4 800193e: cb0f ldmia r3, {r0, r1, r2, r3} 8001940: e884 000f stmia.w r4, {r0, r1, r2, r3} #if defined(RCC_CFGR2_PREDIV1) const uint8_t aPredivFactorTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}; #else const uint8_t aPredivFactorTable[2] = {1, 2}; 8001944: f240 2301 movw r3, #513 ; 0x201 8001948: 803b strh r3, [r7, #0] #endif /*RCC_CFGR2_PREDIV1*/ #endif uint32_t tmpreg = 0U, prediv = 0U, pllclk = 0U, pllmul = 0U; 800194a: 2300 movs r3, #0 800194c: 61fb str r3, [r7, #28] 800194e: 2300 movs r3, #0 8001950: 61bb str r3, [r7, #24] 8001952: 2300 movs r3, #0 8001954: 627b str r3, [r7, #36] ; 0x24 8001956: 2300 movs r3, #0 8001958: 617b str r3, [r7, #20] uint32_t sysclockfreq = 0U; 800195a: 2300 movs r3, #0 800195c: 623b str r3, [r7, #32] #if defined(RCC_CFGR2_PREDIV1SRC) uint32_t prediv2 = 0U, pll2mul = 0U; #endif /*RCC_CFGR2_PREDIV1SRC*/ tmpreg = RCC->CFGR; 800195e: 4b21 ldr r3, [pc, #132] ; (80019e4 ) 8001960: 685b ldr r3, [r3, #4] 8001962: 61fb str r3, [r7, #28] /* Get SYSCLK source -------------------------------------------------------*/ switch (tmpreg & RCC_CFGR_SWS) 8001964: 69fb ldr r3, [r7, #28] 8001966: f003 030c and.w r3, r3, #12 800196a: 2b04 cmp r3, #4 800196c: d002 beq.n 8001974 800196e: 2b08 cmp r3, #8 8001970: d003 beq.n 800197a 8001972: e02b b.n 80019cc { case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */ { sysclockfreq = HSE_VALUE; 8001974: 4b1c ldr r3, [pc, #112] ; (80019e8 ) 8001976: 623b str r3, [r7, #32] break; 8001978: e02b b.n 80019d2 } case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */ { pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos]; 800197a: 69fb ldr r3, [r7, #28] 800197c: 0c9b lsrs r3, r3, #18 800197e: f003 030f and.w r3, r3, #15 8001982: 3328 adds r3, #40 ; 0x28 8001984: 443b add r3, r7 8001986: f813 3c24 ldrb.w r3, [r3, #-36] 800198a: 617b str r3, [r7, #20] if ((tmpreg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2) 800198c: 69fb ldr r3, [r7, #28] 800198e: f403 3380 and.w r3, r3, #65536 ; 0x10000 8001992: 2b00 cmp r3, #0 8001994: d012 beq.n 80019bc { #if defined(RCC_CFGR2_PREDIV1) prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> RCC_CFGR2_PREDIV1_Pos]; #else prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos]; 8001996: 4b13 ldr r3, [pc, #76] ; (80019e4 ) 8001998: 685b ldr r3, [r3, #4] 800199a: 0c5b lsrs r3, r3, #17 800199c: f003 0301 and.w r3, r3, #1 80019a0: 3328 adds r3, #40 ; 0x28 80019a2: 443b add r3, r7 80019a4: f813 3c28 ldrb.w r3, [r3, #-40] 80019a8: 61bb str r3, [r7, #24] { pllclk = pllclk / 2; } #else /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */ pllclk = (uint32_t)((HSE_VALUE * pllmul) / prediv); 80019aa: 697b ldr r3, [r7, #20] 80019ac: 4a0e ldr r2, [pc, #56] ; (80019e8 ) 80019ae: fb03 f202 mul.w r2, r3, r2 80019b2: 69bb ldr r3, [r7, #24] 80019b4: fbb2 f3f3 udiv r3, r2, r3 80019b8: 627b str r3, [r7, #36] ; 0x24 80019ba: e004 b.n 80019c6 #endif /*RCC_CFGR2_PREDIV1SRC*/ } else { /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */ pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul); 80019bc: 697b ldr r3, [r7, #20] 80019be: 4a0b ldr r2, [pc, #44] ; (80019ec ) 80019c0: fb02 f303 mul.w r3, r2, r3 80019c4: 627b str r3, [r7, #36] ; 0x24 } sysclockfreq = pllclk; 80019c6: 6a7b ldr r3, [r7, #36] ; 0x24 80019c8: 623b str r3, [r7, #32] break; 80019ca: e002 b.n 80019d2 } case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */ default: /* HSI used as system clock */ { sysclockfreq = HSI_VALUE; 80019cc: 4b06 ldr r3, [pc, #24] ; (80019e8 ) 80019ce: 623b str r3, [r7, #32] break; 80019d0: bf00 nop } } return sysclockfreq; 80019d2: 6a3b ldr r3, [r7, #32] } 80019d4: 4618 mov r0, r3 80019d6: 3728 adds r7, #40 ; 0x28 80019d8: 46bd mov sp, r7 80019da: bc90 pop {r4, r7} 80019dc: 4770 bx lr 80019de: bf00 nop 80019e0: 080028e4 .word 0x080028e4 80019e4: 40021000 .word 0x40021000 80019e8: 007a1200 .word 0x007a1200 80019ec: 003d0900 .word 0x003d0900 080019f0 : * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency * and updated within this function * @retval HCLK frequency */ uint32_t HAL_RCC_GetHCLKFreq(void) { 80019f0: b480 push {r7} 80019f2: af00 add r7, sp, #0 return SystemCoreClock; 80019f4: 4b02 ldr r3, [pc, #8] ; (8001a00 ) 80019f6: 681b ldr r3, [r3, #0] } 80019f8: 4618 mov r0, r3 80019fa: 46bd mov sp, r7 80019fc: bc80 pop {r7} 80019fe: 4770 bx lr 8001a00: 20000000 .word 0x20000000 08001a04 : * @note Each time PCLK1 changes, this function must be called to update the * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK1 frequency */ uint32_t HAL_RCC_GetPCLK1Freq(void) { 8001a04: b580 push {r7, lr} 8001a06: af00 add r7, sp, #0 /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]); 8001a08: f7ff fff2 bl 80019f0 8001a0c: 4602 mov r2, r0 8001a0e: 4b05 ldr r3, [pc, #20] ; (8001a24 ) 8001a10: 685b ldr r3, [r3, #4] 8001a12: 0a1b lsrs r3, r3, #8 8001a14: f003 0307 and.w r3, r3, #7 8001a18: 4903 ldr r1, [pc, #12] ; (8001a28 ) 8001a1a: 5ccb ldrb r3, [r1, r3] 8001a1c: fa22 f303 lsr.w r3, r2, r3 } 8001a20: 4618 mov r0, r3 8001a22: bd80 pop {r7, pc} 8001a24: 40021000 .word 0x40021000 8001a28: 08002904 .word 0x08002904 08001a2c : * @note Each time PCLK2 changes, this function must be called to update the * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK2 frequency */ uint32_t HAL_RCC_GetPCLK2Freq(void) { 8001a2c: b580 push {r7, lr} 8001a2e: af00 add r7, sp, #0 /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]); 8001a30: f7ff ffde bl 80019f0 8001a34: 4602 mov r2, r0 8001a36: 4b05 ldr r3, [pc, #20] ; (8001a4c ) 8001a38: 685b ldr r3, [r3, #4] 8001a3a: 0adb lsrs r3, r3, #11 8001a3c: f003 0307 and.w r3, r3, #7 8001a40: 4903 ldr r1, [pc, #12] ; (8001a50 ) 8001a42: 5ccb ldrb r3, [r1, r3] 8001a44: fa22 f303 lsr.w r3, r2, r3 } 8001a48: 4618 mov r0, r3 8001a4a: bd80 pop {r7, pc} 8001a4c: 40021000 .word 0x40021000 8001a50: 08002904 .word 0x08002904 08001a54 : * @brief This function provides delay (in milliseconds) based on CPU cycles method. * @param mdelay: specifies the delay time length, in milliseconds. * @retval None */ static void RCC_Delay(uint32_t mdelay) { 8001a54: b480 push {r7} 8001a56: b085 sub sp, #20 8001a58: af00 add r7, sp, #0 8001a5a: 6078 str r0, [r7, #4] __IO uint32_t Delay = mdelay * (SystemCoreClock / 8U / 1000U); 8001a5c: 4b0a ldr r3, [pc, #40] ; (8001a88 ) 8001a5e: 681b ldr r3, [r3, #0] 8001a60: 4a0a ldr r2, [pc, #40] ; (8001a8c ) 8001a62: fba2 2303 umull r2, r3, r2, r3 8001a66: 0a5b lsrs r3, r3, #9 8001a68: 687a ldr r2, [r7, #4] 8001a6a: fb02 f303 mul.w r3, r2, r3 8001a6e: 60fb str r3, [r7, #12] do { __NOP(); 8001a70: bf00 nop } while (Delay --); 8001a72: 68fb ldr r3, [r7, #12] 8001a74: 1e5a subs r2, r3, #1 8001a76: 60fa str r2, [r7, #12] 8001a78: 2b00 cmp r3, #0 8001a7a: d1f9 bne.n 8001a70 } 8001a7c: bf00 nop 8001a7e: bf00 nop 8001a80: 3714 adds r7, #20 8001a82: 46bd mov sp, r7 8001a84: bc80 pop {r7} 8001a86: 4770 bx lr 8001a88: 20000000 .word 0x20000000 8001a8c: 10624dd3 .word 0x10624dd3 08001a90 : * manually disable it. * * @retval HAL status */ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) { 8001a90: b580 push {r7, lr} 8001a92: b086 sub sp, #24 8001a94: af00 add r7, sp, #0 8001a96: 6078 str r0, [r7, #4] uint32_t tickstart = 0U, temp_reg = 0U; 8001a98: 2300 movs r3, #0 8001a9a: 613b str r3, [r7, #16] 8001a9c: 2300 movs r3, #0 8001a9e: 60fb str r3, [r7, #12] /* Check the parameters */ assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); /*------------------------------- RTC/LCD Configuration ------------------------*/ if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) 8001aa0: 687b ldr r3, [r7, #4] 8001aa2: 681b ldr r3, [r3, #0] 8001aa4: f003 0301 and.w r3, r3, #1 8001aa8: 2b00 cmp r3, #0 8001aaa: d07d beq.n 8001ba8 { FlagStatus pwrclkchanged = RESET; 8001aac: 2300 movs r3, #0 8001aae: 75fb strb r3, [r7, #23] assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); /* As soon as function is called to change RTC clock source, activation of the power domain is done. */ /* Requires to enable write access to Backup Domain of necessary */ if (__HAL_RCC_PWR_IS_CLK_DISABLED()) 8001ab0: 4b4f ldr r3, [pc, #316] ; (8001bf0 ) 8001ab2: 69db ldr r3, [r3, #28] 8001ab4: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 8001ab8: 2b00 cmp r3, #0 8001aba: d10d bne.n 8001ad8 { __HAL_RCC_PWR_CLK_ENABLE(); 8001abc: 4b4c ldr r3, [pc, #304] ; (8001bf0 ) 8001abe: 69db ldr r3, [r3, #28] 8001ac0: 4a4b ldr r2, [pc, #300] ; (8001bf0 ) 8001ac2: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 8001ac6: 61d3 str r3, [r2, #28] 8001ac8: 4b49 ldr r3, [pc, #292] ; (8001bf0 ) 8001aca: 69db ldr r3, [r3, #28] 8001acc: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 8001ad0: 60bb str r3, [r7, #8] 8001ad2: 68bb ldr r3, [r7, #8] pwrclkchanged = SET; 8001ad4: 2301 movs r3, #1 8001ad6: 75fb strb r3, [r7, #23] } if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8001ad8: 4b46 ldr r3, [pc, #280] ; (8001bf4 ) 8001ada: 681b ldr r3, [r3, #0] 8001adc: f403 7380 and.w r3, r3, #256 ; 0x100 8001ae0: 2b00 cmp r3, #0 8001ae2: d118 bne.n 8001b16 { /* Enable write access to Backup domain */ SET_BIT(PWR->CR, PWR_CR_DBP); 8001ae4: 4b43 ldr r3, [pc, #268] ; (8001bf4 ) 8001ae6: 681b ldr r3, [r3, #0] 8001ae8: 4a42 ldr r2, [pc, #264] ; (8001bf4 ) 8001aea: f443 7380 orr.w r3, r3, #256 ; 0x100 8001aee: 6013 str r3, [r2, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 8001af0: f7fe fdf8 bl 80006e4 8001af4: 6138 str r0, [r7, #16] while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8001af6: e008 b.n 8001b0a { if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 8001af8: f7fe fdf4 bl 80006e4 8001afc: 4602 mov r2, r0 8001afe: 693b ldr r3, [r7, #16] 8001b00: 1ad3 subs r3, r2, r3 8001b02: 2b64 cmp r3, #100 ; 0x64 8001b04: d901 bls.n 8001b0a { return HAL_TIMEOUT; 8001b06: 2303 movs r3, #3 8001b08: e06d b.n 8001be6 while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8001b0a: 4b3a ldr r3, [pc, #232] ; (8001bf4 ) 8001b0c: 681b ldr r3, [r3, #0] 8001b0e: f403 7380 and.w r3, r3, #256 ; 0x100 8001b12: 2b00 cmp r3, #0 8001b14: d0f0 beq.n 8001af8 } } } /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ temp_reg = (RCC->BDCR & RCC_BDCR_RTCSEL); 8001b16: 4b36 ldr r3, [pc, #216] ; (8001bf0 ) 8001b18: 6a1b ldr r3, [r3, #32] 8001b1a: f403 7340 and.w r3, r3, #768 ; 0x300 8001b1e: 60fb str r3, [r7, #12] if ((temp_reg != 0x00000000U) && (temp_reg != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))) 8001b20: 68fb ldr r3, [r7, #12] 8001b22: 2b00 cmp r3, #0 8001b24: d02e beq.n 8001b84 8001b26: 687b ldr r3, [r7, #4] 8001b28: 685b ldr r3, [r3, #4] 8001b2a: f403 7340 and.w r3, r3, #768 ; 0x300 8001b2e: 68fa ldr r2, [r7, #12] 8001b30: 429a cmp r2, r3 8001b32: d027 beq.n 8001b84 { /* Store the content of BDCR register before the reset of Backup Domain */ temp_reg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); 8001b34: 4b2e ldr r3, [pc, #184] ; (8001bf0 ) 8001b36: 6a1b ldr r3, [r3, #32] 8001b38: f423 7340 bic.w r3, r3, #768 ; 0x300 8001b3c: 60fb str r3, [r7, #12] /* RTC Clock selection can be changed only if the Backup Domain is reset */ __HAL_RCC_BACKUPRESET_FORCE(); 8001b3e: 4b2e ldr r3, [pc, #184] ; (8001bf8 ) 8001b40: 2201 movs r2, #1 8001b42: 601a str r2, [r3, #0] __HAL_RCC_BACKUPRESET_RELEASE(); 8001b44: 4b2c ldr r3, [pc, #176] ; (8001bf8 ) 8001b46: 2200 movs r2, #0 8001b48: 601a str r2, [r3, #0] /* Restore the Content of BDCR register */ RCC->BDCR = temp_reg; 8001b4a: 4a29 ldr r2, [pc, #164] ; (8001bf0 ) 8001b4c: 68fb ldr r3, [r7, #12] 8001b4e: 6213 str r3, [r2, #32] /* Wait for LSERDY if LSE was enabled */ if (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSEON)) 8001b50: 68fb ldr r3, [r7, #12] 8001b52: f003 0301 and.w r3, r3, #1 8001b56: 2b00 cmp r3, #0 8001b58: d014 beq.n 8001b84 { /* Get Start Tick */ tickstart = HAL_GetTick(); 8001b5a: f7fe fdc3 bl 80006e4 8001b5e: 6138 str r0, [r7, #16] /* Wait till LSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 8001b60: e00a b.n 8001b78 { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 8001b62: f7fe fdbf bl 80006e4 8001b66: 4602 mov r2, r0 8001b68: 693b ldr r3, [r7, #16] 8001b6a: 1ad3 subs r3, r2, r3 8001b6c: f241 3288 movw r2, #5000 ; 0x1388 8001b70: 4293 cmp r3, r2 8001b72: d901 bls.n 8001b78 { return HAL_TIMEOUT; 8001b74: 2303 movs r3, #3 8001b76: e036 b.n 8001be6 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 8001b78: 4b1d ldr r3, [pc, #116] ; (8001bf0 ) 8001b7a: 6a1b ldr r3, [r3, #32] 8001b7c: f003 0302 and.w r3, r3, #2 8001b80: 2b00 cmp r3, #0 8001b82: d0ee beq.n 8001b62 } } } } __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); 8001b84: 4b1a ldr r3, [pc, #104] ; (8001bf0 ) 8001b86: 6a1b ldr r3, [r3, #32] 8001b88: f423 7240 bic.w r2, r3, #768 ; 0x300 8001b8c: 687b ldr r3, [r7, #4] 8001b8e: 685b ldr r3, [r3, #4] 8001b90: 4917 ldr r1, [pc, #92] ; (8001bf0 ) 8001b92: 4313 orrs r3, r2 8001b94: 620b str r3, [r1, #32] /* Require to disable power clock if necessary */ if (pwrclkchanged == SET) 8001b96: 7dfb ldrb r3, [r7, #23] 8001b98: 2b01 cmp r3, #1 8001b9a: d105 bne.n 8001ba8 { __HAL_RCC_PWR_CLK_DISABLE(); 8001b9c: 4b14 ldr r3, [pc, #80] ; (8001bf0 ) 8001b9e: 69db ldr r3, [r3, #28] 8001ba0: 4a13 ldr r2, [pc, #76] ; (8001bf0 ) 8001ba2: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000 8001ba6: 61d3 str r3, [r2, #28] } } /*------------------------------ ADC clock Configuration ------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) 8001ba8: 687b ldr r3, [r7, #4] 8001baa: 681b ldr r3, [r3, #0] 8001bac: f003 0302 and.w r3, r3, #2 8001bb0: 2b00 cmp r3, #0 8001bb2: d008 beq.n 8001bc6 { /* Check the parameters */ assert_param(IS_RCC_ADCPLLCLK_DIV(PeriphClkInit->AdcClockSelection)); /* Configure the ADC clock source */ __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection); 8001bb4: 4b0e ldr r3, [pc, #56] ; (8001bf0 ) 8001bb6: 685b ldr r3, [r3, #4] 8001bb8: f423 4240 bic.w r2, r3, #49152 ; 0xc000 8001bbc: 687b ldr r3, [r7, #4] 8001bbe: 689b ldr r3, [r3, #8] 8001bc0: 490b ldr r1, [pc, #44] ; (8001bf0 ) 8001bc2: 4313 orrs r3, r2 8001bc4: 604b str r3, [r1, #4] #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\ || defined(STM32F105xC) || defined(STM32F107xC) /*------------------------------ USB clock Configuration ------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) 8001bc6: 687b ldr r3, [r7, #4] 8001bc8: 681b ldr r3, [r3, #0] 8001bca: f003 0310 and.w r3, r3, #16 8001bce: 2b00 cmp r3, #0 8001bd0: d008 beq.n 8001be4 { /* Check the parameters */ assert_param(IS_RCC_USBPLLCLK_DIV(PeriphClkInit->UsbClockSelection)); /* Configure the USB clock source */ __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection); 8001bd2: 4b07 ldr r3, [pc, #28] ; (8001bf0 ) 8001bd4: 685b ldr r3, [r3, #4] 8001bd6: f423 0280 bic.w r2, r3, #4194304 ; 0x400000 8001bda: 687b ldr r3, [r7, #4] 8001bdc: 68db ldr r3, [r3, #12] 8001bde: 4904 ldr r1, [pc, #16] ; (8001bf0 ) 8001be0: 4313 orrs r3, r2 8001be2: 604b str r3, [r1, #4] } #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ return HAL_OK; 8001be4: 2300 movs r3, #0 } 8001be6: 4618 mov r0, r3 8001be8: 3718 adds r7, #24 8001bea: 46bd mov sp, r7 8001bec: bd80 pop {r7, pc} 8001bee: bf00 nop 8001bf0: 40021000 .word 0x40021000 8001bf4: 40007000 .word 0x40007000 8001bf8: 42420440 .word 0x42420440 08001bfc : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) { 8001bfc: b580 push {r7, lr} 8001bfe: b082 sub sp, #8 8001c00: af00 add r7, sp, #0 8001c02: 6078 str r0, [r7, #4] /* Check the UART handle allocation */ if (huart == NULL) 8001c04: 687b ldr r3, [r7, #4] 8001c06: 2b00 cmp r3, #0 8001c08: d101 bne.n 8001c0e { return HAL_ERROR; 8001c0a: 2301 movs r3, #1 8001c0c: e03f b.n 8001c8e assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength)); #if defined(USART_CR1_OVER8) assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling)); #endif /* USART_CR1_OVER8 */ if (huart->gState == HAL_UART_STATE_RESET) 8001c0e: 687b ldr r3, [r7, #4] 8001c10: f893 303d ldrb.w r3, [r3, #61] ; 0x3d 8001c14: b2db uxtb r3, r3 8001c16: 2b00 cmp r3, #0 8001c18: d106 bne.n 8001c28 { /* Allocate lock resource and initialize it */ huart->Lock = HAL_UNLOCKED; 8001c1a: 687b ldr r3, [r7, #4] 8001c1c: 2200 movs r2, #0 8001c1e: f883 203c strb.w r2, [r3, #60] ; 0x3c /* Init the low level hardware */ huart->MspInitCallback(huart); #else /* Init the low level hardware : GPIO, CLOCK */ HAL_UART_MspInit(huart); 8001c22: 6878 ldr r0, [r7, #4] 8001c24: f7fe fc96 bl 8000554 #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } huart->gState = HAL_UART_STATE_BUSY; 8001c28: 687b ldr r3, [r7, #4] 8001c2a: 2224 movs r2, #36 ; 0x24 8001c2c: f883 203d strb.w r2, [r3, #61] ; 0x3d /* Disable the peripheral */ __HAL_UART_DISABLE(huart); 8001c30: 687b ldr r3, [r7, #4] 8001c32: 681b ldr r3, [r3, #0] 8001c34: 68da ldr r2, [r3, #12] 8001c36: 687b ldr r3, [r7, #4] 8001c38: 681b ldr r3, [r3, #0] 8001c3a: f422 5200 bic.w r2, r2, #8192 ; 0x2000 8001c3e: 60da str r2, [r3, #12] /* Set the UART Communication parameters */ UART_SetConfig(huart); 8001c40: 6878 ldr r0, [r7, #4] 8001c42: f000 f905 bl 8001e50 /* In asynchronous mode, the following bits must be kept cleared: - LINEN and CLKEN bits in the USART_CR2 register, - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/ CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); 8001c46: 687b ldr r3, [r7, #4] 8001c48: 681b ldr r3, [r3, #0] 8001c4a: 691a ldr r2, [r3, #16] 8001c4c: 687b ldr r3, [r7, #4] 8001c4e: 681b ldr r3, [r3, #0] 8001c50: f422 4290 bic.w r2, r2, #18432 ; 0x4800 8001c54: 611a str r2, [r3, #16] CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); 8001c56: 687b ldr r3, [r7, #4] 8001c58: 681b ldr r3, [r3, #0] 8001c5a: 695a ldr r2, [r3, #20] 8001c5c: 687b ldr r3, [r7, #4] 8001c5e: 681b ldr r3, [r3, #0] 8001c60: f022 022a bic.w r2, r2, #42 ; 0x2a 8001c64: 615a str r2, [r3, #20] /* Enable the peripheral */ __HAL_UART_ENABLE(huart); 8001c66: 687b ldr r3, [r7, #4] 8001c68: 681b ldr r3, [r3, #0] 8001c6a: 68da ldr r2, [r3, #12] 8001c6c: 687b ldr r3, [r7, #4] 8001c6e: 681b ldr r3, [r3, #0] 8001c70: f442 5200 orr.w r2, r2, #8192 ; 0x2000 8001c74: 60da str r2, [r3, #12] /* Initialize the UART state */ huart->ErrorCode = HAL_UART_ERROR_NONE; 8001c76: 687b ldr r3, [r7, #4] 8001c78: 2200 movs r2, #0 8001c7a: 641a str r2, [r3, #64] ; 0x40 huart->gState = HAL_UART_STATE_READY; 8001c7c: 687b ldr r3, [r7, #4] 8001c7e: 2220 movs r2, #32 8001c80: f883 203d strb.w r2, [r3, #61] ; 0x3d huart->RxState = HAL_UART_STATE_READY; 8001c84: 687b ldr r3, [r7, #4] 8001c86: 2220 movs r2, #32 8001c88: f883 203e strb.w r2, [r3, #62] ; 0x3e return HAL_OK; 8001c8c: 2300 movs r3, #0 } 8001c8e: 4618 mov r0, r3 8001c90: 3708 adds r7, #8 8001c92: 46bd mov sp, r7 8001c94: bd80 pop {r7, pc} 08001c96 : * @param Size Amount of data elements (u8 or u16) to be sent * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout) { 8001c96: b580 push {r7, lr} 8001c98: b08a sub sp, #40 ; 0x28 8001c9a: af02 add r7, sp, #8 8001c9c: 60f8 str r0, [r7, #12] 8001c9e: 60b9 str r1, [r7, #8] 8001ca0: 603b str r3, [r7, #0] 8001ca2: 4613 mov r3, r2 8001ca4: 80fb strh r3, [r7, #6] uint8_t *pdata8bits; uint16_t *pdata16bits; uint32_t tickstart = 0U; 8001ca6: 2300 movs r3, #0 8001ca8: 617b str r3, [r7, #20] /* Check that a Tx process is not already ongoing */ if (huart->gState == HAL_UART_STATE_READY) 8001caa: 68fb ldr r3, [r7, #12] 8001cac: f893 303d ldrb.w r3, [r3, #61] ; 0x3d 8001cb0: b2db uxtb r3, r3 8001cb2: 2b20 cmp r3, #32 8001cb4: d17c bne.n 8001db0 { if ((pData == NULL) || (Size == 0U)) 8001cb6: 68bb ldr r3, [r7, #8] 8001cb8: 2b00 cmp r3, #0 8001cba: d002 beq.n 8001cc2 8001cbc: 88fb ldrh r3, [r7, #6] 8001cbe: 2b00 cmp r3, #0 8001cc0: d101 bne.n 8001cc6 { return HAL_ERROR; 8001cc2: 2301 movs r3, #1 8001cc4: e075 b.n 8001db2 } /* Process Locked */ __HAL_LOCK(huart); 8001cc6: 68fb ldr r3, [r7, #12] 8001cc8: f893 303c ldrb.w r3, [r3, #60] ; 0x3c 8001ccc: 2b01 cmp r3, #1 8001cce: d101 bne.n 8001cd4 8001cd0: 2302 movs r3, #2 8001cd2: e06e b.n 8001db2 8001cd4: 68fb ldr r3, [r7, #12] 8001cd6: 2201 movs r2, #1 8001cd8: f883 203c strb.w r2, [r3, #60] ; 0x3c huart->ErrorCode = HAL_UART_ERROR_NONE; 8001cdc: 68fb ldr r3, [r7, #12] 8001cde: 2200 movs r2, #0 8001ce0: 641a str r2, [r3, #64] ; 0x40 huart->gState = HAL_UART_STATE_BUSY_TX; 8001ce2: 68fb ldr r3, [r7, #12] 8001ce4: 2221 movs r2, #33 ; 0x21 8001ce6: f883 203d strb.w r2, [r3, #61] ; 0x3d /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); 8001cea: f7fe fcfb bl 80006e4 8001cee: 6178 str r0, [r7, #20] huart->TxXferSize = Size; 8001cf0: 68fb ldr r3, [r7, #12] 8001cf2: 88fa ldrh r2, [r7, #6] 8001cf4: 849a strh r2, [r3, #36] ; 0x24 huart->TxXferCount = Size; 8001cf6: 68fb ldr r3, [r7, #12] 8001cf8: 88fa ldrh r2, [r7, #6] 8001cfa: 84da strh r2, [r3, #38] ; 0x26 /* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) 8001cfc: 68fb ldr r3, [r7, #12] 8001cfe: 689b ldr r3, [r3, #8] 8001d00: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 8001d04: d108 bne.n 8001d18 8001d06: 68fb ldr r3, [r7, #12] 8001d08: 691b ldr r3, [r3, #16] 8001d0a: 2b00 cmp r3, #0 8001d0c: d104 bne.n 8001d18 { pdata8bits = NULL; 8001d0e: 2300 movs r3, #0 8001d10: 61fb str r3, [r7, #28] pdata16bits = (uint16_t *) pData; 8001d12: 68bb ldr r3, [r7, #8] 8001d14: 61bb str r3, [r7, #24] 8001d16: e003 b.n 8001d20 } else { pdata8bits = pData; 8001d18: 68bb ldr r3, [r7, #8] 8001d1a: 61fb str r3, [r7, #28] pdata16bits = NULL; 8001d1c: 2300 movs r3, #0 8001d1e: 61bb str r3, [r7, #24] } /* Process Unlocked */ __HAL_UNLOCK(huart); 8001d20: 68fb ldr r3, [r7, #12] 8001d22: 2200 movs r2, #0 8001d24: f883 203c strb.w r2, [r3, #60] ; 0x3c while (huart->TxXferCount > 0U) 8001d28: e02a b.n 8001d80 { if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) 8001d2a: 683b ldr r3, [r7, #0] 8001d2c: 9300 str r3, [sp, #0] 8001d2e: 697b ldr r3, [r7, #20] 8001d30: 2200 movs r2, #0 8001d32: 2180 movs r1, #128 ; 0x80 8001d34: 68f8 ldr r0, [r7, #12] 8001d36: f000 f840 bl 8001dba 8001d3a: 4603 mov r3, r0 8001d3c: 2b00 cmp r3, #0 8001d3e: d001 beq.n 8001d44 { return HAL_TIMEOUT; 8001d40: 2303 movs r3, #3 8001d42: e036 b.n 8001db2 } if (pdata8bits == NULL) 8001d44: 69fb ldr r3, [r7, #28] 8001d46: 2b00 cmp r3, #0 8001d48: d10b bne.n 8001d62 { huart->Instance->DR = (uint16_t)(*pdata16bits & 0x01FFU); 8001d4a: 69bb ldr r3, [r7, #24] 8001d4c: 881b ldrh r3, [r3, #0] 8001d4e: 461a mov r2, r3 8001d50: 68fb ldr r3, [r7, #12] 8001d52: 681b ldr r3, [r3, #0] 8001d54: f3c2 0208 ubfx r2, r2, #0, #9 8001d58: 605a str r2, [r3, #4] pdata16bits++; 8001d5a: 69bb ldr r3, [r7, #24] 8001d5c: 3302 adds r3, #2 8001d5e: 61bb str r3, [r7, #24] 8001d60: e007 b.n 8001d72 } else { huart->Instance->DR = (uint8_t)(*pdata8bits & 0xFFU); 8001d62: 69fb ldr r3, [r7, #28] 8001d64: 781a ldrb r2, [r3, #0] 8001d66: 68fb ldr r3, [r7, #12] 8001d68: 681b ldr r3, [r3, #0] 8001d6a: 605a str r2, [r3, #4] pdata8bits++; 8001d6c: 69fb ldr r3, [r7, #28] 8001d6e: 3301 adds r3, #1 8001d70: 61fb str r3, [r7, #28] } huart->TxXferCount--; 8001d72: 68fb ldr r3, [r7, #12] 8001d74: 8cdb ldrh r3, [r3, #38] ; 0x26 8001d76: b29b uxth r3, r3 8001d78: 3b01 subs r3, #1 8001d7a: b29a uxth r2, r3 8001d7c: 68fb ldr r3, [r7, #12] 8001d7e: 84da strh r2, [r3, #38] ; 0x26 while (huart->TxXferCount > 0U) 8001d80: 68fb ldr r3, [r7, #12] 8001d82: 8cdb ldrh r3, [r3, #38] ; 0x26 8001d84: b29b uxth r3, r3 8001d86: 2b00 cmp r3, #0 8001d88: d1cf bne.n 8001d2a } if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) 8001d8a: 683b ldr r3, [r7, #0] 8001d8c: 9300 str r3, [sp, #0] 8001d8e: 697b ldr r3, [r7, #20] 8001d90: 2200 movs r2, #0 8001d92: 2140 movs r1, #64 ; 0x40 8001d94: 68f8 ldr r0, [r7, #12] 8001d96: f000 f810 bl 8001dba 8001d9a: 4603 mov r3, r0 8001d9c: 2b00 cmp r3, #0 8001d9e: d001 beq.n 8001da4 { return HAL_TIMEOUT; 8001da0: 2303 movs r3, #3 8001da2: e006 b.n 8001db2 } /* At end of Tx process, restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; 8001da4: 68fb ldr r3, [r7, #12] 8001da6: 2220 movs r2, #32 8001da8: f883 203d strb.w r2, [r3, #61] ; 0x3d return HAL_OK; 8001dac: 2300 movs r3, #0 8001dae: e000 b.n 8001db2 } else { return HAL_BUSY; 8001db0: 2302 movs r3, #2 } } 8001db2: 4618 mov r0, r3 8001db4: 3720 adds r7, #32 8001db6: 46bd mov sp, r7 8001db8: bd80 pop {r7, pc} 08001dba : * @param Tickstart Tick start value * @param Timeout Timeout duration * @retval HAL status */ static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout) { 8001dba: b580 push {r7, lr} 8001dbc: b084 sub sp, #16 8001dbe: af00 add r7, sp, #0 8001dc0: 60f8 str r0, [r7, #12] 8001dc2: 60b9 str r1, [r7, #8] 8001dc4: 603b str r3, [r7, #0] 8001dc6: 4613 mov r3, r2 8001dc8: 71fb strb r3, [r7, #7] /* Wait until flag is set */ while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) 8001dca: e02c b.n 8001e26 { /* Check for the Timeout */ if (Timeout != HAL_MAX_DELAY) 8001dcc: 69bb ldr r3, [r7, #24] 8001dce: f1b3 3fff cmp.w r3, #4294967295 8001dd2: d028 beq.n 8001e26 { if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout)) 8001dd4: 69bb ldr r3, [r7, #24] 8001dd6: 2b00 cmp r3, #0 8001dd8: d007 beq.n 8001dea 8001dda: f7fe fc83 bl 80006e4 8001dde: 4602 mov r2, r0 8001de0: 683b ldr r3, [r7, #0] 8001de2: 1ad3 subs r3, r2, r3 8001de4: 69ba ldr r2, [r7, #24] 8001de6: 429a cmp r2, r3 8001de8: d21d bcs.n 8001e26 { /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE)); 8001dea: 68fb ldr r3, [r7, #12] 8001dec: 681b ldr r3, [r3, #0] 8001dee: 68da ldr r2, [r3, #12] 8001df0: 68fb ldr r3, [r7, #12] 8001df2: 681b ldr r3, [r3, #0] 8001df4: f422 72d0 bic.w r2, r2, #416 ; 0x1a0 8001df8: 60da str r2, [r3, #12] CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 8001dfa: 68fb ldr r3, [r7, #12] 8001dfc: 681b ldr r3, [r3, #0] 8001dfe: 695a ldr r2, [r3, #20] 8001e00: 68fb ldr r3, [r7, #12] 8001e02: 681b ldr r3, [r3, #0] 8001e04: f022 0201 bic.w r2, r2, #1 8001e08: 615a str r2, [r3, #20] huart->gState = HAL_UART_STATE_READY; 8001e0a: 68fb ldr r3, [r7, #12] 8001e0c: 2220 movs r2, #32 8001e0e: f883 203d strb.w r2, [r3, #61] ; 0x3d huart->RxState = HAL_UART_STATE_READY; 8001e12: 68fb ldr r3, [r7, #12] 8001e14: 2220 movs r2, #32 8001e16: f883 203e strb.w r2, [r3, #62] ; 0x3e /* Process Unlocked */ __HAL_UNLOCK(huart); 8001e1a: 68fb ldr r3, [r7, #12] 8001e1c: 2200 movs r2, #0 8001e1e: f883 203c strb.w r2, [r3, #60] ; 0x3c return HAL_TIMEOUT; 8001e22: 2303 movs r3, #3 8001e24: e00f b.n 8001e46 while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) 8001e26: 68fb ldr r3, [r7, #12] 8001e28: 681b ldr r3, [r3, #0] 8001e2a: 681a ldr r2, [r3, #0] 8001e2c: 68bb ldr r3, [r7, #8] 8001e2e: 4013 ands r3, r2 8001e30: 68ba ldr r2, [r7, #8] 8001e32: 429a cmp r2, r3 8001e34: bf0c ite eq 8001e36: 2301 moveq r3, #1 8001e38: 2300 movne r3, #0 8001e3a: b2db uxtb r3, r3 8001e3c: 461a mov r2, r3 8001e3e: 79fb ldrb r3, [r7, #7] 8001e40: 429a cmp r2, r3 8001e42: d0c3 beq.n 8001dcc } } } return HAL_OK; 8001e44: 2300 movs r3, #0 } 8001e46: 4618 mov r0, r3 8001e48: 3710 adds r7, #16 8001e4a: 46bd mov sp, r7 8001e4c: bd80 pop {r7, pc} ... 08001e50 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ static void UART_SetConfig(UART_HandleTypeDef *huart) { 8001e50: b580 push {r7, lr} 8001e52: b084 sub sp, #16 8001e54: af00 add r7, sp, #0 8001e56: 6078 str r0, [r7, #4] assert_param(IS_UART_MODE(huart->Init.Mode)); /*-------------------------- USART CR2 Configuration -----------------------*/ /* Configure the UART Stop Bits: Set STOP[13:12] bits according to huart->Init.StopBits value */ MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits); 8001e58: 687b ldr r3, [r7, #4] 8001e5a: 681b ldr r3, [r3, #0] 8001e5c: 691b ldr r3, [r3, #16] 8001e5e: f423 5140 bic.w r1, r3, #12288 ; 0x3000 8001e62: 687b ldr r3, [r7, #4] 8001e64: 68da ldr r2, [r3, #12] 8001e66: 687b ldr r3, [r7, #4] 8001e68: 681b ldr r3, [r3, #0] 8001e6a: 430a orrs r2, r1 8001e6c: 611a str r2, [r3, #16] tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling; MODIFY_REG(huart->Instance->CR1, (uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8), tmpreg); #else tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode; 8001e6e: 687b ldr r3, [r7, #4] 8001e70: 689a ldr r2, [r3, #8] 8001e72: 687b ldr r3, [r7, #4] 8001e74: 691b ldr r3, [r3, #16] 8001e76: 431a orrs r2, r3 8001e78: 687b ldr r3, [r7, #4] 8001e7a: 695b ldr r3, [r3, #20] 8001e7c: 4313 orrs r3, r2 8001e7e: 60bb str r3, [r7, #8] MODIFY_REG(huart->Instance->CR1, 8001e80: 687b ldr r3, [r7, #4] 8001e82: 681b ldr r3, [r3, #0] 8001e84: 68db ldr r3, [r3, #12] 8001e86: f423 53b0 bic.w r3, r3, #5632 ; 0x1600 8001e8a: f023 030c bic.w r3, r3, #12 8001e8e: 687a ldr r2, [r7, #4] 8001e90: 6812 ldr r2, [r2, #0] 8001e92: 68b9 ldr r1, [r7, #8] 8001e94: 430b orrs r3, r1 8001e96: 60d3 str r3, [r2, #12] tmpreg); #endif /* USART_CR1_OVER8 */ /*-------------------------- USART CR3 Configuration -----------------------*/ /* Configure the UART HFC: Set CTSE and RTSE bits according to huart->Init.HwFlowCtl value */ MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE), huart->Init.HwFlowCtl); 8001e98: 687b ldr r3, [r7, #4] 8001e9a: 681b ldr r3, [r3, #0] 8001e9c: 695b ldr r3, [r3, #20] 8001e9e: f423 7140 bic.w r1, r3, #768 ; 0x300 8001ea2: 687b ldr r3, [r7, #4] 8001ea4: 699a ldr r2, [r3, #24] 8001ea6: 687b ldr r3, [r7, #4] 8001ea8: 681b ldr r3, [r3, #0] 8001eaa: 430a orrs r2, r1 8001eac: 615a str r2, [r3, #20] if(huart->Instance == USART1) 8001eae: 687b ldr r3, [r7, #4] 8001eb0: 681b ldr r3, [r3, #0] 8001eb2: 4a2c ldr r2, [pc, #176] ; (8001f64 ) 8001eb4: 4293 cmp r3, r2 8001eb6: d103 bne.n 8001ec0 { pclk = HAL_RCC_GetPCLK2Freq(); 8001eb8: f7ff fdb8 bl 8001a2c 8001ebc: 60f8 str r0, [r7, #12] 8001ebe: e002 b.n 8001ec6 } else { pclk = HAL_RCC_GetPCLK1Freq(); 8001ec0: f7ff fda0 bl 8001a04 8001ec4: 60f8 str r0, [r7, #12] else { huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate); } #else huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate); 8001ec6: 68fa ldr r2, [r7, #12] 8001ec8: 4613 mov r3, r2 8001eca: 009b lsls r3, r3, #2 8001ecc: 4413 add r3, r2 8001ece: 009a lsls r2, r3, #2 8001ed0: 441a add r2, r3 8001ed2: 687b ldr r3, [r7, #4] 8001ed4: 685b ldr r3, [r3, #4] 8001ed6: 009b lsls r3, r3, #2 8001ed8: fbb2 f3f3 udiv r3, r2, r3 8001edc: 4a22 ldr r2, [pc, #136] ; (8001f68 ) 8001ede: fba2 2303 umull r2, r3, r2, r3 8001ee2: 095b lsrs r3, r3, #5 8001ee4: 0119 lsls r1, r3, #4 8001ee6: 68fa ldr r2, [r7, #12] 8001ee8: 4613 mov r3, r2 8001eea: 009b lsls r3, r3, #2 8001eec: 4413 add r3, r2 8001eee: 009a lsls r2, r3, #2 8001ef0: 441a add r2, r3 8001ef2: 687b ldr r3, [r7, #4] 8001ef4: 685b ldr r3, [r3, #4] 8001ef6: 009b lsls r3, r3, #2 8001ef8: fbb2 f2f3 udiv r2, r2, r3 8001efc: 4b1a ldr r3, [pc, #104] ; (8001f68 ) 8001efe: fba3 0302 umull r0, r3, r3, r2 8001f02: 095b lsrs r3, r3, #5 8001f04: 2064 movs r0, #100 ; 0x64 8001f06: fb00 f303 mul.w r3, r0, r3 8001f0a: 1ad3 subs r3, r2, r3 8001f0c: 011b lsls r3, r3, #4 8001f0e: 3332 adds r3, #50 ; 0x32 8001f10: 4a15 ldr r2, [pc, #84] ; (8001f68 ) 8001f12: fba2 2303 umull r2, r3, r2, r3 8001f16: 095b lsrs r3, r3, #5 8001f18: f003 03f0 and.w r3, r3, #240 ; 0xf0 8001f1c: 4419 add r1, r3 8001f1e: 68fa ldr r2, [r7, #12] 8001f20: 4613 mov r3, r2 8001f22: 009b lsls r3, r3, #2 8001f24: 4413 add r3, r2 8001f26: 009a lsls r2, r3, #2 8001f28: 441a add r2, r3 8001f2a: 687b ldr r3, [r7, #4] 8001f2c: 685b ldr r3, [r3, #4] 8001f2e: 009b lsls r3, r3, #2 8001f30: fbb2 f2f3 udiv r2, r2, r3 8001f34: 4b0c ldr r3, [pc, #48] ; (8001f68 ) 8001f36: fba3 0302 umull r0, r3, r3, r2 8001f3a: 095b lsrs r3, r3, #5 8001f3c: 2064 movs r0, #100 ; 0x64 8001f3e: fb00 f303 mul.w r3, r0, r3 8001f42: 1ad3 subs r3, r2, r3 8001f44: 011b lsls r3, r3, #4 8001f46: 3332 adds r3, #50 ; 0x32 8001f48: 4a07 ldr r2, [pc, #28] ; (8001f68 ) 8001f4a: fba2 2303 umull r2, r3, r2, r3 8001f4e: 095b lsrs r3, r3, #5 8001f50: f003 020f and.w r2, r3, #15 8001f54: 687b ldr r3, [r7, #4] 8001f56: 681b ldr r3, [r3, #0] 8001f58: 440a add r2, r1 8001f5a: 609a str r2, [r3, #8] #endif /* USART_CR1_OVER8 */ } 8001f5c: bf00 nop 8001f5e: 3710 adds r7, #16 8001f60: 46bd mov sp, r7 8001f62: bd80 pop {r7, pc} 8001f64: 40013800 .word 0x40013800 8001f68: 51eb851f .word 0x51eb851f 08001f6c <__errno>: 8001f6c: 4b01 ldr r3, [pc, #4] ; (8001f74 <__errno+0x8>) 8001f6e: 6818 ldr r0, [r3, #0] 8001f70: 4770 bx lr 8001f72: bf00 nop 8001f74: 2000000c .word 0x2000000c 08001f78 <__libc_init_array>: 8001f78: b570 push {r4, r5, r6, lr} 8001f7a: 2600 movs r6, #0 8001f7c: 4d0c ldr r5, [pc, #48] ; (8001fb0 <__libc_init_array+0x38>) 8001f7e: 4c0d ldr r4, [pc, #52] ; (8001fb4 <__libc_init_array+0x3c>) 8001f80: 1b64 subs r4, r4, r5 8001f82: 10a4 asrs r4, r4, #2 8001f84: 42a6 cmp r6, r4 8001f86: d109 bne.n 8001f9c <__libc_init_array+0x24> 8001f88: f000 fc9c bl 80028c4 <_init> 8001f8c: 2600 movs r6, #0 8001f8e: 4d0a ldr r5, [pc, #40] ; (8001fb8 <__libc_init_array+0x40>) 8001f90: 4c0a ldr r4, [pc, #40] ; (8001fbc <__libc_init_array+0x44>) 8001f92: 1b64 subs r4, r4, r5 8001f94: 10a4 asrs r4, r4, #2 8001f96: 42a6 cmp r6, r4 8001f98: d105 bne.n 8001fa6 <__libc_init_array+0x2e> 8001f9a: bd70 pop {r4, r5, r6, pc} 8001f9c: f855 3b04 ldr.w r3, [r5], #4 8001fa0: 4798 blx r3 8001fa2: 3601 adds r6, #1 8001fa4: e7ee b.n 8001f84 <__libc_init_array+0xc> 8001fa6: f855 3b04 ldr.w r3, [r5], #4 8001faa: 4798 blx r3 8001fac: 3601 adds r6, #1 8001fae: e7f2 b.n 8001f96 <__libc_init_array+0x1e> 8001fb0: 08002940 .word 0x08002940 8001fb4: 08002940 .word 0x08002940 8001fb8: 08002940 .word 0x08002940 8001fbc: 08002944 .word 0x08002944 08001fc0 : 8001fc0: 4603 mov r3, r0 8001fc2: 4402 add r2, r0 8001fc4: 4293 cmp r3, r2 8001fc6: d100 bne.n 8001fca 8001fc8: 4770 bx lr 8001fca: f803 1b01 strb.w r1, [r3], #1 8001fce: e7f9 b.n 8001fc4 08001fd0 : 8001fd0: b40e push {r1, r2, r3} 8001fd2: f06f 4100 mvn.w r1, #2147483648 ; 0x80000000 8001fd6: b500 push {lr} 8001fd8: b09c sub sp, #112 ; 0x70 8001fda: ab1d add r3, sp, #116 ; 0x74 8001fdc: 9002 str r0, [sp, #8] 8001fde: 9006 str r0, [sp, #24] 8001fe0: 9107 str r1, [sp, #28] 8001fe2: 9104 str r1, [sp, #16] 8001fe4: 4808 ldr r0, [pc, #32] ; (8002008 ) 8001fe6: 4909 ldr r1, [pc, #36] ; (800200c ) 8001fe8: f853 2b04 ldr.w r2, [r3], #4 8001fec: 9105 str r1, [sp, #20] 8001fee: 6800 ldr r0, [r0, #0] 8001ff0: a902 add r1, sp, #8 8001ff2: 9301 str r3, [sp, #4] 8001ff4: f000 f868 bl 80020c8 <_svfiprintf_r> 8001ff8: 2200 movs r2, #0 8001ffa: 9b02 ldr r3, [sp, #8] 8001ffc: 701a strb r2, [r3, #0] 8001ffe: b01c add sp, #112 ; 0x70 8002000: f85d eb04 ldr.w lr, [sp], #4 8002004: b003 add sp, #12 8002006: 4770 bx lr 8002008: 2000000c .word 0x2000000c 800200c: ffff0208 .word 0xffff0208 08002010 <__ssputs_r>: 8002010: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 8002014: 688e ldr r6, [r1, #8] 8002016: 4682 mov sl, r0 8002018: 429e cmp r6, r3 800201a: 460c mov r4, r1 800201c: 4690 mov r8, r2 800201e: 461f mov r7, r3 8002020: d838 bhi.n 8002094 <__ssputs_r+0x84> 8002022: 898a ldrh r2, [r1, #12] 8002024: f412 6f90 tst.w r2, #1152 ; 0x480 8002028: d032 beq.n 8002090 <__ssputs_r+0x80> 800202a: 6825 ldr r5, [r4, #0] 800202c: 6909 ldr r1, [r1, #16] 800202e: 3301 adds r3, #1 8002030: eba5 0901 sub.w r9, r5, r1 8002034: 6965 ldr r5, [r4, #20] 8002036: 444b add r3, r9 8002038: eb05 0545 add.w r5, r5, r5, lsl #1 800203c: eb05 75d5 add.w r5, r5, r5, lsr #31 8002040: 106d asrs r5, r5, #1 8002042: 429d cmp r5, r3 8002044: bf38 it cc 8002046: 461d movcc r5, r3 8002048: 0553 lsls r3, r2, #21 800204a: d531 bpl.n 80020b0 <__ssputs_r+0xa0> 800204c: 4629 mov r1, r5 800204e: f000 fb6f bl 8002730 <_malloc_r> 8002052: 4606 mov r6, r0 8002054: b950 cbnz r0, 800206c <__ssputs_r+0x5c> 8002056: 230c movs r3, #12 8002058: f04f 30ff mov.w r0, #4294967295 800205c: f8ca 3000 str.w r3, [sl] 8002060: 89a3 ldrh r3, [r4, #12] 8002062: f043 0340 orr.w r3, r3, #64 ; 0x40 8002066: 81a3 strh r3, [r4, #12] 8002068: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 800206c: 464a mov r2, r9 800206e: 6921 ldr r1, [r4, #16] 8002070: f000 face bl 8002610 8002074: 89a3 ldrh r3, [r4, #12] 8002076: f423 6390 bic.w r3, r3, #1152 ; 0x480 800207a: f043 0380 orr.w r3, r3, #128 ; 0x80 800207e: 81a3 strh r3, [r4, #12] 8002080: 6126 str r6, [r4, #16] 8002082: 444e add r6, r9 8002084: 6026 str r6, [r4, #0] 8002086: 463e mov r6, r7 8002088: 6165 str r5, [r4, #20] 800208a: eba5 0509 sub.w r5, r5, r9 800208e: 60a5 str r5, [r4, #8] 8002090: 42be cmp r6, r7 8002092: d900 bls.n 8002096 <__ssputs_r+0x86> 8002094: 463e mov r6, r7 8002096: 4632 mov r2, r6 8002098: 4641 mov r1, r8 800209a: 6820 ldr r0, [r4, #0] 800209c: f000 fac6 bl 800262c 80020a0: 68a3 ldr r3, [r4, #8] 80020a2: 2000 movs r0, #0 80020a4: 1b9b subs r3, r3, r6 80020a6: 60a3 str r3, [r4, #8] 80020a8: 6823 ldr r3, [r4, #0] 80020aa: 4433 add r3, r6 80020ac: 6023 str r3, [r4, #0] 80020ae: e7db b.n 8002068 <__ssputs_r+0x58> 80020b0: 462a mov r2, r5 80020b2: f000 fbb1 bl 8002818 <_realloc_r> 80020b6: 4606 mov r6, r0 80020b8: 2800 cmp r0, #0 80020ba: d1e1 bne.n 8002080 <__ssputs_r+0x70> 80020bc: 4650 mov r0, sl 80020be: 6921 ldr r1, [r4, #16] 80020c0: f000 face bl 8002660 <_free_r> 80020c4: e7c7 b.n 8002056 <__ssputs_r+0x46> ... 080020c8 <_svfiprintf_r>: 80020c8: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 80020cc: 4698 mov r8, r3 80020ce: 898b ldrh r3, [r1, #12] 80020d0: 4607 mov r7, r0 80020d2: 061b lsls r3, r3, #24 80020d4: 460d mov r5, r1 80020d6: 4614 mov r4, r2 80020d8: b09d sub sp, #116 ; 0x74 80020da: d50e bpl.n 80020fa <_svfiprintf_r+0x32> 80020dc: 690b ldr r3, [r1, #16] 80020de: b963 cbnz r3, 80020fa <_svfiprintf_r+0x32> 80020e0: 2140 movs r1, #64 ; 0x40 80020e2: f000 fb25 bl 8002730 <_malloc_r> 80020e6: 6028 str r0, [r5, #0] 80020e8: 6128 str r0, [r5, #16] 80020ea: b920 cbnz r0, 80020f6 <_svfiprintf_r+0x2e> 80020ec: 230c movs r3, #12 80020ee: 603b str r3, [r7, #0] 80020f0: f04f 30ff mov.w r0, #4294967295 80020f4: e0d1 b.n 800229a <_svfiprintf_r+0x1d2> 80020f6: 2340 movs r3, #64 ; 0x40 80020f8: 616b str r3, [r5, #20] 80020fa: 2300 movs r3, #0 80020fc: 9309 str r3, [sp, #36] ; 0x24 80020fe: 2320 movs r3, #32 8002100: f88d 3029 strb.w r3, [sp, #41] ; 0x29 8002104: 2330 movs r3, #48 ; 0x30 8002106: f04f 0901 mov.w r9, #1 800210a: f8cd 800c str.w r8, [sp, #12] 800210e: f8df 81a4 ldr.w r8, [pc, #420] ; 80022b4 <_svfiprintf_r+0x1ec> 8002112: f88d 302a strb.w r3, [sp, #42] ; 0x2a 8002116: 4623 mov r3, r4 8002118: 469a mov sl, r3 800211a: f813 2b01 ldrb.w r2, [r3], #1 800211e: b10a cbz r2, 8002124 <_svfiprintf_r+0x5c> 8002120: 2a25 cmp r2, #37 ; 0x25 8002122: d1f9 bne.n 8002118 <_svfiprintf_r+0x50> 8002124: ebba 0b04 subs.w fp, sl, r4 8002128: d00b beq.n 8002142 <_svfiprintf_r+0x7a> 800212a: 465b mov r3, fp 800212c: 4622 mov r2, r4 800212e: 4629 mov r1, r5 8002130: 4638 mov r0, r7 8002132: f7ff ff6d bl 8002010 <__ssputs_r> 8002136: 3001 adds r0, #1 8002138: f000 80aa beq.w 8002290 <_svfiprintf_r+0x1c8> 800213c: 9a09 ldr r2, [sp, #36] ; 0x24 800213e: 445a add r2, fp 8002140: 9209 str r2, [sp, #36] ; 0x24 8002142: f89a 3000 ldrb.w r3, [sl] 8002146: 2b00 cmp r3, #0 8002148: f000 80a2 beq.w 8002290 <_svfiprintf_r+0x1c8> 800214c: 2300 movs r3, #0 800214e: f04f 32ff mov.w r2, #4294967295 8002152: e9cd 2305 strd r2, r3, [sp, #20] 8002156: f10a 0a01 add.w sl, sl, #1 800215a: 9304 str r3, [sp, #16] 800215c: 9307 str r3, [sp, #28] 800215e: f88d 3053 strb.w r3, [sp, #83] ; 0x53 8002162: 931a str r3, [sp, #104] ; 0x68 8002164: 4654 mov r4, sl 8002166: 2205 movs r2, #5 8002168: f814 1b01 ldrb.w r1, [r4], #1 800216c: 4851 ldr r0, [pc, #324] ; (80022b4 <_svfiprintf_r+0x1ec>) 800216e: f000 fa41 bl 80025f4 8002172: 9a04 ldr r2, [sp, #16] 8002174: b9d8 cbnz r0, 80021ae <_svfiprintf_r+0xe6> 8002176: 06d0 lsls r0, r2, #27 8002178: bf44 itt mi 800217a: 2320 movmi r3, #32 800217c: f88d 3053 strbmi.w r3, [sp, #83] ; 0x53 8002180: 0711 lsls r1, r2, #28 8002182: bf44 itt mi 8002184: 232b movmi r3, #43 ; 0x2b 8002186: f88d 3053 strbmi.w r3, [sp, #83] ; 0x53 800218a: f89a 3000 ldrb.w r3, [sl] 800218e: 2b2a cmp r3, #42 ; 0x2a 8002190: d015 beq.n 80021be <_svfiprintf_r+0xf6> 8002192: 4654 mov r4, sl 8002194: 2000 movs r0, #0 8002196: f04f 0c0a mov.w ip, #10 800219a: 9a07 ldr r2, [sp, #28] 800219c: 4621 mov r1, r4 800219e: f811 3b01 ldrb.w r3, [r1], #1 80021a2: 3b30 subs r3, #48 ; 0x30 80021a4: 2b09 cmp r3, #9 80021a6: d94e bls.n 8002246 <_svfiprintf_r+0x17e> 80021a8: b1b0 cbz r0, 80021d8 <_svfiprintf_r+0x110> 80021aa: 9207 str r2, [sp, #28] 80021ac: e014 b.n 80021d8 <_svfiprintf_r+0x110> 80021ae: eba0 0308 sub.w r3, r0, r8 80021b2: fa09 f303 lsl.w r3, r9, r3 80021b6: 4313 orrs r3, r2 80021b8: 46a2 mov sl, r4 80021ba: 9304 str r3, [sp, #16] 80021bc: e7d2 b.n 8002164 <_svfiprintf_r+0x9c> 80021be: 9b03 ldr r3, [sp, #12] 80021c0: 1d19 adds r1, r3, #4 80021c2: 681b ldr r3, [r3, #0] 80021c4: 9103 str r1, [sp, #12] 80021c6: 2b00 cmp r3, #0 80021c8: bfbb ittet lt 80021ca: 425b neglt r3, r3 80021cc: f042 0202 orrlt.w r2, r2, #2 80021d0: 9307 strge r3, [sp, #28] 80021d2: 9307 strlt r3, [sp, #28] 80021d4: bfb8 it lt 80021d6: 9204 strlt r2, [sp, #16] 80021d8: 7823 ldrb r3, [r4, #0] 80021da: 2b2e cmp r3, #46 ; 0x2e 80021dc: d10c bne.n 80021f8 <_svfiprintf_r+0x130> 80021de: 7863 ldrb r3, [r4, #1] 80021e0: 2b2a cmp r3, #42 ; 0x2a 80021e2: d135 bne.n 8002250 <_svfiprintf_r+0x188> 80021e4: 9b03 ldr r3, [sp, #12] 80021e6: 3402 adds r4, #2 80021e8: 1d1a adds r2, r3, #4 80021ea: 681b ldr r3, [r3, #0] 80021ec: 9203 str r2, [sp, #12] 80021ee: 2b00 cmp r3, #0 80021f0: bfb8 it lt 80021f2: f04f 33ff movlt.w r3, #4294967295 80021f6: 9305 str r3, [sp, #20] 80021f8: f8df a0bc ldr.w sl, [pc, #188] ; 80022b8 <_svfiprintf_r+0x1f0> 80021fc: 2203 movs r2, #3 80021fe: 4650 mov r0, sl 8002200: 7821 ldrb r1, [r4, #0] 8002202: f000 f9f7 bl 80025f4 8002206: b140 cbz r0, 800221a <_svfiprintf_r+0x152> 8002208: 2340 movs r3, #64 ; 0x40 800220a: eba0 000a sub.w r0, r0, sl 800220e: fa03 f000 lsl.w r0, r3, r0 8002212: 9b04 ldr r3, [sp, #16] 8002214: 3401 adds r4, #1 8002216: 4303 orrs r3, r0 8002218: 9304 str r3, [sp, #16] 800221a: f814 1b01 ldrb.w r1, [r4], #1 800221e: 2206 movs r2, #6 8002220: 4826 ldr r0, [pc, #152] ; (80022bc <_svfiprintf_r+0x1f4>) 8002222: f88d 1028 strb.w r1, [sp, #40] ; 0x28 8002226: f000 f9e5 bl 80025f4 800222a: 2800 cmp r0, #0 800222c: d038 beq.n 80022a0 <_svfiprintf_r+0x1d8> 800222e: 4b24 ldr r3, [pc, #144] ; (80022c0 <_svfiprintf_r+0x1f8>) 8002230: bb1b cbnz r3, 800227a <_svfiprintf_r+0x1b2> 8002232: 9b03 ldr r3, [sp, #12] 8002234: 3307 adds r3, #7 8002236: f023 0307 bic.w r3, r3, #7 800223a: 3308 adds r3, #8 800223c: 9303 str r3, [sp, #12] 800223e: 9b09 ldr r3, [sp, #36] ; 0x24 8002240: 4433 add r3, r6 8002242: 9309 str r3, [sp, #36] ; 0x24 8002244: e767 b.n 8002116 <_svfiprintf_r+0x4e> 8002246: 460c mov r4, r1 8002248: 2001 movs r0, #1 800224a: fb0c 3202 mla r2, ip, r2, r3 800224e: e7a5 b.n 800219c <_svfiprintf_r+0xd4> 8002250: 2300 movs r3, #0 8002252: f04f 0c0a mov.w ip, #10 8002256: 4619 mov r1, r3 8002258: 3401 adds r4, #1 800225a: 9305 str r3, [sp, #20] 800225c: 4620 mov r0, r4 800225e: f810 2b01 ldrb.w r2, [r0], #1 8002262: 3a30 subs r2, #48 ; 0x30 8002264: 2a09 cmp r2, #9 8002266: d903 bls.n 8002270 <_svfiprintf_r+0x1a8> 8002268: 2b00 cmp r3, #0 800226a: d0c5 beq.n 80021f8 <_svfiprintf_r+0x130> 800226c: 9105 str r1, [sp, #20] 800226e: e7c3 b.n 80021f8 <_svfiprintf_r+0x130> 8002270: 4604 mov r4, r0 8002272: 2301 movs r3, #1 8002274: fb0c 2101 mla r1, ip, r1, r2 8002278: e7f0 b.n 800225c <_svfiprintf_r+0x194> 800227a: ab03 add r3, sp, #12 800227c: 9300 str r3, [sp, #0] 800227e: 462a mov r2, r5 8002280: 4638 mov r0, r7 8002282: 4b10 ldr r3, [pc, #64] ; (80022c4 <_svfiprintf_r+0x1fc>) 8002284: a904 add r1, sp, #16 8002286: f3af 8000 nop.w 800228a: 1c42 adds r2, r0, #1 800228c: 4606 mov r6, r0 800228e: d1d6 bne.n 800223e <_svfiprintf_r+0x176> 8002290: 89ab ldrh r3, [r5, #12] 8002292: 065b lsls r3, r3, #25 8002294: f53f af2c bmi.w 80020f0 <_svfiprintf_r+0x28> 8002298: 9809 ldr r0, [sp, #36] ; 0x24 800229a: b01d add sp, #116 ; 0x74 800229c: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 80022a0: ab03 add r3, sp, #12 80022a2: 9300 str r3, [sp, #0] 80022a4: 462a mov r2, r5 80022a6: 4638 mov r0, r7 80022a8: 4b06 ldr r3, [pc, #24] ; (80022c4 <_svfiprintf_r+0x1fc>) 80022aa: a904 add r1, sp, #16 80022ac: f000 f87c bl 80023a8 <_printf_i> 80022b0: e7eb b.n 800228a <_svfiprintf_r+0x1c2> 80022b2: bf00 nop 80022b4: 0800290c .word 0x0800290c 80022b8: 08002912 .word 0x08002912 80022bc: 08002916 .word 0x08002916 80022c0: 00000000 .word 0x00000000 80022c4: 08002011 .word 0x08002011 080022c8 <_printf_common>: 80022c8: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 80022cc: 4616 mov r6, r2 80022ce: 4699 mov r9, r3 80022d0: 688a ldr r2, [r1, #8] 80022d2: 690b ldr r3, [r1, #16] 80022d4: 4607 mov r7, r0 80022d6: 4293 cmp r3, r2 80022d8: bfb8 it lt 80022da: 4613 movlt r3, r2 80022dc: 6033 str r3, [r6, #0] 80022de: f891 2043 ldrb.w r2, [r1, #67] ; 0x43 80022e2: 460c mov r4, r1 80022e4: f8dd 8020 ldr.w r8, [sp, #32] 80022e8: b10a cbz r2, 80022ee <_printf_common+0x26> 80022ea: 3301 adds r3, #1 80022ec: 6033 str r3, [r6, #0] 80022ee: 6823 ldr r3, [r4, #0] 80022f0: 0699 lsls r1, r3, #26 80022f2: bf42 ittt mi 80022f4: 6833 ldrmi r3, [r6, #0] 80022f6: 3302 addmi r3, #2 80022f8: 6033 strmi r3, [r6, #0] 80022fa: 6825 ldr r5, [r4, #0] 80022fc: f015 0506 ands.w r5, r5, #6 8002300: d106 bne.n 8002310 <_printf_common+0x48> 8002302: f104 0a19 add.w sl, r4, #25 8002306: 68e3 ldr r3, [r4, #12] 8002308: 6832 ldr r2, [r6, #0] 800230a: 1a9b subs r3, r3, r2 800230c: 42ab cmp r3, r5 800230e: dc28 bgt.n 8002362 <_printf_common+0x9a> 8002310: f894 2043 ldrb.w r2, [r4, #67] ; 0x43 8002314: 1e13 subs r3, r2, #0 8002316: 6822 ldr r2, [r4, #0] 8002318: bf18 it ne 800231a: 2301 movne r3, #1 800231c: 0692 lsls r2, r2, #26 800231e: d42d bmi.n 800237c <_printf_common+0xb4> 8002320: 4649 mov r1, r9 8002322: 4638 mov r0, r7 8002324: f104 0243 add.w r2, r4, #67 ; 0x43 8002328: 47c0 blx r8 800232a: 3001 adds r0, #1 800232c: d020 beq.n 8002370 <_printf_common+0xa8> 800232e: 6823 ldr r3, [r4, #0] 8002330: 68e5 ldr r5, [r4, #12] 8002332: f003 0306 and.w r3, r3, #6 8002336: 2b04 cmp r3, #4 8002338: bf18 it ne 800233a: 2500 movne r5, #0 800233c: 6832 ldr r2, [r6, #0] 800233e: f04f 0600 mov.w r6, #0 8002342: 68a3 ldr r3, [r4, #8] 8002344: bf08 it eq 8002346: 1aad subeq r5, r5, r2 8002348: 6922 ldr r2, [r4, #16] 800234a: bf08 it eq 800234c: ea25 75e5 biceq.w r5, r5, r5, asr #31 8002350: 4293 cmp r3, r2 8002352: bfc4 itt gt 8002354: 1a9b subgt r3, r3, r2 8002356: 18ed addgt r5, r5, r3 8002358: 341a adds r4, #26 800235a: 42b5 cmp r5, r6 800235c: d11a bne.n 8002394 <_printf_common+0xcc> 800235e: 2000 movs r0, #0 8002360: e008 b.n 8002374 <_printf_common+0xac> 8002362: 2301 movs r3, #1 8002364: 4652 mov r2, sl 8002366: 4649 mov r1, r9 8002368: 4638 mov r0, r7 800236a: 47c0 blx r8 800236c: 3001 adds r0, #1 800236e: d103 bne.n 8002378 <_printf_common+0xb0> 8002370: f04f 30ff mov.w r0, #4294967295 8002374: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 8002378: 3501 adds r5, #1 800237a: e7c4 b.n 8002306 <_printf_common+0x3e> 800237c: 2030 movs r0, #48 ; 0x30 800237e: 18e1 adds r1, r4, r3 8002380: f881 0043 strb.w r0, [r1, #67] ; 0x43 8002384: 1c5a adds r2, r3, #1 8002386: f894 1045 ldrb.w r1, [r4, #69] ; 0x45 800238a: 4422 add r2, r4 800238c: 3302 adds r3, #2 800238e: f882 1043 strb.w r1, [r2, #67] ; 0x43 8002392: e7c5 b.n 8002320 <_printf_common+0x58> 8002394: 2301 movs r3, #1 8002396: 4622 mov r2, r4 8002398: 4649 mov r1, r9 800239a: 4638 mov r0, r7 800239c: 47c0 blx r8 800239e: 3001 adds r0, #1 80023a0: d0e6 beq.n 8002370 <_printf_common+0xa8> 80023a2: 3601 adds r6, #1 80023a4: e7d9 b.n 800235a <_printf_common+0x92> ... 080023a8 <_printf_i>: 80023a8: e92d 47ff stmdb sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, lr} 80023ac: 7e0f ldrb r7, [r1, #24] 80023ae: 4691 mov r9, r2 80023b0: 2f78 cmp r7, #120 ; 0x78 80023b2: 4680 mov r8, r0 80023b4: 460c mov r4, r1 80023b6: 469a mov sl, r3 80023b8: 9d0c ldr r5, [sp, #48] ; 0x30 80023ba: f101 0243 add.w r2, r1, #67 ; 0x43 80023be: d807 bhi.n 80023d0 <_printf_i+0x28> 80023c0: 2f62 cmp r7, #98 ; 0x62 80023c2: d80a bhi.n 80023da <_printf_i+0x32> 80023c4: 2f00 cmp r7, #0 80023c6: f000 80d9 beq.w 800257c <_printf_i+0x1d4> 80023ca: 2f58 cmp r7, #88 ; 0x58 80023cc: f000 80a4 beq.w 8002518 <_printf_i+0x170> 80023d0: f104 0542 add.w r5, r4, #66 ; 0x42 80023d4: f884 7042 strb.w r7, [r4, #66] ; 0x42 80023d8: e03a b.n 8002450 <_printf_i+0xa8> 80023da: f1a7 0363 sub.w r3, r7, #99 ; 0x63 80023de: 2b15 cmp r3, #21 80023e0: d8f6 bhi.n 80023d0 <_printf_i+0x28> 80023e2: a101 add r1, pc, #4 ; (adr r1, 80023e8 <_printf_i+0x40>) 80023e4: f851 f023 ldr.w pc, [r1, r3, lsl #2] 80023e8: 08002441 .word 0x08002441 80023ec: 08002455 .word 0x08002455 80023f0: 080023d1 .word 0x080023d1 80023f4: 080023d1 .word 0x080023d1 80023f8: 080023d1 .word 0x080023d1 80023fc: 080023d1 .word 0x080023d1 8002400: 08002455 .word 0x08002455 8002404: 080023d1 .word 0x080023d1 8002408: 080023d1 .word 0x080023d1 800240c: 080023d1 .word 0x080023d1 8002410: 080023d1 .word 0x080023d1 8002414: 08002563 .word 0x08002563 8002418: 08002485 .word 0x08002485 800241c: 08002545 .word 0x08002545 8002420: 080023d1 .word 0x080023d1 8002424: 080023d1 .word 0x080023d1 8002428: 08002585 .word 0x08002585 800242c: 080023d1 .word 0x080023d1 8002430: 08002485 .word 0x08002485 8002434: 080023d1 .word 0x080023d1 8002438: 080023d1 .word 0x080023d1 800243c: 0800254d .word 0x0800254d 8002440: 682b ldr r3, [r5, #0] 8002442: 1d1a adds r2, r3, #4 8002444: 681b ldr r3, [r3, #0] 8002446: 602a str r2, [r5, #0] 8002448: f104 0542 add.w r5, r4, #66 ; 0x42 800244c: f884 3042 strb.w r3, [r4, #66] ; 0x42 8002450: 2301 movs r3, #1 8002452: e0a4 b.n 800259e <_printf_i+0x1f6> 8002454: 6820 ldr r0, [r4, #0] 8002456: 6829 ldr r1, [r5, #0] 8002458: 0606 lsls r6, r0, #24 800245a: f101 0304 add.w r3, r1, #4 800245e: d50a bpl.n 8002476 <_printf_i+0xce> 8002460: 680e ldr r6, [r1, #0] 8002462: 602b str r3, [r5, #0] 8002464: 2e00 cmp r6, #0 8002466: da03 bge.n 8002470 <_printf_i+0xc8> 8002468: 232d movs r3, #45 ; 0x2d 800246a: 4276 negs r6, r6 800246c: f884 3043 strb.w r3, [r4, #67] ; 0x43 8002470: 230a movs r3, #10 8002472: 485e ldr r0, [pc, #376] ; (80025ec <_printf_i+0x244>) 8002474: e019 b.n 80024aa <_printf_i+0x102> 8002476: 680e ldr r6, [r1, #0] 8002478: f010 0f40 tst.w r0, #64 ; 0x40 800247c: 602b str r3, [r5, #0] 800247e: bf18 it ne 8002480: b236 sxthne r6, r6 8002482: e7ef b.n 8002464 <_printf_i+0xbc> 8002484: 682b ldr r3, [r5, #0] 8002486: 6820 ldr r0, [r4, #0] 8002488: 1d19 adds r1, r3, #4 800248a: 6029 str r1, [r5, #0] 800248c: 0601 lsls r1, r0, #24 800248e: d501 bpl.n 8002494 <_printf_i+0xec> 8002490: 681e ldr r6, [r3, #0] 8002492: e002 b.n 800249a <_printf_i+0xf2> 8002494: 0646 lsls r6, r0, #25 8002496: d5fb bpl.n 8002490 <_printf_i+0xe8> 8002498: 881e ldrh r6, [r3, #0] 800249a: 2f6f cmp r7, #111 ; 0x6f 800249c: bf0c ite eq 800249e: 2308 moveq r3, #8 80024a0: 230a movne r3, #10 80024a2: 4852 ldr r0, [pc, #328] ; (80025ec <_printf_i+0x244>) 80024a4: 2100 movs r1, #0 80024a6: f884 1043 strb.w r1, [r4, #67] ; 0x43 80024aa: 6865 ldr r5, [r4, #4] 80024ac: 2d00 cmp r5, #0 80024ae: bfa8 it ge 80024b0: 6821 ldrge r1, [r4, #0] 80024b2: 60a5 str r5, [r4, #8] 80024b4: bfa4 itt ge 80024b6: f021 0104 bicge.w r1, r1, #4 80024ba: 6021 strge r1, [r4, #0] 80024bc: b90e cbnz r6, 80024c2 <_printf_i+0x11a> 80024be: 2d00 cmp r5, #0 80024c0: d04d beq.n 800255e <_printf_i+0x1b6> 80024c2: 4615 mov r5, r2 80024c4: fbb6 f1f3 udiv r1, r6, r3 80024c8: fb03 6711 mls r7, r3, r1, r6 80024cc: 5dc7 ldrb r7, [r0, r7] 80024ce: f805 7d01 strb.w r7, [r5, #-1]! 80024d2: 4637 mov r7, r6 80024d4: 42bb cmp r3, r7 80024d6: 460e mov r6, r1 80024d8: d9f4 bls.n 80024c4 <_printf_i+0x11c> 80024da: 2b08 cmp r3, #8 80024dc: d10b bne.n 80024f6 <_printf_i+0x14e> 80024de: 6823 ldr r3, [r4, #0] 80024e0: 07de lsls r6, r3, #31 80024e2: d508 bpl.n 80024f6 <_printf_i+0x14e> 80024e4: 6923 ldr r3, [r4, #16] 80024e6: 6861 ldr r1, [r4, #4] 80024e8: 4299 cmp r1, r3 80024ea: bfde ittt le 80024ec: 2330 movle r3, #48 ; 0x30 80024ee: f805 3c01 strble.w r3, [r5, #-1] 80024f2: f105 35ff addle.w r5, r5, #4294967295 80024f6: 1b52 subs r2, r2, r5 80024f8: 6122 str r2, [r4, #16] 80024fa: 464b mov r3, r9 80024fc: 4621 mov r1, r4 80024fe: 4640 mov r0, r8 8002500: f8cd a000 str.w sl, [sp] 8002504: aa03 add r2, sp, #12 8002506: f7ff fedf bl 80022c8 <_printf_common> 800250a: 3001 adds r0, #1 800250c: d14c bne.n 80025a8 <_printf_i+0x200> 800250e: f04f 30ff mov.w r0, #4294967295 8002512: b004 add sp, #16 8002514: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 8002518: 4834 ldr r0, [pc, #208] ; (80025ec <_printf_i+0x244>) 800251a: f881 7045 strb.w r7, [r1, #69] ; 0x45 800251e: 6829 ldr r1, [r5, #0] 8002520: 6823 ldr r3, [r4, #0] 8002522: f851 6b04 ldr.w r6, [r1], #4 8002526: 6029 str r1, [r5, #0] 8002528: 061d lsls r5, r3, #24 800252a: d514 bpl.n 8002556 <_printf_i+0x1ae> 800252c: 07df lsls r7, r3, #31 800252e: bf44 itt mi 8002530: f043 0320 orrmi.w r3, r3, #32 8002534: 6023 strmi r3, [r4, #0] 8002536: b91e cbnz r6, 8002540 <_printf_i+0x198> 8002538: 6823 ldr r3, [r4, #0] 800253a: f023 0320 bic.w r3, r3, #32 800253e: 6023 str r3, [r4, #0] 8002540: 2310 movs r3, #16 8002542: e7af b.n 80024a4 <_printf_i+0xfc> 8002544: 6823 ldr r3, [r4, #0] 8002546: f043 0320 orr.w r3, r3, #32 800254a: 6023 str r3, [r4, #0] 800254c: 2378 movs r3, #120 ; 0x78 800254e: 4828 ldr r0, [pc, #160] ; (80025f0 <_printf_i+0x248>) 8002550: f884 3045 strb.w r3, [r4, #69] ; 0x45 8002554: e7e3 b.n 800251e <_printf_i+0x176> 8002556: 0659 lsls r1, r3, #25 8002558: bf48 it mi 800255a: b2b6 uxthmi r6, r6 800255c: e7e6 b.n 800252c <_printf_i+0x184> 800255e: 4615 mov r5, r2 8002560: e7bb b.n 80024da <_printf_i+0x132> 8002562: 682b ldr r3, [r5, #0] 8002564: 6826 ldr r6, [r4, #0] 8002566: 1d18 adds r0, r3, #4 8002568: 6961 ldr r1, [r4, #20] 800256a: 6028 str r0, [r5, #0] 800256c: 0635 lsls r5, r6, #24 800256e: 681b ldr r3, [r3, #0] 8002570: d501 bpl.n 8002576 <_printf_i+0x1ce> 8002572: 6019 str r1, [r3, #0] 8002574: e002 b.n 800257c <_printf_i+0x1d4> 8002576: 0670 lsls r0, r6, #25 8002578: d5fb bpl.n 8002572 <_printf_i+0x1ca> 800257a: 8019 strh r1, [r3, #0] 800257c: 2300 movs r3, #0 800257e: 4615 mov r5, r2 8002580: 6123 str r3, [r4, #16] 8002582: e7ba b.n 80024fa <_printf_i+0x152> 8002584: 682b ldr r3, [r5, #0] 8002586: 2100 movs r1, #0 8002588: 1d1a adds r2, r3, #4 800258a: 602a str r2, [r5, #0] 800258c: 681d ldr r5, [r3, #0] 800258e: 6862 ldr r2, [r4, #4] 8002590: 4628 mov r0, r5 8002592: f000 f82f bl 80025f4 8002596: b108 cbz r0, 800259c <_printf_i+0x1f4> 8002598: 1b40 subs r0, r0, r5 800259a: 6060 str r0, [r4, #4] 800259c: 6863 ldr r3, [r4, #4] 800259e: 6123 str r3, [r4, #16] 80025a0: 2300 movs r3, #0 80025a2: f884 3043 strb.w r3, [r4, #67] ; 0x43 80025a6: e7a8 b.n 80024fa <_printf_i+0x152> 80025a8: 462a mov r2, r5 80025aa: 4649 mov r1, r9 80025ac: 4640 mov r0, r8 80025ae: 6923 ldr r3, [r4, #16] 80025b0: 47d0 blx sl 80025b2: 3001 adds r0, #1 80025b4: d0ab beq.n 800250e <_printf_i+0x166> 80025b6: 6823 ldr r3, [r4, #0] 80025b8: 079b lsls r3, r3, #30 80025ba: d413 bmi.n 80025e4 <_printf_i+0x23c> 80025bc: 68e0 ldr r0, [r4, #12] 80025be: 9b03 ldr r3, [sp, #12] 80025c0: 4298 cmp r0, r3 80025c2: bfb8 it lt 80025c4: 4618 movlt r0, r3 80025c6: e7a4 b.n 8002512 <_printf_i+0x16a> 80025c8: 2301 movs r3, #1 80025ca: 4632 mov r2, r6 80025cc: 4649 mov r1, r9 80025ce: 4640 mov r0, r8 80025d0: 47d0 blx sl 80025d2: 3001 adds r0, #1 80025d4: d09b beq.n 800250e <_printf_i+0x166> 80025d6: 3501 adds r5, #1 80025d8: 68e3 ldr r3, [r4, #12] 80025da: 9903 ldr r1, [sp, #12] 80025dc: 1a5b subs r3, r3, r1 80025de: 42ab cmp r3, r5 80025e0: dcf2 bgt.n 80025c8 <_printf_i+0x220> 80025e2: e7eb b.n 80025bc <_printf_i+0x214> 80025e4: 2500 movs r5, #0 80025e6: f104 0619 add.w r6, r4, #25 80025ea: e7f5 b.n 80025d8 <_printf_i+0x230> 80025ec: 0800291d .word 0x0800291d 80025f0: 0800292e .word 0x0800292e 080025f4 : 80025f4: 4603 mov r3, r0 80025f6: b510 push {r4, lr} 80025f8: b2c9 uxtb r1, r1 80025fa: 4402 add r2, r0 80025fc: 4293 cmp r3, r2 80025fe: 4618 mov r0, r3 8002600: d101 bne.n 8002606 8002602: 2000 movs r0, #0 8002604: e003 b.n 800260e 8002606: 7804 ldrb r4, [r0, #0] 8002608: 3301 adds r3, #1 800260a: 428c cmp r4, r1 800260c: d1f6 bne.n 80025fc 800260e: bd10 pop {r4, pc} 08002610 : 8002610: 440a add r2, r1 8002612: 4291 cmp r1, r2 8002614: f100 33ff add.w r3, r0, #4294967295 8002618: d100 bne.n 800261c 800261a: 4770 bx lr 800261c: b510 push {r4, lr} 800261e: f811 4b01 ldrb.w r4, [r1], #1 8002622: 4291 cmp r1, r2 8002624: f803 4f01 strb.w r4, [r3, #1]! 8002628: d1f9 bne.n 800261e 800262a: bd10 pop {r4, pc} 0800262c : 800262c: 4288 cmp r0, r1 800262e: b510 push {r4, lr} 8002630: eb01 0402 add.w r4, r1, r2 8002634: d902 bls.n 800263c 8002636: 4284 cmp r4, r0 8002638: 4623 mov r3, r4 800263a: d807 bhi.n 800264c 800263c: 1e43 subs r3, r0, #1 800263e: 42a1 cmp r1, r4 8002640: d008 beq.n 8002654 8002642: f811 2b01 ldrb.w r2, [r1], #1 8002646: f803 2f01 strb.w r2, [r3, #1]! 800264a: e7f8 b.n 800263e 800264c: 4601 mov r1, r0 800264e: 4402 add r2, r0 8002650: 428a cmp r2, r1 8002652: d100 bne.n 8002656 8002654: bd10 pop {r4, pc} 8002656: f813 4d01 ldrb.w r4, [r3, #-1]! 800265a: f802 4d01 strb.w r4, [r2, #-1]! 800265e: e7f7 b.n 8002650 08002660 <_free_r>: 8002660: b538 push {r3, r4, r5, lr} 8002662: 4605 mov r5, r0 8002664: 2900 cmp r1, #0 8002666: d040 beq.n 80026ea <_free_r+0x8a> 8002668: f851 3c04 ldr.w r3, [r1, #-4] 800266c: 1f0c subs r4, r1, #4 800266e: 2b00 cmp r3, #0 8002670: bfb8 it lt 8002672: 18e4 addlt r4, r4, r3 8002674: f000 f910 bl 8002898 <__malloc_lock> 8002678: 4a1c ldr r2, [pc, #112] ; (80026ec <_free_r+0x8c>) 800267a: 6813 ldr r3, [r2, #0] 800267c: b933 cbnz r3, 800268c <_free_r+0x2c> 800267e: 6063 str r3, [r4, #4] 8002680: 6014 str r4, [r2, #0] 8002682: 4628 mov r0, r5 8002684: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} 8002688: f000 b90c b.w 80028a4 <__malloc_unlock> 800268c: 42a3 cmp r3, r4 800268e: d908 bls.n 80026a2 <_free_r+0x42> 8002690: 6820 ldr r0, [r4, #0] 8002692: 1821 adds r1, r4, r0 8002694: 428b cmp r3, r1 8002696: bf01 itttt eq 8002698: 6819 ldreq r1, [r3, #0] 800269a: 685b ldreq r3, [r3, #4] 800269c: 1809 addeq r1, r1, r0 800269e: 6021 streq r1, [r4, #0] 80026a0: e7ed b.n 800267e <_free_r+0x1e> 80026a2: 461a mov r2, r3 80026a4: 685b ldr r3, [r3, #4] 80026a6: b10b cbz r3, 80026ac <_free_r+0x4c> 80026a8: 42a3 cmp r3, r4 80026aa: d9fa bls.n 80026a2 <_free_r+0x42> 80026ac: 6811 ldr r1, [r2, #0] 80026ae: 1850 adds r0, r2, r1 80026b0: 42a0 cmp r0, r4 80026b2: d10b bne.n 80026cc <_free_r+0x6c> 80026b4: 6820 ldr r0, [r4, #0] 80026b6: 4401 add r1, r0 80026b8: 1850 adds r0, r2, r1 80026ba: 4283 cmp r3, r0 80026bc: 6011 str r1, [r2, #0] 80026be: d1e0 bne.n 8002682 <_free_r+0x22> 80026c0: 6818 ldr r0, [r3, #0] 80026c2: 685b ldr r3, [r3, #4] 80026c4: 4401 add r1, r0 80026c6: 6011 str r1, [r2, #0] 80026c8: 6053 str r3, [r2, #4] 80026ca: e7da b.n 8002682 <_free_r+0x22> 80026cc: d902 bls.n 80026d4 <_free_r+0x74> 80026ce: 230c movs r3, #12 80026d0: 602b str r3, [r5, #0] 80026d2: e7d6 b.n 8002682 <_free_r+0x22> 80026d4: 6820 ldr r0, [r4, #0] 80026d6: 1821 adds r1, r4, r0 80026d8: 428b cmp r3, r1 80026da: bf01 itttt eq 80026dc: 6819 ldreq r1, [r3, #0] 80026de: 685b ldreq r3, [r3, #4] 80026e0: 1809 addeq r1, r1, r0 80026e2: 6021 streq r1, [r4, #0] 80026e4: 6063 str r3, [r4, #4] 80026e6: 6054 str r4, [r2, #4] 80026e8: e7cb b.n 8002682 <_free_r+0x22> 80026ea: bd38 pop {r3, r4, r5, pc} 80026ec: 20000108 .word 0x20000108 080026f0 : 80026f0: b570 push {r4, r5, r6, lr} 80026f2: 4e0e ldr r6, [pc, #56] ; (800272c ) 80026f4: 460c mov r4, r1 80026f6: 6831 ldr r1, [r6, #0] 80026f8: 4605 mov r5, r0 80026fa: b911 cbnz r1, 8002702 80026fc: f000 f8bc bl 8002878 <_sbrk_r> 8002700: 6030 str r0, [r6, #0] 8002702: 4621 mov r1, r4 8002704: 4628 mov r0, r5 8002706: f000 f8b7 bl 8002878 <_sbrk_r> 800270a: 1c43 adds r3, r0, #1 800270c: d00a beq.n 8002724 800270e: 1cc4 adds r4, r0, #3 8002710: f024 0403 bic.w r4, r4, #3 8002714: 42a0 cmp r0, r4 8002716: d007 beq.n 8002728 8002718: 1a21 subs r1, r4, r0 800271a: 4628 mov r0, r5 800271c: f000 f8ac bl 8002878 <_sbrk_r> 8002720: 3001 adds r0, #1 8002722: d101 bne.n 8002728 8002724: f04f 34ff mov.w r4, #4294967295 8002728: 4620 mov r0, r4 800272a: bd70 pop {r4, r5, r6, pc} 800272c: 2000010c .word 0x2000010c 08002730 <_malloc_r>: 8002730: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} 8002734: 1ccd adds r5, r1, #3 8002736: f025 0503 bic.w r5, r5, #3 800273a: 3508 adds r5, #8 800273c: 2d0c cmp r5, #12 800273e: bf38 it cc 8002740: 250c movcc r5, #12 8002742: 2d00 cmp r5, #0 8002744: 4607 mov r7, r0 8002746: db01 blt.n 800274c <_malloc_r+0x1c> 8002748: 42a9 cmp r1, r5 800274a: d905 bls.n 8002758 <_malloc_r+0x28> 800274c: 230c movs r3, #12 800274e: 2600 movs r6, #0 8002750: 603b str r3, [r7, #0] 8002752: 4630 mov r0, r6 8002754: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} 8002758: 4e2e ldr r6, [pc, #184] ; (8002814 <_malloc_r+0xe4>) 800275a: f000 f89d bl 8002898 <__malloc_lock> 800275e: 6833 ldr r3, [r6, #0] 8002760: 461c mov r4, r3 8002762: bb34 cbnz r4, 80027b2 <_malloc_r+0x82> 8002764: 4629 mov r1, r5 8002766: 4638 mov r0, r7 8002768: f7ff ffc2 bl 80026f0 800276c: 1c43 adds r3, r0, #1 800276e: 4604 mov r4, r0 8002770: d14d bne.n 800280e <_malloc_r+0xde> 8002772: 6834 ldr r4, [r6, #0] 8002774: 4626 mov r6, r4 8002776: 2e00 cmp r6, #0 8002778: d140 bne.n 80027fc <_malloc_r+0xcc> 800277a: 6823 ldr r3, [r4, #0] 800277c: 4631 mov r1, r6 800277e: 4638 mov r0, r7 8002780: eb04 0803 add.w r8, r4, r3 8002784: f000 f878 bl 8002878 <_sbrk_r> 8002788: 4580 cmp r8, r0 800278a: d13a bne.n 8002802 <_malloc_r+0xd2> 800278c: 6821 ldr r1, [r4, #0] 800278e: 3503 adds r5, #3 8002790: 1a6d subs r5, r5, r1 8002792: f025 0503 bic.w r5, r5, #3 8002796: 3508 adds r5, #8 8002798: 2d0c cmp r5, #12 800279a: bf38 it cc 800279c: 250c movcc r5, #12 800279e: 4638 mov r0, r7 80027a0: 4629 mov r1, r5 80027a2: f7ff ffa5 bl 80026f0 80027a6: 3001 adds r0, #1 80027a8: d02b beq.n 8002802 <_malloc_r+0xd2> 80027aa: 6823 ldr r3, [r4, #0] 80027ac: 442b add r3, r5 80027ae: 6023 str r3, [r4, #0] 80027b0: e00e b.n 80027d0 <_malloc_r+0xa0> 80027b2: 6822 ldr r2, [r4, #0] 80027b4: 1b52 subs r2, r2, r5 80027b6: d41e bmi.n 80027f6 <_malloc_r+0xc6> 80027b8: 2a0b cmp r2, #11 80027ba: d916 bls.n 80027ea <_malloc_r+0xba> 80027bc: 1961 adds r1, r4, r5 80027be: 42a3 cmp r3, r4 80027c0: 6025 str r5, [r4, #0] 80027c2: bf18 it ne 80027c4: 6059 strne r1, [r3, #4] 80027c6: 6863 ldr r3, [r4, #4] 80027c8: bf08 it eq 80027ca: 6031 streq r1, [r6, #0] 80027cc: 5162 str r2, [r4, r5] 80027ce: 604b str r3, [r1, #4] 80027d0: 4638 mov r0, r7 80027d2: f104 060b add.w r6, r4, #11 80027d6: f000 f865 bl 80028a4 <__malloc_unlock> 80027da: f026 0607 bic.w r6, r6, #7 80027de: 1d23 adds r3, r4, #4 80027e0: 1af2 subs r2, r6, r3 80027e2: d0b6 beq.n 8002752 <_malloc_r+0x22> 80027e4: 1b9b subs r3, r3, r6 80027e6: 50a3 str r3, [r4, r2] 80027e8: e7b3 b.n 8002752 <_malloc_r+0x22> 80027ea: 6862 ldr r2, [r4, #4] 80027ec: 42a3 cmp r3, r4 80027ee: bf0c ite eq 80027f0: 6032 streq r2, [r6, #0] 80027f2: 605a strne r2, [r3, #4] 80027f4: e7ec b.n 80027d0 <_malloc_r+0xa0> 80027f6: 4623 mov r3, r4 80027f8: 6864 ldr r4, [r4, #4] 80027fa: e7b2 b.n 8002762 <_malloc_r+0x32> 80027fc: 4634 mov r4, r6 80027fe: 6876 ldr r6, [r6, #4] 8002800: e7b9 b.n 8002776 <_malloc_r+0x46> 8002802: 230c movs r3, #12 8002804: 4638 mov r0, r7 8002806: 603b str r3, [r7, #0] 8002808: f000 f84c bl 80028a4 <__malloc_unlock> 800280c: e7a1 b.n 8002752 <_malloc_r+0x22> 800280e: 6025 str r5, [r4, #0] 8002810: e7de b.n 80027d0 <_malloc_r+0xa0> 8002812: bf00 nop 8002814: 20000108 .word 0x20000108 08002818 <_realloc_r>: 8002818: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} 800281c: 4680 mov r8, r0 800281e: 4614 mov r4, r2 8002820: 460e mov r6, r1 8002822: b921 cbnz r1, 800282e <_realloc_r+0x16> 8002824: 4611 mov r1, r2 8002826: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} 800282a: f7ff bf81 b.w 8002730 <_malloc_r> 800282e: b92a cbnz r2, 800283c <_realloc_r+0x24> 8002830: f7ff ff16 bl 8002660 <_free_r> 8002834: 4625 mov r5, r4 8002836: 4628 mov r0, r5 8002838: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} 800283c: f000 f838 bl 80028b0 <_malloc_usable_size_r> 8002840: 4284 cmp r4, r0 8002842: 4607 mov r7, r0 8002844: d802 bhi.n 800284c <_realloc_r+0x34> 8002846: ebb4 0f50 cmp.w r4, r0, lsr #1 800284a: d812 bhi.n 8002872 <_realloc_r+0x5a> 800284c: 4621 mov r1, r4 800284e: 4640 mov r0, r8 8002850: f7ff ff6e bl 8002730 <_malloc_r> 8002854: 4605 mov r5, r0 8002856: 2800 cmp r0, #0 8002858: d0ed beq.n 8002836 <_realloc_r+0x1e> 800285a: 42bc cmp r4, r7 800285c: 4622 mov r2, r4 800285e: 4631 mov r1, r6 8002860: bf28 it cs 8002862: 463a movcs r2, r7 8002864: f7ff fed4 bl 8002610 8002868: 4631 mov r1, r6 800286a: 4640 mov r0, r8 800286c: f7ff fef8 bl 8002660 <_free_r> 8002870: e7e1 b.n 8002836 <_realloc_r+0x1e> 8002872: 4635 mov r5, r6 8002874: e7df b.n 8002836 <_realloc_r+0x1e> ... 08002878 <_sbrk_r>: 8002878: b538 push {r3, r4, r5, lr} 800287a: 2300 movs r3, #0 800287c: 4d05 ldr r5, [pc, #20] ; (8002894 <_sbrk_r+0x1c>) 800287e: 4604 mov r4, r0 8002880: 4608 mov r0, r1 8002882: 602b str r3, [r5, #0] 8002884: f7fd fe00 bl 8000488 <_sbrk> 8002888: 1c43 adds r3, r0, #1 800288a: d102 bne.n 8002892 <_sbrk_r+0x1a> 800288c: 682b ldr r3, [r5, #0] 800288e: b103 cbz r3, 8002892 <_sbrk_r+0x1a> 8002890: 6023 str r3, [r4, #0] 8002892: bd38 pop {r3, r4, r5, pc} 8002894: 20000110 .word 0x20000110 08002898 <__malloc_lock>: 8002898: 4801 ldr r0, [pc, #4] ; (80028a0 <__malloc_lock+0x8>) 800289a: f000 b811 b.w 80028c0 <__retarget_lock_acquire_recursive> 800289e: bf00 nop 80028a0: 20000114 .word 0x20000114 080028a4 <__malloc_unlock>: 80028a4: 4801 ldr r0, [pc, #4] ; (80028ac <__malloc_unlock+0x8>) 80028a6: f000 b80c b.w 80028c2 <__retarget_lock_release_recursive> 80028aa: bf00 nop 80028ac: 20000114 .word 0x20000114 080028b0 <_malloc_usable_size_r>: 80028b0: f851 3c04 ldr.w r3, [r1, #-4] 80028b4: 1f18 subs r0, r3, #4 80028b6: 2b00 cmp r3, #0 80028b8: bfbc itt lt 80028ba: 580b ldrlt r3, [r1, r0] 80028bc: 18c0 addlt r0, r0, r3 80028be: 4770 bx lr 080028c0 <__retarget_lock_acquire_recursive>: 80028c0: 4770 bx lr 080028c2 <__retarget_lock_release_recursive>: 80028c2: 4770 bx lr 080028c4 <_init>: 80028c4: b5f8 push {r3, r4, r5, r6, r7, lr} 80028c6: bf00 nop 80028c8: bcf8 pop {r3, r4, r5, r6, r7} 80028ca: bc08 pop {r3} 80028cc: 469e mov lr, r3 80028ce: 4770 bx lr 080028d0 <_fini>: 80028d0: b5f8 push {r3, r4, r5, r6, r7, lr} 80028d2: bf00 nop 80028d4: bcf8 pop {r3, r4, r5, r6, r7} 80028d6: bc08 pop {r3} 80028d8: 469e mov lr, r3 80028da: 4770 bx lr