PWM_DRV8833.elf: file format elf32-littlearm Sections: Idx Name Size VMA LMA File off Algn 0 .isr_vector 0000010c 08000000 08000000 00010000 2**0 CONTENTS, ALLOC, LOAD, READONLY, DATA 1 .text 00001d58 0800010c 0800010c 0001010c 2**2 CONTENTS, ALLOC, LOAD, READONLY, CODE 2 .rodata 00000020 08001e64 08001e64 00011e64 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 3 .ARM.extab 00000000 08001e84 08001e84 0002000c 2**0 CONTENTS 4 .ARM 00000000 08001e84 08001e84 0002000c 2**0 CONTENTS 5 .preinit_array 00000000 08001e84 08001e84 0002000c 2**0 CONTENTS, ALLOC, LOAD, DATA 6 .init_array 00000004 08001e84 08001e84 00011e84 2**2 CONTENTS, ALLOC, LOAD, DATA 7 .fini_array 00000004 08001e88 08001e88 00011e88 2**2 CONTENTS, ALLOC, LOAD, DATA 8 .data 0000000c 20000000 08001e8c 00020000 2**2 CONTENTS, ALLOC, LOAD, DATA 9 .bss 00000068 2000000c 08001e98 0002000c 2**2 ALLOC 10 ._user_heap_stack 00000604 20000074 08001e98 00020074 2**0 ALLOC 11 .ARM.attributes 00000029 00000000 00000000 0002000c 2**0 CONTENTS, READONLY 12 .debug_info 0000799b 00000000 00000000 00020035 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 13 .debug_abbrev 0000156d 00000000 00000000 000279d0 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 14 .debug_aranges 00000958 00000000 00000000 00028f40 2**3 CONTENTS, READONLY, DEBUGGING, OCTETS 15 .debug_ranges 00000890 00000000 00000000 00029898 2**3 CONTENTS, READONLY, DEBUGGING, OCTETS 16 .debug_macro 000168cb 00000000 00000000 0002a128 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 17 .debug_line 00009f09 00000000 00000000 000409f3 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 18 .debug_str 00083dd6 00000000 00000000 0004a8fc 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 19 .comment 00000050 00000000 00000000 000ce6d2 2**0 CONTENTS, READONLY 20 .debug_frame 000025dc 00000000 00000000 000ce724 2**2 CONTENTS, READONLY, DEBUGGING, OCTETS Disassembly of section .text: 0800010c <__do_global_dtors_aux>: 800010c: b510 push {r4, lr} 800010e: 4c05 ldr r4, [pc, #20] ; (8000124 <__do_global_dtors_aux+0x18>) 8000110: 7823 ldrb r3, [r4, #0] 8000112: b933 cbnz r3, 8000122 <__do_global_dtors_aux+0x16> 8000114: 4b04 ldr r3, [pc, #16] ; (8000128 <__do_global_dtors_aux+0x1c>) 8000116: b113 cbz r3, 800011e <__do_global_dtors_aux+0x12> 8000118: 4804 ldr r0, [pc, #16] ; (800012c <__do_global_dtors_aux+0x20>) 800011a: f3af 8000 nop.w 800011e: 2301 movs r3, #1 8000120: 7023 strb r3, [r4, #0] 8000122: bd10 pop {r4, pc} 8000124: 2000000c .word 0x2000000c 8000128: 00000000 .word 0x00000000 800012c: 08001e4c .word 0x08001e4c 08000130 : 8000130: b508 push {r3, lr} 8000132: 4b03 ldr r3, [pc, #12] ; (8000140 ) 8000134: b11b cbz r3, 800013e 8000136: 4903 ldr r1, [pc, #12] ; (8000144 ) 8000138: 4803 ldr r0, [pc, #12] ; (8000148 ) 800013a: f3af 8000 nop.w 800013e: bd08 pop {r3, pc} 8000140: 00000000 .word 0x00000000 8000144: 20000010 .word 0x20000010 8000148: 08001e4c .word 0x08001e4c 0800014c : * Output * EVENT_OUT * EXTI */ void MX_GPIO_Init(void) { 800014c: b480 push {r7} 800014e: b083 sub sp, #12 8000150: af00 add r7, sp, #0 /* GPIO Ports Clock Enable */ __HAL_RCC_GPIOD_CLK_ENABLE(); 8000152: 4b0e ldr r3, [pc, #56] ; (800018c ) 8000154: 699b ldr r3, [r3, #24] 8000156: 4a0d ldr r2, [pc, #52] ; (800018c ) 8000158: f043 0320 orr.w r3, r3, #32 800015c: 6193 str r3, [r2, #24] 800015e: 4b0b ldr r3, [pc, #44] ; (800018c ) 8000160: 699b ldr r3, [r3, #24] 8000162: f003 0320 and.w r3, r3, #32 8000166: 607b str r3, [r7, #4] 8000168: 687b ldr r3, [r7, #4] __HAL_RCC_GPIOA_CLK_ENABLE(); 800016a: 4b08 ldr r3, [pc, #32] ; (800018c ) 800016c: 699b ldr r3, [r3, #24] 800016e: 4a07 ldr r2, [pc, #28] ; (800018c ) 8000170: f043 0304 orr.w r3, r3, #4 8000174: 6193 str r3, [r2, #24] 8000176: 4b05 ldr r3, [pc, #20] ; (800018c ) 8000178: 699b ldr r3, [r3, #24] 800017a: f003 0304 and.w r3, r3, #4 800017e: 603b str r3, [r7, #0] 8000180: 683b ldr r3, [r7, #0] } 8000182: bf00 nop 8000184: 370c adds r7, #12 8000186: 46bd mov sp, r7 8000188: bc80 pop {r7} 800018a: 4770 bx lr 800018c: 40021000 .word 0x40021000 08000190
: /** * @brief The application entry point. * @retval int */ int main(void) { 8000190: b580 push {r7, lr} 8000192: af00 add r7, sp, #0 /* USER CODE END 1 */ /* MCU Configuration--------------------------------------------------------*/ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ HAL_Init(); 8000194: f000 f9ae bl 80004f4 /* USER CODE BEGIN Init */ /* USER CODE END Init */ /* Configure the system clock */ SystemClock_Config(); 8000198: f000 f810 bl 80001bc /* USER CODE BEGIN SysInit */ /* USER CODE END SysInit */ /* Initialize all configured peripherals */ MX_GPIO_Init(); 800019c: f7ff ffd6 bl 800014c MX_TIM2_Init(); 80001a0: f000 f8b6 bl 8000310 /* USER CODE BEGIN 2 */ //启动PWM通道2输出（只能同时启动1个通道，两个通道对应正/反转） HAL_TIM_PWM_Start(&htim2, TIM_CHANNEL_1); 80001a4: 2100 movs r1, #0 80001a6: 4804 ldr r0, [pc, #16] ; (80001b8 ) 80001a8: f001 f8fe bl 80013a8 //配置通道2的占空比，影响电机转速（占空比过低可能导致电机无法启动） __HAL_TIM_SET_COMPARE(&htim2, TIM_CHANNEL_1, 82); 80001ac: 4b02 ldr r3, [pc, #8] ; (80001b8 ) 80001ae: 681b ldr r3, [r3, #0] 80001b0: 2252 movs r2, #82 ; 0x52 80001b2: 635a str r2, [r3, #52] ; 0x34 /* USER CODE END 2 */ /* Infinite loop */ /* USER CODE BEGIN WHILE */ while (1) { 80001b4: e7fe b.n 80001b4 80001b6: bf00 nop 80001b8: 20000028 .word 0x20000028 080001bc : /** * @brief System Clock Configuration * @retval None */ void SystemClock_Config(void) { 80001bc: b580 push {r7, lr} 80001be: b090 sub sp, #64 ; 0x40 80001c0: af00 add r7, sp, #0 RCC_OscInitTypeDef RCC_OscInitStruct = { 0 }; 80001c2: f107 0318 add.w r3, r7, #24 80001c6: 2228 movs r2, #40 ; 0x28 80001c8: 2100 movs r1, #0 80001ca: 4618 mov r0, r3 80001cc: f001 fe36 bl 8001e3c RCC_ClkInitTypeDef RCC_ClkInitStruct = { 0 }; 80001d0: 1d3b adds r3, r7, #4 80001d2: 2200 movs r2, #0 80001d4: 601a str r2, [r3, #0] 80001d6: 605a str r2, [r3, #4] 80001d8: 609a str r2, [r3, #8] 80001da: 60da str r2, [r3, #12] 80001dc: 611a str r2, [r3, #16] /** Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; 80001de: 2301 movs r3, #1 80001e0: 61bb str r3, [r7, #24] RCC_OscInitStruct.HSEState = RCC_HSE_ON; 80001e2: f44f 3380 mov.w r3, #65536 ; 0x10000 80001e6: 61fb str r3, [r7, #28] RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV1; 80001e8: 2300 movs r3, #0 80001ea: 623b str r3, [r7, #32] RCC_OscInitStruct.HSIState = RCC_HSI_ON; 80001ec: 2301 movs r3, #1 80001ee: 62bb str r3, [r7, #40] ; 0x28 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; 80001f0: 2302 movs r3, #2 80001f2: 637b str r3, [r7, #52] ; 0x34 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; 80001f4: f44f 3380 mov.w r3, #65536 ; 0x10000 80001f8: 63bb str r3, [r7, #56] ; 0x38 RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9; 80001fa: f44f 13e0 mov.w r3, #1835008 ; 0x1c0000 80001fe: 63fb str r3, [r7, #60] ; 0x3c if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { 8000200: f107 0318 add.w r3, r7, #24 8000204: 4618 mov r0, r3 8000206: f000 fc3f bl 8000a88 800020a: 4603 mov r3, r0 800020c: 2b00 cmp r3, #0 800020e: d001 beq.n 8000214 Error_Handler(); 8000210: f000 f819 bl 8000246 } /** Initializes the CPU, AHB and APB buses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK 8000214: 230f movs r3, #15 8000216: 607b str r3, [r7, #4] | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; 8000218: 2302 movs r3, #2 800021a: 60bb str r3, [r7, #8] RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; 800021c: 2300 movs r3, #0 800021e: 60fb str r3, [r7, #12] RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; 8000220: f44f 6380 mov.w r3, #1024 ; 0x400 8000224: 613b str r3, [r7, #16] RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; 8000226: 2300 movs r3, #0 8000228: 617b str r3, [r7, #20] if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) { 800022a: 1d3b adds r3, r7, #4 800022c: 2102 movs r1, #2 800022e: 4618 mov r0, r3 8000230: f000 feac bl 8000f8c 8000234: 4603 mov r3, r0 8000236: 2b00 cmp r3, #0 8000238: d001 beq.n 800023e Error_Handler(); 800023a: f000 f804 bl 8000246 } } 800023e: bf00 nop 8000240: 3740 adds r7, #64 ; 0x40 8000242: 46bd mov sp, r7 8000244: bd80 pop {r7, pc} 08000246 : /** * @brief This function is executed in case of error occurrence. * @retval None */ void Error_Handler(void) { 8000246: b480 push {r7} 8000248: af00 add r7, sp, #0 \details Disables IRQ interrupts by setting the I-bit in the CPSR. Can only be executed in Privileged modes. */ __STATIC_FORCEINLINE void __disable_irq(void) { __ASM volatile ("cpsid i" : : : "memory"); 800024a: b672 cpsid i } 800024c: bf00 nop /* USER CODE BEGIN Error_Handler_Debug */ /* User can add his own implementation to report the HAL error return state */ __disable_irq(); while (1) { 800024e: e7fe b.n 800024e 08000250 : /* USER CODE END 0 */ /** * Initializes the Global MSP. */ void HAL_MspInit(void) { 8000250: b480 push {r7} 8000252: b085 sub sp, #20 8000254: af00 add r7, sp, #0 /* USER CODE BEGIN MspInit 0 */ /* USER CODE END MspInit 0 */ __HAL_RCC_AFIO_CLK_ENABLE(); 8000256: 4b15 ldr r3, [pc, #84] ; (80002ac ) 8000258: 699b ldr r3, [r3, #24] 800025a: 4a14 ldr r2, [pc, #80] ; (80002ac ) 800025c: f043 0301 orr.w r3, r3, #1 8000260: 6193 str r3, [r2, #24] 8000262: 4b12 ldr r3, [pc, #72] ; (80002ac ) 8000264: 699b ldr r3, [r3, #24] 8000266: f003 0301 and.w r3, r3, #1 800026a: 60bb str r3, [r7, #8] 800026c: 68bb ldr r3, [r7, #8] __HAL_RCC_PWR_CLK_ENABLE(); 800026e: 4b0f ldr r3, [pc, #60] ; (80002ac ) 8000270: 69db ldr r3, [r3, #28] 8000272: 4a0e ldr r2, [pc, #56] ; (80002ac ) 8000274: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 8000278: 61d3 str r3, [r2, #28] 800027a: 4b0c ldr r3, [pc, #48] ; (80002ac ) 800027c: 69db ldr r3, [r3, #28] 800027e: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 8000282: 607b str r3, [r7, #4] 8000284: 687b ldr r3, [r7, #4] /* System interrupt init*/ /** NOJTAG: JTAG-DP Disabled and SW-DP Enabled */ __HAL_AFIO_REMAP_SWJ_NOJTAG(); 8000286: 4b0a ldr r3, [pc, #40] ; (80002b0 ) 8000288: 685b ldr r3, [r3, #4] 800028a: 60fb str r3, [r7, #12] 800028c: 68fb ldr r3, [r7, #12] 800028e: f023 63e0 bic.w r3, r3, #117440512 ; 0x7000000 8000292: 60fb str r3, [r7, #12] 8000294: 68fb ldr r3, [r7, #12] 8000296: f043 7300 orr.w r3, r3, #33554432 ; 0x2000000 800029a: 60fb str r3, [r7, #12] 800029c: 4a04 ldr r2, [pc, #16] ; (80002b0 ) 800029e: 68fb ldr r3, [r7, #12] 80002a0: 6053 str r3, [r2, #4] /* USER CODE BEGIN MspInit 1 */ /* USER CODE END MspInit 1 */ } 80002a2: bf00 nop 80002a4: 3714 adds r7, #20 80002a6: 46bd mov sp, r7 80002a8: bc80 pop {r7} 80002aa: 4770 bx lr 80002ac: 40021000 .word 0x40021000 80002b0: 40010000 .word 0x40010000 080002b4 : /******************************************************************************/ /** * @brief This function handles Non maskable interrupt. */ void NMI_Handler(void) { 80002b4: b480 push {r7} 80002b6: af00 add r7, sp, #0 /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ /* USER CODE END NonMaskableInt_IRQn 0 */ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ while (1) 80002b8: e7fe b.n 80002b8 080002ba : /** * @brief This function handles Hard fault interrupt. */ void HardFault_Handler(void) { 80002ba: b480 push {r7} 80002bc: af00 add r7, sp, #0 /* USER CODE BEGIN HardFault_IRQn 0 */ /* USER CODE END HardFault_IRQn 0 */ while (1) 80002be: e7fe b.n 80002be 080002c0 : /** * @brief This function handles Memory management fault. */ void MemManage_Handler(void) { 80002c0: b480 push {r7} 80002c2: af00 add r7, sp, #0 /* USER CODE BEGIN MemoryManagement_IRQn 0 */ /* USER CODE END MemoryManagement_IRQn 0 */ while (1) 80002c4: e7fe b.n 80002c4 080002c6 : /** * @brief This function handles Prefetch fault, memory access fault. */ void BusFault_Handler(void) { 80002c6: b480 push {r7} 80002c8: af00 add r7, sp, #0 /* USER CODE BEGIN BusFault_IRQn 0 */ /* USER CODE END BusFault_IRQn 0 */ while (1) 80002ca: e7fe b.n 80002ca 080002cc : /** * @brief This function handles Undefined instruction or illegal state. */ void UsageFault_Handler(void) { 80002cc: b480 push {r7} 80002ce: af00 add r7, sp, #0 /* USER CODE BEGIN UsageFault_IRQn 0 */ /* USER CODE END UsageFault_IRQn 0 */ while (1) 80002d0: e7fe b.n 80002d0 080002d2 : /** * @brief This function handles System service call via SWI instruction. */ void SVC_Handler(void) { 80002d2: b480 push {r7} 80002d4: af00 add r7, sp, #0 /* USER CODE END SVCall_IRQn 0 */ /* USER CODE BEGIN SVCall_IRQn 1 */ /* USER CODE END SVCall_IRQn 1 */ } 80002d6: bf00 nop 80002d8: 46bd mov sp, r7 80002da: bc80 pop {r7} 80002dc: 4770 bx lr 080002de : /** * @brief This function handles Debug monitor. */ void DebugMon_Handler(void) { 80002de: b480 push {r7} 80002e0: af00 add r7, sp, #0 /* USER CODE END DebugMonitor_IRQn 0 */ /* USER CODE BEGIN DebugMonitor_IRQn 1 */ /* USER CODE END DebugMonitor_IRQn 1 */ } 80002e2: bf00 nop 80002e4: 46bd mov sp, r7 80002e6: bc80 pop {r7} 80002e8: 4770 bx lr 080002ea : /** * @brief This function handles Pendable request for system service. */ void PendSV_Handler(void) { 80002ea: b480 push {r7} 80002ec: af00 add r7, sp, #0 /* USER CODE END PendSV_IRQn 0 */ /* USER CODE BEGIN PendSV_IRQn 1 */ /* USER CODE END PendSV_IRQn 1 */ } 80002ee: bf00 nop 80002f0: 46bd mov sp, r7 80002f2: bc80 pop {r7} 80002f4: 4770 bx lr 080002f6 : /** * @brief This function handles System tick timer. */ void SysTick_Handler(void) { 80002f6: b580 push {r7, lr} 80002f8: af00 add r7, sp, #0 /* USER CODE BEGIN SysTick_IRQn 0 */ /* USER CODE END SysTick_IRQn 0 */ HAL_IncTick(); 80002fa: f000 f941 bl 8000580 /* USER CODE BEGIN SysTick_IRQn 1 */ /* USER CODE END SysTick_IRQn 1 */ } 80002fe: bf00 nop 8000300: bd80 pop {r7, pc} 08000302 : * @note This function should be used only after reset. * @param None * @retval None */ void SystemInit (void) { 8000302: b480 push {r7} 8000304: af00 add r7, sp, #0 /* Configure the Vector Table location -------------------------------------*/ #if defined(USER_VECT_TAB_ADDRESS) SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ #endif /* USER_VECT_TAB_ADDRESS */ } 8000306: bf00 nop 8000308: 46bd mov sp, r7 800030a: bc80 pop {r7} 800030c: 4770 bx lr ... 08000310 : TIM_HandleTypeDef htim2; /* TIM2 init function */ void MX_TIM2_Init(void) { 8000310: b580 push {r7, lr} 8000312: b08e sub sp, #56 ; 0x38 8000314: af00 add r7, sp, #0 /* USER CODE BEGIN TIM2_Init 0 */ /* USER CODE END TIM2_Init 0 */ TIM_ClockConfigTypeDef sClockSourceConfig = {0}; 8000316: f107 0328 add.w r3, r7, #40 ; 0x28 800031a: 2200 movs r2, #0 800031c: 601a str r2, [r3, #0] 800031e: 605a str r2, [r3, #4] 8000320: 609a str r2, [r3, #8] 8000322: 60da str r2, [r3, #12] TIM_MasterConfigTypeDef sMasterConfig = {0}; 8000324: f107 0320 add.w r3, r7, #32 8000328: 2200 movs r2, #0 800032a: 601a str r2, [r3, #0] 800032c: 605a str r2, [r3, #4] TIM_OC_InitTypeDef sConfigOC = {0}; 800032e: 1d3b adds r3, r7, #4 8000330: 2200 movs r2, #0 8000332: 601a str r2, [r3, #0] 8000334: 605a str r2, [r3, #4] 8000336: 609a str r2, [r3, #8] 8000338: 60da str r2, [r3, #12] 800033a: 611a str r2, [r3, #16] 800033c: 615a str r2, [r3, #20] 800033e: 619a str r2, [r3, #24] /* USER CODE BEGIN TIM2_Init 1 */ /* USER CODE END TIM2_Init 1 */ htim2.Instance = TIM2; 8000340: 4b32 ldr r3, [pc, #200] ; (800040c ) 8000342: f04f 4280 mov.w r2, #1073741824 ; 0x40000000 8000346: 601a str r2, [r3, #0] htim2.Init.Prescaler = 72-1; 8000348: 4b30 ldr r3, [pc, #192] ; (800040c ) 800034a: 2247 movs r2, #71 ; 0x47 800034c: 605a str r2, [r3, #4] htim2.Init.CounterMode = TIM_COUNTERMODE_UP; 800034e: 4b2f ldr r3, [pc, #188] ; (800040c ) 8000350: 2200 movs r2, #0 8000352: 609a str r2, [r3, #8] htim2.Init.Period = 100-1; 8000354: 4b2d ldr r3, [pc, #180] ; (800040c ) 8000356: 2263 movs r2, #99 ; 0x63 8000358: 60da str r2, [r3, #12] htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 800035a: 4b2c ldr r3, [pc, #176] ; (800040c ) 800035c: 2200 movs r2, #0 800035e: 611a str r2, [r3, #16] htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 8000360: 4b2a ldr r3, [pc, #168] ; (800040c ) 8000362: 2200 movs r2, #0 8000364: 619a str r2, [r3, #24] if (HAL_TIM_Base_Init(&htim2) != HAL_OK) 8000366: 4829 ldr r0, [pc, #164] ; (800040c ) 8000368: f000 ff76 bl 8001258 800036c: 4603 mov r3, r0 800036e: 2b00 cmp r3, #0 8000370: d001 beq.n 8000376 { Error_Handler(); 8000372: f7ff ff68 bl 8000246 } sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; 8000376: f44f 5380 mov.w r3, #4096 ; 0x1000 800037a: 62bb str r3, [r7, #40] ; 0x28 if (HAL_TIM_ConfigClockSource(&htim2, &sClockSourceConfig) != HAL_OK) 800037c: f107 0328 add.w r3, r7, #40 ; 0x28 8000380: 4619 mov r1, r3 8000382: 4822 ldr r0, [pc, #136] ; (800040c ) 8000384: f001 f970 bl 8001668 8000388: 4603 mov r3, r0 800038a: 2b00 cmp r3, #0 800038c: d001 beq.n 8000392 { Error_Handler(); 800038e: f7ff ff5a bl 8000246 } if (HAL_TIM_PWM_Init(&htim2) != HAL_OK) 8000392: 481e ldr r0, [pc, #120] ; (800040c ) 8000394: f000 ffaf bl 80012f6 8000398: 4603 mov r3, r0 800039a: 2b00 cmp r3, #0 800039c: d001 beq.n 80003a2 { Error_Handler(); 800039e: f7ff ff52 bl 8000246 } sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; 80003a2: 2300 movs r3, #0 80003a4: 623b str r3, [r7, #32] sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 80003a6: 2300 movs r3, #0 80003a8: 627b str r3, [r7, #36] ; 0x24 if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK) 80003aa: f107 0320 add.w r3, r7, #32 80003ae: 4619 mov r1, r3 80003b0: 4816 ldr r0, [pc, #88] ; (800040c ) 80003b2: f001 fcc1 bl 8001d38 80003b6: 4603 mov r3, r0 80003b8: 2b00 cmp r3, #0 80003ba: d001 beq.n 80003c0 { Error_Handler(); 80003bc: f7ff ff43 bl 8000246 } sConfigOC.OCMode = TIM_OCMODE_PWM1; 80003c0: 2360 movs r3, #96 ; 0x60 80003c2: 607b str r3, [r7, #4] sConfigOC.Pulse = 0; 80003c4: 2300 movs r3, #0 80003c6: 60bb str r3, [r7, #8] sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; 80003c8: 2300 movs r3, #0 80003ca: 60fb str r3, [r7, #12] sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; 80003cc: 2300 movs r3, #0 80003ce: 617b str r3, [r7, #20] if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_1) != HAL_OK) 80003d0: 1d3b adds r3, r7, #4 80003d2: 2200 movs r2, #0 80003d4: 4619 mov r1, r3 80003d6: 480d ldr r0, [pc, #52] ; (800040c ) 80003d8: f001 f888 bl 80014ec 80003dc: 4603 mov r3, r0 80003de: 2b00 cmp r3, #0 80003e0: d001 beq.n 80003e6 { Error_Handler(); 80003e2: f7ff ff30 bl 8000246 } if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_2) != HAL_OK) 80003e6: 1d3b adds r3, r7, #4 80003e8: 2204 movs r2, #4 80003ea: 4619 mov r1, r3 80003ec: 4807 ldr r0, [pc, #28] ; (800040c ) 80003ee: f001 f87d bl 80014ec 80003f2: 4603 mov r3, r0 80003f4: 2b00 cmp r3, #0 80003f6: d001 beq.n 80003fc { Error_Handler(); 80003f8: f7ff ff25 bl 8000246 } /* USER CODE BEGIN TIM2_Init 2 */ /* USER CODE END TIM2_Init 2 */ HAL_TIM_MspPostInit(&htim2); 80003fc: 4803 ldr r0, [pc, #12] ; (800040c ) 80003fe: f000 f823 bl 8000448 } 8000402: bf00 nop 8000404: 3738 adds r7, #56 ; 0x38 8000406: 46bd mov sp, r7 8000408: bd80 pop {r7, pc} 800040a: bf00 nop 800040c: 20000028 .word 0x20000028 08000410 : void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* tim_baseHandle) { 8000410: b480 push {r7} 8000412: b085 sub sp, #20 8000414: af00 add r7, sp, #0 8000416: 6078 str r0, [r7, #4] if(tim_baseHandle->Instance==TIM2) 8000418: 687b ldr r3, [r7, #4] 800041a: 681b ldr r3, [r3, #0] 800041c: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000 8000420: d10b bne.n 800043a { /* USER CODE BEGIN TIM2_MspInit 0 */ /* USER CODE END TIM2_MspInit 0 */ /* TIM2 clock enable */ __HAL_RCC_TIM2_CLK_ENABLE(); 8000422: 4b08 ldr r3, [pc, #32] ; (8000444 ) 8000424: 69db ldr r3, [r3, #28] 8000426: 4a07 ldr r2, [pc, #28] ; (8000444 ) 8000428: f043 0301 orr.w r3, r3, #1 800042c: 61d3 str r3, [r2, #28] 800042e: 4b05 ldr r3, [pc, #20] ; (8000444 ) 8000430: 69db ldr r3, [r3, #28] 8000432: f003 0301 and.w r3, r3, #1 8000436: 60fb str r3, [r7, #12] 8000438: 68fb ldr r3, [r7, #12] /* USER CODE BEGIN TIM2_MspInit 1 */ /* USER CODE END TIM2_MspInit 1 */ } } 800043a: bf00 nop 800043c: 3714 adds r7, #20 800043e: 46bd mov sp, r7 8000440: bc80 pop {r7} 8000442: 4770 bx lr 8000444: 40021000 .word 0x40021000 08000448 : void HAL_TIM_MspPostInit(TIM_HandleTypeDef* timHandle) { 8000448: b580 push {r7, lr} 800044a: b088 sub sp, #32 800044c: af00 add r7, sp, #0 800044e: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8000450: f107 0310 add.w r3, r7, #16 8000454: 2200 movs r2, #0 8000456: 601a str r2, [r3, #0] 8000458: 605a str r2, [r3, #4] 800045a: 609a str r2, [r3, #8] 800045c: 60da str r2, [r3, #12] if(timHandle->Instance==TIM2) 800045e: 687b ldr r3, [r7, #4] 8000460: 681b ldr r3, [r3, #0] 8000462: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000 8000466: d117 bne.n 8000498 { /* USER CODE BEGIN TIM2_MspPostInit 0 */ /* USER CODE END TIM2_MspPostInit 0 */ __HAL_RCC_GPIOA_CLK_ENABLE(); 8000468: 4b0d ldr r3, [pc, #52] ; (80004a0 ) 800046a: 699b ldr r3, [r3, #24] 800046c: 4a0c ldr r2, [pc, #48] ; (80004a0 ) 800046e: f043 0304 orr.w r3, r3, #4 8000472: 6193 str r3, [r2, #24] 8000474: 4b0a ldr r3, [pc, #40] ; (80004a0 ) 8000476: 699b ldr r3, [r3, #24] 8000478: f003 0304 and.w r3, r3, #4 800047c: 60fb str r3, [r7, #12] 800047e: 68fb ldr r3, [r7, #12] /**TIM2 GPIO Configuration PA0-WKUP ------> TIM2_CH1 PA1 ------> TIM2_CH2 */ GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1; 8000480: 2303 movs r3, #3 8000482: 613b str r3, [r7, #16] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8000484: 2302 movs r3, #2 8000486: 617b str r3, [r7, #20] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8000488: 2302 movs r3, #2 800048a: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 800048c: f107 0310 add.w r3, r7, #16 8000490: 4619 mov r1, r3 8000492: 4804 ldr r0, [pc, #16] ; (80004a4 ) 8000494: f000 f974 bl 8000780 /* USER CODE BEGIN TIM2_MspPostInit 1 */ /* USER CODE END TIM2_MspPostInit 1 */ } } 8000498: bf00 nop 800049a: 3720 adds r7, #32 800049c: 46bd mov sp, r7 800049e: bd80 pop {r7, pc} 80004a0: 40021000 .word 0x40021000 80004a4: 40010800 .word 0x40010800 080004a8 : .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata 80004a8: 480c ldr r0, [pc, #48] ; (80004dc ) ldr r1, =_edata 80004aa: 490d ldr r1, [pc, #52] ; (80004e0 ) ldr r2, =_sidata 80004ac: 4a0d ldr r2, [pc, #52] ; (80004e4 ) movs r3, #0 80004ae: 2300 movs r3, #0 b LoopCopyDataInit 80004b0: e002 b.n 80004b8 080004b2 : CopyDataInit: ldr r4, [r2, r3] 80004b2: 58d4 ldr r4, [r2, r3] str r4, [r0, r3] 80004b4: 50c4 str r4, [r0, r3] adds r3, r3, #4 80004b6: 3304 adds r3, #4 080004b8 : LoopCopyDataInit: adds r4, r0, r3 80004b8: 18c4 adds r4, r0, r3 cmp r4, r1 80004ba: 428c cmp r4, r1 bcc CopyDataInit 80004bc: d3f9 bcc.n 80004b2 /* Zero fill the bss segment. */ ldr r2, =_sbss 80004be: 4a0a ldr r2, [pc, #40] ; (80004e8 ) ldr r4, =_ebss 80004c0: 4c0a ldr r4, [pc, #40] ; (80004ec ) movs r3, #0 80004c2: 2300 movs r3, #0 b LoopFillZerobss 80004c4: e001 b.n 80004ca 080004c6 : FillZerobss: str r3, [r2] 80004c6: 6013 str r3, [r2, #0] adds r2, r2, #4 80004c8: 3204 adds r2, #4 080004ca : LoopFillZerobss: cmp r2, r4 80004ca: 42a2 cmp r2, r4 bcc FillZerobss 80004cc: d3fb bcc.n 80004c6 /* Call the clock system intitialization function.*/ bl SystemInit 80004ce: f7ff ff18 bl 8000302 /* Call static constructors */ bl __libc_init_array 80004d2: f001 fc8f bl 8001df4 <__libc_init_array> /* Call the application's entry point.*/ bl main 80004d6: f7ff fe5b bl 8000190
bx lr 80004da: 4770 bx lr ldr r0, =_sdata 80004dc: 20000000 .word 0x20000000 ldr r1, =_edata 80004e0: 2000000c .word 0x2000000c ldr r2, =_sidata 80004e4: 08001e8c .word 0x08001e8c ldr r2, =_sbss 80004e8: 2000000c .word 0x2000000c ldr r4, =_ebss 80004ec: 20000074 .word 0x20000074 080004f0 : * @retval : None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop 80004f0: e7fe b.n 80004f0 ... 080004f4 : * need to ensure that the SysTick time base is always set to 1 millisecond * to have correct HAL operation. * @retval HAL status */ HAL_StatusTypeDef HAL_Init(void) { 80004f4: b580 push {r7, lr} 80004f6: af00 add r7, sp, #0 defined(STM32F102x6) || defined(STM32F102xB) || \ defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || \ defined(STM32F105xC) || defined(STM32F107xC) /* Prefetch buffer is not available on value line devices */ __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); 80004f8: 4b08 ldr r3, [pc, #32] ; (800051c ) 80004fa: 681b ldr r3, [r3, #0] 80004fc: 4a07 ldr r2, [pc, #28] ; (800051c ) 80004fe: f043 0310 orr.w r3, r3, #16 8000502: 6013 str r3, [r2, #0] #endif #endif /* PREFETCH_ENABLE */ /* Set Interrupt Group Priority */ HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); 8000504: 2003 movs r0, #3 8000506: f000 f907 bl 8000718 /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ HAL_InitTick(TICK_INT_PRIORITY); 800050a: 200f movs r0, #15 800050c: f000 f808 bl 8000520 /* Init the low level hardware */ HAL_MspInit(); 8000510: f7ff fe9e bl 8000250 /* Return function status */ return HAL_OK; 8000514: 2300 movs r3, #0 } 8000516: 4618 mov r0, r3 8000518: bd80 pop {r7, pc} 800051a: bf00 nop 800051c: 40022000 .word 0x40022000 08000520 : * implementation in user file. * @param TickPriority Tick interrupt priority. * @retval HAL status */ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { 8000520: b580 push {r7, lr} 8000522: b082 sub sp, #8 8000524: af00 add r7, sp, #0 8000526: 6078 str r0, [r7, #4] /* Configure the SysTick to have interrupt in 1ms time basis*/ if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U) 8000528: 4b12 ldr r3, [pc, #72] ; (8000574 ) 800052a: 681a ldr r2, [r3, #0] 800052c: 4b12 ldr r3, [pc, #72] ; (8000578 ) 800052e: 781b ldrb r3, [r3, #0] 8000530: 4619 mov r1, r3 8000532: f44f 737a mov.w r3, #1000 ; 0x3e8 8000536: fbb3 f3f1 udiv r3, r3, r1 800053a: fbb2 f3f3 udiv r3, r2, r3 800053e: 4618 mov r0, r3 8000540: f000 f911 bl 8000766 8000544: 4603 mov r3, r0 8000546: 2b00 cmp r3, #0 8000548: d001 beq.n 800054e { return HAL_ERROR; 800054a: 2301 movs r3, #1 800054c: e00e b.n 800056c } /* Configure the SysTick IRQ priority */ if (TickPriority < (1UL << __NVIC_PRIO_BITS)) 800054e: 687b ldr r3, [r7, #4] 8000550: 2b0f cmp r3, #15 8000552: d80a bhi.n 800056a { HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); 8000554: 2200 movs r2, #0 8000556: 6879 ldr r1, [r7, #4] 8000558: f04f 30ff mov.w r0, #4294967295 800055c: f000 f8e7 bl 800072e uwTickPrio = TickPriority; 8000560: 4a06 ldr r2, [pc, #24] ; (800057c ) 8000562: 687b ldr r3, [r7, #4] 8000564: 6013 str r3, [r2, #0] { return HAL_ERROR; } /* Return function status */ return HAL_OK; 8000566: 2300 movs r3, #0 8000568: e000 b.n 800056c return HAL_ERROR; 800056a: 2301 movs r3, #1 } 800056c: 4618 mov r0, r3 800056e: 3708 adds r7, #8 8000570: 46bd mov sp, r7 8000572: bd80 pop {r7, pc} 8000574: 20000000 .word 0x20000000 8000578: 20000008 .word 0x20000008 800057c: 20000004 .word 0x20000004 08000580 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ __weak void HAL_IncTick(void) { 8000580: b480 push {r7} 8000582: af00 add r7, sp, #0 uwTick += uwTickFreq; 8000584: 4b05 ldr r3, [pc, #20] ; (800059c ) 8000586: 781b ldrb r3, [r3, #0] 8000588: 461a mov r2, r3 800058a: 4b05 ldr r3, [pc, #20] ; (80005a0 ) 800058c: 681b ldr r3, [r3, #0] 800058e: 4413 add r3, r2 8000590: 4a03 ldr r2, [pc, #12] ; (80005a0 ) 8000592: 6013 str r3, [r2, #0] } 8000594: bf00 nop 8000596: 46bd mov sp, r7 8000598: bc80 pop {r7} 800059a: 4770 bx lr 800059c: 20000008 .word 0x20000008 80005a0: 20000070 .word 0x20000070 080005a4 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval tick value */ __weak uint32_t HAL_GetTick(void) { 80005a4: b480 push {r7} 80005a6: af00 add r7, sp, #0 return uwTick; 80005a8: 4b02 ldr r3, [pc, #8] ; (80005b4 ) 80005aa: 681b ldr r3, [r3, #0] } 80005ac: 4618 mov r0, r3 80005ae: 46bd mov sp, r7 80005b0: bc80 pop {r7} 80005b2: 4770 bx lr 80005b4: 20000070 .word 0x20000070 080005b8 <__NVIC_SetPriorityGrouping>: In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 80005b8: b480 push {r7} 80005ba: b085 sub sp, #20 80005bc: af00 add r7, sp, #0 80005be: 6078 str r0, [r7, #4] uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 80005c0: 687b ldr r3, [r7, #4] 80005c2: f003 0307 and.w r3, r3, #7 80005c6: 60fb str r3, [r7, #12] reg_value = SCB->AIRCR; /* read old register configuration */ 80005c8: 4b0c ldr r3, [pc, #48] ; (80005fc <__NVIC_SetPriorityGrouping+0x44>) 80005ca: 68db ldr r3, [r3, #12] 80005cc: 60bb str r3, [r7, #8] reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ 80005ce: 68ba ldr r2, [r7, #8] 80005d0: f64f 03ff movw r3, #63743 ; 0xf8ff 80005d4: 4013 ands r3, r2 80005d6: 60bb str r3, [r7, #8] reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ 80005d8: 68fb ldr r3, [r7, #12] 80005da: 021a lsls r2, r3, #8 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 80005dc: 68bb ldr r3, [r7, #8] 80005de: 4313 orrs r3, r2 reg_value = (reg_value | 80005e0: f043 63bf orr.w r3, r3, #100139008 ; 0x5f80000 80005e4: f443 3300 orr.w r3, r3, #131072 ; 0x20000 80005e8: 60bb str r3, [r7, #8] SCB->AIRCR = reg_value; 80005ea: 4a04 ldr r2, [pc, #16] ; (80005fc <__NVIC_SetPriorityGrouping+0x44>) 80005ec: 68bb ldr r3, [r7, #8] 80005ee: 60d3 str r3, [r2, #12] } 80005f0: bf00 nop 80005f2: 3714 adds r7, #20 80005f4: 46bd mov sp, r7 80005f6: bc80 pop {r7} 80005f8: 4770 bx lr 80005fa: bf00 nop 80005fc: e000ed00 .word 0xe000ed00 08000600 <__NVIC_GetPriorityGrouping>: \brief Get Priority Grouping \details Reads the priority grouping field from the NVIC Interrupt Controller. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) { 8000600: b480 push {r7} 8000602: af00 add r7, sp, #0 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); 8000604: 4b04 ldr r3, [pc, #16] ; (8000618 <__NVIC_GetPriorityGrouping+0x18>) 8000606: 68db ldr r3, [r3, #12] 8000608: 0a1b lsrs r3, r3, #8 800060a: f003 0307 and.w r3, r3, #7 } 800060e: 4618 mov r0, r3 8000610: 46bd mov sp, r7 8000612: bc80 pop {r7} 8000614: 4770 bx lr 8000616: bf00 nop 8000618: e000ed00 .word 0xe000ed00 0800061c <__NVIC_SetPriority>: \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { 800061c: b480 push {r7} 800061e: b083 sub sp, #12 8000620: af00 add r7, sp, #0 8000622: 4603 mov r3, r0 8000624: 6039 str r1, [r7, #0] 8000626: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) 8000628: f997 3007 ldrsb.w r3, [r7, #7] 800062c: 2b00 cmp r3, #0 800062e: db0a blt.n 8000646 <__NVIC_SetPriority+0x2a> { NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 8000630: 683b ldr r3, [r7, #0] 8000632: b2da uxtb r2, r3 8000634: 490c ldr r1, [pc, #48] ; (8000668 <__NVIC_SetPriority+0x4c>) 8000636: f997 3007 ldrsb.w r3, [r7, #7] 800063a: 0112 lsls r2, r2, #4 800063c: b2d2 uxtb r2, r2 800063e: 440b add r3, r1 8000640: f883 2300 strb.w r2, [r3, #768] ; 0x300 } else { SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } 8000644: e00a b.n 800065c <__NVIC_SetPriority+0x40> SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 8000646: 683b ldr r3, [r7, #0] 8000648: b2da uxtb r2, r3 800064a: 4908 ldr r1, [pc, #32] ; (800066c <__NVIC_SetPriority+0x50>) 800064c: 79fb ldrb r3, [r7, #7] 800064e: f003 030f and.w r3, r3, #15 8000652: 3b04 subs r3, #4 8000654: 0112 lsls r2, r2, #4 8000656: b2d2 uxtb r2, r2 8000658: 440b add r3, r1 800065a: 761a strb r2, [r3, #24] } 800065c: bf00 nop 800065e: 370c adds r7, #12 8000660: 46bd mov sp, r7 8000662: bc80 pop {r7} 8000664: 4770 bx lr 8000666: bf00 nop 8000668: e000e100 .word 0xe000e100 800066c: e000ed00 .word 0xe000ed00 08000670 : \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { 8000670: b480 push {r7} 8000672: b089 sub sp, #36 ; 0x24 8000674: af00 add r7, sp, #0 8000676: 60f8 str r0, [r7, #12] 8000678: 60b9 str r1, [r7, #8] 800067a: 607a str r2, [r7, #4] uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 800067c: 68fb ldr r3, [r7, #12] 800067e: f003 0307 and.w r3, r3, #7 8000682: 61fb str r3, [r7, #28] uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 8000684: 69fb ldr r3, [r7, #28] 8000686: f1c3 0307 rsb r3, r3, #7 800068a: 2b04 cmp r3, #4 800068c: bf28 it cs 800068e: 2304 movcs r3, #4 8000690: 61bb str r3, [r7, #24] SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 8000692: 69fb ldr r3, [r7, #28] 8000694: 3304 adds r3, #4 8000696: 2b06 cmp r3, #6 8000698: d902 bls.n 80006a0 800069a: 69fb ldr r3, [r7, #28] 800069c: 3b03 subs r3, #3 800069e: e000 b.n 80006a2 80006a0: 2300 movs r3, #0 80006a2: 617b str r3, [r7, #20] return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 80006a4: f04f 32ff mov.w r2, #4294967295 80006a8: 69bb ldr r3, [r7, #24] 80006aa: fa02 f303 lsl.w r3, r2, r3 80006ae: 43da mvns r2, r3 80006b0: 68bb ldr r3, [r7, #8] 80006b2: 401a ands r2, r3 80006b4: 697b ldr r3, [r7, #20] 80006b6: 409a lsls r2, r3 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) 80006b8: f04f 31ff mov.w r1, #4294967295 80006bc: 697b ldr r3, [r7, #20] 80006be: fa01 f303 lsl.w r3, r1, r3 80006c2: 43d9 mvns r1, r3 80006c4: 687b ldr r3, [r7, #4] 80006c6: 400b ands r3, r1 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 80006c8: 4313 orrs r3, r2 ); } 80006ca: 4618 mov r0, r3 80006cc: 3724 adds r7, #36 ; 0x24 80006ce: 46bd mov sp, r7 80006d0: bc80 pop {r7} 80006d2: 4770 bx lr 080006d4 : \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { 80006d4: b580 push {r7, lr} 80006d6: b082 sub sp, #8 80006d8: af00 add r7, sp, #0 80006da: 6078 str r0, [r7, #4] if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) 80006dc: 687b ldr r3, [r7, #4] 80006de: 3b01 subs r3, #1 80006e0: f1b3 7f80 cmp.w r3, #16777216 ; 0x1000000 80006e4: d301 bcc.n 80006ea { return (1UL); /* Reload value impossible */ 80006e6: 2301 movs r3, #1 80006e8: e00f b.n 800070a } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 80006ea: 4a0a ldr r2, [pc, #40] ; (8000714 ) 80006ec: 687b ldr r3, [r7, #4] 80006ee: 3b01 subs r3, #1 80006f0: 6053 str r3, [r2, #4] NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ 80006f2: 210f movs r1, #15 80006f4: f04f 30ff mov.w r0, #4294967295 80006f8: f7ff ff90 bl 800061c <__NVIC_SetPriority> SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ 80006fc: 4b05 ldr r3, [pc, #20] ; (8000714 ) 80006fe: 2200 movs r2, #0 8000700: 609a str r2, [r3, #8] SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 8000702: 4b04 ldr r3, [pc, #16] ; (8000714 ) 8000704: 2207 movs r2, #7 8000706: 601a str r2, [r3, #0] SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ 8000708: 2300 movs r3, #0 } 800070a: 4618 mov r0, r3 800070c: 3708 adds r7, #8 800070e: 46bd mov sp, r7 8000710: bd80 pop {r7, pc} 8000712: bf00 nop 8000714: e000e010 .word 0xe000e010 08000718 : * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. * The pending IRQ priority will be managed only by the subpriority. * @retval None */ void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 8000718: b580 push {r7, lr} 800071a: b082 sub sp, #8 800071c: af00 add r7, sp, #0 800071e: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ NVIC_SetPriorityGrouping(PriorityGroup); 8000720: 6878 ldr r0, [r7, #4] 8000722: f7ff ff49 bl 80005b8 <__NVIC_SetPriorityGrouping> } 8000726: bf00 nop 8000728: 3708 adds r7, #8 800072a: 46bd mov sp, r7 800072c: bd80 pop {r7, pc} 0800072e : * This parameter can be a value between 0 and 15 * A lower priority value indicates a higher priority. * @retval None */ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) { 800072e: b580 push {r7, lr} 8000730: b086 sub sp, #24 8000732: af00 add r7, sp, #0 8000734: 4603 mov r3, r0 8000736: 60b9 str r1, [r7, #8] 8000738: 607a str r2, [r7, #4] 800073a: 73fb strb r3, [r7, #15] uint32_t prioritygroup = 0x00U; 800073c: 2300 movs r3, #0 800073e: 617b str r3, [r7, #20] /* Check the parameters */ assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); prioritygroup = NVIC_GetPriorityGrouping(); 8000740: f7ff ff5e bl 8000600 <__NVIC_GetPriorityGrouping> 8000744: 6178 str r0, [r7, #20] NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); 8000746: 687a ldr r2, [r7, #4] 8000748: 68b9 ldr r1, [r7, #8] 800074a: 6978 ldr r0, [r7, #20] 800074c: f7ff ff90 bl 8000670 8000750: 4602 mov r2, r0 8000752: f997 300f ldrsb.w r3, [r7, #15] 8000756: 4611 mov r1, r2 8000758: 4618 mov r0, r3 800075a: f7ff ff5f bl 800061c <__NVIC_SetPriority> } 800075e: bf00 nop 8000760: 3718 adds r7, #24 8000762: 46bd mov sp, r7 8000764: bd80 pop {r7, pc} 08000766 : * @param TicksNumb: Specifies the ticks Number of ticks between two interrupts. * @retval status: - 0 Function succeeded. * - 1 Function failed. */ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) { 8000766: b580 push {r7, lr} 8000768: b082 sub sp, #8 800076a: af00 add r7, sp, #0 800076c: 6078 str r0, [r7, #4] return SysTick_Config(TicksNumb); 800076e: 6878 ldr r0, [r7, #4] 8000770: f7ff ffb0 bl 80006d4 8000774: 4603 mov r3, r0 } 8000776: 4618 mov r0, r3 8000778: 3708 adds r7, #8 800077a: 46bd mov sp, r7 800077c: bd80 pop {r7, pc} ... 08000780 : * @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains * the configuration information for the specified GPIO peripheral. * @retval None */ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) { 8000780: b480 push {r7} 8000782: b08b sub sp, #44 ; 0x2c 8000784: af00 add r7, sp, #0 8000786: 6078 str r0, [r7, #4] 8000788: 6039 str r1, [r7, #0] uint32_t position = 0x00u; 800078a: 2300 movs r3, #0 800078c: 627b str r3, [r7, #36] ; 0x24 uint32_t ioposition; uint32_t iocurrent; uint32_t temp; uint32_t config = 0x00u; 800078e: 2300 movs r3, #0 8000790: 623b str r3, [r7, #32] assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); /* Configure the port pins */ while (((GPIO_Init->Pin) >> position) != 0x00u) 8000792: e169 b.n 8000a68 { /* Get the IO position */ ioposition = (0x01uL << position); 8000794: 2201 movs r2, #1 8000796: 6a7b ldr r3, [r7, #36] ; 0x24 8000798: fa02 f303 lsl.w r3, r2, r3 800079c: 61fb str r3, [r7, #28] /* Get the current IO position */ iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition; 800079e: 683b ldr r3, [r7, #0] 80007a0: 681b ldr r3, [r3, #0] 80007a2: 69fa ldr r2, [r7, #28] 80007a4: 4013 ands r3, r2 80007a6: 61bb str r3, [r7, #24] if (iocurrent == ioposition) 80007a8: 69ba ldr r2, [r7, #24] 80007aa: 69fb ldr r3, [r7, #28] 80007ac: 429a cmp r2, r3 80007ae: f040 8158 bne.w 8000a62 { /* Check the Alternate function parameters */ assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); /* Based on the required mode, filling config variable with MODEy[1:0] and CNFy[3:2] corresponding bits */ switch (GPIO_Init->Mode) 80007b2: 683b ldr r3, [r7, #0] 80007b4: 685b ldr r3, [r3, #4] 80007b6: 4a9a ldr r2, [pc, #616] ; (8000a20 ) 80007b8: 4293 cmp r3, r2 80007ba: d05e beq.n 800087a 80007bc: 4a98 ldr r2, [pc, #608] ; (8000a20 ) 80007be: 4293 cmp r3, r2 80007c0: d875 bhi.n 80008ae 80007c2: 4a98 ldr r2, [pc, #608] ; (8000a24 ) 80007c4: 4293 cmp r3, r2 80007c6: d058 beq.n 800087a 80007c8: 4a96 ldr r2, [pc, #600] ; (8000a24 ) 80007ca: 4293 cmp r3, r2 80007cc: d86f bhi.n 80008ae 80007ce: 4a96 ldr r2, [pc, #600] ; (8000a28 ) 80007d0: 4293 cmp r3, r2 80007d2: d052 beq.n 800087a 80007d4: 4a94 ldr r2, [pc, #592] ; (8000a28 ) 80007d6: 4293 cmp r3, r2 80007d8: d869 bhi.n 80008ae 80007da: 4a94 ldr r2, [pc, #592] ; (8000a2c ) 80007dc: 4293 cmp r3, r2 80007de: d04c beq.n 800087a 80007e0: 4a92 ldr r2, [pc, #584] ; (8000a2c ) 80007e2: 4293 cmp r3, r2 80007e4: d863 bhi.n 80008ae 80007e6: 4a92 ldr r2, [pc, #584] ; (8000a30 ) 80007e8: 4293 cmp r3, r2 80007ea: d046 beq.n 800087a 80007ec: 4a90 ldr r2, [pc, #576] ; (8000a30 ) 80007ee: 4293 cmp r3, r2 80007f0: d85d bhi.n 80008ae 80007f2: 2b12 cmp r3, #18 80007f4: d82a bhi.n 800084c 80007f6: 2b12 cmp r3, #18 80007f8: d859 bhi.n 80008ae 80007fa: a201 add r2, pc, #4 ; (adr r2, 8000800 ) 80007fc: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8000800: 0800087b .word 0x0800087b 8000804: 08000855 .word 0x08000855 8000808: 08000867 .word 0x08000867 800080c: 080008a9 .word 0x080008a9 8000810: 080008af .word 0x080008af 8000814: 080008af .word 0x080008af 8000818: 080008af .word 0x080008af 800081c: 080008af .word 0x080008af 8000820: 080008af .word 0x080008af 8000824: 080008af .word 0x080008af 8000828: 080008af .word 0x080008af 800082c: 080008af .word 0x080008af 8000830: 080008af .word 0x080008af 8000834: 080008af .word 0x080008af 8000838: 080008af .word 0x080008af 800083c: 080008af .word 0x080008af 8000840: 080008af .word 0x080008af 8000844: 0800085d .word 0x0800085d 8000848: 08000871 .word 0x08000871 800084c: 4a79 ldr r2, [pc, #484] ; (8000a34 ) 800084e: 4293 cmp r3, r2 8000850: d013 beq.n 800087a config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG; break; /* Parameters are checked with assert_param */ default: break; 8000852: e02c b.n 80008ae config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_PP; 8000854: 683b ldr r3, [r7, #0] 8000856: 68db ldr r3, [r3, #12] 8000858: 623b str r3, [r7, #32] break; 800085a: e029 b.n 80008b0 config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_OD; 800085c: 683b ldr r3, [r7, #0] 800085e: 68db ldr r3, [r3, #12] 8000860: 3304 adds r3, #4 8000862: 623b str r3, [r7, #32] break; 8000864: e024 b.n 80008b0 config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_PP; 8000866: 683b ldr r3, [r7, #0] 8000868: 68db ldr r3, [r3, #12] 800086a: 3308 adds r3, #8 800086c: 623b str r3, [r7, #32] break; 800086e: e01f b.n 80008b0 config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_OD; 8000870: 683b ldr r3, [r7, #0] 8000872: 68db ldr r3, [r3, #12] 8000874: 330c adds r3, #12 8000876: 623b str r3, [r7, #32] break; 8000878: e01a b.n 80008b0 if (GPIO_Init->Pull == GPIO_NOPULL) 800087a: 683b ldr r3, [r7, #0] 800087c: 689b ldr r3, [r3, #8] 800087e: 2b00 cmp r3, #0 8000880: d102 bne.n 8000888 config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_FLOATING; 8000882: 2304 movs r3, #4 8000884: 623b str r3, [r7, #32] break; 8000886: e013 b.n 80008b0 else if (GPIO_Init->Pull == GPIO_PULLUP) 8000888: 683b ldr r3, [r7, #0] 800088a: 689b ldr r3, [r3, #8] 800088c: 2b01 cmp r3, #1 800088e: d105 bne.n 800089c config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD; 8000890: 2308 movs r3, #8 8000892: 623b str r3, [r7, #32] GPIOx->BSRR = ioposition; 8000894: 687b ldr r3, [r7, #4] 8000896: 69fa ldr r2, [r7, #28] 8000898: 611a str r2, [r3, #16] break; 800089a: e009 b.n 80008b0 config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD; 800089c: 2308 movs r3, #8 800089e: 623b str r3, [r7, #32] GPIOx->BRR = ioposition; 80008a0: 687b ldr r3, [r7, #4] 80008a2: 69fa ldr r2, [r7, #28] 80008a4: 615a str r2, [r3, #20] break; 80008a6: e003 b.n 80008b0 config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG; 80008a8: 2300 movs r3, #0 80008aa: 623b str r3, [r7, #32] break; 80008ac: e000 b.n 80008b0 break; 80008ae: bf00 nop } /* Check if the current bit belongs to first half or last half of the pin count number in order to address CRH or CRL register*/ configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL : &GPIOx->CRH; 80008b0: 69bb ldr r3, [r7, #24] 80008b2: 2bff cmp r3, #255 ; 0xff 80008b4: d801 bhi.n 80008ba 80008b6: 687b ldr r3, [r7, #4] 80008b8: e001 b.n 80008be 80008ba: 687b ldr r3, [r7, #4] 80008bc: 3304 adds r3, #4 80008be: 617b str r3, [r7, #20] registeroffset = (iocurrent < GPIO_PIN_8) ? (position << 2u) : ((position - 8u) << 2u); 80008c0: 69bb ldr r3, [r7, #24] 80008c2: 2bff cmp r3, #255 ; 0xff 80008c4: d802 bhi.n 80008cc 80008c6: 6a7b ldr r3, [r7, #36] ; 0x24 80008c8: 009b lsls r3, r3, #2 80008ca: e002 b.n 80008d2 80008cc: 6a7b ldr r3, [r7, #36] ; 0x24 80008ce: 3b08 subs r3, #8 80008d0: 009b lsls r3, r3, #2 80008d2: 613b str r3, [r7, #16] /* Apply the new configuration of the pin to the register */ MODIFY_REG((*configregister), ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset), (config << registeroffset)); 80008d4: 697b ldr r3, [r7, #20] 80008d6: 681a ldr r2, [r3, #0] 80008d8: 210f movs r1, #15 80008da: 693b ldr r3, [r7, #16] 80008dc: fa01 f303 lsl.w r3, r1, r3 80008e0: 43db mvns r3, r3 80008e2: 401a ands r2, r3 80008e4: 6a39 ldr r1, [r7, #32] 80008e6: 693b ldr r3, [r7, #16] 80008e8: fa01 f303 lsl.w r3, r1, r3 80008ec: 431a orrs r2, r3 80008ee: 697b ldr r3, [r7, #20] 80008f0: 601a str r2, [r3, #0] /*--------------------- EXTI Mode Configuration ------------------------*/ /* Configure the External Interrupt or event for the current IO */ if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE) 80008f2: 683b ldr r3, [r7, #0] 80008f4: 685b ldr r3, [r3, #4] 80008f6: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 80008fa: 2b00 cmp r3, #0 80008fc: f000 80b1 beq.w 8000a62 { /* Enable AFIO Clock */ __HAL_RCC_AFIO_CLK_ENABLE(); 8000900: 4b4d ldr r3, [pc, #308] ; (8000a38 ) 8000902: 699b ldr r3, [r3, #24] 8000904: 4a4c ldr r2, [pc, #304] ; (8000a38 ) 8000906: f043 0301 orr.w r3, r3, #1 800090a: 6193 str r3, [r2, #24] 800090c: 4b4a ldr r3, [pc, #296] ; (8000a38 ) 800090e: 699b ldr r3, [r3, #24] 8000910: f003 0301 and.w r3, r3, #1 8000914: 60bb str r3, [r7, #8] 8000916: 68bb ldr r3, [r7, #8] temp = AFIO->EXTICR[position >> 2u]; 8000918: 4a48 ldr r2, [pc, #288] ; (8000a3c ) 800091a: 6a7b ldr r3, [r7, #36] ; 0x24 800091c: 089b lsrs r3, r3, #2 800091e: 3302 adds r3, #2 8000920: f852 3023 ldr.w r3, [r2, r3, lsl #2] 8000924: 60fb str r3, [r7, #12] CLEAR_BIT(temp, (0x0Fu) << (4u * (position & 0x03u))); 8000926: 6a7b ldr r3, [r7, #36] ; 0x24 8000928: f003 0303 and.w r3, r3, #3 800092c: 009b lsls r3, r3, #2 800092e: 220f movs r2, #15 8000930: fa02 f303 lsl.w r3, r2, r3 8000934: 43db mvns r3, r3 8000936: 68fa ldr r2, [r7, #12] 8000938: 4013 ands r3, r2 800093a: 60fb str r3, [r7, #12] SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4u * (position & 0x03u))); 800093c: 687b ldr r3, [r7, #4] 800093e: 4a40 ldr r2, [pc, #256] ; (8000a40 ) 8000940: 4293 cmp r3, r2 8000942: d013 beq.n 800096c 8000944: 687b ldr r3, [r7, #4] 8000946: 4a3f ldr r2, [pc, #252] ; (8000a44 ) 8000948: 4293 cmp r3, r2 800094a: d00d beq.n 8000968 800094c: 687b ldr r3, [r7, #4] 800094e: 4a3e ldr r2, [pc, #248] ; (8000a48 ) 8000950: 4293 cmp r3, r2 8000952: d007 beq.n 8000964 8000954: 687b ldr r3, [r7, #4] 8000956: 4a3d ldr r2, [pc, #244] ; (8000a4c ) 8000958: 4293 cmp r3, r2 800095a: d101 bne.n 8000960 800095c: 2303 movs r3, #3 800095e: e006 b.n 800096e 8000960: 2304 movs r3, #4 8000962: e004 b.n 800096e 8000964: 2302 movs r3, #2 8000966: e002 b.n 800096e 8000968: 2301 movs r3, #1 800096a: e000 b.n 800096e 800096c: 2300 movs r3, #0 800096e: 6a7a ldr r2, [r7, #36] ; 0x24 8000970: f002 0203 and.w r2, r2, #3 8000974: 0092 lsls r2, r2, #2 8000976: 4093 lsls r3, r2 8000978: 68fa ldr r2, [r7, #12] 800097a: 4313 orrs r3, r2 800097c: 60fb str r3, [r7, #12] AFIO->EXTICR[position >> 2u] = temp; 800097e: 492f ldr r1, [pc, #188] ; (8000a3c ) 8000980: 6a7b ldr r3, [r7, #36] ; 0x24 8000982: 089b lsrs r3, r3, #2 8000984: 3302 adds r3, #2 8000986: 68fa ldr r2, [r7, #12] 8000988: f841 2023 str.w r2, [r1, r3, lsl #2] /* Configure the interrupt mask */ if ((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT) 800098c: 683b ldr r3, [r7, #0] 800098e: 685b ldr r3, [r3, #4] 8000990: f403 3380 and.w r3, r3, #65536 ; 0x10000 8000994: 2b00 cmp r3, #0 8000996: d006 beq.n 80009a6 { SET_BIT(EXTI->IMR, iocurrent); 8000998: 4b2d ldr r3, [pc, #180] ; (8000a50 ) 800099a: 681a ldr r2, [r3, #0] 800099c: 492c ldr r1, [pc, #176] ; (8000a50 ) 800099e: 69bb ldr r3, [r7, #24] 80009a0: 4313 orrs r3, r2 80009a2: 600b str r3, [r1, #0] 80009a4: e006 b.n 80009b4 } else { CLEAR_BIT(EXTI->IMR, iocurrent); 80009a6: 4b2a ldr r3, [pc, #168] ; (8000a50 ) 80009a8: 681a ldr r2, [r3, #0] 80009aa: 69bb ldr r3, [r7, #24] 80009ac: 43db mvns r3, r3 80009ae: 4928 ldr r1, [pc, #160] ; (8000a50 ) 80009b0: 4013 ands r3, r2 80009b2: 600b str r3, [r1, #0] } /* Configure the event mask */ if ((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT) 80009b4: 683b ldr r3, [r7, #0] 80009b6: 685b ldr r3, [r3, #4] 80009b8: f403 3300 and.w r3, r3, #131072 ; 0x20000 80009bc: 2b00 cmp r3, #0 80009be: d006 beq.n 80009ce { SET_BIT(EXTI->EMR, iocurrent); 80009c0: 4b23 ldr r3, [pc, #140] ; (8000a50 ) 80009c2: 685a ldr r2, [r3, #4] 80009c4: 4922 ldr r1, [pc, #136] ; (8000a50 ) 80009c6: 69bb ldr r3, [r7, #24] 80009c8: 4313 orrs r3, r2 80009ca: 604b str r3, [r1, #4] 80009cc: e006 b.n 80009dc } else { CLEAR_BIT(EXTI->EMR, iocurrent); 80009ce: 4b20 ldr r3, [pc, #128] ; (8000a50 ) 80009d0: 685a ldr r2, [r3, #4] 80009d2: 69bb ldr r3, [r7, #24] 80009d4: 43db mvns r3, r3 80009d6: 491e ldr r1, [pc, #120] ; (8000a50 ) 80009d8: 4013 ands r3, r2 80009da: 604b str r3, [r1, #4] } /* Enable or disable the rising trigger */ if ((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE) 80009dc: 683b ldr r3, [r7, #0] 80009de: 685b ldr r3, [r3, #4] 80009e0: f403 1380 and.w r3, r3, #1048576 ; 0x100000 80009e4: 2b00 cmp r3, #0 80009e6: d006 beq.n 80009f6 { SET_BIT(EXTI->RTSR, iocurrent); 80009e8: 4b19 ldr r3, [pc, #100] ; (8000a50 ) 80009ea: 689a ldr r2, [r3, #8] 80009ec: 4918 ldr r1, [pc, #96] ; (8000a50 ) 80009ee: 69bb ldr r3, [r7, #24] 80009f0: 4313 orrs r3, r2 80009f2: 608b str r3, [r1, #8] 80009f4: e006 b.n 8000a04 } else { CLEAR_BIT(EXTI->RTSR, iocurrent); 80009f6: 4b16 ldr r3, [pc, #88] ; (8000a50 ) 80009f8: 689a ldr r2, [r3, #8] 80009fa: 69bb ldr r3, [r7, #24] 80009fc: 43db mvns r3, r3 80009fe: 4914 ldr r1, [pc, #80] ; (8000a50 ) 8000a00: 4013 ands r3, r2 8000a02: 608b str r3, [r1, #8] } /* Enable or disable the falling trigger */ if ((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE) 8000a04: 683b ldr r3, [r7, #0] 8000a06: 685b ldr r3, [r3, #4] 8000a08: f403 1300 and.w r3, r3, #2097152 ; 0x200000 8000a0c: 2b00 cmp r3, #0 8000a0e: d021 beq.n 8000a54 { SET_BIT(EXTI->FTSR, iocurrent); 8000a10: 4b0f ldr r3, [pc, #60] ; (8000a50 ) 8000a12: 68da ldr r2, [r3, #12] 8000a14: 490e ldr r1, [pc, #56] ; (8000a50 ) 8000a16: 69bb ldr r3, [r7, #24] 8000a18: 4313 orrs r3, r2 8000a1a: 60cb str r3, [r1, #12] 8000a1c: e021 b.n 8000a62 8000a1e: bf00 nop 8000a20: 10320000 .word 0x10320000 8000a24: 10310000 .word 0x10310000 8000a28: 10220000 .word 0x10220000 8000a2c: 10210000 .word 0x10210000 8000a30: 10120000 .word 0x10120000 8000a34: 10110000 .word 0x10110000 8000a38: 40021000 .word 0x40021000 8000a3c: 40010000 .word 0x40010000 8000a40: 40010800 .word 0x40010800 8000a44: 40010c00 .word 0x40010c00 8000a48: 40011000 .word 0x40011000 8000a4c: 40011400 .word 0x40011400 8000a50: 40010400 .word 0x40010400 } else { CLEAR_BIT(EXTI->FTSR, iocurrent); 8000a54: 4b0b ldr r3, [pc, #44] ; (8000a84 ) 8000a56: 68da ldr r2, [r3, #12] 8000a58: 69bb ldr r3, [r7, #24] 8000a5a: 43db mvns r3, r3 8000a5c: 4909 ldr r1, [pc, #36] ; (8000a84 ) 8000a5e: 4013 ands r3, r2 8000a60: 60cb str r3, [r1, #12] } } } position++; 8000a62: 6a7b ldr r3, [r7, #36] ; 0x24 8000a64: 3301 adds r3, #1 8000a66: 627b str r3, [r7, #36] ; 0x24 while (((GPIO_Init->Pin) >> position) != 0x00u) 8000a68: 683b ldr r3, [r7, #0] 8000a6a: 681a ldr r2, [r3, #0] 8000a6c: 6a7b ldr r3, [r7, #36] ; 0x24 8000a6e: fa22 f303 lsr.w r3, r2, r3 8000a72: 2b00 cmp r3, #0 8000a74: f47f ae8e bne.w 8000794 } } 8000a78: bf00 nop 8000a7a: bf00 nop 8000a7c: 372c adds r7, #44 ; 0x2c 8000a7e: 46bd mov sp, r7 8000a80: bc80 pop {r7} 8000a82: 4770 bx lr 8000a84: 40010400 .word 0x40010400 08000a88 : * supported by this macro. User should request a transition to HSE Off * first and then HSE On or HSE Bypass. * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { 8000a88: b580 push {r7, lr} 8000a8a: b086 sub sp, #24 8000a8c: af00 add r7, sp, #0 8000a8e: 6078 str r0, [r7, #4] uint32_t tickstart; uint32_t pll_config; /* Check Null pointer */ if (RCC_OscInitStruct == NULL) 8000a90: 687b ldr r3, [r7, #4] 8000a92: 2b00 cmp r3, #0 8000a94: d101 bne.n 8000a9a { return HAL_ERROR; 8000a96: 2301 movs r3, #1 8000a98: e272 b.n 8000f80 /* Check the parameters */ assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); /*------------------------------- HSE Configuration ------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) 8000a9a: 687b ldr r3, [r7, #4] 8000a9c: 681b ldr r3, [r3, #0] 8000a9e: f003 0301 and.w r3, r3, #1 8000aa2: 2b00 cmp r3, #0 8000aa4: f000 8087 beq.w 8000bb6 { /* Check the parameters */ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */ if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE) 8000aa8: 4b92 ldr r3, [pc, #584] ; (8000cf4 ) 8000aaa: 685b ldr r3, [r3, #4] 8000aac: f003 030c and.w r3, r3, #12 8000ab0: 2b04 cmp r3, #4 8000ab2: d00c beq.n 8000ace || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE))) 8000ab4: 4b8f ldr r3, [pc, #572] ; (8000cf4 ) 8000ab6: 685b ldr r3, [r3, #4] 8000ab8: f003 030c and.w r3, r3, #12 8000abc: 2b08 cmp r3, #8 8000abe: d112 bne.n 8000ae6 8000ac0: 4b8c ldr r3, [pc, #560] ; (8000cf4 ) 8000ac2: 685b ldr r3, [r3, #4] 8000ac4: f403 3380 and.w r3, r3, #65536 ; 0x10000 8000ac8: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 8000acc: d10b bne.n 8000ae6 { if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 8000ace: 4b89 ldr r3, [pc, #548] ; (8000cf4 ) 8000ad0: 681b ldr r3, [r3, #0] 8000ad2: f403 3300 and.w r3, r3, #131072 ; 0x20000 8000ad6: 2b00 cmp r3, #0 8000ad8: d06c beq.n 8000bb4 8000ada: 687b ldr r3, [r7, #4] 8000adc: 685b ldr r3, [r3, #4] 8000ade: 2b00 cmp r3, #0 8000ae0: d168 bne.n 8000bb4 { return HAL_ERROR; 8000ae2: 2301 movs r3, #1 8000ae4: e24c b.n 8000f80 } } else { /* Set the new HSE configuration ---------------------------------------*/ __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); 8000ae6: 687b ldr r3, [r7, #4] 8000ae8: 685b ldr r3, [r3, #4] 8000aea: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 8000aee: d106 bne.n 8000afe 8000af0: 4b80 ldr r3, [pc, #512] ; (8000cf4 ) 8000af2: 681b ldr r3, [r3, #0] 8000af4: 4a7f ldr r2, [pc, #508] ; (8000cf4 ) 8000af6: f443 3380 orr.w r3, r3, #65536 ; 0x10000 8000afa: 6013 str r3, [r2, #0] 8000afc: e02e b.n 8000b5c 8000afe: 687b ldr r3, [r7, #4] 8000b00: 685b ldr r3, [r3, #4] 8000b02: 2b00 cmp r3, #0 8000b04: d10c bne.n 8000b20 8000b06: 4b7b ldr r3, [pc, #492] ; (8000cf4 ) 8000b08: 681b ldr r3, [r3, #0] 8000b0a: 4a7a ldr r2, [pc, #488] ; (8000cf4 ) 8000b0c: f423 3380 bic.w r3, r3, #65536 ; 0x10000 8000b10: 6013 str r3, [r2, #0] 8000b12: 4b78 ldr r3, [pc, #480] ; (8000cf4 ) 8000b14: 681b ldr r3, [r3, #0] 8000b16: 4a77 ldr r2, [pc, #476] ; (8000cf4 ) 8000b18: f423 2380 bic.w r3, r3, #262144 ; 0x40000 8000b1c: 6013 str r3, [r2, #0] 8000b1e: e01d b.n 8000b5c 8000b20: 687b ldr r3, [r7, #4] 8000b22: 685b ldr r3, [r3, #4] 8000b24: f5b3 2fa0 cmp.w r3, #327680 ; 0x50000 8000b28: d10c bne.n 8000b44 8000b2a: 4b72 ldr r3, [pc, #456] ; (8000cf4 ) 8000b2c: 681b ldr r3, [r3, #0] 8000b2e: 4a71 ldr r2, [pc, #452] ; (8000cf4 ) 8000b30: f443 2380 orr.w r3, r3, #262144 ; 0x40000 8000b34: 6013 str r3, [r2, #0] 8000b36: 4b6f ldr r3, [pc, #444] ; (8000cf4 ) 8000b38: 681b ldr r3, [r3, #0] 8000b3a: 4a6e ldr r2, [pc, #440] ; (8000cf4 ) 8000b3c: f443 3380 orr.w r3, r3, #65536 ; 0x10000 8000b40: 6013 str r3, [r2, #0] 8000b42: e00b b.n 8000b5c 8000b44: 4b6b ldr r3, [pc, #428] ; (8000cf4 ) 8000b46: 681b ldr r3, [r3, #0] 8000b48: 4a6a ldr r2, [pc, #424] ; (8000cf4 ) 8000b4a: f423 3380 bic.w r3, r3, #65536 ; 0x10000 8000b4e: 6013 str r3, [r2, #0] 8000b50: 4b68 ldr r3, [pc, #416] ; (8000cf4 ) 8000b52: 681b ldr r3, [r3, #0] 8000b54: 4a67 ldr r2, [pc, #412] ; (8000cf4 ) 8000b56: f423 2380 bic.w r3, r3, #262144 ; 0x40000 8000b5a: 6013 str r3, [r2, #0] /* Check the HSE State */ if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF) 8000b5c: 687b ldr r3, [r7, #4] 8000b5e: 685b ldr r3, [r3, #4] 8000b60: 2b00 cmp r3, #0 8000b62: d013 beq.n 8000b8c { /* Get Start Tick */ tickstart = HAL_GetTick(); 8000b64: f7ff fd1e bl 80005a4 8000b68: 6138 str r0, [r7, #16] /* Wait till HSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 8000b6a: e008 b.n 8000b7e { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 8000b6c: f7ff fd1a bl 80005a4 8000b70: 4602 mov r2, r0 8000b72: 693b ldr r3, [r7, #16] 8000b74: 1ad3 subs r3, r2, r3 8000b76: 2b64 cmp r3, #100 ; 0x64 8000b78: d901 bls.n 8000b7e { return HAL_TIMEOUT; 8000b7a: 2303 movs r3, #3 8000b7c: e200 b.n 8000f80 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 8000b7e: 4b5d ldr r3, [pc, #372] ; (8000cf4 ) 8000b80: 681b ldr r3, [r3, #0] 8000b82: f403 3300 and.w r3, r3, #131072 ; 0x20000 8000b86: 2b00 cmp r3, #0 8000b88: d0f0 beq.n 8000b6c 8000b8a: e014 b.n 8000bb6 } } else { /* Get Start Tick */ tickstart = HAL_GetTick(); 8000b8c: f7ff fd0a bl 80005a4 8000b90: 6138 str r0, [r7, #16] /* Wait till HSE is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) 8000b92: e008 b.n 8000ba6 { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 8000b94: f7ff fd06 bl 80005a4 8000b98: 4602 mov r2, r0 8000b9a: 693b ldr r3, [r7, #16] 8000b9c: 1ad3 subs r3, r2, r3 8000b9e: 2b64 cmp r3, #100 ; 0x64 8000ba0: d901 bls.n 8000ba6 { return HAL_TIMEOUT; 8000ba2: 2303 movs r3, #3 8000ba4: e1ec b.n 8000f80 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) 8000ba6: 4b53 ldr r3, [pc, #332] ; (8000cf4 ) 8000ba8: 681b ldr r3, [r3, #0] 8000baa: f403 3300 and.w r3, r3, #131072 ; 0x20000 8000bae: 2b00 cmp r3, #0 8000bb0: d1f0 bne.n 8000b94 8000bb2: e000 b.n 8000bb6 if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 8000bb4: bf00 nop } } } } /*----------------------------- HSI Configuration --------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) 8000bb6: 687b ldr r3, [r7, #4] 8000bb8: 681b ldr r3, [r3, #0] 8000bba: f003 0302 and.w r3, r3, #2 8000bbe: 2b00 cmp r3, #0 8000bc0: d063 beq.n 8000c8a /* Check the parameters */ assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI) 8000bc2: 4b4c ldr r3, [pc, #304] ; (8000cf4 ) 8000bc4: 685b ldr r3, [r3, #4] 8000bc6: f003 030c and.w r3, r3, #12 8000bca: 2b00 cmp r3, #0 8000bcc: d00b beq.n 8000be6 || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI_DIV2))) 8000bce: 4b49 ldr r3, [pc, #292] ; (8000cf4 ) 8000bd0: 685b ldr r3, [r3, #4] 8000bd2: f003 030c and.w r3, r3, #12 8000bd6: 2b08 cmp r3, #8 8000bd8: d11c bne.n 8000c14 8000bda: 4b46 ldr r3, [pc, #280] ; (8000cf4 ) 8000bdc: 685b ldr r3, [r3, #4] 8000bde: f403 3380 and.w r3, r3, #65536 ; 0x10000 8000be2: 2b00 cmp r3, #0 8000be4: d116 bne.n 8000c14 { /* When HSI is used as system clock it will not disabled */ if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) 8000be6: 4b43 ldr r3, [pc, #268] ; (8000cf4 ) 8000be8: 681b ldr r3, [r3, #0] 8000bea: f003 0302 and.w r3, r3, #2 8000bee: 2b00 cmp r3, #0 8000bf0: d005 beq.n 8000bfe 8000bf2: 687b ldr r3, [r7, #4] 8000bf4: 691b ldr r3, [r3, #16] 8000bf6: 2b01 cmp r3, #1 8000bf8: d001 beq.n 8000bfe { return HAL_ERROR; 8000bfa: 2301 movs r3, #1 8000bfc: e1c0 b.n 8000f80 } /* Otherwise, just the calibration is allowed */ else { /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 8000bfe: 4b3d ldr r3, [pc, #244] ; (8000cf4 ) 8000c00: 681b ldr r3, [r3, #0] 8000c02: f023 02f8 bic.w r2, r3, #248 ; 0xf8 8000c06: 687b ldr r3, [r7, #4] 8000c08: 695b ldr r3, [r3, #20] 8000c0a: 00db lsls r3, r3, #3 8000c0c: 4939 ldr r1, [pc, #228] ; (8000cf4 ) 8000c0e: 4313 orrs r3, r2 8000c10: 600b str r3, [r1, #0] if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) 8000c12: e03a b.n 8000c8a } } else { /* Check the HSI State */ if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF) 8000c14: 687b ldr r3, [r7, #4] 8000c16: 691b ldr r3, [r3, #16] 8000c18: 2b00 cmp r3, #0 8000c1a: d020 beq.n 8000c5e { /* Enable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_ENABLE(); 8000c1c: 4b36 ldr r3, [pc, #216] ; (8000cf8 ) 8000c1e: 2201 movs r2, #1 8000c20: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8000c22: f7ff fcbf bl 80005a4 8000c26: 6138 str r0, [r7, #16] /* Wait till HSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 8000c28: e008 b.n 8000c3c { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 8000c2a: f7ff fcbb bl 80005a4 8000c2e: 4602 mov r2, r0 8000c30: 693b ldr r3, [r7, #16] 8000c32: 1ad3 subs r3, r2, r3 8000c34: 2b02 cmp r3, #2 8000c36: d901 bls.n 8000c3c { return HAL_TIMEOUT; 8000c38: 2303 movs r3, #3 8000c3a: e1a1 b.n 8000f80 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 8000c3c: 4b2d ldr r3, [pc, #180] ; (8000cf4 ) 8000c3e: 681b ldr r3, [r3, #0] 8000c40: f003 0302 and.w r3, r3, #2 8000c44: 2b00 cmp r3, #0 8000c46: d0f0 beq.n 8000c2a } } /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 8000c48: 4b2a ldr r3, [pc, #168] ; (8000cf4 ) 8000c4a: 681b ldr r3, [r3, #0] 8000c4c: f023 02f8 bic.w r2, r3, #248 ; 0xf8 8000c50: 687b ldr r3, [r7, #4] 8000c52: 695b ldr r3, [r3, #20] 8000c54: 00db lsls r3, r3, #3 8000c56: 4927 ldr r1, [pc, #156] ; (8000cf4 ) 8000c58: 4313 orrs r3, r2 8000c5a: 600b str r3, [r1, #0] 8000c5c: e015 b.n 8000c8a } else { /* Disable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_DISABLE(); 8000c5e: 4b26 ldr r3, [pc, #152] ; (8000cf8 ) 8000c60: 2200 movs r2, #0 8000c62: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8000c64: f7ff fc9e bl 80005a4 8000c68: 6138 str r0, [r7, #16] /* Wait till HSI is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) 8000c6a: e008 b.n 8000c7e { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 8000c6c: f7ff fc9a bl 80005a4 8000c70: 4602 mov r2, r0 8000c72: 693b ldr r3, [r7, #16] 8000c74: 1ad3 subs r3, r2, r3 8000c76: 2b02 cmp r3, #2 8000c78: d901 bls.n 8000c7e { return HAL_TIMEOUT; 8000c7a: 2303 movs r3, #3 8000c7c: e180 b.n 8000f80 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) 8000c7e: 4b1d ldr r3, [pc, #116] ; (8000cf4 ) 8000c80: 681b ldr r3, [r3, #0] 8000c82: f003 0302 and.w r3, r3, #2 8000c86: 2b00 cmp r3, #0 8000c88: d1f0 bne.n 8000c6c } } } } /*------------------------------ LSI Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) 8000c8a: 687b ldr r3, [r7, #4] 8000c8c: 681b ldr r3, [r3, #0] 8000c8e: f003 0308 and.w r3, r3, #8 8000c92: 2b00 cmp r3, #0 8000c94: d03a beq.n 8000d0c { /* Check the parameters */ assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); /* Check the LSI State */ if (RCC_OscInitStruct->LSIState != RCC_LSI_OFF) 8000c96: 687b ldr r3, [r7, #4] 8000c98: 699b ldr r3, [r3, #24] 8000c9a: 2b00 cmp r3, #0 8000c9c: d019 beq.n 8000cd2 { /* Enable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_ENABLE(); 8000c9e: 4b17 ldr r3, [pc, #92] ; (8000cfc ) 8000ca0: 2201 movs r2, #1 8000ca2: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8000ca4: f7ff fc7e bl 80005a4 8000ca8: 6138 str r0, [r7, #16] /* Wait till LSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) 8000caa: e008 b.n 8000cbe { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 8000cac: f7ff fc7a bl 80005a4 8000cb0: 4602 mov r2, r0 8000cb2: 693b ldr r3, [r7, #16] 8000cb4: 1ad3 subs r3, r2, r3 8000cb6: 2b02 cmp r3, #2 8000cb8: d901 bls.n 8000cbe { return HAL_TIMEOUT; 8000cba: 2303 movs r3, #3 8000cbc: e160 b.n 8000f80 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) 8000cbe: 4b0d ldr r3, [pc, #52] ; (8000cf4 ) 8000cc0: 6a5b ldr r3, [r3, #36] ; 0x24 8000cc2: f003 0302 and.w r3, r3, #2 8000cc6: 2b00 cmp r3, #0 8000cc8: d0f0 beq.n 8000cac } } /* To have a fully stabilized clock in the specified range, a software delay of 1ms should be added.*/ RCC_Delay(1); 8000cca: 2001 movs r0, #1 8000ccc: f000 faa6 bl 800121c 8000cd0: e01c b.n 8000d0c } else { /* Disable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_DISABLE(); 8000cd2: 4b0a ldr r3, [pc, #40] ; (8000cfc ) 8000cd4: 2200 movs r2, #0 8000cd6: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8000cd8: f7ff fc64 bl 80005a4 8000cdc: 6138 str r0, [r7, #16] /* Wait till LSI is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) 8000cde: e00f b.n 8000d00 { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 8000ce0: f7ff fc60 bl 80005a4 8000ce4: 4602 mov r2, r0 8000ce6: 693b ldr r3, [r7, #16] 8000ce8: 1ad3 subs r3, r2, r3 8000cea: 2b02 cmp r3, #2 8000cec: d908 bls.n 8000d00 { return HAL_TIMEOUT; 8000cee: 2303 movs r3, #3 8000cf0: e146 b.n 8000f80 8000cf2: bf00 nop 8000cf4: 40021000 .word 0x40021000 8000cf8: 42420000 .word 0x42420000 8000cfc: 42420480 .word 0x42420480 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) 8000d00: 4b92 ldr r3, [pc, #584] ; (8000f4c ) 8000d02: 6a5b ldr r3, [r3, #36] ; 0x24 8000d04: f003 0302 and.w r3, r3, #2 8000d08: 2b00 cmp r3, #0 8000d0a: d1e9 bne.n 8000ce0 } } } } /*------------------------------ LSE Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) 8000d0c: 687b ldr r3, [r7, #4] 8000d0e: 681b ldr r3, [r3, #0] 8000d10: f003 0304 and.w r3, r3, #4 8000d14: 2b00 cmp r3, #0 8000d16: f000 80a6 beq.w 8000e66 { FlagStatus pwrclkchanged = RESET; 8000d1a: 2300 movs r3, #0 8000d1c: 75fb strb r3, [r7, #23] /* Check the parameters */ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); /* Update LSE configuration in Backup Domain control register */ /* Requires to enable write access to Backup Domain of necessary */ if (__HAL_RCC_PWR_IS_CLK_DISABLED()) 8000d1e: 4b8b ldr r3, [pc, #556] ; (8000f4c ) 8000d20: 69db ldr r3, [r3, #28] 8000d22: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 8000d26: 2b00 cmp r3, #0 8000d28: d10d bne.n 8000d46 { __HAL_RCC_PWR_CLK_ENABLE(); 8000d2a: 4b88 ldr r3, [pc, #544] ; (8000f4c ) 8000d2c: 69db ldr r3, [r3, #28] 8000d2e: 4a87 ldr r2, [pc, #540] ; (8000f4c ) 8000d30: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 8000d34: 61d3 str r3, [r2, #28] 8000d36: 4b85 ldr r3, [pc, #532] ; (8000f4c ) 8000d38: 69db ldr r3, [r3, #28] 8000d3a: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 8000d3e: 60bb str r3, [r7, #8] 8000d40: 68bb ldr r3, [r7, #8] pwrclkchanged = SET; 8000d42: 2301 movs r3, #1 8000d44: 75fb strb r3, [r7, #23] } if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8000d46: 4b82 ldr r3, [pc, #520] ; (8000f50 ) 8000d48: 681b ldr r3, [r3, #0] 8000d4a: f403 7380 and.w r3, r3, #256 ; 0x100 8000d4e: 2b00 cmp r3, #0 8000d50: d118 bne.n 8000d84 { /* Enable write access to Backup domain */ SET_BIT(PWR->CR, PWR_CR_DBP); 8000d52: 4b7f ldr r3, [pc, #508] ; (8000f50 ) 8000d54: 681b ldr r3, [r3, #0] 8000d56: 4a7e ldr r2, [pc, #504] ; (8000f50 ) 8000d58: f443 7380 orr.w r3, r3, #256 ; 0x100 8000d5c: 6013 str r3, [r2, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 8000d5e: f7ff fc21 bl 80005a4 8000d62: 6138 str r0, [r7, #16] while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8000d64: e008 b.n 8000d78 { if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 8000d66: f7ff fc1d bl 80005a4 8000d6a: 4602 mov r2, r0 8000d6c: 693b ldr r3, [r7, #16] 8000d6e: 1ad3 subs r3, r2, r3 8000d70: 2b64 cmp r3, #100 ; 0x64 8000d72: d901 bls.n 8000d78 { return HAL_TIMEOUT; 8000d74: 2303 movs r3, #3 8000d76: e103 b.n 8000f80 while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8000d78: 4b75 ldr r3, [pc, #468] ; (8000f50 ) 8000d7a: 681b ldr r3, [r3, #0] 8000d7c: f403 7380 and.w r3, r3, #256 ; 0x100 8000d80: 2b00 cmp r3, #0 8000d82: d0f0 beq.n 8000d66 } } } /* Set the new LSE configuration -----------------------------------------*/ __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); 8000d84: 687b ldr r3, [r7, #4] 8000d86: 68db ldr r3, [r3, #12] 8000d88: 2b01 cmp r3, #1 8000d8a: d106 bne.n 8000d9a 8000d8c: 4b6f ldr r3, [pc, #444] ; (8000f4c ) 8000d8e: 6a1b ldr r3, [r3, #32] 8000d90: 4a6e ldr r2, [pc, #440] ; (8000f4c ) 8000d92: f043 0301 orr.w r3, r3, #1 8000d96: 6213 str r3, [r2, #32] 8000d98: e02d b.n 8000df6 8000d9a: 687b ldr r3, [r7, #4] 8000d9c: 68db ldr r3, [r3, #12] 8000d9e: 2b00 cmp r3, #0 8000da0: d10c bne.n 8000dbc 8000da2: 4b6a ldr r3, [pc, #424] ; (8000f4c ) 8000da4: 6a1b ldr r3, [r3, #32] 8000da6: 4a69 ldr r2, [pc, #420] ; (8000f4c ) 8000da8: f023 0301 bic.w r3, r3, #1 8000dac: 6213 str r3, [r2, #32] 8000dae: 4b67 ldr r3, [pc, #412] ; (8000f4c ) 8000db0: 6a1b ldr r3, [r3, #32] 8000db2: 4a66 ldr r2, [pc, #408] ; (8000f4c ) 8000db4: f023 0304 bic.w r3, r3, #4 8000db8: 6213 str r3, [r2, #32] 8000dba: e01c b.n 8000df6 8000dbc: 687b ldr r3, [r7, #4] 8000dbe: 68db ldr r3, [r3, #12] 8000dc0: 2b05 cmp r3, #5 8000dc2: d10c bne.n 8000dde 8000dc4: 4b61 ldr r3, [pc, #388] ; (8000f4c ) 8000dc6: 6a1b ldr r3, [r3, #32] 8000dc8: 4a60 ldr r2, [pc, #384] ; (8000f4c ) 8000dca: f043 0304 orr.w r3, r3, #4 8000dce: 6213 str r3, [r2, #32] 8000dd0: 4b5e ldr r3, [pc, #376] ; (8000f4c ) 8000dd2: 6a1b ldr r3, [r3, #32] 8000dd4: 4a5d ldr r2, [pc, #372] ; (8000f4c ) 8000dd6: f043 0301 orr.w r3, r3, #1 8000dda: 6213 str r3, [r2, #32] 8000ddc: e00b b.n 8000df6 8000dde: 4b5b ldr r3, [pc, #364] ; (8000f4c ) 8000de0: 6a1b ldr r3, [r3, #32] 8000de2: 4a5a ldr r2, [pc, #360] ; (8000f4c ) 8000de4: f023 0301 bic.w r3, r3, #1 8000de8: 6213 str r3, [r2, #32] 8000dea: 4b58 ldr r3, [pc, #352] ; (8000f4c ) 8000dec: 6a1b ldr r3, [r3, #32] 8000dee: 4a57 ldr r2, [pc, #348] ; (8000f4c ) 8000df0: f023 0304 bic.w r3, r3, #4 8000df4: 6213 str r3, [r2, #32] /* Check the LSE State */ if (RCC_OscInitStruct->LSEState != RCC_LSE_OFF) 8000df6: 687b ldr r3, [r7, #4] 8000df8: 68db ldr r3, [r3, #12] 8000dfa: 2b00 cmp r3, #0 8000dfc: d015 beq.n 8000e2a { /* Get Start Tick */ tickstart = HAL_GetTick(); 8000dfe: f7ff fbd1 bl 80005a4 8000e02: 6138 str r0, [r7, #16] /* Wait till LSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 8000e04: e00a b.n 8000e1c { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 8000e06: f7ff fbcd bl 80005a4 8000e0a: 4602 mov r2, r0 8000e0c: 693b ldr r3, [r7, #16] 8000e0e: 1ad3 subs r3, r2, r3 8000e10: f241 3288 movw r2, #5000 ; 0x1388 8000e14: 4293 cmp r3, r2 8000e16: d901 bls.n 8000e1c { return HAL_TIMEOUT; 8000e18: 2303 movs r3, #3 8000e1a: e0b1 b.n 8000f80 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 8000e1c: 4b4b ldr r3, [pc, #300] ; (8000f4c ) 8000e1e: 6a1b ldr r3, [r3, #32] 8000e20: f003 0302 and.w r3, r3, #2 8000e24: 2b00 cmp r3, #0 8000e26: d0ee beq.n 8000e06 8000e28: e014 b.n 8000e54 } } else { /* Get Start Tick */ tickstart = HAL_GetTick(); 8000e2a: f7ff fbbb bl 80005a4 8000e2e: 6138 str r0, [r7, #16] /* Wait till LSE is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) 8000e30: e00a b.n 8000e48 { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 8000e32: f7ff fbb7 bl 80005a4 8000e36: 4602 mov r2, r0 8000e38: 693b ldr r3, [r7, #16] 8000e3a: 1ad3 subs r3, r2, r3 8000e3c: f241 3288 movw r2, #5000 ; 0x1388 8000e40: 4293 cmp r3, r2 8000e42: d901 bls.n 8000e48 { return HAL_TIMEOUT; 8000e44: 2303 movs r3, #3 8000e46: e09b b.n 8000f80 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) 8000e48: 4b40 ldr r3, [pc, #256] ; (8000f4c ) 8000e4a: 6a1b ldr r3, [r3, #32] 8000e4c: f003 0302 and.w r3, r3, #2 8000e50: 2b00 cmp r3, #0 8000e52: d1ee bne.n 8000e32 } } } /* Require to disable power clock if necessary */ if (pwrclkchanged == SET) 8000e54: 7dfb ldrb r3, [r7, #23] 8000e56: 2b01 cmp r3, #1 8000e58: d105 bne.n 8000e66 { __HAL_RCC_PWR_CLK_DISABLE(); 8000e5a: 4b3c ldr r3, [pc, #240] ; (8000f4c ) 8000e5c: 69db ldr r3, [r3, #28] 8000e5e: 4a3b ldr r2, [pc, #236] ; (8000f4c ) 8000e60: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000 8000e64: 61d3 str r3, [r2, #28] #endif /* RCC_CR_PLL2ON */ /*-------------------------------- PLL Configuration -----------------------*/ /* Check the parameters */ assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) 8000e66: 687b ldr r3, [r7, #4] 8000e68: 69db ldr r3, [r3, #28] 8000e6a: 2b00 cmp r3, #0 8000e6c: f000 8087 beq.w 8000f7e { /* Check if the PLL is used as system clock or not */ if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) 8000e70: 4b36 ldr r3, [pc, #216] ; (8000f4c ) 8000e72: 685b ldr r3, [r3, #4] 8000e74: f003 030c and.w r3, r3, #12 8000e78: 2b08 cmp r3, #8 8000e7a: d061 beq.n 8000f40 { if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) 8000e7c: 687b ldr r3, [r7, #4] 8000e7e: 69db ldr r3, [r3, #28] 8000e80: 2b02 cmp r3, #2 8000e82: d146 bne.n 8000f12 /* Check the parameters */ assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource)); assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL)); /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 8000e84: 4b33 ldr r3, [pc, #204] ; (8000f54 ) 8000e86: 2200 movs r2, #0 8000e88: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8000e8a: f7ff fb8b bl 80005a4 8000e8e: 6138 str r0, [r7, #16] /* Wait till PLL is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 8000e90: e008 b.n 8000ea4 { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 8000e92: f7ff fb87 bl 80005a4 8000e96: 4602 mov r2, r0 8000e98: 693b ldr r3, [r7, #16] 8000e9a: 1ad3 subs r3, r2, r3 8000e9c: 2b02 cmp r3, #2 8000e9e: d901 bls.n 8000ea4 { return HAL_TIMEOUT; 8000ea0: 2303 movs r3, #3 8000ea2: e06d b.n 8000f80 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 8000ea4: 4b29 ldr r3, [pc, #164] ; (8000f4c ) 8000ea6: 681b ldr r3, [r3, #0] 8000ea8: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 8000eac: 2b00 cmp r3, #0 8000eae: d1f0 bne.n 8000e92 } } /* Configure the HSE prediv factor --------------------------------*/ /* It can be written only when the PLL is disabled. Not used in PLL source is different than HSE */ if (RCC_OscInitStruct->PLL.PLLSource == RCC_PLLSOURCE_HSE) 8000eb0: 687b ldr r3, [r7, #4] 8000eb2: 6a1b ldr r3, [r3, #32] 8000eb4: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 8000eb8: d108 bne.n 8000ecc /* Set PREDIV1 source */ SET_BIT(RCC->CFGR2, RCC_OscInitStruct->Prediv1Source); #endif /* RCC_CFGR2_PREDIV1SRC */ /* Set PREDIV1 Value */ __HAL_RCC_HSE_PREDIV_CONFIG(RCC_OscInitStruct->HSEPredivValue); 8000eba: 4b24 ldr r3, [pc, #144] ; (8000f4c ) 8000ebc: 685b ldr r3, [r3, #4] 8000ebe: f423 3200 bic.w r2, r3, #131072 ; 0x20000 8000ec2: 687b ldr r3, [r7, #4] 8000ec4: 689b ldr r3, [r3, #8] 8000ec6: 4921 ldr r1, [pc, #132] ; (8000f4c ) 8000ec8: 4313 orrs r3, r2 8000eca: 604b str r3, [r1, #4] } /* Configure the main PLL clock source and multiplication factors. */ __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, 8000ecc: 4b1f ldr r3, [pc, #124] ; (8000f4c ) 8000ece: 685b ldr r3, [r3, #4] 8000ed0: f423 1274 bic.w r2, r3, #3997696 ; 0x3d0000 8000ed4: 687b ldr r3, [r7, #4] 8000ed6: 6a19 ldr r1, [r3, #32] 8000ed8: 687b ldr r3, [r7, #4] 8000eda: 6a5b ldr r3, [r3, #36] ; 0x24 8000edc: 430b orrs r3, r1 8000ede: 491b ldr r1, [pc, #108] ; (8000f4c ) 8000ee0: 4313 orrs r3, r2 8000ee2: 604b str r3, [r1, #4] RCC_OscInitStruct->PLL.PLLMUL); /* Enable the main PLL. */ __HAL_RCC_PLL_ENABLE(); 8000ee4: 4b1b ldr r3, [pc, #108] ; (8000f54 ) 8000ee6: 2201 movs r2, #1 8000ee8: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8000eea: f7ff fb5b bl 80005a4 8000eee: 6138 str r0, [r7, #16] /* Wait till PLL is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 8000ef0: e008 b.n 8000f04 { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 8000ef2: f7ff fb57 bl 80005a4 8000ef6: 4602 mov r2, r0 8000ef8: 693b ldr r3, [r7, #16] 8000efa: 1ad3 subs r3, r2, r3 8000efc: 2b02 cmp r3, #2 8000efe: d901 bls.n 8000f04 { return HAL_TIMEOUT; 8000f00: 2303 movs r3, #3 8000f02: e03d b.n 8000f80 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 8000f04: 4b11 ldr r3, [pc, #68] ; (8000f4c ) 8000f06: 681b ldr r3, [r3, #0] 8000f08: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 8000f0c: 2b00 cmp r3, #0 8000f0e: d0f0 beq.n 8000ef2 8000f10: e035 b.n 8000f7e } } else { /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 8000f12: 4b10 ldr r3, [pc, #64] ; (8000f54 ) 8000f14: 2200 movs r2, #0 8000f16: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8000f18: f7ff fb44 bl 80005a4 8000f1c: 6138 str r0, [r7, #16] /* Wait till PLL is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 8000f1e: e008 b.n 8000f32 { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 8000f20: f7ff fb40 bl 80005a4 8000f24: 4602 mov r2, r0 8000f26: 693b ldr r3, [r7, #16] 8000f28: 1ad3 subs r3, r2, r3 8000f2a: 2b02 cmp r3, #2 8000f2c: d901 bls.n 8000f32 { return HAL_TIMEOUT; 8000f2e: 2303 movs r3, #3 8000f30: e026 b.n 8000f80 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 8000f32: 4b06 ldr r3, [pc, #24] ; (8000f4c ) 8000f34: 681b ldr r3, [r3, #0] 8000f36: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 8000f3a: 2b00 cmp r3, #0 8000f3c: d1f0 bne.n 8000f20 8000f3e: e01e b.n 8000f7e } } else { /* Check if there is a request to disable the PLL used as System clock source */ if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) 8000f40: 687b ldr r3, [r7, #4] 8000f42: 69db ldr r3, [r3, #28] 8000f44: 2b01 cmp r3, #1 8000f46: d107 bne.n 8000f58 { return HAL_ERROR; 8000f48: 2301 movs r3, #1 8000f4a: e019 b.n 8000f80 8000f4c: 40021000 .word 0x40021000 8000f50: 40007000 .word 0x40007000 8000f54: 42420060 .word 0x42420060 } else { /* Do not return HAL_ERROR if request repeats the current configuration */ pll_config = RCC->CFGR; 8000f58: 4b0b ldr r3, [pc, #44] ; (8000f88 ) 8000f5a: 685b ldr r3, [r3, #4] 8000f5c: 60fb str r3, [r7, #12] if ((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 8000f5e: 68fb ldr r3, [r7, #12] 8000f60: f403 3280 and.w r2, r3, #65536 ; 0x10000 8000f64: 687b ldr r3, [r7, #4] 8000f66: 6a1b ldr r3, [r3, #32] 8000f68: 429a cmp r2, r3 8000f6a: d106 bne.n 8000f7a (READ_BIT(pll_config, RCC_CFGR_PLLMULL) != RCC_OscInitStruct->PLL.PLLMUL)) 8000f6c: 68fb ldr r3, [r7, #12] 8000f6e: f403 1270 and.w r2, r3, #3932160 ; 0x3c0000 8000f72: 687b ldr r3, [r7, #4] 8000f74: 6a5b ldr r3, [r3, #36] ; 0x24 if ((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 8000f76: 429a cmp r2, r3 8000f78: d001 beq.n 8000f7e { return HAL_ERROR; 8000f7a: 2301 movs r3, #1 8000f7c: e000 b.n 8000f80 } } } } return HAL_OK; 8000f7e: 2300 movs r3, #0 } 8000f80: 4618 mov r0, r3 8000f82: 3718 adds r7, #24 8000f84: 46bd mov sp, r7 8000f86: bd80 pop {r7, pc} 8000f88: 40021000 .word 0x40021000 08000f8c : * You can use @ref HAL_RCC_GetClockConfig() function to know which clock is * currently used as system clock source. * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) { 8000f8c: b580 push {r7, lr} 8000f8e: b084 sub sp, #16 8000f90: af00 add r7, sp, #0 8000f92: 6078 str r0, [r7, #4] 8000f94: 6039 str r1, [r7, #0] uint32_t tickstart; /* Check Null pointer */ if (RCC_ClkInitStruct == NULL) 8000f96: 687b ldr r3, [r7, #4] 8000f98: 2b00 cmp r3, #0 8000f9a: d101 bne.n 8000fa0 { return HAL_ERROR; 8000f9c: 2301 movs r3, #1 8000f9e: e0d0 b.n 8001142 must be correctly programmed according to the frequency of the CPU clock (HCLK) of the device. */ #if defined(FLASH_ACR_LATENCY) /* Increasing the number of wait states because of higher CPU frequency */ if (FLatency > __HAL_FLASH_GET_LATENCY()) 8000fa0: 4b6a ldr r3, [pc, #424] ; (800114c ) 8000fa2: 681b ldr r3, [r3, #0] 8000fa4: f003 0307 and.w r3, r3, #7 8000fa8: 683a ldr r2, [r7, #0] 8000faa: 429a cmp r2, r3 8000fac: d910 bls.n 8000fd0 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 8000fae: 4b67 ldr r3, [pc, #412] ; (800114c ) 8000fb0: 681b ldr r3, [r3, #0] 8000fb2: f023 0207 bic.w r2, r3, #7 8000fb6: 4965 ldr r1, [pc, #404] ; (800114c ) 8000fb8: 683b ldr r3, [r7, #0] 8000fba: 4313 orrs r3, r2 8000fbc: 600b str r3, [r1, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if (__HAL_FLASH_GET_LATENCY() != FLatency) 8000fbe: 4b63 ldr r3, [pc, #396] ; (800114c ) 8000fc0: 681b ldr r3, [r3, #0] 8000fc2: f003 0307 and.w r3, r3, #7 8000fc6: 683a ldr r2, [r7, #0] 8000fc8: 429a cmp r2, r3 8000fca: d001 beq.n 8000fd0 { return HAL_ERROR; 8000fcc: 2301 movs r3, #1 8000fce: e0b8 b.n 8001142 } } #endif /* FLASH_ACR_LATENCY */ /*-------------------------- HCLK Configuration --------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) 8000fd0: 687b ldr r3, [r7, #4] 8000fd2: 681b ldr r3, [r3, #0] 8000fd4: f003 0302 and.w r3, r3, #2 8000fd8: 2b00 cmp r3, #0 8000fda: d020 beq.n 800101e { /* Set the highest APBx dividers in order to ensure that we do not go through a non-spec phase whatever we decrease or increase HCLK. */ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 8000fdc: 687b ldr r3, [r7, #4] 8000fde: 681b ldr r3, [r3, #0] 8000fe0: f003 0304 and.w r3, r3, #4 8000fe4: 2b00 cmp r3, #0 8000fe6: d005 beq.n 8000ff4 { MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16); 8000fe8: 4b59 ldr r3, [pc, #356] ; (8001150 ) 8000fea: 685b ldr r3, [r3, #4] 8000fec: 4a58 ldr r2, [pc, #352] ; (8001150 ) 8000fee: f443 63e0 orr.w r3, r3, #1792 ; 0x700 8000ff2: 6053 str r3, [r2, #4] } if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 8000ff4: 687b ldr r3, [r7, #4] 8000ff6: 681b ldr r3, [r3, #0] 8000ff8: f003 0308 and.w r3, r3, #8 8000ffc: 2b00 cmp r3, #0 8000ffe: d005 beq.n 800100c { MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3)); 8001000: 4b53 ldr r3, [pc, #332] ; (8001150 ) 8001002: 685b ldr r3, [r3, #4] 8001004: 4a52 ldr r2, [pc, #328] ; (8001150 ) 8001006: f443 5360 orr.w r3, r3, #14336 ; 0x3800 800100a: 6053 str r3, [r2, #4] } /* Set the new HCLK clock divider */ assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); 800100c: 4b50 ldr r3, [pc, #320] ; (8001150 ) 800100e: 685b ldr r3, [r3, #4] 8001010: f023 02f0 bic.w r2, r3, #240 ; 0xf0 8001014: 687b ldr r3, [r7, #4] 8001016: 689b ldr r3, [r3, #8] 8001018: 494d ldr r1, [pc, #308] ; (8001150 ) 800101a: 4313 orrs r3, r2 800101c: 604b str r3, [r1, #4] } /*------------------------- SYSCLK Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) 800101e: 687b ldr r3, [r7, #4] 8001020: 681b ldr r3, [r3, #0] 8001022: f003 0301 and.w r3, r3, #1 8001026: 2b00 cmp r3, #0 8001028: d040 beq.n 80010ac { assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); /* HSE is selected as System Clock Source */ if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) 800102a: 687b ldr r3, [r7, #4] 800102c: 685b ldr r3, [r3, #4] 800102e: 2b01 cmp r3, #1 8001030: d107 bne.n 8001042 { /* Check the HSE ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 8001032: 4b47 ldr r3, [pc, #284] ; (8001150 ) 8001034: 681b ldr r3, [r3, #0] 8001036: f403 3300 and.w r3, r3, #131072 ; 0x20000 800103a: 2b00 cmp r3, #0 800103c: d115 bne.n 800106a { return HAL_ERROR; 800103e: 2301 movs r3, #1 8001040: e07f b.n 8001142 } } /* PLL is selected as System Clock Source */ else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) 8001042: 687b ldr r3, [r7, #4] 8001044: 685b ldr r3, [r3, #4] 8001046: 2b02 cmp r3, #2 8001048: d107 bne.n 800105a { /* Check the PLL ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 800104a: 4b41 ldr r3, [pc, #260] ; (8001150 ) 800104c: 681b ldr r3, [r3, #0] 800104e: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 8001052: 2b00 cmp r3, #0 8001054: d109 bne.n 800106a { return HAL_ERROR; 8001056: 2301 movs r3, #1 8001058: e073 b.n 8001142 } /* HSI is selected as System Clock Source */ else { /* Check the HSI ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 800105a: 4b3d ldr r3, [pc, #244] ; (8001150 ) 800105c: 681b ldr r3, [r3, #0] 800105e: f003 0302 and.w r3, r3, #2 8001062: 2b00 cmp r3, #0 8001064: d101 bne.n 800106a { return HAL_ERROR; 8001066: 2301 movs r3, #1 8001068: e06b b.n 8001142 } } __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource); 800106a: 4b39 ldr r3, [pc, #228] ; (8001150 ) 800106c: 685b ldr r3, [r3, #4] 800106e: f023 0203 bic.w r2, r3, #3 8001072: 687b ldr r3, [r7, #4] 8001074: 685b ldr r3, [r3, #4] 8001076: 4936 ldr r1, [pc, #216] ; (8001150 ) 8001078: 4313 orrs r3, r2 800107a: 604b str r3, [r1, #4] /* Get Start Tick */ tickstart = HAL_GetTick(); 800107c: f7ff fa92 bl 80005a4 8001080: 60f8 str r0, [r7, #12] while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 8001082: e00a b.n 800109a { if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) 8001084: f7ff fa8e bl 80005a4 8001088: 4602 mov r2, r0 800108a: 68fb ldr r3, [r7, #12] 800108c: 1ad3 subs r3, r2, r3 800108e: f241 3288 movw r2, #5000 ; 0x1388 8001092: 4293 cmp r3, r2 8001094: d901 bls.n 800109a { return HAL_TIMEOUT; 8001096: 2303 movs r3, #3 8001098: e053 b.n 8001142 while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 800109a: 4b2d ldr r3, [pc, #180] ; (8001150 ) 800109c: 685b ldr r3, [r3, #4] 800109e: f003 020c and.w r2, r3, #12 80010a2: 687b ldr r3, [r7, #4] 80010a4: 685b ldr r3, [r3, #4] 80010a6: 009b lsls r3, r3, #2 80010a8: 429a cmp r2, r3 80010aa: d1eb bne.n 8001084 } } #if defined(FLASH_ACR_LATENCY) /* Decreasing the number of wait states because of lower CPU frequency */ if (FLatency < __HAL_FLASH_GET_LATENCY()) 80010ac: 4b27 ldr r3, [pc, #156] ; (800114c ) 80010ae: 681b ldr r3, [r3, #0] 80010b0: f003 0307 and.w r3, r3, #7 80010b4: 683a ldr r2, [r7, #0] 80010b6: 429a cmp r2, r3 80010b8: d210 bcs.n 80010dc { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 80010ba: 4b24 ldr r3, [pc, #144] ; (800114c ) 80010bc: 681b ldr r3, [r3, #0] 80010be: f023 0207 bic.w r2, r3, #7 80010c2: 4922 ldr r1, [pc, #136] ; (800114c ) 80010c4: 683b ldr r3, [r7, #0] 80010c6: 4313 orrs r3, r2 80010c8: 600b str r3, [r1, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if (__HAL_FLASH_GET_LATENCY() != FLatency) 80010ca: 4b20 ldr r3, [pc, #128] ; (800114c ) 80010cc: 681b ldr r3, [r3, #0] 80010ce: f003 0307 and.w r3, r3, #7 80010d2: 683a ldr r2, [r7, #0] 80010d4: 429a cmp r2, r3 80010d6: d001 beq.n 80010dc { return HAL_ERROR; 80010d8: 2301 movs r3, #1 80010da: e032 b.n 8001142 } } #endif /* FLASH_ACR_LATENCY */ /*-------------------------- PCLK1 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 80010dc: 687b ldr r3, [r7, #4] 80010de: 681b ldr r3, [r3, #0] 80010e0: f003 0304 and.w r3, r3, #4 80010e4: 2b00 cmp r3, #0 80010e6: d008 beq.n 80010fa { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider); 80010e8: 4b19 ldr r3, [pc, #100] ; (8001150 ) 80010ea: 685b ldr r3, [r3, #4] 80010ec: f423 62e0 bic.w r2, r3, #1792 ; 0x700 80010f0: 687b ldr r3, [r7, #4] 80010f2: 68db ldr r3, [r3, #12] 80010f4: 4916 ldr r1, [pc, #88] ; (8001150 ) 80010f6: 4313 orrs r3, r2 80010f8: 604b str r3, [r1, #4] } /*-------------------------- PCLK2 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 80010fa: 687b ldr r3, [r7, #4] 80010fc: 681b ldr r3, [r3, #0] 80010fe: f003 0308 and.w r3, r3, #8 8001102: 2b00 cmp r3, #0 8001104: d009 beq.n 800111a { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3)); 8001106: 4b12 ldr r3, [pc, #72] ; (8001150 ) 8001108: 685b ldr r3, [r3, #4] 800110a: f423 5260 bic.w r2, r3, #14336 ; 0x3800 800110e: 687b ldr r3, [r7, #4] 8001110: 691b ldr r3, [r3, #16] 8001112: 00db lsls r3, r3, #3 8001114: 490e ldr r1, [pc, #56] ; (8001150 ) 8001116: 4313 orrs r3, r2 8001118: 604b str r3, [r1, #4] } /* Update the SystemCoreClock global variable */ SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]; 800111a: f000 f821 bl 8001160 800111e: 4602 mov r2, r0 8001120: 4b0b ldr r3, [pc, #44] ; (8001150 ) 8001122: 685b ldr r3, [r3, #4] 8001124: 091b lsrs r3, r3, #4 8001126: f003 030f and.w r3, r3, #15 800112a: 490a ldr r1, [pc, #40] ; (8001154 ) 800112c: 5ccb ldrb r3, [r1, r3] 800112e: fa22 f303 lsr.w r3, r2, r3 8001132: 4a09 ldr r2, [pc, #36] ; (8001158 ) 8001134: 6013 str r3, [r2, #0] /* Configure the source of time base considering new system clocks settings*/ HAL_InitTick(uwTickPrio); 8001136: 4b09 ldr r3, [pc, #36] ; (800115c ) 8001138: 681b ldr r3, [r3, #0] 800113a: 4618 mov r0, r3 800113c: f7ff f9f0 bl 8000520 return HAL_OK; 8001140: 2300 movs r3, #0 } 8001142: 4618 mov r0, r3 8001144: 3710 adds r7, #16 8001146: 46bd mov sp, r7 8001148: bd80 pop {r7, pc} 800114a: bf00 nop 800114c: 40022000 .word 0x40022000 8001150: 40021000 .word 0x40021000 8001154: 08001e74 .word 0x08001e74 8001158: 20000000 .word 0x20000000 800115c: 20000004 .word 0x20000004 08001160 : * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect. * * @retval SYSCLK frequency */ uint32_t HAL_RCC_GetSysClockFreq(void) { 8001160: b490 push {r4, r7} 8001162: b08a sub sp, #40 ; 0x28 8001164: af00 add r7, sp, #0 #if defined(RCC_CFGR2_PREDIV1SRC) const uint8_t aPLLMULFactorTable[14] = {0, 0, 4, 5, 6, 7, 8, 9, 0, 0, 0, 0, 0, 13}; const uint8_t aPredivFactorTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}; #else const uint8_t aPLLMULFactorTable[16] = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16}; 8001166: 4b29 ldr r3, [pc, #164] ; (800120c ) 8001168: 1d3c adds r4, r7, #4 800116a: cb0f ldmia r3, {r0, r1, r2, r3} 800116c: e884 000f stmia.w r4, {r0, r1, r2, r3} #if defined(RCC_CFGR2_PREDIV1) const uint8_t aPredivFactorTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}; #else const uint8_t aPredivFactorTable[2] = {1, 2}; 8001170: f240 2301 movw r3, #513 ; 0x201 8001174: 803b strh r3, [r7, #0] #endif /*RCC_CFGR2_PREDIV1*/ #endif uint32_t tmpreg = 0U, prediv = 0U, pllclk = 0U, pllmul = 0U; 8001176: 2300 movs r3, #0 8001178: 61fb str r3, [r7, #28] 800117a: 2300 movs r3, #0 800117c: 61bb str r3, [r7, #24] 800117e: 2300 movs r3, #0 8001180: 627b str r3, [r7, #36] ; 0x24 8001182: 2300 movs r3, #0 8001184: 617b str r3, [r7, #20] uint32_t sysclockfreq = 0U; 8001186: 2300 movs r3, #0 8001188: 623b str r3, [r7, #32] #if defined(RCC_CFGR2_PREDIV1SRC) uint32_t prediv2 = 0U, pll2mul = 0U; #endif /*RCC_CFGR2_PREDIV1SRC*/ tmpreg = RCC->CFGR; 800118a: 4b21 ldr r3, [pc, #132] ; (8001210 ) 800118c: 685b ldr r3, [r3, #4] 800118e: 61fb str r3, [r7, #28] /* Get SYSCLK source -------------------------------------------------------*/ switch (tmpreg & RCC_CFGR_SWS) 8001190: 69fb ldr r3, [r7, #28] 8001192: f003 030c and.w r3, r3, #12 8001196: 2b04 cmp r3, #4 8001198: d002 beq.n 80011a0 800119a: 2b08 cmp r3, #8 800119c: d003 beq.n 80011a6 800119e: e02b b.n 80011f8 { case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */ { sysclockfreq = HSE_VALUE; 80011a0: 4b1c ldr r3, [pc, #112] ; (8001214 ) 80011a2: 623b str r3, [r7, #32] break; 80011a4: e02b b.n 80011fe } case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */ { pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos]; 80011a6: 69fb ldr r3, [r7, #28] 80011a8: 0c9b lsrs r3, r3, #18 80011aa: f003 030f and.w r3, r3, #15 80011ae: 3328 adds r3, #40 ; 0x28 80011b0: 443b add r3, r7 80011b2: f813 3c24 ldrb.w r3, [r3, #-36] 80011b6: 617b str r3, [r7, #20] if ((tmpreg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2) 80011b8: 69fb ldr r3, [r7, #28] 80011ba: f403 3380 and.w r3, r3, #65536 ; 0x10000 80011be: 2b00 cmp r3, #0 80011c0: d012 beq.n 80011e8 { #if defined(RCC_CFGR2_PREDIV1) prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> RCC_CFGR2_PREDIV1_Pos]; #else prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos]; 80011c2: 4b13 ldr r3, [pc, #76] ; (8001210 ) 80011c4: 685b ldr r3, [r3, #4] 80011c6: 0c5b lsrs r3, r3, #17 80011c8: f003 0301 and.w r3, r3, #1 80011cc: 3328 adds r3, #40 ; 0x28 80011ce: 443b add r3, r7 80011d0: f813 3c28 ldrb.w r3, [r3, #-40] 80011d4: 61bb str r3, [r7, #24] { pllclk = pllclk / 2; } #else /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */ pllclk = (uint32_t)((HSE_VALUE * pllmul) / prediv); 80011d6: 697b ldr r3, [r7, #20] 80011d8: 4a0e ldr r2, [pc, #56] ; (8001214 ) 80011da: fb03 f202 mul.w r2, r3, r2 80011de: 69bb ldr r3, [r7, #24] 80011e0: fbb2 f3f3 udiv r3, r2, r3 80011e4: 627b str r3, [r7, #36] ; 0x24 80011e6: e004 b.n 80011f2 #endif /*RCC_CFGR2_PREDIV1SRC*/ } else { /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */ pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul); 80011e8: 697b ldr r3, [r7, #20] 80011ea: 4a0b ldr r2, [pc, #44] ; (8001218 ) 80011ec: fb02 f303 mul.w r3, r2, r3 80011f0: 627b str r3, [r7, #36] ; 0x24 } sysclockfreq = pllclk; 80011f2: 6a7b ldr r3, [r7, #36] ; 0x24 80011f4: 623b str r3, [r7, #32] break; 80011f6: e002 b.n 80011fe } case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */ default: /* HSI used as system clock */ { sysclockfreq = HSI_VALUE; 80011f8: 4b06 ldr r3, [pc, #24] ; (8001214 ) 80011fa: 623b str r3, [r7, #32] break; 80011fc: bf00 nop } } return sysclockfreq; 80011fe: 6a3b ldr r3, [r7, #32] } 8001200: 4618 mov r0, r3 8001202: 3728 adds r7, #40 ; 0x28 8001204: 46bd mov sp, r7 8001206: bc90 pop {r4, r7} 8001208: 4770 bx lr 800120a: bf00 nop 800120c: 08001e64 .word 0x08001e64 8001210: 40021000 .word 0x40021000 8001214: 007a1200 .word 0x007a1200 8001218: 003d0900 .word 0x003d0900 0800121c : * @brief This function provides delay (in milliseconds) based on CPU cycles method. * @param mdelay: specifies the delay time length, in milliseconds. * @retval None */ static void RCC_Delay(uint32_t mdelay) { 800121c: b480 push {r7} 800121e: b085 sub sp, #20 8001220: af00 add r7, sp, #0 8001222: 6078 str r0, [r7, #4] __IO uint32_t Delay = mdelay * (SystemCoreClock / 8U / 1000U); 8001224: 4b0a ldr r3, [pc, #40] ; (8001250 ) 8001226: 681b ldr r3, [r3, #0] 8001228: 4a0a ldr r2, [pc, #40] ; (8001254 ) 800122a: fba2 2303 umull r2, r3, r2, r3 800122e: 0a5b lsrs r3, r3, #9 8001230: 687a ldr r2, [r7, #4] 8001232: fb02 f303 mul.w r3, r2, r3 8001236: 60fb str r3, [r7, #12] do { __NOP(); 8001238: bf00 nop } while (Delay --); 800123a: 68fb ldr r3, [r7, #12] 800123c: 1e5a subs r2, r3, #1 800123e: 60fa str r2, [r7, #12] 8001240: 2b00 cmp r3, #0 8001242: d1f9 bne.n 8001238 } 8001244: bf00 nop 8001246: bf00 nop 8001248: 3714 adds r7, #20 800124a: 46bd mov sp, r7 800124c: bc80 pop {r7} 800124e: 4770 bx lr 8001250: 20000000 .word 0x20000000 8001254: 10624dd3 .word 0x10624dd3 08001258 : * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init() * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) { 8001258: b580 push {r7, lr} 800125a: b082 sub sp, #8 800125c: af00 add r7, sp, #0 800125e: 6078 str r0, [r7, #4] /* Check the TIM handle allocation */ if (htim == NULL) 8001260: 687b ldr r3, [r7, #4] 8001262: 2b00 cmp r3, #0 8001264: d101 bne.n 800126a { return HAL_ERROR; 8001266: 2301 movs r3, #1 8001268: e041 b.n 80012ee assert_param(IS_TIM_INSTANCE(htim->Instance)); assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) 800126a: 687b ldr r3, [r7, #4] 800126c: f893 303d ldrb.w r3, [r3, #61] ; 0x3d 8001270: b2db uxtb r3, r3 8001272: 2b00 cmp r3, #0 8001274: d106 bne.n 8001284 { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; 8001276: 687b ldr r3, [r7, #4] 8001278: 2200 movs r2, #0 800127a: f883 203c strb.w r2, [r3, #60] ; 0x3c } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->Base_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC */ HAL_TIM_Base_MspInit(htim); 800127e: 6878 ldr r0, [r7, #4] 8001280: f7ff f8c6 bl 8000410 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 8001284: 687b ldr r3, [r7, #4] 8001286: 2202 movs r2, #2 8001288: f883 203d strb.w r2, [r3, #61] ; 0x3d /* Set the Time Base configuration */ TIM_Base_SetConfig(htim->Instance, &htim->Init); 800128c: 687b ldr r3, [r7, #4] 800128e: 681a ldr r2, [r3, #0] 8001290: 687b ldr r3, [r7, #4] 8001292: 3304 adds r3, #4 8001294: 4619 mov r1, r3 8001296: 4610 mov r0, r2 8001298: f000 faaa bl 80017f0 /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; 800129c: 687b ldr r3, [r7, #4] 800129e: 2201 movs r2, #1 80012a0: f883 2046 strb.w r2, [r3, #70] ; 0x46 /* Initialize the TIM channels state */ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 80012a4: 687b ldr r3, [r7, #4] 80012a6: 2201 movs r2, #1 80012a8: f883 203e strb.w r2, [r3, #62] ; 0x3e 80012ac: 687b ldr r3, [r7, #4] 80012ae: 2201 movs r2, #1 80012b0: f883 203f strb.w r2, [r3, #63] ; 0x3f 80012b4: 687b ldr r3, [r7, #4] 80012b6: 2201 movs r2, #1 80012b8: f883 2040 strb.w r2, [r3, #64] ; 0x40 80012bc: 687b ldr r3, [r7, #4] 80012be: 2201 movs r2, #1 80012c0: f883 2041 strb.w r2, [r3, #65] ; 0x41 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 80012c4: 687b ldr r3, [r7, #4] 80012c6: 2201 movs r2, #1 80012c8: f883 2042 strb.w r2, [r3, #66] ; 0x42 80012cc: 687b ldr r3, [r7, #4] 80012ce: 2201 movs r2, #1 80012d0: f883 2043 strb.w r2, [r3, #67] ; 0x43 80012d4: 687b ldr r3, [r7, #4] 80012d6: 2201 movs r2, #1 80012d8: f883 2044 strb.w r2, [r3, #68] ; 0x44 80012dc: 687b ldr r3, [r7, #4] 80012de: 2201 movs r2, #1 80012e0: f883 2045 strb.w r2, [r3, #69] ; 0x45 /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; 80012e4: 687b ldr r3, [r7, #4] 80012e6: 2201 movs r2, #1 80012e8: f883 203d strb.w r2, [r3, #61] ; 0x3d return HAL_OK; 80012ec: 2300 movs r3, #0 } 80012ee: 4618 mov r0, r3 80012f0: 3708 adds r7, #8 80012f2: 46bd mov sp, r7 80012f4: bd80 pop {r7, pc} 080012f6 : * Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init() * @param htim TIM PWM handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) { 80012f6: b580 push {r7, lr} 80012f8: b082 sub sp, #8 80012fa: af00 add r7, sp, #0 80012fc: 6078 str r0, [r7, #4] /* Check the TIM handle allocation */ if (htim == NULL) 80012fe: 687b ldr r3, [r7, #4] 8001300: 2b00 cmp r3, #0 8001302: d101 bne.n 8001308 { return HAL_ERROR; 8001304: 2301 movs r3, #1 8001306: e041 b.n 800138c assert_param(IS_TIM_INSTANCE(htim->Instance)); assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) 8001308: 687b ldr r3, [r7, #4] 800130a: f893 303d ldrb.w r3, [r3, #61] ; 0x3d 800130e: b2db uxtb r3, r3 8001310: 2b00 cmp r3, #0 8001312: d106 bne.n 8001322 { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; 8001314: 687b ldr r3, [r7, #4] 8001316: 2200 movs r2, #0 8001318: f883 203c strb.w r2, [r3, #60] ; 0x3c } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->PWM_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_TIM_PWM_MspInit(htim); 800131c: 6878 ldr r0, [r7, #4] 800131e: f000 f839 bl 8001394 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 8001322: 687b ldr r3, [r7, #4] 8001324: 2202 movs r2, #2 8001326: f883 203d strb.w r2, [r3, #61] ; 0x3d /* Init the base time for the PWM */ TIM_Base_SetConfig(htim->Instance, &htim->Init); 800132a: 687b ldr r3, [r7, #4] 800132c: 681a ldr r2, [r3, #0] 800132e: 687b ldr r3, [r7, #4] 8001330: 3304 adds r3, #4 8001332: 4619 mov r1, r3 8001334: 4610 mov r0, r2 8001336: f000 fa5b bl 80017f0 /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; 800133a: 687b ldr r3, [r7, #4] 800133c: 2201 movs r2, #1 800133e: f883 2046 strb.w r2, [r3, #70] ; 0x46 /* Initialize the TIM channels state */ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 8001342: 687b ldr r3, [r7, #4] 8001344: 2201 movs r2, #1 8001346: f883 203e strb.w r2, [r3, #62] ; 0x3e 800134a: 687b ldr r3, [r7, #4] 800134c: 2201 movs r2, #1 800134e: f883 203f strb.w r2, [r3, #63] ; 0x3f 8001352: 687b ldr r3, [r7, #4] 8001354: 2201 movs r2, #1 8001356: f883 2040 strb.w r2, [r3, #64] ; 0x40 800135a: 687b ldr r3, [r7, #4] 800135c: 2201 movs r2, #1 800135e: f883 2041 strb.w r2, [r3, #65] ; 0x41 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 8001362: 687b ldr r3, [r7, #4] 8001364: 2201 movs r2, #1 8001366: f883 2042 strb.w r2, [r3, #66] ; 0x42 800136a: 687b ldr r3, [r7, #4] 800136c: 2201 movs r2, #1 800136e: f883 2043 strb.w r2, [r3, #67] ; 0x43 8001372: 687b ldr r3, [r7, #4] 8001374: 2201 movs r2, #1 8001376: f883 2044 strb.w r2, [r3, #68] ; 0x44 800137a: 687b ldr r3, [r7, #4] 800137c: 2201 movs r2, #1 800137e: f883 2045 strb.w r2, [r3, #69] ; 0x45 /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; 8001382: 687b ldr r3, [r7, #4] 8001384: 2201 movs r2, #1 8001386: f883 203d strb.w r2, [r3, #61] ; 0x3d return HAL_OK; 800138a: 2300 movs r3, #0 } 800138c: 4618 mov r0, r3 800138e: 3708 adds r7, #8 8001390: 46bd mov sp, r7 8001392: bd80 pop {r7, pc} 08001394 : * @brief Initializes the TIM PWM MSP. * @param htim TIM PWM handle * @retval None */ __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim) { 8001394: b480 push {r7} 8001396: b083 sub sp, #12 8001398: af00 add r7, sp, #0 800139a: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_PWM_MspInit could be implemented in the user file */ } 800139c: bf00 nop 800139e: 370c adds r7, #12 80013a0: 46bd mov sp, r7 80013a2: bc80 pop {r7} 80013a4: 4770 bx lr ... 080013a8 : * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel) { 80013a8: b580 push {r7, lr} 80013aa: b084 sub sp, #16 80013ac: af00 add r7, sp, #0 80013ae: 6078 str r0, [r7, #4] 80013b0: 6039 str r1, [r7, #0] /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); /* Check the TIM channel state */ if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) 80013b2: 683b ldr r3, [r7, #0] 80013b4: 2b00 cmp r3, #0 80013b6: d109 bne.n 80013cc 80013b8: 687b ldr r3, [r7, #4] 80013ba: f893 303e ldrb.w r3, [r3, #62] ; 0x3e 80013be: b2db uxtb r3, r3 80013c0: 2b01 cmp r3, #1 80013c2: bf14 ite ne 80013c4: 2301 movne r3, #1 80013c6: 2300 moveq r3, #0 80013c8: b2db uxtb r3, r3 80013ca: e022 b.n 8001412 80013cc: 683b ldr r3, [r7, #0] 80013ce: 2b04 cmp r3, #4 80013d0: d109 bne.n 80013e6 80013d2: 687b ldr r3, [r7, #4] 80013d4: f893 303f ldrb.w r3, [r3, #63] ; 0x3f 80013d8: b2db uxtb r3, r3 80013da: 2b01 cmp r3, #1 80013dc: bf14 ite ne 80013de: 2301 movne r3, #1 80013e0: 2300 moveq r3, #0 80013e2: b2db uxtb r3, r3 80013e4: e015 b.n 8001412 80013e6: 683b ldr r3, [r7, #0] 80013e8: 2b08 cmp r3, #8 80013ea: d109 bne.n 8001400 80013ec: 687b ldr r3, [r7, #4] 80013ee: f893 3040 ldrb.w r3, [r3, #64] ; 0x40 80013f2: b2db uxtb r3, r3 80013f4: 2b01 cmp r3, #1 80013f6: bf14 ite ne 80013f8: 2301 movne r3, #1 80013fa: 2300 moveq r3, #0 80013fc: b2db uxtb r3, r3 80013fe: e008 b.n 8001412 8001400: 687b ldr r3, [r7, #4] 8001402: f893 3041 ldrb.w r3, [r3, #65] ; 0x41 8001406: b2db uxtb r3, r3 8001408: 2b01 cmp r3, #1 800140a: bf14 ite ne 800140c: 2301 movne r3, #1 800140e: 2300 moveq r3, #0 8001410: b2db uxtb r3, r3 8001412: 2b00 cmp r3, #0 8001414: d001 beq.n 800141a { return HAL_ERROR; 8001416: 2301 movs r3, #1 8001418: e05e b.n 80014d8 } /* Set the TIM channel state */ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); 800141a: 683b ldr r3, [r7, #0] 800141c: 2b00 cmp r3, #0 800141e: d104 bne.n 800142a 8001420: 687b ldr r3, [r7, #4] 8001422: 2202 movs r2, #2 8001424: f883 203e strb.w r2, [r3, #62] ; 0x3e 8001428: e013 b.n 8001452 800142a: 683b ldr r3, [r7, #0] 800142c: 2b04 cmp r3, #4 800142e: d104 bne.n 800143a 8001430: 687b ldr r3, [r7, #4] 8001432: 2202 movs r2, #2 8001434: f883 203f strb.w r2, [r3, #63] ; 0x3f 8001438: e00b b.n 8001452 800143a: 683b ldr r3, [r7, #0] 800143c: 2b08 cmp r3, #8 800143e: d104 bne.n 800144a 8001440: 687b ldr r3, [r7, #4] 8001442: 2202 movs r2, #2 8001444: f883 2040 strb.w r2, [r3, #64] ; 0x40 8001448: e003 b.n 8001452 800144a: 687b ldr r3, [r7, #4] 800144c: 2202 movs r2, #2 800144e: f883 2041 strb.w r2, [r3, #65] ; 0x41 /* Enable the Capture compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); 8001452: 687b ldr r3, [r7, #4] 8001454: 681b ldr r3, [r3, #0] 8001456: 2201 movs r2, #1 8001458: 6839 ldr r1, [r7, #0] 800145a: 4618 mov r0, r3 800145c: f000 fc48 bl 8001cf0 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) 8001460: 687b ldr r3, [r7, #4] 8001462: 681b ldr r3, [r3, #0] 8001464: 4a1e ldr r2, [pc, #120] ; (80014e0 ) 8001466: 4293 cmp r3, r2 8001468: d107 bne.n 800147a { /* Enable the main output */ __HAL_TIM_MOE_ENABLE(htim); 800146a: 687b ldr r3, [r7, #4] 800146c: 681b ldr r3, [r3, #0] 800146e: 6c5a ldr r2, [r3, #68] ; 0x44 8001470: 687b ldr r3, [r7, #4] 8001472: 681b ldr r3, [r3, #0] 8001474: f442 4200 orr.w r2, r2, #32768 ; 0x8000 8001478: 645a str r2, [r3, #68] ; 0x44 } /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 800147a: 687b ldr r3, [r7, #4] 800147c: 681b ldr r3, [r3, #0] 800147e: 4a18 ldr r2, [pc, #96] ; (80014e0 ) 8001480: 4293 cmp r3, r2 8001482: d00e beq.n 80014a2 8001484: 687b ldr r3, [r7, #4] 8001486: 681b ldr r3, [r3, #0] 8001488: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000 800148c: d009 beq.n 80014a2 800148e: 687b ldr r3, [r7, #4] 8001490: 681b ldr r3, [r3, #0] 8001492: 4a14 ldr r2, [pc, #80] ; (80014e4 ) 8001494: 4293 cmp r3, r2 8001496: d004 beq.n 80014a2 8001498: 687b ldr r3, [r7, #4] 800149a: 681b ldr r3, [r3, #0] 800149c: 4a12 ldr r2, [pc, #72] ; (80014e8 ) 800149e: 4293 cmp r3, r2 80014a0: d111 bne.n 80014c6 { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; 80014a2: 687b ldr r3, [r7, #4] 80014a4: 681b ldr r3, [r3, #0] 80014a6: 689b ldr r3, [r3, #8] 80014a8: f003 0307 and.w r3, r3, #7 80014ac: 60fb str r3, [r7, #12] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 80014ae: 68fb ldr r3, [r7, #12] 80014b0: 2b06 cmp r3, #6 80014b2: d010 beq.n 80014d6 { __HAL_TIM_ENABLE(htim); 80014b4: 687b ldr r3, [r7, #4] 80014b6: 681b ldr r3, [r3, #0] 80014b8: 681a ldr r2, [r3, #0] 80014ba: 687b ldr r3, [r7, #4] 80014bc: 681b ldr r3, [r3, #0] 80014be: f042 0201 orr.w r2, r2, #1 80014c2: 601a str r2, [r3, #0] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 80014c4: e007 b.n 80014d6 } } else { __HAL_TIM_ENABLE(htim); 80014c6: 687b ldr r3, [r7, #4] 80014c8: 681b ldr r3, [r3, #0] 80014ca: 681a ldr r2, [r3, #0] 80014cc: 687b ldr r3, [r7, #4] 80014ce: 681b ldr r3, [r3, #0] 80014d0: f042 0201 orr.w r2, r2, #1 80014d4: 601a str r2, [r3, #0] } /* Return function status */ return HAL_OK; 80014d6: 2300 movs r3, #0 } 80014d8: 4618 mov r0, r3 80014da: 3710 adds r7, #16 80014dc: 46bd mov sp, r7 80014de: bd80 pop {r7, pc} 80014e0: 40012c00 .word 0x40012c00 80014e4: 40000400 .word 0x40000400 80014e8: 40000800 .word 0x40000800 080014ec : * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel) { 80014ec: b580 push {r7, lr} 80014ee: b084 sub sp, #16 80014f0: af00 add r7, sp, #0 80014f2: 60f8 str r0, [r7, #12] 80014f4: 60b9 str r1, [r7, #8] 80014f6: 607a str r2, [r7, #4] assert_param(IS_TIM_PWM_MODE(sConfig->OCMode)); assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode)); /* Process Locked */ __HAL_LOCK(htim); 80014f8: 68fb ldr r3, [r7, #12] 80014fa: f893 303c ldrb.w r3, [r3, #60] ; 0x3c 80014fe: 2b01 cmp r3, #1 8001500: d101 bne.n 8001506 8001502: 2302 movs r3, #2 8001504: e0ac b.n 8001660 8001506: 68fb ldr r3, [r7, #12] 8001508: 2201 movs r2, #1 800150a: f883 203c strb.w r2, [r3, #60] ; 0x3c switch (Channel) 800150e: 687b ldr r3, [r7, #4] 8001510: 2b0c cmp r3, #12 8001512: f200 809f bhi.w 8001654 8001516: a201 add r2, pc, #4 ; (adr r2, 800151c ) 8001518: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800151c: 08001551 .word 0x08001551 8001520: 08001655 .word 0x08001655 8001524: 08001655 .word 0x08001655 8001528: 08001655 .word 0x08001655 800152c: 08001591 .word 0x08001591 8001530: 08001655 .word 0x08001655 8001534: 08001655 .word 0x08001655 8001538: 08001655 .word 0x08001655 800153c: 080015d3 .word 0x080015d3 8001540: 08001655 .word 0x08001655 8001544: 08001655 .word 0x08001655 8001548: 08001655 .word 0x08001655 800154c: 08001613 .word 0x08001613 { /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); /* Configure the Channel 1 in PWM mode */ TIM_OC1_SetConfig(htim->Instance, sConfig); 8001550: 68fb ldr r3, [r7, #12] 8001552: 681b ldr r3, [r3, #0] 8001554: 68b9 ldr r1, [r7, #8] 8001556: 4618 mov r0, r3 8001558: f000 f9ac bl 80018b4 /* Set the Preload enable bit for channel1 */ htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE; 800155c: 68fb ldr r3, [r7, #12] 800155e: 681b ldr r3, [r3, #0] 8001560: 699a ldr r2, [r3, #24] 8001562: 68fb ldr r3, [r7, #12] 8001564: 681b ldr r3, [r3, #0] 8001566: f042 0208 orr.w r2, r2, #8 800156a: 619a str r2, [r3, #24] /* Configure the Output Fast mode */ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE; 800156c: 68fb ldr r3, [r7, #12] 800156e: 681b ldr r3, [r3, #0] 8001570: 699a ldr r2, [r3, #24] 8001572: 68fb ldr r3, [r7, #12] 8001574: 681b ldr r3, [r3, #0] 8001576: f022 0204 bic.w r2, r2, #4 800157a: 619a str r2, [r3, #24] htim->Instance->CCMR1 |= sConfig->OCFastMode; 800157c: 68fb ldr r3, [r7, #12] 800157e: 681b ldr r3, [r3, #0] 8001580: 6999 ldr r1, [r3, #24] 8001582: 68bb ldr r3, [r7, #8] 8001584: 691a ldr r2, [r3, #16] 8001586: 68fb ldr r3, [r7, #12] 8001588: 681b ldr r3, [r3, #0] 800158a: 430a orrs r2, r1 800158c: 619a str r2, [r3, #24] break; 800158e: e062 b.n 8001656 { /* Check the parameters */ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); /* Configure the Channel 2 in PWM mode */ TIM_OC2_SetConfig(htim->Instance, sConfig); 8001590: 68fb ldr r3, [r7, #12] 8001592: 681b ldr r3, [r3, #0] 8001594: 68b9 ldr r1, [r7, #8] 8001596: 4618 mov r0, r3 8001598: f000 f9f2 bl 8001980 /* Set the Preload enable bit for channel2 */ htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE; 800159c: 68fb ldr r3, [r7, #12] 800159e: 681b ldr r3, [r3, #0] 80015a0: 699a ldr r2, [r3, #24] 80015a2: 68fb ldr r3, [r7, #12] 80015a4: 681b ldr r3, [r3, #0] 80015a6: f442 6200 orr.w r2, r2, #2048 ; 0x800 80015aa: 619a str r2, [r3, #24] /* Configure the Output Fast mode */ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE; 80015ac: 68fb ldr r3, [r7, #12] 80015ae: 681b ldr r3, [r3, #0] 80015b0: 699a ldr r2, [r3, #24] 80015b2: 68fb ldr r3, [r7, #12] 80015b4: 681b ldr r3, [r3, #0] 80015b6: f422 6280 bic.w r2, r2, #1024 ; 0x400 80015ba: 619a str r2, [r3, #24] htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U; 80015bc: 68fb ldr r3, [r7, #12] 80015be: 681b ldr r3, [r3, #0] 80015c0: 6999 ldr r1, [r3, #24] 80015c2: 68bb ldr r3, [r7, #8] 80015c4: 691b ldr r3, [r3, #16] 80015c6: 021a lsls r2, r3, #8 80015c8: 68fb ldr r3, [r7, #12] 80015ca: 681b ldr r3, [r3, #0] 80015cc: 430a orrs r2, r1 80015ce: 619a str r2, [r3, #24] break; 80015d0: e041 b.n 8001656 { /* Check the parameters */ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); /* Configure the Channel 3 in PWM mode */ TIM_OC3_SetConfig(htim->Instance, sConfig); 80015d2: 68fb ldr r3, [r7, #12] 80015d4: 681b ldr r3, [r3, #0] 80015d6: 68b9 ldr r1, [r7, #8] 80015d8: 4618 mov r0, r3 80015da: f000 fa3b bl 8001a54 /* Set the Preload enable bit for channel3 */ htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE; 80015de: 68fb ldr r3, [r7, #12] 80015e0: 681b ldr r3, [r3, #0] 80015e2: 69da ldr r2, [r3, #28] 80015e4: 68fb ldr r3, [r7, #12] 80015e6: 681b ldr r3, [r3, #0] 80015e8: f042 0208 orr.w r2, r2, #8 80015ec: 61da str r2, [r3, #28] /* Configure the Output Fast mode */ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE; 80015ee: 68fb ldr r3, [r7, #12] 80015f0: 681b ldr r3, [r3, #0] 80015f2: 69da ldr r2, [r3, #28] 80015f4: 68fb ldr r3, [r7, #12] 80015f6: 681b ldr r3, [r3, #0] 80015f8: f022 0204 bic.w r2, r2, #4 80015fc: 61da str r2, [r3, #28] htim->Instance->CCMR2 |= sConfig->OCFastMode; 80015fe: 68fb ldr r3, [r7, #12] 8001600: 681b ldr r3, [r3, #0] 8001602: 69d9 ldr r1, [r3, #28] 8001604: 68bb ldr r3, [r7, #8] 8001606: 691a ldr r2, [r3, #16] 8001608: 68fb ldr r3, [r7, #12] 800160a: 681b ldr r3, [r3, #0] 800160c: 430a orrs r2, r1 800160e: 61da str r2, [r3, #28] break; 8001610: e021 b.n 8001656 { /* Check the parameters */ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); /* Configure the Channel 4 in PWM mode */ TIM_OC4_SetConfig(htim->Instance, sConfig); 8001612: 68fb ldr r3, [r7, #12] 8001614: 681b ldr r3, [r3, #0] 8001616: 68b9 ldr r1, [r7, #8] 8001618: 4618 mov r0, r3 800161a: f000 fa85 bl 8001b28 /* Set the Preload enable bit for channel4 */ htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE; 800161e: 68fb ldr r3, [r7, #12] 8001620: 681b ldr r3, [r3, #0] 8001622: 69da ldr r2, [r3, #28] 8001624: 68fb ldr r3, [r7, #12] 8001626: 681b ldr r3, [r3, #0] 8001628: f442 6200 orr.w r2, r2, #2048 ; 0x800 800162c: 61da str r2, [r3, #28] /* Configure the Output Fast mode */ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE; 800162e: 68fb ldr r3, [r7, #12] 8001630: 681b ldr r3, [r3, #0] 8001632: 69da ldr r2, [r3, #28] 8001634: 68fb ldr r3, [r7, #12] 8001636: 681b ldr r3, [r3, #0] 8001638: f422 6280 bic.w r2, r2, #1024 ; 0x400 800163c: 61da str r2, [r3, #28] htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U; 800163e: 68fb ldr r3, [r7, #12] 8001640: 681b ldr r3, [r3, #0] 8001642: 69d9 ldr r1, [r3, #28] 8001644: 68bb ldr r3, [r7, #8] 8001646: 691b ldr r3, [r3, #16] 8001648: 021a lsls r2, r3, #8 800164a: 68fb ldr r3, [r7, #12] 800164c: 681b ldr r3, [r3, #0] 800164e: 430a orrs r2, r1 8001650: 61da str r2, [r3, #28] break; 8001652: e000 b.n 8001656 } default: break; 8001654: bf00 nop } __HAL_UNLOCK(htim); 8001656: 68fb ldr r3, [r7, #12] 8001658: 2200 movs r2, #0 800165a: f883 203c strb.w r2, [r3, #60] ; 0x3c return HAL_OK; 800165e: 2300 movs r3, #0 } 8001660: 4618 mov r0, r3 8001662: 3710 adds r7, #16 8001664: 46bd mov sp, r7 8001666: bd80 pop {r7, pc} 08001668 : * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that * contains the clock source information for the TIM peripheral. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig) { 8001668: b580 push {r7, lr} 800166a: b084 sub sp, #16 800166c: af00 add r7, sp, #0 800166e: 6078 str r0, [r7, #4] 8001670: 6039 str r1, [r7, #0] uint32_t tmpsmcr; /* Process Locked */ __HAL_LOCK(htim); 8001672: 687b ldr r3, [r7, #4] 8001674: f893 303c ldrb.w r3, [r3, #60] ; 0x3c 8001678: 2b01 cmp r3, #1 800167a: d101 bne.n 8001680 800167c: 2302 movs r3, #2 800167e: e0b3 b.n 80017e8 8001680: 687b ldr r3, [r7, #4] 8001682: 2201 movs r2, #1 8001684: f883 203c strb.w r2, [r3, #60] ; 0x3c htim->State = HAL_TIM_STATE_BUSY; 8001688: 687b ldr r3, [r7, #4] 800168a: 2202 movs r2, #2 800168c: f883 203d strb.w r2, [r3, #61] ; 0x3d /* Check the parameters */ assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource)); /* Reset the SMS, TS, ECE, ETPS and ETRF bits */ tmpsmcr = htim->Instance->SMCR; 8001690: 687b ldr r3, [r7, #4] 8001692: 681b ldr r3, [r3, #0] 8001694: 689b ldr r3, [r3, #8] 8001696: 60fb str r3, [r7, #12] tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS); 8001698: 68fb ldr r3, [r7, #12] 800169a: f023 0377 bic.w r3, r3, #119 ; 0x77 800169e: 60fb str r3, [r7, #12] tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); 80016a0: 68fb ldr r3, [r7, #12] 80016a2: f423 437f bic.w r3, r3, #65280 ; 0xff00 80016a6: 60fb str r3, [r7, #12] htim->Instance->SMCR = tmpsmcr; 80016a8: 687b ldr r3, [r7, #4] 80016aa: 681b ldr r3, [r3, #0] 80016ac: 68fa ldr r2, [r7, #12] 80016ae: 609a str r2, [r3, #8] switch (sClockSourceConfig->ClockSource) 80016b0: 683b ldr r3, [r7, #0] 80016b2: 681b ldr r3, [r3, #0] 80016b4: f5b3 5f00 cmp.w r3, #8192 ; 0x2000 80016b8: d03e beq.n 8001738 80016ba: f5b3 5f00 cmp.w r3, #8192 ; 0x2000 80016be: f200 8087 bhi.w 80017d0 80016c2: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 80016c6: f000 8085 beq.w 80017d4 80016ca: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 80016ce: d87f bhi.n 80017d0 80016d0: 2b70 cmp r3, #112 ; 0x70 80016d2: d01a beq.n 800170a 80016d4: 2b70 cmp r3, #112 ; 0x70 80016d6: d87b bhi.n 80017d0 80016d8: 2b60 cmp r3, #96 ; 0x60 80016da: d050 beq.n 800177e 80016dc: 2b60 cmp r3, #96 ; 0x60 80016de: d877 bhi.n 80017d0 80016e0: 2b50 cmp r3, #80 ; 0x50 80016e2: d03c beq.n 800175e 80016e4: 2b50 cmp r3, #80 ; 0x50 80016e6: d873 bhi.n 80017d0 80016e8: 2b40 cmp r3, #64 ; 0x40 80016ea: d058 beq.n 800179e 80016ec: 2b40 cmp r3, #64 ; 0x40 80016ee: d86f bhi.n 80017d0 80016f0: 2b30 cmp r3, #48 ; 0x30 80016f2: d064 beq.n 80017be 80016f4: 2b30 cmp r3, #48 ; 0x30 80016f6: d86b bhi.n 80017d0 80016f8: 2b20 cmp r3, #32 80016fa: d060 beq.n 80017be 80016fc: 2b20 cmp r3, #32 80016fe: d867 bhi.n 80017d0 8001700: 2b00 cmp r3, #0 8001702: d05c beq.n 80017be 8001704: 2b10 cmp r3, #16 8001706: d05a beq.n 80017be TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource); break; } default: break; 8001708: e062 b.n 80017d0 TIM_ETR_SetConfig(htim->Instance, 800170a: 687b ldr r3, [r7, #4] 800170c: 6818 ldr r0, [r3, #0] 800170e: 683b ldr r3, [r7, #0] 8001710: 6899 ldr r1, [r3, #8] 8001712: 683b ldr r3, [r7, #0] 8001714: 685a ldr r2, [r3, #4] 8001716: 683b ldr r3, [r7, #0] 8001718: 68db ldr r3, [r3, #12] 800171a: f000 faca bl 8001cb2 tmpsmcr = htim->Instance->SMCR; 800171e: 687b ldr r3, [r7, #4] 8001720: 681b ldr r3, [r3, #0] 8001722: 689b ldr r3, [r3, #8] 8001724: 60fb str r3, [r7, #12] tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1); 8001726: 68fb ldr r3, [r7, #12] 8001728: f043 0377 orr.w r3, r3, #119 ; 0x77 800172c: 60fb str r3, [r7, #12] htim->Instance->SMCR = tmpsmcr; 800172e: 687b ldr r3, [r7, #4] 8001730: 681b ldr r3, [r3, #0] 8001732: 68fa ldr r2, [r7, #12] 8001734: 609a str r2, [r3, #8] break; 8001736: e04e b.n 80017d6 TIM_ETR_SetConfig(htim->Instance, 8001738: 687b ldr r3, [r7, #4] 800173a: 6818 ldr r0, [r3, #0] 800173c: 683b ldr r3, [r7, #0] 800173e: 6899 ldr r1, [r3, #8] 8001740: 683b ldr r3, [r7, #0] 8001742: 685a ldr r2, [r3, #4] 8001744: 683b ldr r3, [r7, #0] 8001746: 68db ldr r3, [r3, #12] 8001748: f000 fab3 bl 8001cb2 htim->Instance->SMCR |= TIM_SMCR_ECE; 800174c: 687b ldr r3, [r7, #4] 800174e: 681b ldr r3, [r3, #0] 8001750: 689a ldr r2, [r3, #8] 8001752: 687b ldr r3, [r7, #4] 8001754: 681b ldr r3, [r3, #0] 8001756: f442 4280 orr.w r2, r2, #16384 ; 0x4000 800175a: 609a str r2, [r3, #8] break; 800175c: e03b b.n 80017d6 TIM_TI1_ConfigInputStage(htim->Instance, 800175e: 687b ldr r3, [r7, #4] 8001760: 6818 ldr r0, [r3, #0] 8001762: 683b ldr r3, [r7, #0] 8001764: 6859 ldr r1, [r3, #4] 8001766: 683b ldr r3, [r7, #0] 8001768: 68db ldr r3, [r3, #12] 800176a: 461a mov r2, r3 800176c: f000 fa2a bl 8001bc4 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1); 8001770: 687b ldr r3, [r7, #4] 8001772: 681b ldr r3, [r3, #0] 8001774: 2150 movs r1, #80 ; 0x50 8001776: 4618 mov r0, r3 8001778: f000 fa81 bl 8001c7e break; 800177c: e02b b.n 80017d6 TIM_TI2_ConfigInputStage(htim->Instance, 800177e: 687b ldr r3, [r7, #4] 8001780: 6818 ldr r0, [r3, #0] 8001782: 683b ldr r3, [r7, #0] 8001784: 6859 ldr r1, [r3, #4] 8001786: 683b ldr r3, [r7, #0] 8001788: 68db ldr r3, [r3, #12] 800178a: 461a mov r2, r3 800178c: f000 fa48 bl 8001c20 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2); 8001790: 687b ldr r3, [r7, #4] 8001792: 681b ldr r3, [r3, #0] 8001794: 2160 movs r1, #96 ; 0x60 8001796: 4618 mov r0, r3 8001798: f000 fa71 bl 8001c7e break; 800179c: e01b b.n 80017d6 TIM_TI1_ConfigInputStage(htim->Instance, 800179e: 687b ldr r3, [r7, #4] 80017a0: 6818 ldr r0, [r3, #0] 80017a2: 683b ldr r3, [r7, #0] 80017a4: 6859 ldr r1, [r3, #4] 80017a6: 683b ldr r3, [r7, #0] 80017a8: 68db ldr r3, [r3, #12] 80017aa: 461a mov r2, r3 80017ac: f000 fa0a bl 8001bc4 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED); 80017b0: 687b ldr r3, [r7, #4] 80017b2: 681b ldr r3, [r3, #0] 80017b4: 2140 movs r1, #64 ; 0x40 80017b6: 4618 mov r0, r3 80017b8: f000 fa61 bl 8001c7e break; 80017bc: e00b b.n 80017d6 TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource); 80017be: 687b ldr r3, [r7, #4] 80017c0: 681a ldr r2, [r3, #0] 80017c2: 683b ldr r3, [r7, #0] 80017c4: 681b ldr r3, [r3, #0] 80017c6: 4619 mov r1, r3 80017c8: 4610 mov r0, r2 80017ca: f000 fa58 bl 8001c7e break; 80017ce: e002 b.n 80017d6 break; 80017d0: bf00 nop 80017d2: e000 b.n 80017d6 break; 80017d4: bf00 nop } htim->State = HAL_TIM_STATE_READY; 80017d6: 687b ldr r3, [r7, #4] 80017d8: 2201 movs r2, #1 80017da: f883 203d strb.w r2, [r3, #61] ; 0x3d __HAL_UNLOCK(htim); 80017de: 687b ldr r3, [r7, #4] 80017e0: 2200 movs r2, #0 80017e2: f883 203c strb.w r2, [r3, #60] ; 0x3c return HAL_OK; 80017e6: 2300 movs r3, #0 } 80017e8: 4618 mov r0, r3 80017ea: 3710 adds r7, #16 80017ec: 46bd mov sp, r7 80017ee: bd80 pop {r7, pc} 080017f0 : * @param TIMx TIM peripheral * @param Structure TIM Base configuration structure * @retval None */ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure) { 80017f0: b480 push {r7} 80017f2: b085 sub sp, #20 80017f4: af00 add r7, sp, #0 80017f6: 6078 str r0, [r7, #4] 80017f8: 6039 str r1, [r7, #0] uint32_t tmpcr1; tmpcr1 = TIMx->CR1; 80017fa: 687b ldr r3, [r7, #4] 80017fc: 681b ldr r3, [r3, #0] 80017fe: 60fb str r3, [r7, #12] /* Set TIM Time Base Unit parameters ---------------------------------------*/ if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) 8001800: 687b ldr r3, [r7, #4] 8001802: 4a29 ldr r2, [pc, #164] ; (80018a8 ) 8001804: 4293 cmp r3, r2 8001806: d00b beq.n 8001820 8001808: 687b ldr r3, [r7, #4] 800180a: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000 800180e: d007 beq.n 8001820 8001810: 687b ldr r3, [r7, #4] 8001812: 4a26 ldr r2, [pc, #152] ; (80018ac ) 8001814: 4293 cmp r3, r2 8001816: d003 beq.n 8001820 8001818: 687b ldr r3, [r7, #4] 800181a: 4a25 ldr r2, [pc, #148] ; (80018b0 ) 800181c: 4293 cmp r3, r2 800181e: d108 bne.n 8001832 { /* Select the Counter Mode */ tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); 8001820: 68fb ldr r3, [r7, #12] 8001822: f023 0370 bic.w r3, r3, #112 ; 0x70 8001826: 60fb str r3, [r7, #12] tmpcr1 |= Structure->CounterMode; 8001828: 683b ldr r3, [r7, #0] 800182a: 685b ldr r3, [r3, #4] 800182c: 68fa ldr r2, [r7, #12] 800182e: 4313 orrs r3, r2 8001830: 60fb str r3, [r7, #12] } if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) 8001832: 687b ldr r3, [r7, #4] 8001834: 4a1c ldr r2, [pc, #112] ; (80018a8 ) 8001836: 4293 cmp r3, r2 8001838: d00b beq.n 8001852 800183a: 687b ldr r3, [r7, #4] 800183c: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000 8001840: d007 beq.n 8001852 8001842: 687b ldr r3, [r7, #4] 8001844: 4a19 ldr r2, [pc, #100] ; (80018ac ) 8001846: 4293 cmp r3, r2 8001848: d003 beq.n 8001852 800184a: 687b ldr r3, [r7, #4] 800184c: 4a18 ldr r2, [pc, #96] ; (80018b0 ) 800184e: 4293 cmp r3, r2 8001850: d108 bne.n 8001864 { /* Set the clock division */ tmpcr1 &= ~TIM_CR1_CKD; 8001852: 68fb ldr r3, [r7, #12] 8001854: f423 7340 bic.w r3, r3, #768 ; 0x300 8001858: 60fb str r3, [r7, #12] tmpcr1 |= (uint32_t)Structure->ClockDivision; 800185a: 683b ldr r3, [r7, #0] 800185c: 68db ldr r3, [r3, #12] 800185e: 68fa ldr r2, [r7, #12] 8001860: 4313 orrs r3, r2 8001862: 60fb str r3, [r7, #12] } /* Set the auto-reload preload */ MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); 8001864: 68fb ldr r3, [r7, #12] 8001866: f023 0280 bic.w r2, r3, #128 ; 0x80 800186a: 683b ldr r3, [r7, #0] 800186c: 695b ldr r3, [r3, #20] 800186e: 4313 orrs r3, r2 8001870: 60fb str r3, [r7, #12] TIMx->CR1 = tmpcr1; 8001872: 687b ldr r3, [r7, #4] 8001874: 68fa ldr r2, [r7, #12] 8001876: 601a str r2, [r3, #0] /* Set the Autoreload value */ TIMx->ARR = (uint32_t)Structure->Period ; 8001878: 683b ldr r3, [r7, #0] 800187a: 689a ldr r2, [r3, #8] 800187c: 687b ldr r3, [r7, #4] 800187e: 62da str r2, [r3, #44] ; 0x2c /* Set the Prescaler value */ TIMx->PSC = Structure->Prescaler; 8001880: 683b ldr r3, [r7, #0] 8001882: 681a ldr r2, [r3, #0] 8001884: 687b ldr r3, [r7, #4] 8001886: 629a str r2, [r3, #40] ; 0x28 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) 8001888: 687b ldr r3, [r7, #4] 800188a: 4a07 ldr r2, [pc, #28] ; (80018a8 ) 800188c: 4293 cmp r3, r2 800188e: d103 bne.n 8001898 { /* Set the Repetition Counter value */ TIMx->RCR = Structure->RepetitionCounter; 8001890: 683b ldr r3, [r7, #0] 8001892: 691a ldr r2, [r3, #16] 8001894: 687b ldr r3, [r7, #4] 8001896: 631a str r2, [r3, #48] ; 0x30 } /* Generate an update event to reload the Prescaler and the repetition counter (only for advanced timer) value immediately */ TIMx->EGR = TIM_EGR_UG; 8001898: 687b ldr r3, [r7, #4] 800189a: 2201 movs r2, #1 800189c: 615a str r2, [r3, #20] } 800189e: bf00 nop 80018a0: 3714 adds r7, #20 80018a2: 46bd mov sp, r7 80018a4: bc80 pop {r7} 80018a6: 4770 bx lr 80018a8: 40012c00 .word 0x40012c00 80018ac: 40000400 .word 0x40000400 80018b0: 40000800 .word 0x40000800 080018b4 : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) { 80018b4: b480 push {r7} 80018b6: b087 sub sp, #28 80018b8: af00 add r7, sp, #0 80018ba: 6078 str r0, [r7, #4] 80018bc: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Disable the Channel 1: Reset the CC1E Bit */ TIMx->CCER &= ~TIM_CCER_CC1E; 80018be: 687b ldr r3, [r7, #4] 80018c0: 6a1b ldr r3, [r3, #32] 80018c2: f023 0201 bic.w r2, r3, #1 80018c6: 687b ldr r3, [r7, #4] 80018c8: 621a str r2, [r3, #32] /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 80018ca: 687b ldr r3, [r7, #4] 80018cc: 6a1b ldr r3, [r3, #32] 80018ce: 617b str r3, [r7, #20] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 80018d0: 687b ldr r3, [r7, #4] 80018d2: 685b ldr r3, [r3, #4] 80018d4: 613b str r3, [r7, #16] /* Get the TIMx CCMR1 register value */ tmpccmrx = TIMx->CCMR1; 80018d6: 687b ldr r3, [r7, #4] 80018d8: 699b ldr r3, [r3, #24] 80018da: 60fb str r3, [r7, #12] /* Reset the Output Compare Mode Bits */ tmpccmrx &= ~TIM_CCMR1_OC1M; 80018dc: 68fb ldr r3, [r7, #12] 80018de: f023 0370 bic.w r3, r3, #112 ; 0x70 80018e2: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR1_CC1S; 80018e4: 68fb ldr r3, [r7, #12] 80018e6: f023 0303 bic.w r3, r3, #3 80018ea: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= OC_Config->OCMode; 80018ec: 683b ldr r3, [r7, #0] 80018ee: 681b ldr r3, [r3, #0] 80018f0: 68fa ldr r2, [r7, #12] 80018f2: 4313 orrs r3, r2 80018f4: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC1P; 80018f6: 697b ldr r3, [r7, #20] 80018f8: f023 0302 bic.w r3, r3, #2 80018fc: 617b str r3, [r7, #20] /* Set the Output Compare Polarity */ tmpccer |= OC_Config->OCPolarity; 80018fe: 683b ldr r3, [r7, #0] 8001900: 689b ldr r3, [r3, #8] 8001902: 697a ldr r2, [r7, #20] 8001904: 4313 orrs r3, r2 8001906: 617b str r3, [r7, #20] if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1)) 8001908: 687b ldr r3, [r7, #4] 800190a: 4a1c ldr r2, [pc, #112] ; (800197c ) 800190c: 4293 cmp r3, r2 800190e: d10c bne.n 800192a { /* Check parameters */ assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC1NP; 8001910: 697b ldr r3, [r7, #20] 8001912: f023 0308 bic.w r3, r3, #8 8001916: 617b str r3, [r7, #20] /* Set the Output N Polarity */ tmpccer |= OC_Config->OCNPolarity; 8001918: 683b ldr r3, [r7, #0] 800191a: 68db ldr r3, [r3, #12] 800191c: 697a ldr r2, [r7, #20] 800191e: 4313 orrs r3, r2 8001920: 617b str r3, [r7, #20] /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC1NE; 8001922: 697b ldr r3, [r7, #20] 8001924: f023 0304 bic.w r3, r3, #4 8001928: 617b str r3, [r7, #20] } if (IS_TIM_BREAK_INSTANCE(TIMx)) 800192a: 687b ldr r3, [r7, #4] 800192c: 4a13 ldr r2, [pc, #76] ; (800197c ) 800192e: 4293 cmp r3, r2 8001930: d111 bne.n 8001956 /* Check parameters */ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= ~TIM_CR2_OIS1; 8001932: 693b ldr r3, [r7, #16] 8001934: f423 7380 bic.w r3, r3, #256 ; 0x100 8001938: 613b str r3, [r7, #16] tmpcr2 &= ~TIM_CR2_OIS1N; 800193a: 693b ldr r3, [r7, #16] 800193c: f423 7300 bic.w r3, r3, #512 ; 0x200 8001940: 613b str r3, [r7, #16] /* Set the Output Idle state */ tmpcr2 |= OC_Config->OCIdleState; 8001942: 683b ldr r3, [r7, #0] 8001944: 695b ldr r3, [r3, #20] 8001946: 693a ldr r2, [r7, #16] 8001948: 4313 orrs r3, r2 800194a: 613b str r3, [r7, #16] /* Set the Output N Idle state */ tmpcr2 |= OC_Config->OCNIdleState; 800194c: 683b ldr r3, [r7, #0] 800194e: 699b ldr r3, [r3, #24] 8001950: 693a ldr r2, [r7, #16] 8001952: 4313 orrs r3, r2 8001954: 613b str r3, [r7, #16] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 8001956: 687b ldr r3, [r7, #4] 8001958: 693a ldr r2, [r7, #16] 800195a: 605a str r2, [r3, #4] /* Write to TIMx CCMR1 */ TIMx->CCMR1 = tmpccmrx; 800195c: 687b ldr r3, [r7, #4] 800195e: 68fa ldr r2, [r7, #12] 8001960: 619a str r2, [r3, #24] /* Set the Capture Compare Register value */ TIMx->CCR1 = OC_Config->Pulse; 8001962: 683b ldr r3, [r7, #0] 8001964: 685a ldr r2, [r3, #4] 8001966: 687b ldr r3, [r7, #4] 8001968: 635a str r2, [r3, #52] ; 0x34 /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 800196a: 687b ldr r3, [r7, #4] 800196c: 697a ldr r2, [r7, #20] 800196e: 621a str r2, [r3, #32] } 8001970: bf00 nop 8001972: 371c adds r7, #28 8001974: 46bd mov sp, r7 8001976: bc80 pop {r7} 8001978: 4770 bx lr 800197a: bf00 nop 800197c: 40012c00 .word 0x40012c00 08001980 : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) { 8001980: b480 push {r7} 8001982: b087 sub sp, #28 8001984: af00 add r7, sp, #0 8001986: 6078 str r0, [r7, #4] 8001988: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Disable the Channel 2: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC2E; 800198a: 687b ldr r3, [r7, #4] 800198c: 6a1b ldr r3, [r3, #32] 800198e: f023 0210 bic.w r2, r3, #16 8001992: 687b ldr r3, [r7, #4] 8001994: 621a str r2, [r3, #32] /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 8001996: 687b ldr r3, [r7, #4] 8001998: 6a1b ldr r3, [r3, #32] 800199a: 617b str r3, [r7, #20] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 800199c: 687b ldr r3, [r7, #4] 800199e: 685b ldr r3, [r3, #4] 80019a0: 613b str r3, [r7, #16] /* Get the TIMx CCMR1 register value */ tmpccmrx = TIMx->CCMR1; 80019a2: 687b ldr r3, [r7, #4] 80019a4: 699b ldr r3, [r3, #24] 80019a6: 60fb str r3, [r7, #12] /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= ~TIM_CCMR1_OC2M; 80019a8: 68fb ldr r3, [r7, #12] 80019aa: f423 43e0 bic.w r3, r3, #28672 ; 0x7000 80019ae: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR1_CC2S; 80019b0: 68fb ldr r3, [r7, #12] 80019b2: f423 7340 bic.w r3, r3, #768 ; 0x300 80019b6: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= (OC_Config->OCMode << 8U); 80019b8: 683b ldr r3, [r7, #0] 80019ba: 681b ldr r3, [r3, #0] 80019bc: 021b lsls r3, r3, #8 80019be: 68fa ldr r2, [r7, #12] 80019c0: 4313 orrs r3, r2 80019c2: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC2P; 80019c4: 697b ldr r3, [r7, #20] 80019c6: f023 0320 bic.w r3, r3, #32 80019ca: 617b str r3, [r7, #20] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 4U); 80019cc: 683b ldr r3, [r7, #0] 80019ce: 689b ldr r3, [r3, #8] 80019d0: 011b lsls r3, r3, #4 80019d2: 697a ldr r2, [r7, #20] 80019d4: 4313 orrs r3, r2 80019d6: 617b str r3, [r7, #20] if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2)) 80019d8: 687b ldr r3, [r7, #4] 80019da: 4a1d ldr r2, [pc, #116] ; (8001a50 ) 80019dc: 4293 cmp r3, r2 80019de: d10d bne.n 80019fc { assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC2NP; 80019e0: 697b ldr r3, [r7, #20] 80019e2: f023 0380 bic.w r3, r3, #128 ; 0x80 80019e6: 617b str r3, [r7, #20] /* Set the Output N Polarity */ tmpccer |= (OC_Config->OCNPolarity << 4U); 80019e8: 683b ldr r3, [r7, #0] 80019ea: 68db ldr r3, [r3, #12] 80019ec: 011b lsls r3, r3, #4 80019ee: 697a ldr r2, [r7, #20] 80019f0: 4313 orrs r3, r2 80019f2: 617b str r3, [r7, #20] /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC2NE; 80019f4: 697b ldr r3, [r7, #20] 80019f6: f023 0340 bic.w r3, r3, #64 ; 0x40 80019fa: 617b str r3, [r7, #20] } if (IS_TIM_BREAK_INSTANCE(TIMx)) 80019fc: 687b ldr r3, [r7, #4] 80019fe: 4a14 ldr r2, [pc, #80] ; (8001a50 ) 8001a00: 4293 cmp r3, r2 8001a02: d113 bne.n 8001a2c /* Check parameters */ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= ~TIM_CR2_OIS2; 8001a04: 693b ldr r3, [r7, #16] 8001a06: f423 6380 bic.w r3, r3, #1024 ; 0x400 8001a0a: 613b str r3, [r7, #16] tmpcr2 &= ~TIM_CR2_OIS2N; 8001a0c: 693b ldr r3, [r7, #16] 8001a0e: f423 6300 bic.w r3, r3, #2048 ; 0x800 8001a12: 613b str r3, [r7, #16] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 2U); 8001a14: 683b ldr r3, [r7, #0] 8001a16: 695b ldr r3, [r3, #20] 8001a18: 009b lsls r3, r3, #2 8001a1a: 693a ldr r2, [r7, #16] 8001a1c: 4313 orrs r3, r2 8001a1e: 613b str r3, [r7, #16] /* Set the Output N Idle state */ tmpcr2 |= (OC_Config->OCNIdleState << 2U); 8001a20: 683b ldr r3, [r7, #0] 8001a22: 699b ldr r3, [r3, #24] 8001a24: 009b lsls r3, r3, #2 8001a26: 693a ldr r2, [r7, #16] 8001a28: 4313 orrs r3, r2 8001a2a: 613b str r3, [r7, #16] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 8001a2c: 687b ldr r3, [r7, #4] 8001a2e: 693a ldr r2, [r7, #16] 8001a30: 605a str r2, [r3, #4] /* Write to TIMx CCMR1 */ TIMx->CCMR1 = tmpccmrx; 8001a32: 687b ldr r3, [r7, #4] 8001a34: 68fa ldr r2, [r7, #12] 8001a36: 619a str r2, [r3, #24] /* Set the Capture Compare Register value */ TIMx->CCR2 = OC_Config->Pulse; 8001a38: 683b ldr r3, [r7, #0] 8001a3a: 685a ldr r2, [r3, #4] 8001a3c: 687b ldr r3, [r7, #4] 8001a3e: 639a str r2, [r3, #56] ; 0x38 /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 8001a40: 687b ldr r3, [r7, #4] 8001a42: 697a ldr r2, [r7, #20] 8001a44: 621a str r2, [r3, #32] } 8001a46: bf00 nop 8001a48: 371c adds r7, #28 8001a4a: 46bd mov sp, r7 8001a4c: bc80 pop {r7} 8001a4e: 4770 bx lr 8001a50: 40012c00 .word 0x40012c00 08001a54 : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) { 8001a54: b480 push {r7} 8001a56: b087 sub sp, #28 8001a58: af00 add r7, sp, #0 8001a5a: 6078 str r0, [r7, #4] 8001a5c: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Disable the Channel 3: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC3E; 8001a5e: 687b ldr r3, [r7, #4] 8001a60: 6a1b ldr r3, [r3, #32] 8001a62: f423 7280 bic.w r2, r3, #256 ; 0x100 8001a66: 687b ldr r3, [r7, #4] 8001a68: 621a str r2, [r3, #32] /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 8001a6a: 687b ldr r3, [r7, #4] 8001a6c: 6a1b ldr r3, [r3, #32] 8001a6e: 617b str r3, [r7, #20] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 8001a70: 687b ldr r3, [r7, #4] 8001a72: 685b ldr r3, [r3, #4] 8001a74: 613b str r3, [r7, #16] /* Get the TIMx CCMR2 register value */ tmpccmrx = TIMx->CCMR2; 8001a76: 687b ldr r3, [r7, #4] 8001a78: 69db ldr r3, [r3, #28] 8001a7a: 60fb str r3, [r7, #12] /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= ~TIM_CCMR2_OC3M; 8001a7c: 68fb ldr r3, [r7, #12] 8001a7e: f023 0370 bic.w r3, r3, #112 ; 0x70 8001a82: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR2_CC3S; 8001a84: 68fb ldr r3, [r7, #12] 8001a86: f023 0303 bic.w r3, r3, #3 8001a8a: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= OC_Config->OCMode; 8001a8c: 683b ldr r3, [r7, #0] 8001a8e: 681b ldr r3, [r3, #0] 8001a90: 68fa ldr r2, [r7, #12] 8001a92: 4313 orrs r3, r2 8001a94: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC3P; 8001a96: 697b ldr r3, [r7, #20] 8001a98: f423 7300 bic.w r3, r3, #512 ; 0x200 8001a9c: 617b str r3, [r7, #20] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 8U); 8001a9e: 683b ldr r3, [r7, #0] 8001aa0: 689b ldr r3, [r3, #8] 8001aa2: 021b lsls r3, r3, #8 8001aa4: 697a ldr r2, [r7, #20] 8001aa6: 4313 orrs r3, r2 8001aa8: 617b str r3, [r7, #20] if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3)) 8001aaa: 687b ldr r3, [r7, #4] 8001aac: 4a1d ldr r2, [pc, #116] ; (8001b24 ) 8001aae: 4293 cmp r3, r2 8001ab0: d10d bne.n 8001ace { assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC3NP; 8001ab2: 697b ldr r3, [r7, #20] 8001ab4: f423 6300 bic.w r3, r3, #2048 ; 0x800 8001ab8: 617b str r3, [r7, #20] /* Set the Output N Polarity */ tmpccer |= (OC_Config->OCNPolarity << 8U); 8001aba: 683b ldr r3, [r7, #0] 8001abc: 68db ldr r3, [r3, #12] 8001abe: 021b lsls r3, r3, #8 8001ac0: 697a ldr r2, [r7, #20] 8001ac2: 4313 orrs r3, r2 8001ac4: 617b str r3, [r7, #20] /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC3NE; 8001ac6: 697b ldr r3, [r7, #20] 8001ac8: f423 6380 bic.w r3, r3, #1024 ; 0x400 8001acc: 617b str r3, [r7, #20] } if (IS_TIM_BREAK_INSTANCE(TIMx)) 8001ace: 687b ldr r3, [r7, #4] 8001ad0: 4a14 ldr r2, [pc, #80] ; (8001b24 ) 8001ad2: 4293 cmp r3, r2 8001ad4: d113 bne.n 8001afe /* Check parameters */ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= ~TIM_CR2_OIS3; 8001ad6: 693b ldr r3, [r7, #16] 8001ad8: f423 5380 bic.w r3, r3, #4096 ; 0x1000 8001adc: 613b str r3, [r7, #16] tmpcr2 &= ~TIM_CR2_OIS3N; 8001ade: 693b ldr r3, [r7, #16] 8001ae0: f423 5300 bic.w r3, r3, #8192 ; 0x2000 8001ae4: 613b str r3, [r7, #16] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 4U); 8001ae6: 683b ldr r3, [r7, #0] 8001ae8: 695b ldr r3, [r3, #20] 8001aea: 011b lsls r3, r3, #4 8001aec: 693a ldr r2, [r7, #16] 8001aee: 4313 orrs r3, r2 8001af0: 613b str r3, [r7, #16] /* Set the Output N Idle state */ tmpcr2 |= (OC_Config->OCNIdleState << 4U); 8001af2: 683b ldr r3, [r7, #0] 8001af4: 699b ldr r3, [r3, #24] 8001af6: 011b lsls r3, r3, #4 8001af8: 693a ldr r2, [r7, #16] 8001afa: 4313 orrs r3, r2 8001afc: 613b str r3, [r7, #16] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 8001afe: 687b ldr r3, [r7, #4] 8001b00: 693a ldr r2, [r7, #16] 8001b02: 605a str r2, [r3, #4] /* Write to TIMx CCMR2 */ TIMx->CCMR2 = tmpccmrx; 8001b04: 687b ldr r3, [r7, #4] 8001b06: 68fa ldr r2, [r7, #12] 8001b08: 61da str r2, [r3, #28] /* Set the Capture Compare Register value */ TIMx->CCR3 = OC_Config->Pulse; 8001b0a: 683b ldr r3, [r7, #0] 8001b0c: 685a ldr r2, [r3, #4] 8001b0e: 687b ldr r3, [r7, #4] 8001b10: 63da str r2, [r3, #60] ; 0x3c /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 8001b12: 687b ldr r3, [r7, #4] 8001b14: 697a ldr r2, [r7, #20] 8001b16: 621a str r2, [r3, #32] } 8001b18: bf00 nop 8001b1a: 371c adds r7, #28 8001b1c: 46bd mov sp, r7 8001b1e: bc80 pop {r7} 8001b20: 4770 bx lr 8001b22: bf00 nop 8001b24: 40012c00 .word 0x40012c00 08001b28 : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) { 8001b28: b480 push {r7} 8001b2a: b087 sub sp, #28 8001b2c: af00 add r7, sp, #0 8001b2e: 6078 str r0, [r7, #4] 8001b30: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Disable the Channel 4: Reset the CC4E Bit */ TIMx->CCER &= ~TIM_CCER_CC4E; 8001b32: 687b ldr r3, [r7, #4] 8001b34: 6a1b ldr r3, [r3, #32] 8001b36: f423 5280 bic.w r2, r3, #4096 ; 0x1000 8001b3a: 687b ldr r3, [r7, #4] 8001b3c: 621a str r2, [r3, #32] /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 8001b3e: 687b ldr r3, [r7, #4] 8001b40: 6a1b ldr r3, [r3, #32] 8001b42: 613b str r3, [r7, #16] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 8001b44: 687b ldr r3, [r7, #4] 8001b46: 685b ldr r3, [r3, #4] 8001b48: 617b str r3, [r7, #20] /* Get the TIMx CCMR2 register value */ tmpccmrx = TIMx->CCMR2; 8001b4a: 687b ldr r3, [r7, #4] 8001b4c: 69db ldr r3, [r3, #28] 8001b4e: 60fb str r3, [r7, #12] /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= ~TIM_CCMR2_OC4M; 8001b50: 68fb ldr r3, [r7, #12] 8001b52: f423 43e0 bic.w r3, r3, #28672 ; 0x7000 8001b56: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR2_CC4S; 8001b58: 68fb ldr r3, [r7, #12] 8001b5a: f423 7340 bic.w r3, r3, #768 ; 0x300 8001b5e: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= (OC_Config->OCMode << 8U); 8001b60: 683b ldr r3, [r7, #0] 8001b62: 681b ldr r3, [r3, #0] 8001b64: 021b lsls r3, r3, #8 8001b66: 68fa ldr r2, [r7, #12] 8001b68: 4313 orrs r3, r2 8001b6a: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC4P; 8001b6c: 693b ldr r3, [r7, #16] 8001b6e: f423 5300 bic.w r3, r3, #8192 ; 0x2000 8001b72: 613b str r3, [r7, #16] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 12U); 8001b74: 683b ldr r3, [r7, #0] 8001b76: 689b ldr r3, [r3, #8] 8001b78: 031b lsls r3, r3, #12 8001b7a: 693a ldr r2, [r7, #16] 8001b7c: 4313 orrs r3, r2 8001b7e: 613b str r3, [r7, #16] if (IS_TIM_BREAK_INSTANCE(TIMx)) 8001b80: 687b ldr r3, [r7, #4] 8001b82: 4a0f ldr r2, [pc, #60] ; (8001bc0 ) 8001b84: 4293 cmp r3, r2 8001b86: d109 bne.n 8001b9c { /* Check parameters */ assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare IDLE State */ tmpcr2 &= ~TIM_CR2_OIS4; 8001b88: 697b ldr r3, [r7, #20] 8001b8a: f423 4380 bic.w r3, r3, #16384 ; 0x4000 8001b8e: 617b str r3, [r7, #20] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 6U); 8001b90: 683b ldr r3, [r7, #0] 8001b92: 695b ldr r3, [r3, #20] 8001b94: 019b lsls r3, r3, #6 8001b96: 697a ldr r2, [r7, #20] 8001b98: 4313 orrs r3, r2 8001b9a: 617b str r3, [r7, #20] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 8001b9c: 687b ldr r3, [r7, #4] 8001b9e: 697a ldr r2, [r7, #20] 8001ba0: 605a str r2, [r3, #4] /* Write to TIMx CCMR2 */ TIMx->CCMR2 = tmpccmrx; 8001ba2: 687b ldr r3, [r7, #4] 8001ba4: 68fa ldr r2, [r7, #12] 8001ba6: 61da str r2, [r3, #28] /* Set the Capture Compare Register value */ TIMx->CCR4 = OC_Config->Pulse; 8001ba8: 683b ldr r3, [r7, #0] 8001baa: 685a ldr r2, [r3, #4] 8001bac: 687b ldr r3, [r7, #4] 8001bae: 641a str r2, [r3, #64] ; 0x40 /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 8001bb0: 687b ldr r3, [r7, #4] 8001bb2: 693a ldr r2, [r7, #16] 8001bb4: 621a str r2, [r3, #32] } 8001bb6: bf00 nop 8001bb8: 371c adds r7, #28 8001bba: 46bd mov sp, r7 8001bbc: bc80 pop {r7} 8001bbe: 4770 bx lr 8001bc0: 40012c00 .word 0x40012c00 08001bc4 : * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None */ static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) { 8001bc4: b480 push {r7} 8001bc6: b087 sub sp, #28 8001bc8: af00 add r7, sp, #0 8001bca: 60f8 str r0, [r7, #12] 8001bcc: 60b9 str r1, [r7, #8] 8001bce: 607a str r2, [r7, #4] uint32_t tmpccmr1; uint32_t tmpccer; /* Disable the Channel 1: Reset the CC1E Bit */ tmpccer = TIMx->CCER; 8001bd0: 68fb ldr r3, [r7, #12] 8001bd2: 6a1b ldr r3, [r3, #32] 8001bd4: 617b str r3, [r7, #20] TIMx->CCER &= ~TIM_CCER_CC1E; 8001bd6: 68fb ldr r3, [r7, #12] 8001bd8: 6a1b ldr r3, [r3, #32] 8001bda: f023 0201 bic.w r2, r3, #1 8001bde: 68fb ldr r3, [r7, #12] 8001be0: 621a str r2, [r3, #32] tmpccmr1 = TIMx->CCMR1; 8001be2: 68fb ldr r3, [r7, #12] 8001be4: 699b ldr r3, [r3, #24] 8001be6: 613b str r3, [r7, #16] /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC1F; 8001be8: 693b ldr r3, [r7, #16] 8001bea: f023 03f0 bic.w r3, r3, #240 ; 0xf0 8001bee: 613b str r3, [r7, #16] tmpccmr1 |= (TIM_ICFilter << 4U); 8001bf0: 687b ldr r3, [r7, #4] 8001bf2: 011b lsls r3, r3, #4 8001bf4: 693a ldr r2, [r7, #16] 8001bf6: 4313 orrs r3, r2 8001bf8: 613b str r3, [r7, #16] /* Select the Polarity and set the CC1E Bit */ tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); 8001bfa: 697b ldr r3, [r7, #20] 8001bfc: f023 030a bic.w r3, r3, #10 8001c00: 617b str r3, [r7, #20] tmpccer |= TIM_ICPolarity; 8001c02: 697a ldr r2, [r7, #20] 8001c04: 68bb ldr r3, [r7, #8] 8001c06: 4313 orrs r3, r2 8001c08: 617b str r3, [r7, #20] /* Write to TIMx CCMR1 and CCER registers */ TIMx->CCMR1 = tmpccmr1; 8001c0a: 68fb ldr r3, [r7, #12] 8001c0c: 693a ldr r2, [r7, #16] 8001c0e: 619a str r2, [r3, #24] TIMx->CCER = tmpccer; 8001c10: 68fb ldr r3, [r7, #12] 8001c12: 697a ldr r2, [r7, #20] 8001c14: 621a str r2, [r3, #32] } 8001c16: bf00 nop 8001c18: 371c adds r7, #28 8001c1a: 46bd mov sp, r7 8001c1c: bc80 pop {r7} 8001c1e: 4770 bx lr 08001c20 : * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None */ static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) { 8001c20: b480 push {r7} 8001c22: b087 sub sp, #28 8001c24: af00 add r7, sp, #0 8001c26: 60f8 str r0, [r7, #12] 8001c28: 60b9 str r1, [r7, #8] 8001c2a: 607a str r2, [r7, #4] uint32_t tmpccmr1; uint32_t tmpccer; /* Disable the Channel 2: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC2E; 8001c2c: 68fb ldr r3, [r7, #12] 8001c2e: 6a1b ldr r3, [r3, #32] 8001c30: f023 0210 bic.w r2, r3, #16 8001c34: 68fb ldr r3, [r7, #12] 8001c36: 621a str r2, [r3, #32] tmpccmr1 = TIMx->CCMR1; 8001c38: 68fb ldr r3, [r7, #12] 8001c3a: 699b ldr r3, [r3, #24] 8001c3c: 617b str r3, [r7, #20] tmpccer = TIMx->CCER; 8001c3e: 68fb ldr r3, [r7, #12] 8001c40: 6a1b ldr r3, [r3, #32] 8001c42: 613b str r3, [r7, #16] /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC2F; 8001c44: 697b ldr r3, [r7, #20] 8001c46: f423 4370 bic.w r3, r3, #61440 ; 0xf000 8001c4a: 617b str r3, [r7, #20] tmpccmr1 |= (TIM_ICFilter << 12U); 8001c4c: 687b ldr r3, [r7, #4] 8001c4e: 031b lsls r3, r3, #12 8001c50: 697a ldr r2, [r7, #20] 8001c52: 4313 orrs r3, r2 8001c54: 617b str r3, [r7, #20] /* Select the Polarity and set the CC2E Bit */ tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); 8001c56: 693b ldr r3, [r7, #16] 8001c58: f023 03a0 bic.w r3, r3, #160 ; 0xa0 8001c5c: 613b str r3, [r7, #16] tmpccer |= (TIM_ICPolarity << 4U); 8001c5e: 68bb ldr r3, [r7, #8] 8001c60: 011b lsls r3, r3, #4 8001c62: 693a ldr r2, [r7, #16] 8001c64: 4313 orrs r3, r2 8001c66: 613b str r3, [r7, #16] /* Write to TIMx CCMR1 and CCER registers */ TIMx->CCMR1 = tmpccmr1 ; 8001c68: 68fb ldr r3, [r7, #12] 8001c6a: 697a ldr r2, [r7, #20] 8001c6c: 619a str r2, [r3, #24] TIMx->CCER = tmpccer; 8001c6e: 68fb ldr r3, [r7, #12] 8001c70: 693a ldr r2, [r7, #16] 8001c72: 621a str r2, [r3, #32] } 8001c74: bf00 nop 8001c76: 371c adds r7, #28 8001c78: 46bd mov sp, r7 8001c7a: bc80 pop {r7} 8001c7c: 4770 bx lr 08001c7e : * @arg TIM_TS_TI2FP2: Filtered Timer Input 2 * @arg TIM_TS_ETRF: External Trigger input * @retval None */ static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource) { 8001c7e: b480 push {r7} 8001c80: b085 sub sp, #20 8001c82: af00 add r7, sp, #0 8001c84: 6078 str r0, [r7, #4] 8001c86: 6039 str r1, [r7, #0] uint32_t tmpsmcr; /* Get the TIMx SMCR register value */ tmpsmcr = TIMx->SMCR; 8001c88: 687b ldr r3, [r7, #4] 8001c8a: 689b ldr r3, [r3, #8] 8001c8c: 60fb str r3, [r7, #12] /* Reset the TS Bits */ tmpsmcr &= ~TIM_SMCR_TS; 8001c8e: 68fb ldr r3, [r7, #12] 8001c90: f023 0370 bic.w r3, r3, #112 ; 0x70 8001c94: 60fb str r3, [r7, #12] /* Set the Input Trigger source and the slave mode*/ tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1); 8001c96: 683a ldr r2, [r7, #0] 8001c98: 68fb ldr r3, [r7, #12] 8001c9a: 4313 orrs r3, r2 8001c9c: f043 0307 orr.w r3, r3, #7 8001ca0: 60fb str r3, [r7, #12] /* Write to TIMx SMCR */ TIMx->SMCR = tmpsmcr; 8001ca2: 687b ldr r3, [r7, #4] 8001ca4: 68fa ldr r2, [r7, #12] 8001ca6: 609a str r2, [r3, #8] } 8001ca8: bf00 nop 8001caa: 3714 adds r7, #20 8001cac: 46bd mov sp, r7 8001cae: bc80 pop {r7} 8001cb0: 4770 bx lr 08001cb2 : * This parameter must be a value between 0x00 and 0x0F * @retval None */ void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter) { 8001cb2: b480 push {r7} 8001cb4: b087 sub sp, #28 8001cb6: af00 add r7, sp, #0 8001cb8: 60f8 str r0, [r7, #12] 8001cba: 60b9 str r1, [r7, #8] 8001cbc: 607a str r2, [r7, #4] 8001cbe: 603b str r3, [r7, #0] uint32_t tmpsmcr; tmpsmcr = TIMx->SMCR; 8001cc0: 68fb ldr r3, [r7, #12] 8001cc2: 689b ldr r3, [r3, #8] 8001cc4: 617b str r3, [r7, #20] /* Reset the ETR Bits */ tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); 8001cc6: 697b ldr r3, [r7, #20] 8001cc8: f423 437f bic.w r3, r3, #65280 ; 0xff00 8001ccc: 617b str r3, [r7, #20] /* Set the Prescaler, the Filter value and the Polarity */ tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U))); 8001cce: 683b ldr r3, [r7, #0] 8001cd0: 021a lsls r2, r3, #8 8001cd2: 687b ldr r3, [r7, #4] 8001cd4: 431a orrs r2, r3 8001cd6: 68bb ldr r3, [r7, #8] 8001cd8: 4313 orrs r3, r2 8001cda: 697a ldr r2, [r7, #20] 8001cdc: 4313 orrs r3, r2 8001cde: 617b str r3, [r7, #20] /* Write to TIMx SMCR */ TIMx->SMCR = tmpsmcr; 8001ce0: 68fb ldr r3, [r7, #12] 8001ce2: 697a ldr r2, [r7, #20] 8001ce4: 609a str r2, [r3, #8] } 8001ce6: bf00 nop 8001ce8: 371c adds r7, #28 8001cea: 46bd mov sp, r7 8001cec: bc80 pop {r7} 8001cee: 4770 bx lr 08001cf0 : * @param ChannelState specifies the TIM Channel CCxE bit new state. * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE. * @retval None */ void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState) { 8001cf0: b480 push {r7} 8001cf2: b087 sub sp, #28 8001cf4: af00 add r7, sp, #0 8001cf6: 60f8 str r0, [r7, #12] 8001cf8: 60b9 str r1, [r7, #8] 8001cfa: 607a str r2, [r7, #4] /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(TIMx)); assert_param(IS_TIM_CHANNELS(Channel)); tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */ 8001cfc: 68bb ldr r3, [r7, #8] 8001cfe: f003 031f and.w r3, r3, #31 8001d02: 2201 movs r2, #1 8001d04: fa02 f303 lsl.w r3, r2, r3 8001d08: 617b str r3, [r7, #20] /* Reset the CCxE Bit */ TIMx->CCER &= ~tmp; 8001d0a: 68fb ldr r3, [r7, #12] 8001d0c: 6a1a ldr r2, [r3, #32] 8001d0e: 697b ldr r3, [r7, #20] 8001d10: 43db mvns r3, r3 8001d12: 401a ands r2, r3 8001d14: 68fb ldr r3, [r7, #12] 8001d16: 621a str r2, [r3, #32] /* Set or reset the CCxE Bit */ TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */ 8001d18: 68fb ldr r3, [r7, #12] 8001d1a: 6a1a ldr r2, [r3, #32] 8001d1c: 68bb ldr r3, [r7, #8] 8001d1e: f003 031f and.w r3, r3, #31 8001d22: 6879 ldr r1, [r7, #4] 8001d24: fa01 f303 lsl.w r3, r1, r3 8001d28: 431a orrs r2, r3 8001d2a: 68fb ldr r3, [r7, #12] 8001d2c: 621a str r2, [r3, #32] } 8001d2e: bf00 nop 8001d30: 371c adds r7, #28 8001d32: 46bd mov sp, r7 8001d34: bc80 pop {r7} 8001d36: 4770 bx lr 08001d38 : * mode. * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef *sMasterConfig) { 8001d38: b480 push {r7} 8001d3a: b085 sub sp, #20 8001d3c: af00 add r7, sp, #0 8001d3e: 6078 str r0, [r7, #4] 8001d40: 6039 str r1, [r7, #0] assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance)); assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger)); assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode)); /* Check input state */ __HAL_LOCK(htim); 8001d42: 687b ldr r3, [r7, #4] 8001d44: f893 303c ldrb.w r3, [r3, #60] ; 0x3c 8001d48: 2b01 cmp r3, #1 8001d4a: d101 bne.n 8001d50 8001d4c: 2302 movs r3, #2 8001d4e: e046 b.n 8001dde 8001d50: 687b ldr r3, [r7, #4] 8001d52: 2201 movs r2, #1 8001d54: f883 203c strb.w r2, [r3, #60] ; 0x3c /* Change the handler state */ htim->State = HAL_TIM_STATE_BUSY; 8001d58: 687b ldr r3, [r7, #4] 8001d5a: 2202 movs r2, #2 8001d5c: f883 203d strb.w r2, [r3, #61] ; 0x3d /* Get the TIMx CR2 register value */ tmpcr2 = htim->Instance->CR2; 8001d60: 687b ldr r3, [r7, #4] 8001d62: 681b ldr r3, [r3, #0] 8001d64: 685b ldr r3, [r3, #4] 8001d66: 60fb str r3, [r7, #12] /* Get the TIMx SMCR register value */ tmpsmcr = htim->Instance->SMCR; 8001d68: 687b ldr r3, [r7, #4] 8001d6a: 681b ldr r3, [r3, #0] 8001d6c: 689b ldr r3, [r3, #8] 8001d6e: 60bb str r3, [r7, #8] /* Reset the MMS Bits */ tmpcr2 &= ~TIM_CR2_MMS; 8001d70: 68fb ldr r3, [r7, #12] 8001d72: f023 0370 bic.w r3, r3, #112 ; 0x70 8001d76: 60fb str r3, [r7, #12] /* Select the TRGO source */ tmpcr2 |= sMasterConfig->MasterOutputTrigger; 8001d78: 683b ldr r3, [r7, #0] 8001d7a: 681b ldr r3, [r3, #0] 8001d7c: 68fa ldr r2, [r7, #12] 8001d7e: 4313 orrs r3, r2 8001d80: 60fb str r3, [r7, #12] /* Update TIMx CR2 */ htim->Instance->CR2 = tmpcr2; 8001d82: 687b ldr r3, [r7, #4] 8001d84: 681b ldr r3, [r3, #0] 8001d86: 68fa ldr r2, [r7, #12] 8001d88: 605a str r2, [r3, #4] if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 8001d8a: 687b ldr r3, [r7, #4] 8001d8c: 681b ldr r3, [r3, #0] 8001d8e: 4a16 ldr r2, [pc, #88] ; (8001de8 ) 8001d90: 4293 cmp r3, r2 8001d92: d00e beq.n 8001db2 8001d94: 687b ldr r3, [r7, #4] 8001d96: 681b ldr r3, [r3, #0] 8001d98: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000 8001d9c: d009 beq.n 8001db2 8001d9e: 687b ldr r3, [r7, #4] 8001da0: 681b ldr r3, [r3, #0] 8001da2: 4a12 ldr r2, [pc, #72] ; (8001dec ) 8001da4: 4293 cmp r3, r2 8001da6: d004 beq.n 8001db2 8001da8: 687b ldr r3, [r7, #4] 8001daa: 681b ldr r3, [r3, #0] 8001dac: 4a10 ldr r2, [pc, #64] ; (8001df0 ) 8001dae: 4293 cmp r3, r2 8001db0: d10c bne.n 8001dcc { /* Reset the MSM Bit */ tmpsmcr &= ~TIM_SMCR_MSM; 8001db2: 68bb ldr r3, [r7, #8] 8001db4: f023 0380 bic.w r3, r3, #128 ; 0x80 8001db8: 60bb str r3, [r7, #8] /* Set master mode */ tmpsmcr |= sMasterConfig->MasterSlaveMode; 8001dba: 683b ldr r3, [r7, #0] 8001dbc: 685b ldr r3, [r3, #4] 8001dbe: 68ba ldr r2, [r7, #8] 8001dc0: 4313 orrs r3, r2 8001dc2: 60bb str r3, [r7, #8] /* Update TIMx SMCR */ htim->Instance->SMCR = tmpsmcr; 8001dc4: 687b ldr r3, [r7, #4] 8001dc6: 681b ldr r3, [r3, #0] 8001dc8: 68ba ldr r2, [r7, #8] 8001dca: 609a str r2, [r3, #8] } /* Change the htim state */ htim->State = HAL_TIM_STATE_READY; 8001dcc: 687b ldr r3, [r7, #4] 8001dce: 2201 movs r2, #1 8001dd0: f883 203d strb.w r2, [r3, #61] ; 0x3d __HAL_UNLOCK(htim); 8001dd4: 687b ldr r3, [r7, #4] 8001dd6: 2200 movs r2, #0 8001dd8: f883 203c strb.w r2, [r3, #60] ; 0x3c return HAL_OK; 8001ddc: 2300 movs r3, #0 } 8001dde: 4618 mov r0, r3 8001de0: 3714 adds r7, #20 8001de2: 46bd mov sp, r7 8001de4: bc80 pop {r7} 8001de6: 4770 bx lr 8001de8: 40012c00 .word 0x40012c00 8001dec: 40000400 .word 0x40000400 8001df0: 40000800 .word 0x40000800 08001df4 <__libc_init_array>: 8001df4: b570 push {r4, r5, r6, lr} 8001df6: 2600 movs r6, #0 8001df8: 4d0c ldr r5, [pc, #48] ; (8001e2c <__libc_init_array+0x38>) 8001dfa: 4c0d ldr r4, [pc, #52] ; (8001e30 <__libc_init_array+0x3c>) 8001dfc: 1b64 subs r4, r4, r5 8001dfe: 10a4 asrs r4, r4, #2 8001e00: 42a6 cmp r6, r4 8001e02: d109 bne.n 8001e18 <__libc_init_array+0x24> 8001e04: f000 f822 bl 8001e4c <_init> 8001e08: 2600 movs r6, #0 8001e0a: 4d0a ldr r5, [pc, #40] ; (8001e34 <__libc_init_array+0x40>) 8001e0c: 4c0a ldr r4, [pc, #40] ; (8001e38 <__libc_init_array+0x44>) 8001e0e: 1b64 subs r4, r4, r5 8001e10: 10a4 asrs r4, r4, #2 8001e12: 42a6 cmp r6, r4 8001e14: d105 bne.n 8001e22 <__libc_init_array+0x2e> 8001e16: bd70 pop {r4, r5, r6, pc} 8001e18: f855 3b04 ldr.w r3, [r5], #4 8001e1c: 4798 blx r3 8001e1e: 3601 adds r6, #1 8001e20: e7ee b.n 8001e00 <__libc_init_array+0xc> 8001e22: f855 3b04 ldr.w r3, [r5], #4 8001e26: 4798 blx r3 8001e28: 3601 adds r6, #1 8001e2a: e7f2 b.n 8001e12 <__libc_init_array+0x1e> 8001e2c: 08001e84 .word 0x08001e84 8001e30: 08001e84 .word 0x08001e84 8001e34: 08001e84 .word 0x08001e84 8001e38: 08001e88 .word 0x08001e88 08001e3c : 8001e3c: 4603 mov r3, r0 8001e3e: 4402 add r2, r0 8001e40: 4293 cmp r3, r2 8001e42: d100 bne.n 8001e46 8001e44: 4770 bx lr 8001e46: f803 1b01 strb.w r1, [r3], #1 8001e4a: e7f9 b.n 8001e40 08001e4c <_init>: 8001e4c: b5f8 push {r3, r4, r5, r6, r7, lr} 8001e4e: bf00 nop 8001e50: bcf8 pop {r3, r4, r5, r6, r7} 8001e52: bc08 pop {r3} 8001e54: 469e mov lr, r3 8001e56: 4770 bx lr 08001e58 <_fini>: 8001e58: b5f8 push {r3, r4, r5, r6, r7, lr} 8001e5a: bf00 nop 8001e5c: bcf8 pop {r3, r4, r5, r6, r7} 8001e5e: bc08 pop {r3} 8001e60: 469e mov lr, r3 8001e62: 4770 bx lr