: /** * @brief The application entry point. * @retval int */ int main(void) { 8000a20: b580 push {r7, lr} 8000a22: b08e sub sp, #56 ; 0x38 8000a24: af00 add r7, sp, #0 /* USER CODE END 1 */ /* MCU Configuration--------------------------------------------------------*/ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ HAL_Init(); 8000a26: f000 fa61 bl 8000eec /* USER CODE BEGIN Init */ /* USER CODE END Init */ /* Configure the system clock */ SystemClock_Config(); 8000a2a: f000 f875 bl 8000b18 /* USER CODE BEGIN SysInit */ /* USER CODE END SysInit */ /* Initialize all configured peripherals */ MX_GPIO_Init(); 8000a2e: f7ff ffab bl 8000988 MX_TIM1_Init(); 8000a32: f000 f951 bl 8000cd8 MX_USART2_UART_Init(); 8000a36: f000 f9bf bl 8000db8 /* USER CODE END 2 */ /* Infinite loop */ /* USER CODE BEGIN WHILE */ char send_buf[50] = { 0 }; 8000a3a: 2300 movs r3, #0 8000a3c: 607b str r3, [r7, #4] 8000a3e: f107 0308 add.w r3, r7, #8 8000a42: 222e movs r2, #46 ; 0x2e 8000a44: 2100 movs r1, #0 8000a46: 4618 mov r0, r3 8000a48: f001 fe44 bl 80026d4 while (1) { HAL_Delay(500); 8000a4c: f44f 70fa mov.w r0, #500 ; 0x1f4 8000a50: f000 faae bl 8000fb0 //触发模块输出 HAL_GPIO_WritePin(TRIG_GPIO_Port, TRIG_Pin, 1); 8000a54: 2201 movs r2, #1 8000a56: f44f 6100 mov.w r1, #2048 ; 0x800 8000a5a: 482b ldr r0, [pc, #172] ; (8000b08 ) 8000a5c: f000 fd4b bl 80014f6 HAL_Delay(5); 8000a60: 2005 movs r0, #5 8000a62: f000 faa5 bl 8000fb0 HAL_GPIO_WritePin(TRIG_GPIO_Port, TRIG_Pin, 0); 8000a66: 2200 movs r2, #0 8000a68: f44f 6100 mov.w r1, #2048 ; 0x800 8000a6c: 4826 ldr r0, [pc, #152] ; (8000b08 ) 8000a6e: f000 fd42 bl 80014f6 //清零TIM1的计�?? htim1.Instance->CNT = 0; 8000a72: 4b26 ldr r3, [pc, #152] ; (8000b0c ) 8000a74: 681b ldr r3, [r3, #0] 8000a76: 2200 movs r2, #0 8000a78: 625a str r2, [r3, #36] ; 0x24 //等待echo引脚拉高 while (!HAL_GPIO_ReadPin(ECHO_GPIO_Port, ECHO_Pin)) { 8000a7a: bf00 nop 8000a7c: f44f 6180 mov.w r1, #1024 ; 0x400 8000a80: 4821 ldr r0, [pc, #132] ; (8000b08 ) 8000a82: f000 fd21 bl 80014c8 8000a86: 4603 mov r3, r0 8000a88: 2b00 cmp r3, #0 8000a8a: d0f7 beq.n 8000a7c } //echo引脚拉高时，�??始计�?? HAL_TIM_Base_Start(&htim1); 8000a8c: 481f ldr r0, [pc, #124] ; (8000b0c ) 8000a8e: f001 f9b5 bl 8001dfc //等待echo引脚拉低 while (HAL_GPIO_ReadPin(ECHO_GPIO_Port, ECHO_Pin)) { 8000a92: bf00 nop 8000a94: f44f 6180 mov.w r1, #1024 ; 0x400 8000a98: 481b ldr r0, [pc, #108] ; (8000b08 ) 8000a9a: f000 fd15 bl 80014c8 8000a9e: 4603 mov r3, r0 8000aa0: 2b00 cmp r3, #0 8000aa2: d1f7 bne.n 8000a94 } //echo拉低，停止计�?? HAL_TIM_Base_Stop(&htim1); 8000aa4: 4819 ldr r0, [pc, #100] ; (8000b0c ) 8000aa6: f001 f9f3 bl 8001e90 //计算、输出距�?? //定时器每10us计数�??次，因此距离=计数*3.4/2（毫米） sprintf(send_buf, "%u millimeter\r\n", (uint16_t) ((float) htim1.Instance->CNT * 1.7)); 8000aaa: 4b18 ldr r3, [pc, #96] ; (8000b0c ) 8000aac: 681b ldr r3, [r3, #0] 8000aae: 6a5b ldr r3, [r3, #36] ; 0x24 8000ab0: 4618 mov r0, r3 8000ab2: f7ff ff11 bl 80008d8 <__aeabi_ui2f> 8000ab6: 4603 mov r3, r0 8000ab8: 4618 mov r0, r3 8000aba: f7ff fddf bl 800067c <__aeabi_f2d> 8000abe: a310 add r3, pc, #64 ; (adr r3, 8000b00 ) 8000ac0: e9d3 2300 ldrd r2, r3, [r3] 8000ac4: f7ff fb4c bl 8000160 <__aeabi_dmul> 8000ac8: 4602 mov r2, r0 8000aca: 460b mov r3, r1 8000acc: 4610 mov r0, r2 8000ace: 4619 mov r1, r3 8000ad0: f7ff fe2c bl 800072c <__aeabi_d2uiz> 8000ad4: 4603 mov r3, r0 8000ad6: b29b uxth r3, r3 sprintf(send_buf, "%u millimeter\r\n", 8000ad8: 461a mov r2, r3 8000ada: 1d3b adds r3, r7, #4 8000adc: 490c ldr r1, [pc, #48] ; (8000b10 ) 8000ade: 4618 mov r0, r3 8000ae0: f001 fe00 bl 80026e4 HAL_UART_Transmit(&huart2, (uint8_t*) send_buf, strlen(send_buf), 10); 8000ae4: 1d3b adds r3, r7, #4 8000ae6: 4618 mov r0, r3 8000ae8: f7ff fb32 bl 8000150 8000aec: 4603 mov r3, r0 8000aee: b29a uxth r2, r3 8000af0: 1d39 adds r1, r7, #4 8000af2: 230a movs r3, #10 8000af4: 4807 ldr r0, [pc, #28] ; (8000b14 ) 8000af6: f001 fc58 bl 80023aa HAL_Delay(500); 8000afa: e7a7 b.n 8000a4c 8000afc: f3af 8000 nop.w 8000b00: 33333333 .word 0x33333333 8000b04: 3ffb3333 .word 0x3ffb3333 8000b08: 40010800 .word 0x40010800 8000b0c: 20000090 .word 0x20000090 8000b10: 08002ff0 .word 0x08002ff0 8000b14: 200000d8 .word 0x200000d8 08000b18 : /** * @brief System Clock Configuration * @retval None */ void SystemClock_Config(void) { 8000b18: b580 push {r7, lr} 8000b1a: b090 sub sp, #64 ; 0x40 8000b1c: af00 add r7, sp, #0 RCC_OscInitTypeDef RCC_OscInitStruct = { 0 }; 8000b1e: f107 0318 add.w r3, r7, #24 8000b22: 2228 movs r2, #40 ; 0x28 8000b24: 2100 movs r1, #0 8000b26: 4618 mov r0, r3 8000b28: f001 fdd4 bl 80026d4 RCC_ClkInitTypeDef RCC_ClkInitStruct = { 0 }; 8000b2c: 1d3b adds r3, r7, #4 8000b2e: 2200 movs r2, #0 8000b30: 601a str r2, [r3, #0] 8000b32: 605a str r2, [r3, #4] 8000b34: 609a str r2, [r3, #8] 8000b36: 60da str r2, [r3, #12] 8000b38: 611a str r2, [r3, #16] /** Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; 8000b3a: 2301 movs r3, #1 8000b3c: 61bb str r3, [r7, #24] RCC_OscInitStruct.HSEState = RCC_HSE_ON; 8000b3e: f44f 3380 mov.w r3, #65536 ; 0x10000 8000b42: 61fb str r3, [r7, #28] RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV1; 8000b44: 2300 movs r3, #0 8000b46: 623b str r3, [r7, #32] RCC_OscInitStruct.HSIState = RCC_HSI_ON; 8000b48: 2301 movs r3, #1 8000b4a: 62bb str r3, [r7, #40] ; 0x28 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; 8000b4c: 2302 movs r3, #2 8000b4e: 637b str r3, [r7, #52] ; 0x34 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; 8000b50: f44f 3380 mov.w r3, #65536 ; 0x10000 8000b54: 63bb str r3, [r7, #56] ; 0x38 RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9; 8000b56: f44f 13e0 mov.w r3, #1835008 ; 0x1c0000 8000b5a: 63fb str r3, [r7, #60] ; 0x3c if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { 8000b5c: f107 0318 add.w r3, r7, #24 8000b60: 4618 mov r0, r3 8000b62: f000 fce1 bl 8001528 8000b66: 4603 mov r3, r0 8000b68: 2b00 cmp r3, #0 8000b6a: d001 beq.n 8000b70 Error_Handler(); 8000b6c: f000 f819 bl 8000ba2 } /** Initializes the CPU, AHB and APB buses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK 8000b70: 230f movs r3, #15 8000b72: 607b str r3, [r7, #4] | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; 8000b74: 2302 movs r3, #2 8000b76: 60bb str r3, [r7, #8] RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; 8000b78: 2300 movs r3, #0 8000b7a: 60fb str r3, [r7, #12] RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; 8000b7c: f44f 6380 mov.w r3, #1024 ; 0x400 8000b80: 613b str r3, [r7, #16] RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; 8000b82: 2300 movs r3, #0 8000b84: 617b str r3, [r7, #20] if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) { 8000b86: 1d3b adds r3, r7, #4 8000b88: 2102 movs r1, #2 8000b8a: 4618 mov r0, r3 8000b8c: f000 ff4e bl 8001a2c 8000b90: 4603 mov r3, r0 8000b92: 2b00 cmp r3, #0 8000b94: d001 beq.n 8000b9a Error_Handler(); 8000b96: f000 f804 bl 8000ba2 } } 8000b9a: bf00 nop 8000b9c: 3740 adds r7, #64 ; 0x40 8000b9e: 46bd mov sp, r7 8000ba0: bd80 pop {r7, pc} 08000ba2 : /** * @brief This function is executed in case of error occurrence. * @retval None */ void Error_Handler(void) { 8000ba2: b480 push {r7} 8000ba4: af00 add r7, sp, #0 \details Disables IRQ interrupts by setting the I-bit in the CPSR. Can only be executed in Privileged modes. */ __STATIC_FORCEINLINE void __disable_irq(void) { __ASM volatile ("cpsid i" : : : "memory"); 8000ba6: b672 cpsid i } 8000ba8: bf00 nop /* USER CODE BEGIN Error_Handler_Debug */ /* User can add his own implementation to report the HAL error return state */ __disable_irq(); while (1) { 8000baa: e7fe b.n 8000baa 08000bac : /* USER CODE END 0 */ /** * Initializes the Global MSP. */ void HAL_MspInit(void) { 8000bac: b480 push {r7} 8000bae: b085 sub sp, #20 8000bb0: af00 add r7, sp, #0 /* USER CODE BEGIN MspInit 0 */ /* USER CODE END MspInit 0 */ __HAL_RCC_AFIO_CLK_ENABLE(); 8000bb2: 4b15 ldr r3, [pc, #84] ; (8000c08 ) 8000bb4: 699b ldr r3, [r3, #24] 8000bb6: 4a14 ldr r2, [pc, #80] ; (8000c08 ) 8000bb8: f043 0301 orr.w r3, r3, #1 8000bbc: 6193 str r3, [r2, #24] 8000bbe: 4b12 ldr r3, [pc, #72] ; (8000c08 ) 8000bc0: 699b ldr r3, [r3, #24] 8000bc2: f003 0301 and.w r3, r3, #1 8000bc6: 60bb str r3, [r7, #8] 8000bc8: 68bb ldr r3, [r7, #8] __HAL_RCC_PWR_CLK_ENABLE(); 8000bca: 4b0f ldr r3, [pc, #60] ; (8000c08 ) 8000bcc: 69db ldr r3, [r3, #28] 8000bce: 4a0e ldr r2, [pc, #56] ; (8000c08 ) 8000bd0: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 8000bd4: 61d3 str r3, [r2, #28] 8000bd6: 4b0c ldr r3, [pc, #48] ; (8000c08 ) 8000bd8: 69db ldr r3, [r3, #28] 8000bda: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 8000bde: 607b str r3, [r7, #4] 8000be0: 687b ldr r3, [r7, #4] /* System interrupt init*/ /** NOJTAG: JTAG-DP Disabled and SW-DP Enabled */ __HAL_AFIO_REMAP_SWJ_NOJTAG(); 8000be2: 4b0a ldr r3, [pc, #40] ; (8000c0c ) 8000be4: 685b ldr r3, [r3, #4] 8000be6: 60fb str r3, [r7, #12] 8000be8: 68fb ldr r3, [r7, #12] 8000bea: f023 63e0 bic.w r3, r3, #117440512 ; 0x7000000 8000bee: 60fb str r3, [r7, #12] 8000bf0: 68fb ldr r3, [r7, #12] 8000bf2: f043 7300 orr.w r3, r3, #33554432 ; 0x2000000 8000bf6: 60fb str r3, [r7, #12] 8000bf8: 4a04 ldr r2, [pc, #16] ; (8000c0c ) 8000bfa: 68fb ldr r3, [r7, #12] 8000bfc: 6053 str r3, [r2, #4] /* USER CODE BEGIN MspInit 1 */ /* USER CODE END MspInit 1 */ } 8000bfe: bf00 nop 8000c00: 3714 adds r7, #20 8000c02: 46bd mov sp, r7 8000c04: bc80 pop {r7} 8000c06: 4770 bx lr 8000c08: 40021000 .word 0x40021000 8000c0c: 40010000 .word 0x40010000 08000c10 : /******************************************************************************/ /** * @brief This function handles Non maskable interrupt. */ void NMI_Handler(void) { 8000c10: b480 push {r7} 8000c12: af00 add r7, sp, #0 /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ /* USER CODE END NonMaskableInt_IRQn 0 */ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ while (1) 8000c14: e7fe b.n 8000c14 08000c16 : /** * @brief This function handles Hard fault interrupt. */ void HardFault_Handler(void) { 8000c16: b480 push {r7} 8000c18: af00 add r7, sp, #0 /* USER CODE BEGIN HardFault_IRQn 0 */ /* USER CODE END HardFault_IRQn 0 */ while (1) 8000c1a: e7fe b.n 8000c1a 08000c1c : /** * @brief This function handles Memory management fault. */ void MemManage_Handler(void) { 8000c1c: b480 push {r7} 8000c1e: af00 add r7, sp, #0 /* USER CODE BEGIN MemoryManagement_IRQn 0 */ /* USER CODE END MemoryManagement_IRQn 0 */ while (1) 8000c20: e7fe b.n 8000c20 08000c22 : /** * @brief This function handles Prefetch fault, memory access fault. */ void BusFault_Handler(void) { 8000c22: b480 push {r7} 8000c24: af00 add r7, sp, #0 /* USER CODE BEGIN BusFault_IRQn 0 */ /* USER CODE END BusFault_IRQn 0 */ while (1) 8000c26: e7fe b.n 8000c26 08000c28 : /** * @brief This function handles Undefined instruction or illegal state. */ void UsageFault_Handler(void) { 8000c28: b480 push {r7} 8000c2a: af00 add r7, sp, #0 /* USER CODE BEGIN UsageFault_IRQn 0 */ /* USER CODE END UsageFault_IRQn 0 */ while (1) 8000c2c: e7fe b.n 8000c2c 08000c2e : /** * @brief This function handles System service call via SWI instruction. */ void SVC_Handler(void) { 8000c2e: b480 push {r7} 8000c30: af00 add r7, sp, #0 /* USER CODE END SVCall_IRQn 0 */ /* USER CODE BEGIN SVCall_IRQn 1 */ /* USER CODE END SVCall_IRQn 1 */ } 8000c32: bf00 nop 8000c34: 46bd mov sp, r7 8000c36: bc80 pop {r7} 8000c38: 4770 bx lr 08000c3a : /** * @brief This function handles Debug monitor. */ void DebugMon_Handler(void) { 8000c3a: b480 push {r7} 8000c3c: af00 add r7, sp, #0 /* USER CODE END DebugMonitor_IRQn 0 */ /* USER CODE BEGIN DebugMonitor_IRQn 1 */ /* USER CODE END DebugMonitor_IRQn 1 */ } 8000c3e: bf00 nop 8000c40: 46bd mov sp, r7 8000c42: bc80 pop {r7} 8000c44: 4770 bx lr 08000c46 : /** * @brief This function handles Pendable request for system service. */ void PendSV_Handler(void) { 8000c46: b480 push {r7} 8000c48: af00 add r7, sp, #0 /* USER CODE END PendSV_IRQn 0 */ /* USER CODE BEGIN PendSV_IRQn 1 */ /* USER CODE END PendSV_IRQn 1 */ } 8000c4a: bf00 nop 8000c4c: 46bd mov sp, r7 8000c4e: bc80 pop {r7} 8000c50: 4770 bx lr 08000c52 : /** * @brief This function handles System tick timer. */ void SysTick_Handler(void) { 8000c52: b580 push {r7, lr} 8000c54: af00 add r7, sp, #0 /* USER CODE BEGIN SysTick_IRQn 0 */ /* USER CODE END SysTick_IRQn 0 */ HAL_IncTick(); 8000c56: f000 f98f bl 8000f78 /* USER CODE BEGIN SysTick_IRQn 1 */ /* USER CODE END SysTick_IRQn 1 */ } 8000c5a: bf00 nop 8000c5c: bd80 pop {r7, pc} ... 08000c60 <_sbrk>: * * @param incr Memory size * @return Pointer to allocated memory */ void *_sbrk(ptrdiff_t incr) { 8000c60: b580 push {r7, lr} 8000c62: b086 sub sp, #24 8000c64: af00 add r7, sp, #0 8000c66: 6078 str r0, [r7, #4] extern uint8_t _end; /* Symbol defined in the linker script */ extern uint8_t _estack; /* Symbol defined in the linker script */ extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */ const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size; 8000c68: 4a14 ldr r2, [pc, #80] ; (8000cbc <_sbrk+0x5c>) 8000c6a: 4b15 ldr r3, [pc, #84] ; (8000cc0 <_sbrk+0x60>) 8000c6c: 1ad3 subs r3, r2, r3 8000c6e: 617b str r3, [r7, #20] const uint8_t *max_heap = (uint8_t *)stack_limit; 8000c70: 697b ldr r3, [r7, #20] 8000c72: 613b str r3, [r7, #16] uint8_t *prev_heap_end; /* Initialize heap end at first call */ if (NULL == __sbrk_heap_end) 8000c74: 4b13 ldr r3, [pc, #76] ; (8000cc4 <_sbrk+0x64>) 8000c76: 681b ldr r3, [r3, #0] 8000c78: 2b00 cmp r3, #0 8000c7a: d102 bne.n 8000c82 <_sbrk+0x22> { __sbrk_heap_end = &_end; 8000c7c: 4b11 ldr r3, [pc, #68] ; (8000cc4 <_sbrk+0x64>) 8000c7e: 4a12 ldr r2, [pc, #72] ; (8000cc8 <_sbrk+0x68>) 8000c80: 601a str r2, [r3, #0] } /* Protect heap from growing into the reserved MSP stack */ if (__sbrk_heap_end + incr > max_heap) 8000c82: 4b10 ldr r3, [pc, #64] ; (8000cc4 <_sbrk+0x64>) 8000c84: 681a ldr r2, [r3, #0] 8000c86: 687b ldr r3, [r7, #4] 8000c88: 4413 add r3, r2 8000c8a: 693a ldr r2, [r7, #16] 8000c8c: 429a cmp r2, r3 8000c8e: d207 bcs.n 8000ca0 <_sbrk+0x40> { errno = ENOMEM; 8000c90: f001 fcf6 bl 8002680 <__errno> 8000c94: 4603 mov r3, r0 8000c96: 220c movs r2, #12 8000c98: 601a str r2, [r3, #0] return (void *)-1; 8000c9a: f04f 33ff mov.w r3, #4294967295 8000c9e: e009 b.n 8000cb4 <_sbrk+0x54> } prev_heap_end = __sbrk_heap_end; 8000ca0: 4b08 ldr r3, [pc, #32] ; (8000cc4 <_sbrk+0x64>) 8000ca2: 681b ldr r3, [r3, #0] 8000ca4: 60fb str r3, [r7, #12] __sbrk_heap_end += incr; 8000ca6: 4b07 ldr r3, [pc, #28] ; (8000cc4 <_sbrk+0x64>) 8000ca8: 681a ldr r2, [r3, #0] 8000caa: 687b ldr r3, [r7, #4] 8000cac: 4413 add r3, r2 8000cae: 4a05 ldr r2, [pc, #20] ; (8000cc4 <_sbrk+0x64>) 8000cb0: 6013 str r3, [r2, #0] return (void *)prev_heap_end; 8000cb2: 68fb ldr r3, [r7, #12] } 8000cb4: 4618 mov r0, r3 8000cb6: 3718 adds r7, #24 8000cb8: 46bd mov sp, r7 8000cba: bd80 pop {r7, pc} 8000cbc: 20005000 .word 0x20005000 8000cc0: 00000400 .word 0x00000400 8000cc4: 2000008c .word 0x2000008c 8000cc8: 20000130 .word 0x20000130 08000ccc : * @note This function should be used only after reset. * @param None * @retval None */ void SystemInit (void) { 8000ccc: b480 push {r7} 8000cce: af00 add r7, sp, #0 /* Configure the Vector Table location -------------------------------------*/ #if defined(USER_VECT_TAB_ADDRESS) SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ #endif /* USER_VECT_TAB_ADDRESS */ } 8000cd0: bf00 nop 8000cd2: 46bd mov sp, r7 8000cd4: bc80 pop {r7} 8000cd6: 4770 bx lr 08000cd8 : TIM_HandleTypeDef htim1; /* TIM1 init function */ void MX_TIM1_Init(void) { 8000cd8: b580 push {r7, lr} 8000cda: b086 sub sp, #24 8000cdc: af00 add r7, sp, #0 /* USER CODE BEGIN TIM1_Init 0 */ /* USER CODE END TIM1_Init 0 */ TIM_ClockConfigTypeDef sClockSourceConfig = {0}; 8000cde: f107 0308 add.w r3, r7, #8 8000ce2: 2200 movs r2, #0 8000ce4: 601a str r2, [r3, #0] 8000ce6: 605a str r2, [r3, #4] 8000ce8: 609a str r2, [r3, #8] 8000cea: 60da str r2, [r3, #12] TIM_MasterConfigTypeDef sMasterConfig = {0}; 8000cec: 463b mov r3, r7 8000cee: 2200 movs r2, #0 8000cf0: 601a str r2, [r3, #0] 8000cf2: 605a str r2, [r3, #4] /* USER CODE BEGIN TIM1_Init 1 */ /* USER CODE END TIM1_Init 1 */ htim1.Instance = TIM1; 8000cf4: 4b1f ldr r3, [pc, #124] ; (8000d74 ) 8000cf6: 4a20 ldr r2, [pc, #128] ; (8000d78 ) 8000cf8: 601a str r2, [r3, #0] htim1.Init.Prescaler = 720-1; 8000cfa: 4b1e ldr r3, [pc, #120] ; (8000d74 ) 8000cfc: f240 22cf movw r2, #719 ; 0x2cf 8000d00: 605a str r2, [r3, #4] htim1.Init.CounterMode = TIM_COUNTERMODE_UP; 8000d02: 4b1c ldr r3, [pc, #112] ; (8000d74 ) 8000d04: 2200 movs r2, #0 8000d06: 609a str r2, [r3, #8] htim1.Init.Period = 65535; 8000d08: 4b1a ldr r3, [pc, #104] ; (8000d74 ) 8000d0a: f64f 72ff movw r2, #65535 ; 0xffff 8000d0e: 60da str r2, [r3, #12] htim1.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 8000d10: 4b18 ldr r3, [pc, #96] ; (8000d74 ) 8000d12: 2200 movs r2, #0 8000d14: 611a str r2, [r3, #16] htim1.Init.RepetitionCounter = 0; 8000d16: 4b17 ldr r3, [pc, #92] ; (8000d74 ) 8000d18: 2200 movs r2, #0 8000d1a: 615a str r2, [r3, #20] htim1.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 8000d1c: 4b15 ldr r3, [pc, #84] ; (8000d74 ) 8000d1e: 2200 movs r2, #0 8000d20: 619a str r2, [r3, #24] if (HAL_TIM_Base_Init(&htim1) != HAL_OK) 8000d22: 4814 ldr r0, [pc, #80] ; (8000d74 ) 8000d24: f001 f81a bl 8001d5c 8000d28: 4603 mov r3, r0 8000d2a: 2b00 cmp r3, #0 8000d2c: d001 beq.n 8000d32 { Error_Handler(); 8000d2e: f7ff ff38 bl 8000ba2 } sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; 8000d32: f44f 5380 mov.w r3, #4096 ; 0x1000 8000d36: 60bb str r3, [r7, #8] if (HAL_TIM_ConfigClockSource(&htim1, &sClockSourceConfig) != HAL_OK) 8000d38: f107 0308 add.w r3, r7, #8 8000d3c: 4619 mov r1, r3 8000d3e: 480d ldr r0, [pc, #52] ; (8000d74 ) 8000d40: f001 f8cc bl 8001edc 8000d44: 4603 mov r3, r0 8000d46: 2b00 cmp r3, #0 8000d48: d001 beq.n 8000d4e { Error_Handler(); 8000d4a: f7ff ff2a bl 8000ba2 } sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; 8000d4e: 2300 movs r3, #0 8000d50: 603b str r3, [r7, #0] sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 8000d52: 2300 movs r3, #0 8000d54: 607b str r3, [r7, #4] if (HAL_TIMEx_MasterConfigSynchronization(&htim1, &sMasterConfig) != HAL_OK) 8000d56: 463b mov r3, r7 8000d58: 4619 mov r1, r3 8000d5a: 4806 ldr r0, [pc, #24] ; (8000d74 ) 8000d5c: f001 fa7a bl 8002254 8000d60: 4603 mov r3, r0 8000d62: 2b00 cmp r3, #0 8000d64: d001 beq.n 8000d6a { Error_Handler(); 8000d66: f7ff ff1c bl 8000ba2 } /* USER CODE BEGIN TIM1_Init 2 */ /* USER CODE END TIM1_Init 2 */ } 8000d6a: bf00 nop 8000d6c: 3718 adds r7, #24 8000d6e: 46bd mov sp, r7 8000d70: bd80 pop {r7, pc} 8000d72: bf00 nop 8000d74: 20000090 .word 0x20000090 8000d78: 40012c00 .word 0x40012c00 08000d7c : void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* tim_baseHandle) { 8000d7c: b480 push {r7} 8000d7e: b085 sub sp, #20 8000d80: af00 add r7, sp, #0 8000d82: 6078 str r0, [r7, #4] if(tim_baseHandle->Instance==TIM1) 8000d84: 687b ldr r3, [r7, #4] 8000d86: 681b ldr r3, [r3, #0] 8000d88: 4a09 ldr r2, [pc, #36] ; (8000db0 ) 8000d8a: 4293 cmp r3, r2 8000d8c: d10b bne.n 8000da6 { /* USER CODE BEGIN TIM1_MspInit 0 */ /* USER CODE END TIM1_MspInit 0 */ /* TIM1 clock enable */ __HAL_RCC_TIM1_CLK_ENABLE(); 8000d8e: 4b09 ldr r3, [pc, #36] ; (8000db4 ) 8000d90: 699b ldr r3, [r3, #24] 8000d92: 4a08 ldr r2, [pc, #32] ; (8000db4 ) 8000d94: f443 6300 orr.w r3, r3, #2048 ; 0x800 8000d98: 6193 str r3, [r2, #24] 8000d9a: 4b06 ldr r3, [pc, #24] ; (8000db4 ) 8000d9c: 699b ldr r3, [r3, #24] 8000d9e: f403 6300 and.w r3, r3, #2048 ; 0x800 8000da2: 60fb str r3, [r7, #12] 8000da4: 68fb ldr r3, [r7, #12] /* USER CODE BEGIN TIM1_MspInit 1 */ /* USER CODE END TIM1_MspInit 1 */ } } 8000da6: bf00 nop 8000da8: 3714 adds r7, #20 8000daa: 46bd mov sp, r7 8000dac: bc80 pop {r7} 8000dae: 4770 bx lr 8000db0: 40012c00 .word 0x40012c00 8000db4: 40021000 .word 0x40021000 08000db8 : UART_HandleTypeDef huart2; /* USART2 init function */ void MX_USART2_UART_Init(void) { 8000db8: b580 push {r7, lr} 8000dba: af00 add r7, sp, #0 /* USER CODE END USART2_Init 0 */ /* USER CODE BEGIN USART2_Init 1 */ /* USER CODE END USART2_Init 1 */ huart2.Instance = USART2; 8000dbc: 4b11 ldr r3, [pc, #68] ; (8000e04 ) 8000dbe: 4a12 ldr r2, [pc, #72] ; (8000e08 ) 8000dc0: 601a str r2, [r3, #0] huart2.Init.BaudRate = 115200; 8000dc2: 4b10 ldr r3, [pc, #64] ; (8000e04 ) 8000dc4: f44f 32e1 mov.w r2, #115200 ; 0x1c200 8000dc8: 605a str r2, [r3, #4] huart2.Init.WordLength = UART_WORDLENGTH_8B; 8000dca: 4b0e ldr r3, [pc, #56] ; (8000e04 ) 8000dcc: 2200 movs r2, #0 8000dce: 609a str r2, [r3, #8] huart2.Init.StopBits = UART_STOPBITS_1; 8000dd0: 4b0c ldr r3, [pc, #48] ; (8000e04 ) 8000dd2: 2200 movs r2, #0 8000dd4: 60da str r2, [r3, #12] huart2.Init.Parity = UART_PARITY_NONE; 8000dd6: 4b0b ldr r3, [pc, #44] ; (8000e04 ) 8000dd8: 2200 movs r2, #0 8000dda: 611a str r2, [r3, #16] huart2.Init.Mode = UART_MODE_TX_RX; 8000ddc: 4b09 ldr r3, [pc, #36] ; (8000e04 ) 8000dde: 220c movs r2, #12 8000de0: 615a str r2, [r3, #20] huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE; 8000de2: 4b08 ldr r3, [pc, #32] ; (8000e04 ) 8000de4: 2200 movs r2, #0 8000de6: 619a str r2, [r3, #24] huart2.Init.OverSampling = UART_OVERSAMPLING_16; 8000de8: 4b06 ldr r3, [pc, #24] ; (8000e04 ) 8000dea: 2200 movs r2, #0 8000dec: 61da str r2, [r3, #28] if (HAL_UART_Init(&huart2) != HAL_OK) 8000dee: 4805 ldr r0, [pc, #20] ; (8000e04 ) 8000df0: f001 fa8e bl 8002310 8000df4: 4603 mov r3, r0 8000df6: 2b00 cmp r3, #0 8000df8: d001 beq.n 8000dfe { Error_Handler(); 8000dfa: f7ff fed2 bl 8000ba2 } /* USER CODE BEGIN USART2_Init 2 */ /* USER CODE END USART2_Init 2 */ } 8000dfe: bf00 nop 8000e00: bd80 pop {r7, pc} 8000e02: bf00 nop 8000e04: 200000d8 .word 0x200000d8 8000e08: 40004400 .word 0x40004400 08000e0c : void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle) { 8000e0c: b580 push {r7, lr} 8000e0e: b088 sub sp, #32 8000e10: af00 add r7, sp, #0 8000e12: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8000e14: f107 0310 add.w r3, r7, #16 8000e18: 2200 movs r2, #0 8000e1a: 601a str r2, [r3, #0] 8000e1c: 605a str r2, [r3, #4] 8000e1e: 609a str r2, [r3, #8] 8000e20: 60da str r2, [r3, #12] if(uartHandle->Instance==USART2) 8000e22: 687b ldr r3, [r7, #4] 8000e24: 681b ldr r3, [r3, #0] 8000e26: 4a1b ldr r2, [pc, #108] ; (8000e94 ) 8000e28: 4293 cmp r3, r2 8000e2a: d12f bne.n 8000e8c { /* USER CODE BEGIN USART2_MspInit 0 */ /* USER CODE END USART2_MspInit 0 */ /* USART2 clock enable */ __HAL_RCC_USART2_CLK_ENABLE(); 8000e2c: 4b1a ldr r3, [pc, #104] ; (8000e98 ) 8000e2e: 69db ldr r3, [r3, #28] 8000e30: 4a19 ldr r2, [pc, #100] ; (8000e98 ) 8000e32: f443 3300 orr.w r3, r3, #131072 ; 0x20000 8000e36: 61d3 str r3, [r2, #28] 8000e38: 4b17 ldr r3, [pc, #92] ; (8000e98 ) 8000e3a: 69db ldr r3, [r3, #28] 8000e3c: f403 3300 and.w r3, r3, #131072 ; 0x20000 8000e40: 60fb str r3, [r7, #12] 8000e42: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOA_CLK_ENABLE(); 8000e44: 4b14 ldr r3, [pc, #80] ; (8000e98 ) 8000e46: 699b ldr r3, [r3, #24] 8000e48: 4a13 ldr r2, [pc, #76] ; (8000e98 ) 8000e4a: f043 0304 orr.w r3, r3, #4 8000e4e: 6193 str r3, [r2, #24] 8000e50: 4b11 ldr r3, [pc, #68] ; (8000e98 ) 8000e52: 699b ldr r3, [r3, #24] 8000e54: f003 0304 and.w r3, r3, #4 8000e58: 60bb str r3, [r7, #8] 8000e5a: 68bb ldr r3, [r7, #8] /**USART2 GPIO Configuration PA2 ------> USART2_TX PA3 ------> USART2_RX */ GPIO_InitStruct.Pin = GPIO_PIN_2; 8000e5c: 2304 movs r3, #4 8000e5e: 613b str r3, [r7, #16] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8000e60: 2302 movs r3, #2 8000e62: 617b str r3, [r7, #20] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 8000e64: 2303 movs r3, #3 8000e66: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8000e68: f107 0310 add.w r3, r7, #16 8000e6c: 4619 mov r1, r3 8000e6e: 480b ldr r0, [pc, #44] ; (8000e9c ) 8000e70: f000 f9a6 bl 80011c0 GPIO_InitStruct.Pin = GPIO_PIN_3; 8000e74: 2308 movs r3, #8 8000e76: 613b str r3, [r7, #16] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 8000e78: 2300 movs r3, #0 8000e7a: 617b str r3, [r7, #20] GPIO_InitStruct.Pull = GPIO_NOPULL; 8000e7c: 2300 movs r3, #0 8000e7e: 61bb str r3, [r7, #24] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8000e80: f107 0310 add.w r3, r7, #16 8000e84: 4619 mov r1, r3 8000e86: 4805 ldr r0, [pc, #20] ; (8000e9c ) 8000e88: f000 f99a bl 80011c0 /* USER CODE BEGIN USART2_MspInit 1 */ /* USER CODE END USART2_MspInit 1 */ } } 8000e8c: bf00 nop 8000e8e: 3720 adds r7, #32 8000e90: 46bd mov sp, r7 8000e92: bd80 pop {r7, pc} 8000e94: 40004400 .word 0x40004400 8000e98: 40021000 .word 0x40021000 8000e9c: 40010800 .word 0x40010800 08000ea0 : .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata 8000ea0: 480c ldr r0, [pc, #48] ; (8000ed4 ) ldr r1, =_edata 8000ea2: 490d ldr r1, [pc, #52] ; (8000ed8 ) ldr r2, =_sidata 8000ea4: 4a0d ldr r2, [pc, #52] ; (8000edc ) movs r3, #0 8000ea6: 2300 movs r3, #0 b LoopCopyDataInit 8000ea8: e002 b.n 8000eb0 08000eaa : CopyDataInit: ldr r4, [r2, r3] 8000eaa: 58d4 ldr r4, [r2, r3] str r4, [r0, r3] 8000eac: 50c4 str r4, [r0, r3] adds r3, r3, #4 8000eae: 3304 adds r3, #4 08000eb0 : LoopCopyDataInit: adds r4, r0, r3 8000eb0: 18c4 adds r4, r0, r3 cmp r4, r1 8000eb2: 428c cmp r4, r1 bcc CopyDataInit 8000eb4: d3f9 bcc.n 8000eaa /* Zero fill the bss segment. */ ldr r2, =_sbss 8000eb6: 4a0a ldr r2, [pc, #40] ; (8000ee0 ) ldr r4, =_ebss 8000eb8: 4c0a ldr r4, [pc, #40] ; (8000ee4 ) movs r3, #0 8000eba: 2300 movs r3, #0 b LoopFillZerobss 8000ebc: e001 b.n 8000ec2 08000ebe : FillZerobss: str r3, [r2] 8000ebe: 6013 str r3, [r2, #0] adds r2, r2, #4 8000ec0: 3204 adds r2, #4 08000ec2 : LoopFillZerobss: cmp r2, r4 8000ec2: 42a2 cmp r2, r4 bcc FillZerobss 8000ec4: d3fb bcc.n 8000ebe /* Call the clock system intitialization function.*/ bl SystemInit 8000ec6: f7ff ff01 bl 8000ccc /* Call static constructors */ bl __libc_init_array 8000eca: f001 fbdf bl 800268c <__libc_init_array> /* Call the application's entry point.*/ bl main 8000ece: f7ff fda7 bl 8000a20

bx lr 8000ed2: 4770 bx lr ldr r0, =_sdata 8000ed4: 20000000 .word 0x20000000 ldr r1, =_edata 8000ed8: 20000070 .word 0x20000070 ldr r2, =_sidata 8000edc: 08003064 .word 0x08003064 ldr r2, =_sbss 8000ee0: 20000070 .word 0x20000070 ldr r4, =_ebss 8000ee4: 20000130 .word 0x20000130 08000ee8 : * @retval : None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop 8000ee8: e7fe b.n 8000ee8 ... 08000eec : * need to ensure that the SysTick time base is always set to 1 millisecond * to have correct HAL operation. * @retval HAL status */ HAL_StatusTypeDef HAL_Init(void) { 8000eec: b580 push {r7, lr} 8000eee: af00 add r7, sp, #0 defined(STM32F102x6) || defined(STM32F102xB) || \ defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || \ defined(STM32F105xC) || defined(STM32F107xC) /* Prefetch buffer is not available on value line devices */ __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); 8000ef0: 4b08 ldr r3, [pc, #32] ; (8000f14 ) 8000ef2: 681b ldr r3, [r3, #0] 8000ef4: 4a07 ldr r2, [pc, #28] ; (8000f14 ) 8000ef6: f043 0310 orr.w r3, r3, #16 8000efa: 6013 str r3, [r2, #0] #endif #endif /* PREFETCH_ENABLE */ /* Set Interrupt Group Priority */ HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); 8000efc: 2003 movs r0, #3 8000efe: f000 f92b bl 8001158 /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ HAL_InitTick(TICK_INT_PRIORITY); 8000f02: 200f movs r0, #15 8000f04: f000 f808 bl 8000f18 /* Init the low level hardware */ HAL_MspInit(); 8000f08: f7ff fe50 bl 8000bac /* Return function status */ return HAL_OK; 8000f0c: 2300 movs r3, #0 } 8000f0e: 4618 mov r0, r3 8000f10: bd80 pop {r7, pc} 8000f12: bf00 nop 8000f14: 40022000 .word 0x40022000 08000f18 : * implementation in user file. * @param TickPriority Tick interrupt priority. * @retval HAL status */ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { 8000f18: b580 push {r7, lr} 8000f1a: b082 sub sp, #8 8000f1c: af00 add r7, sp, #0 8000f1e: 6078 str r0, [r7, #4] /* Configure the SysTick to have interrupt in 1ms time basis*/ if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U) 8000f20: 4b12 ldr r3, [pc, #72] ; (8000f6c ) 8000f22: 681a ldr r2, [r3, #0] 8000f24: 4b12 ldr r3, [pc, #72] ; (8000f70 ) 8000f26: 781b ldrb r3, [r3, #0] 8000f28: 4619 mov r1, r3 8000f2a: f44f 737a mov.w r3, #1000 ; 0x3e8 8000f2e: fbb3 f3f1 udiv r3, r3, r1 8000f32: fbb2 f3f3 udiv r3, r2, r3 8000f36: 4618 mov r0, r3 8000f38: f000 f935 bl 80011a6 8000f3c: 4603 mov r3, r0 8000f3e: 2b00 cmp r3, #0 8000f40: d001 beq.n 8000f46 { return HAL_ERROR; 8000f42: 2301 movs r3, #1 8000f44: e00e b.n 8000f64 } /* Configure the SysTick IRQ priority */ if (TickPriority < (1UL << __NVIC_PRIO_BITS)) 8000f46: 687b ldr r3, [r7, #4] 8000f48: 2b0f cmp r3, #15 8000f4a: d80a bhi.n 8000f62 { HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); 8000f4c: 2200 movs r2, #0 8000f4e: 6879 ldr r1, [r7, #4] 8000f50: f04f 30ff mov.w r0, #4294967295 8000f54: f000 f90b bl 800116e uwTickPrio = TickPriority; 8000f58: 4a06 ldr r2, [pc, #24] ; (8000f74 ) 8000f5a: 687b ldr r3, [r7, #4] 8000f5c: 6013 str r3, [r2, #0] { return HAL_ERROR; } /* Return function status */ return HAL_OK; 8000f5e: 2300 movs r3, #0 8000f60: e000 b.n 8000f64 return HAL_ERROR; 8000f62: 2301 movs r3, #1 } 8000f64: 4618 mov r0, r3 8000f66: 3708 adds r7, #8 8000f68: 46bd mov sp, r7 8000f6a: bd80 pop {r7, pc} 8000f6c: 20000000 .word 0x20000000 8000f70: 20000008 .word 0x20000008 8000f74: 20000004 .word 0x20000004 08000f78 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ __weak void HAL_IncTick(void) { 8000f78: b480 push {r7} 8000f7a: af00 add r7, sp, #0 uwTick += uwTickFreq; 8000f7c: 4b05 ldr r3, [pc, #20] ; (8000f94 ) 8000f7e: 781b ldrb r3, [r3, #0] 8000f80: 461a mov r2, r3 8000f82: 4b05 ldr r3, [pc, #20] ; (8000f98 ) 8000f84: 681b ldr r3, [r3, #0] 8000f86: 4413 add r3, r2 8000f88: 4a03 ldr r2, [pc, #12] ; (8000f98 ) 8000f8a: 6013 str r3, [r2, #0] } 8000f8c: bf00 nop 8000f8e: 46bd mov sp, r7 8000f90: bc80 pop {r7} 8000f92: 4770 bx lr 8000f94: 20000008 .word 0x20000008 8000f98: 2000011c .word 0x2000011c 08000f9c : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval tick value */ __weak uint32_t HAL_GetTick(void) { 8000f9c: b480 push {r7} 8000f9e: af00 add r7, sp, #0 return uwTick; 8000fa0: 4b02 ldr r3, [pc, #8] ; (8000fac ) 8000fa2: 681b ldr r3, [r3, #0] } 8000fa4: 4618 mov r0, r3 8000fa6: 46bd mov sp, r7 8000fa8: bc80 pop {r7} 8000faa: 4770 bx lr 8000fac: 2000011c .word 0x2000011c 08000fb0 : * implementations in user file. * @param Delay specifies the delay time length, in milliseconds. * @retval None */ __weak void HAL_Delay(uint32_t Delay) { 8000fb0: b580 push {r7, lr} 8000fb2: b084 sub sp, #16 8000fb4: af00 add r7, sp, #0 8000fb6: 6078 str r0, [r7, #4] uint32_t tickstart = HAL_GetTick(); 8000fb8: f7ff fff0 bl 8000f9c 8000fbc: 60b8 str r0, [r7, #8] uint32_t wait = Delay; 8000fbe: 687b ldr r3, [r7, #4] 8000fc0: 60fb str r3, [r7, #12] /* Add a freq to guarantee minimum wait */ if (wait < HAL_MAX_DELAY) 8000fc2: 68fb ldr r3, [r7, #12] 8000fc4: f1b3 3fff cmp.w r3, #4294967295 8000fc8: d005 beq.n 8000fd6 { wait += (uint32_t)(uwTickFreq); 8000fca: 4b0a ldr r3, [pc, #40] ; (8000ff4 ) 8000fcc: 781b ldrb r3, [r3, #0] 8000fce: 461a mov r2, r3 8000fd0: 68fb ldr r3, [r7, #12] 8000fd2: 4413 add r3, r2 8000fd4: 60fb str r3, [r7, #12] } while ((HAL_GetTick() - tickstart) < wait) 8000fd6: bf00 nop 8000fd8: f7ff ffe0 bl 8000f9c 8000fdc: 4602 mov r2, r0 8000fde: 68bb ldr r3, [r7, #8] 8000fe0: 1ad3 subs r3, r2, r3 8000fe2: 68fa ldr r2, [r7, #12] 8000fe4: 429a cmp r2, r3 8000fe6: d8f7 bhi.n 8000fd8 { } } 8000fe8: bf00 nop 8000fea: bf00 nop 8000fec: 3710 adds r7, #16 8000fee: 46bd mov sp, r7 8000ff0: bd80 pop {r7, pc} 8000ff2: bf00 nop 8000ff4: 20000008 .word 0x20000008 08000ff8 <__NVIC_SetPriorityGrouping>: In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 8000ff8: b480 push {r7} 8000ffa: b085 sub sp, #20 8000ffc: af00 add r7, sp, #0 8000ffe: 6078 str r0, [r7, #4] uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 8001000: 687b ldr r3, [r7, #4] 8001002: f003 0307 and.w r3, r3, #7 8001006: 60fb str r3, [r7, #12] reg_value = SCB->AIRCR; /* read old register configuration */ 8001008: 4b0c ldr r3, [pc, #48] ; (800103c <__NVIC_SetPriorityGrouping+0x44>) 800100a: 68db ldr r3, [r3, #12] 800100c: 60bb str r3, [r7, #8] reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ 800100e: 68ba ldr r2, [r7, #8] 8001010: f64f 03ff movw r3, #63743 ; 0xf8ff 8001014: 4013 ands r3, r2 8001016: 60bb str r3, [r7, #8] reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ 8001018: 68fb ldr r3, [r7, #12] 800101a: 021a lsls r2, r3, #8 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 800101c: 68bb ldr r3, [r7, #8] 800101e: 4313 orrs r3, r2 reg_value = (reg_value | 8001020: f043 63bf orr.w r3, r3, #100139008 ; 0x5f80000 8001024: f443 3300 orr.w r3, r3, #131072 ; 0x20000 8001028: 60bb str r3, [r7, #8] SCB->AIRCR = reg_value; 800102a: 4a04 ldr r2, [pc, #16] ; (800103c <__NVIC_SetPriorityGrouping+0x44>) 800102c: 68bb ldr r3, [r7, #8] 800102e: 60d3 str r3, [r2, #12] } 8001030: bf00 nop 8001032: 3714 adds r7, #20 8001034: 46bd mov sp, r7 8001036: bc80 pop {r7} 8001038: 4770 bx lr 800103a: bf00 nop 800103c: e000ed00 .word 0xe000ed00 08001040 <__NVIC_GetPriorityGrouping>: \brief Get Priority Grouping \details Reads the priority grouping field from the NVIC Interrupt Controller. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) { 8001040: b480 push {r7} 8001042: af00 add r7, sp, #0 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); 8001044: 4b04 ldr r3, [pc, #16] ; (8001058 <__NVIC_GetPriorityGrouping+0x18>) 8001046: 68db ldr r3, [r3, #12] 8001048: 0a1b lsrs r3, r3, #8 800104a: f003 0307 and.w r3, r3, #7 } 800104e: 4618 mov r0, r3 8001050: 46bd mov sp, r7 8001052: bc80 pop {r7} 8001054: 4770 bx lr 8001056: bf00 nop 8001058: e000ed00 .word 0xe000ed00 0800105c <__NVIC_SetPriority>: \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { 800105c: b480 push {r7} 800105e: b083 sub sp, #12 8001060: af00 add r7, sp, #0 8001062: 4603 mov r3, r0 8001064: 6039 str r1, [r7, #0] 8001066: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) 8001068: f997 3007 ldrsb.w r3, [r7, #7] 800106c: 2b00 cmp r3, #0 800106e: db0a blt.n 8001086 <__NVIC_SetPriority+0x2a> { NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 8001070: 683b ldr r3, [r7, #0] 8001072: b2da uxtb r2, r3 8001074: 490c ldr r1, [pc, #48] ; (80010a8 <__NVIC_SetPriority+0x4c>) 8001076: f997 3007 ldrsb.w r3, [r7, #7] 800107a: 0112 lsls r2, r2, #4 800107c: b2d2 uxtb r2, r2 800107e: 440b add r3, r1 8001080: f883 2300 strb.w r2, [r3, #768] ; 0x300 } else { SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } 8001084: e00a b.n 800109c <__NVIC_SetPriority+0x40> SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 8001086: 683b ldr r3, [r7, #0] 8001088: b2da uxtb r2, r3 800108a: 4908 ldr r1, [pc, #32] ; (80010ac <__NVIC_SetPriority+0x50>) 800108c: 79fb ldrb r3, [r7, #7] 800108e: f003 030f and.w r3, r3, #15 8001092: 3b04 subs r3, #4 8001094: 0112 lsls r2, r2, #4 8001096: b2d2 uxtb r2, r2 8001098: 440b add r3, r1 800109a: 761a strb r2, [r3, #24] } 800109c: bf00 nop 800109e: 370c adds r7, #12 80010a0: 46bd mov sp, r7 80010a2: bc80 pop {r7} 80010a4: 4770 bx lr 80010a6: bf00 nop 80010a8: e000e100 .word 0xe000e100 80010ac: e000ed00 .word 0xe000ed00 080010b0 : \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { 80010b0: b480 push {r7} 80010b2: b089 sub sp, #36 ; 0x24 80010b4: af00 add r7, sp, #0 80010b6: 60f8 str r0, [r7, #12] 80010b8: 60b9 str r1, [r7, #8] 80010ba: 607a str r2, [r7, #4] uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 80010bc: 68fb ldr r3, [r7, #12] 80010be: f003 0307 and.w r3, r3, #7 80010c2: 61fb str r3, [r7, #28] uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 80010c4: 69fb ldr r3, [r7, #28] 80010c6: f1c3 0307 rsb r3, r3, #7 80010ca: 2b04 cmp r3, #4 80010cc: bf28 it cs 80010ce: 2304 movcs r3, #4 80010d0: 61bb str r3, [r7, #24] SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 80010d2: 69fb ldr r3, [r7, #28] 80010d4: 3304 adds r3, #4 80010d6: 2b06 cmp r3, #6 80010d8: d902 bls.n 80010e0 80010da: 69fb ldr r3, [r7, #28] 80010dc: 3b03 subs r3, #3 80010de: e000 b.n 80010e2 80010e0: 2300 movs r3, #0 80010e2: 617b str r3, [r7, #20] return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 80010e4: f04f 32ff mov.w r2, #4294967295 80010e8: 69bb ldr r3, [r7, #24] 80010ea: fa02 f303 lsl.w r3, r2, r3 80010ee: 43da mvns r2, r3 80010f0: 68bb ldr r3, [r7, #8] 80010f2: 401a ands r2, r3 80010f4: 697b ldr r3, [r7, #20] 80010f6: 409a lsls r2, r3 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) 80010f8: f04f 31ff mov.w r1, #4294967295 80010fc: 697b ldr r3, [r7, #20] 80010fe: fa01 f303 lsl.w r3, r1, r3 8001102: 43d9 mvns r1, r3 8001104: 687b ldr r3, [r7, #4] 8001106: 400b ands r3, r1 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 8001108: 4313 orrs r3, r2 ); } 800110a: 4618 mov r0, r3 800110c: 3724 adds r7, #36 ; 0x24 800110e: 46bd mov sp, r7 8001110: bc80 pop {r7} 8001112: 4770 bx lr 08001114 : \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { 8001114: b580 push {r7, lr} 8001116: b082 sub sp, #8 8001118: af00 add r7, sp, #0 800111a: 6078 str r0, [r7, #4] if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) 800111c: 687b ldr r3, [r7, #4] 800111e: 3b01 subs r3, #1 8001120: f1b3 7f80 cmp.w r3, #16777216 ; 0x1000000 8001124: d301 bcc.n 800112a { return (1UL); /* Reload value impossible */ 8001126: 2301 movs r3, #1 8001128: e00f b.n 800114a } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 800112a: 4a0a ldr r2, [pc, #40] ; (8001154 ) 800112c: 687b ldr r3, [r7, #4] 800112e: 3b01 subs r3, #1 8001130: 6053 str r3, [r2, #4] NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ 8001132: 210f movs r1, #15 8001134: f04f 30ff mov.w r0, #4294967295 8001138: f7ff ff90 bl 800105c <__NVIC_SetPriority> SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ 800113c: 4b05 ldr r3, [pc, #20] ; (8001154 ) 800113e: 2200 movs r2, #0 8001140: 609a str r2, [r3, #8] SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 8001142: 4b04 ldr r3, [pc, #16] ; (8001154 ) 8001144: 2207 movs r2, #7 8001146: 601a str r2, [r3, #0] SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ 8001148: 2300 movs r3, #0 } 800114a: 4618 mov r0, r3 800114c: 3708 adds r7, #8 800114e: 46bd mov sp, r7 8001150: bd80 pop {r7, pc} 8001152: bf00 nop 8001154: e000e010 .word 0xe000e010 08001158 : * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. * The pending IRQ priority will be managed only by the subpriority. * @retval None */ void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 8001158: b580 push {r7, lr} 800115a: b082 sub sp, #8 800115c: af00 add r7, sp, #0 800115e: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ NVIC_SetPriorityGrouping(PriorityGroup); 8001160: 6878 ldr r0, [r7, #4] 8001162: f7ff ff49 bl 8000ff8 <__NVIC_SetPriorityGrouping> } 8001166: bf00 nop 8001168: 3708 adds r7, #8 800116a: 46bd mov sp, r7 800116c: bd80 pop {r7, pc} 0800116e : * This parameter can be a value between 0 and 15 * A lower priority value indicates a higher priority. * @retval None */ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) { 800116e: b580 push {r7, lr} 8001170: b086 sub sp, #24 8001172: af00 add r7, sp, #0 8001174: 4603 mov r3, r0 8001176: 60b9 str r1, [r7, #8] 8001178: 607a str r2, [r7, #4] 800117a: 73fb strb r3, [r7, #15] uint32_t prioritygroup = 0x00U; 800117c: 2300 movs r3, #0 800117e: 617b str r3, [r7, #20] /* Check the parameters */ assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); prioritygroup = NVIC_GetPriorityGrouping(); 8001180: f7ff ff5e bl 8001040 <__NVIC_GetPriorityGrouping> 8001184: 6178 str r0, [r7, #20] NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); 8001186: 687a ldr r2, [r7, #4] 8001188: 68b9 ldr r1, [r7, #8] 800118a: 6978 ldr r0, [r7, #20] 800118c: f7ff ff90 bl 80010b0 8001190: 4602 mov r2, r0 8001192: f997 300f ldrsb.w r3, [r7, #15] 8001196: 4611 mov r1, r2 8001198: 4618 mov r0, r3 800119a: f7ff ff5f bl 800105c <__NVIC_SetPriority> } 800119e: bf00 nop 80011a0: 3718 adds r7, #24 80011a2: 46bd mov sp, r7 80011a4: bd80 pop {r7, pc} 080011a6 : * @param TicksNumb: Specifies the ticks Number of ticks between two interrupts. * @retval status: - 0 Function succeeded. * - 1 Function failed. */ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) { 80011a6: b580 push {r7, lr} 80011a8: b082 sub sp, #8 80011aa: af00 add r7, sp, #0 80011ac: 6078 str r0, [r7, #4] return SysTick_Config(TicksNumb); 80011ae: 6878 ldr r0, [r7, #4] 80011b0: f7ff ffb0 bl 8001114 80011b4: 4603 mov r3, r0 } 80011b6: 4618 mov r0, r3 80011b8: 3708 adds r7, #8 80011ba: 46bd mov sp, r7 80011bc: bd80 pop {r7, pc} ... 080011c0 : * @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains * the configuration information for the specified GPIO peripheral. * @retval None */ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) { 80011c0: b480 push {r7} 80011c2: b08b sub sp, #44 ; 0x2c 80011c4: af00 add r7, sp, #0 80011c6: 6078 str r0, [r7, #4] 80011c8: 6039 str r1, [r7, #0] uint32_t position = 0x00u; 80011ca: 2300 movs r3, #0 80011cc: 627b str r3, [r7, #36] ; 0x24 uint32_t ioposition; uint32_t iocurrent; uint32_t temp; uint32_t config = 0x00u; 80011ce: 2300 movs r3, #0 80011d0: 623b str r3, [r7, #32] assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); /* Configure the port pins */ while (((GPIO_Init->Pin) >> position) != 0x00u) 80011d2: e169 b.n 80014a8 { /* Get the IO position */ ioposition = (0x01uL << position); 80011d4: 2201 movs r2, #1 80011d6: 6a7b ldr r3, [r7, #36] ; 0x24 80011d8: fa02 f303 lsl.w r3, r2, r3 80011dc: 61fb str r3, [r7, #28] /* Get the current IO position */ iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition; 80011de: 683b ldr r3, [r7, #0] 80011e0: 681b ldr r3, [r3, #0] 80011e2: 69fa ldr r2, [r7, #28] 80011e4: 4013 ands r3, r2 80011e6: 61bb str r3, [r7, #24] if (iocurrent == ioposition) 80011e8: 69ba ldr r2, [r7, #24] 80011ea: 69fb ldr r3, [r7, #28] 80011ec: 429a cmp r2, r3 80011ee: f040 8158 bne.w 80014a2 { /* Check the Alternate function parameters */ assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); /* Based on the required mode, filling config variable with MODEy[1:0] and CNFy[3:2] corresponding bits */ switch (GPIO_Init->Mode) 80011f2: 683b ldr r3, [r7, #0] 80011f4: 685b ldr r3, [r3, #4] 80011f6: 4a9a ldr r2, [pc, #616] ; (8001460 ) 80011f8: 4293 cmp r3, r2 80011fa: d05e beq.n 80012ba 80011fc: 4a98 ldr r2, [pc, #608] ; (8001460 ) 80011fe: 4293 cmp r3, r2 8001200: d875 bhi.n 80012ee 8001202: 4a98 ldr r2, [pc, #608] ; (8001464 ) 8001204: 4293 cmp r3, r2 8001206: d058 beq.n 80012ba 8001208: 4a96 ldr r2, [pc, #600] ; (8001464 ) 800120a: 4293 cmp r3, r2 800120c: d86f bhi.n 80012ee 800120e: 4a96 ldr r2, [pc, #600] ; (8001468 ) 8001210: 4293 cmp r3, r2 8001212: d052 beq.n 80012ba 8001214: 4a94 ldr r2, [pc, #592] ; (8001468 ) 8001216: 4293 cmp r3, r2 8001218: d869 bhi.n 80012ee 800121a: 4a94 ldr r2, [pc, #592] ; (800146c ) 800121c: 4293 cmp r3, r2 800121e: d04c beq.n 80012ba 8001220: 4a92 ldr r2, [pc, #584] ; (800146c ) 8001222: 4293 cmp r3, r2 8001224: d863 bhi.n 80012ee 8001226: 4a92 ldr r2, [pc, #584] ; (8001470 ) 8001228: 4293 cmp r3, r2 800122a: d046 beq.n 80012ba 800122c: 4a90 ldr r2, [pc, #576] ; (8001470 ) 800122e: 4293 cmp r3, r2 8001230: d85d bhi.n 80012ee 8001232: 2b12 cmp r3, #18 8001234: d82a bhi.n 800128c 8001236: 2b12 cmp r3, #18 8001238: d859 bhi.n 80012ee 800123a: a201 add r2, pc, #4 ; (adr r2, 8001240 ) 800123c: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8001240: 080012bb .word 0x080012bb 8001244: 08001295 .word 0x08001295 8001248: 080012a7 .word 0x080012a7 800124c: 080012e9 .word 0x080012e9 8001250: 080012ef .word 0x080012ef 8001254: 080012ef .word 0x080012ef 8001258: 080012ef .word 0x080012ef 800125c: 080012ef .word 0x080012ef 8001260: 080012ef .word 0x080012ef 8001264: 080012ef .word 0x080012ef 8001268: 080012ef .word 0x080012ef 800126c: 080012ef .word 0x080012ef 8001270: 080012ef .word 0x080012ef 8001274: 080012ef .word 0x080012ef 8001278: 080012ef .word 0x080012ef 800127c: 080012ef .word 0x080012ef 8001280: 080012ef .word 0x080012ef 8001284: 0800129d .word 0x0800129d 8001288: 080012b1 .word 0x080012b1 800128c: 4a79 ldr r2, [pc, #484] ; (8001474 ) 800128e: 4293 cmp r3, r2 8001290: d013 beq.n 80012ba config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG; break; /* Parameters are checked with assert_param */ default: break; 8001292: e02c b.n 80012ee config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_PP; 8001294: 683b ldr r3, [r7, #0] 8001296: 68db ldr r3, [r3, #12] 8001298: 623b str r3, [r7, #32] break; 800129a: e029 b.n 80012f0 config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_OD; 800129c: 683b ldr r3, [r7, #0] 800129e: 68db ldr r3, [r3, #12] 80012a0: 3304 adds r3, #4 80012a2: 623b str r3, [r7, #32] break; 80012a4: e024 b.n 80012f0 config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_PP; 80012a6: 683b ldr r3, [r7, #0] 80012a8: 68db ldr r3, [r3, #12] 80012aa: 3308 adds r3, #8 80012ac: 623b str r3, [r7, #32] break; 80012ae: e01f b.n 80012f0 config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_OD; 80012b0: 683b ldr r3, [r7, #0] 80012b2: 68db ldr r3, [r3, #12] 80012b4: 330c adds r3, #12 80012b6: 623b str r3, [r7, #32] break; 80012b8: e01a b.n 80012f0 if (GPIO_Init->Pull == GPIO_NOPULL) 80012ba: 683b ldr r3, [r7, #0] 80012bc: 689b ldr r3, [r3, #8] 80012be: 2b00 cmp r3, #0 80012c0: d102 bne.n 80012c8 config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_FLOATING; 80012c2: 2304 movs r3, #4 80012c4: 623b str r3, [r7, #32] break; 80012c6: e013 b.n 80012f0 else if (GPIO_Init->Pull == GPIO_PULLUP) 80012c8: 683b ldr r3, [r7, #0] 80012ca: 689b ldr r3, [r3, #8] 80012cc: 2b01 cmp r3, #1 80012ce: d105 bne.n 80012dc config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD; 80012d0: 2308 movs r3, #8 80012d2: 623b str r3, [r7, #32] GPIOx->BSRR = ioposition; 80012d4: 687b ldr r3, [r7, #4] 80012d6: 69fa ldr r2, [r7, #28] 80012d8: 611a str r2, [r3, #16] break; 80012da: e009 b.n 80012f0 config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD; 80012dc: 2308 movs r3, #8 80012de: 623b str r3, [r7, #32] GPIOx->BRR = ioposition; 80012e0: 687b ldr r3, [r7, #4] 80012e2: 69fa ldr r2, [r7, #28] 80012e4: 615a str r2, [r3, #20] break; 80012e6: e003 b.n 80012f0 config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG; 80012e8: 2300 movs r3, #0 80012ea: 623b str r3, [r7, #32] break; 80012ec: e000 b.n 80012f0 break; 80012ee: bf00 nop } /* Check if the current bit belongs to first half or last half of the pin count number in order to address CRH or CRL register*/ configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL : &GPIOx->CRH; 80012f0: 69bb ldr r3, [r7, #24] 80012f2: 2bff cmp r3, #255 ; 0xff 80012f4: d801 bhi.n 80012fa 80012f6: 687b ldr r3, [r7, #4] 80012f8: e001 b.n 80012fe 80012fa: 687b ldr r3, [r7, #4] 80012fc: 3304 adds r3, #4 80012fe: 617b str r3, [r7, #20] registeroffset = (iocurrent < GPIO_PIN_8) ? (position << 2u) : ((position - 8u) << 2u); 8001300: 69bb ldr r3, [r7, #24] 8001302: 2bff cmp r3, #255 ; 0xff 8001304: d802 bhi.n 800130c 8001306: 6a7b ldr r3, [r7, #36] ; 0x24 8001308: 009b lsls r3, r3, #2 800130a: e002 b.n 8001312 800130c: 6a7b ldr r3, [r7, #36] ; 0x24 800130e: 3b08 subs r3, #8 8001310: 009b lsls r3, r3, #2 8001312: 613b str r3, [r7, #16] /* Apply the new configuration of the pin to the register */ MODIFY_REG((*configregister), ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset), (config << registeroffset)); 8001314: 697b ldr r3, [r7, #20] 8001316: 681a ldr r2, [r3, #0] 8001318: 210f movs r1, #15 800131a: 693b ldr r3, [r7, #16] 800131c: fa01 f303 lsl.w r3, r1, r3 8001320: 43db mvns r3, r3 8001322: 401a ands r2, r3 8001324: 6a39 ldr r1, [r7, #32] 8001326: 693b ldr r3, [r7, #16] 8001328: fa01 f303 lsl.w r3, r1, r3 800132c: 431a orrs r2, r3 800132e: 697b ldr r3, [r7, #20] 8001330: 601a str r2, [r3, #0] /*--------------------- EXTI Mode Configuration ------------------------*/ /* Configure the External Interrupt or event for the current IO */ if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE) 8001332: 683b ldr r3, [r7, #0] 8001334: 685b ldr r3, [r3, #4] 8001336: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 800133a: 2b00 cmp r3, #0 800133c: f000 80b1 beq.w 80014a2 { /* Enable AFIO Clock */ __HAL_RCC_AFIO_CLK_ENABLE(); 8001340: 4b4d ldr r3, [pc, #308] ; (8001478 ) 8001342: 699b ldr r3, [r3, #24] 8001344: 4a4c ldr r2, [pc, #304] ; (8001478 ) 8001346: f043 0301 orr.w r3, r3, #1 800134a: 6193 str r3, [r2, #24] 800134c: 4b4a ldr r3, [pc, #296] ; (8001478 ) 800134e: 699b ldr r3, [r3, #24] 8001350: f003 0301 and.w r3, r3, #1 8001354: 60bb str r3, [r7, #8] 8001356: 68bb ldr r3, [r7, #8] temp = AFIO->EXTICR[position >> 2u]; 8001358: 4a48 ldr r2, [pc, #288] ; (800147c ) 800135a: 6a7b ldr r3, [r7, #36] ; 0x24 800135c: 089b lsrs r3, r3, #2 800135e: 3302 adds r3, #2 8001360: f852 3023 ldr.w r3, [r2, r3, lsl #2] 8001364: 60fb str r3, [r7, #12] CLEAR_BIT(temp, (0x0Fu) << (4u * (position & 0x03u))); 8001366: 6a7b ldr r3, [r7, #36] ; 0x24 8001368: f003 0303 and.w r3, r3, #3 800136c: 009b lsls r3, r3, #2 800136e: 220f movs r2, #15 8001370: fa02 f303 lsl.w r3, r2, r3 8001374: 43db mvns r3, r3 8001376: 68fa ldr r2, [r7, #12] 8001378: 4013 ands r3, r2 800137a: 60fb str r3, [r7, #12] SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4u * (position & 0x03u))); 800137c: 687b ldr r3, [r7, #4] 800137e: 4a40 ldr r2, [pc, #256] ; (8001480 ) 8001380: 4293 cmp r3, r2 8001382: d013 beq.n 80013ac 8001384: 687b ldr r3, [r7, #4] 8001386: 4a3f ldr r2, [pc, #252] ; (8001484 ) 8001388: 4293 cmp r3, r2 800138a: d00d beq.n 80013a8 800138c: 687b ldr r3, [r7, #4] 800138e: 4a3e ldr r2, [pc, #248] ; (8001488 ) 8001390: 4293 cmp r3, r2 8001392: d007 beq.n 80013a4 8001394: 687b ldr r3, [r7, #4] 8001396: 4a3d ldr r2, [pc, #244] ; (800148c ) 8001398: 4293 cmp r3, r2 800139a: d101 bne.n 80013a0 800139c: 2303 movs r3, #3 800139e: e006 b.n 80013ae 80013a0: 2304 movs r3, #4 80013a2: e004 b.n 80013ae 80013a4: 2302 movs r3, #2 80013a6: e002 b.n 80013ae 80013a8: 2301 movs r3, #1 80013aa: e000 b.n 80013ae 80013ac: 2300 movs r3, #0 80013ae: 6a7a ldr r2, [r7, #36] ; 0x24 80013b0: f002 0203 and.w r2, r2, #3 80013b4: 0092 lsls r2, r2, #2 80013b6: 4093 lsls r3, r2 80013b8: 68fa ldr r2, [r7, #12] 80013ba: 4313 orrs r3, r2 80013bc: 60fb str r3, [r7, #12] AFIO->EXTICR[position >> 2u] = temp; 80013be: 492f ldr r1, [pc, #188] ; (800147c ) 80013c0: 6a7b ldr r3, [r7, #36] ; 0x24 80013c2: 089b lsrs r3, r3, #2 80013c4: 3302 adds r3, #2 80013c6: 68fa ldr r2, [r7, #12] 80013c8: f841 2023 str.w r2, [r1, r3, lsl #2] /* Configure the interrupt mask */ if ((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT) 80013cc: 683b ldr r3, [r7, #0] 80013ce: 685b ldr r3, [r3, #4] 80013d0: f403 3380 and.w r3, r3, #65536 ; 0x10000 80013d4: 2b00 cmp r3, #0 80013d6: d006 beq.n 80013e6 { SET_BIT(EXTI->IMR, iocurrent); 80013d8: 4b2d ldr r3, [pc, #180] ; (8001490 ) 80013da: 681a ldr r2, [r3, #0] 80013dc: 492c ldr r1, [pc, #176] ; (8001490 ) 80013de: 69bb ldr r3, [r7, #24] 80013e0: 4313 orrs r3, r2 80013e2: 600b str r3, [r1, #0] 80013e4: e006 b.n 80013f4 } else { CLEAR_BIT(EXTI->IMR, iocurrent); 80013e6: 4b2a ldr r3, [pc, #168] ; (8001490 ) 80013e8: 681a ldr r2, [r3, #0] 80013ea: 69bb ldr r3, [r7, #24] 80013ec: 43db mvns r3, r3 80013ee: 4928 ldr r1, [pc, #160] ; (8001490 ) 80013f0: 4013 ands r3, r2 80013f2: 600b str r3, [r1, #0] } /* Configure the event mask */ if ((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT) 80013f4: 683b ldr r3, [r7, #0] 80013f6: 685b ldr r3, [r3, #4] 80013f8: f403 3300 and.w r3, r3, #131072 ; 0x20000 80013fc: 2b00 cmp r3, #0 80013fe: d006 beq.n 800140e { SET_BIT(EXTI->EMR, iocurrent); 8001400: 4b23 ldr r3, [pc, #140] ; (8001490 ) 8001402: 685a ldr r2, [r3, #4] 8001404: 4922 ldr r1, [pc, #136] ; (8001490 ) 8001406: 69bb ldr r3, [r7, #24] 8001408: 4313 orrs r3, r2 800140a: 604b str r3, [r1, #4] 800140c: e006 b.n 800141c } else { CLEAR_BIT(EXTI->EMR, iocurrent); 800140e: 4b20 ldr r3, [pc, #128] ; (8001490 ) 8001410: 685a ldr r2, [r3, #4] 8001412: 69bb ldr r3, [r7, #24] 8001414: 43db mvns r3, r3 8001416: 491e ldr r1, [pc, #120] ; (8001490 ) 8001418: 4013 ands r3, r2 800141a: 604b str r3, [r1, #4] } /* Enable or disable the rising trigger */ if ((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE) 800141c: 683b ldr r3, [r7, #0] 800141e: 685b ldr r3, [r3, #4] 8001420: f403 1380 and.w r3, r3, #1048576 ; 0x100000 8001424: 2b00 cmp r3, #0 8001426: d006 beq.n 8001436 { SET_BIT(EXTI->RTSR, iocurrent); 8001428: 4b19 ldr r3, [pc, #100] ; (8001490 ) 800142a: 689a ldr r2, [r3, #8] 800142c: 4918 ldr r1, [pc, #96] ; (8001490 ) 800142e: 69bb ldr r3, [r7, #24] 8001430: 4313 orrs r3, r2 8001432: 608b str r3, [r1, #8] 8001434: e006 b.n 8001444 } else { CLEAR_BIT(EXTI->RTSR, iocurrent); 8001436: 4b16 ldr r3, [pc, #88] ; (8001490 ) 8001438: 689a ldr r2, [r3, #8] 800143a: 69bb ldr r3, [r7, #24] 800143c: 43db mvns r3, r3 800143e: 4914 ldr r1, [pc, #80] ; (8001490 ) 8001440: 4013 ands r3, r2 8001442: 608b str r3, [r1, #8] } /* Enable or disable the falling trigger */ if ((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE) 8001444: 683b ldr r3, [r7, #0] 8001446: 685b ldr r3, [r3, #4] 8001448: f403 1300 and.w r3, r3, #2097152 ; 0x200000 800144c: 2b00 cmp r3, #0 800144e: d021 beq.n 8001494 { SET_BIT(EXTI->FTSR, iocurrent); 8001450: 4b0f ldr r3, [pc, #60] ; (8001490 ) 8001452: 68da ldr r2, [r3, #12] 8001454: 490e ldr r1, [pc, #56] ; (8001490 ) 8001456: 69bb ldr r3, [r7, #24] 8001458: 4313 orrs r3, r2 800145a: 60cb str r3, [r1, #12] 800145c: e021 b.n 80014a2 800145e: bf00 nop 8001460: 10320000 .word 0x10320000 8001464: 10310000 .word 0x10310000 8001468: 10220000 .word 0x10220000 800146c: 10210000 .word 0x10210000 8001470: 10120000 .word 0x10120000 8001474: 10110000 .word 0x10110000 8001478: 40021000 .word 0x40021000 800147c: 40010000 .word 0x40010000 8001480: 40010800 .word 0x40010800 8001484: 40010c00 .word 0x40010c00 8001488: 40011000 .word 0x40011000 800148c: 40011400 .word 0x40011400 8001490: 40010400 .word 0x40010400 } else { CLEAR_BIT(EXTI->FTSR, iocurrent); 8001494: 4b0b ldr r3, [pc, #44] ; (80014c4 ) 8001496: 68da ldr r2, [r3, #12] 8001498: 69bb ldr r3, [r7, #24] 800149a: 43db mvns r3, r3 800149c: 4909 ldr r1, [pc, #36] ; (80014c4 ) 800149e: 4013 ands r3, r2 80014a0: 60cb str r3, [r1, #12] } } } position++; 80014a2: 6a7b ldr r3, [r7, #36] ; 0x24 80014a4: 3301 adds r3, #1 80014a6: 627b str r3, [r7, #36] ; 0x24 while (((GPIO_Init->Pin) >> position) != 0x00u) 80014a8: 683b ldr r3, [r7, #0] 80014aa: 681a ldr r2, [r3, #0] 80014ac: 6a7b ldr r3, [r7, #36] ; 0x24 80014ae: fa22 f303 lsr.w r3, r2, r3 80014b2: 2b00 cmp r3, #0 80014b4: f47f ae8e bne.w 80011d4 } } 80014b8: bf00 nop 80014ba: bf00 nop 80014bc: 372c adds r7, #44 ; 0x2c 80014be: 46bd mov sp, r7 80014c0: bc80 pop {r7} 80014c2: 4770 bx lr 80014c4: 40010400 .word 0x40010400 080014c8 : * @param GPIO_Pin: specifies the port bit to read. * This parameter can be GPIO_PIN_x where x can be (0..15). * @retval The input port pin value. */ GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) { 80014c8: b480 push {r7} 80014ca: b085 sub sp, #20 80014cc: af00 add r7, sp, #0 80014ce: 6078 str r0, [r7, #4] 80014d0: 460b mov r3, r1 80014d2: 807b strh r3, [r7, #2] GPIO_PinState bitstatus; /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET) 80014d4: 687b ldr r3, [r7, #4] 80014d6: 689a ldr r2, [r3, #8] 80014d8: 887b ldrh r3, [r7, #2] 80014da: 4013 ands r3, r2 80014dc: 2b00 cmp r3, #0 80014de: d002 beq.n 80014e6 { bitstatus = GPIO_PIN_SET; 80014e0: 2301 movs r3, #1 80014e2: 73fb strb r3, [r7, #15] 80014e4: e001 b.n 80014ea } else { bitstatus = GPIO_PIN_RESET; 80014e6: 2300 movs r3, #0 80014e8: 73fb strb r3, [r7, #15] } return bitstatus; 80014ea: 7bfb ldrb r3, [r7, #15] } 80014ec: 4618 mov r0, r3 80014ee: 3714 adds r7, #20 80014f0: 46bd mov sp, r7 80014f2: bc80 pop {r7} 80014f4: 4770 bx lr 080014f6 : * @arg GPIO_PIN_RESET: to clear the port pin * @arg GPIO_PIN_SET: to set the port pin * @retval None */ void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) { 80014f6: b480 push {r7} 80014f8: b083 sub sp, #12 80014fa: af00 add r7, sp, #0 80014fc: 6078 str r0, [r7, #4] 80014fe: 460b mov r3, r1 8001500: 807b strh r3, [r7, #2] 8001502: 4613 mov r3, r2 8001504: 707b strb r3, [r7, #1] /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); assert_param(IS_GPIO_PIN_ACTION(PinState)); if (PinState != GPIO_PIN_RESET) 8001506: 787b ldrb r3, [r7, #1] 8001508: 2b00 cmp r3, #0 800150a: d003 beq.n 8001514 { GPIOx->BSRR = GPIO_Pin; 800150c: 887a ldrh r2, [r7, #2] 800150e: 687b ldr r3, [r7, #4] 8001510: 611a str r2, [r3, #16] } else { GPIOx->BSRR = (uint32_t)GPIO_Pin << 16u; } } 8001512: e003 b.n 800151c GPIOx->BSRR = (uint32_t)GPIO_Pin << 16u; 8001514: 887b ldrh r3, [r7, #2] 8001516: 041a lsls r2, r3, #16 8001518: 687b ldr r3, [r7, #4] 800151a: 611a str r2, [r3, #16] } 800151c: bf00 nop 800151e: 370c adds r7, #12 8001520: 46bd mov sp, r7 8001522: bc80 pop {r7} 8001524: 4770 bx lr ... 08001528 : * supported by this macro. User should request a transition to HSE Off * first and then HSE On or HSE Bypass. * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { 8001528: b580 push {r7, lr} 800152a: b086 sub sp, #24 800152c: af00 add r7, sp, #0 800152e: 6078 str r0, [r7, #4] uint32_t tickstart; uint32_t pll_config; /* Check Null pointer */ if (RCC_OscInitStruct == NULL) 8001530: 687b ldr r3, [r7, #4] 8001532: 2b00 cmp r3, #0 8001534: d101 bne.n 800153a { return HAL_ERROR; 8001536: 2301 movs r3, #1 8001538: e272 b.n 8001a20 /* Check the parameters */ assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); /*------------------------------- HSE Configuration ------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) 800153a: 687b ldr r3, [r7, #4] 800153c: 681b ldr r3, [r3, #0] 800153e: f003 0301 and.w r3, r3, #1 8001542: 2b00 cmp r3, #0 8001544: f000 8087 beq.w 8001656 { /* Check the parameters */ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */ if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE) 8001548: 4b92 ldr r3, [pc, #584] ; (8001794 ) 800154a: 685b ldr r3, [r3, #4] 800154c: f003 030c and.w r3, r3, #12 8001550: 2b04 cmp r3, #4 8001552: d00c beq.n 800156e || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE))) 8001554: 4b8f ldr r3, [pc, #572] ; (8001794 ) 8001556: 685b ldr r3, [r3, #4] 8001558: f003 030c and.w r3, r3, #12 800155c: 2b08 cmp r3, #8 800155e: d112 bne.n 8001586 8001560: 4b8c ldr r3, [pc, #560] ; (8001794 ) 8001562: 685b ldr r3, [r3, #4] 8001564: f403 3380 and.w r3, r3, #65536 ; 0x10000 8001568: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 800156c: d10b bne.n 8001586 { if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 800156e: 4b89 ldr r3, [pc, #548] ; (8001794 ) 8001570: 681b ldr r3, [r3, #0] 8001572: f403 3300 and.w r3, r3, #131072 ; 0x20000 8001576: 2b00 cmp r3, #0 8001578: d06c beq.n 8001654 800157a: 687b ldr r3, [r7, #4] 800157c: 685b ldr r3, [r3, #4] 800157e: 2b00 cmp r3, #0 8001580: d168 bne.n 8001654 { return HAL_ERROR; 8001582: 2301 movs r3, #1 8001584: e24c b.n 8001a20 } } else { /* Set the new HSE configuration ---------------------------------------*/ __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); 8001586: 687b ldr r3, [r7, #4] 8001588: 685b ldr r3, [r3, #4] 800158a: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 800158e: d106 bne.n 800159e 8001590: 4b80 ldr r3, [pc, #512] ; (8001794 ) 8001592: 681b ldr r3, [r3, #0] 8001594: 4a7f ldr r2, [pc, #508] ; (8001794 ) 8001596: f443 3380 orr.w r3, r3, #65536 ; 0x10000 800159a: 6013 str r3, [r2, #0] 800159c: e02e b.n 80015fc 800159e: 687b ldr r3, [r7, #4] 80015a0: 685b ldr r3, [r3, #4] 80015a2: 2b00 cmp r3, #0 80015a4: d10c bne.n 80015c0 80015a6: 4b7b ldr r3, [pc, #492] ; (8001794 ) 80015a8: 681b ldr r3, [r3, #0] 80015aa: 4a7a ldr r2, [pc, #488] ; (8001794 ) 80015ac: f423 3380 bic.w r3, r3, #65536 ; 0x10000 80015b0: 6013 str r3, [r2, #0] 80015b2: 4b78 ldr r3, [pc, #480] ; (8001794 ) 80015b4: 681b ldr r3, [r3, #0] 80015b6: 4a77 ldr r2, [pc, #476] ; (8001794 ) 80015b8: f423 2380 bic.w r3, r3, #262144 ; 0x40000 80015bc: 6013 str r3, [r2, #0] 80015be: e01d b.n 80015fc 80015c0: 687b ldr r3, [r7, #4] 80015c2: 685b ldr r3, [r3, #4] 80015c4: f5b3 2fa0 cmp.w r3, #327680 ; 0x50000 80015c8: d10c bne.n 80015e4 80015ca: 4b72 ldr r3, [pc, #456] ; (8001794 ) 80015cc: 681b ldr r3, [r3, #0] 80015ce: 4a71 ldr r2, [pc, #452] ; (8001794 ) 80015d0: f443 2380 orr.w r3, r3, #262144 ; 0x40000 80015d4: 6013 str r3, [r2, #0] 80015d6: 4b6f ldr r3, [pc, #444] ; (8001794 ) 80015d8: 681b ldr r3, [r3, #0] 80015da: 4a6e ldr r2, [pc, #440] ; (8001794 ) 80015dc: f443 3380 orr.w r3, r3, #65536 ; 0x10000 80015e0: 6013 str r3, [r2, #0] 80015e2: e00b b.n 80015fc 80015e4: 4b6b ldr r3, [pc, #428] ; (8001794 ) 80015e6: 681b ldr r3, [r3, #0] 80015e8: 4a6a ldr r2, [pc, #424] ; (8001794 ) 80015ea: f423 3380 bic.w r3, r3, #65536 ; 0x10000 80015ee: 6013 str r3, [r2, #0] 80015f0: 4b68 ldr r3, [pc, #416] ; (8001794 ) 80015f2: 681b ldr r3, [r3, #0] 80015f4: 4a67 ldr r2, [pc, #412] ; (8001794 ) 80015f6: f423 2380 bic.w r3, r3, #262144 ; 0x40000 80015fa: 6013 str r3, [r2, #0] /* Check the HSE State */ if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF) 80015fc: 687b ldr r3, [r7, #4] 80015fe: 685b ldr r3, [r3, #4] 8001600: 2b00 cmp r3, #0 8001602: d013 beq.n 800162c { /* Get Start Tick */ tickstart = HAL_GetTick(); 8001604: f7ff fcca bl 8000f9c 8001608: 6138 str r0, [r7, #16] /* Wait till HSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 800160a: e008 b.n 800161e { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 800160c: f7ff fcc6 bl 8000f9c 8001610: 4602 mov r2, r0 8001612: 693b ldr r3, [r7, #16] 8001614: 1ad3 subs r3, r2, r3 8001616: 2b64 cmp r3, #100 ; 0x64 8001618: d901 bls.n 800161e { return HAL_TIMEOUT; 800161a: 2303 movs r3, #3 800161c: e200 b.n 8001a20 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 800161e: 4b5d ldr r3, [pc, #372] ; (8001794 ) 8001620: 681b ldr r3, [r3, #0] 8001622: f403 3300 and.w r3, r3, #131072 ; 0x20000 8001626: 2b00 cmp r3, #0 8001628: d0f0 beq.n 800160c 800162a: e014 b.n 8001656 } } else { /* Get Start Tick */ tickstart = HAL_GetTick(); 800162c: f7ff fcb6 bl 8000f9c 8001630: 6138 str r0, [r7, #16] /* Wait till HSE is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) 8001632: e008 b.n 8001646 { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 8001634: f7ff fcb2 bl 8000f9c 8001638: 4602 mov r2, r0 800163a: 693b ldr r3, [r7, #16] 800163c: 1ad3 subs r3, r2, r3 800163e: 2b64 cmp r3, #100 ; 0x64 8001640: d901 bls.n 8001646 { return HAL_TIMEOUT; 8001642: 2303 movs r3, #3 8001644: e1ec b.n 8001a20 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) 8001646: 4b53 ldr r3, [pc, #332] ; (8001794 ) 8001648: 681b ldr r3, [r3, #0] 800164a: f403 3300 and.w r3, r3, #131072 ; 0x20000 800164e: 2b00 cmp r3, #0 8001650: d1f0 bne.n 8001634 8001652: e000 b.n 8001656 if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 8001654: bf00 nop } } } } /*----------------------------- HSI Configuration --------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) 8001656: 687b ldr r3, [r7, #4] 8001658: 681b ldr r3, [r3, #0] 800165a: f003 0302 and.w r3, r3, #2 800165e: 2b00 cmp r3, #0 8001660: d063 beq.n 800172a /* Check the parameters */ assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI) 8001662: 4b4c ldr r3, [pc, #304] ; (8001794 ) 8001664: 685b ldr r3, [r3, #4] 8001666: f003 030c and.w r3, r3, #12 800166a: 2b00 cmp r3, #0 800166c: d00b beq.n 8001686 || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI_DIV2))) 800166e: 4b49 ldr r3, [pc, #292] ; (8001794 ) 8001670: 685b ldr r3, [r3, #4] 8001672: f003 030c and.w r3, r3, #12 8001676: 2b08 cmp r3, #8 8001678: d11c bne.n 80016b4 800167a: 4b46 ldr r3, [pc, #280] ; (8001794 ) 800167c: 685b ldr r3, [r3, #4] 800167e: f403 3380 and.w r3, r3, #65536 ; 0x10000 8001682: 2b00 cmp r3, #0 8001684: d116 bne.n 80016b4 { /* When HSI is used as system clock it will not disabled */ if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) 8001686: 4b43 ldr r3, [pc, #268] ; (8001794 ) 8001688: 681b ldr r3, [r3, #0] 800168a: f003 0302 and.w r3, r3, #2 800168e: 2b00 cmp r3, #0 8001690: d005 beq.n 800169e 8001692: 687b ldr r3, [r7, #4] 8001694: 691b ldr r3, [r3, #16] 8001696: 2b01 cmp r3, #1 8001698: d001 beq.n 800169e { return HAL_ERROR; 800169a: 2301 movs r3, #1 800169c: e1c0 b.n 8001a20 } /* Otherwise, just the calibration is allowed */ else { /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 800169e: 4b3d ldr r3, [pc, #244] ; (8001794 ) 80016a0: 681b ldr r3, [r3, #0] 80016a2: f023 02f8 bic.w r2, r3, #248 ; 0xf8 80016a6: 687b ldr r3, [r7, #4] 80016a8: 695b ldr r3, [r3, #20] 80016aa: 00db lsls r3, r3, #3 80016ac: 4939 ldr r1, [pc, #228] ; (8001794 ) 80016ae: 4313 orrs r3, r2 80016b0: 600b str r3, [r1, #0] if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) 80016b2: e03a b.n 800172a } } else { /* Check the HSI State */ if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF) 80016b4: 687b ldr r3, [r7, #4] 80016b6: 691b ldr r3, [r3, #16] 80016b8: 2b00 cmp r3, #0 80016ba: d020 beq.n 80016fe { /* Enable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_ENABLE(); 80016bc: 4b36 ldr r3, [pc, #216] ; (8001798 ) 80016be: 2201 movs r2, #1 80016c0: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 80016c2: f7ff fc6b bl 8000f9c 80016c6: 6138 str r0, [r7, #16] /* Wait till HSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 80016c8: e008 b.n 80016dc { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 80016ca: f7ff fc67 bl 8000f9c 80016ce: 4602 mov r2, r0 80016d0: 693b ldr r3, [r7, #16] 80016d2: 1ad3 subs r3, r2, r3 80016d4: 2b02 cmp r3, #2 80016d6: d901 bls.n 80016dc { return HAL_TIMEOUT; 80016d8: 2303 movs r3, #3 80016da: e1a1 b.n 8001a20 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 80016dc: 4b2d ldr r3, [pc, #180] ; (8001794 ) 80016de: 681b ldr r3, [r3, #0] 80016e0: f003 0302 and.w r3, r3, #2 80016e4: 2b00 cmp r3, #0 80016e6: d0f0 beq.n 80016ca } } /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 80016e8: 4b2a ldr r3, [pc, #168] ; (8001794 ) 80016ea: 681b ldr r3, [r3, #0] 80016ec: f023 02f8 bic.w r2, r3, #248 ; 0xf8 80016f0: 687b ldr r3, [r7, #4] 80016f2: 695b ldr r3, [r3, #20] 80016f4: 00db lsls r3, r3, #3 80016f6: 4927 ldr r1, [pc, #156] ; (8001794 ) 80016f8: 4313 orrs r3, r2 80016fa: 600b str r3, [r1, #0] 80016fc: e015 b.n 800172a } else { /* Disable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_DISABLE(); 80016fe: 4b26 ldr r3, [pc, #152] ; (8001798 ) 8001700: 2200 movs r2, #0 8001702: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8001704: f7ff fc4a bl 8000f9c 8001708: 6138 str r0, [r7, #16] /* Wait till HSI is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) 800170a: e008 b.n 800171e { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 800170c: f7ff fc46 bl 8000f9c 8001710: 4602 mov r2, r0 8001712: 693b ldr r3, [r7, #16] 8001714: 1ad3 subs r3, r2, r3 8001716: 2b02 cmp r3, #2 8001718: d901 bls.n 800171e { return HAL_TIMEOUT; 800171a: 2303 movs r3, #3 800171c: e180 b.n 8001a20 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) 800171e: 4b1d ldr r3, [pc, #116] ; (8001794 ) 8001720: 681b ldr r3, [r3, #0] 8001722: f003 0302 and.w r3, r3, #2 8001726: 2b00 cmp r3, #0 8001728: d1f0 bne.n 800170c } } } } /*------------------------------ LSI Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) 800172a: 687b ldr r3, [r7, #4] 800172c: 681b ldr r3, [r3, #0] 800172e: f003 0308 and.w r3, r3, #8 8001732: 2b00 cmp r3, #0 8001734: d03a beq.n 80017ac { /* Check the parameters */ assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); /* Check the LSI State */ if (RCC_OscInitStruct->LSIState != RCC_LSI_OFF) 8001736: 687b ldr r3, [r7, #4] 8001738: 699b ldr r3, [r3, #24] 800173a: 2b00 cmp r3, #0 800173c: d019 beq.n 8001772 { /* Enable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_ENABLE(); 800173e: 4b17 ldr r3, [pc, #92] ; (800179c ) 8001740: 2201 movs r2, #1 8001742: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8001744: f7ff fc2a bl 8000f9c 8001748: 6138 str r0, [r7, #16] /* Wait till LSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) 800174a: e008 b.n 800175e { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 800174c: f7ff fc26 bl 8000f9c 8001750: 4602 mov r2, r0 8001752: 693b ldr r3, [r7, #16] 8001754: 1ad3 subs r3, r2, r3 8001756: 2b02 cmp r3, #2 8001758: d901 bls.n 800175e { return HAL_TIMEOUT; 800175a: 2303 movs r3, #3 800175c: e160 b.n 8001a20 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) 800175e: 4b0d ldr r3, [pc, #52] ; (8001794 ) 8001760: 6a5b ldr r3, [r3, #36] ; 0x24 8001762: f003 0302 and.w r3, r3, #2 8001766: 2b00 cmp r3, #0 8001768: d0f0 beq.n 800174c } } /* To have a fully stabilized clock in the specified range, a software delay of 1ms should be added.*/ RCC_Delay(1); 800176a: 2001 movs r0, #1 800176c: f000 fad8 bl 8001d20 8001770: e01c b.n 80017ac } else { /* Disable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_DISABLE(); 8001772: 4b0a ldr r3, [pc, #40] ; (800179c ) 8001774: 2200 movs r2, #0 8001776: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8001778: f7ff fc10 bl 8000f9c 800177c: 6138 str r0, [r7, #16] /* Wait till LSI is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) 800177e: e00f b.n 80017a0 { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 8001780: f7ff fc0c bl 8000f9c 8001784: 4602 mov r2, r0 8001786: 693b ldr r3, [r7, #16] 8001788: 1ad3 subs r3, r2, r3 800178a: 2b02 cmp r3, #2 800178c: d908 bls.n 80017a0 { return HAL_TIMEOUT; 800178e: 2303 movs r3, #3 8001790: e146 b.n 8001a20 8001792: bf00 nop 8001794: 40021000 .word 0x40021000 8001798: 42420000 .word 0x42420000 800179c: 42420480 .word 0x42420480 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) 80017a0: 4b92 ldr r3, [pc, #584] ; (80019ec ) 80017a2: 6a5b ldr r3, [r3, #36] ; 0x24 80017a4: f003 0302 and.w r3, r3, #2 80017a8: 2b00 cmp r3, #0 80017aa: d1e9 bne.n 8001780 } } } } /*------------------------------ LSE Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) 80017ac: 687b ldr r3, [r7, #4] 80017ae: 681b ldr r3, [r3, #0] 80017b0: f003 0304 and.w r3, r3, #4 80017b4: 2b00 cmp r3, #0 80017b6: f000 80a6 beq.w 8001906 { FlagStatus pwrclkchanged = RESET; 80017ba: 2300 movs r3, #0 80017bc: 75fb strb r3, [r7, #23] /* Check the parameters */ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); /* Update LSE configuration in Backup Domain control register */ /* Requires to enable write access to Backup Domain of necessary */ if (__HAL_RCC_PWR_IS_CLK_DISABLED()) 80017be: 4b8b ldr r3, [pc, #556] ; (80019ec ) 80017c0: 69db ldr r3, [r3, #28] 80017c2: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 80017c6: 2b00 cmp r3, #0 80017c8: d10d bne.n 80017e6 { __HAL_RCC_PWR_CLK_ENABLE(); 80017ca: 4b88 ldr r3, [pc, #544] ; (80019ec ) 80017cc: 69db ldr r3, [r3, #28] 80017ce: 4a87 ldr r2, [pc, #540] ; (80019ec ) 80017d0: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 80017d4: 61d3 str r3, [r2, #28] 80017d6: 4b85 ldr r3, [pc, #532] ; (80019ec ) 80017d8: 69db ldr r3, [r3, #28] 80017da: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 80017de: 60bb str r3, [r7, #8] 80017e0: 68bb ldr r3, [r7, #8] pwrclkchanged = SET; 80017e2: 2301 movs r3, #1 80017e4: 75fb strb r3, [r7, #23] } if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 80017e6: 4b82 ldr r3, [pc, #520] ; (80019f0 ) 80017e8: 681b ldr r3, [r3, #0] 80017ea: f403 7380 and.w r3, r3, #256 ; 0x100 80017ee: 2b00 cmp r3, #0 80017f0: d118 bne.n 8001824 { /* Enable write access to Backup domain */ SET_BIT(PWR->CR, PWR_CR_DBP); 80017f2: 4b7f ldr r3, [pc, #508] ; (80019f0 ) 80017f4: 681b ldr r3, [r3, #0] 80017f6: 4a7e ldr r2, [pc, #504] ; (80019f0 ) 80017f8: f443 7380 orr.w r3, r3, #256 ; 0x100 80017fc: 6013 str r3, [r2, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 80017fe: f7ff fbcd bl 8000f9c 8001802: 6138 str r0, [r7, #16] while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8001804: e008 b.n 8001818 { if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 8001806: f7ff fbc9 bl 8000f9c 800180a: 4602 mov r2, r0 800180c: 693b ldr r3, [r7, #16] 800180e: 1ad3 subs r3, r2, r3 8001810: 2b64 cmp r3, #100 ; 0x64 8001812: d901 bls.n 8001818 { return HAL_TIMEOUT; 8001814: 2303 movs r3, #3 8001816: e103 b.n 8001a20 while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8001818: 4b75 ldr r3, [pc, #468] ; (80019f0 ) 800181a: 681b ldr r3, [r3, #0] 800181c: f403 7380 and.w r3, r3, #256 ; 0x100 8001820: 2b00 cmp r3, #0 8001822: d0f0 beq.n 8001806 } } } /* Set the new LSE configuration -----------------------------------------*/ __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); 8001824: 687b ldr r3, [r7, #4] 8001826: 68db ldr r3, [r3, #12] 8001828: 2b01 cmp r3, #1 800182a: d106 bne.n 800183a 800182c: 4b6f ldr r3, [pc, #444] ; (80019ec ) 800182e: 6a1b ldr r3, [r3, #32] 8001830: 4a6e ldr r2, [pc, #440] ; (80019ec ) 8001832: f043 0301 orr.w r3, r3, #1 8001836: 6213 str r3, [r2, #32] 8001838: e02d b.n 8001896 800183a: 687b ldr r3, [r7, #4] 800183c: 68db ldr r3, [r3, #12] 800183e: 2b00 cmp r3, #0 8001840: d10c bne.n 800185c 8001842: 4b6a ldr r3, [pc, #424] ; (80019ec ) 8001844: 6a1b ldr r3, [r3, #32] 8001846: 4a69 ldr r2, [pc, #420] ; (80019ec