: /** * @brief The application entry point. * @retval int */ int main(void) { 8000188: b580 push {r7, lr} 800018a: b08e sub sp, #56 ; 0x38 800018c: af00 add r7, sp, #0 /* USER CODE END 1 */ /* MCU Configuration--------------------------------------------------------*/ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ HAL_Init(); 800018e: f000 f99f bl 80004d0 /* USER CODE BEGIN Init */ /* USER CODE END Init */ /* Configure the system clock */ SystemClock_Config(); 8000192: f000 f82d bl 80001f0 /* USER CODE BEGIN SysInit */ /* USER CODE END SysInit */ /* Initialize all configured peripherals */ MX_GPIO_Init(); 8000196: f7ff ffe1 bl 800015c MX_USART2_UART_Init(); 800019a: f000 f8ff bl 800039c /* USER CODE END 2 */ /* Infinite loop */ /* USER CODE BEGIN WHILE */ char send_buffer[50] = { 0 }; 800019e: 2300 movs r3, #0 80001a0: 607b str r3, [r7, #4] 80001a2: f107 0308 add.w r3, r7, #8 80001a6: 222e movs r2, #46 ; 0x2e 80001a8: 2100 movs r1, #0 80001aa: 4618 mov r0, r3 80001ac: f001 fa7a bl 80016a4 uint16_t send_cnt = 0; 80001b0: 2300 movs r3, #0 80001b2: 86fb strh r3, [r7, #54] ; 0x36 while (1) { sprintf(send_buffer, "Send %d packets\r\n", send_cnt++); 80001b4: 8efb ldrh r3, [r7, #54] ; 0x36 80001b6: 1c5a adds r2, r3, #1 80001b8: 86fa strh r2, [r7, #54] ; 0x36 80001ba: 461a mov r2, r3 80001bc: 1d3b adds r3, r7, #4 80001be: 490a ldr r1, [pc, #40] ; (80001e8 ) 80001c0: 4618 mov r0, r3 80001c2: f001 fa77 bl 80016b4 HAL_UART_Transmit(&huart2, (uint8_t*) send_buffer, strlen(send_buffer), 80001c6: 1d3b adds r3, r7, #4 80001c8: 4618 mov r0, r3 80001ca: f7ff ffbf bl 800014c 80001ce: 4603 mov r3, r0 80001d0: b29a uxth r2, r3 80001d2: 1d39 adds r1, r7, #4 80001d4: 230a movs r3, #10 80001d6: 4805 ldr r0, [pc, #20] ; (80001ec ) 80001d8: f001 f8cf bl 800137a 10); HAL_Delay(500); 80001dc: f44f 70fa mov.w r0, #500 ; 0x1f4 80001e0: f000 f9d8 bl 8000594 sprintf(send_buffer, "Send %d packets\r\n", send_cnt++); 80001e4: e7e6 b.n 80001b4 80001e6: bf00 nop 80001e8: 08001fc0 .word 0x08001fc0 80001ec: 20000090 .word 0x20000090 080001f0 : /** * @brief System Clock Configuration * @retval None */ void SystemClock_Config(void) { 80001f0: b580 push {r7, lr} 80001f2: b090 sub sp, #64 ; 0x40 80001f4: af00 add r7, sp, #0 RCC_OscInitTypeDef RCC_OscInitStruct = { 0 }; 80001f6: f107 0318 add.w r3, r7, #24 80001fa: 2228 movs r2, #40 ; 0x28 80001fc: 2100 movs r1, #0 80001fe: 4618 mov r0, r3 8000200: f001 fa50 bl 80016a4 RCC_ClkInitTypeDef RCC_ClkInitStruct = { 0 }; 8000204: 1d3b adds r3, r7, #4 8000206: 2200 movs r2, #0 8000208: 601a str r2, [r3, #0] 800020a: 605a str r2, [r3, #4] 800020c: 609a str r2, [r3, #8] 800020e: 60da str r2, [r3, #12] 8000210: 611a str r2, [r3, #16] /** Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; 8000212: 2302 movs r3, #2 8000214: 61bb str r3, [r7, #24] RCC_OscInitStruct.HSIState = RCC_HSI_ON; 8000216: 2301 movs r3, #1 8000218: 62bb str r3, [r7, #40] ; 0x28 RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; 800021a: 2310 movs r3, #16 800021c: 62fb str r3, [r7, #44] ; 0x2c RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; 800021e: 2300 movs r3, #0 8000220: 637b str r3, [r7, #52] ; 0x34 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { 8000222: f107 0318 add.w r3, r7, #24 8000226: 4618 mov r0, r3 8000228: f000 fc40 bl 8000aac 800022c: 4603 mov r3, r0 800022e: 2b00 cmp r3, #0 8000230: d001 beq.n 8000236 Error_Handler(); 8000232: f000 f818 bl 8000266 } /** Initializes the CPU, AHB and APB buses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK 8000236: 230f movs r3, #15 8000238: 607b str r3, [r7, #4] | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI; 800023a: 2300 movs r3, #0 800023c: 60bb str r3, [r7, #8] RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; 800023e: 2300 movs r3, #0 8000240: 60fb str r3, [r7, #12] RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; 8000242: 2300 movs r3, #0 8000244: 613b str r3, [r7, #16] RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; 8000246: 2300 movs r3, #0 8000248: 617b str r3, [r7, #20] if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK) { 800024a: 1d3b adds r3, r7, #4 800024c: 2100 movs r1, #0 800024e: 4618 mov r0, r3 8000250: f000 feae bl 8000fb0 8000254: 4603 mov r3, r0 8000256: 2b00 cmp r3, #0 8000258: d001 beq.n 800025e Error_Handler(); 800025a: f000 f804 bl 8000266 } } 800025e: bf00 nop 8000260: 3740 adds r7, #64 ; 0x40 8000262: 46bd mov sp, r7 8000264: bd80 pop {r7, pc} 08000266 : /** * @brief This function is executed in case of error occurrence. * @retval None */ void Error_Handler(void) { 8000266: b480 push {r7} 8000268: af00 add r7, sp, #0 \details Disables IRQ interrupts by setting the I-bit in the CPSR. Can only be executed in Privileged modes. */ __STATIC_FORCEINLINE void __disable_irq(void) { __ASM volatile ("cpsid i" : : : "memory"); 800026a: b672 cpsid i } 800026c: bf00 nop /* USER CODE BEGIN Error_Handler_Debug */ /* User can add his own implementation to report the HAL error return state */ __disable_irq(); while (1) { 800026e: e7fe b.n 800026e 08000270 : /* USER CODE END 0 */ /** * Initializes the Global MSP. */ void HAL_MspInit(void) { 8000270: b480 push {r7} 8000272: b085 sub sp, #20 8000274: af00 add r7, sp, #0 /* USER CODE BEGIN MspInit 0 */ /* USER CODE END MspInit 0 */ __HAL_RCC_AFIO_CLK_ENABLE(); 8000276: 4b15 ldr r3, [pc, #84] ; (80002cc ) 8000278: 699b ldr r3, [r3, #24] 800027a: 4a14 ldr r2, [pc, #80] ; (80002cc ) 800027c: f043 0301 orr.w r3, r3, #1 8000280: 6193 str r3, [r2, #24] 8000282: 4b12 ldr r3, [pc, #72] ; (80002cc ) 8000284: 699b ldr r3, [r3, #24] 8000286: f003 0301 and.w r3, r3, #1 800028a: 60bb str r3, [r7, #8] 800028c: 68bb ldr r3, [r7, #8] __HAL_RCC_PWR_CLK_ENABLE(); 800028e: 4b0f ldr r3, [pc, #60] ; (80002cc ) 8000290: 69db ldr r3, [r3, #28] 8000292: 4a0e ldr r2, [pc, #56] ; (80002cc ) 8000294: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 8000298: 61d3 str r3, [r2, #28] 800029a: 4b0c ldr r3, [pc, #48] ; (80002cc ) 800029c: 69db ldr r3, [r3, #28] 800029e: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 80002a2: 607b str r3, [r7, #4] 80002a4: 687b ldr r3, [r7, #4] /* System interrupt init*/ /** NOJTAG: JTAG-DP Disabled and SW-DP Enabled */ __HAL_AFIO_REMAP_SWJ_NOJTAG(); 80002a6: 4b0a ldr r3, [pc, #40] ; (80002d0 ) 80002a8: 685b ldr r3, [r3, #4] 80002aa: 60fb str r3, [r7, #12] 80002ac: 68fb ldr r3, [r7, #12] 80002ae: f023 63e0 bic.w r3, r3, #117440512 ; 0x7000000 80002b2: 60fb str r3, [r7, #12] 80002b4: 68fb ldr r3, [r7, #12] 80002b6: f043 7300 orr.w r3, r3, #33554432 ; 0x2000000 80002ba: 60fb str r3, [r7, #12] 80002bc: 4a04 ldr r2, [pc, #16] ; (80002d0 ) 80002be: 68fb ldr r3, [r7, #12] 80002c0: 6053 str r3, [r2, #4] /* USER CODE BEGIN MspInit 1 */ /* USER CODE END MspInit 1 */ } 80002c2: bf00 nop 80002c4: 3714 adds r7, #20 80002c6: 46bd mov sp, r7 80002c8: bc80 pop {r7} 80002ca: 4770 bx lr 80002cc: 40021000 .word 0x40021000 80002d0: 40010000 .word 0x40010000 080002d4 : /******************************************************************************/ /** * @brief This function handles Non maskable interrupt. */ void NMI_Handler(void) { 80002d4: b480 push {r7} 80002d6: af00 add r7, sp, #0 /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ /* USER CODE END NonMaskableInt_IRQn 0 */ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ while (1) 80002d8: e7fe b.n 80002d8 080002da : /** * @brief This function handles Hard fault interrupt. */ void HardFault_Handler(void) { 80002da: b480 push {r7} 80002dc: af00 add r7, sp, #0 /* USER CODE BEGIN HardFault_IRQn 0 */ /* USER CODE END HardFault_IRQn 0 */ while (1) 80002de: e7fe b.n 80002de 080002e0 : /** * @brief This function handles Memory management fault. */ void MemManage_Handler(void) { 80002e0: b480 push {r7} 80002e2: af00 add r7, sp, #0 /* USER CODE BEGIN MemoryManagement_IRQn 0 */ /* USER CODE END MemoryManagement_IRQn 0 */ while (1) 80002e4: e7fe b.n 80002e4 080002e6 : /** * @brief This function handles Prefetch fault, memory access fault. */ void BusFault_Handler(void) { 80002e6: b480 push {r7} 80002e8: af00 add r7, sp, #0 /* USER CODE BEGIN BusFault_IRQn 0 */ /* USER CODE END BusFault_IRQn 0 */ while (1) 80002ea: e7fe b.n 80002ea 080002ec : /** * @brief This function handles Undefined instruction or illegal state. */ void UsageFault_Handler(void) { 80002ec: b480 push {r7} 80002ee: af00 add r7, sp, #0 /* USER CODE BEGIN UsageFault_IRQn 0 */ /* USER CODE END UsageFault_IRQn 0 */ while (1) 80002f0: e7fe b.n 80002f0 080002f2 : /** * @brief This function handles System service call via SWI instruction. */ void SVC_Handler(void) { 80002f2: b480 push {r7} 80002f4: af00 add r7, sp, #0 /* USER CODE END SVCall_IRQn 0 */ /* USER CODE BEGIN SVCall_IRQn 1 */ /* USER CODE END SVCall_IRQn 1 */ } 80002f6: bf00 nop 80002f8: 46bd mov sp, r7 80002fa: bc80 pop {r7} 80002fc: 4770 bx lr 080002fe : /** * @brief This function handles Debug monitor. */ void DebugMon_Handler(void) { 80002fe: b480 push {r7} 8000300: af00 add r7, sp, #0 /* USER CODE END DebugMonitor_IRQn 0 */ /* USER CODE BEGIN DebugMonitor_IRQn 1 */ /* USER CODE END DebugMonitor_IRQn 1 */ } 8000302: bf00 nop 8000304: 46bd mov sp, r7 8000306: bc80 pop {r7} 8000308: 4770 bx lr 0800030a : /** * @brief This function handles Pendable request for system service. */ void PendSV_Handler(void) { 800030a: b480 push {r7} 800030c: af00 add r7, sp, #0 /* USER CODE END PendSV_IRQn 0 */ /* USER CODE BEGIN PendSV_IRQn 1 */ /* USER CODE END PendSV_IRQn 1 */ } 800030e: bf00 nop 8000310: 46bd mov sp, r7 8000312: bc80 pop {r7} 8000314: 4770 bx lr 08000316 : /** * @brief This function handles System tick timer. */ void SysTick_Handler(void) { 8000316: b580 push {r7, lr} 8000318: af00 add r7, sp, #0 /* USER CODE BEGIN SysTick_IRQn 0 */ /* USER CODE END SysTick_IRQn 0 */ HAL_IncTick(); 800031a: f000 f91f bl 800055c /* USER CODE BEGIN SysTick_IRQn 1 */ /* USER CODE END SysTick_IRQn 1 */ } 800031e: bf00 nop 8000320: bd80 pop {r7, pc} ... 08000324 <_sbrk>: * * @param incr Memory size * @return Pointer to allocated memory */ void *_sbrk(ptrdiff_t incr) { 8000324: b580 push {r7, lr} 8000326: b086 sub sp, #24 8000328: af00 add r7, sp, #0 800032a: 6078 str r0, [r7, #4] extern uint8_t _end; /* Symbol defined in the linker script */ extern uint8_t _estack; /* Symbol defined in the linker script */ extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */ const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size; 800032c: 4a14 ldr r2, [pc, #80] ; (8000380 <_sbrk+0x5c>) 800032e: 4b15 ldr r3, [pc, #84] ; (8000384 <_sbrk+0x60>) 8000330: 1ad3 subs r3, r2, r3 8000332: 617b str r3, [r7, #20] const uint8_t *max_heap = (uint8_t *)stack_limit; 8000334: 697b ldr r3, [r7, #20] 8000336: 613b str r3, [r7, #16] uint8_t *prev_heap_end; /* Initialize heap end at first call */ if (NULL == __sbrk_heap_end) 8000338: 4b13 ldr r3, [pc, #76] ; (8000388 <_sbrk+0x64>) 800033a: 681b ldr r3, [r3, #0] 800033c: 2b00 cmp r3, #0 800033e: d102 bne.n 8000346 <_sbrk+0x22> { __sbrk_heap_end = &_end; 8000340: 4b11 ldr r3, [pc, #68] ; (8000388 <_sbrk+0x64>) 8000342: 4a12 ldr r2, [pc, #72] ; (800038c <_sbrk+0x68>) 8000344: 601a str r2, [r3, #0] } /* Protect heap from growing into the reserved MSP stack */ if (__sbrk_heap_end + incr > max_heap) 8000346: 4b10 ldr r3, [pc, #64] ; (8000388 <_sbrk+0x64>) 8000348: 681a ldr r2, [r3, #0] 800034a: 687b ldr r3, [r7, #4] 800034c: 4413 add r3, r2 800034e: 693a ldr r2, [r7, #16] 8000350: 429a cmp r2, r3 8000352: d207 bcs.n 8000364 <_sbrk+0x40> { errno = ENOMEM; 8000354: f001 f97c bl 8001650 <__errno> 8000358: 4603 mov r3, r0 800035a: 220c movs r2, #12 800035c: 601a str r2, [r3, #0] return (void *)-1; 800035e: f04f 33ff mov.w r3, #4294967295 8000362: e009 b.n 8000378 <_sbrk+0x54> } prev_heap_end = __sbrk_heap_end; 8000364: 4b08 ldr r3, [pc, #32] ; (8000388 <_sbrk+0x64>) 8000366: 681b ldr r3, [r3, #0] 8000368: 60fb str r3, [r7, #12] __sbrk_heap_end += incr; 800036a: 4b07 ldr r3, [pc, #28] ; (8000388 <_sbrk+0x64>) 800036c: 681a ldr r2, [r3, #0] 800036e: 687b ldr r3, [r7, #4] 8000370: 4413 add r3, r2 8000372: 4a05 ldr r2, [pc, #20] ; (8000388 <_sbrk+0x64>) 8000374: 6013 str r3, [r2, #0] return (void *)prev_heap_end; 8000376: 68fb ldr r3, [r7, #12] } 8000378: 4618 mov r0, r3 800037a: 3718 adds r7, #24 800037c: 46bd mov sp, r7 800037e: bd80 pop {r7, pc} 8000380: 20005000 .word 0x20005000 8000384: 00000400 .word 0x00000400 8000388: 2000008c .word 0x2000008c 800038c: 200000e8 .word 0x200000e8 08000390 : * @note This function should be used only after reset. * @param None * @retval None */ void SystemInit (void) { 8000390: b480 push {r7} 8000392: af00 add r7, sp, #0 /* Configure the Vector Table location -------------------------------------*/ #if defined(USER_VECT_TAB_ADDRESS) SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ #endif /* USER_VECT_TAB_ADDRESS */ } 8000394: bf00 nop 8000396: 46bd mov sp, r7 8000398: bc80 pop {r7} 800039a: 4770 bx lr 0800039c : UART_HandleTypeDef huart2; /* USART2 init function */ void MX_USART2_UART_Init(void) { 800039c: b580 push {r7, lr} 800039e: af00 add r7, sp, #0 /* USER CODE END USART2_Init 0 */ /* USER CODE BEGIN USART2_Init 1 */ /* USER CODE END USART2_Init 1 */ huart2.Instance = USART2; 80003a0: 4b11 ldr r3, [pc, #68] ; (80003e8 ) 80003a2: 4a12 ldr r2, [pc, #72] ; (80003ec ) 80003a4: 601a str r2, [r3, #0] huart2.Init.BaudRate = 115200; 80003a6: 4b10 ldr r3, [pc, #64] ; (80003e8 ) 80003a8: f44f 32e1 mov.w r2, #115200 ; 0x1c200 80003ac: 605a str r2, [r3, #4] huart2.Init.WordLength = UART_WORDLENGTH_8B; 80003ae: 4b0e ldr r3, [pc, #56] ; (80003e8 ) 80003b0: 2200 movs r2, #0 80003b2: 609a str r2, [r3, #8] huart2.Init.StopBits = UART_STOPBITS_1; 80003b4: 4b0c ldr r3, [pc, #48] ; (80003e8 ) 80003b6: 2200 movs r2, #0 80003b8: 60da str r2, [r3, #12] huart2.Init.Parity = UART_PARITY_NONE; 80003ba: 4b0b ldr r3, [pc, #44] ; (80003e8 ) 80003bc: 2200 movs r2, #0 80003be: 611a str r2, [r3, #16] huart2.Init.Mode = UART_MODE_TX_RX; 80003c0: 4b09 ldr r3, [pc, #36] ; (80003e8 ) 80003c2: 220c movs r2, #12 80003c4: 615a str r2, [r3, #20] huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE; 80003c6: 4b08 ldr r3, [pc, #32] ; (80003e8 ) 80003c8: 2200 movs r2, #0 80003ca: 619a str r2, [r3, #24] huart2.Init.OverSampling = UART_OVERSAMPLING_16; 80003cc: 4b06 ldr r3, [pc, #24] ; (80003e8 ) 80003ce: 2200 movs r2, #0 80003d0: 61da str r2, [r3, #28] if (HAL_UART_Init(&huart2) != HAL_OK) 80003d2: 4805 ldr r0, [pc, #20] ; (80003e8 ) 80003d4: f000 ff84 bl 80012e0 80003d8: 4603 mov r3, r0 80003da: 2b00 cmp r3, #0 80003dc: d001 beq.n 80003e2 { Error_Handler(); 80003de: f7ff ff42 bl 8000266 } /* USER CODE BEGIN USART2_Init 2 */ /* USER CODE END USART2_Init 2 */ } 80003e2: bf00 nop 80003e4: bd80 pop {r7, pc} 80003e6: bf00 nop 80003e8: 20000090 .word 0x20000090 80003ec: 40004400 .word 0x40004400 080003f0 : void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle) { 80003f0: b580 push {r7, lr} 80003f2: b088 sub sp, #32 80003f4: af00 add r7, sp, #0 80003f6: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 80003f8: f107 0310 add.w r3, r7, #16 80003fc: 2200 movs r2, #0 80003fe: 601a str r2, [r3, #0] 8000400: 605a str r2, [r3, #4] 8000402: 609a str r2, [r3, #8] 8000404: 60da str r2, [r3, #12] if(uartHandle->Instance==USART2) 8000406: 687b ldr r3, [r7, #4] 8000408: 681b ldr r3, [r3, #0] 800040a: 4a1b ldr r2, [pc, #108] ; (8000478 ) 800040c: 4293 cmp r3, r2 800040e: d12f bne.n 8000470 { /* USER CODE BEGIN USART2_MspInit 0 */ /* USER CODE END USART2_MspInit 0 */ /* USART2 clock enable */ __HAL_RCC_USART2_CLK_ENABLE(); 8000410: 4b1a ldr r3, [pc, #104] ; (800047c ) 8000412: 69db ldr r3, [r3, #28] 8000414: 4a19 ldr r2, [pc, #100] ; (800047c ) 8000416: f443 3300 orr.w r3, r3, #131072 ; 0x20000 800041a: 61d3 str r3, [r2, #28] 800041c: 4b17 ldr r3, [pc, #92] ; (800047c ) 800041e: 69db ldr r3, [r3, #28] 8000420: f403 3300 and.w r3, r3, #131072 ; 0x20000 8000424: 60fb str r3, [r7, #12] 8000426: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOA_CLK_ENABLE(); 8000428: 4b14 ldr r3, [pc, #80] ; (800047c ) 800042a: 699b ldr r3, [r3, #24] 800042c: 4a13 ldr r2, [pc, #76] ; (800047c ) 800042e: f043 0304 orr.w r3, r3, #4 8000432: 6193 str r3, [r2, #24] 8000434: 4b11 ldr r3, [pc, #68] ; (800047c ) 8000436: 699b ldr r3, [r3, #24] 8000438: f003 0304 and.w r3, r3, #4 800043c: 60bb str r3, [r7, #8] 800043e: 68bb ldr r3, [r7, #8] /**USART2 GPIO Configuration PA2 ------> USART2_TX PA3 ------> USART2_RX */ GPIO_InitStruct.Pin = GPIO_PIN_2; 8000440: 2304 movs r3, #4 8000442: 613b str r3, [r7, #16] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8000444: 2302 movs r3, #2 8000446: 617b str r3, [r7, #20] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 8000448: 2303 movs r3, #3 800044a: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 800044c: f107 0310 add.w r3, r7, #16 8000450: 4619 mov r1, r3 8000452: 480b ldr r0, [pc, #44] ; (8000480 ) 8000454: f000 f9a6 bl 80007a4 GPIO_InitStruct.Pin = GPIO_PIN_3; 8000458: 2308 movs r3, #8 800045a: 613b str r3, [r7, #16] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 800045c: 2300 movs r3, #0 800045e: 617b str r3, [r7, #20] GPIO_InitStruct.Pull = GPIO_NOPULL; 8000460: 2300 movs r3, #0 8000462: 61bb str r3, [r7, #24] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8000464: f107 0310 add.w r3, r7, #16 8000468: 4619 mov r1, r3 800046a: 4805 ldr r0, [pc, #20] ; (8000480 ) 800046c: f000 f99a bl 80007a4 /* USER CODE BEGIN USART2_MspInit 1 */ /* USER CODE END USART2_MspInit 1 */ } } 8000470: bf00 nop 8000472: 3720 adds r7, #32 8000474: 46bd mov sp, r7 8000476: bd80 pop {r7, pc} 8000478: 40004400 .word 0x40004400 800047c: 40021000 .word 0x40021000 8000480: 40010800 .word 0x40010800 08000484 : .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata 8000484: 480c ldr r0, [pc, #48] ; (80004b8 ) ldr r1, =_edata 8000486: 490d ldr r1, [pc, #52] ; (80004bc ) ldr r2, =_sidata 8000488: 4a0d ldr r2, [pc, #52] ; (80004c0 ) movs r3, #0 800048a: 2300 movs r3, #0 b LoopCopyDataInit 800048c: e002 b.n 8000494 0800048e : CopyDataInit: ldr r4, [r2, r3] 800048e: 58d4 ldr r4, [r2, r3] str r4, [r0, r3] 8000490: 50c4 str r4, [r0, r3] adds r3, r3, #4 8000492: 3304 adds r3, #4 08000494 : LoopCopyDataInit: adds r4, r0, r3 8000494: 18c4 adds r4, r0, r3 cmp r4, r1 8000496: 428c cmp r4, r1 bcc CopyDataInit 8000498: d3f9 bcc.n 800048e /* Zero fill the bss segment. */ ldr r2, =_sbss 800049a: 4a0a ldr r2, [pc, #40] ; (80004c4 ) ldr r4, =_ebss 800049c: 4c0a ldr r4, [pc, #40] ; (80004c8 ) movs r3, #0 800049e: 2300 movs r3, #0 b LoopFillZerobss 80004a0: e001 b.n 80004a6 080004a2 : FillZerobss: str r3, [r2] 80004a2: 6013 str r3, [r2, #0] adds r2, r2, #4 80004a4: 3204 adds r2, #4 080004a6 : LoopFillZerobss: cmp r2, r4 80004a6: 42a2 cmp r2, r4 bcc FillZerobss 80004a8: d3fb bcc.n 80004a2 /* Call the clock system intitialization function.*/ bl SystemInit 80004aa: f7ff ff71 bl 8000390 /* Call static constructors */ bl __libc_init_array 80004ae: f001 f8d5 bl 800165c <__libc_init_array> /* Call the application's entry point.*/ bl main 80004b2: f7ff fe69 bl 8000188

bx lr 80004b6: 4770 bx lr ldr r0, =_sdata 80004b8: 20000000 .word 0x20000000 ldr r1, =_edata 80004bc: 20000070 .word 0x20000070 ldr r2, =_sidata 80004c0: 08002038 .word 0x08002038 ldr r2, =_sbss 80004c4: 20000070 .word 0x20000070 ldr r4, =_ebss 80004c8: 200000e8 .word 0x200000e8 080004cc : * @retval : None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop 80004cc: e7fe b.n 80004cc ... 080004d0 : * need to ensure that the SysTick time base is always set to 1 millisecond * to have correct HAL operation. * @retval HAL status */ HAL_StatusTypeDef HAL_Init(void) { 80004d0: b580 push {r7, lr} 80004d2: af00 add r7, sp, #0 defined(STM32F102x6) || defined(STM32F102xB) || \ defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || \ defined(STM32F105xC) || defined(STM32F107xC) /* Prefetch buffer is not available on value line devices */ __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); 80004d4: 4b08 ldr r3, [pc, #32] ; (80004f8 ) 80004d6: 681b ldr r3, [r3, #0] 80004d8: 4a07 ldr r2, [pc, #28] ; (80004f8 ) 80004da: f043 0310 orr.w r3, r3, #16 80004de: 6013 str r3, [r2, #0] #endif #endif /* PREFETCH_ENABLE */ /* Set Interrupt Group Priority */ HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); 80004e0: 2003 movs r0, #3 80004e2: f000 f92b bl 800073c /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ HAL_InitTick(TICK_INT_PRIORITY); 80004e6: 200f movs r0, #15 80004e8: f000 f808 bl 80004fc /* Init the low level hardware */ HAL_MspInit(); 80004ec: f7ff fec0 bl 8000270 /* Return function status */ return HAL_OK; 80004f0: 2300 movs r3, #0 } 80004f2: 4618 mov r0, r3 80004f4: bd80 pop {r7, pc} 80004f6: bf00 nop 80004f8: 40022000 .word 0x40022000 080004fc : * implementation in user file. * @param TickPriority Tick interrupt priority. * @retval HAL status */ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { 80004fc: b580 push {r7, lr} 80004fe: b082 sub sp, #8 8000500: af00 add r7, sp, #0 8000502: 6078 str r0, [r7, #4] /* Configure the SysTick to have interrupt in 1ms time basis*/ if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U) 8000504: 4b12 ldr r3, [pc, #72] ; (8000550 ) 8000506: 681a ldr r2, [r3, #0] 8000508: 4b12 ldr r3, [pc, #72] ; (8000554 ) 800050a: 781b ldrb r3, [r3, #0] 800050c: 4619 mov r1, r3 800050e: f44f 737a mov.w r3, #1000 ; 0x3e8 8000512: fbb3 f3f1 udiv r3, r3, r1 8000516: fbb2 f3f3 udiv r3, r2, r3 800051a: 4618 mov r0, r3 800051c: f000 f935 bl 800078a 8000520: 4603 mov r3, r0 8000522: 2b00 cmp r3, #0 8000524: d001 beq.n 800052a { return HAL_ERROR; 8000526: 2301 movs r3, #1 8000528: e00e b.n 8000548 } /* Configure the SysTick IRQ priority */ if (TickPriority < (1UL << __NVIC_PRIO_BITS)) 800052a: 687b ldr r3, [r7, #4] 800052c: 2b0f cmp r3, #15 800052e: d80a bhi.n 8000546 { HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); 8000530: 2200 movs r2, #0 8000532: 6879 ldr r1, [r7, #4] 8000534: f04f 30ff mov.w r0, #4294967295 8000538: f000 f90b bl 8000752 uwTickPrio = TickPriority; 800053c: 4a06 ldr r2, [pc, #24] ; (8000558 ) 800053e: 687b ldr r3, [r7, #4] 8000540: 6013 str r3, [r2, #0] { return HAL_ERROR; } /* Return function status */ return HAL_OK; 8000542: 2300 movs r3, #0 8000544: e000 b.n 8000548 return HAL_ERROR; 8000546: 2301 movs r3, #1 } 8000548: 4618 mov r0, r3 800054a: 3708 adds r7, #8 800054c: 46bd mov sp, r7 800054e: bd80 pop {r7, pc} 8000550: 20000000 .word 0x20000000 8000554: 20000008 .word 0x20000008 8000558: 20000004 .word 0x20000004 0800055c : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ __weak void HAL_IncTick(void) { 800055c: b480 push {r7} 800055e: af00 add r7, sp, #0 uwTick += uwTickFreq; 8000560: 4b05 ldr r3, [pc, #20] ; (8000578 ) 8000562: 781b ldrb r3, [r3, #0] 8000564: 461a mov r2, r3 8000566: 4b05 ldr r3, [pc, #20] ; (800057c ) 8000568: 681b ldr r3, [r3, #0] 800056a: 4413 add r3, r2 800056c: 4a03 ldr r2, [pc, #12] ; (800057c ) 800056e: 6013 str r3, [r2, #0] } 8000570: bf00 nop 8000572: 46bd mov sp, r7 8000574: bc80 pop {r7} 8000576: 4770 bx lr 8000578: 20000008 .word 0x20000008 800057c: 200000d4 .word 0x200000d4 08000580 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval tick value */ __weak uint32_t HAL_GetTick(void) { 8000580: b480 push {r7} 8000582: af00 add r7, sp, #0 return uwTick; 8000584: 4b02 ldr r3, [pc, #8] ; (8000590 ) 8000586: 681b ldr r3, [r3, #0] } 8000588: 4618 mov r0, r3 800058a: 46bd mov sp, r7 800058c: bc80 pop {r7} 800058e: 4770 bx lr 8000590: 200000d4 .word 0x200000d4 08000594 : * implementations in user file. * @param Delay specifies the delay time length, in milliseconds. * @retval None */ __weak void HAL_Delay(uint32_t Delay) { 8000594: b580 push {r7, lr} 8000596: b084 sub sp, #16 8000598: af00 add r7, sp, #0 800059a: 6078 str r0, [r7, #4] uint32_t tickstart = HAL_GetTick(); 800059c: f7ff fff0 bl 8000580 80005a0: 60b8 str r0, [r7, #8] uint32_t wait = Delay; 80005a2: 687b ldr r3, [r7, #4] 80005a4: 60fb str r3, [r7, #12] /* Add a freq to guarantee minimum wait */ if (wait < HAL_MAX_DELAY) 80005a6: 68fb ldr r3, [r7, #12] 80005a8: f1b3 3fff cmp.w r3, #4294967295 80005ac: d005 beq.n 80005ba { wait += (uint32_t)(uwTickFreq); 80005ae: 4b0a ldr r3, [pc, #40] ; (80005d8 ) 80005b0: 781b ldrb r3, [r3, #0] 80005b2: 461a mov r2, r3 80005b4: 68fb ldr r3, [r7, #12] 80005b6: 4413 add r3, r2 80005b8: 60fb str r3, [r7, #12] } while ((HAL_GetTick() - tickstart) < wait) 80005ba: bf00 nop 80005bc: f7ff ffe0 bl 8000580 80005c0: 4602 mov r2, r0 80005c2: 68bb ldr r3, [r7, #8] 80005c4: 1ad3 subs r3, r2, r3 80005c6: 68fa ldr r2, [r7, #12] 80005c8: 429a cmp r2, r3 80005ca: d8f7 bhi.n 80005bc { } } 80005cc: bf00 nop 80005ce: bf00 nop 80005d0: 3710 adds r7, #16 80005d2: 46bd mov sp, r7 80005d4: bd80 pop {r7, pc} 80005d6: bf00 nop 80005d8: 20000008 .word 0x20000008 080005dc <__NVIC_SetPriorityGrouping>: In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 80005dc: b480 push {r7} 80005de: b085 sub sp, #20 80005e0: af00 add r7, sp, #0 80005e2: 6078 str r0, [r7, #4] uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 80005e4: 687b ldr r3, [r7, #4] 80005e6: f003 0307 and.w r3, r3, #7 80005ea: 60fb str r3, [r7, #12] reg_value = SCB->AIRCR; /* read old register configuration */ 80005ec: 4b0c ldr r3, [pc, #48] ; (8000620 <__NVIC_SetPriorityGrouping+0x44>) 80005ee: 68db ldr r3, [r3, #12] 80005f0: 60bb str r3, [r7, #8] reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ 80005f2: 68ba ldr r2, [r7, #8] 80005f4: f64f 03ff movw r3, #63743 ; 0xf8ff 80005f8: 4013 ands r3, r2 80005fa: 60bb str r3, [r7, #8] reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ 80005fc: 68fb ldr r3, [r7, #12] 80005fe: 021a lsls r2, r3, #8 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 8000600: 68bb ldr r3, [r7, #8] 8000602: 4313 orrs r3, r2 reg_value = (reg_value | 8000604: f043 63bf orr.w r3, r3, #100139008 ; 0x5f80000 8000608: f443 3300 orr.w r3, r3, #131072 ; 0x20000 800060c: 60bb str r3, [r7, #8] SCB->AIRCR = reg_value; 800060e: 4a04 ldr r2, [pc, #16] ; (8000620 <__NVIC_SetPriorityGrouping+0x44>) 8000610: 68bb ldr r3, [r7, #8] 8000612: 60d3 str r3, [r2, #12] } 8000614: bf00 nop 8000616: 3714 adds r7, #20 8000618: 46bd mov sp, r7 800061a: bc80 pop {r7} 800061c: 4770 bx lr 800061e: bf00 nop 8000620: e000ed00 .word 0xe000ed00 08000624 <__NVIC_GetPriorityGrouping>: \brief Get Priority Grouping \details Reads the priority grouping field from the NVIC Interrupt Controller. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) { 8000624: b480 push {r7} 8000626: af00 add r7, sp, #0 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); 8000628: 4b04 ldr r3, [pc, #16] ; (800063c <__NVIC_GetPriorityGrouping+0x18>) 800062a: 68db ldr r3, [r3, #12] 800062c: 0a1b lsrs r3, r3, #8 800062e: f003 0307 and.w r3, r3, #7 } 8000632: 4618 mov r0, r3 8000634: 46bd mov sp, r7 8000636: bc80 pop {r7} 8000638: 4770 bx lr 800063a: bf00 nop 800063c: e000ed00 .word 0xe000ed00 08000640 <__NVIC_SetPriority>: \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { 8000640: b480 push {r7} 8000642: b083 sub sp, #12 8000644: af00 add r7, sp, #0 8000646: 4603 mov r3, r0 8000648: 6039 str r1, [r7, #0] 800064a: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) 800064c: f997 3007 ldrsb.w r3, [r7, #7] 8000650: 2b00 cmp r3, #0 8000652: db0a blt.n 800066a <__NVIC_SetPriority+0x2a> { NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 8000654: 683b ldr r3, [r7, #0] 8000656: b2da uxtb r2, r3 8000658: 490c ldr r1, [pc, #48] ; (800068c <__NVIC_SetPriority+0x4c>) 800065a: f997 3007 ldrsb.w r3, [r7, #7] 800065e: 0112 lsls r2, r2, #4 8000660: b2d2 uxtb r2, r2 8000662: 440b add r3, r1 8000664: f883 2300 strb.w r2, [r3, #768] ; 0x300 } else { SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } 8000668: e00a b.n 8000680 <__NVIC_SetPriority+0x40> SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 800066a: 683b ldr r3, [r7, #0] 800066c: b2da uxtb r2, r3 800066e: 4908 ldr r1, [pc, #32] ; (8000690 <__NVIC_SetPriority+0x50>) 8000670: 79fb ldrb r3, [r7, #7] 8000672: f003 030f and.w r3, r3, #15 8000676: 3b04 subs r3, #4 8000678: 0112 lsls r2, r2, #4 800067a: b2d2 uxtb r2, r2 800067c: 440b add r3, r1 800067e: 761a strb r2, [r3, #24] } 8000680: bf00 nop 8000682: 370c adds r7, #12 8000684: 46bd mov sp, r7 8000686: bc80 pop {r7} 8000688: 4770 bx lr 800068a: bf00 nop 800068c: e000e100 .word 0xe000e100 8000690: e000ed00 .word 0xe000ed00 08000694 : \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { 8000694: b480 push {r7} 8000696: b089 sub sp, #36 ; 0x24 8000698: af00 add r7, sp, #0 800069a: 60f8 str r0, [r7, #12] 800069c: 60b9 str r1, [r7, #8] 800069e: 607a str r2, [r7, #4] uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 80006a0: 68fb ldr r3, [r7, #12] 80006a2: f003 0307 and.w r3, r3, #7 80006a6: 61fb str r3, [r7, #28] uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 80006a8: 69fb ldr r3, [r7, #28] 80006aa: f1c3 0307 rsb r3, r3, #7 80006ae: 2b04 cmp r3, #4 80006b0: bf28 it cs 80006b2: 2304 movcs r3, #4 80006b4: 61bb str r3, [r7, #24] SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 80006b6: 69fb ldr r3, [r7, #28] 80006b8: 3304 adds r3, #4 80006ba: 2b06 cmp r3, #6 80006bc: d902 bls.n 80006c4 80006be: 69fb ldr r3, [r7, #28] 80006c0: 3b03 subs r3, #3 80006c2: e000 b.n 80006c6 80006c4: 2300 movs r3, #0 80006c6: 617b str r3, [r7, #20] return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 80006c8: f04f 32ff mov.w r2, #4294967295 80006cc: 69bb ldr r3, [r7, #24] 80006ce: fa02 f303 lsl.w r3, r2, r3 80006d2: 43da mvns r2, r3 80006d4: 68bb ldr r3, [r7, #8] 80006d6: 401a ands r2, r3 80006d8: 697b ldr r3, [r7, #20] 80006da: 409a lsls r2, r3 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) 80006dc: f04f 31ff mov.w r1, #4294967295 80006e0: 697b ldr r3, [r7, #20] 80006e2: fa01 f303 lsl.w r3, r1, r3 80006e6: 43d9 mvns r1, r3 80006e8: 687b ldr r3, [r7, #4] 80006ea: 400b ands r3, r1 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 80006ec: 4313 orrs r3, r2 ); } 80006ee: 4618 mov r0, r3 80006f0: 3724 adds r7, #36 ; 0x24 80006f2: 46bd mov sp, r7 80006f4: bc80 pop {r7} 80006f6: 4770 bx lr 080006f8 : \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { 80006f8: b580 push {r7, lr} 80006fa: b082 sub sp, #8 80006fc: af00 add r7, sp, #0 80006fe: 6078 str r0, [r7, #4] if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) 8000700: 687b ldr r3, [r7, #4] 8000702: 3b01 subs r3, #1 8000704: f1b3 7f80 cmp.w r3, #16777216 ; 0x1000000 8000708: d301 bcc.n 800070e { return (1UL); /* Reload value impossible */ 800070a: 2301 movs r3, #1 800070c: e00f b.n 800072e } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 800070e: 4a0a ldr r2, [pc, #40] ; (8000738 ) 8000710: 687b ldr r3, [r7, #4] 8000712: 3b01 subs r3, #1 8000714: 6053 str r3, [r2, #4] NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ 8000716: 210f movs r1, #15 8000718: f04f 30ff mov.w r0, #4294967295 800071c: f7ff ff90 bl 8000640 <__NVIC_SetPriority> SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ 8000720: 4b05 ldr r3, [pc, #20] ; (8000738 ) 8000722: 2200 movs r2, #0 8000724: 609a str r2, [r3, #8] SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 8000726: 4b04 ldr r3, [pc, #16] ; (8000738 ) 8000728: 2207 movs r2, #7 800072a: 601a str r2, [r3, #0] SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ 800072c: 2300 movs r3, #0 } 800072e: 4618 mov r0, r3 8000730: 3708 adds r7, #8 8000732: 46bd mov sp, r7 8000734: bd80 pop {r7, pc} 8000736: bf00 nop 8000738: e000e010 .word 0xe000e010 0800073c : * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. * The pending IRQ priority will be managed only by the subpriority. * @retval None */ void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 800073c: b580 push {r7, lr} 800073e: b082 sub sp, #8 8000740: af00 add r7, sp, #0 8000742: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ NVIC_SetPriorityGrouping(PriorityGroup); 8000744: 6878 ldr r0, [r7, #4] 8000746: f7ff ff49 bl 80005dc <__NVIC_SetPriorityGrouping> } 800074a: bf00 nop 800074c: 3708 adds r7, #8 800074e: 46bd mov sp, r7 8000750: bd80 pop {r7, pc} 08000752 : * This parameter can be a value between 0 and 15 * A lower priority value indicates a higher priority. * @retval None */ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) { 8000752: b580 push {r7, lr} 8000754: b086 sub sp, #24 8000756: af00 add r7, sp, #0 8000758: 4603 mov r3, r0 800075a: 60b9 str r1, [r7, #8] 800075c: 607a str r2, [r7, #4] 800075e: 73fb strb r3, [r7, #15] uint32_t prioritygroup = 0x00U; 8000760: 2300 movs r3, #0 8000762: 617b str r3, [r7, #20] /* Check the parameters */ assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); prioritygroup = NVIC_GetPriorityGrouping(); 8000764: f7ff ff5e bl 8000624 <__NVIC_GetPriorityGrouping> 8000768: 6178 str r0, [r7, #20] NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); 800076a: 687a ldr r2, [r7, #4] 800076c: 68b9 ldr r1, [r7, #8] 800076e: 6978 ldr r0, [r7, #20] 8000770: f7ff ff90 bl 8000694 8000774: 4602 mov r2, r0 8000776: f997 300f ldrsb.w r3, [r7, #15] 800077a: 4611 mov r1, r2 800077c: 4618 mov r0, r3 800077e: f7ff ff5f bl 8000640 <__NVIC_SetPriority> } 8000782: bf00 nop 8000784: 3718 adds r7, #24 8000786: 46bd mov sp, r7 8000788: bd80 pop {r7, pc} 0800078a : * @param TicksNumb: Specifies the ticks Number of ticks between two interrupts. * @retval status: - 0 Function succeeded. * - 1 Function failed. */ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) { 800078a: b580 push {r7, lr} 800078c: b082 sub sp, #8 800078e: af00 add r7, sp, #0 8000790: 6078 str r0, [r7, #4] return SysTick_Config(TicksNumb); 8000792: 6878 ldr r0, [r7, #4] 8000794: f7ff ffb0 bl 80006f8 8000798: 4603 mov r3, r0 } 800079a: 4618 mov r0, r3 800079c: 3708 adds r7, #8 800079e: 46bd mov sp, r7 80007a0: bd80 pop {r7, pc} ... 080007a4 : * @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains * the configuration information for the specified GPIO peripheral. * @retval None */ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) { 80007a4: b480 push {r7} 80007a6: b08b sub sp, #44 ; 0x2c 80007a8: af00 add r7, sp, #0 80007aa: 6078 str r0, [r7, #4] 80007ac: 6039 str r1, [r7, #0] uint32_t position = 0x00u; 80007ae: 2300 movs r3, #0 80007b0: 627b str r3, [r7, #36] ; 0x24 uint32_t ioposition; uint32_t iocurrent; uint32_t temp; uint32_t config = 0x00u; 80007b2: 2300 movs r3, #0 80007b4: 623b str r3, [r7, #32] assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); /* Configure the port pins */ while (((GPIO_Init->Pin) >> position) != 0x00u) 80007b6: e169 b.n 8000a8c { /* Get the IO position */ ioposition = (0x01uL << position); 80007b8: 2201 movs r2, #1 80007ba: 6a7b ldr r3, [r7, #36] ; 0x24 80007bc: fa02 f303 lsl.w r3, r2, r3 80007c0: 61fb str r3, [r7, #28] /* Get the current IO position */ iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition; 80007c2: 683b ldr r3, [r7, #0] 80007c4: 681b ldr r3, [r3, #0] 80007c6: 69fa ldr r2, [r7, #28] 80007c8: 4013 ands r3, r2 80007ca: 61bb str r3, [r7, #24] if (iocurrent == ioposition) 80007cc: 69ba ldr r2, [r7, #24] 80007ce: 69fb ldr r3, [r7, #28] 80007d0: 429a cmp r2, r3 80007d2: f040 8158 bne.w 8000a86 { /* Check the Alternate function parameters */ assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); /* Based on the required mode, filling config variable with MODEy[1:0] and CNFy[3:2] corresponding bits */ switch (GPIO_Init->Mode) 80007d6: 683b ldr r3, [r7, #0] 80007d8: 685b ldr r3, [r3, #4] 80007da: 4a9a ldr r2, [pc, #616] ; (8000a44 ) 80007dc: 4293 cmp r3, r2 80007de: d05e beq.n 800089e 80007e0: 4a98 ldr r2, [pc, #608] ; (8000a44 ) 80007e2: 4293 cmp r3, r2 80007e4: d875 bhi.n 80008d2 80007e6: 4a98 ldr r2, [pc, #608] ; (8000a48 ) 80007e8: 4293 cmp r3, r2 80007ea: d058 beq.n 800089e 80007ec: 4a96 ldr r2, [pc, #600] ; (8000a48 ) 80007ee: 4293 cmp r3, r2 80007f0: d86f bhi.n 80008d2 80007f2: 4a96 ldr r2, [pc, #600] ; (8000a4c ) 80007f4: 4293 cmp r3, r2 80007f6: d052 beq.n 800089e 80007f8: 4a94 ldr r2, [pc, #592] ; (8000a4c ) 80007fa: 4293 cmp r3, r2 80007fc: d869 bhi.n 80008d2 80007fe: 4a94 ldr r2, [pc, #592] ; (8000a50 ) 8000800: 4293 cmp r3, r2 8000802: d04c beq.n 800089e 8000804: 4a92 ldr r2, [pc, #584] ; (8000a50 ) 8000806: 4293 cmp r3, r2 8000808: d863 bhi.n 80008d2 800080a: 4a92 ldr r2, [pc, #584] ; (8000a54 ) 800080c: 4293 cmp r3, r2 800080e: d046 beq.n 800089e 8000810: 4a90 ldr r2, [pc, #576] ; (8000a54 ) 8000812: 4293 cmp r3, r2 8000814: d85d bhi.n 80008d2 8000816: 2b12 cmp r3, #18 8000818: d82a bhi.n 8000870 800081a: 2b12 cmp r3, #18 800081c: d859 bhi.n 80008d2 800081e: a201 add r2, pc, #4 ; (adr r2, 8000824 ) 8000820: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8000824: 0800089f .word 0x0800089f 8000828: 08000879 .word 0x08000879 800082c: 0800088b .word 0x0800088b 8000830: 080008cd .word 0x080008cd 8000834: 080008d3 .word 0x080008d3 8000838: 080008d3 .word 0x080008d3 800083c: 080008d3 .word 0x080008d3 8000840: 080008d3 .word 0x080008d3 8000844: 080008d3 .word 0x080008d3 8000848: 080008d3 .word 0x080008d3 800084c: 080008d3 .word 0x080008d3 8000850: 080008d3 .word 0x080008d3 8000854: 080008d3 .word 0x080008d3 8000858: 080008d3 .word 0x080008d3 800085c: 080008d3 .word 0x080008d3 8000860: 080008d3 .word 0x080008d3 8000864: 080008d3 .word 0x080008d3 8000868: 08000881 .word 0x08000881 800086c: 08000895 .word 0x08000895 8000870: 4a79 ldr r2, [pc, #484] ; (8000a58 ) 8000872: 4293 cmp r3, r2 8000874: d013 beq.n 800089e config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG; break; /* Parameters are checked with assert_param */ default: break; 8000876: e02c b.n 80008d2 config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_PP; 8000878: 683b ldr r3, [r7, #0] 800087a: 68db ldr r3, [r3, #12] 800087c: 623b str r3, [r7, #32] break; 800087e: e029 b.n 80008d4 config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_OD; 8000880: 683b ldr r3, [r7, #0] 8000882: 68db ldr r3, [r3, #12] 8000884: 3304 adds r3, #4 8000886: 623b str r3, [r7, #32] break; 8000888: e024 b.n 80008d4 config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_PP; 800088a: 683b ldr r3, [r7, #0] 800088c: 68db ldr r3, [r3, #12] 800088e: 3308 adds r3, #8 8000890: 623b str r3, [r7, #32] break; 8000892: e01f b.n 80008d4 config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_OD; 8000894: 683b ldr r3, [r7, #0] 8000896: 68db ldr r3, [r3, #12] 8000898: 330c adds r3, #12 800089a: 623b str r3, [r7, #32] break; 800089c: e01a b.n 80008d4 if (GPIO_Init->Pull == GPIO_NOPULL) 800089e: 683b ldr r3, [r7, #0] 80008a0: 689b ldr r3, [r3, #8] 80008a2: 2b00 cmp r3, #0 80008a4: d102 bne.n 80008ac config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_FLOATING; 80008a6: 2304 movs r3, #4 80008a8: 623b str r3, [r7, #32] break; 80008aa: e013 b.n 80008d4 else if (GPIO_Init->Pull == GPIO_PULLUP) 80008ac: 683b ldr r3, [r7, #0] 80008ae: 689b ldr r3, [r3, #8] 80008b0: 2b01 cmp r3, #1 80008b2: d105 bne.n 80008c0 config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD; 80008b4: 2308 movs r3, #8 80008b6: 623b str r3, [r7, #32] GPIOx->BSRR = ioposition; 80008b8: 687b ldr r3, [r7, #4] 80008ba: 69fa ldr r2, [r7, #28] 80008bc: 611a str r2, [r3, #16] break; 80008be: e009 b.n 80008d4 config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD; 80008c0: 2308 movs r3, #8 80008c2: 623b str r3, [r7, #32] GPIOx->BRR = ioposition; 80008c4: 687b ldr r3, [r7, #4] 80008c6: 69fa ldr r2, [r7, #28] 80008c8: 615a str r2, [r3, #20] break; 80008ca: e003 b.n 80008d4 config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG; 80008cc: 2300 movs r3, #0 80008ce: 623b str r3, [r7, #32] break; 80008d0: e000 b.n 80008d4 break; 80008d2: bf00 nop } /* Check if the current bit belongs to first half or last half of the pin count number in order to address CRH or CRL register*/ configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL : &GPIOx->CRH; 80008d4: 69bb ldr r3, [r7, #24] 80008d6: 2bff cmp r3, #255 ; 0xff 80008d8: d801 bhi.n 80008de 80008da: 687b ldr r3, [r7, #4] 80008dc: e001 b.n 80008e2 80008de: 687b ldr r3, [r7, #4] 80008e0: 3304 adds r3, #4 80008e2: 617b str r3, [r7, #20] registeroffset = (iocurrent < GPIO_PIN_8) ? (position << 2u) : ((position - 8u) << 2u); 80008e4: 69bb ldr r3, [r7, #24] 80008e6: 2bff cmp r3, #255 ; 0xff 80008e8: d802 bhi.n 80008f0 80008ea: 6a7b ldr r3, [r7, #36] ; 0x24 80008ec: 009b lsls r3, r3, #2 80008ee: e002 b.n 80008f6 80008f0: 6a7b ldr r3, [r7, #36] ; 0x24 80008f2: 3b08 subs r3, #8 80008f4: 009b lsls r3, r3, #2 80008f6: 613b str r3, [r7, #16] /* Apply the new configuration of the pin to the register */ MODIFY_REG((*configregister), ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset), (config << registeroffset)); 80008f8: 697b ldr r3, [r7, #20] 80008fa: 681a ldr r2, [r3, #0] 80008fc: 210f movs r1, #15 80008fe: 693b ldr r3, [r7, #16] 8000900: fa01 f303 lsl.w r3, r1, r3 8000904: 43db mvns r3, r3 8000906: 401a ands r2, r3 8000908: 6a39 ldr r1, [r7, #32] 800090a: 693b ldr r3, [r7, #16] 800090c: fa01 f303 lsl.w r3, r1, r3 8000910: 431a orrs r2, r3 8000912: 697b ldr r3, [r7, #20] 8000914: 601a str r2, [r3, #0] /*--------------------- EXTI Mode Configuration ------------------------*/ /* Configure the External Interrupt or event for the current IO */ if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE) 8000916: 683b ldr r3, [r7, #0] 8000918: 685b ldr r3, [r3, #4] 800091a: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 800091e: 2b00 cmp r3, #0 8000920: f000 80b1 beq.w 8000a86 { /* Enable AFIO Clock */ __HAL_RCC_AFIO_CLK_ENABLE(); 8000924: 4b4d ldr r3, [pc, #308] ; (8000a5c ) 8000926: 699b ldr r3, [r3, #24] 8000928: 4a4c ldr r2, [pc, #304] ; (8000a5c ) 800092a: f043 0301 orr.w r3, r3, #1 800092e: 6193 str r3, [r2, #24] 8000930: 4b4a ldr r3, [pc, #296] ; (8000a5c ) 8000932: 699b ldr r3, [r3, #24] 8000934: f003 0301 and.w r3, r3, #1 8000938: 60bb str r3, [r7, #8] 800093a: 68bb ldr r3, [r7, #8] temp = AFIO->EXTICR[position >> 2u]; 800093c: 4a48 ldr r2, [pc, #288] ; (8000a60 ) 800093e: 6a7b ldr r3, [r7, #36] ; 0x24 8000940: 089b lsrs r3, r3, #2 8000942: 3302 adds r3, #2 8000944: f852 3023 ldr.w r3, [r2, r3, lsl #2] 8000948: 60fb str r3, [r7, #12] CLEAR_BIT(temp, (0x0Fu) << (4u * (position & 0x03u))); 800094a: 6a7b ldr r3, [r7, #36] ; 0x24 800094c: f003 0303 and.w r3, r3, #3 8000950: 009b lsls r3, r3, #2 8000952: 220f movs r2, #15 8000954: fa02 f303 lsl.w r3, r2, r3 8000958: 43db mvns r3, r3 800095a: 68fa ldr r2, [r7, #12] 800095c: 4013 ands r3, r2 800095e: 60fb str r3, [r7, #12] SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4u * (position & 0x03u))); 8000960: 687b ldr r3, [r7, #4] 8000962: 4a40 ldr r2, [pc, #256] ; (8000a64 ) 8000964: 4293 cmp r3, r2 8000966: d013 beq.n 8000990 8000968: 687b ldr r3, [r7, #4] 800096a: 4a3f ldr r2, [pc, #252] ; (8000a68 ) 800096c: 4293 cmp r3, r2 800096e: d00d beq.n 800098c 8000970: 687b ldr r3, [r7, #4] 8000972: 4a3e ldr r2, [pc, #248] ; (8000a6c ) 8000974: 4293 cmp r3, r2 8000976: d007 beq.n 8000988 8000978: 687b ldr r3, [r7, #4] 800097a: 4a3d ldr r2, [pc, #244] ; (8000a70 ) 800097c: 4293 cmp r3, r2 800097e: d101 bne.n 8000984 8000980: 2303 movs r3, #3 8000982: e006 b.n 8000992 8000984: 2304 movs r3, #4 8000986: e004 b.n 8000992 8000988: 2302 movs r3, #2 800098a: e002 b.n 8000992 800098c: 2301 movs r3, #1 800098e: e000 b.n 8000992 8000990: 2300 movs r3, #0 8000992: 6a7a ldr r2, [r7, #36] ; 0x24 8000994: f002 0203 and.w r2, r2, #3 8000998: 0092 lsls r2, r2, #2 800099a: 4093 lsls r3, r2 800099c: 68fa ldr r2, [r7, #12] 800099e: 4313 orrs r3, r2 80009a0: 60fb str r3, [r7, #12] AFIO->EXTICR[position >> 2u] = temp; 80009a2: 492f ldr r1, [pc, #188] ; (8000a60 ) 80009a4: 6a7b ldr r3, [r7, #36] ; 0x24 80009a6: 089b lsrs r3, r3, #2 80009a8: 3302 adds r3, #2 80009aa: 68fa ldr r2, [r7, #12] 80009ac: f841 2023 str.w r2, [r1, r3, lsl #2] /* Configure the interrupt mask */ if ((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT) 80009b0: 683b ldr r3, [r7, #0] 80009b2: 685b ldr r3, [r3, #4] 80009b4: f403 3380 and.w r3, r3, #65536 ; 0x10000 80009b8: 2b00 cmp r3, #0 80009ba: d006 beq.n 80009ca { SET_BIT(EXTI->IMR, iocurrent); 80009bc: 4b2d ldr r3, [pc, #180] ; (8000a74 ) 80009be: 681a ldr r2, [r3, #0] 80009c0: 492c ldr r1, [pc, #176] ; (8000a74 ) 80009c2: 69bb ldr r3, [r7, #24] 80009c4: 4313 orrs r3, r2 80009c6: 600b str r3, [r1, #0] 80009c8: e006 b.n 80009d8 } else { CLEAR_BIT(EXTI->IMR, iocurrent); 80009ca: 4b2a ldr r3, [pc, #168] ; (8000a74 ) 80009cc: 681a ldr r2, [r3, #0] 80009ce: 69bb ldr r3, [r7, #24] 80009d0: 43db mvns r3, r3 80009d2: 4928 ldr r1, [pc, #160] ; (8000a74 ) 80009d4: 4013 ands r3, r2 80009d6: 600b str r3, [r1, #0] } /* Configure the event mask */ if ((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT) 80009d8: 683b ldr r3, [r7, #0] 80009da: 685b ldr r3, [r3, #4] 80009dc: f403 3300 and.w r3, r3, #131072 ; 0x20000 80009e0: 2b00 cmp r3, #0 80009e2: d006 beq.n 80009f2 { SET_BIT(EXTI->EMR, iocurrent); 80009e4: 4b23 ldr r3, [pc, #140] ; (8000a74 ) 80009e6: 685a ldr r2, [r3, #4] 80009e8: 4922 ldr r1, [pc, #136] ; (8000a74 ) 80009ea: 69bb ldr r3, [r7, #24] 80009ec: 4313 orrs r3, r2 80009ee: 604b str r3, [r1, #4] 80009f0: e006 b.n 8000a00 } else { CLEAR_BIT(EXTI->EMR, iocurrent); 80009f2: 4b20 ldr r3, [pc, #128] ; (8000a74 ) 80009f4: 685a ldr r2, [r3, #4] 80009f6: 69bb ldr r3, [r7, #24] 80009f8: 43db mvns r3, r3 80009fa: 491e ldr r1, [pc, #120] ; (8000a74 ) 80009fc: 4013 ands r3, r2 80009fe: 604b str r3, [r1, #4] } /* Enable or disable the rising trigger */ if ((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE) 8000a00: 683b ldr r3, [r7, #0] 8000a02: 685b ldr r3, [r3, #4] 8000a04: f403 1380 and.w r3, r3, #1048576 ; 0x100000 8000a08: 2b00 cmp r3, #0 8000a0a: d006 beq.n 8000a1a { SET_BIT(EXTI->RTSR, iocurrent); 8000a0c: 4b19 ldr r3, [pc, #100] ; (8000a74 ) 8000a0e: 689a ldr r2, [r3, #8] 8000a10: 4918 ldr r1, [pc, #96] ; (8000a74 ) 8000a12: 69bb ldr r3, [r7, #24] 8000a14: 4313 orrs r3, r2 8000a16: 608b str r3, [r1, #8] 8000a18: e006 b.n 8000a28 } else { CLEAR_BIT(EXTI->RTSR, iocurrent); 8000a1a: 4b16 ldr r3, [pc, #88] ; (8000a74 ) 8000a1c: 689a ldr r2, [r3, #8] 8000a1e: 69bb ldr r3, [r7, #24] 8000a20: 43db mvns r3, r3 8000a22: 4914 ldr r1, [pc, #80] ; (8000a74 ) 8000a24: 4013 ands r3, r2 8000a26: 608b str r3, [r1, #8] } /* Enable or disable the falling trigger */ if ((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE) 8000a28: 683b ldr r3, [r7, #0] 8000a2a: 685b ldr r3, [r3, #4] 8000a2c: f403 1300 and.w r3, r3, #2097152 ; 0x200000 8000a30: 2b00 cmp r3, #0 8000a32: d021 beq.n 8000a78 { SET_BIT(EXTI->FTSR, iocurrent); 8000a34: 4b0f ldr r3, [pc, #60] ; (8000a74 ) 8000a36: 68da ldr r2, [r3, #12] 8000a38: 490e ldr r1, [pc, #56] ; (8000a74 ) 8000a3a: 69bb ldr r3, [r7, #24] 8000a3c: 4313 orrs r3, r2 8000a3e: 60cb str r3, [r1, #12] 8000a40: e021 b.n 8000a86 8000a42: bf00 nop 8000a44: 10320000 .word 0x10320000 8000a48: 10310000 .word 0x10310000 8000a4c: 10220000 .word 0x10220000 8000a50: 10210000 .word 0x10210000 8000a54: 10120000 .word 0x10120000 8000a58: 10110000 .word 0x10110000 8000a5c: 40021000 .word 0x40021000 8000a60: 40010000 .word 0x40010000 8000a64: 40010800 .word 0x40010800 8000a68: 40010c00 .word 0x40010c00 8000a6c: 40011000 .word 0x40011000 8000a70: 40011400 .word 0x40011400 8000a74: 40010400 .word 0x40010400 } else { CLEAR_BIT(EXTI->FTSR, iocurrent); 8000a78: 4b0b ldr r3, [pc, #44] ; (8000aa8 ) 8000a7a: 68da ldr r2, [r3, #12] 8000a7c: 69bb ldr r3, [r7, #24] 8000a7e: 43db mvns r3, r3 8000a80: 4909 ldr r1, [pc, #36] ; (8000aa8 ) 8000a82: 4013 ands r3, r2 8000a84: 60cb str r3, [r1, #12] } } } position++; 8000a86: 6a7b ldr r3, [r7, #36] ; 0x24 8000a88: 3301 adds r3, #1 8000a8a: 627b str r3, [r7, #36] ; 0x24 while (((GPIO_Init->Pin) >> position) != 0x00u) 8000a8c: 683b ldr r3, [r7, #0] 8000a8e: 681a ldr r2, [r3, #0] 8000a90: 6a7b ldr r3, [r7, #36] ; 0x24 8000a92: fa22 f303 lsr.w r3, r2, r3 8000a96: 2b00 cmp r3, #0 8000a98: f47f ae8e bne.w 80007b8 } } 8000a9c: bf00 nop 8000a9e: bf00 nop 8000aa0: 372c adds r7, #44 ; 0x2c 8000aa2: 46bd mov sp, r7 8000aa4: bc80 pop {r7} 8000aa6: 4770 bx lr 8000aa8: 40010400 .word 0x40010400 08000aac : * supported by this macro. User should request a transition to HSE Off * first and then HSE On or HSE Bypass. * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { 8000aac: b580 push {r7, lr} 8000aae: b086 sub sp, #24 8000ab0: af00 add r7, sp, #0 8000ab2: 6078 str r0, [r7, #4] uint32_t tickstart; uint32_t pll_config; /* Check Null pointer */ if (RCC_OscInitStruct == NULL) 8000ab4: 687b ldr r3, [r7, #4] 8000ab6: 2b00 cmp r3, #0 8000ab8: d101 bne.n 8000abe { return HAL_ERROR; 8000aba: 2301 movs r3, #1 8000abc: e272 b.n 8000fa4 /* Check the parameters */ assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); /*------------------------------- HSE Configuration ------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) 8000abe: 687b ldr r3, [r7, #4] 8000ac0: 681b ldr r3, [r3, #0] 8000ac2: f003 0301 and.w r3, r3, #1 8000ac6: 2b00 cmp r3, #0 8000ac8: f000 8087 beq.w 8000bda { /* Check the parameters */ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */ if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE) 8000acc: 4b92 ldr r3, [pc, #584] ; (8000d18 ) 8000ace: 685b ldr r3, [r3, #4] 8000ad0: f003 030c and.w r3, r3, #12 8000ad4: 2b04 cmp r3, #4 8000ad6: d00c beq.n 8000af2 || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE))) 8000ad8: 4b8f ldr r3, [pc, #572] ; (8000d18 ) 8000ada: 685b ldr r3, [r3, #4] 8000adc: f003 030c and.w r3, r3, #12 8000ae0: 2b08 cmp r3, #8 8000ae2: d112 bne.n 8000b0a 8000ae4: 4b8c ldr r3, [pc, #560] ; (8000d18 ) 8000ae6: 685b ldr r3, [r3, #4] 8000ae8: f403 3380 and.w r3, r3, #65536 ; 0x10000 8000aec: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 8000af0: d10b bne.n 8000b0a { if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 8000af2: 4b89 ldr r3, [pc, #548] ; (8000d18 ) 8000af4: 681b ldr r3, [r3, #0] 8000af6: f403 3300 and.w r3, r3, #131072 ; 0x20000 8000afa: 2b00 cmp r3, #0 8000afc: d06c beq.n 8000bd8 8000afe: 687b ldr r3, [r7, #4] 8000b00: 685b ldr r3, [r3, #4] 8000b02: 2b00 cmp r3, #0 8000b04: d168 bne.n 8000bd8 { return HAL_ERROR; 8000b06: 2301 movs r3, #1 8000b08: e24c b.n 8000fa4 } } else { /* Set the new HSE configuration ---------------------------------------*/ __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); 8000b0a: 687b ldr r3, [r7, #4] 8000b0c: 685b ldr r3, [r3, #4] 8000b0e: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 8000b12: d106 bne.n 8000b22 8000b14: 4b80 ldr r3, [pc, #512] ; (8000d18 ) 8000b16: 681b ldr r3, [r3, #0] 8000b18: 4a7f ldr r2, [pc, #508] ; (8000d18 ) 8000b1a: f443 3380 orr.w r3, r3, #65536 ; 0x10000 8000b1e: 6013 str r3, [r2, #0] 8000b20: e02e b.n 8000b80 8000b22: 687b ldr r3, [r7, #4] 8000b24: 685b ldr r3, [r3, #4] 8000b26: 2b00 cmp r3, #0 8000b28: d10c bne.n 8000b44 8000b2a: 4b7b ldr r3, [pc, #492] ; (8000d18 ) 8000b2c: 681b ldr r3, [r3, #0] 8000b2e: 4a7a ldr r2, [pc, #488] ; (8000d18 ) 8000b30: f423 3380 bic.w r3, r3, #65536 ; 0x10000 8000b34: 6013 str r3, [r2, #0] 8000b36: 4b78 ldr r3, [pc, #480] ; (8000d18 ) 8000b38: 681b ldr r3, [r3, #0] 8000b3a: 4a77 ldr r2, [pc, #476] ; (8000d18 ) 8000b3c: f423 2380 bic.w r3, r3, #262144 ; 0x40000 8000b40: 6013 str r3, [r2, #0] 8000b42: e01d b.n 8000b80 8000b44: 687b ldr r3, [r7, #4] 8000b46: 685b ldr r3, [r3, #4] 8000b48: f5b3 2fa0 cmp.w r3, #327680 ; 0x50000 8000b4c: d10c bne.n 8000b68 8000b4e: 4b72 ldr r3, [pc, #456] ; (8000d18 ) 8000b50: 681b ldr r3, [r3, #0] 8000b52: 4a71 ldr r2, [pc, #452] ; (8000d18 ) 8000b54: f443 2380 orr.w r3, r3, #262144 ; 0x40000 8000b58: 6013 str r3, [r2, #0] 8000b5a: 4b6f ldr r3, [pc, #444] ; (8000d18 ) 8000b5c: 681b ldr r3, [r3, #0] 8000b5e: 4a6e ldr r2, [pc, #440] ; (8000d18 ) 8000b60: f443 3380 orr.w r3, r3, #65536 ; 0x10000 8000b64: 6013 str r3, [r2, #0] 8000b66: e00b b.n 8000b80 8000b68: 4b6b ldr r3, [pc, #428] ; (8000d18 ) 8000b6a: 681b ldr r3, [r3, #0] 8000b6c: 4a6a ldr r2, [pc, #424] ; (8000d18 ) 8000b6e: f423 3380 bic.w r3, r3, #65536 ; 0x10000 8000b72: 6013 str r3, [r2, #0] 8000b74: 4b68 ldr r3, [pc, #416] ; (8000d18 ) 8000b76: 681b ldr r3, [r3, #0] 8000b78: 4a67 ldr r2, [pc, #412] ; (8000d18 ) 8000b7a: f423 2380 bic.w r3, r3, #262144 ; 0x40000 8000b7e: 6013 str r3, [r2, #0] /* Check the HSE State */ if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF) 8000b80: 687b ldr r3, [r7, #4] 8000b82: 685b ldr r3, [r3, #4] 8000b84: 2b00 cmp r3, #0 8000b86: d013 beq.n 8000bb0 { /* Get Start Tick */ tickstart = HAL_GetTick(); 8000b88: f7ff fcfa bl 8000580 8000b8c: 6138 str r0, [r7, #16] /* Wait till HSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 8000b8e: e008 b.n 8000ba2 { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 8000b90: f7ff fcf6 bl 8000580 8000b94: 4602 mov r2, r0 8000b96: 693b ldr r3, [r7, #16] 8000b98: 1ad3 subs r3, r2, r3 8000b9a: 2b64 cmp r3, #100 ; 0x64 8000b9c: d901 bls.n 8000ba2 { return HAL_TIMEOUT; 8000b9e: 2303 movs r3, #3 8000ba0: e200 b.n 8000fa4 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 8000ba2: 4b5d ldr r3, [pc, #372] ; (8000d18 ) 8000ba4: 681b ldr r3, [r3, #0] 8000ba6: f403 3300 and.w r3, r3, #131072 ; 0x20000 8000baa: 2b00 cmp r3, #0 8000bac: d0f0 beq.n 8000b90 8000bae: e014 b.n 8000bda } } else { /* Get Start Tick */ tickstart = HAL_GetTick(); 8000bb0: f7ff fce6 bl 8000580 8000bb4: 6138 str r0, [r7, #16] /* Wait till HSE is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) 8000bb6: e008 b.n 8000bca { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 8000bb8: f7ff fce2 bl 8000580 8000bbc: 4602 mov r2, r0 8000bbe: 693b ldr r3, [r7, #16] 8000bc0: 1ad3 subs r3, r2, r3 8000bc2: 2b64 cmp r3, #100 ; 0x64 8000bc4: d901 bls.n 8000bca { return HAL_TIMEOUT; 8000bc6: 2303 movs r3, #3 8000bc8: e1ec b.n 8000fa4 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) 8000bca: 4b53 ldr r3, [pc, #332] ; (8000d18 ) 8000bcc: 681b ldr r3, [r3, #0] 8000bce: f403 3300 and.w r3, r3, #131072 ; 0x20000 8000bd2: 2b00 cmp r3, #0 8000bd4: d1f0 bne.n 8000bb8 8000bd6: e000 b.n 8000bda if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 8000bd8: bf00 nop } } } } /*----------------------------- HSI Configuration --------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) 8000bda: 687b ldr r3, [r7, #4] 8000bdc: 681b ldr r3, [r3, #0] 8000bde: f003 0302 and.w r3, r3, #2 8000be2: 2b00 cmp r3, #0 8000be4: d063 beq.n 8000cae /* Check the parameters */ assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI) 8000be6: 4b4c ldr r3, [pc, #304] ; (8000d18 ) 8000be8: 685b ldr r3, [r3, #4] 8000bea: f003 030c and.w r3, r3, #12 8000bee: 2b00 cmp r3, #0 8000bf0: d00b beq.n 8000c0a || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI_DIV2))) 8000bf2: 4b49 ldr r3, [pc, #292] ; (8000d18 ) 8000bf4: 685b ldr r3, [r3, #4] 8000bf6: f003 030c and.w r3, r3, #12 8000bfa: 2b08 cmp r3, #8 8000bfc: d11c bne.n 8000c38 8000bfe: 4b46 ldr r3, [pc, #280] ; (8000d18 ) 8000c00: 685b ldr r3, [r3, #4] 8000c02: f403 3380 and.w r3, r3, #65536 ; 0x10000 8000c06: 2b00 cmp r3, #0 8000c08: d116 bne.n 8000c38 { /* When HSI is used as system clock it will not disabled */ if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) 8000c0a: 4b43 ldr r3, [pc, #268] ; (8000d18 ) 8000c0c: 681b ldr r3, [r3, #0] 8000c0e: f003 0302 and.w r3, r3, #2 8000c12: 2b00 cmp r3, #0 8000c14: d005 beq.n 8000c22 8000c16: 687b ldr r3, [r7, #4] 8000c18: 691b ldr r3, [r3, #16] 8000c1a: 2b01 cmp r3, #1 8000c1c: d001 beq.n 8000c22 { return HAL_ERROR; 8000c1e: 2301 movs r3, #1 8000c20: e1c0 b.n 8000fa4 } /* Otherwise, just the calibration is allowed */ else { /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 8000c22: 4b3d ldr r3, [pc, #244] ; (8000d18 ) 8000c24: 681b ldr r3, [r3, #0] 8000c26: f023 02f8 bic.w r2, r3, #248 ; 0xf8 8000c2a: 687b ldr r3, [r7, #4] 8000c2c: 695b ldr r3, [r3, #20] 8000c2e: 00db lsls r3, r3, #3 8000c30: 4939 ldr r1, [pc, #228] ; (8000d18 ) 8000c32: 4313 orrs r3, r2 8000c34: 600b str r3, [r1, #0] if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) 8000c36: e03a b.n 8000cae } } else { /* Check the HSI State */ if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF) 8000c38: 687b ldr r3, [r7, #4] 8000c3a: 691b ldr r3, [r3, #16] 8000c3c: 2b00 cmp r3, #0 8000c3e: d020 beq.n 8000c82 { /* Enable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_ENABLE(); 8000c40: 4b36 ldr r3, [pc, #216] ; (8000d1c ) 8000c42: 2201 movs r2, #1 8000c44: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8000c46: f7ff fc9b bl 8000580 8000c4a: 6138 str r0, [r7, #16] /* Wait till HSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 8000c4c: e008 b.n 8000c60 { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 8000c4e: f7ff fc97 bl 8000580 8000c52: 4602 mov r2, r0 8000c54: 693b ldr r3, [r7, #16] 8000c56: 1ad3 subs r3, r2, r3 8000c58: 2b02 cmp r3, #2 8000c5a: d901 bls.n 8000c60 { return HAL_TIMEOUT; 8000c5c: 2303 movs r3, #3 8000c5e: e1a1 b.n 8000fa4 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 8000c60: 4b2d ldr r3, [pc, #180] ; (8000d18 ) 8000c62: 681b ldr r3, [r3, #0] 8000c64: f003 0302 and.w r3, r3, #2 8000c68: 2b00 cmp r3, #0 8000c6a: d0f0 beq.n 8000c4e } } /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 8000c6c: 4b2a ldr r3, [pc, #168] ; (8000d18 ) 8000c6e: 681b ldr r3, [r3, #0] 8000c70: f023 02f8 bic.w r2, r3, #248 ; 0xf8 8000c74: 687b ldr r3, [r7, #4] 8000c76: 695b ldr r3, [r3, #20] 8000c78: 00db lsls r3, r3, #3 8000c7a: 4927 ldr r1, [pc, #156] ; (8000d18 ) 8000c7c: 4313 orrs r3, r2 8000c7e: 600b str r3, [r1, #0] 8000c80: e015 b.n 8000cae } else { /* Disable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_DISABLE(); 8000c82: 4b26 ldr r3, [pc, #152] ; (8000d1c ) 8000c84: 2200 movs r2, #0 8000c86: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8000c88: f7ff fc7a bl 8000580 8000c8c: 6138 str r0, [r7, #16] /* Wait till HSI is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) 8000c8e: e008 b.n 8000ca2 { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 8000c90: f7ff fc76 bl 8000580 8000c94: 4602 mov r2, r0 8000c96: 693b ldr r3, [r7, #16] 8000c98: 1ad3 subs r3, r2, r3 8000c9a: 2b02 cmp r3, #2 8000c9c: d901 bls.n 8000ca2 { return HAL_TIMEOUT; 8000c9e: 2303 movs r3, #3 8000ca0: e180 b.n 8000fa4 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) 8000ca2: 4b1d ldr r3, [pc, #116] ; (8000d18 ) 8000ca4: 681b ldr r3, [r3, #0] 8000ca6: f003 0302 and.w r3, r3, #2 8000caa: 2b00 cmp r3, #0 8000cac: d1f0 bne.n 8000c90 } } } } /*------------------------------ LSI Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) 8000cae: 687b ldr r3, [r7, #4] 8000cb0: 681b ldr r3, [r3, #0] 8000cb2: f003 0308 and.w r3, r3, #8 8000cb6: 2b00 cmp r3, #0 8000cb8: d03a beq.n 8000d30 { /* Check the parameters */ assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); /* Check the LSI State */ if (RCC_OscInitStruct->LSIState != RCC_LSI_OFF) 8000cba: 687b ldr r3, [r7, #4] 8000cbc: 699b ldr r3, [r3, #24] 8000cbe: 2b00 cmp r3, #0 8000cc0: d019 beq.n 8000cf6 { /* Enable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_ENABLE(); 8000cc2: 4b17 ldr r3, [pc, #92] ; (8000d20 ) 8000cc4: 2201 movs r2, #1 8000cc6: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8000cc8: f7ff fc5a bl 8000580 8000ccc: 6138 str r0, [r7, #16] /* Wait till LSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) 8000cce: e008 b.n 8000ce2 { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 8000cd0: f7ff fc56 bl 8000580 8000cd4: 4602 mov r2, r0 8000cd6: 693b ldr r3, [r7, #16] 8000cd8: 1ad3 subs r3, r2, r3 8000cda: 2b02 cmp r3, #2 8000cdc: d901 bls.n 8000ce2 { return HAL_TIMEOUT; 8000cde: 2303 movs r3, #3 8000ce0: e160 b.n 8000fa4 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) 8000ce2: 4b0d ldr r3, [pc, #52] ; (8000d18 ) 8000ce4: 6a5b ldr r3, [r3, #36] ; 0x24 8000ce6: f003 0302 and.w r3, r3, #2 8000cea: 2b00 cmp r3, #0 8000cec: d0f0 beq.n 8000cd0 } } /* To have a fully stabilized clock in the specified range, a software delay of 1ms should be added.*/ RCC_Delay(1); 8000cee: 2001 movs r0, #1 8000cf0: f000 fad8 bl 80012a4 8000cf4: e01c b.n 8000d30 } else { /* Disable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_DISABLE(); 8000cf6: 4b0a ldr r3, [pc, #40] ; (8000d20 ) 8000cf8: 2200 movs r2, #0 8000cfa: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8000cfc: f7ff fc40 bl 8000580 8000d00: 6138 str r0, [r7, #16] /* Wait till LSI is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) 8000d02: e00f b.n 8000d24 { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 8000d04: f7ff fc3c bl 8000580 8000d08: 4602 mov r2, r0 8000d0a: 693b ldr r3, [r7, #16] 8000d0c: 1ad3 subs r3, r2, r3 8000d0e: 2b02 cmp r3, #2 8000d10: d908 bls.n 8000d24 { return HAL_TIMEOUT; 8000d12: 2303 movs r3, #3 8000d14: e146 b.n 8000fa4 8000d16: bf00 nop 8000d18: 40021000 .word 0x40021000 8000d1c: 42420000 .word 0x42420000 8000d20: 42420480 .word 0x42420480 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) 8000d24: 4b92 ldr r3, [pc, #584] ; (8000f70 ) 8000d26: 6a5b ldr r3, [r3, #36] ; 0x24 8000d28: f003 0302 and.w r3, r3, #2 8000d2c: 2b00 cmp r3, #0 8000d2e: d1e9 bne.n 8000d04 } } } } /*------------------------------ LSE Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) 8000d30: 687b ldr r3, [r7, #4] 8000d32: 681b ldr r3, [r3, #0] 8000d34: f003 0304 and.w r3, r3, #4 8000d38: 2b00 cmp r3, #0 8000d3a: f000 80a6 beq.w 8000e8a { FlagStatus pwrclkchanged = RESET; 8000d3e: 2300 movs r3, #0 8000d40: 75fb strb r3, [r7, #23] /* Check the parameters */ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); /* Update LSE configuration in Backup Domain control register */ /* Requires to enable write access to Backup Domain of necessary */ if (__HAL_RCC_PWR_IS_CLK_DISABLED()) 8000d42: 4b8b ldr r3, [pc, #556] ; (8000f70 ) 8000d44: 69db ldr r3, [r3, #28] 8000d46: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 8000d4a: 2b00 cmp r3, #0 8000d4c: d10d bne.n 8000d6a { __HAL_RCC_PWR_CLK_ENABLE(); 8000d4e: 4b88 ldr r3, [pc, #544] ; (8000f70 ) 8000d50: 69db ldr r3, [r3, #28] 8000d52: 4a87 ldr r2, [pc, #540] ; (8000f70 ) 8000d54: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 8000d58: 61d3 str r3, [r2, #28] 8000d5a: 4b85 ldr r3, [pc, #532] ; (8000f70 ) 8000d5c: 69db ldr r3, [r3, #28] 8000d5e: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 8000d62: 60bb str r3, [r7, #8] 8000d64: 68bb ldr r3, [r7, #8] pwrclkchanged = SET; 8000d66: 2301 movs r3, #1 8000d68: 75fb strb r3, [r7, #23] } if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8000d6a: 4b82 ldr r3, [pc, #520] ; (8000f74 ) 8000d6c: 681b ldr r3, [r3, #0] 8000d6e: f403 7380 and.w r3, r3, #256 ; 0x100 8000d72: 2b00 cmp r3, #0 8000d74: d118 bne.n 8000da8 { /* Enable write access to Backup domain */ SET_BIT(PWR->CR, PWR_CR_DBP); 8000d76: 4b7f ldr r3, [pc, #508] ; (8000f74 ) 8000d78: 681b ldr r3, [r3, #0] 8000d7a: 4a7e ldr r2, [pc, #504] ; (8000f74 ) 8000d7c: f443 7380 orr.w r3, r3, #256 ; 0x100 8000d80: 6013 str r3, [r2, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 8000d82: f7ff fbfd bl 8000580 8000d86: 6138 str r0, [r7, #16] while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8000d88: e008 b.n 8000d9c { if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 8000d8a: f7ff fbf9 bl 8000580 8000d8e: 4602 mov r2, r0 8000d90: 693b ldr r3, [r7, #16] 8000d92: 1ad3 subs r3, r2, r3 8000d94: 2b64 cmp r3, #100 ; 0x64 8000d96: d901 bls.n 8000d9c { return HAL_TIMEOUT; 8000d98: 2303 movs r3, #3 8000d9a: e103 b.n 8000fa4 while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8000d9c: 4b75 ldr r3, [pc, #468] ; (8000f74 ) 8000d9e: 681b ldr r3, [r3, #0] 8000da0: f403 7380 and.w r3, r3, #256 ; 0x100 8000da4: 2b00 cmp r3, #0 8000da6: d0f0 beq.n 8000d8a } } } /* Set the new LSE configuration -----------------------------------------*/ __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); 8000da8: 687b ldr r3, [r7, #4] 8000daa: 68db ldr r3, [r3, #12] 8000dac: 2b01 cmp r3, #1 8000dae: d106 bne.n 8000dbe 8000db0: 4b6f ldr r3, [pc, #444] ; (8000f70 ) 8000db2: 6a1b ldr r3, [r3, #32] 8000db4: 4a6e ldr r2, [pc, #440] ; (8000f70 ) 8000db6: f043 0301 orr.w r3, r3, #1 8000dba: 6213 str r3, [r2, #32] 8000dbc: e02d b.n 8000e1a 8000dbe: 687b ldr r3, [r7, #4] 8000dc0: 68db ldr r3, [r3, #12] 8000dc2: 2b00 cmp r3, #0 8000dc4: d10c bne.n 8000de0 8000dc6: 4b6a ldr r3, [pc, #424] ; (8000f70 ) 8000dc8: 6a1b ldr r3, [r3, #32] 8000dca: 4a69 ldr r2, [pc, #420] ; (8000f70 ) 8000dcc: f023 0301 bic.w r3, r3, #1 8000dd0: 6213 str r3, [r2, #32] 8000dd2: 4b67 ldr r3, [pc, #412] ; (8000f70 ) 8000dd4: 6a1b ldr r3, [r3, #32] 8000dd6: 4a66 ldr r2, [pc, #408] ; (8000f70 ) 8000dd8: f023 0304 bic.w r3, r3, #4 8000ddc: 6213 str r3, [r2, #32] 8000dde: e01c b.n 8000e1a 8000de0: 687b ldr r3, [r7, #4] 8000de2: 68db ldr r3, [r3, #12] 8000de4: 2b05 cmp r3, #5 8000de6: d10c bne.n 8000e02 8000de8: 4b61 ldr r3, [pc, #388] ; (8000f70 ) 8000dea: 6a1b ldr r3, [r3, #32] 8000dec: 4a60 ldr r2, [pc, #384] ; (8000f70 ) 8000dee: f043 0304 orr.w r3, r3, #4 8000df2: 6213 str r3, [r2, #32] 8000df4: 4b5e ldr r3, [pc, #376] ; (8000f70 ) 8000df6: 6a1b ldr r3, [r3, #32] 8000df8: 4a5d ldr r2, [pc, #372] ; (8000f70 ) 8000dfa: f043 0301 orr.w r3, r3, #1 8000dfe: 6213 str r3, [r2, #32] 8000e00: e00b b.n 8000e1a 8000e02: 4b5b ldr r3, [pc, #364] ; (8000f70 ) 8000e04: 6a1b ldr r3, [r3, #32] 8000e06: 4a5a ldr r2, [pc, #360] ; (8000f70 ) 8000e08: f023 0301 bic.w r3, r3, #1 8000e0c: 6213 str r3, [r2, #32] 8000e0e: 4b58 ldr r3, [pc, #352] ; (8000f70 ) 8000e10: 6a1b ldr r3, [r3, #32] 8000e12: 4a57 ldr r2, [pc, #348] ; (8000f70 ) 8000e14: f023 0304 bic.w r3, r3, #4 8000e18: 6213 str r3, [r2, #32] /* Check the LSE State */ if (RCC_OscInitStruct->LSEState != RCC_LSE_OFF) 8000e1a: 687b ldr r3, [r7, #4] 8000e1c: 68db ldr r3, [r3, #12] 8000e1e: 2b00 cmp r3, #0 8000e20: d015 beq.n 8000e4e { /* Get Start Tick */ tickstart = HAL_GetTick(); 8000e22: f7ff fbad bl 8000580 8000e26: 6138 str r0, [r7, #16] /* Wait till LSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 8000e28: e00a b.n 8000e40 { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 8000e2a: f7ff fba9 bl 8000580 8000e2e: 4602 mov r2, r0 8000e30: 693b ldr r3, [r7, #16] 8000e32: 1ad3 subs r3, r2, r3 8000e34: f241 3288 movw r2, #5000 ; 0x1388 8000e38: 4293 cmp r3, r2 8000e3a: d901 bls.n 8000e40 { return HAL_TIMEOUT; 8000e3c: 2303 movs r3, #3 8000e3e: e0b1 b.n 8000fa4 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 8000e40: 4b4b ldr r3, [pc, #300] ; (8000f70 ) 8000e42: 6a1b ldr r3, [r3, #32] 8000e44: f003 0302 and.w r3, r3, #2 8000e48: 2b00 cmp r3, #0 8000e4a: d0ee beq.n 8000e2a 8000e4c: e014 b.n 8000e78 } } else { /* Get Start Tick */ tickstart = HAL_GetTick(); 8000e4e: f7ff fb97 bl 8000580 8000e52: 6138 str r0, [r7, #16] /* Wait till LSE is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) 8000e54: e00a b.n 8000e6c { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 8000e56: f7ff fb93 bl 8000580 8000e5a: 4602 mov r2, r0 8000e5c: 693b ldr r3, [r7, #16] 8000e5e: 1ad3 subs r3, r2, r3 8000e60: f241 3288 movw r2, #5000 ; 0x1388 8000e64: 4293 cmp r3, r2 8000e66: d901 bls.n 8000e6c { return HAL_TIMEOUT; 8000e68: 2303 movs r3, #3 8000e6a: e09b b.n 8000fa4 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) 8000e6c: 4b40 ldr r3, [pc, #256] ; (8000f70 ) 8000e6e: 6a1b ldr r3, [r3, #32] 8000e70: f003 0302 and.w r3, r3, #2 8000e74: 2b00 cmp r3, #0 8000e76: d1ee bne.n 8000e56 } } } /* Require to disable power clock if necessary */ if (pwrclkchanged == SET) 8000e78: 7dfb ldrb r3, [r7, #23] 8000e7a: 2b01 cmp r3, #1 8000e7c: d105 bne.n 8000e8a { __HAL_RCC_PWR_CLK_DISABLE(); 8000e7e: 4b3c ldr r3, [pc, #240] ; (8000f70 ) 8000e80: 69db ldr r3, [r3, #28] 8000e82: 4a3b ldr r2, [pc, #236] ; (8000f70 ) 8000e84: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000 8000e88: 61d3 str r3, [r2, #28] #endif /* RCC_CR_PLL2ON */ /*-------------------------------- PLL Configuration -----------------------*/ /* Check the parameters */ assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) 8000e8a: 687b ldr r3, [r7, #4] 8000e8c: 69db ldr r3, [r3, #28] 8000e8e: 2b00 cmp r3, #0 8000e90: f000 8087 beq.w 8000fa2 { /* Check if the PLL is used as system clock or not */ if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) 8000e94: 4b36 ldr r3, [pc, #216] ; (8000f70 ) 8000e96: 685b ldr r3, [r3, #4] 8000e98: f003 030c and.w r3, r3, #12 8000e9c: 2b08 cmp r3, #8 8000e9e: d061 beq.n 8000f64 { if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) 8000ea0: 687b ldr r3, [r7, #4] 8000ea2: 69db ldr r3, [r3, #28] 8000ea4: 2b02 cmp r3, #2 8000ea6: d146 bne.n 8000f36 /* Check the parameters */ assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource)); assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL)); /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 8000ea8: 4b33 ldr r3, [pc, #204] ; (8000f78 ) 8000eaa: 2200 movs r2, #0 8000eac: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8000eae: f7ff fb67 bl 8000580 8000eb2: 6138 str r0, [r7, #16] /* Wait till PLL is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 8000eb4: e008 b.n 8000ec8 { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 8000eb6: f7ff fb63 bl 8000580 8000eba: 4602 mov r2, r0 8000ebc: 693b ldr r3, [r7, #16] 8000ebe: 1ad3 subs r3, r2, r3 8000ec0: 2b02 cmp r3, #2 8000ec2: d901 bls.n 8000ec8 { return HAL_TIMEOUT; 8000ec4: 2303 movs r3, #3 8000ec6: e06d b.n 8000fa4 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 8000ec8: 4b29 ldr r3, [pc, #164] ; (8000f70 ) 8000eca: 681b ldr r3, [r3, #0] 8000ecc: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 8000ed0: 2b00 cmp r3, #0 8000ed2: d1f0 bne.n 8000eb6 } } /* Configure the HSE prediv factor --------------------------------*/ /* It can be written only when the PLL is disabled. Not used in PLL source is different than HSE */ if (RCC_OscInitStruct->PLL.PLLSource == RCC_PLLSOURCE_HSE) 8000ed4: 687b ldr r3, [r7, #4] 8000ed6: 6a1b ldr r3, [r3, #32] 8000ed8: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 8000edc: d108 bne.n 8000ef0 /* Set PREDIV1 source */ SET_BIT(RCC->CFGR2, RCC_OscInitStruct->Prediv1Source); #endif /* RCC_CFGR2_PREDIV1SRC */ /* Set PREDIV1 Value */ __HAL_RCC_HSE_PREDIV_CONFIG(RCC_OscInitStruct->HSEPredivValue); 8000ede: 4b24 ldr r3, [pc, #144] ; (8000f70 ) 8000ee0: 685b ldr r3, [r3, #4] 8000ee2: f423 3200 bic.w r2, r3, #131072 ; 0x20000 8000ee6: 687b ldr r3, [r7, #4] 8000ee8: 689b ldr r3, [r3, #8] 8000eea: 4921 ldr r1, [pc, #132] ; (8000f70 ) 8000eec: 4313 orrs r3, r2 8000eee: 604b str r3, [r1, #4] } /* Configure the main PLL clock source and multiplication factors. */ __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, 8000ef0: 4b1f ldr r3, [pc, #124] ; (8000f70 ) 8000ef2: 685b ldr r3, [r3, #4] 8000ef4: f423 1274 bic.w r2, r3, #3997696 ; 0x3d0000 8000ef8: 687b ldr r3, [r7, #4] 8000efa: 6a19 ldr r1, [r3, #32] 8000efc: 687b ldr r3, [r7, #4] 8000efe: 6a5b ldr r3, [r3, #36] ; 0x24 8000f00: 430b orrs r3, r1 8000f02: 491b ldr r1, [pc, #108] ; (8000f70 ) 8000f04: 4313 orrs r3, r2 8000f06: 604b str r3, [r1, #4] RCC_OscInitStruct->PLL.PLLMUL); /* Enable the main PLL. */ __HAL_RCC_PLL_ENABLE(); 8000f08: 4b1b ldr r3, [pc, #108] ; (8000f78 ) 8000f0a: 2201 movs r2, #1 8000f0c: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8000f0e: f7ff fb37 bl 8000580 8000f12: 6138 str r0, [r7, #16] /* Wait till PLL is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 8000f14: e008 b.n 8000f28