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6070 lines
232 KiB
Plaintext
6070 lines
232 KiB
Plaintext
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Timer_RotaryEncoder.elf: file format elf32-littlearm
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Sections:
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Idx Name Size VMA LMA File off Algn
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0 .isr_vector 0000010c 08000000 08000000 00010000 2**0
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CONTENTS, ALLOC, LOAD, READONLY, DATA
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1 .text 00002450 0800010c 0800010c 0001010c 2**2
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CONTENTS, ALLOC, LOAD, READONLY, CODE
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2 .rodata 00000064 0800255c 0800255c 0001255c 2**2
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CONTENTS, ALLOC, LOAD, READONLY, DATA
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3 .ARM.extab 00000000 080025c0 080025c0 00020070 2**0
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CONTENTS
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4 .ARM 00000000 080025c0 080025c0 00020070 2**0
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CONTENTS
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5 .preinit_array 00000000 080025c0 080025c0 00020070 2**0
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CONTENTS, ALLOC, LOAD, DATA
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6 .init_array 00000004 080025c0 080025c0 000125c0 2**2
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CONTENTS, ALLOC, LOAD, DATA
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7 .fini_array 00000004 080025c4 080025c4 000125c4 2**2
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CONTENTS, ALLOC, LOAD, DATA
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8 .data 00000070 20000000 080025c8 00020000 2**2
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CONTENTS, ALLOC, LOAD, DATA
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9 .bss 000000c0 20000070 08002638 00020070 2**2
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ALLOC
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10 ._user_heap_stack 00000600 20000130 08002638 00020130 2**0
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ALLOC
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11 .ARM.attributes 00000029 00000000 00000000 00020070 2**0
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CONTENTS, READONLY
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12 .debug_info 00009b6b 00000000 00000000 00020099 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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13 .debug_abbrev 00001a97 00000000 00000000 00029c04 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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14 .debug_aranges 00000ba0 00000000 00000000 0002b6a0 2**3
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CONTENTS, READONLY, DEBUGGING, OCTETS
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15 .debug_ranges 00000ad8 00000000 00000000 0002c240 2**3
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CONTENTS, READONLY, DEBUGGING, OCTETS
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16 .debug_macro 00017ed3 00000000 00000000 0002cd18 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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17 .debug_line 0000c819 00000000 00000000 00044beb 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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18 .debug_str 0008a460 00000000 00000000 00051404 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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19 .comment 00000050 00000000 00000000 000db864 2**0
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CONTENTS, READONLY
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20 .debug_frame 000033ac 00000000 00000000 000db8b4 2**2
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CONTENTS, READONLY, DEBUGGING, OCTETS
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Disassembly of section .text:
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0800010c <__do_global_dtors_aux>:
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800010c: b510 push {r4, lr}
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800010e: 4c05 ldr r4, [pc, #20] ; (8000124 <__do_global_dtors_aux+0x18>)
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8000110: 7823 ldrb r3, [r4, #0]
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8000112: b933 cbnz r3, 8000122 <__do_global_dtors_aux+0x16>
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8000114: 4b04 ldr r3, [pc, #16] ; (8000128 <__do_global_dtors_aux+0x1c>)
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8000116: b113 cbz r3, 800011e <__do_global_dtors_aux+0x12>
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8000118: 4804 ldr r0, [pc, #16] ; (800012c <__do_global_dtors_aux+0x20>)
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800011a: f3af 8000 nop.w
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800011e: 2301 movs r3, #1
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8000120: 7023 strb r3, [r4, #0]
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8000122: bd10 pop {r4, pc}
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8000124: 20000070 .word 0x20000070
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8000128: 00000000 .word 0x00000000
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800012c: 08002544 .word 0x08002544
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08000130 <frame_dummy>:
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8000130: b508 push {r3, lr}
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8000132: 4b03 ldr r3, [pc, #12] ; (8000140 <frame_dummy+0x10>)
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8000134: b11b cbz r3, 800013e <frame_dummy+0xe>
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8000136: 4903 ldr r1, [pc, #12] ; (8000144 <frame_dummy+0x14>)
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8000138: 4803 ldr r0, [pc, #12] ; (8000148 <frame_dummy+0x18>)
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800013a: f3af 8000 nop.w
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800013e: bd08 pop {r3, pc}
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8000140: 00000000 .word 0x00000000
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8000144: 20000074 .word 0x20000074
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8000148: 08002544 .word 0x08002544
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0800014c <strlen>:
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800014c: 4603 mov r3, r0
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800014e: f813 2b01 ldrb.w r2, [r3], #1
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8000152: 2a00 cmp r2, #0
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8000154: d1fb bne.n 800014e <strlen+0x2>
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8000156: 1a18 subs r0, r3, r0
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8000158: 3801 subs r0, #1
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800015a: 4770 bx lr
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0800015c <MX_GPIO_Init>:
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* Output
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* EVENT_OUT
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* EXTI
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*/
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void MX_GPIO_Init(void)
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{
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800015c: b480 push {r7}
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800015e: b083 sub sp, #12
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8000160: af00 add r7, sp, #0
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/* GPIO Ports Clock Enable */
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__HAL_RCC_GPIOD_CLK_ENABLE();
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8000162: 4b0e ldr r3, [pc, #56] ; (800019c <MX_GPIO_Init+0x40>)
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8000164: 699b ldr r3, [r3, #24]
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8000166: 4a0d ldr r2, [pc, #52] ; (800019c <MX_GPIO_Init+0x40>)
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8000168: f043 0320 orr.w r3, r3, #32
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800016c: 6193 str r3, [r2, #24]
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800016e: 4b0b ldr r3, [pc, #44] ; (800019c <MX_GPIO_Init+0x40>)
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8000170: 699b ldr r3, [r3, #24]
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8000172: f003 0320 and.w r3, r3, #32
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8000176: 607b str r3, [r7, #4]
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8000178: 687b ldr r3, [r7, #4]
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__HAL_RCC_GPIOA_CLK_ENABLE();
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800017a: 4b08 ldr r3, [pc, #32] ; (800019c <MX_GPIO_Init+0x40>)
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800017c: 699b ldr r3, [r3, #24]
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800017e: 4a07 ldr r2, [pc, #28] ; (800019c <MX_GPIO_Init+0x40>)
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8000180: f043 0304 orr.w r3, r3, #4
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8000184: 6193 str r3, [r2, #24]
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8000186: 4b05 ldr r3, [pc, #20] ; (800019c <MX_GPIO_Init+0x40>)
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8000188: 699b ldr r3, [r3, #24]
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800018a: f003 0304 and.w r3, r3, #4
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800018e: 603b str r3, [r7, #0]
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8000190: 683b ldr r3, [r7, #0]
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}
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8000192: bf00 nop
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8000194: 370c adds r7, #12
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8000196: 46bd mov sp, r7
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8000198: bc80 pop {r7}
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800019a: 4770 bx lr
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800019c: 40021000 .word 0x40021000
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080001a0 <main>:
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/**
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* @brief The application entry point.
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* @retval int
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*/
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int main(void) {
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80001a0: b580 push {r7, lr}
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80001a2: b08e sub sp, #56 ; 0x38
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80001a4: af00 add r7, sp, #0
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/* USER CODE END 1 */
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/* MCU Configuration--------------------------------------------------------*/
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/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
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HAL_Init();
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80001a6: f000 fa4d bl 8000644 <HAL_Init>
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/* USER CODE BEGIN Init */
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/* USER CODE END Init */
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/* Configure the system clock */
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SystemClock_Config();
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80001aa: f000 f839 bl 8000220 <SystemClock_Config>
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/* USER CODE BEGIN SysInit */
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/* USER CODE END SysInit */
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/* Initialize all configured peripherals */
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MX_GPIO_Init();
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80001ae: f7ff ffd5 bl 800015c <MX_GPIO_Init>
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MX_TIM1_Init();
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80001b2: f000 f915 bl 80003e0 <MX_TIM1_Init>
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MX_USART2_UART_Init();
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80001b6: f000 f9ab bl 8000510 <MX_USART2_UART_Init>
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/* USER CODE BEGIN 2 */
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HAL_TIM_Encoder_Start(&htim1, TIM_CHANNEL_ALL);
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80001ba: 213c movs r1, #60 ; 0x3c
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80001bc: 4815 ldr r0, [pc, #84] ; (8000214 <main+0x74>)
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80001be: f001 f9eb bl 8001598 <HAL_TIM_Encoder_Start>
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/* USER CODE END 2 */
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/* Infinite loop */
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/* USER CODE BEGIN WHILE */
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char send_buf[50] = { 0 };
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80001c2: 2300 movs r3, #0
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80001c4: 607b str r3, [r7, #4]
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80001c6: f107 0308 add.w r3, r7, #8
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80001ca: 222e movs r2, #46 ; 0x2e
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80001cc: 2100 movs r1, #0
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80001ce: 4618 mov r0, r3
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80001d0: f001 fd36 bl 8001c40 <memset>
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uint16_t cnt_encoder = 0;
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80001d4: 2300 movs r3, #0
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80001d6: 86fb strh r3, [r7, #54] ; 0x36
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//We preset TIM_COUNTER, to prevent it from reaching 65535
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htim1.Instance->CNT = 1000;
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80001d8: 4b0e ldr r3, [pc, #56] ; (8000214 <main+0x74>)
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80001da: 681b ldr r3, [r3, #0]
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80001dc: f44f 727a mov.w r2, #1000 ; 0x3e8
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80001e0: 625a str r2, [r3, #36] ; 0x24
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while (1) {
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cnt_encoder = __HAL_TIM_GET_COUNTER(&htim1);
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80001e2: 4b0c ldr r3, [pc, #48] ; (8000214 <main+0x74>)
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80001e4: 681b ldr r3, [r3, #0]
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80001e6: 6a5b ldr r3, [r3, #36] ; 0x24
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80001e8: 86fb strh r3, [r7, #54] ; 0x36
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sprintf(send_buf, "%d\r\n", cnt_encoder);
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80001ea: 8efa ldrh r2, [r7, #54] ; 0x36
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80001ec: 1d3b adds r3, r7, #4
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80001ee: 490a ldr r1, [pc, #40] ; (8000218 <main+0x78>)
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80001f0: 4618 mov r0, r3
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80001f2: f001 fd2d bl 8001c50 <siprintf>
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HAL_UART_Transmit(&huart2, (uint8_t*) send_buf, strlen(send_buf), 10);
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80001f6: 1d3b adds r3, r7, #4
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80001f8: 4618 mov r0, r3
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80001fa: f7ff ffa7 bl 800014c <strlen>
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80001fe: 4603 mov r3, r0
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8000200: b29a uxth r2, r3
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8000202: 1d39 adds r1, r7, #4
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8000204: 230a movs r3, #10
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8000206: 4805 ldr r0, [pc, #20] ; (800021c <main+0x7c>)
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8000208: f001 fb85 bl 8001916 <HAL_UART_Transmit>
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HAL_Delay(50);
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800020c: 2032 movs r0, #50 ; 0x32
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800020e: f000 fa7b bl 8000708 <HAL_Delay>
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cnt_encoder = __HAL_TIM_GET_COUNTER(&htim1);
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8000212: e7e6 b.n 80001e2 <main+0x42>
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8000214: 20000090 .word 0x20000090
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8000218: 0800255c .word 0x0800255c
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800021c: 200000d8 .word 0x200000d8
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08000220 <SystemClock_Config>:
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/**
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* @brief System Clock Configuration
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* @retval None
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*/
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void SystemClock_Config(void) {
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8000220: b580 push {r7, lr}
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8000222: b090 sub sp, #64 ; 0x40
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8000224: af00 add r7, sp, #0
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RCC_OscInitTypeDef RCC_OscInitStruct = { 0 };
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8000226: f107 0318 add.w r3, r7, #24
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800022a: 2228 movs r2, #40 ; 0x28
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800022c: 2100 movs r1, #0
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800022e: 4618 mov r0, r3
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8000230: f001 fd06 bl 8001c40 <memset>
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RCC_ClkInitTypeDef RCC_ClkInitStruct = { 0 };
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8000234: 1d3b adds r3, r7, #4
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8000236: 2200 movs r2, #0
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8000238: 601a str r2, [r3, #0]
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800023a: 605a str r2, [r3, #4]
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800023c: 609a str r2, [r3, #8]
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800023e: 60da str r2, [r3, #12]
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8000240: 611a str r2, [r3, #16]
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/** Initializes the RCC Oscillators according to the specified parameters
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* in the RCC_OscInitTypeDef structure.
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*/
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RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
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8000242: 2301 movs r3, #1
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8000244: 61bb str r3, [r7, #24]
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RCC_OscInitStruct.HSEState = RCC_HSE_ON;
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8000246: f44f 3380 mov.w r3, #65536 ; 0x10000
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800024a: 61fb str r3, [r7, #28]
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RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV1;
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800024c: 2300 movs r3, #0
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800024e: 623b str r3, [r7, #32]
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RCC_OscInitStruct.HSIState = RCC_HSI_ON;
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8000250: 2301 movs r3, #1
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8000252: 62bb str r3, [r7, #40] ; 0x28
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RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
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8000254: 2302 movs r3, #2
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8000256: 637b str r3, [r7, #52] ; 0x34
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RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
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8000258: f44f 3380 mov.w r3, #65536 ; 0x10000
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800025c: 63bb str r3, [r7, #56] ; 0x38
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RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9;
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800025e: f44f 13e0 mov.w r3, #1835008 ; 0x1c0000
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8000262: 63fb str r3, [r7, #60] ; 0x3c
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if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
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8000264: f107 0318 add.w r3, r7, #24
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8000268: 4618 mov r0, r3
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800026a: f000 fcd9 bl 8000c20 <HAL_RCC_OscConfig>
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800026e: 4603 mov r3, r0
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8000270: 2b00 cmp r3, #0
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8000272: d001 beq.n 8000278 <SystemClock_Config+0x58>
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Error_Handler();
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8000274: f000 f819 bl 80002aa <Error_Handler>
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}
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/** Initializes the CPU, AHB and APB buses clocks
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*/
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RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
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8000278: 230f movs r3, #15
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800027a: 607b str r3, [r7, #4]
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| RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
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RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
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800027c: 2302 movs r3, #2
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800027e: 60bb str r3, [r7, #8]
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RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
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8000280: 2300 movs r3, #0
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8000282: 60fb str r3, [r7, #12]
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RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
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8000284: f44f 6380 mov.w r3, #1024 ; 0x400
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8000288: 613b str r3, [r7, #16]
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RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
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800028a: 2300 movs r3, #0
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800028c: 617b str r3, [r7, #20]
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if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) {
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800028e: 1d3b adds r3, r7, #4
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8000290: 2102 movs r1, #2
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8000292: 4618 mov r0, r3
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8000294: f000 ff46 bl 8001124 <HAL_RCC_ClockConfig>
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8000298: 4603 mov r3, r0
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800029a: 2b00 cmp r3, #0
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800029c: d001 beq.n 80002a2 <SystemClock_Config+0x82>
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Error_Handler();
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800029e: f000 f804 bl 80002aa <Error_Handler>
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}
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}
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80002a2: bf00 nop
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80002a4: 3740 adds r7, #64 ; 0x40
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|
80002a6: 46bd mov sp, r7
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80002a8: bd80 pop {r7, pc}
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|
080002aa <Error_Handler>:
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|
|
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/**
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|
* @brief This function is executed in case of error occurrence.
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* @retval None
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*/
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void Error_Handler(void) {
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80002aa: b480 push {r7}
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|
80002ac: af00 add r7, sp, #0
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\details Disables IRQ interrupts by setting the I-bit in the CPSR.
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Can only be executed in Privileged modes.
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|
*/
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__STATIC_FORCEINLINE void __disable_irq(void)
|
|
{
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|
__ASM volatile ("cpsid i" : : : "memory");
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80002ae: b672 cpsid i
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}
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80002b0: bf00 nop
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|
/* USER CODE BEGIN Error_Handler_Debug */
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|
/* User can add his own implementation to report the HAL error return state */
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|
__disable_irq();
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while (1) {
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|
80002b2: e7fe b.n 80002b2 <Error_Handler+0x8>
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|
|
080002b4 <HAL_MspInit>:
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|
/* USER CODE END 0 */
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|
/**
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|
* Initializes the Global MSP.
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|
*/
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|
void HAL_MspInit(void)
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|
{
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|
80002b4: b480 push {r7}
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|
80002b6: b085 sub sp, #20
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|
80002b8: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN MspInit 0 */
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|
|
/* USER CODE END MspInit 0 */
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__HAL_RCC_AFIO_CLK_ENABLE();
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|
80002ba: 4b15 ldr r3, [pc, #84] ; (8000310 <HAL_MspInit+0x5c>)
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|
80002bc: 699b ldr r3, [r3, #24]
|
|
80002be: 4a14 ldr r2, [pc, #80] ; (8000310 <HAL_MspInit+0x5c>)
|
|
80002c0: f043 0301 orr.w r3, r3, #1
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|
80002c4: 6193 str r3, [r2, #24]
|
|
80002c6: 4b12 ldr r3, [pc, #72] ; (8000310 <HAL_MspInit+0x5c>)
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|
80002c8: 699b ldr r3, [r3, #24]
|
|
80002ca: f003 0301 and.w r3, r3, #1
|
|
80002ce: 60bb str r3, [r7, #8]
|
|
80002d0: 68bb ldr r3, [r7, #8]
|
|
__HAL_RCC_PWR_CLK_ENABLE();
|
|
80002d2: 4b0f ldr r3, [pc, #60] ; (8000310 <HAL_MspInit+0x5c>)
|
|
80002d4: 69db ldr r3, [r3, #28]
|
|
80002d6: 4a0e ldr r2, [pc, #56] ; (8000310 <HAL_MspInit+0x5c>)
|
|
80002d8: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
|
|
80002dc: 61d3 str r3, [r2, #28]
|
|
80002de: 4b0c ldr r3, [pc, #48] ; (8000310 <HAL_MspInit+0x5c>)
|
|
80002e0: 69db ldr r3, [r3, #28]
|
|
80002e2: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
|
|
80002e6: 607b str r3, [r7, #4]
|
|
80002e8: 687b ldr r3, [r7, #4]
|
|
|
|
/* System interrupt init*/
|
|
|
|
/** NOJTAG: JTAG-DP Disabled and SW-DP Enabled
|
|
*/
|
|
__HAL_AFIO_REMAP_SWJ_NOJTAG();
|
|
80002ea: 4b0a ldr r3, [pc, #40] ; (8000314 <HAL_MspInit+0x60>)
|
|
80002ec: 685b ldr r3, [r3, #4]
|
|
80002ee: 60fb str r3, [r7, #12]
|
|
80002f0: 68fb ldr r3, [r7, #12]
|
|
80002f2: f023 63e0 bic.w r3, r3, #117440512 ; 0x7000000
|
|
80002f6: 60fb str r3, [r7, #12]
|
|
80002f8: 68fb ldr r3, [r7, #12]
|
|
80002fa: f043 7300 orr.w r3, r3, #33554432 ; 0x2000000
|
|
80002fe: 60fb str r3, [r7, #12]
|
|
8000300: 4a04 ldr r2, [pc, #16] ; (8000314 <HAL_MspInit+0x60>)
|
|
8000302: 68fb ldr r3, [r7, #12]
|
|
8000304: 6053 str r3, [r2, #4]
|
|
|
|
/* USER CODE BEGIN MspInit 1 */
|
|
|
|
/* USER CODE END MspInit 1 */
|
|
}
|
|
8000306: bf00 nop
|
|
8000308: 3714 adds r7, #20
|
|
800030a: 46bd mov sp, r7
|
|
800030c: bc80 pop {r7}
|
|
800030e: 4770 bx lr
|
|
8000310: 40021000 .word 0x40021000
|
|
8000314: 40010000 .word 0x40010000
|
|
|
|
08000318 <NMI_Handler>:
|
|
/******************************************************************************/
|
|
/**
|
|
* @brief This function handles Non maskable interrupt.
|
|
*/
|
|
void NMI_Handler(void)
|
|
{
|
|
8000318: b480 push {r7}
|
|
800031a: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
|
|
|
|
/* USER CODE END NonMaskableInt_IRQn 0 */
|
|
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
|
|
while (1)
|
|
800031c: e7fe b.n 800031c <NMI_Handler+0x4>
|
|
|
|
0800031e <HardFault_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Hard fault interrupt.
|
|
*/
|
|
void HardFault_Handler(void)
|
|
{
|
|
800031e: b480 push {r7}
|
|
8000320: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN HardFault_IRQn 0 */
|
|
|
|
/* USER CODE END HardFault_IRQn 0 */
|
|
while (1)
|
|
8000322: e7fe b.n 8000322 <HardFault_Handler+0x4>
|
|
|
|
08000324 <MemManage_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Memory management fault.
|
|
*/
|
|
void MemManage_Handler(void)
|
|
{
|
|
8000324: b480 push {r7}
|
|
8000326: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN MemoryManagement_IRQn 0 */
|
|
|
|
/* USER CODE END MemoryManagement_IRQn 0 */
|
|
while (1)
|
|
8000328: e7fe b.n 8000328 <MemManage_Handler+0x4>
|
|
|
|
0800032a <BusFault_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Prefetch fault, memory access fault.
|
|
*/
|
|
void BusFault_Handler(void)
|
|
{
|
|
800032a: b480 push {r7}
|
|
800032c: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN BusFault_IRQn 0 */
|
|
|
|
/* USER CODE END BusFault_IRQn 0 */
|
|
while (1)
|
|
800032e: e7fe b.n 800032e <BusFault_Handler+0x4>
|
|
|
|
08000330 <UsageFault_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Undefined instruction or illegal state.
|
|
*/
|
|
void UsageFault_Handler(void)
|
|
{
|
|
8000330: b480 push {r7}
|
|
8000332: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN UsageFault_IRQn 0 */
|
|
|
|
/* USER CODE END UsageFault_IRQn 0 */
|
|
while (1)
|
|
8000334: e7fe b.n 8000334 <UsageFault_Handler+0x4>
|
|
|
|
08000336 <SVC_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles System service call via SWI instruction.
|
|
*/
|
|
void SVC_Handler(void)
|
|
{
|
|
8000336: b480 push {r7}
|
|
8000338: af00 add r7, sp, #0
|
|
|
|
/* USER CODE END SVCall_IRQn 0 */
|
|
/* USER CODE BEGIN SVCall_IRQn 1 */
|
|
|
|
/* USER CODE END SVCall_IRQn 1 */
|
|
}
|
|
800033a: bf00 nop
|
|
800033c: 46bd mov sp, r7
|
|
800033e: bc80 pop {r7}
|
|
8000340: 4770 bx lr
|
|
|
|
08000342 <DebugMon_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Debug monitor.
|
|
*/
|
|
void DebugMon_Handler(void)
|
|
{
|
|
8000342: b480 push {r7}
|
|
8000344: af00 add r7, sp, #0
|
|
|
|
/* USER CODE END DebugMonitor_IRQn 0 */
|
|
/* USER CODE BEGIN DebugMonitor_IRQn 1 */
|
|
|
|
/* USER CODE END DebugMonitor_IRQn 1 */
|
|
}
|
|
8000346: bf00 nop
|
|
8000348: 46bd mov sp, r7
|
|
800034a: bc80 pop {r7}
|
|
800034c: 4770 bx lr
|
|
|
|
0800034e <PendSV_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Pendable request for system service.
|
|
*/
|
|
void PendSV_Handler(void)
|
|
{
|
|
800034e: b480 push {r7}
|
|
8000350: af00 add r7, sp, #0
|
|
|
|
/* USER CODE END PendSV_IRQn 0 */
|
|
/* USER CODE BEGIN PendSV_IRQn 1 */
|
|
|
|
/* USER CODE END PendSV_IRQn 1 */
|
|
}
|
|
8000352: bf00 nop
|
|
8000354: 46bd mov sp, r7
|
|
8000356: bc80 pop {r7}
|
|
8000358: 4770 bx lr
|
|
|
|
0800035a <SysTick_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles System tick timer.
|
|
*/
|
|
void SysTick_Handler(void)
|
|
{
|
|
800035a: b580 push {r7, lr}
|
|
800035c: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN SysTick_IRQn 0 */
|
|
|
|
/* USER CODE END SysTick_IRQn 0 */
|
|
HAL_IncTick();
|
|
800035e: f000 f9b7 bl 80006d0 <HAL_IncTick>
|
|
/* USER CODE BEGIN SysTick_IRQn 1 */
|
|
|
|
/* USER CODE END SysTick_IRQn 1 */
|
|
}
|
|
8000362: bf00 nop
|
|
8000364: bd80 pop {r7, pc}
|
|
...
|
|
|
|
08000368 <_sbrk>:
|
|
*
|
|
* @param incr Memory size
|
|
* @return Pointer to allocated memory
|
|
*/
|
|
void *_sbrk(ptrdiff_t incr)
|
|
{
|
|
8000368: b580 push {r7, lr}
|
|
800036a: b086 sub sp, #24
|
|
800036c: af00 add r7, sp, #0
|
|
800036e: 6078 str r0, [r7, #4]
|
|
extern uint8_t _end; /* Symbol defined in the linker script */
|
|
extern uint8_t _estack; /* Symbol defined in the linker script */
|
|
extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */
|
|
const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size;
|
|
8000370: 4a14 ldr r2, [pc, #80] ; (80003c4 <_sbrk+0x5c>)
|
|
8000372: 4b15 ldr r3, [pc, #84] ; (80003c8 <_sbrk+0x60>)
|
|
8000374: 1ad3 subs r3, r2, r3
|
|
8000376: 617b str r3, [r7, #20]
|
|
const uint8_t *max_heap = (uint8_t *)stack_limit;
|
|
8000378: 697b ldr r3, [r7, #20]
|
|
800037a: 613b str r3, [r7, #16]
|
|
uint8_t *prev_heap_end;
|
|
|
|
/* Initialize heap end at first call */
|
|
if (NULL == __sbrk_heap_end)
|
|
800037c: 4b13 ldr r3, [pc, #76] ; (80003cc <_sbrk+0x64>)
|
|
800037e: 681b ldr r3, [r3, #0]
|
|
8000380: 2b00 cmp r3, #0
|
|
8000382: d102 bne.n 800038a <_sbrk+0x22>
|
|
{
|
|
__sbrk_heap_end = &_end;
|
|
8000384: 4b11 ldr r3, [pc, #68] ; (80003cc <_sbrk+0x64>)
|
|
8000386: 4a12 ldr r2, [pc, #72] ; (80003d0 <_sbrk+0x68>)
|
|
8000388: 601a str r2, [r3, #0]
|
|
}
|
|
|
|
/* Protect heap from growing into the reserved MSP stack */
|
|
if (__sbrk_heap_end + incr > max_heap)
|
|
800038a: 4b10 ldr r3, [pc, #64] ; (80003cc <_sbrk+0x64>)
|
|
800038c: 681a ldr r2, [r3, #0]
|
|
800038e: 687b ldr r3, [r7, #4]
|
|
8000390: 4413 add r3, r2
|
|
8000392: 693a ldr r2, [r7, #16]
|
|
8000394: 429a cmp r2, r3
|
|
8000396: d207 bcs.n 80003a8 <_sbrk+0x40>
|
|
{
|
|
errno = ENOMEM;
|
|
8000398: f001 fc28 bl 8001bec <__errno>
|
|
800039c: 4603 mov r3, r0
|
|
800039e: 220c movs r2, #12
|
|
80003a0: 601a str r2, [r3, #0]
|
|
return (void *)-1;
|
|
80003a2: f04f 33ff mov.w r3, #4294967295
|
|
80003a6: e009 b.n 80003bc <_sbrk+0x54>
|
|
}
|
|
|
|
prev_heap_end = __sbrk_heap_end;
|
|
80003a8: 4b08 ldr r3, [pc, #32] ; (80003cc <_sbrk+0x64>)
|
|
80003aa: 681b ldr r3, [r3, #0]
|
|
80003ac: 60fb str r3, [r7, #12]
|
|
__sbrk_heap_end += incr;
|
|
80003ae: 4b07 ldr r3, [pc, #28] ; (80003cc <_sbrk+0x64>)
|
|
80003b0: 681a ldr r2, [r3, #0]
|
|
80003b2: 687b ldr r3, [r7, #4]
|
|
80003b4: 4413 add r3, r2
|
|
80003b6: 4a05 ldr r2, [pc, #20] ; (80003cc <_sbrk+0x64>)
|
|
80003b8: 6013 str r3, [r2, #0]
|
|
|
|
return (void *)prev_heap_end;
|
|
80003ba: 68fb ldr r3, [r7, #12]
|
|
}
|
|
80003bc: 4618 mov r0, r3
|
|
80003be: 3718 adds r7, #24
|
|
80003c0: 46bd mov sp, r7
|
|
80003c2: bd80 pop {r7, pc}
|
|
80003c4: 20005000 .word 0x20005000
|
|
80003c8: 00000400 .word 0x00000400
|
|
80003cc: 2000008c .word 0x2000008c
|
|
80003d0: 20000130 .word 0x20000130
|
|
|
|
080003d4 <SystemInit>:
|
|
* @note This function should be used only after reset.
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
void SystemInit (void)
|
|
{
|
|
80003d4: b480 push {r7}
|
|
80003d6: af00 add r7, sp, #0
|
|
|
|
/* Configure the Vector Table location -------------------------------------*/
|
|
#if defined(USER_VECT_TAB_ADDRESS)
|
|
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
|
|
#endif /* USER_VECT_TAB_ADDRESS */
|
|
}
|
|
80003d8: bf00 nop
|
|
80003da: 46bd mov sp, r7
|
|
80003dc: bc80 pop {r7}
|
|
80003de: 4770 bx lr
|
|
|
|
080003e0 <MX_TIM1_Init>:
|
|
|
|
TIM_HandleTypeDef htim1;
|
|
|
|
/* TIM1 init function */
|
|
void MX_TIM1_Init(void)
|
|
{
|
|
80003e0: b580 push {r7, lr}
|
|
80003e2: b08c sub sp, #48 ; 0x30
|
|
80003e4: af00 add r7, sp, #0
|
|
|
|
/* USER CODE BEGIN TIM1_Init 0 */
|
|
|
|
/* USER CODE END TIM1_Init 0 */
|
|
|
|
TIM_Encoder_InitTypeDef sConfig = {0};
|
|
80003e6: f107 030c add.w r3, r7, #12
|
|
80003ea: 2224 movs r2, #36 ; 0x24
|
|
80003ec: 2100 movs r1, #0
|
|
80003ee: 4618 mov r0, r3
|
|
80003f0: f001 fc26 bl 8001c40 <memset>
|
|
TIM_MasterConfigTypeDef sMasterConfig = {0};
|
|
80003f4: 1d3b adds r3, r7, #4
|
|
80003f6: 2200 movs r2, #0
|
|
80003f8: 601a str r2, [r3, #0]
|
|
80003fa: 605a str r2, [r3, #4]
|
|
|
|
/* USER CODE BEGIN TIM1_Init 1 */
|
|
|
|
/* USER CODE END TIM1_Init 1 */
|
|
htim1.Instance = TIM1;
|
|
80003fc: 4b22 ldr r3, [pc, #136] ; (8000488 <MX_TIM1_Init+0xa8>)
|
|
80003fe: 4a23 ldr r2, [pc, #140] ; (800048c <MX_TIM1_Init+0xac>)
|
|
8000400: 601a str r2, [r3, #0]
|
|
htim1.Init.Prescaler = 0;
|
|
8000402: 4b21 ldr r3, [pc, #132] ; (8000488 <MX_TIM1_Init+0xa8>)
|
|
8000404: 2200 movs r2, #0
|
|
8000406: 605a str r2, [r3, #4]
|
|
htim1.Init.CounterMode = TIM_COUNTERMODE_UP;
|
|
8000408: 4b1f ldr r3, [pc, #124] ; (8000488 <MX_TIM1_Init+0xa8>)
|
|
800040a: 2200 movs r2, #0
|
|
800040c: 609a str r2, [r3, #8]
|
|
htim1.Init.Period = 65535;
|
|
800040e: 4b1e ldr r3, [pc, #120] ; (8000488 <MX_TIM1_Init+0xa8>)
|
|
8000410: f64f 72ff movw r2, #65535 ; 0xffff
|
|
8000414: 60da str r2, [r3, #12]
|
|
htim1.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
|
|
8000416: 4b1c ldr r3, [pc, #112] ; (8000488 <MX_TIM1_Init+0xa8>)
|
|
8000418: 2200 movs r2, #0
|
|
800041a: 611a str r2, [r3, #16]
|
|
htim1.Init.RepetitionCounter = 0;
|
|
800041c: 4b1a ldr r3, [pc, #104] ; (8000488 <MX_TIM1_Init+0xa8>)
|
|
800041e: 2200 movs r2, #0
|
|
8000420: 615a str r2, [r3, #20]
|
|
htim1.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
|
|
8000422: 4b19 ldr r3, [pc, #100] ; (8000488 <MX_TIM1_Init+0xa8>)
|
|
8000424: 2200 movs r2, #0
|
|
8000426: 619a str r2, [r3, #24]
|
|
sConfig.EncoderMode = TIM_ENCODERMODE_TI1;
|
|
8000428: 2301 movs r3, #1
|
|
800042a: 60fb str r3, [r7, #12]
|
|
sConfig.IC1Polarity = TIM_ICPOLARITY_RISING;
|
|
800042c: 2300 movs r3, #0
|
|
800042e: 613b str r3, [r7, #16]
|
|
sConfig.IC1Selection = TIM_ICSELECTION_DIRECTTI;
|
|
8000430: 2301 movs r3, #1
|
|
8000432: 617b str r3, [r7, #20]
|
|
sConfig.IC1Prescaler = TIM_ICPSC_DIV1;
|
|
8000434: 2300 movs r3, #0
|
|
8000436: 61bb str r3, [r7, #24]
|
|
sConfig.IC1Filter = 10;
|
|
8000438: 230a movs r3, #10
|
|
800043a: 61fb str r3, [r7, #28]
|
|
sConfig.IC2Polarity = TIM_ICPOLARITY_RISING;
|
|
800043c: 2300 movs r3, #0
|
|
800043e: 623b str r3, [r7, #32]
|
|
sConfig.IC2Selection = TIM_ICSELECTION_DIRECTTI;
|
|
8000440: 2301 movs r3, #1
|
|
8000442: 627b str r3, [r7, #36] ; 0x24
|
|
sConfig.IC2Prescaler = TIM_ICPSC_DIV1;
|
|
8000444: 2300 movs r3, #0
|
|
8000446: 62bb str r3, [r7, #40] ; 0x28
|
|
sConfig.IC2Filter = 10;
|
|
8000448: 230a movs r3, #10
|
|
800044a: 62fb str r3, [r7, #44] ; 0x2c
|
|
if (HAL_TIM_Encoder_Init(&htim1, &sConfig) != HAL_OK)
|
|
800044c: f107 030c add.w r3, r7, #12
|
|
8000450: 4619 mov r1, r3
|
|
8000452: 480d ldr r0, [pc, #52] ; (8000488 <MX_TIM1_Init+0xa8>)
|
|
8000454: f000 fffe bl 8001454 <HAL_TIM_Encoder_Init>
|
|
8000458: 4603 mov r3, r0
|
|
800045a: 2b00 cmp r3, #0
|
|
800045c: d001 beq.n 8000462 <MX_TIM1_Init+0x82>
|
|
{
|
|
Error_Handler();
|
|
800045e: f7ff ff24 bl 80002aa <Error_Handler>
|
|
}
|
|
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
|
|
8000462: 2300 movs r3, #0
|
|
8000464: 607b str r3, [r7, #4]
|
|
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
|
|
8000466: 2300 movs r3, #0
|
|
8000468: 60bb str r3, [r7, #8]
|
|
if (HAL_TIMEx_MasterConfigSynchronization(&htim1, &sMasterConfig) != HAL_OK)
|
|
800046a: 1d3b adds r3, r7, #4
|
|
800046c: 4619 mov r1, r3
|
|
800046e: 4806 ldr r0, [pc, #24] ; (8000488 <MX_TIM1_Init+0xa8>)
|
|
8000470: f001 f9a6 bl 80017c0 <HAL_TIMEx_MasterConfigSynchronization>
|
|
8000474: 4603 mov r3, r0
|
|
8000476: 2b00 cmp r3, #0
|
|
8000478: d001 beq.n 800047e <MX_TIM1_Init+0x9e>
|
|
{
|
|
Error_Handler();
|
|
800047a: f7ff ff16 bl 80002aa <Error_Handler>
|
|
}
|
|
/* USER CODE BEGIN TIM1_Init 2 */
|
|
|
|
/* USER CODE END TIM1_Init 2 */
|
|
|
|
}
|
|
800047e: bf00 nop
|
|
8000480: 3730 adds r7, #48 ; 0x30
|
|
8000482: 46bd mov sp, r7
|
|
8000484: bd80 pop {r7, pc}
|
|
8000486: bf00 nop
|
|
8000488: 20000090 .word 0x20000090
|
|
800048c: 40012c00 .word 0x40012c00
|
|
|
|
08000490 <HAL_TIM_Encoder_MspInit>:
|
|
|
|
void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef* tim_encoderHandle)
|
|
{
|
|
8000490: b580 push {r7, lr}
|
|
8000492: b088 sub sp, #32
|
|
8000494: af00 add r7, sp, #0
|
|
8000496: 6078 str r0, [r7, #4]
|
|
|
|
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
|
8000498: f107 0310 add.w r3, r7, #16
|
|
800049c: 2200 movs r2, #0
|
|
800049e: 601a str r2, [r3, #0]
|
|
80004a0: 605a str r2, [r3, #4]
|
|
80004a2: 609a str r2, [r3, #8]
|
|
80004a4: 60da str r2, [r3, #12]
|
|
if(tim_encoderHandle->Instance==TIM1)
|
|
80004a6: 687b ldr r3, [r7, #4]
|
|
80004a8: 681b ldr r3, [r3, #0]
|
|
80004aa: 4a16 ldr r2, [pc, #88] ; (8000504 <HAL_TIM_Encoder_MspInit+0x74>)
|
|
80004ac: 4293 cmp r3, r2
|
|
80004ae: d124 bne.n 80004fa <HAL_TIM_Encoder_MspInit+0x6a>
|
|
{
|
|
/* USER CODE BEGIN TIM1_MspInit 0 */
|
|
|
|
/* USER CODE END TIM1_MspInit 0 */
|
|
/* TIM1 clock enable */
|
|
__HAL_RCC_TIM1_CLK_ENABLE();
|
|
80004b0: 4b15 ldr r3, [pc, #84] ; (8000508 <HAL_TIM_Encoder_MspInit+0x78>)
|
|
80004b2: 699b ldr r3, [r3, #24]
|
|
80004b4: 4a14 ldr r2, [pc, #80] ; (8000508 <HAL_TIM_Encoder_MspInit+0x78>)
|
|
80004b6: f443 6300 orr.w r3, r3, #2048 ; 0x800
|
|
80004ba: 6193 str r3, [r2, #24]
|
|
80004bc: 4b12 ldr r3, [pc, #72] ; (8000508 <HAL_TIM_Encoder_MspInit+0x78>)
|
|
80004be: 699b ldr r3, [r3, #24]
|
|
80004c0: f403 6300 and.w r3, r3, #2048 ; 0x800
|
|
80004c4: 60fb str r3, [r7, #12]
|
|
80004c6: 68fb ldr r3, [r7, #12]
|
|
|
|
__HAL_RCC_GPIOA_CLK_ENABLE();
|
|
80004c8: 4b0f ldr r3, [pc, #60] ; (8000508 <HAL_TIM_Encoder_MspInit+0x78>)
|
|
80004ca: 699b ldr r3, [r3, #24]
|
|
80004cc: 4a0e ldr r2, [pc, #56] ; (8000508 <HAL_TIM_Encoder_MspInit+0x78>)
|
|
80004ce: f043 0304 orr.w r3, r3, #4
|
|
80004d2: 6193 str r3, [r2, #24]
|
|
80004d4: 4b0c ldr r3, [pc, #48] ; (8000508 <HAL_TIM_Encoder_MspInit+0x78>)
|
|
80004d6: 699b ldr r3, [r3, #24]
|
|
80004d8: f003 0304 and.w r3, r3, #4
|
|
80004dc: 60bb str r3, [r7, #8]
|
|
80004de: 68bb ldr r3, [r7, #8]
|
|
/**TIM1 GPIO Configuration
|
|
PA8 ------> TIM1_CH1
|
|
PA9 ------> TIM1_CH2
|
|
*/
|
|
GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9;
|
|
80004e0: f44f 7340 mov.w r3, #768 ; 0x300
|
|
80004e4: 613b str r3, [r7, #16]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
|
|
80004e6: 2300 movs r3, #0
|
|
80004e8: 617b str r3, [r7, #20]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
80004ea: 2300 movs r3, #0
|
|
80004ec: 61bb str r3, [r7, #24]
|
|
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
|
80004ee: f107 0310 add.w r3, r7, #16
|
|
80004f2: 4619 mov r1, r3
|
|
80004f4: 4805 ldr r0, [pc, #20] ; (800050c <HAL_TIM_Encoder_MspInit+0x7c>)
|
|
80004f6: f000 fa0f bl 8000918 <HAL_GPIO_Init>
|
|
|
|
/* USER CODE BEGIN TIM1_MspInit 1 */
|
|
|
|
/* USER CODE END TIM1_MspInit 1 */
|
|
}
|
|
}
|
|
80004fa: bf00 nop
|
|
80004fc: 3720 adds r7, #32
|
|
80004fe: 46bd mov sp, r7
|
|
8000500: bd80 pop {r7, pc}
|
|
8000502: bf00 nop
|
|
8000504: 40012c00 .word 0x40012c00
|
|
8000508: 40021000 .word 0x40021000
|
|
800050c: 40010800 .word 0x40010800
|
|
|
|
08000510 <MX_USART2_UART_Init>:
|
|
UART_HandleTypeDef huart2;
|
|
|
|
/* USART2 init function */
|
|
|
|
void MX_USART2_UART_Init(void)
|
|
{
|
|
8000510: b580 push {r7, lr}
|
|
8000512: af00 add r7, sp, #0
|
|
/* USER CODE END USART2_Init 0 */
|
|
|
|
/* USER CODE BEGIN USART2_Init 1 */
|
|
|
|
/* USER CODE END USART2_Init 1 */
|
|
huart2.Instance = USART2;
|
|
8000514: 4b11 ldr r3, [pc, #68] ; (800055c <MX_USART2_UART_Init+0x4c>)
|
|
8000516: 4a12 ldr r2, [pc, #72] ; (8000560 <MX_USART2_UART_Init+0x50>)
|
|
8000518: 601a str r2, [r3, #0]
|
|
huart2.Init.BaudRate = 115200;
|
|
800051a: 4b10 ldr r3, [pc, #64] ; (800055c <MX_USART2_UART_Init+0x4c>)
|
|
800051c: f44f 32e1 mov.w r2, #115200 ; 0x1c200
|
|
8000520: 605a str r2, [r3, #4]
|
|
huart2.Init.WordLength = UART_WORDLENGTH_8B;
|
|
8000522: 4b0e ldr r3, [pc, #56] ; (800055c <MX_USART2_UART_Init+0x4c>)
|
|
8000524: 2200 movs r2, #0
|
|
8000526: 609a str r2, [r3, #8]
|
|
huart2.Init.StopBits = UART_STOPBITS_1;
|
|
8000528: 4b0c ldr r3, [pc, #48] ; (800055c <MX_USART2_UART_Init+0x4c>)
|
|
800052a: 2200 movs r2, #0
|
|
800052c: 60da str r2, [r3, #12]
|
|
huart2.Init.Parity = UART_PARITY_NONE;
|
|
800052e: 4b0b ldr r3, [pc, #44] ; (800055c <MX_USART2_UART_Init+0x4c>)
|
|
8000530: 2200 movs r2, #0
|
|
8000532: 611a str r2, [r3, #16]
|
|
huart2.Init.Mode = UART_MODE_TX_RX;
|
|
8000534: 4b09 ldr r3, [pc, #36] ; (800055c <MX_USART2_UART_Init+0x4c>)
|
|
8000536: 220c movs r2, #12
|
|
8000538: 615a str r2, [r3, #20]
|
|
huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE;
|
|
800053a: 4b08 ldr r3, [pc, #32] ; (800055c <MX_USART2_UART_Init+0x4c>)
|
|
800053c: 2200 movs r2, #0
|
|
800053e: 619a str r2, [r3, #24]
|
|
huart2.Init.OverSampling = UART_OVERSAMPLING_16;
|
|
8000540: 4b06 ldr r3, [pc, #24] ; (800055c <MX_USART2_UART_Init+0x4c>)
|
|
8000542: 2200 movs r2, #0
|
|
8000544: 61da str r2, [r3, #28]
|
|
if (HAL_UART_Init(&huart2) != HAL_OK)
|
|
8000546: 4805 ldr r0, [pc, #20] ; (800055c <MX_USART2_UART_Init+0x4c>)
|
|
8000548: f001 f998 bl 800187c <HAL_UART_Init>
|
|
800054c: 4603 mov r3, r0
|
|
800054e: 2b00 cmp r3, #0
|
|
8000550: d001 beq.n 8000556 <MX_USART2_UART_Init+0x46>
|
|
{
|
|
Error_Handler();
|
|
8000552: f7ff feaa bl 80002aa <Error_Handler>
|
|
}
|
|
/* USER CODE BEGIN USART2_Init 2 */
|
|
|
|
/* USER CODE END USART2_Init 2 */
|
|
|
|
}
|
|
8000556: bf00 nop
|
|
8000558: bd80 pop {r7, pc}
|
|
800055a: bf00 nop
|
|
800055c: 200000d8 .word 0x200000d8
|
|
8000560: 40004400 .word 0x40004400
|
|
|
|
08000564 <HAL_UART_MspInit>:
|
|
|
|
void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle)
|
|
{
|
|
8000564: b580 push {r7, lr}
|
|
8000566: b088 sub sp, #32
|
|
8000568: af00 add r7, sp, #0
|
|
800056a: 6078 str r0, [r7, #4]
|
|
|
|
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
|
800056c: f107 0310 add.w r3, r7, #16
|
|
8000570: 2200 movs r2, #0
|
|
8000572: 601a str r2, [r3, #0]
|
|
8000574: 605a str r2, [r3, #4]
|
|
8000576: 609a str r2, [r3, #8]
|
|
8000578: 60da str r2, [r3, #12]
|
|
if(uartHandle->Instance==USART2)
|
|
800057a: 687b ldr r3, [r7, #4]
|
|
800057c: 681b ldr r3, [r3, #0]
|
|
800057e: 4a1b ldr r2, [pc, #108] ; (80005ec <HAL_UART_MspInit+0x88>)
|
|
8000580: 4293 cmp r3, r2
|
|
8000582: d12f bne.n 80005e4 <HAL_UART_MspInit+0x80>
|
|
{
|
|
/* USER CODE BEGIN USART2_MspInit 0 */
|
|
|
|
/* USER CODE END USART2_MspInit 0 */
|
|
/* USART2 clock enable */
|
|
__HAL_RCC_USART2_CLK_ENABLE();
|
|
8000584: 4b1a ldr r3, [pc, #104] ; (80005f0 <HAL_UART_MspInit+0x8c>)
|
|
8000586: 69db ldr r3, [r3, #28]
|
|
8000588: 4a19 ldr r2, [pc, #100] ; (80005f0 <HAL_UART_MspInit+0x8c>)
|
|
800058a: f443 3300 orr.w r3, r3, #131072 ; 0x20000
|
|
800058e: 61d3 str r3, [r2, #28]
|
|
8000590: 4b17 ldr r3, [pc, #92] ; (80005f0 <HAL_UART_MspInit+0x8c>)
|
|
8000592: 69db ldr r3, [r3, #28]
|
|
8000594: f403 3300 and.w r3, r3, #131072 ; 0x20000
|
|
8000598: 60fb str r3, [r7, #12]
|
|
800059a: 68fb ldr r3, [r7, #12]
|
|
|
|
__HAL_RCC_GPIOA_CLK_ENABLE();
|
|
800059c: 4b14 ldr r3, [pc, #80] ; (80005f0 <HAL_UART_MspInit+0x8c>)
|
|
800059e: 699b ldr r3, [r3, #24]
|
|
80005a0: 4a13 ldr r2, [pc, #76] ; (80005f0 <HAL_UART_MspInit+0x8c>)
|
|
80005a2: f043 0304 orr.w r3, r3, #4
|
|
80005a6: 6193 str r3, [r2, #24]
|
|
80005a8: 4b11 ldr r3, [pc, #68] ; (80005f0 <HAL_UART_MspInit+0x8c>)
|
|
80005aa: 699b ldr r3, [r3, #24]
|
|
80005ac: f003 0304 and.w r3, r3, #4
|
|
80005b0: 60bb str r3, [r7, #8]
|
|
80005b2: 68bb ldr r3, [r7, #8]
|
|
/**USART2 GPIO Configuration
|
|
PA2 ------> USART2_TX
|
|
PA3 ------> USART2_RX
|
|
*/
|
|
GPIO_InitStruct.Pin = GPIO_PIN_2;
|
|
80005b4: 2304 movs r3, #4
|
|
80005b6: 613b str r3, [r7, #16]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
80005b8: 2302 movs r3, #2
|
|
80005ba: 617b str r3, [r7, #20]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
|
|
80005bc: 2303 movs r3, #3
|
|
80005be: 61fb str r3, [r7, #28]
|
|
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
|
80005c0: f107 0310 add.w r3, r7, #16
|
|
80005c4: 4619 mov r1, r3
|
|
80005c6: 480b ldr r0, [pc, #44] ; (80005f4 <HAL_UART_MspInit+0x90>)
|
|
80005c8: f000 f9a6 bl 8000918 <HAL_GPIO_Init>
|
|
|
|
GPIO_InitStruct.Pin = GPIO_PIN_3;
|
|
80005cc: 2308 movs r3, #8
|
|
80005ce: 613b str r3, [r7, #16]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
|
|
80005d0: 2300 movs r3, #0
|
|
80005d2: 617b str r3, [r7, #20]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
80005d4: 2300 movs r3, #0
|
|
80005d6: 61bb str r3, [r7, #24]
|
|
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
|
80005d8: f107 0310 add.w r3, r7, #16
|
|
80005dc: 4619 mov r1, r3
|
|
80005de: 4805 ldr r0, [pc, #20] ; (80005f4 <HAL_UART_MspInit+0x90>)
|
|
80005e0: f000 f99a bl 8000918 <HAL_GPIO_Init>
|
|
|
|
/* USER CODE BEGIN USART2_MspInit 1 */
|
|
|
|
/* USER CODE END USART2_MspInit 1 */
|
|
}
|
|
}
|
|
80005e4: bf00 nop
|
|
80005e6: 3720 adds r7, #32
|
|
80005e8: 46bd mov sp, r7
|
|
80005ea: bd80 pop {r7, pc}
|
|
80005ec: 40004400 .word 0x40004400
|
|
80005f0: 40021000 .word 0x40021000
|
|
80005f4: 40010800 .word 0x40010800
|
|
|
|
080005f8 <Reset_Handler>:
|
|
.weak Reset_Handler
|
|
.type Reset_Handler, %function
|
|
Reset_Handler:
|
|
|
|
/* Copy the data segment initializers from flash to SRAM */
|
|
ldr r0, =_sdata
|
|
80005f8: 480c ldr r0, [pc, #48] ; (800062c <LoopFillZerobss+0x12>)
|
|
ldr r1, =_edata
|
|
80005fa: 490d ldr r1, [pc, #52] ; (8000630 <LoopFillZerobss+0x16>)
|
|
ldr r2, =_sidata
|
|
80005fc: 4a0d ldr r2, [pc, #52] ; (8000634 <LoopFillZerobss+0x1a>)
|
|
movs r3, #0
|
|
80005fe: 2300 movs r3, #0
|
|
b LoopCopyDataInit
|
|
8000600: e002 b.n 8000608 <LoopCopyDataInit>
|
|
|
|
08000602 <CopyDataInit>:
|
|
|
|
CopyDataInit:
|
|
ldr r4, [r2, r3]
|
|
8000602: 58d4 ldr r4, [r2, r3]
|
|
str r4, [r0, r3]
|
|
8000604: 50c4 str r4, [r0, r3]
|
|
adds r3, r3, #4
|
|
8000606: 3304 adds r3, #4
|
|
|
|
08000608 <LoopCopyDataInit>:
|
|
|
|
LoopCopyDataInit:
|
|
adds r4, r0, r3
|
|
8000608: 18c4 adds r4, r0, r3
|
|
cmp r4, r1
|
|
800060a: 428c cmp r4, r1
|
|
bcc CopyDataInit
|
|
800060c: d3f9 bcc.n 8000602 <CopyDataInit>
|
|
|
|
/* Zero fill the bss segment. */
|
|
ldr r2, =_sbss
|
|
800060e: 4a0a ldr r2, [pc, #40] ; (8000638 <LoopFillZerobss+0x1e>)
|
|
ldr r4, =_ebss
|
|
8000610: 4c0a ldr r4, [pc, #40] ; (800063c <LoopFillZerobss+0x22>)
|
|
movs r3, #0
|
|
8000612: 2300 movs r3, #0
|
|
b LoopFillZerobss
|
|
8000614: e001 b.n 800061a <LoopFillZerobss>
|
|
|
|
08000616 <FillZerobss>:
|
|
|
|
FillZerobss:
|
|
str r3, [r2]
|
|
8000616: 6013 str r3, [r2, #0]
|
|
adds r2, r2, #4
|
|
8000618: 3204 adds r2, #4
|
|
|
|
0800061a <LoopFillZerobss>:
|
|
|
|
LoopFillZerobss:
|
|
cmp r2, r4
|
|
800061a: 42a2 cmp r2, r4
|
|
bcc FillZerobss
|
|
800061c: d3fb bcc.n 8000616 <FillZerobss>
|
|
|
|
/* Call the clock system intitialization function.*/
|
|
bl SystemInit
|
|
800061e: f7ff fed9 bl 80003d4 <SystemInit>
|
|
/* Call static constructors */
|
|
bl __libc_init_array
|
|
8000622: f001 fae9 bl 8001bf8 <__libc_init_array>
|
|
/* Call the application's entry point.*/
|
|
bl main
|
|
8000626: f7ff fdbb bl 80001a0 <main>
|
|
bx lr
|
|
800062a: 4770 bx lr
|
|
ldr r0, =_sdata
|
|
800062c: 20000000 .word 0x20000000
|
|
ldr r1, =_edata
|
|
8000630: 20000070 .word 0x20000070
|
|
ldr r2, =_sidata
|
|
8000634: 080025c8 .word 0x080025c8
|
|
ldr r2, =_sbss
|
|
8000638: 20000070 .word 0x20000070
|
|
ldr r4, =_ebss
|
|
800063c: 20000130 .word 0x20000130
|
|
|
|
08000640 <ADC1_2_IRQHandler>:
|
|
* @retval : None
|
|
*/
|
|
.section .text.Default_Handler,"ax",%progbits
|
|
Default_Handler:
|
|
Infinite_Loop:
|
|
b Infinite_Loop
|
|
8000640: e7fe b.n 8000640 <ADC1_2_IRQHandler>
|
|
...
|
|
|
|
08000644 <HAL_Init>:
|
|
* need to ensure that the SysTick time base is always set to 1 millisecond
|
|
* to have correct HAL operation.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_Init(void)
|
|
{
|
|
8000644: b580 push {r7, lr}
|
|
8000646: af00 add r7, sp, #0
|
|
defined(STM32F102x6) || defined(STM32F102xB) || \
|
|
defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || \
|
|
defined(STM32F105xC) || defined(STM32F107xC)
|
|
|
|
/* Prefetch buffer is not available on value line devices */
|
|
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
|
|
8000648: 4b08 ldr r3, [pc, #32] ; (800066c <HAL_Init+0x28>)
|
|
800064a: 681b ldr r3, [r3, #0]
|
|
800064c: 4a07 ldr r2, [pc, #28] ; (800066c <HAL_Init+0x28>)
|
|
800064e: f043 0310 orr.w r3, r3, #16
|
|
8000652: 6013 str r3, [r2, #0]
|
|
#endif
|
|
#endif /* PREFETCH_ENABLE */
|
|
|
|
/* Set Interrupt Group Priority */
|
|
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
|
|
8000654: 2003 movs r0, #3
|
|
8000656: f000 f92b bl 80008b0 <HAL_NVIC_SetPriorityGrouping>
|
|
|
|
/* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
|
|
HAL_InitTick(TICK_INT_PRIORITY);
|
|
800065a: 200f movs r0, #15
|
|
800065c: f000 f808 bl 8000670 <HAL_InitTick>
|
|
|
|
/* Init the low level hardware */
|
|
HAL_MspInit();
|
|
8000660: f7ff fe28 bl 80002b4 <HAL_MspInit>
|
|
|
|
/* Return function status */
|
|
return HAL_OK;
|
|
8000664: 2300 movs r3, #0
|
|
}
|
|
8000666: 4618 mov r0, r3
|
|
8000668: bd80 pop {r7, pc}
|
|
800066a: bf00 nop
|
|
800066c: 40022000 .word 0x40022000
|
|
|
|
08000670 <HAL_InitTick>:
|
|
* implementation in user file.
|
|
* @param TickPriority Tick interrupt priority.
|
|
* @retval HAL status
|
|
*/
|
|
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
|
|
{
|
|
8000670: b580 push {r7, lr}
|
|
8000672: b082 sub sp, #8
|
|
8000674: af00 add r7, sp, #0
|
|
8000676: 6078 str r0, [r7, #4]
|
|
/* Configure the SysTick to have interrupt in 1ms time basis*/
|
|
if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U)
|
|
8000678: 4b12 ldr r3, [pc, #72] ; (80006c4 <HAL_InitTick+0x54>)
|
|
800067a: 681a ldr r2, [r3, #0]
|
|
800067c: 4b12 ldr r3, [pc, #72] ; (80006c8 <HAL_InitTick+0x58>)
|
|
800067e: 781b ldrb r3, [r3, #0]
|
|
8000680: 4619 mov r1, r3
|
|
8000682: f44f 737a mov.w r3, #1000 ; 0x3e8
|
|
8000686: fbb3 f3f1 udiv r3, r3, r1
|
|
800068a: fbb2 f3f3 udiv r3, r2, r3
|
|
800068e: 4618 mov r0, r3
|
|
8000690: f000 f935 bl 80008fe <HAL_SYSTICK_Config>
|
|
8000694: 4603 mov r3, r0
|
|
8000696: 2b00 cmp r3, #0
|
|
8000698: d001 beq.n 800069e <HAL_InitTick+0x2e>
|
|
{
|
|
return HAL_ERROR;
|
|
800069a: 2301 movs r3, #1
|
|
800069c: e00e b.n 80006bc <HAL_InitTick+0x4c>
|
|
}
|
|
|
|
/* Configure the SysTick IRQ priority */
|
|
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
|
|
800069e: 687b ldr r3, [r7, #4]
|
|
80006a0: 2b0f cmp r3, #15
|
|
80006a2: d80a bhi.n 80006ba <HAL_InitTick+0x4a>
|
|
{
|
|
HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
|
|
80006a4: 2200 movs r2, #0
|
|
80006a6: 6879 ldr r1, [r7, #4]
|
|
80006a8: f04f 30ff mov.w r0, #4294967295
|
|
80006ac: f000 f90b bl 80008c6 <HAL_NVIC_SetPriority>
|
|
uwTickPrio = TickPriority;
|
|
80006b0: 4a06 ldr r2, [pc, #24] ; (80006cc <HAL_InitTick+0x5c>)
|
|
80006b2: 687b ldr r3, [r7, #4]
|
|
80006b4: 6013 str r3, [r2, #0]
|
|
{
|
|
return HAL_ERROR;
|
|
}
|
|
|
|
/* Return function status */
|
|
return HAL_OK;
|
|
80006b6: 2300 movs r3, #0
|
|
80006b8: e000 b.n 80006bc <HAL_InitTick+0x4c>
|
|
return HAL_ERROR;
|
|
80006ba: 2301 movs r3, #1
|
|
}
|
|
80006bc: 4618 mov r0, r3
|
|
80006be: 3708 adds r7, #8
|
|
80006c0: 46bd mov sp, r7
|
|
80006c2: bd80 pop {r7, pc}
|
|
80006c4: 20000000 .word 0x20000000
|
|
80006c8: 20000008 .word 0x20000008
|
|
80006cc: 20000004 .word 0x20000004
|
|
|
|
080006d0 <HAL_IncTick>:
|
|
* @note This function is declared as __weak to be overwritten in case of other
|
|
* implementations in user file.
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_IncTick(void)
|
|
{
|
|
80006d0: b480 push {r7}
|
|
80006d2: af00 add r7, sp, #0
|
|
uwTick += uwTickFreq;
|
|
80006d4: 4b05 ldr r3, [pc, #20] ; (80006ec <HAL_IncTick+0x1c>)
|
|
80006d6: 781b ldrb r3, [r3, #0]
|
|
80006d8: 461a mov r2, r3
|
|
80006da: 4b05 ldr r3, [pc, #20] ; (80006f0 <HAL_IncTick+0x20>)
|
|
80006dc: 681b ldr r3, [r3, #0]
|
|
80006de: 4413 add r3, r2
|
|
80006e0: 4a03 ldr r2, [pc, #12] ; (80006f0 <HAL_IncTick+0x20>)
|
|
80006e2: 6013 str r3, [r2, #0]
|
|
}
|
|
80006e4: bf00 nop
|
|
80006e6: 46bd mov sp, r7
|
|
80006e8: bc80 pop {r7}
|
|
80006ea: 4770 bx lr
|
|
80006ec: 20000008 .word 0x20000008
|
|
80006f0: 2000011c .word 0x2000011c
|
|
|
|
080006f4 <HAL_GetTick>:
|
|
* @note This function is declared as __weak to be overwritten in case of other
|
|
* implementations in user file.
|
|
* @retval tick value
|
|
*/
|
|
__weak uint32_t HAL_GetTick(void)
|
|
{
|
|
80006f4: b480 push {r7}
|
|
80006f6: af00 add r7, sp, #0
|
|
return uwTick;
|
|
80006f8: 4b02 ldr r3, [pc, #8] ; (8000704 <HAL_GetTick+0x10>)
|
|
80006fa: 681b ldr r3, [r3, #0]
|
|
}
|
|
80006fc: 4618 mov r0, r3
|
|
80006fe: 46bd mov sp, r7
|
|
8000700: bc80 pop {r7}
|
|
8000702: 4770 bx lr
|
|
8000704: 2000011c .word 0x2000011c
|
|
|
|
08000708 <HAL_Delay>:
|
|
* implementations in user file.
|
|
* @param Delay specifies the delay time length, in milliseconds.
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_Delay(uint32_t Delay)
|
|
{
|
|
8000708: b580 push {r7, lr}
|
|
800070a: b084 sub sp, #16
|
|
800070c: af00 add r7, sp, #0
|
|
800070e: 6078 str r0, [r7, #4]
|
|
uint32_t tickstart = HAL_GetTick();
|
|
8000710: f7ff fff0 bl 80006f4 <HAL_GetTick>
|
|
8000714: 60b8 str r0, [r7, #8]
|
|
uint32_t wait = Delay;
|
|
8000716: 687b ldr r3, [r7, #4]
|
|
8000718: 60fb str r3, [r7, #12]
|
|
|
|
/* Add a freq to guarantee minimum wait */
|
|
if (wait < HAL_MAX_DELAY)
|
|
800071a: 68fb ldr r3, [r7, #12]
|
|
800071c: f1b3 3fff cmp.w r3, #4294967295
|
|
8000720: d005 beq.n 800072e <HAL_Delay+0x26>
|
|
{
|
|
wait += (uint32_t)(uwTickFreq);
|
|
8000722: 4b0a ldr r3, [pc, #40] ; (800074c <HAL_Delay+0x44>)
|
|
8000724: 781b ldrb r3, [r3, #0]
|
|
8000726: 461a mov r2, r3
|
|
8000728: 68fb ldr r3, [r7, #12]
|
|
800072a: 4413 add r3, r2
|
|
800072c: 60fb str r3, [r7, #12]
|
|
}
|
|
|
|
while ((HAL_GetTick() - tickstart) < wait)
|
|
800072e: bf00 nop
|
|
8000730: f7ff ffe0 bl 80006f4 <HAL_GetTick>
|
|
8000734: 4602 mov r2, r0
|
|
8000736: 68bb ldr r3, [r7, #8]
|
|
8000738: 1ad3 subs r3, r2, r3
|
|
800073a: 68fa ldr r2, [r7, #12]
|
|
800073c: 429a cmp r2, r3
|
|
800073e: d8f7 bhi.n 8000730 <HAL_Delay+0x28>
|
|
{
|
|
}
|
|
}
|
|
8000740: bf00 nop
|
|
8000742: bf00 nop
|
|
8000744: 3710 adds r7, #16
|
|
8000746: 46bd mov sp, r7
|
|
8000748: bd80 pop {r7, pc}
|
|
800074a: bf00 nop
|
|
800074c: 20000008 .word 0x20000008
|
|
|
|
08000750 <__NVIC_SetPriorityGrouping>:
|
|
In case of a conflict between priority grouping and available
|
|
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
|
|
\param [in] PriorityGroup Priority grouping field.
|
|
*/
|
|
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
|
|
{
|
|
8000750: b480 push {r7}
|
|
8000752: b085 sub sp, #20
|
|
8000754: af00 add r7, sp, #0
|
|
8000756: 6078 str r0, [r7, #4]
|
|
uint32_t reg_value;
|
|
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
|
|
8000758: 687b ldr r3, [r7, #4]
|
|
800075a: f003 0307 and.w r3, r3, #7
|
|
800075e: 60fb str r3, [r7, #12]
|
|
|
|
reg_value = SCB->AIRCR; /* read old register configuration */
|
|
8000760: 4b0c ldr r3, [pc, #48] ; (8000794 <__NVIC_SetPriorityGrouping+0x44>)
|
|
8000762: 68db ldr r3, [r3, #12]
|
|
8000764: 60bb str r3, [r7, #8]
|
|
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
|
|
8000766: 68ba ldr r2, [r7, #8]
|
|
8000768: f64f 03ff movw r3, #63743 ; 0xf8ff
|
|
800076c: 4013 ands r3, r2
|
|
800076e: 60bb str r3, [r7, #8]
|
|
reg_value = (reg_value |
|
|
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
|
|
(PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
|
|
8000770: 68fb ldr r3, [r7, #12]
|
|
8000772: 021a lsls r2, r3, #8
|
|
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
|
|
8000774: 68bb ldr r3, [r7, #8]
|
|
8000776: 4313 orrs r3, r2
|
|
reg_value = (reg_value |
|
|
8000778: f043 63bf orr.w r3, r3, #100139008 ; 0x5f80000
|
|
800077c: f443 3300 orr.w r3, r3, #131072 ; 0x20000
|
|
8000780: 60bb str r3, [r7, #8]
|
|
SCB->AIRCR = reg_value;
|
|
8000782: 4a04 ldr r2, [pc, #16] ; (8000794 <__NVIC_SetPriorityGrouping+0x44>)
|
|
8000784: 68bb ldr r3, [r7, #8]
|
|
8000786: 60d3 str r3, [r2, #12]
|
|
}
|
|
8000788: bf00 nop
|
|
800078a: 3714 adds r7, #20
|
|
800078c: 46bd mov sp, r7
|
|
800078e: bc80 pop {r7}
|
|
8000790: 4770 bx lr
|
|
8000792: bf00 nop
|
|
8000794: e000ed00 .word 0xe000ed00
|
|
|
|
08000798 <__NVIC_GetPriorityGrouping>:
|
|
\brief Get Priority Grouping
|
|
\details Reads the priority grouping field from the NVIC Interrupt Controller.
|
|
\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
|
|
*/
|
|
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
|
|
{
|
|
8000798: b480 push {r7}
|
|
800079a: af00 add r7, sp, #0
|
|
return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
|
|
800079c: 4b04 ldr r3, [pc, #16] ; (80007b0 <__NVIC_GetPriorityGrouping+0x18>)
|
|
800079e: 68db ldr r3, [r3, #12]
|
|
80007a0: 0a1b lsrs r3, r3, #8
|
|
80007a2: f003 0307 and.w r3, r3, #7
|
|
}
|
|
80007a6: 4618 mov r0, r3
|
|
80007a8: 46bd mov sp, r7
|
|
80007aa: bc80 pop {r7}
|
|
80007ac: 4770 bx lr
|
|
80007ae: bf00 nop
|
|
80007b0: e000ed00 .word 0xe000ed00
|
|
|
|
080007b4 <__NVIC_SetPriority>:
|
|
\param [in] IRQn Interrupt number.
|
|
\param [in] priority Priority to set.
|
|
\note The priority cannot be set for every processor exception.
|
|
*/
|
|
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
|
|
{
|
|
80007b4: b480 push {r7}
|
|
80007b6: b083 sub sp, #12
|
|
80007b8: af00 add r7, sp, #0
|
|
80007ba: 4603 mov r3, r0
|
|
80007bc: 6039 str r1, [r7, #0]
|
|
80007be: 71fb strb r3, [r7, #7]
|
|
if ((int32_t)(IRQn) >= 0)
|
|
80007c0: f997 3007 ldrsb.w r3, [r7, #7]
|
|
80007c4: 2b00 cmp r3, #0
|
|
80007c6: db0a blt.n 80007de <__NVIC_SetPriority+0x2a>
|
|
{
|
|
NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
|
|
80007c8: 683b ldr r3, [r7, #0]
|
|
80007ca: b2da uxtb r2, r3
|
|
80007cc: 490c ldr r1, [pc, #48] ; (8000800 <__NVIC_SetPriority+0x4c>)
|
|
80007ce: f997 3007 ldrsb.w r3, [r7, #7]
|
|
80007d2: 0112 lsls r2, r2, #4
|
|
80007d4: b2d2 uxtb r2, r2
|
|
80007d6: 440b add r3, r1
|
|
80007d8: f883 2300 strb.w r2, [r3, #768] ; 0x300
|
|
}
|
|
else
|
|
{
|
|
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
|
|
}
|
|
}
|
|
80007dc: e00a b.n 80007f4 <__NVIC_SetPriority+0x40>
|
|
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
|
|
80007de: 683b ldr r3, [r7, #0]
|
|
80007e0: b2da uxtb r2, r3
|
|
80007e2: 4908 ldr r1, [pc, #32] ; (8000804 <__NVIC_SetPriority+0x50>)
|
|
80007e4: 79fb ldrb r3, [r7, #7]
|
|
80007e6: f003 030f and.w r3, r3, #15
|
|
80007ea: 3b04 subs r3, #4
|
|
80007ec: 0112 lsls r2, r2, #4
|
|
80007ee: b2d2 uxtb r2, r2
|
|
80007f0: 440b add r3, r1
|
|
80007f2: 761a strb r2, [r3, #24]
|
|
}
|
|
80007f4: bf00 nop
|
|
80007f6: 370c adds r7, #12
|
|
80007f8: 46bd mov sp, r7
|
|
80007fa: bc80 pop {r7}
|
|
80007fc: 4770 bx lr
|
|
80007fe: bf00 nop
|
|
8000800: e000e100 .word 0xe000e100
|
|
8000804: e000ed00 .word 0xe000ed00
|
|
|
|
08000808 <NVIC_EncodePriority>:
|
|
\param [in] PreemptPriority Preemptive priority value (starting from 0).
|
|
\param [in] SubPriority Subpriority value (starting from 0).
|
|
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
|
|
*/
|
|
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
|
|
{
|
|
8000808: b480 push {r7}
|
|
800080a: b089 sub sp, #36 ; 0x24
|
|
800080c: af00 add r7, sp, #0
|
|
800080e: 60f8 str r0, [r7, #12]
|
|
8000810: 60b9 str r1, [r7, #8]
|
|
8000812: 607a str r2, [r7, #4]
|
|
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
|
|
8000814: 68fb ldr r3, [r7, #12]
|
|
8000816: f003 0307 and.w r3, r3, #7
|
|
800081a: 61fb str r3, [r7, #28]
|
|
uint32_t PreemptPriorityBits;
|
|
uint32_t SubPriorityBits;
|
|
|
|
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
|
|
800081c: 69fb ldr r3, [r7, #28]
|
|
800081e: f1c3 0307 rsb r3, r3, #7
|
|
8000822: 2b04 cmp r3, #4
|
|
8000824: bf28 it cs
|
|
8000826: 2304 movcs r3, #4
|
|
8000828: 61bb str r3, [r7, #24]
|
|
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
|
|
800082a: 69fb ldr r3, [r7, #28]
|
|
800082c: 3304 adds r3, #4
|
|
800082e: 2b06 cmp r3, #6
|
|
8000830: d902 bls.n 8000838 <NVIC_EncodePriority+0x30>
|
|
8000832: 69fb ldr r3, [r7, #28]
|
|
8000834: 3b03 subs r3, #3
|
|
8000836: e000 b.n 800083a <NVIC_EncodePriority+0x32>
|
|
8000838: 2300 movs r3, #0
|
|
800083a: 617b str r3, [r7, #20]
|
|
|
|
return (
|
|
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
|
|
800083c: f04f 32ff mov.w r2, #4294967295
|
|
8000840: 69bb ldr r3, [r7, #24]
|
|
8000842: fa02 f303 lsl.w r3, r2, r3
|
|
8000846: 43da mvns r2, r3
|
|
8000848: 68bb ldr r3, [r7, #8]
|
|
800084a: 401a ands r2, r3
|
|
800084c: 697b ldr r3, [r7, #20]
|
|
800084e: 409a lsls r2, r3
|
|
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
|
|
8000850: f04f 31ff mov.w r1, #4294967295
|
|
8000854: 697b ldr r3, [r7, #20]
|
|
8000856: fa01 f303 lsl.w r3, r1, r3
|
|
800085a: 43d9 mvns r1, r3
|
|
800085c: 687b ldr r3, [r7, #4]
|
|
800085e: 400b ands r3, r1
|
|
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
|
|
8000860: 4313 orrs r3, r2
|
|
);
|
|
}
|
|
8000862: 4618 mov r0, r3
|
|
8000864: 3724 adds r7, #36 ; 0x24
|
|
8000866: 46bd mov sp, r7
|
|
8000868: bc80 pop {r7}
|
|
800086a: 4770 bx lr
|
|
|
|
0800086c <SysTick_Config>:
|
|
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
|
|
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
|
|
must contain a vendor-specific implementation of this function.
|
|
*/
|
|
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
|
|
{
|
|
800086c: b580 push {r7, lr}
|
|
800086e: b082 sub sp, #8
|
|
8000870: af00 add r7, sp, #0
|
|
8000872: 6078 str r0, [r7, #4]
|
|
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
|
|
8000874: 687b ldr r3, [r7, #4]
|
|
8000876: 3b01 subs r3, #1
|
|
8000878: f1b3 7f80 cmp.w r3, #16777216 ; 0x1000000
|
|
800087c: d301 bcc.n 8000882 <SysTick_Config+0x16>
|
|
{
|
|
return (1UL); /* Reload value impossible */
|
|
800087e: 2301 movs r3, #1
|
|
8000880: e00f b.n 80008a2 <SysTick_Config+0x36>
|
|
}
|
|
|
|
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
|
|
8000882: 4a0a ldr r2, [pc, #40] ; (80008ac <SysTick_Config+0x40>)
|
|
8000884: 687b ldr r3, [r7, #4]
|
|
8000886: 3b01 subs r3, #1
|
|
8000888: 6053 str r3, [r2, #4]
|
|
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
|
|
800088a: 210f movs r1, #15
|
|
800088c: f04f 30ff mov.w r0, #4294967295
|
|
8000890: f7ff ff90 bl 80007b4 <__NVIC_SetPriority>
|
|
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
|
|
8000894: 4b05 ldr r3, [pc, #20] ; (80008ac <SysTick_Config+0x40>)
|
|
8000896: 2200 movs r2, #0
|
|
8000898: 609a str r2, [r3, #8]
|
|
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
|
|
800089a: 4b04 ldr r3, [pc, #16] ; (80008ac <SysTick_Config+0x40>)
|
|
800089c: 2207 movs r2, #7
|
|
800089e: 601a str r2, [r3, #0]
|
|
SysTick_CTRL_TICKINT_Msk |
|
|
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
|
|
return (0UL); /* Function successful */
|
|
80008a0: 2300 movs r3, #0
|
|
}
|
|
80008a2: 4618 mov r0, r3
|
|
80008a4: 3708 adds r7, #8
|
|
80008a6: 46bd mov sp, r7
|
|
80008a8: bd80 pop {r7, pc}
|
|
80008aa: bf00 nop
|
|
80008ac: e000e010 .word 0xe000e010
|
|
|
|
080008b0 <HAL_NVIC_SetPriorityGrouping>:
|
|
* @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible.
|
|
* The pending IRQ priority will be managed only by the subpriority.
|
|
* @retval None
|
|
*/
|
|
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
|
|
{
|
|
80008b0: b580 push {r7, lr}
|
|
80008b2: b082 sub sp, #8
|
|
80008b4: af00 add r7, sp, #0
|
|
80008b6: 6078 str r0, [r7, #4]
|
|
/* Check the parameters */
|
|
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
|
|
|
|
/* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
|
|
NVIC_SetPriorityGrouping(PriorityGroup);
|
|
80008b8: 6878 ldr r0, [r7, #4]
|
|
80008ba: f7ff ff49 bl 8000750 <__NVIC_SetPriorityGrouping>
|
|
}
|
|
80008be: bf00 nop
|
|
80008c0: 3708 adds r7, #8
|
|
80008c2: 46bd mov sp, r7
|
|
80008c4: bd80 pop {r7, pc}
|
|
|
|
080008c6 <HAL_NVIC_SetPriority>:
|
|
* This parameter can be a value between 0 and 15
|
|
* A lower priority value indicates a higher priority.
|
|
* @retval None
|
|
*/
|
|
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
|
|
{
|
|
80008c6: b580 push {r7, lr}
|
|
80008c8: b086 sub sp, #24
|
|
80008ca: af00 add r7, sp, #0
|
|
80008cc: 4603 mov r3, r0
|
|
80008ce: 60b9 str r1, [r7, #8]
|
|
80008d0: 607a str r2, [r7, #4]
|
|
80008d2: 73fb strb r3, [r7, #15]
|
|
uint32_t prioritygroup = 0x00U;
|
|
80008d4: 2300 movs r3, #0
|
|
80008d6: 617b str r3, [r7, #20]
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
|
|
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
|
|
|
|
prioritygroup = NVIC_GetPriorityGrouping();
|
|
80008d8: f7ff ff5e bl 8000798 <__NVIC_GetPriorityGrouping>
|
|
80008dc: 6178 str r0, [r7, #20]
|
|
|
|
NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
|
|
80008de: 687a ldr r2, [r7, #4]
|
|
80008e0: 68b9 ldr r1, [r7, #8]
|
|
80008e2: 6978 ldr r0, [r7, #20]
|
|
80008e4: f7ff ff90 bl 8000808 <NVIC_EncodePriority>
|
|
80008e8: 4602 mov r2, r0
|
|
80008ea: f997 300f ldrsb.w r3, [r7, #15]
|
|
80008ee: 4611 mov r1, r2
|
|
80008f0: 4618 mov r0, r3
|
|
80008f2: f7ff ff5f bl 80007b4 <__NVIC_SetPriority>
|
|
}
|
|
80008f6: bf00 nop
|
|
80008f8: 3718 adds r7, #24
|
|
80008fa: 46bd mov sp, r7
|
|
80008fc: bd80 pop {r7, pc}
|
|
|
|
080008fe <HAL_SYSTICK_Config>:
|
|
* @param TicksNumb: Specifies the ticks Number of ticks between two interrupts.
|
|
* @retval status: - 0 Function succeeded.
|
|
* - 1 Function failed.
|
|
*/
|
|
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
|
|
{
|
|
80008fe: b580 push {r7, lr}
|
|
8000900: b082 sub sp, #8
|
|
8000902: af00 add r7, sp, #0
|
|
8000904: 6078 str r0, [r7, #4]
|
|
return SysTick_Config(TicksNumb);
|
|
8000906: 6878 ldr r0, [r7, #4]
|
|
8000908: f7ff ffb0 bl 800086c <SysTick_Config>
|
|
800090c: 4603 mov r3, r0
|
|
}
|
|
800090e: 4618 mov r0, r3
|
|
8000910: 3708 adds r7, #8
|
|
8000912: 46bd mov sp, r7
|
|
8000914: bd80 pop {r7, pc}
|
|
...
|
|
|
|
08000918 <HAL_GPIO_Init>:
|
|
* @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains
|
|
* the configuration information for the specified GPIO peripheral.
|
|
* @retval None
|
|
*/
|
|
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
|
|
{
|
|
8000918: b480 push {r7}
|
|
800091a: b08b sub sp, #44 ; 0x2c
|
|
800091c: af00 add r7, sp, #0
|
|
800091e: 6078 str r0, [r7, #4]
|
|
8000920: 6039 str r1, [r7, #0]
|
|
uint32_t position = 0x00u;
|
|
8000922: 2300 movs r3, #0
|
|
8000924: 627b str r3, [r7, #36] ; 0x24
|
|
uint32_t ioposition;
|
|
uint32_t iocurrent;
|
|
uint32_t temp;
|
|
uint32_t config = 0x00u;
|
|
8000926: 2300 movs r3, #0
|
|
8000928: 623b str r3, [r7, #32]
|
|
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
|
|
assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
|
|
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
|
|
|
|
/* Configure the port pins */
|
|
while (((GPIO_Init->Pin) >> position) != 0x00u)
|
|
800092a: e169 b.n 8000c00 <HAL_GPIO_Init+0x2e8>
|
|
{
|
|
/* Get the IO position */
|
|
ioposition = (0x01uL << position);
|
|
800092c: 2201 movs r2, #1
|
|
800092e: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
8000930: fa02 f303 lsl.w r3, r2, r3
|
|
8000934: 61fb str r3, [r7, #28]
|
|
|
|
/* Get the current IO position */
|
|
iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition;
|
|
8000936: 683b ldr r3, [r7, #0]
|
|
8000938: 681b ldr r3, [r3, #0]
|
|
800093a: 69fa ldr r2, [r7, #28]
|
|
800093c: 4013 ands r3, r2
|
|
800093e: 61bb str r3, [r7, #24]
|
|
|
|
if (iocurrent == ioposition)
|
|
8000940: 69ba ldr r2, [r7, #24]
|
|
8000942: 69fb ldr r3, [r7, #28]
|
|
8000944: 429a cmp r2, r3
|
|
8000946: f040 8158 bne.w 8000bfa <HAL_GPIO_Init+0x2e2>
|
|
{
|
|
/* Check the Alternate function parameters */
|
|
assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
|
|
|
|
/* Based on the required mode, filling config variable with MODEy[1:0] and CNFy[3:2] corresponding bits */
|
|
switch (GPIO_Init->Mode)
|
|
800094a: 683b ldr r3, [r7, #0]
|
|
800094c: 685b ldr r3, [r3, #4]
|
|
800094e: 4a9a ldr r2, [pc, #616] ; (8000bb8 <HAL_GPIO_Init+0x2a0>)
|
|
8000950: 4293 cmp r3, r2
|
|
8000952: d05e beq.n 8000a12 <HAL_GPIO_Init+0xfa>
|
|
8000954: 4a98 ldr r2, [pc, #608] ; (8000bb8 <HAL_GPIO_Init+0x2a0>)
|
|
8000956: 4293 cmp r3, r2
|
|
8000958: d875 bhi.n 8000a46 <HAL_GPIO_Init+0x12e>
|
|
800095a: 4a98 ldr r2, [pc, #608] ; (8000bbc <HAL_GPIO_Init+0x2a4>)
|
|
800095c: 4293 cmp r3, r2
|
|
800095e: d058 beq.n 8000a12 <HAL_GPIO_Init+0xfa>
|
|
8000960: 4a96 ldr r2, [pc, #600] ; (8000bbc <HAL_GPIO_Init+0x2a4>)
|
|
8000962: 4293 cmp r3, r2
|
|
8000964: d86f bhi.n 8000a46 <HAL_GPIO_Init+0x12e>
|
|
8000966: 4a96 ldr r2, [pc, #600] ; (8000bc0 <HAL_GPIO_Init+0x2a8>)
|
|
8000968: 4293 cmp r3, r2
|
|
800096a: d052 beq.n 8000a12 <HAL_GPIO_Init+0xfa>
|
|
800096c: 4a94 ldr r2, [pc, #592] ; (8000bc0 <HAL_GPIO_Init+0x2a8>)
|
|
800096e: 4293 cmp r3, r2
|
|
8000970: d869 bhi.n 8000a46 <HAL_GPIO_Init+0x12e>
|
|
8000972: 4a94 ldr r2, [pc, #592] ; (8000bc4 <HAL_GPIO_Init+0x2ac>)
|
|
8000974: 4293 cmp r3, r2
|
|
8000976: d04c beq.n 8000a12 <HAL_GPIO_Init+0xfa>
|
|
8000978: 4a92 ldr r2, [pc, #584] ; (8000bc4 <HAL_GPIO_Init+0x2ac>)
|
|
800097a: 4293 cmp r3, r2
|
|
800097c: d863 bhi.n 8000a46 <HAL_GPIO_Init+0x12e>
|
|
800097e: 4a92 ldr r2, [pc, #584] ; (8000bc8 <HAL_GPIO_Init+0x2b0>)
|
|
8000980: 4293 cmp r3, r2
|
|
8000982: d046 beq.n 8000a12 <HAL_GPIO_Init+0xfa>
|
|
8000984: 4a90 ldr r2, [pc, #576] ; (8000bc8 <HAL_GPIO_Init+0x2b0>)
|
|
8000986: 4293 cmp r3, r2
|
|
8000988: d85d bhi.n 8000a46 <HAL_GPIO_Init+0x12e>
|
|
800098a: 2b12 cmp r3, #18
|
|
800098c: d82a bhi.n 80009e4 <HAL_GPIO_Init+0xcc>
|
|
800098e: 2b12 cmp r3, #18
|
|
8000990: d859 bhi.n 8000a46 <HAL_GPIO_Init+0x12e>
|
|
8000992: a201 add r2, pc, #4 ; (adr r2, 8000998 <HAL_GPIO_Init+0x80>)
|
|
8000994: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
8000998: 08000a13 .word 0x08000a13
|
|
800099c: 080009ed .word 0x080009ed
|
|
80009a0: 080009ff .word 0x080009ff
|
|
80009a4: 08000a41 .word 0x08000a41
|
|
80009a8: 08000a47 .word 0x08000a47
|
|
80009ac: 08000a47 .word 0x08000a47
|
|
80009b0: 08000a47 .word 0x08000a47
|
|
80009b4: 08000a47 .word 0x08000a47
|
|
80009b8: 08000a47 .word 0x08000a47
|
|
80009bc: 08000a47 .word 0x08000a47
|
|
80009c0: 08000a47 .word 0x08000a47
|
|
80009c4: 08000a47 .word 0x08000a47
|
|
80009c8: 08000a47 .word 0x08000a47
|
|
80009cc: 08000a47 .word 0x08000a47
|
|
80009d0: 08000a47 .word 0x08000a47
|
|
80009d4: 08000a47 .word 0x08000a47
|
|
80009d8: 08000a47 .word 0x08000a47
|
|
80009dc: 080009f5 .word 0x080009f5
|
|
80009e0: 08000a09 .word 0x08000a09
|
|
80009e4: 4a79 ldr r2, [pc, #484] ; (8000bcc <HAL_GPIO_Init+0x2b4>)
|
|
80009e6: 4293 cmp r3, r2
|
|
80009e8: d013 beq.n 8000a12 <HAL_GPIO_Init+0xfa>
|
|
config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG;
|
|
break;
|
|
|
|
/* Parameters are checked with assert_param */
|
|
default:
|
|
break;
|
|
80009ea: e02c b.n 8000a46 <HAL_GPIO_Init+0x12e>
|
|
config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_PP;
|
|
80009ec: 683b ldr r3, [r7, #0]
|
|
80009ee: 68db ldr r3, [r3, #12]
|
|
80009f0: 623b str r3, [r7, #32]
|
|
break;
|
|
80009f2: e029 b.n 8000a48 <HAL_GPIO_Init+0x130>
|
|
config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_OD;
|
|
80009f4: 683b ldr r3, [r7, #0]
|
|
80009f6: 68db ldr r3, [r3, #12]
|
|
80009f8: 3304 adds r3, #4
|
|
80009fa: 623b str r3, [r7, #32]
|
|
break;
|
|
80009fc: e024 b.n 8000a48 <HAL_GPIO_Init+0x130>
|
|
config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_PP;
|
|
80009fe: 683b ldr r3, [r7, #0]
|
|
8000a00: 68db ldr r3, [r3, #12]
|
|
8000a02: 3308 adds r3, #8
|
|
8000a04: 623b str r3, [r7, #32]
|
|
break;
|
|
8000a06: e01f b.n 8000a48 <HAL_GPIO_Init+0x130>
|
|
config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_OD;
|
|
8000a08: 683b ldr r3, [r7, #0]
|
|
8000a0a: 68db ldr r3, [r3, #12]
|
|
8000a0c: 330c adds r3, #12
|
|
8000a0e: 623b str r3, [r7, #32]
|
|
break;
|
|
8000a10: e01a b.n 8000a48 <HAL_GPIO_Init+0x130>
|
|
if (GPIO_Init->Pull == GPIO_NOPULL)
|
|
8000a12: 683b ldr r3, [r7, #0]
|
|
8000a14: 689b ldr r3, [r3, #8]
|
|
8000a16: 2b00 cmp r3, #0
|
|
8000a18: d102 bne.n 8000a20 <HAL_GPIO_Init+0x108>
|
|
config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_FLOATING;
|
|
8000a1a: 2304 movs r3, #4
|
|
8000a1c: 623b str r3, [r7, #32]
|
|
break;
|
|
8000a1e: e013 b.n 8000a48 <HAL_GPIO_Init+0x130>
|
|
else if (GPIO_Init->Pull == GPIO_PULLUP)
|
|
8000a20: 683b ldr r3, [r7, #0]
|
|
8000a22: 689b ldr r3, [r3, #8]
|
|
8000a24: 2b01 cmp r3, #1
|
|
8000a26: d105 bne.n 8000a34 <HAL_GPIO_Init+0x11c>
|
|
config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD;
|
|
8000a28: 2308 movs r3, #8
|
|
8000a2a: 623b str r3, [r7, #32]
|
|
GPIOx->BSRR = ioposition;
|
|
8000a2c: 687b ldr r3, [r7, #4]
|
|
8000a2e: 69fa ldr r2, [r7, #28]
|
|
8000a30: 611a str r2, [r3, #16]
|
|
break;
|
|
8000a32: e009 b.n 8000a48 <HAL_GPIO_Init+0x130>
|
|
config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD;
|
|
8000a34: 2308 movs r3, #8
|
|
8000a36: 623b str r3, [r7, #32]
|
|
GPIOx->BRR = ioposition;
|
|
8000a38: 687b ldr r3, [r7, #4]
|
|
8000a3a: 69fa ldr r2, [r7, #28]
|
|
8000a3c: 615a str r2, [r3, #20]
|
|
break;
|
|
8000a3e: e003 b.n 8000a48 <HAL_GPIO_Init+0x130>
|
|
config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG;
|
|
8000a40: 2300 movs r3, #0
|
|
8000a42: 623b str r3, [r7, #32]
|
|
break;
|
|
8000a44: e000 b.n 8000a48 <HAL_GPIO_Init+0x130>
|
|
break;
|
|
8000a46: bf00 nop
|
|
}
|
|
|
|
/* Check if the current bit belongs to first half or last half of the pin count number
|
|
in order to address CRH or CRL register*/
|
|
configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL : &GPIOx->CRH;
|
|
8000a48: 69bb ldr r3, [r7, #24]
|
|
8000a4a: 2bff cmp r3, #255 ; 0xff
|
|
8000a4c: d801 bhi.n 8000a52 <HAL_GPIO_Init+0x13a>
|
|
8000a4e: 687b ldr r3, [r7, #4]
|
|
8000a50: e001 b.n 8000a56 <HAL_GPIO_Init+0x13e>
|
|
8000a52: 687b ldr r3, [r7, #4]
|
|
8000a54: 3304 adds r3, #4
|
|
8000a56: 617b str r3, [r7, #20]
|
|
registeroffset = (iocurrent < GPIO_PIN_8) ? (position << 2u) : ((position - 8u) << 2u);
|
|
8000a58: 69bb ldr r3, [r7, #24]
|
|
8000a5a: 2bff cmp r3, #255 ; 0xff
|
|
8000a5c: d802 bhi.n 8000a64 <HAL_GPIO_Init+0x14c>
|
|
8000a5e: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
8000a60: 009b lsls r3, r3, #2
|
|
8000a62: e002 b.n 8000a6a <HAL_GPIO_Init+0x152>
|
|
8000a64: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
8000a66: 3b08 subs r3, #8
|
|
8000a68: 009b lsls r3, r3, #2
|
|
8000a6a: 613b str r3, [r7, #16]
|
|
|
|
/* Apply the new configuration of the pin to the register */
|
|
MODIFY_REG((*configregister), ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset), (config << registeroffset));
|
|
8000a6c: 697b ldr r3, [r7, #20]
|
|
8000a6e: 681a ldr r2, [r3, #0]
|
|
8000a70: 210f movs r1, #15
|
|
8000a72: 693b ldr r3, [r7, #16]
|
|
8000a74: fa01 f303 lsl.w r3, r1, r3
|
|
8000a78: 43db mvns r3, r3
|
|
8000a7a: 401a ands r2, r3
|
|
8000a7c: 6a39 ldr r1, [r7, #32]
|
|
8000a7e: 693b ldr r3, [r7, #16]
|
|
8000a80: fa01 f303 lsl.w r3, r1, r3
|
|
8000a84: 431a orrs r2, r3
|
|
8000a86: 697b ldr r3, [r7, #20]
|
|
8000a88: 601a str r2, [r3, #0]
|
|
|
|
/*--------------------- EXTI Mode Configuration ------------------------*/
|
|
/* Configure the External Interrupt or event for the current IO */
|
|
if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
|
|
8000a8a: 683b ldr r3, [r7, #0]
|
|
8000a8c: 685b ldr r3, [r3, #4]
|
|
8000a8e: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
|
|
8000a92: 2b00 cmp r3, #0
|
|
8000a94: f000 80b1 beq.w 8000bfa <HAL_GPIO_Init+0x2e2>
|
|
{
|
|
/* Enable AFIO Clock */
|
|
__HAL_RCC_AFIO_CLK_ENABLE();
|
|
8000a98: 4b4d ldr r3, [pc, #308] ; (8000bd0 <HAL_GPIO_Init+0x2b8>)
|
|
8000a9a: 699b ldr r3, [r3, #24]
|
|
8000a9c: 4a4c ldr r2, [pc, #304] ; (8000bd0 <HAL_GPIO_Init+0x2b8>)
|
|
8000a9e: f043 0301 orr.w r3, r3, #1
|
|
8000aa2: 6193 str r3, [r2, #24]
|
|
8000aa4: 4b4a ldr r3, [pc, #296] ; (8000bd0 <HAL_GPIO_Init+0x2b8>)
|
|
8000aa6: 699b ldr r3, [r3, #24]
|
|
8000aa8: f003 0301 and.w r3, r3, #1
|
|
8000aac: 60bb str r3, [r7, #8]
|
|
8000aae: 68bb ldr r3, [r7, #8]
|
|
temp = AFIO->EXTICR[position >> 2u];
|
|
8000ab0: 4a48 ldr r2, [pc, #288] ; (8000bd4 <HAL_GPIO_Init+0x2bc>)
|
|
8000ab2: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
8000ab4: 089b lsrs r3, r3, #2
|
|
8000ab6: 3302 adds r3, #2
|
|
8000ab8: f852 3023 ldr.w r3, [r2, r3, lsl #2]
|
|
8000abc: 60fb str r3, [r7, #12]
|
|
CLEAR_BIT(temp, (0x0Fu) << (4u * (position & 0x03u)));
|
|
8000abe: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
8000ac0: f003 0303 and.w r3, r3, #3
|
|
8000ac4: 009b lsls r3, r3, #2
|
|
8000ac6: 220f movs r2, #15
|
|
8000ac8: fa02 f303 lsl.w r3, r2, r3
|
|
8000acc: 43db mvns r3, r3
|
|
8000ace: 68fa ldr r2, [r7, #12]
|
|
8000ad0: 4013 ands r3, r2
|
|
8000ad2: 60fb str r3, [r7, #12]
|
|
SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4u * (position & 0x03u)));
|
|
8000ad4: 687b ldr r3, [r7, #4]
|
|
8000ad6: 4a40 ldr r2, [pc, #256] ; (8000bd8 <HAL_GPIO_Init+0x2c0>)
|
|
8000ad8: 4293 cmp r3, r2
|
|
8000ada: d013 beq.n 8000b04 <HAL_GPIO_Init+0x1ec>
|
|
8000adc: 687b ldr r3, [r7, #4]
|
|
8000ade: 4a3f ldr r2, [pc, #252] ; (8000bdc <HAL_GPIO_Init+0x2c4>)
|
|
8000ae0: 4293 cmp r3, r2
|
|
8000ae2: d00d beq.n 8000b00 <HAL_GPIO_Init+0x1e8>
|
|
8000ae4: 687b ldr r3, [r7, #4]
|
|
8000ae6: 4a3e ldr r2, [pc, #248] ; (8000be0 <HAL_GPIO_Init+0x2c8>)
|
|
8000ae8: 4293 cmp r3, r2
|
|
8000aea: d007 beq.n 8000afc <HAL_GPIO_Init+0x1e4>
|
|
8000aec: 687b ldr r3, [r7, #4]
|
|
8000aee: 4a3d ldr r2, [pc, #244] ; (8000be4 <HAL_GPIO_Init+0x2cc>)
|
|
8000af0: 4293 cmp r3, r2
|
|
8000af2: d101 bne.n 8000af8 <HAL_GPIO_Init+0x1e0>
|
|
8000af4: 2303 movs r3, #3
|
|
8000af6: e006 b.n 8000b06 <HAL_GPIO_Init+0x1ee>
|
|
8000af8: 2304 movs r3, #4
|
|
8000afa: e004 b.n 8000b06 <HAL_GPIO_Init+0x1ee>
|
|
8000afc: 2302 movs r3, #2
|
|
8000afe: e002 b.n 8000b06 <HAL_GPIO_Init+0x1ee>
|
|
8000b00: 2301 movs r3, #1
|
|
8000b02: e000 b.n 8000b06 <HAL_GPIO_Init+0x1ee>
|
|
8000b04: 2300 movs r3, #0
|
|
8000b06: 6a7a ldr r2, [r7, #36] ; 0x24
|
|
8000b08: f002 0203 and.w r2, r2, #3
|
|
8000b0c: 0092 lsls r2, r2, #2
|
|
8000b0e: 4093 lsls r3, r2
|
|
8000b10: 68fa ldr r2, [r7, #12]
|
|
8000b12: 4313 orrs r3, r2
|
|
8000b14: 60fb str r3, [r7, #12]
|
|
AFIO->EXTICR[position >> 2u] = temp;
|
|
8000b16: 492f ldr r1, [pc, #188] ; (8000bd4 <HAL_GPIO_Init+0x2bc>)
|
|
8000b18: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
8000b1a: 089b lsrs r3, r3, #2
|
|
8000b1c: 3302 adds r3, #2
|
|
8000b1e: 68fa ldr r2, [r7, #12]
|
|
8000b20: f841 2023 str.w r2, [r1, r3, lsl #2]
|
|
|
|
|
|
/* Configure the interrupt mask */
|
|
if ((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
|
|
8000b24: 683b ldr r3, [r7, #0]
|
|
8000b26: 685b ldr r3, [r3, #4]
|
|
8000b28: f403 3380 and.w r3, r3, #65536 ; 0x10000
|
|
8000b2c: 2b00 cmp r3, #0
|
|
8000b2e: d006 beq.n 8000b3e <HAL_GPIO_Init+0x226>
|
|
{
|
|
SET_BIT(EXTI->IMR, iocurrent);
|
|
8000b30: 4b2d ldr r3, [pc, #180] ; (8000be8 <HAL_GPIO_Init+0x2d0>)
|
|
8000b32: 681a ldr r2, [r3, #0]
|
|
8000b34: 492c ldr r1, [pc, #176] ; (8000be8 <HAL_GPIO_Init+0x2d0>)
|
|
8000b36: 69bb ldr r3, [r7, #24]
|
|
8000b38: 4313 orrs r3, r2
|
|
8000b3a: 600b str r3, [r1, #0]
|
|
8000b3c: e006 b.n 8000b4c <HAL_GPIO_Init+0x234>
|
|
}
|
|
else
|
|
{
|
|
CLEAR_BIT(EXTI->IMR, iocurrent);
|
|
8000b3e: 4b2a ldr r3, [pc, #168] ; (8000be8 <HAL_GPIO_Init+0x2d0>)
|
|
8000b40: 681a ldr r2, [r3, #0]
|
|
8000b42: 69bb ldr r3, [r7, #24]
|
|
8000b44: 43db mvns r3, r3
|
|
8000b46: 4928 ldr r1, [pc, #160] ; (8000be8 <HAL_GPIO_Init+0x2d0>)
|
|
8000b48: 4013 ands r3, r2
|
|
8000b4a: 600b str r3, [r1, #0]
|
|
}
|
|
|
|
/* Configure the event mask */
|
|
if ((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
|
|
8000b4c: 683b ldr r3, [r7, #0]
|
|
8000b4e: 685b ldr r3, [r3, #4]
|
|
8000b50: f403 3300 and.w r3, r3, #131072 ; 0x20000
|
|
8000b54: 2b00 cmp r3, #0
|
|
8000b56: d006 beq.n 8000b66 <HAL_GPIO_Init+0x24e>
|
|
{
|
|
SET_BIT(EXTI->EMR, iocurrent);
|
|
8000b58: 4b23 ldr r3, [pc, #140] ; (8000be8 <HAL_GPIO_Init+0x2d0>)
|
|
8000b5a: 685a ldr r2, [r3, #4]
|
|
8000b5c: 4922 ldr r1, [pc, #136] ; (8000be8 <HAL_GPIO_Init+0x2d0>)
|
|
8000b5e: 69bb ldr r3, [r7, #24]
|
|
8000b60: 4313 orrs r3, r2
|
|
8000b62: 604b str r3, [r1, #4]
|
|
8000b64: e006 b.n 8000b74 <HAL_GPIO_Init+0x25c>
|
|
}
|
|
else
|
|
{
|
|
CLEAR_BIT(EXTI->EMR, iocurrent);
|
|
8000b66: 4b20 ldr r3, [pc, #128] ; (8000be8 <HAL_GPIO_Init+0x2d0>)
|
|
8000b68: 685a ldr r2, [r3, #4]
|
|
8000b6a: 69bb ldr r3, [r7, #24]
|
|
8000b6c: 43db mvns r3, r3
|
|
8000b6e: 491e ldr r1, [pc, #120] ; (8000be8 <HAL_GPIO_Init+0x2d0>)
|
|
8000b70: 4013 ands r3, r2
|
|
8000b72: 604b str r3, [r1, #4]
|
|
}
|
|
|
|
/* Enable or disable the rising trigger */
|
|
if ((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
|
|
8000b74: 683b ldr r3, [r7, #0]
|
|
8000b76: 685b ldr r3, [r3, #4]
|
|
8000b78: f403 1380 and.w r3, r3, #1048576 ; 0x100000
|
|
8000b7c: 2b00 cmp r3, #0
|
|
8000b7e: d006 beq.n 8000b8e <HAL_GPIO_Init+0x276>
|
|
{
|
|
SET_BIT(EXTI->RTSR, iocurrent);
|
|
8000b80: 4b19 ldr r3, [pc, #100] ; (8000be8 <HAL_GPIO_Init+0x2d0>)
|
|
8000b82: 689a ldr r2, [r3, #8]
|
|
8000b84: 4918 ldr r1, [pc, #96] ; (8000be8 <HAL_GPIO_Init+0x2d0>)
|
|
8000b86: 69bb ldr r3, [r7, #24]
|
|
8000b88: 4313 orrs r3, r2
|
|
8000b8a: 608b str r3, [r1, #8]
|
|
8000b8c: e006 b.n 8000b9c <HAL_GPIO_Init+0x284>
|
|
}
|
|
else
|
|
{
|
|
CLEAR_BIT(EXTI->RTSR, iocurrent);
|
|
8000b8e: 4b16 ldr r3, [pc, #88] ; (8000be8 <HAL_GPIO_Init+0x2d0>)
|
|
8000b90: 689a ldr r2, [r3, #8]
|
|
8000b92: 69bb ldr r3, [r7, #24]
|
|
8000b94: 43db mvns r3, r3
|
|
8000b96: 4914 ldr r1, [pc, #80] ; (8000be8 <HAL_GPIO_Init+0x2d0>)
|
|
8000b98: 4013 ands r3, r2
|
|
8000b9a: 608b str r3, [r1, #8]
|
|
}
|
|
|
|
/* Enable or disable the falling trigger */
|
|
if ((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
|
|
8000b9c: 683b ldr r3, [r7, #0]
|
|
8000b9e: 685b ldr r3, [r3, #4]
|
|
8000ba0: f403 1300 and.w r3, r3, #2097152 ; 0x200000
|
|
8000ba4: 2b00 cmp r3, #0
|
|
8000ba6: d021 beq.n 8000bec <HAL_GPIO_Init+0x2d4>
|
|
{
|
|
SET_BIT(EXTI->FTSR, iocurrent);
|
|
8000ba8: 4b0f ldr r3, [pc, #60] ; (8000be8 <HAL_GPIO_Init+0x2d0>)
|
|
8000baa: 68da ldr r2, [r3, #12]
|
|
8000bac: 490e ldr r1, [pc, #56] ; (8000be8 <HAL_GPIO_Init+0x2d0>)
|
|
8000bae: 69bb ldr r3, [r7, #24]
|
|
8000bb0: 4313 orrs r3, r2
|
|
8000bb2: 60cb str r3, [r1, #12]
|
|
8000bb4: e021 b.n 8000bfa <HAL_GPIO_Init+0x2e2>
|
|
8000bb6: bf00 nop
|
|
8000bb8: 10320000 .word 0x10320000
|
|
8000bbc: 10310000 .word 0x10310000
|
|
8000bc0: 10220000 .word 0x10220000
|
|
8000bc4: 10210000 .word 0x10210000
|
|
8000bc8: 10120000 .word 0x10120000
|
|
8000bcc: 10110000 .word 0x10110000
|
|
8000bd0: 40021000 .word 0x40021000
|
|
8000bd4: 40010000 .word 0x40010000
|
|
8000bd8: 40010800 .word 0x40010800
|
|
8000bdc: 40010c00 .word 0x40010c00
|
|
8000be0: 40011000 .word 0x40011000
|
|
8000be4: 40011400 .word 0x40011400
|
|
8000be8: 40010400 .word 0x40010400
|
|
}
|
|
else
|
|
{
|
|
CLEAR_BIT(EXTI->FTSR, iocurrent);
|
|
8000bec: 4b0b ldr r3, [pc, #44] ; (8000c1c <HAL_GPIO_Init+0x304>)
|
|
8000bee: 68da ldr r2, [r3, #12]
|
|
8000bf0: 69bb ldr r3, [r7, #24]
|
|
8000bf2: 43db mvns r3, r3
|
|
8000bf4: 4909 ldr r1, [pc, #36] ; (8000c1c <HAL_GPIO_Init+0x304>)
|
|
8000bf6: 4013 ands r3, r2
|
|
8000bf8: 60cb str r3, [r1, #12]
|
|
}
|
|
}
|
|
}
|
|
|
|
position++;
|
|
8000bfa: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
8000bfc: 3301 adds r3, #1
|
|
8000bfe: 627b str r3, [r7, #36] ; 0x24
|
|
while (((GPIO_Init->Pin) >> position) != 0x00u)
|
|
8000c00: 683b ldr r3, [r7, #0]
|
|
8000c02: 681a ldr r2, [r3, #0]
|
|
8000c04: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
8000c06: fa22 f303 lsr.w r3, r2, r3
|
|
8000c0a: 2b00 cmp r3, #0
|
|
8000c0c: f47f ae8e bne.w 800092c <HAL_GPIO_Init+0x14>
|
|
}
|
|
}
|
|
8000c10: bf00 nop
|
|
8000c12: bf00 nop
|
|
8000c14: 372c adds r7, #44 ; 0x2c
|
|
8000c16: 46bd mov sp, r7
|
|
8000c18: bc80 pop {r7}
|
|
8000c1a: 4770 bx lr
|
|
8000c1c: 40010400 .word 0x40010400
|
|
|
|
08000c20 <HAL_RCC_OscConfig>:
|
|
* supported by this macro. User should request a transition to HSE Off
|
|
* first and then HSE On or HSE Bypass.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
|
|
{
|
|
8000c20: b580 push {r7, lr}
|
|
8000c22: b086 sub sp, #24
|
|
8000c24: af00 add r7, sp, #0
|
|
8000c26: 6078 str r0, [r7, #4]
|
|
uint32_t tickstart;
|
|
uint32_t pll_config;
|
|
|
|
/* Check Null pointer */
|
|
if (RCC_OscInitStruct == NULL)
|
|
8000c28: 687b ldr r3, [r7, #4]
|
|
8000c2a: 2b00 cmp r3, #0
|
|
8000c2c: d101 bne.n 8000c32 <HAL_RCC_OscConfig+0x12>
|
|
{
|
|
return HAL_ERROR;
|
|
8000c2e: 2301 movs r3, #1
|
|
8000c30: e272 b.n 8001118 <HAL_RCC_OscConfig+0x4f8>
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
|
|
|
|
/*------------------------------- HSE Configuration ------------------------*/
|
|
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
|
|
8000c32: 687b ldr r3, [r7, #4]
|
|
8000c34: 681b ldr r3, [r3, #0]
|
|
8000c36: f003 0301 and.w r3, r3, #1
|
|
8000c3a: 2b00 cmp r3, #0
|
|
8000c3c: f000 8087 beq.w 8000d4e <HAL_RCC_OscConfig+0x12e>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
|
|
|
|
/* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
|
|
if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)
|
|
8000c40: 4b92 ldr r3, [pc, #584] ; (8000e8c <HAL_RCC_OscConfig+0x26c>)
|
|
8000c42: 685b ldr r3, [r3, #4]
|
|
8000c44: f003 030c and.w r3, r3, #12
|
|
8000c48: 2b04 cmp r3, #4
|
|
8000c4a: d00c beq.n 8000c66 <HAL_RCC_OscConfig+0x46>
|
|
|| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE)))
|
|
8000c4c: 4b8f ldr r3, [pc, #572] ; (8000e8c <HAL_RCC_OscConfig+0x26c>)
|
|
8000c4e: 685b ldr r3, [r3, #4]
|
|
8000c50: f003 030c and.w r3, r3, #12
|
|
8000c54: 2b08 cmp r3, #8
|
|
8000c56: d112 bne.n 8000c7e <HAL_RCC_OscConfig+0x5e>
|
|
8000c58: 4b8c ldr r3, [pc, #560] ; (8000e8c <HAL_RCC_OscConfig+0x26c>)
|
|
8000c5a: 685b ldr r3, [r3, #4]
|
|
8000c5c: f403 3380 and.w r3, r3, #65536 ; 0x10000
|
|
8000c60: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
|
|
8000c64: d10b bne.n 8000c7e <HAL_RCC_OscConfig+0x5e>
|
|
{
|
|
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
|
|
8000c66: 4b89 ldr r3, [pc, #548] ; (8000e8c <HAL_RCC_OscConfig+0x26c>)
|
|
8000c68: 681b ldr r3, [r3, #0]
|
|
8000c6a: f403 3300 and.w r3, r3, #131072 ; 0x20000
|
|
8000c6e: 2b00 cmp r3, #0
|
|
8000c70: d06c beq.n 8000d4c <HAL_RCC_OscConfig+0x12c>
|
|
8000c72: 687b ldr r3, [r7, #4]
|
|
8000c74: 685b ldr r3, [r3, #4]
|
|
8000c76: 2b00 cmp r3, #0
|
|
8000c78: d168 bne.n 8000d4c <HAL_RCC_OscConfig+0x12c>
|
|
{
|
|
return HAL_ERROR;
|
|
8000c7a: 2301 movs r3, #1
|
|
8000c7c: e24c b.n 8001118 <HAL_RCC_OscConfig+0x4f8>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Set the new HSE configuration ---------------------------------------*/
|
|
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
|
|
8000c7e: 687b ldr r3, [r7, #4]
|
|
8000c80: 685b ldr r3, [r3, #4]
|
|
8000c82: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
|
|
8000c86: d106 bne.n 8000c96 <HAL_RCC_OscConfig+0x76>
|
|
8000c88: 4b80 ldr r3, [pc, #512] ; (8000e8c <HAL_RCC_OscConfig+0x26c>)
|
|
8000c8a: 681b ldr r3, [r3, #0]
|
|
8000c8c: 4a7f ldr r2, [pc, #508] ; (8000e8c <HAL_RCC_OscConfig+0x26c>)
|
|
8000c8e: f443 3380 orr.w r3, r3, #65536 ; 0x10000
|
|
8000c92: 6013 str r3, [r2, #0]
|
|
8000c94: e02e b.n 8000cf4 <HAL_RCC_OscConfig+0xd4>
|
|
8000c96: 687b ldr r3, [r7, #4]
|
|
8000c98: 685b ldr r3, [r3, #4]
|
|
8000c9a: 2b00 cmp r3, #0
|
|
8000c9c: d10c bne.n 8000cb8 <HAL_RCC_OscConfig+0x98>
|
|
8000c9e: 4b7b ldr r3, [pc, #492] ; (8000e8c <HAL_RCC_OscConfig+0x26c>)
|
|
8000ca0: 681b ldr r3, [r3, #0]
|
|
8000ca2: 4a7a ldr r2, [pc, #488] ; (8000e8c <HAL_RCC_OscConfig+0x26c>)
|
|
8000ca4: f423 3380 bic.w r3, r3, #65536 ; 0x10000
|
|
8000ca8: 6013 str r3, [r2, #0]
|
|
8000caa: 4b78 ldr r3, [pc, #480] ; (8000e8c <HAL_RCC_OscConfig+0x26c>)
|
|
8000cac: 681b ldr r3, [r3, #0]
|
|
8000cae: 4a77 ldr r2, [pc, #476] ; (8000e8c <HAL_RCC_OscConfig+0x26c>)
|
|
8000cb0: f423 2380 bic.w r3, r3, #262144 ; 0x40000
|
|
8000cb4: 6013 str r3, [r2, #0]
|
|
8000cb6: e01d b.n 8000cf4 <HAL_RCC_OscConfig+0xd4>
|
|
8000cb8: 687b ldr r3, [r7, #4]
|
|
8000cba: 685b ldr r3, [r3, #4]
|
|
8000cbc: f5b3 2fa0 cmp.w r3, #327680 ; 0x50000
|
|
8000cc0: d10c bne.n 8000cdc <HAL_RCC_OscConfig+0xbc>
|
|
8000cc2: 4b72 ldr r3, [pc, #456] ; (8000e8c <HAL_RCC_OscConfig+0x26c>)
|
|
8000cc4: 681b ldr r3, [r3, #0]
|
|
8000cc6: 4a71 ldr r2, [pc, #452] ; (8000e8c <HAL_RCC_OscConfig+0x26c>)
|
|
8000cc8: f443 2380 orr.w r3, r3, #262144 ; 0x40000
|
|
8000ccc: 6013 str r3, [r2, #0]
|
|
8000cce: 4b6f ldr r3, [pc, #444] ; (8000e8c <HAL_RCC_OscConfig+0x26c>)
|
|
8000cd0: 681b ldr r3, [r3, #0]
|
|
8000cd2: 4a6e ldr r2, [pc, #440] ; (8000e8c <HAL_RCC_OscConfig+0x26c>)
|
|
8000cd4: f443 3380 orr.w r3, r3, #65536 ; 0x10000
|
|
8000cd8: 6013 str r3, [r2, #0]
|
|
8000cda: e00b b.n 8000cf4 <HAL_RCC_OscConfig+0xd4>
|
|
8000cdc: 4b6b ldr r3, [pc, #428] ; (8000e8c <HAL_RCC_OscConfig+0x26c>)
|
|
8000cde: 681b ldr r3, [r3, #0]
|
|
8000ce0: 4a6a ldr r2, [pc, #424] ; (8000e8c <HAL_RCC_OscConfig+0x26c>)
|
|
8000ce2: f423 3380 bic.w r3, r3, #65536 ; 0x10000
|
|
8000ce6: 6013 str r3, [r2, #0]
|
|
8000ce8: 4b68 ldr r3, [pc, #416] ; (8000e8c <HAL_RCC_OscConfig+0x26c>)
|
|
8000cea: 681b ldr r3, [r3, #0]
|
|
8000cec: 4a67 ldr r2, [pc, #412] ; (8000e8c <HAL_RCC_OscConfig+0x26c>)
|
|
8000cee: f423 2380 bic.w r3, r3, #262144 ; 0x40000
|
|
8000cf2: 6013 str r3, [r2, #0]
|
|
|
|
|
|
/* Check the HSE State */
|
|
if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
|
|
8000cf4: 687b ldr r3, [r7, #4]
|
|
8000cf6: 685b ldr r3, [r3, #4]
|
|
8000cf8: 2b00 cmp r3, #0
|
|
8000cfa: d013 beq.n 8000d24 <HAL_RCC_OscConfig+0x104>
|
|
{
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
8000cfc: f7ff fcfa bl 80006f4 <HAL_GetTick>
|
|
8000d00: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till HSE is ready */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
|
|
8000d02: e008 b.n 8000d16 <HAL_RCC_OscConfig+0xf6>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
|
|
8000d04: f7ff fcf6 bl 80006f4 <HAL_GetTick>
|
|
8000d08: 4602 mov r2, r0
|
|
8000d0a: 693b ldr r3, [r7, #16]
|
|
8000d0c: 1ad3 subs r3, r2, r3
|
|
8000d0e: 2b64 cmp r3, #100 ; 0x64
|
|
8000d10: d901 bls.n 8000d16 <HAL_RCC_OscConfig+0xf6>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8000d12: 2303 movs r3, #3
|
|
8000d14: e200 b.n 8001118 <HAL_RCC_OscConfig+0x4f8>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
|
|
8000d16: 4b5d ldr r3, [pc, #372] ; (8000e8c <HAL_RCC_OscConfig+0x26c>)
|
|
8000d18: 681b ldr r3, [r3, #0]
|
|
8000d1a: f403 3300 and.w r3, r3, #131072 ; 0x20000
|
|
8000d1e: 2b00 cmp r3, #0
|
|
8000d20: d0f0 beq.n 8000d04 <HAL_RCC_OscConfig+0xe4>
|
|
8000d22: e014 b.n 8000d4e <HAL_RCC_OscConfig+0x12e>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
8000d24: f7ff fce6 bl 80006f4 <HAL_GetTick>
|
|
8000d28: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till HSE is disabled */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
|
|
8000d2a: e008 b.n 8000d3e <HAL_RCC_OscConfig+0x11e>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
|
|
8000d2c: f7ff fce2 bl 80006f4 <HAL_GetTick>
|
|
8000d30: 4602 mov r2, r0
|
|
8000d32: 693b ldr r3, [r7, #16]
|
|
8000d34: 1ad3 subs r3, r2, r3
|
|
8000d36: 2b64 cmp r3, #100 ; 0x64
|
|
8000d38: d901 bls.n 8000d3e <HAL_RCC_OscConfig+0x11e>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8000d3a: 2303 movs r3, #3
|
|
8000d3c: e1ec b.n 8001118 <HAL_RCC_OscConfig+0x4f8>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
|
|
8000d3e: 4b53 ldr r3, [pc, #332] ; (8000e8c <HAL_RCC_OscConfig+0x26c>)
|
|
8000d40: 681b ldr r3, [r3, #0]
|
|
8000d42: f403 3300 and.w r3, r3, #131072 ; 0x20000
|
|
8000d46: 2b00 cmp r3, #0
|
|
8000d48: d1f0 bne.n 8000d2c <HAL_RCC_OscConfig+0x10c>
|
|
8000d4a: e000 b.n 8000d4e <HAL_RCC_OscConfig+0x12e>
|
|
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
|
|
8000d4c: bf00 nop
|
|
}
|
|
}
|
|
}
|
|
}
|
|
/*----------------------------- HSI Configuration --------------------------*/
|
|
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
|
|
8000d4e: 687b ldr r3, [r7, #4]
|
|
8000d50: 681b ldr r3, [r3, #0]
|
|
8000d52: f003 0302 and.w r3, r3, #2
|
|
8000d56: 2b00 cmp r3, #0
|
|
8000d58: d063 beq.n 8000e22 <HAL_RCC_OscConfig+0x202>
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
|
|
assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
|
|
|
|
/* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
|
|
if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)
|
|
8000d5a: 4b4c ldr r3, [pc, #304] ; (8000e8c <HAL_RCC_OscConfig+0x26c>)
|
|
8000d5c: 685b ldr r3, [r3, #4]
|
|
8000d5e: f003 030c and.w r3, r3, #12
|
|
8000d62: 2b00 cmp r3, #0
|
|
8000d64: d00b beq.n 8000d7e <HAL_RCC_OscConfig+0x15e>
|
|
|| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI_DIV2)))
|
|
8000d66: 4b49 ldr r3, [pc, #292] ; (8000e8c <HAL_RCC_OscConfig+0x26c>)
|
|
8000d68: 685b ldr r3, [r3, #4]
|
|
8000d6a: f003 030c and.w r3, r3, #12
|
|
8000d6e: 2b08 cmp r3, #8
|
|
8000d70: d11c bne.n 8000dac <HAL_RCC_OscConfig+0x18c>
|
|
8000d72: 4b46 ldr r3, [pc, #280] ; (8000e8c <HAL_RCC_OscConfig+0x26c>)
|
|
8000d74: 685b ldr r3, [r3, #4]
|
|
8000d76: f403 3380 and.w r3, r3, #65536 ; 0x10000
|
|
8000d7a: 2b00 cmp r3, #0
|
|
8000d7c: d116 bne.n 8000dac <HAL_RCC_OscConfig+0x18c>
|
|
{
|
|
/* When HSI is used as system clock it will not disabled */
|
|
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
|
|
8000d7e: 4b43 ldr r3, [pc, #268] ; (8000e8c <HAL_RCC_OscConfig+0x26c>)
|
|
8000d80: 681b ldr r3, [r3, #0]
|
|
8000d82: f003 0302 and.w r3, r3, #2
|
|
8000d86: 2b00 cmp r3, #0
|
|
8000d88: d005 beq.n 8000d96 <HAL_RCC_OscConfig+0x176>
|
|
8000d8a: 687b ldr r3, [r7, #4]
|
|
8000d8c: 691b ldr r3, [r3, #16]
|
|
8000d8e: 2b01 cmp r3, #1
|
|
8000d90: d001 beq.n 8000d96 <HAL_RCC_OscConfig+0x176>
|
|
{
|
|
return HAL_ERROR;
|
|
8000d92: 2301 movs r3, #1
|
|
8000d94: e1c0 b.n 8001118 <HAL_RCC_OscConfig+0x4f8>
|
|
}
|
|
/* Otherwise, just the calibration is allowed */
|
|
else
|
|
{
|
|
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
|
|
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
|
|
8000d96: 4b3d ldr r3, [pc, #244] ; (8000e8c <HAL_RCC_OscConfig+0x26c>)
|
|
8000d98: 681b ldr r3, [r3, #0]
|
|
8000d9a: f023 02f8 bic.w r2, r3, #248 ; 0xf8
|
|
8000d9e: 687b ldr r3, [r7, #4]
|
|
8000da0: 695b ldr r3, [r3, #20]
|
|
8000da2: 00db lsls r3, r3, #3
|
|
8000da4: 4939 ldr r1, [pc, #228] ; (8000e8c <HAL_RCC_OscConfig+0x26c>)
|
|
8000da6: 4313 orrs r3, r2
|
|
8000da8: 600b str r3, [r1, #0]
|
|
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
|
|
8000daa: e03a b.n 8000e22 <HAL_RCC_OscConfig+0x202>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Check the HSI State */
|
|
if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
|
|
8000dac: 687b ldr r3, [r7, #4]
|
|
8000dae: 691b ldr r3, [r3, #16]
|
|
8000db0: 2b00 cmp r3, #0
|
|
8000db2: d020 beq.n 8000df6 <HAL_RCC_OscConfig+0x1d6>
|
|
{
|
|
/* Enable the Internal High Speed oscillator (HSI). */
|
|
__HAL_RCC_HSI_ENABLE();
|
|
8000db4: 4b36 ldr r3, [pc, #216] ; (8000e90 <HAL_RCC_OscConfig+0x270>)
|
|
8000db6: 2201 movs r2, #1
|
|
8000db8: 601a str r2, [r3, #0]
|
|
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
8000dba: f7ff fc9b bl 80006f4 <HAL_GetTick>
|
|
8000dbe: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till HSI is ready */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
|
|
8000dc0: e008 b.n 8000dd4 <HAL_RCC_OscConfig+0x1b4>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
|
|
8000dc2: f7ff fc97 bl 80006f4 <HAL_GetTick>
|
|
8000dc6: 4602 mov r2, r0
|
|
8000dc8: 693b ldr r3, [r7, #16]
|
|
8000dca: 1ad3 subs r3, r2, r3
|
|
8000dcc: 2b02 cmp r3, #2
|
|
8000dce: d901 bls.n 8000dd4 <HAL_RCC_OscConfig+0x1b4>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8000dd0: 2303 movs r3, #3
|
|
8000dd2: e1a1 b.n 8001118 <HAL_RCC_OscConfig+0x4f8>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
|
|
8000dd4: 4b2d ldr r3, [pc, #180] ; (8000e8c <HAL_RCC_OscConfig+0x26c>)
|
|
8000dd6: 681b ldr r3, [r3, #0]
|
|
8000dd8: f003 0302 and.w r3, r3, #2
|
|
8000ddc: 2b00 cmp r3, #0
|
|
8000dde: d0f0 beq.n 8000dc2 <HAL_RCC_OscConfig+0x1a2>
|
|
}
|
|
}
|
|
|
|
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
|
|
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
|
|
8000de0: 4b2a ldr r3, [pc, #168] ; (8000e8c <HAL_RCC_OscConfig+0x26c>)
|
|
8000de2: 681b ldr r3, [r3, #0]
|
|
8000de4: f023 02f8 bic.w r2, r3, #248 ; 0xf8
|
|
8000de8: 687b ldr r3, [r7, #4]
|
|
8000dea: 695b ldr r3, [r3, #20]
|
|
8000dec: 00db lsls r3, r3, #3
|
|
8000dee: 4927 ldr r1, [pc, #156] ; (8000e8c <HAL_RCC_OscConfig+0x26c>)
|
|
8000df0: 4313 orrs r3, r2
|
|
8000df2: 600b str r3, [r1, #0]
|
|
8000df4: e015 b.n 8000e22 <HAL_RCC_OscConfig+0x202>
|
|
}
|
|
else
|
|
{
|
|
/* Disable the Internal High Speed oscillator (HSI). */
|
|
__HAL_RCC_HSI_DISABLE();
|
|
8000df6: 4b26 ldr r3, [pc, #152] ; (8000e90 <HAL_RCC_OscConfig+0x270>)
|
|
8000df8: 2200 movs r2, #0
|
|
8000dfa: 601a str r2, [r3, #0]
|
|
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
8000dfc: f7ff fc7a bl 80006f4 <HAL_GetTick>
|
|
8000e00: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till HSI is disabled */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
|
|
8000e02: e008 b.n 8000e16 <HAL_RCC_OscConfig+0x1f6>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
|
|
8000e04: f7ff fc76 bl 80006f4 <HAL_GetTick>
|
|
8000e08: 4602 mov r2, r0
|
|
8000e0a: 693b ldr r3, [r7, #16]
|
|
8000e0c: 1ad3 subs r3, r2, r3
|
|
8000e0e: 2b02 cmp r3, #2
|
|
8000e10: d901 bls.n 8000e16 <HAL_RCC_OscConfig+0x1f6>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8000e12: 2303 movs r3, #3
|
|
8000e14: e180 b.n 8001118 <HAL_RCC_OscConfig+0x4f8>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
|
|
8000e16: 4b1d ldr r3, [pc, #116] ; (8000e8c <HAL_RCC_OscConfig+0x26c>)
|
|
8000e18: 681b ldr r3, [r3, #0]
|
|
8000e1a: f003 0302 and.w r3, r3, #2
|
|
8000e1e: 2b00 cmp r3, #0
|
|
8000e20: d1f0 bne.n 8000e04 <HAL_RCC_OscConfig+0x1e4>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
/*------------------------------ LSI Configuration -------------------------*/
|
|
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
|
|
8000e22: 687b ldr r3, [r7, #4]
|
|
8000e24: 681b ldr r3, [r3, #0]
|
|
8000e26: f003 0308 and.w r3, r3, #8
|
|
8000e2a: 2b00 cmp r3, #0
|
|
8000e2c: d03a beq.n 8000ea4 <HAL_RCC_OscConfig+0x284>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
|
|
|
|
/* Check the LSI State */
|
|
if (RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
|
|
8000e2e: 687b ldr r3, [r7, #4]
|
|
8000e30: 699b ldr r3, [r3, #24]
|
|
8000e32: 2b00 cmp r3, #0
|
|
8000e34: d019 beq.n 8000e6a <HAL_RCC_OscConfig+0x24a>
|
|
{
|
|
/* Enable the Internal Low Speed oscillator (LSI). */
|
|
__HAL_RCC_LSI_ENABLE();
|
|
8000e36: 4b17 ldr r3, [pc, #92] ; (8000e94 <HAL_RCC_OscConfig+0x274>)
|
|
8000e38: 2201 movs r2, #1
|
|
8000e3a: 601a str r2, [r3, #0]
|
|
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
8000e3c: f7ff fc5a bl 80006f4 <HAL_GetTick>
|
|
8000e40: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till LSI is ready */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
|
|
8000e42: e008 b.n 8000e56 <HAL_RCC_OscConfig+0x236>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
|
|
8000e44: f7ff fc56 bl 80006f4 <HAL_GetTick>
|
|
8000e48: 4602 mov r2, r0
|
|
8000e4a: 693b ldr r3, [r7, #16]
|
|
8000e4c: 1ad3 subs r3, r2, r3
|
|
8000e4e: 2b02 cmp r3, #2
|
|
8000e50: d901 bls.n 8000e56 <HAL_RCC_OscConfig+0x236>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8000e52: 2303 movs r3, #3
|
|
8000e54: e160 b.n 8001118 <HAL_RCC_OscConfig+0x4f8>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
|
|
8000e56: 4b0d ldr r3, [pc, #52] ; (8000e8c <HAL_RCC_OscConfig+0x26c>)
|
|
8000e58: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
8000e5a: f003 0302 and.w r3, r3, #2
|
|
8000e5e: 2b00 cmp r3, #0
|
|
8000e60: d0f0 beq.n 8000e44 <HAL_RCC_OscConfig+0x224>
|
|
}
|
|
}
|
|
/* To have a fully stabilized clock in the specified range, a software delay of 1ms
|
|
should be added.*/
|
|
RCC_Delay(1);
|
|
8000e62: 2001 movs r0, #1
|
|
8000e64: f000 fad8 bl 8001418 <RCC_Delay>
|
|
8000e68: e01c b.n 8000ea4 <HAL_RCC_OscConfig+0x284>
|
|
}
|
|
else
|
|
{
|
|
/* Disable the Internal Low Speed oscillator (LSI). */
|
|
__HAL_RCC_LSI_DISABLE();
|
|
8000e6a: 4b0a ldr r3, [pc, #40] ; (8000e94 <HAL_RCC_OscConfig+0x274>)
|
|
8000e6c: 2200 movs r2, #0
|
|
8000e6e: 601a str r2, [r3, #0]
|
|
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
8000e70: f7ff fc40 bl 80006f4 <HAL_GetTick>
|
|
8000e74: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till LSI is disabled */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
|
|
8000e76: e00f b.n 8000e98 <HAL_RCC_OscConfig+0x278>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
|
|
8000e78: f7ff fc3c bl 80006f4 <HAL_GetTick>
|
|
8000e7c: 4602 mov r2, r0
|
|
8000e7e: 693b ldr r3, [r7, #16]
|
|
8000e80: 1ad3 subs r3, r2, r3
|
|
8000e82: 2b02 cmp r3, #2
|
|
8000e84: d908 bls.n 8000e98 <HAL_RCC_OscConfig+0x278>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8000e86: 2303 movs r3, #3
|
|
8000e88: e146 b.n 8001118 <HAL_RCC_OscConfig+0x4f8>
|
|
8000e8a: bf00 nop
|
|
8000e8c: 40021000 .word 0x40021000
|
|
8000e90: 42420000 .word 0x42420000
|
|
8000e94: 42420480 .word 0x42420480
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
|
|
8000e98: 4b92 ldr r3, [pc, #584] ; (80010e4 <HAL_RCC_OscConfig+0x4c4>)
|
|
8000e9a: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
8000e9c: f003 0302 and.w r3, r3, #2
|
|
8000ea0: 2b00 cmp r3, #0
|
|
8000ea2: d1e9 bne.n 8000e78 <HAL_RCC_OscConfig+0x258>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
/*------------------------------ LSE Configuration -------------------------*/
|
|
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
|
|
8000ea4: 687b ldr r3, [r7, #4]
|
|
8000ea6: 681b ldr r3, [r3, #0]
|
|
8000ea8: f003 0304 and.w r3, r3, #4
|
|
8000eac: 2b00 cmp r3, #0
|
|
8000eae: f000 80a6 beq.w 8000ffe <HAL_RCC_OscConfig+0x3de>
|
|
{
|
|
FlagStatus pwrclkchanged = RESET;
|
|
8000eb2: 2300 movs r3, #0
|
|
8000eb4: 75fb strb r3, [r7, #23]
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
|
|
|
|
/* Update LSE configuration in Backup Domain control register */
|
|
/* Requires to enable write access to Backup Domain of necessary */
|
|
if (__HAL_RCC_PWR_IS_CLK_DISABLED())
|
|
8000eb6: 4b8b ldr r3, [pc, #556] ; (80010e4 <HAL_RCC_OscConfig+0x4c4>)
|
|
8000eb8: 69db ldr r3, [r3, #28]
|
|
8000eba: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
|
|
8000ebe: 2b00 cmp r3, #0
|
|
8000ec0: d10d bne.n 8000ede <HAL_RCC_OscConfig+0x2be>
|
|
{
|
|
__HAL_RCC_PWR_CLK_ENABLE();
|
|
8000ec2: 4b88 ldr r3, [pc, #544] ; (80010e4 <HAL_RCC_OscConfig+0x4c4>)
|
|
8000ec4: 69db ldr r3, [r3, #28]
|
|
8000ec6: 4a87 ldr r2, [pc, #540] ; (80010e4 <HAL_RCC_OscConfig+0x4c4>)
|
|
8000ec8: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
|
|
8000ecc: 61d3 str r3, [r2, #28]
|
|
8000ece: 4b85 ldr r3, [pc, #532] ; (80010e4 <HAL_RCC_OscConfig+0x4c4>)
|
|
8000ed0: 69db ldr r3, [r3, #28]
|
|
8000ed2: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
|
|
8000ed6: 60bb str r3, [r7, #8]
|
|
8000ed8: 68bb ldr r3, [r7, #8]
|
|
pwrclkchanged = SET;
|
|
8000eda: 2301 movs r3, #1
|
|
8000edc: 75fb strb r3, [r7, #23]
|
|
}
|
|
|
|
if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
|
|
8000ede: 4b82 ldr r3, [pc, #520] ; (80010e8 <HAL_RCC_OscConfig+0x4c8>)
|
|
8000ee0: 681b ldr r3, [r3, #0]
|
|
8000ee2: f403 7380 and.w r3, r3, #256 ; 0x100
|
|
8000ee6: 2b00 cmp r3, #0
|
|
8000ee8: d118 bne.n 8000f1c <HAL_RCC_OscConfig+0x2fc>
|
|
{
|
|
/* Enable write access to Backup domain */
|
|
SET_BIT(PWR->CR, PWR_CR_DBP);
|
|
8000eea: 4b7f ldr r3, [pc, #508] ; (80010e8 <HAL_RCC_OscConfig+0x4c8>)
|
|
8000eec: 681b ldr r3, [r3, #0]
|
|
8000eee: 4a7e ldr r2, [pc, #504] ; (80010e8 <HAL_RCC_OscConfig+0x4c8>)
|
|
8000ef0: f443 7380 orr.w r3, r3, #256 ; 0x100
|
|
8000ef4: 6013 str r3, [r2, #0]
|
|
|
|
/* Wait for Backup domain Write protection disable */
|
|
tickstart = HAL_GetTick();
|
|
8000ef6: f7ff fbfd bl 80006f4 <HAL_GetTick>
|
|
8000efa: 6138 str r0, [r7, #16]
|
|
|
|
while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
|
|
8000efc: e008 b.n 8000f10 <HAL_RCC_OscConfig+0x2f0>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
|
|
8000efe: f7ff fbf9 bl 80006f4 <HAL_GetTick>
|
|
8000f02: 4602 mov r2, r0
|
|
8000f04: 693b ldr r3, [r7, #16]
|
|
8000f06: 1ad3 subs r3, r2, r3
|
|
8000f08: 2b64 cmp r3, #100 ; 0x64
|
|
8000f0a: d901 bls.n 8000f10 <HAL_RCC_OscConfig+0x2f0>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8000f0c: 2303 movs r3, #3
|
|
8000f0e: e103 b.n 8001118 <HAL_RCC_OscConfig+0x4f8>
|
|
while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
|
|
8000f10: 4b75 ldr r3, [pc, #468] ; (80010e8 <HAL_RCC_OscConfig+0x4c8>)
|
|
8000f12: 681b ldr r3, [r3, #0]
|
|
8000f14: f403 7380 and.w r3, r3, #256 ; 0x100
|
|
8000f18: 2b00 cmp r3, #0
|
|
8000f1a: d0f0 beq.n 8000efe <HAL_RCC_OscConfig+0x2de>
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Set the new LSE configuration -----------------------------------------*/
|
|
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
|
|
8000f1c: 687b ldr r3, [r7, #4]
|
|
8000f1e: 68db ldr r3, [r3, #12]
|
|
8000f20: 2b01 cmp r3, #1
|
|
8000f22: d106 bne.n 8000f32 <HAL_RCC_OscConfig+0x312>
|
|
8000f24: 4b6f ldr r3, [pc, #444] ; (80010e4 <HAL_RCC_OscConfig+0x4c4>)
|
|
8000f26: 6a1b ldr r3, [r3, #32]
|
|
8000f28: 4a6e ldr r2, [pc, #440] ; (80010e4 <HAL_RCC_OscConfig+0x4c4>)
|
|
8000f2a: f043 0301 orr.w r3, r3, #1
|
|
8000f2e: 6213 str r3, [r2, #32]
|
|
8000f30: e02d b.n 8000f8e <HAL_RCC_OscConfig+0x36e>
|
|
8000f32: 687b ldr r3, [r7, #4]
|
|
8000f34: 68db ldr r3, [r3, #12]
|
|
8000f36: 2b00 cmp r3, #0
|
|
8000f38: d10c bne.n 8000f54 <HAL_RCC_OscConfig+0x334>
|
|
8000f3a: 4b6a ldr r3, [pc, #424] ; (80010e4 <HAL_RCC_OscConfig+0x4c4>)
|
|
8000f3c: 6a1b ldr r3, [r3, #32]
|
|
8000f3e: 4a69 ldr r2, [pc, #420] ; (80010e4 <HAL_RCC_OscConfig+0x4c4>)
|
|
8000f40: f023 0301 bic.w r3, r3, #1
|
|
8000f44: 6213 str r3, [r2, #32]
|
|
8000f46: 4b67 ldr r3, [pc, #412] ; (80010e4 <HAL_RCC_OscConfig+0x4c4>)
|
|
8000f48: 6a1b ldr r3, [r3, #32]
|
|
8000f4a: 4a66 ldr r2, [pc, #408] ; (80010e4 <HAL_RCC_OscConfig+0x4c4>)
|
|
8000f4c: f023 0304 bic.w r3, r3, #4
|
|
8000f50: 6213 str r3, [r2, #32]
|
|
8000f52: e01c b.n 8000f8e <HAL_RCC_OscConfig+0x36e>
|
|
8000f54: 687b ldr r3, [r7, #4]
|
|
8000f56: 68db ldr r3, [r3, #12]
|
|
8000f58: 2b05 cmp r3, #5
|
|
8000f5a: d10c bne.n 8000f76 <HAL_RCC_OscConfig+0x356>
|
|
8000f5c: 4b61 ldr r3, [pc, #388] ; (80010e4 <HAL_RCC_OscConfig+0x4c4>)
|
|
8000f5e: 6a1b ldr r3, [r3, #32]
|
|
8000f60: 4a60 ldr r2, [pc, #384] ; (80010e4 <HAL_RCC_OscConfig+0x4c4>)
|
|
8000f62: f043 0304 orr.w r3, r3, #4
|
|
8000f66: 6213 str r3, [r2, #32]
|
|
8000f68: 4b5e ldr r3, [pc, #376] ; (80010e4 <HAL_RCC_OscConfig+0x4c4>)
|
|
8000f6a: 6a1b ldr r3, [r3, #32]
|
|
8000f6c: 4a5d ldr r2, [pc, #372] ; (80010e4 <HAL_RCC_OscConfig+0x4c4>)
|
|
8000f6e: f043 0301 orr.w r3, r3, #1
|
|
8000f72: 6213 str r3, [r2, #32]
|
|
8000f74: e00b b.n 8000f8e <HAL_RCC_OscConfig+0x36e>
|
|
8000f76: 4b5b ldr r3, [pc, #364] ; (80010e4 <HAL_RCC_OscConfig+0x4c4>)
|
|
8000f78: 6a1b ldr r3, [r3, #32]
|
|
8000f7a: 4a5a ldr r2, [pc, #360] ; (80010e4 <HAL_RCC_OscConfig+0x4c4>)
|
|
8000f7c: f023 0301 bic.w r3, r3, #1
|
|
8000f80: 6213 str r3, [r2, #32]
|
|
8000f82: 4b58 ldr r3, [pc, #352] ; (80010e4 <HAL_RCC_OscConfig+0x4c4>)
|
|
8000f84: 6a1b ldr r3, [r3, #32]
|
|
8000f86: 4a57 ldr r2, [pc, #348] ; (80010e4 <HAL_RCC_OscConfig+0x4c4>)
|
|
8000f88: f023 0304 bic.w r3, r3, #4
|
|
8000f8c: 6213 str r3, [r2, #32]
|
|
/* Check the LSE State */
|
|
if (RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
|
|
8000f8e: 687b ldr r3, [r7, #4]
|
|
8000f90: 68db ldr r3, [r3, #12]
|
|
8000f92: 2b00 cmp r3, #0
|
|
8000f94: d015 beq.n 8000fc2 <HAL_RCC_OscConfig+0x3a2>
|
|
{
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
8000f96: f7ff fbad bl 80006f4 <HAL_GetTick>
|
|
8000f9a: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till LSE is ready */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
|
|
8000f9c: e00a b.n 8000fb4 <HAL_RCC_OscConfig+0x394>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
|
|
8000f9e: f7ff fba9 bl 80006f4 <HAL_GetTick>
|
|
8000fa2: 4602 mov r2, r0
|
|
8000fa4: 693b ldr r3, [r7, #16]
|
|
8000fa6: 1ad3 subs r3, r2, r3
|
|
8000fa8: f241 3288 movw r2, #5000 ; 0x1388
|
|
8000fac: 4293 cmp r3, r2
|
|
8000fae: d901 bls.n 8000fb4 <HAL_RCC_OscConfig+0x394>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8000fb0: 2303 movs r3, #3
|
|
8000fb2: e0b1 b.n 8001118 <HAL_RCC_OscConfig+0x4f8>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
|
|
8000fb4: 4b4b ldr r3, [pc, #300] ; (80010e4 <HAL_RCC_OscConfig+0x4c4>)
|
|
8000fb6: 6a1b ldr r3, [r3, #32]
|
|
8000fb8: f003 0302 and.w r3, r3, #2
|
|
8000fbc: 2b00 cmp r3, #0
|
|
8000fbe: d0ee beq.n 8000f9e <HAL_RCC_OscConfig+0x37e>
|
|
8000fc0: e014 b.n 8000fec <HAL_RCC_OscConfig+0x3cc>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
8000fc2: f7ff fb97 bl 80006f4 <HAL_GetTick>
|
|
8000fc6: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till LSE is disabled */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
|
|
8000fc8: e00a b.n 8000fe0 <HAL_RCC_OscConfig+0x3c0>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
|
|
8000fca: f7ff fb93 bl 80006f4 <HAL_GetTick>
|
|
8000fce: 4602 mov r2, r0
|
|
8000fd0: 693b ldr r3, [r7, #16]
|
|
8000fd2: 1ad3 subs r3, r2, r3
|
|
8000fd4: f241 3288 movw r2, #5000 ; 0x1388
|
|
8000fd8: 4293 cmp r3, r2
|
|
8000fda: d901 bls.n 8000fe0 <HAL_RCC_OscConfig+0x3c0>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8000fdc: 2303 movs r3, #3
|
|
8000fde: e09b b.n 8001118 <HAL_RCC_OscConfig+0x4f8>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
|
|
8000fe0: 4b40 ldr r3, [pc, #256] ; (80010e4 <HAL_RCC_OscConfig+0x4c4>)
|
|
8000fe2: 6a1b ldr r3, [r3, #32]
|
|
8000fe4: f003 0302 and.w r3, r3, #2
|
|
8000fe8: 2b00 cmp r3, #0
|
|
8000fea: d1ee bne.n 8000fca <HAL_RCC_OscConfig+0x3aa>
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Require to disable power clock if necessary */
|
|
if (pwrclkchanged == SET)
|
|
8000fec: 7dfb ldrb r3, [r7, #23]
|
|
8000fee: 2b01 cmp r3, #1
|
|
8000ff0: d105 bne.n 8000ffe <HAL_RCC_OscConfig+0x3de>
|
|
{
|
|
__HAL_RCC_PWR_CLK_DISABLE();
|
|
8000ff2: 4b3c ldr r3, [pc, #240] ; (80010e4 <HAL_RCC_OscConfig+0x4c4>)
|
|
8000ff4: 69db ldr r3, [r3, #28]
|
|
8000ff6: 4a3b ldr r2, [pc, #236] ; (80010e4 <HAL_RCC_OscConfig+0x4c4>)
|
|
8000ff8: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000
|
|
8000ffc: 61d3 str r3, [r2, #28]
|
|
|
|
#endif /* RCC_CR_PLL2ON */
|
|
/*-------------------------------- PLL Configuration -----------------------*/
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
|
|
if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
|
|
8000ffe: 687b ldr r3, [r7, #4]
|
|
8001000: 69db ldr r3, [r3, #28]
|
|
8001002: 2b00 cmp r3, #0
|
|
8001004: f000 8087 beq.w 8001116 <HAL_RCC_OscConfig+0x4f6>
|
|
{
|
|
/* Check if the PLL is used as system clock or not */
|
|
if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
|
|
8001008: 4b36 ldr r3, [pc, #216] ; (80010e4 <HAL_RCC_OscConfig+0x4c4>)
|
|
800100a: 685b ldr r3, [r3, #4]
|
|
800100c: f003 030c and.w r3, r3, #12
|
|
8001010: 2b08 cmp r3, #8
|
|
8001012: d061 beq.n 80010d8 <HAL_RCC_OscConfig+0x4b8>
|
|
{
|
|
if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
|
|
8001014: 687b ldr r3, [r7, #4]
|
|
8001016: 69db ldr r3, [r3, #28]
|
|
8001018: 2b02 cmp r3, #2
|
|
800101a: d146 bne.n 80010aa <HAL_RCC_OscConfig+0x48a>
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
|
|
assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL));
|
|
|
|
/* Disable the main PLL. */
|
|
__HAL_RCC_PLL_DISABLE();
|
|
800101c: 4b33 ldr r3, [pc, #204] ; (80010ec <HAL_RCC_OscConfig+0x4cc>)
|
|
800101e: 2200 movs r2, #0
|
|
8001020: 601a str r2, [r3, #0]
|
|
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
8001022: f7ff fb67 bl 80006f4 <HAL_GetTick>
|
|
8001026: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till PLL is disabled */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
|
|
8001028: e008 b.n 800103c <HAL_RCC_OscConfig+0x41c>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
|
|
800102a: f7ff fb63 bl 80006f4 <HAL_GetTick>
|
|
800102e: 4602 mov r2, r0
|
|
8001030: 693b ldr r3, [r7, #16]
|
|
8001032: 1ad3 subs r3, r2, r3
|
|
8001034: 2b02 cmp r3, #2
|
|
8001036: d901 bls.n 800103c <HAL_RCC_OscConfig+0x41c>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8001038: 2303 movs r3, #3
|
|
800103a: e06d b.n 8001118 <HAL_RCC_OscConfig+0x4f8>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
|
|
800103c: 4b29 ldr r3, [pc, #164] ; (80010e4 <HAL_RCC_OscConfig+0x4c4>)
|
|
800103e: 681b ldr r3, [r3, #0]
|
|
8001040: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
|
|
8001044: 2b00 cmp r3, #0
|
|
8001046: d1f0 bne.n 800102a <HAL_RCC_OscConfig+0x40a>
|
|
}
|
|
}
|
|
|
|
/* Configure the HSE prediv factor --------------------------------*/
|
|
/* It can be written only when the PLL is disabled. Not used in PLL source is different than HSE */
|
|
if (RCC_OscInitStruct->PLL.PLLSource == RCC_PLLSOURCE_HSE)
|
|
8001048: 687b ldr r3, [r7, #4]
|
|
800104a: 6a1b ldr r3, [r3, #32]
|
|
800104c: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
|
|
8001050: d108 bne.n 8001064 <HAL_RCC_OscConfig+0x444>
|
|
/* Set PREDIV1 source */
|
|
SET_BIT(RCC->CFGR2, RCC_OscInitStruct->Prediv1Source);
|
|
#endif /* RCC_CFGR2_PREDIV1SRC */
|
|
|
|
/* Set PREDIV1 Value */
|
|
__HAL_RCC_HSE_PREDIV_CONFIG(RCC_OscInitStruct->HSEPredivValue);
|
|
8001052: 4b24 ldr r3, [pc, #144] ; (80010e4 <HAL_RCC_OscConfig+0x4c4>)
|
|
8001054: 685b ldr r3, [r3, #4]
|
|
8001056: f423 3200 bic.w r2, r3, #131072 ; 0x20000
|
|
800105a: 687b ldr r3, [r7, #4]
|
|
800105c: 689b ldr r3, [r3, #8]
|
|
800105e: 4921 ldr r1, [pc, #132] ; (80010e4 <HAL_RCC_OscConfig+0x4c4>)
|
|
8001060: 4313 orrs r3, r2
|
|
8001062: 604b str r3, [r1, #4]
|
|
}
|
|
|
|
/* Configure the main PLL clock source and multiplication factors. */
|
|
__HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
|
|
8001064: 4b1f ldr r3, [pc, #124] ; (80010e4 <HAL_RCC_OscConfig+0x4c4>)
|
|
8001066: 685b ldr r3, [r3, #4]
|
|
8001068: f423 1274 bic.w r2, r3, #3997696 ; 0x3d0000
|
|
800106c: 687b ldr r3, [r7, #4]
|
|
800106e: 6a19 ldr r1, [r3, #32]
|
|
8001070: 687b ldr r3, [r7, #4]
|
|
8001072: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
8001074: 430b orrs r3, r1
|
|
8001076: 491b ldr r1, [pc, #108] ; (80010e4 <HAL_RCC_OscConfig+0x4c4>)
|
|
8001078: 4313 orrs r3, r2
|
|
800107a: 604b str r3, [r1, #4]
|
|
RCC_OscInitStruct->PLL.PLLMUL);
|
|
/* Enable the main PLL. */
|
|
__HAL_RCC_PLL_ENABLE();
|
|
800107c: 4b1b ldr r3, [pc, #108] ; (80010ec <HAL_RCC_OscConfig+0x4cc>)
|
|
800107e: 2201 movs r2, #1
|
|
8001080: 601a str r2, [r3, #0]
|
|
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
8001082: f7ff fb37 bl 80006f4 <HAL_GetTick>
|
|
8001086: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till PLL is ready */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
|
|
8001088: e008 b.n 800109c <HAL_RCC_OscConfig+0x47c>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
|
|
800108a: f7ff fb33 bl 80006f4 <HAL_GetTick>
|
|
800108e: 4602 mov r2, r0
|
|
8001090: 693b ldr r3, [r7, #16]
|
|
8001092: 1ad3 subs r3, r2, r3
|
|
8001094: 2b02 cmp r3, #2
|
|
8001096: d901 bls.n 800109c <HAL_RCC_OscConfig+0x47c>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8001098: 2303 movs r3, #3
|
|
800109a: e03d b.n 8001118 <HAL_RCC_OscConfig+0x4f8>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
|
|
800109c: 4b11 ldr r3, [pc, #68] ; (80010e4 <HAL_RCC_OscConfig+0x4c4>)
|
|
800109e: 681b ldr r3, [r3, #0]
|
|
80010a0: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
|
|
80010a4: 2b00 cmp r3, #0
|
|
80010a6: d0f0 beq.n 800108a <HAL_RCC_OscConfig+0x46a>
|
|
80010a8: e035 b.n 8001116 <HAL_RCC_OscConfig+0x4f6>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Disable the main PLL. */
|
|
__HAL_RCC_PLL_DISABLE();
|
|
80010aa: 4b10 ldr r3, [pc, #64] ; (80010ec <HAL_RCC_OscConfig+0x4cc>)
|
|
80010ac: 2200 movs r2, #0
|
|
80010ae: 601a str r2, [r3, #0]
|
|
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
80010b0: f7ff fb20 bl 80006f4 <HAL_GetTick>
|
|
80010b4: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till PLL is disabled */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
|
|
80010b6: e008 b.n 80010ca <HAL_RCC_OscConfig+0x4aa>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
|
|
80010b8: f7ff fb1c bl 80006f4 <HAL_GetTick>
|
|
80010bc: 4602 mov r2, r0
|
|
80010be: 693b ldr r3, [r7, #16]
|
|
80010c0: 1ad3 subs r3, r2, r3
|
|
80010c2: 2b02 cmp r3, #2
|
|
80010c4: d901 bls.n 80010ca <HAL_RCC_OscConfig+0x4aa>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
80010c6: 2303 movs r3, #3
|
|
80010c8: e026 b.n 8001118 <HAL_RCC_OscConfig+0x4f8>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
|
|
80010ca: 4b06 ldr r3, [pc, #24] ; (80010e4 <HAL_RCC_OscConfig+0x4c4>)
|
|
80010cc: 681b ldr r3, [r3, #0]
|
|
80010ce: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
|
|
80010d2: 2b00 cmp r3, #0
|
|
80010d4: d1f0 bne.n 80010b8 <HAL_RCC_OscConfig+0x498>
|
|
80010d6: e01e b.n 8001116 <HAL_RCC_OscConfig+0x4f6>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Check if there is a request to disable the PLL used as System clock source */
|
|
if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
|
|
80010d8: 687b ldr r3, [r7, #4]
|
|
80010da: 69db ldr r3, [r3, #28]
|
|
80010dc: 2b01 cmp r3, #1
|
|
80010de: d107 bne.n 80010f0 <HAL_RCC_OscConfig+0x4d0>
|
|
{
|
|
return HAL_ERROR;
|
|
80010e0: 2301 movs r3, #1
|
|
80010e2: e019 b.n 8001118 <HAL_RCC_OscConfig+0x4f8>
|
|
80010e4: 40021000 .word 0x40021000
|
|
80010e8: 40007000 .word 0x40007000
|
|
80010ec: 42420060 .word 0x42420060
|
|
}
|
|
else
|
|
{
|
|
/* Do not return HAL_ERROR if request repeats the current configuration */
|
|
pll_config = RCC->CFGR;
|
|
80010f0: 4b0b ldr r3, [pc, #44] ; (8001120 <HAL_RCC_OscConfig+0x500>)
|
|
80010f2: 685b ldr r3, [r3, #4]
|
|
80010f4: 60fb str r3, [r7, #12]
|
|
if ((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
|
|
80010f6: 68fb ldr r3, [r7, #12]
|
|
80010f8: f403 3280 and.w r2, r3, #65536 ; 0x10000
|
|
80010fc: 687b ldr r3, [r7, #4]
|
|
80010fe: 6a1b ldr r3, [r3, #32]
|
|
8001100: 429a cmp r2, r3
|
|
8001102: d106 bne.n 8001112 <HAL_RCC_OscConfig+0x4f2>
|
|
(READ_BIT(pll_config, RCC_CFGR_PLLMULL) != RCC_OscInitStruct->PLL.PLLMUL))
|
|
8001104: 68fb ldr r3, [r7, #12]
|
|
8001106: f403 1270 and.w r2, r3, #3932160 ; 0x3c0000
|
|
800110a: 687b ldr r3, [r7, #4]
|
|
800110c: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
if ((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
|
|
800110e: 429a cmp r2, r3
|
|
8001110: d001 beq.n 8001116 <HAL_RCC_OscConfig+0x4f6>
|
|
{
|
|
return HAL_ERROR;
|
|
8001112: 2301 movs r3, #1
|
|
8001114: e000 b.n 8001118 <HAL_RCC_OscConfig+0x4f8>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
return HAL_OK;
|
|
8001116: 2300 movs r3, #0
|
|
}
|
|
8001118: 4618 mov r0, r3
|
|
800111a: 3718 adds r7, #24
|
|
800111c: 46bd mov sp, r7
|
|
800111e: bd80 pop {r7, pc}
|
|
8001120: 40021000 .word 0x40021000
|
|
|
|
08001124 <HAL_RCC_ClockConfig>:
|
|
* You can use @ref HAL_RCC_GetClockConfig() function to know which clock is
|
|
* currently used as system clock source.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
|
|
{
|
|
8001124: b580 push {r7, lr}
|
|
8001126: b084 sub sp, #16
|
|
8001128: af00 add r7, sp, #0
|
|
800112a: 6078 str r0, [r7, #4]
|
|
800112c: 6039 str r1, [r7, #0]
|
|
uint32_t tickstart;
|
|
|
|
/* Check Null pointer */
|
|
if (RCC_ClkInitStruct == NULL)
|
|
800112e: 687b ldr r3, [r7, #4]
|
|
8001130: 2b00 cmp r3, #0
|
|
8001132: d101 bne.n 8001138 <HAL_RCC_ClockConfig+0x14>
|
|
{
|
|
return HAL_ERROR;
|
|
8001134: 2301 movs r3, #1
|
|
8001136: e0d0 b.n 80012da <HAL_RCC_ClockConfig+0x1b6>
|
|
must be correctly programmed according to the frequency of the CPU clock
|
|
(HCLK) of the device. */
|
|
|
|
#if defined(FLASH_ACR_LATENCY)
|
|
/* Increasing the number of wait states because of higher CPU frequency */
|
|
if (FLatency > __HAL_FLASH_GET_LATENCY())
|
|
8001138: 4b6a ldr r3, [pc, #424] ; (80012e4 <HAL_RCC_ClockConfig+0x1c0>)
|
|
800113a: 681b ldr r3, [r3, #0]
|
|
800113c: f003 0307 and.w r3, r3, #7
|
|
8001140: 683a ldr r2, [r7, #0]
|
|
8001142: 429a cmp r2, r3
|
|
8001144: d910 bls.n 8001168 <HAL_RCC_ClockConfig+0x44>
|
|
{
|
|
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
|
|
__HAL_FLASH_SET_LATENCY(FLatency);
|
|
8001146: 4b67 ldr r3, [pc, #412] ; (80012e4 <HAL_RCC_ClockConfig+0x1c0>)
|
|
8001148: 681b ldr r3, [r3, #0]
|
|
800114a: f023 0207 bic.w r2, r3, #7
|
|
800114e: 4965 ldr r1, [pc, #404] ; (80012e4 <HAL_RCC_ClockConfig+0x1c0>)
|
|
8001150: 683b ldr r3, [r7, #0]
|
|
8001152: 4313 orrs r3, r2
|
|
8001154: 600b str r3, [r1, #0]
|
|
|
|
/* Check that the new number of wait states is taken into account to access the Flash
|
|
memory by reading the FLASH_ACR register */
|
|
if (__HAL_FLASH_GET_LATENCY() != FLatency)
|
|
8001156: 4b63 ldr r3, [pc, #396] ; (80012e4 <HAL_RCC_ClockConfig+0x1c0>)
|
|
8001158: 681b ldr r3, [r3, #0]
|
|
800115a: f003 0307 and.w r3, r3, #7
|
|
800115e: 683a ldr r2, [r7, #0]
|
|
8001160: 429a cmp r2, r3
|
|
8001162: d001 beq.n 8001168 <HAL_RCC_ClockConfig+0x44>
|
|
{
|
|
return HAL_ERROR;
|
|
8001164: 2301 movs r3, #1
|
|
8001166: e0b8 b.n 80012da <HAL_RCC_ClockConfig+0x1b6>
|
|
}
|
|
}
|
|
|
|
#endif /* FLASH_ACR_LATENCY */
|
|
/*-------------------------- HCLK Configuration --------------------------*/
|
|
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
|
|
8001168: 687b ldr r3, [r7, #4]
|
|
800116a: 681b ldr r3, [r3, #0]
|
|
800116c: f003 0302 and.w r3, r3, #2
|
|
8001170: 2b00 cmp r3, #0
|
|
8001172: d020 beq.n 80011b6 <HAL_RCC_ClockConfig+0x92>
|
|
{
|
|
/* Set the highest APBx dividers in order to ensure that we do not go through
|
|
a non-spec phase whatever we decrease or increase HCLK. */
|
|
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
|
|
8001174: 687b ldr r3, [r7, #4]
|
|
8001176: 681b ldr r3, [r3, #0]
|
|
8001178: f003 0304 and.w r3, r3, #4
|
|
800117c: 2b00 cmp r3, #0
|
|
800117e: d005 beq.n 800118c <HAL_RCC_ClockConfig+0x68>
|
|
{
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16);
|
|
8001180: 4b59 ldr r3, [pc, #356] ; (80012e8 <HAL_RCC_ClockConfig+0x1c4>)
|
|
8001182: 685b ldr r3, [r3, #4]
|
|
8001184: 4a58 ldr r2, [pc, #352] ; (80012e8 <HAL_RCC_ClockConfig+0x1c4>)
|
|
8001186: f443 63e0 orr.w r3, r3, #1792 ; 0x700
|
|
800118a: 6053 str r3, [r2, #4]
|
|
}
|
|
|
|
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
|
|
800118c: 687b ldr r3, [r7, #4]
|
|
800118e: 681b ldr r3, [r3, #0]
|
|
8001190: f003 0308 and.w r3, r3, #8
|
|
8001194: 2b00 cmp r3, #0
|
|
8001196: d005 beq.n 80011a4 <HAL_RCC_ClockConfig+0x80>
|
|
{
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3));
|
|
8001198: 4b53 ldr r3, [pc, #332] ; (80012e8 <HAL_RCC_ClockConfig+0x1c4>)
|
|
800119a: 685b ldr r3, [r3, #4]
|
|
800119c: 4a52 ldr r2, [pc, #328] ; (80012e8 <HAL_RCC_ClockConfig+0x1c4>)
|
|
800119e: f443 5360 orr.w r3, r3, #14336 ; 0x3800
|
|
80011a2: 6053 str r3, [r2, #4]
|
|
}
|
|
|
|
/* Set the new HCLK clock divider */
|
|
assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
|
|
80011a4: 4b50 ldr r3, [pc, #320] ; (80012e8 <HAL_RCC_ClockConfig+0x1c4>)
|
|
80011a6: 685b ldr r3, [r3, #4]
|
|
80011a8: f023 02f0 bic.w r2, r3, #240 ; 0xf0
|
|
80011ac: 687b ldr r3, [r7, #4]
|
|
80011ae: 689b ldr r3, [r3, #8]
|
|
80011b0: 494d ldr r1, [pc, #308] ; (80012e8 <HAL_RCC_ClockConfig+0x1c4>)
|
|
80011b2: 4313 orrs r3, r2
|
|
80011b4: 604b str r3, [r1, #4]
|
|
}
|
|
|
|
/*------------------------- SYSCLK Configuration ---------------------------*/
|
|
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
|
|
80011b6: 687b ldr r3, [r7, #4]
|
|
80011b8: 681b ldr r3, [r3, #0]
|
|
80011ba: f003 0301 and.w r3, r3, #1
|
|
80011be: 2b00 cmp r3, #0
|
|
80011c0: d040 beq.n 8001244 <HAL_RCC_ClockConfig+0x120>
|
|
{
|
|
assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
|
|
|
|
/* HSE is selected as System Clock Source */
|
|
if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
|
|
80011c2: 687b ldr r3, [r7, #4]
|
|
80011c4: 685b ldr r3, [r3, #4]
|
|
80011c6: 2b01 cmp r3, #1
|
|
80011c8: d107 bne.n 80011da <HAL_RCC_ClockConfig+0xb6>
|
|
{
|
|
/* Check the HSE ready flag */
|
|
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
|
|
80011ca: 4b47 ldr r3, [pc, #284] ; (80012e8 <HAL_RCC_ClockConfig+0x1c4>)
|
|
80011cc: 681b ldr r3, [r3, #0]
|
|
80011ce: f403 3300 and.w r3, r3, #131072 ; 0x20000
|
|
80011d2: 2b00 cmp r3, #0
|
|
80011d4: d115 bne.n 8001202 <HAL_RCC_ClockConfig+0xde>
|
|
{
|
|
return HAL_ERROR;
|
|
80011d6: 2301 movs r3, #1
|
|
80011d8: e07f b.n 80012da <HAL_RCC_ClockConfig+0x1b6>
|
|
}
|
|
}
|
|
/* PLL is selected as System Clock Source */
|
|
else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
|
|
80011da: 687b ldr r3, [r7, #4]
|
|
80011dc: 685b ldr r3, [r3, #4]
|
|
80011de: 2b02 cmp r3, #2
|
|
80011e0: d107 bne.n 80011f2 <HAL_RCC_ClockConfig+0xce>
|
|
{
|
|
/* Check the PLL ready flag */
|
|
if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
|
|
80011e2: 4b41 ldr r3, [pc, #260] ; (80012e8 <HAL_RCC_ClockConfig+0x1c4>)
|
|
80011e4: 681b ldr r3, [r3, #0]
|
|
80011e6: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
|
|
80011ea: 2b00 cmp r3, #0
|
|
80011ec: d109 bne.n 8001202 <HAL_RCC_ClockConfig+0xde>
|
|
{
|
|
return HAL_ERROR;
|
|
80011ee: 2301 movs r3, #1
|
|
80011f0: e073 b.n 80012da <HAL_RCC_ClockConfig+0x1b6>
|
|
}
|
|
/* HSI is selected as System Clock Source */
|
|
else
|
|
{
|
|
/* Check the HSI ready flag */
|
|
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
|
|
80011f2: 4b3d ldr r3, [pc, #244] ; (80012e8 <HAL_RCC_ClockConfig+0x1c4>)
|
|
80011f4: 681b ldr r3, [r3, #0]
|
|
80011f6: f003 0302 and.w r3, r3, #2
|
|
80011fa: 2b00 cmp r3, #0
|
|
80011fc: d101 bne.n 8001202 <HAL_RCC_ClockConfig+0xde>
|
|
{
|
|
return HAL_ERROR;
|
|
80011fe: 2301 movs r3, #1
|
|
8001200: e06b b.n 80012da <HAL_RCC_ClockConfig+0x1b6>
|
|
}
|
|
}
|
|
__HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
|
|
8001202: 4b39 ldr r3, [pc, #228] ; (80012e8 <HAL_RCC_ClockConfig+0x1c4>)
|
|
8001204: 685b ldr r3, [r3, #4]
|
|
8001206: f023 0203 bic.w r2, r3, #3
|
|
800120a: 687b ldr r3, [r7, #4]
|
|
800120c: 685b ldr r3, [r3, #4]
|
|
800120e: 4936 ldr r1, [pc, #216] ; (80012e8 <HAL_RCC_ClockConfig+0x1c4>)
|
|
8001210: 4313 orrs r3, r2
|
|
8001212: 604b str r3, [r1, #4]
|
|
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
8001214: f7ff fa6e bl 80006f4 <HAL_GetTick>
|
|
8001218: 60f8 str r0, [r7, #12]
|
|
|
|
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
|
|
800121a: e00a b.n 8001232 <HAL_RCC_ClockConfig+0x10e>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
|
|
800121c: f7ff fa6a bl 80006f4 <HAL_GetTick>
|
|
8001220: 4602 mov r2, r0
|
|
8001222: 68fb ldr r3, [r7, #12]
|
|
8001224: 1ad3 subs r3, r2, r3
|
|
8001226: f241 3288 movw r2, #5000 ; 0x1388
|
|
800122a: 4293 cmp r3, r2
|
|
800122c: d901 bls.n 8001232 <HAL_RCC_ClockConfig+0x10e>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
800122e: 2303 movs r3, #3
|
|
8001230: e053 b.n 80012da <HAL_RCC_ClockConfig+0x1b6>
|
|
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
|
|
8001232: 4b2d ldr r3, [pc, #180] ; (80012e8 <HAL_RCC_ClockConfig+0x1c4>)
|
|
8001234: 685b ldr r3, [r3, #4]
|
|
8001236: f003 020c and.w r2, r3, #12
|
|
800123a: 687b ldr r3, [r7, #4]
|
|
800123c: 685b ldr r3, [r3, #4]
|
|
800123e: 009b lsls r3, r3, #2
|
|
8001240: 429a cmp r2, r3
|
|
8001242: d1eb bne.n 800121c <HAL_RCC_ClockConfig+0xf8>
|
|
}
|
|
}
|
|
|
|
#if defined(FLASH_ACR_LATENCY)
|
|
/* Decreasing the number of wait states because of lower CPU frequency */
|
|
if (FLatency < __HAL_FLASH_GET_LATENCY())
|
|
8001244: 4b27 ldr r3, [pc, #156] ; (80012e4 <HAL_RCC_ClockConfig+0x1c0>)
|
|
8001246: 681b ldr r3, [r3, #0]
|
|
8001248: f003 0307 and.w r3, r3, #7
|
|
800124c: 683a ldr r2, [r7, #0]
|
|
800124e: 429a cmp r2, r3
|
|
8001250: d210 bcs.n 8001274 <HAL_RCC_ClockConfig+0x150>
|
|
{
|
|
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
|
|
__HAL_FLASH_SET_LATENCY(FLatency);
|
|
8001252: 4b24 ldr r3, [pc, #144] ; (80012e4 <HAL_RCC_ClockConfig+0x1c0>)
|
|
8001254: 681b ldr r3, [r3, #0]
|
|
8001256: f023 0207 bic.w r2, r3, #7
|
|
800125a: 4922 ldr r1, [pc, #136] ; (80012e4 <HAL_RCC_ClockConfig+0x1c0>)
|
|
800125c: 683b ldr r3, [r7, #0]
|
|
800125e: 4313 orrs r3, r2
|
|
8001260: 600b str r3, [r1, #0]
|
|
|
|
/* Check that the new number of wait states is taken into account to access the Flash
|
|
memory by reading the FLASH_ACR register */
|
|
if (__HAL_FLASH_GET_LATENCY() != FLatency)
|
|
8001262: 4b20 ldr r3, [pc, #128] ; (80012e4 <HAL_RCC_ClockConfig+0x1c0>)
|
|
8001264: 681b ldr r3, [r3, #0]
|
|
8001266: f003 0307 and.w r3, r3, #7
|
|
800126a: 683a ldr r2, [r7, #0]
|
|
800126c: 429a cmp r2, r3
|
|
800126e: d001 beq.n 8001274 <HAL_RCC_ClockConfig+0x150>
|
|
{
|
|
return HAL_ERROR;
|
|
8001270: 2301 movs r3, #1
|
|
8001272: e032 b.n 80012da <HAL_RCC_ClockConfig+0x1b6>
|
|
}
|
|
}
|
|
#endif /* FLASH_ACR_LATENCY */
|
|
|
|
/*-------------------------- PCLK1 Configuration ---------------------------*/
|
|
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
|
|
8001274: 687b ldr r3, [r7, #4]
|
|
8001276: 681b ldr r3, [r3, #0]
|
|
8001278: f003 0304 and.w r3, r3, #4
|
|
800127c: 2b00 cmp r3, #0
|
|
800127e: d008 beq.n 8001292 <HAL_RCC_ClockConfig+0x16e>
|
|
{
|
|
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
|
|
8001280: 4b19 ldr r3, [pc, #100] ; (80012e8 <HAL_RCC_ClockConfig+0x1c4>)
|
|
8001282: 685b ldr r3, [r3, #4]
|
|
8001284: f423 62e0 bic.w r2, r3, #1792 ; 0x700
|
|
8001288: 687b ldr r3, [r7, #4]
|
|
800128a: 68db ldr r3, [r3, #12]
|
|
800128c: 4916 ldr r1, [pc, #88] ; (80012e8 <HAL_RCC_ClockConfig+0x1c4>)
|
|
800128e: 4313 orrs r3, r2
|
|
8001290: 604b str r3, [r1, #4]
|
|
}
|
|
|
|
/*-------------------------- PCLK2 Configuration ---------------------------*/
|
|
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
|
|
8001292: 687b ldr r3, [r7, #4]
|
|
8001294: 681b ldr r3, [r3, #0]
|
|
8001296: f003 0308 and.w r3, r3, #8
|
|
800129a: 2b00 cmp r3, #0
|
|
800129c: d009 beq.n 80012b2 <HAL_RCC_ClockConfig+0x18e>
|
|
{
|
|
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3));
|
|
800129e: 4b12 ldr r3, [pc, #72] ; (80012e8 <HAL_RCC_ClockConfig+0x1c4>)
|
|
80012a0: 685b ldr r3, [r3, #4]
|
|
80012a2: f423 5260 bic.w r2, r3, #14336 ; 0x3800
|
|
80012a6: 687b ldr r3, [r7, #4]
|
|
80012a8: 691b ldr r3, [r3, #16]
|
|
80012aa: 00db lsls r3, r3, #3
|
|
80012ac: 490e ldr r1, [pc, #56] ; (80012e8 <HAL_RCC_ClockConfig+0x1c4>)
|
|
80012ae: 4313 orrs r3, r2
|
|
80012b0: 604b str r3, [r1, #4]
|
|
}
|
|
|
|
/* Update the SystemCoreClock global variable */
|
|
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos];
|
|
80012b2: f000 f821 bl 80012f8 <HAL_RCC_GetSysClockFreq>
|
|
80012b6: 4602 mov r2, r0
|
|
80012b8: 4b0b ldr r3, [pc, #44] ; (80012e8 <HAL_RCC_ClockConfig+0x1c4>)
|
|
80012ba: 685b ldr r3, [r3, #4]
|
|
80012bc: 091b lsrs r3, r3, #4
|
|
80012be: f003 030f and.w r3, r3, #15
|
|
80012c2: 490a ldr r1, [pc, #40] ; (80012ec <HAL_RCC_ClockConfig+0x1c8>)
|
|
80012c4: 5ccb ldrb r3, [r1, r3]
|
|
80012c6: fa22 f303 lsr.w r3, r2, r3
|
|
80012ca: 4a09 ldr r2, [pc, #36] ; (80012f0 <HAL_RCC_ClockConfig+0x1cc>)
|
|
80012cc: 6013 str r3, [r2, #0]
|
|
|
|
/* Configure the source of time base considering new system clocks settings*/
|
|
HAL_InitTick(uwTickPrio);
|
|
80012ce: 4b09 ldr r3, [pc, #36] ; (80012f4 <HAL_RCC_ClockConfig+0x1d0>)
|
|
80012d0: 681b ldr r3, [r3, #0]
|
|
80012d2: 4618 mov r0, r3
|
|
80012d4: f7ff f9cc bl 8000670 <HAL_InitTick>
|
|
|
|
return HAL_OK;
|
|
80012d8: 2300 movs r3, #0
|
|
}
|
|
80012da: 4618 mov r0, r3
|
|
80012dc: 3710 adds r7, #16
|
|
80012de: 46bd mov sp, r7
|
|
80012e0: bd80 pop {r7, pc}
|
|
80012e2: bf00 nop
|
|
80012e4: 40022000 .word 0x40022000
|
|
80012e8: 40021000 .word 0x40021000
|
|
80012ec: 08002574 .word 0x08002574
|
|
80012f0: 20000000 .word 0x20000000
|
|
80012f4: 20000004 .word 0x20000004
|
|
|
|
080012f8 <HAL_RCC_GetSysClockFreq>:
|
|
* right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
|
|
*
|
|
* @retval SYSCLK frequency
|
|
*/
|
|
uint32_t HAL_RCC_GetSysClockFreq(void)
|
|
{
|
|
80012f8: b490 push {r4, r7}
|
|
80012fa: b08a sub sp, #40 ; 0x28
|
|
80012fc: af00 add r7, sp, #0
|
|
#if defined(RCC_CFGR2_PREDIV1SRC)
|
|
const uint8_t aPLLMULFactorTable[14] = {0, 0, 4, 5, 6, 7, 8, 9, 0, 0, 0, 0, 0, 13};
|
|
const uint8_t aPredivFactorTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16};
|
|
#else
|
|
const uint8_t aPLLMULFactorTable[16] = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16};
|
|
80012fe: 4b29 ldr r3, [pc, #164] ; (80013a4 <HAL_RCC_GetSysClockFreq+0xac>)
|
|
8001300: 1d3c adds r4, r7, #4
|
|
8001302: cb0f ldmia r3, {r0, r1, r2, r3}
|
|
8001304: e884 000f stmia.w r4, {r0, r1, r2, r3}
|
|
#if defined(RCC_CFGR2_PREDIV1)
|
|
const uint8_t aPredivFactorTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16};
|
|
#else
|
|
const uint8_t aPredivFactorTable[2] = {1, 2};
|
|
8001308: f240 2301 movw r3, #513 ; 0x201
|
|
800130c: 803b strh r3, [r7, #0]
|
|
#endif /*RCC_CFGR2_PREDIV1*/
|
|
|
|
#endif
|
|
uint32_t tmpreg = 0U, prediv = 0U, pllclk = 0U, pllmul = 0U;
|
|
800130e: 2300 movs r3, #0
|
|
8001310: 61fb str r3, [r7, #28]
|
|
8001312: 2300 movs r3, #0
|
|
8001314: 61bb str r3, [r7, #24]
|
|
8001316: 2300 movs r3, #0
|
|
8001318: 627b str r3, [r7, #36] ; 0x24
|
|
800131a: 2300 movs r3, #0
|
|
800131c: 617b str r3, [r7, #20]
|
|
uint32_t sysclockfreq = 0U;
|
|
800131e: 2300 movs r3, #0
|
|
8001320: 623b str r3, [r7, #32]
|
|
#if defined(RCC_CFGR2_PREDIV1SRC)
|
|
uint32_t prediv2 = 0U, pll2mul = 0U;
|
|
#endif /*RCC_CFGR2_PREDIV1SRC*/
|
|
|
|
tmpreg = RCC->CFGR;
|
|
8001322: 4b21 ldr r3, [pc, #132] ; (80013a8 <HAL_RCC_GetSysClockFreq+0xb0>)
|
|
8001324: 685b ldr r3, [r3, #4]
|
|
8001326: 61fb str r3, [r7, #28]
|
|
|
|
/* Get SYSCLK source -------------------------------------------------------*/
|
|
switch (tmpreg & RCC_CFGR_SWS)
|
|
8001328: 69fb ldr r3, [r7, #28]
|
|
800132a: f003 030c and.w r3, r3, #12
|
|
800132e: 2b04 cmp r3, #4
|
|
8001330: d002 beq.n 8001338 <HAL_RCC_GetSysClockFreq+0x40>
|
|
8001332: 2b08 cmp r3, #8
|
|
8001334: d003 beq.n 800133e <HAL_RCC_GetSysClockFreq+0x46>
|
|
8001336: e02b b.n 8001390 <HAL_RCC_GetSysClockFreq+0x98>
|
|
{
|
|
case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */
|
|
{
|
|
sysclockfreq = HSE_VALUE;
|
|
8001338: 4b1c ldr r3, [pc, #112] ; (80013ac <HAL_RCC_GetSysClockFreq+0xb4>)
|
|
800133a: 623b str r3, [r7, #32]
|
|
break;
|
|
800133c: e02b b.n 8001396 <HAL_RCC_GetSysClockFreq+0x9e>
|
|
}
|
|
case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */
|
|
{
|
|
pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos];
|
|
800133e: 69fb ldr r3, [r7, #28]
|
|
8001340: 0c9b lsrs r3, r3, #18
|
|
8001342: f003 030f and.w r3, r3, #15
|
|
8001346: 3328 adds r3, #40 ; 0x28
|
|
8001348: 443b add r3, r7
|
|
800134a: f813 3c24 ldrb.w r3, [r3, #-36]
|
|
800134e: 617b str r3, [r7, #20]
|
|
if ((tmpreg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2)
|
|
8001350: 69fb ldr r3, [r7, #28]
|
|
8001352: f403 3380 and.w r3, r3, #65536 ; 0x10000
|
|
8001356: 2b00 cmp r3, #0
|
|
8001358: d012 beq.n 8001380 <HAL_RCC_GetSysClockFreq+0x88>
|
|
{
|
|
#if defined(RCC_CFGR2_PREDIV1)
|
|
prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> RCC_CFGR2_PREDIV1_Pos];
|
|
#else
|
|
prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos];
|
|
800135a: 4b13 ldr r3, [pc, #76] ; (80013a8 <HAL_RCC_GetSysClockFreq+0xb0>)
|
|
800135c: 685b ldr r3, [r3, #4]
|
|
800135e: 0c5b lsrs r3, r3, #17
|
|
8001360: f003 0301 and.w r3, r3, #1
|
|
8001364: 3328 adds r3, #40 ; 0x28
|
|
8001366: 443b add r3, r7
|
|
8001368: f813 3c28 ldrb.w r3, [r3, #-40]
|
|
800136c: 61bb str r3, [r7, #24]
|
|
{
|
|
pllclk = pllclk / 2;
|
|
}
|
|
#else
|
|
/* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */
|
|
pllclk = (uint32_t)((HSE_VALUE * pllmul) / prediv);
|
|
800136e: 697b ldr r3, [r7, #20]
|
|
8001370: 4a0e ldr r2, [pc, #56] ; (80013ac <HAL_RCC_GetSysClockFreq+0xb4>)
|
|
8001372: fb03 f202 mul.w r2, r3, r2
|
|
8001376: 69bb ldr r3, [r7, #24]
|
|
8001378: fbb2 f3f3 udiv r3, r2, r3
|
|
800137c: 627b str r3, [r7, #36] ; 0x24
|
|
800137e: e004 b.n 800138a <HAL_RCC_GetSysClockFreq+0x92>
|
|
#endif /*RCC_CFGR2_PREDIV1SRC*/
|
|
}
|
|
else
|
|
{
|
|
/* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */
|
|
pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul);
|
|
8001380: 697b ldr r3, [r7, #20]
|
|
8001382: 4a0b ldr r2, [pc, #44] ; (80013b0 <HAL_RCC_GetSysClockFreq+0xb8>)
|
|
8001384: fb02 f303 mul.w r3, r2, r3
|
|
8001388: 627b str r3, [r7, #36] ; 0x24
|
|
}
|
|
sysclockfreq = pllclk;
|
|
800138a: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
800138c: 623b str r3, [r7, #32]
|
|
break;
|
|
800138e: e002 b.n 8001396 <HAL_RCC_GetSysClockFreq+0x9e>
|
|
}
|
|
case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
|
|
default: /* HSI used as system clock */
|
|
{
|
|
sysclockfreq = HSI_VALUE;
|
|
8001390: 4b06 ldr r3, [pc, #24] ; (80013ac <HAL_RCC_GetSysClockFreq+0xb4>)
|
|
8001392: 623b str r3, [r7, #32]
|
|
break;
|
|
8001394: bf00 nop
|
|
}
|
|
}
|
|
return sysclockfreq;
|
|
8001396: 6a3b ldr r3, [r7, #32]
|
|
}
|
|
8001398: 4618 mov r0, r3
|
|
800139a: 3728 adds r7, #40 ; 0x28
|
|
800139c: 46bd mov sp, r7
|
|
800139e: bc90 pop {r4, r7}
|
|
80013a0: 4770 bx lr
|
|
80013a2: bf00 nop
|
|
80013a4: 08002564 .word 0x08002564
|
|
80013a8: 40021000 .word 0x40021000
|
|
80013ac: 007a1200 .word 0x007a1200
|
|
80013b0: 003d0900 .word 0x003d0900
|
|
|
|
080013b4 <HAL_RCC_GetHCLKFreq>:
|
|
* @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
|
|
* and updated within this function
|
|
* @retval HCLK frequency
|
|
*/
|
|
uint32_t HAL_RCC_GetHCLKFreq(void)
|
|
{
|
|
80013b4: b480 push {r7}
|
|
80013b6: af00 add r7, sp, #0
|
|
return SystemCoreClock;
|
|
80013b8: 4b02 ldr r3, [pc, #8] ; (80013c4 <HAL_RCC_GetHCLKFreq+0x10>)
|
|
80013ba: 681b ldr r3, [r3, #0]
|
|
}
|
|
80013bc: 4618 mov r0, r3
|
|
80013be: 46bd mov sp, r7
|
|
80013c0: bc80 pop {r7}
|
|
80013c2: 4770 bx lr
|
|
80013c4: 20000000 .word 0x20000000
|
|
|
|
080013c8 <HAL_RCC_GetPCLK1Freq>:
|
|
* @note Each time PCLK1 changes, this function must be called to update the
|
|
* right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
|
|
* @retval PCLK1 frequency
|
|
*/
|
|
uint32_t HAL_RCC_GetPCLK1Freq(void)
|
|
{
|
|
80013c8: b580 push {r7, lr}
|
|
80013ca: af00 add r7, sp, #0
|
|
/* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
|
|
return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]);
|
|
80013cc: f7ff fff2 bl 80013b4 <HAL_RCC_GetHCLKFreq>
|
|
80013d0: 4602 mov r2, r0
|
|
80013d2: 4b05 ldr r3, [pc, #20] ; (80013e8 <HAL_RCC_GetPCLK1Freq+0x20>)
|
|
80013d4: 685b ldr r3, [r3, #4]
|
|
80013d6: 0a1b lsrs r3, r3, #8
|
|
80013d8: f003 0307 and.w r3, r3, #7
|
|
80013dc: 4903 ldr r1, [pc, #12] ; (80013ec <HAL_RCC_GetPCLK1Freq+0x24>)
|
|
80013de: 5ccb ldrb r3, [r1, r3]
|
|
80013e0: fa22 f303 lsr.w r3, r2, r3
|
|
}
|
|
80013e4: 4618 mov r0, r3
|
|
80013e6: bd80 pop {r7, pc}
|
|
80013e8: 40021000 .word 0x40021000
|
|
80013ec: 08002584 .word 0x08002584
|
|
|
|
080013f0 <HAL_RCC_GetPCLK2Freq>:
|
|
* @note Each time PCLK2 changes, this function must be called to update the
|
|
* right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
|
|
* @retval PCLK2 frequency
|
|
*/
|
|
uint32_t HAL_RCC_GetPCLK2Freq(void)
|
|
{
|
|
80013f0: b580 push {r7, lr}
|
|
80013f2: af00 add r7, sp, #0
|
|
/* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
|
|
return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]);
|
|
80013f4: f7ff ffde bl 80013b4 <HAL_RCC_GetHCLKFreq>
|
|
80013f8: 4602 mov r2, r0
|
|
80013fa: 4b05 ldr r3, [pc, #20] ; (8001410 <HAL_RCC_GetPCLK2Freq+0x20>)
|
|
80013fc: 685b ldr r3, [r3, #4]
|
|
80013fe: 0adb lsrs r3, r3, #11
|
|
8001400: f003 0307 and.w r3, r3, #7
|
|
8001404: 4903 ldr r1, [pc, #12] ; (8001414 <HAL_RCC_GetPCLK2Freq+0x24>)
|
|
8001406: 5ccb ldrb r3, [r1, r3]
|
|
8001408: fa22 f303 lsr.w r3, r2, r3
|
|
}
|
|
800140c: 4618 mov r0, r3
|
|
800140e: bd80 pop {r7, pc}
|
|
8001410: 40021000 .word 0x40021000
|
|
8001414: 08002584 .word 0x08002584
|
|
|
|
08001418 <RCC_Delay>:
|
|
* @brief This function provides delay (in milliseconds) based on CPU cycles method.
|
|
* @param mdelay: specifies the delay time length, in milliseconds.
|
|
* @retval None
|
|
*/
|
|
static void RCC_Delay(uint32_t mdelay)
|
|
{
|
|
8001418: b480 push {r7}
|
|
800141a: b085 sub sp, #20
|
|
800141c: af00 add r7, sp, #0
|
|
800141e: 6078 str r0, [r7, #4]
|
|
__IO uint32_t Delay = mdelay * (SystemCoreClock / 8U / 1000U);
|
|
8001420: 4b0a ldr r3, [pc, #40] ; (800144c <RCC_Delay+0x34>)
|
|
8001422: 681b ldr r3, [r3, #0]
|
|
8001424: 4a0a ldr r2, [pc, #40] ; (8001450 <RCC_Delay+0x38>)
|
|
8001426: fba2 2303 umull r2, r3, r2, r3
|
|
800142a: 0a5b lsrs r3, r3, #9
|
|
800142c: 687a ldr r2, [r7, #4]
|
|
800142e: fb02 f303 mul.w r3, r2, r3
|
|
8001432: 60fb str r3, [r7, #12]
|
|
do
|
|
{
|
|
__NOP();
|
|
8001434: bf00 nop
|
|
}
|
|
while (Delay --);
|
|
8001436: 68fb ldr r3, [r7, #12]
|
|
8001438: 1e5a subs r2, r3, #1
|
|
800143a: 60fa str r2, [r7, #12]
|
|
800143c: 2b00 cmp r3, #0
|
|
800143e: d1f9 bne.n 8001434 <RCC_Delay+0x1c>
|
|
}
|
|
8001440: bf00 nop
|
|
8001442: bf00 nop
|
|
8001444: 3714 adds r7, #20
|
|
8001446: 46bd mov sp, r7
|
|
8001448: bc80 pop {r7}
|
|
800144a: 4770 bx lr
|
|
800144c: 20000000 .word 0x20000000
|
|
8001450: 10624dd3 .word 0x10624dd3
|
|
|
|
08001454 <HAL_TIM_Encoder_Init>:
|
|
* @param htim TIM Encoder Interface handle
|
|
* @param sConfig TIM Encoder Interface configuration structure
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig)
|
|
{
|
|
8001454: b580 push {r7, lr}
|
|
8001456: b086 sub sp, #24
|
|
8001458: af00 add r7, sp, #0
|
|
800145a: 6078 str r0, [r7, #4]
|
|
800145c: 6039 str r1, [r7, #0]
|
|
uint32_t tmpsmcr;
|
|
uint32_t tmpccmr1;
|
|
uint32_t tmpccer;
|
|
|
|
/* Check the TIM handle allocation */
|
|
if (htim == NULL)
|
|
800145e: 687b ldr r3, [r7, #4]
|
|
8001460: 2b00 cmp r3, #0
|
|
8001462: d101 bne.n 8001468 <HAL_TIM_Encoder_Init+0x14>
|
|
{
|
|
return HAL_ERROR;
|
|
8001464: 2301 movs r3, #1
|
|
8001466: e093 b.n 8001590 <HAL_TIM_Encoder_Init+0x13c>
|
|
assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
|
|
assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
|
|
assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
|
|
assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
|
|
|
|
if (htim->State == HAL_TIM_STATE_RESET)
|
|
8001468: 687b ldr r3, [r7, #4]
|
|
800146a: f893 303d ldrb.w r3, [r3, #61] ; 0x3d
|
|
800146e: b2db uxtb r3, r3
|
|
8001470: 2b00 cmp r3, #0
|
|
8001472: d106 bne.n 8001482 <HAL_TIM_Encoder_Init+0x2e>
|
|
{
|
|
/* Allocate lock resource and initialize it */
|
|
htim->Lock = HAL_UNLOCKED;
|
|
8001474: 687b ldr r3, [r7, #4]
|
|
8001476: 2200 movs r2, #0
|
|
8001478: f883 203c strb.w r2, [r3, #60] ; 0x3c
|
|
}
|
|
/* Init the low level hardware : GPIO, CLOCK, NVIC */
|
|
htim->Encoder_MspInitCallback(htim);
|
|
#else
|
|
/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
|
|
HAL_TIM_Encoder_MspInit(htim);
|
|
800147c: 6878 ldr r0, [r7, #4]
|
|
800147e: f7ff f807 bl 8000490 <HAL_TIM_Encoder_MspInit>
|
|
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
|
|
}
|
|
|
|
/* Set the TIM state */
|
|
htim->State = HAL_TIM_STATE_BUSY;
|
|
8001482: 687b ldr r3, [r7, #4]
|
|
8001484: 2202 movs r2, #2
|
|
8001486: f883 203d strb.w r2, [r3, #61] ; 0x3d
|
|
|
|
/* Reset the SMS and ECE bits */
|
|
htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE);
|
|
800148a: 687b ldr r3, [r7, #4]
|
|
800148c: 681b ldr r3, [r3, #0]
|
|
800148e: 689b ldr r3, [r3, #8]
|
|
8001490: 687a ldr r2, [r7, #4]
|
|
8001492: 6812 ldr r2, [r2, #0]
|
|
8001494: f423 4380 bic.w r3, r3, #16384 ; 0x4000
|
|
8001498: f023 0307 bic.w r3, r3, #7
|
|
800149c: 6093 str r3, [r2, #8]
|
|
|
|
/* Configure the Time base in the Encoder Mode */
|
|
TIM_Base_SetConfig(htim->Instance, &htim->Init);
|
|
800149e: 687b ldr r3, [r7, #4]
|
|
80014a0: 681a ldr r2, [r3, #0]
|
|
80014a2: 687b ldr r3, [r7, #4]
|
|
80014a4: 3304 adds r3, #4
|
|
80014a6: 4619 mov r1, r3
|
|
80014a8: 4610 mov r0, r2
|
|
80014aa: f000 f903 bl 80016b4 <TIM_Base_SetConfig>
|
|
|
|
/* Get the TIMx SMCR register value */
|
|
tmpsmcr = htim->Instance->SMCR;
|
|
80014ae: 687b ldr r3, [r7, #4]
|
|
80014b0: 681b ldr r3, [r3, #0]
|
|
80014b2: 689b ldr r3, [r3, #8]
|
|
80014b4: 617b str r3, [r7, #20]
|
|
|
|
/* Get the TIMx CCMR1 register value */
|
|
tmpccmr1 = htim->Instance->CCMR1;
|
|
80014b6: 687b ldr r3, [r7, #4]
|
|
80014b8: 681b ldr r3, [r3, #0]
|
|
80014ba: 699b ldr r3, [r3, #24]
|
|
80014bc: 613b str r3, [r7, #16]
|
|
|
|
/* Get the TIMx CCER register value */
|
|
tmpccer = htim->Instance->CCER;
|
|
80014be: 687b ldr r3, [r7, #4]
|
|
80014c0: 681b ldr r3, [r3, #0]
|
|
80014c2: 6a1b ldr r3, [r3, #32]
|
|
80014c4: 60fb str r3, [r7, #12]
|
|
|
|
/* Set the encoder Mode */
|
|
tmpsmcr |= sConfig->EncoderMode;
|
|
80014c6: 683b ldr r3, [r7, #0]
|
|
80014c8: 681b ldr r3, [r3, #0]
|
|
80014ca: 697a ldr r2, [r7, #20]
|
|
80014cc: 4313 orrs r3, r2
|
|
80014ce: 617b str r3, [r7, #20]
|
|
|
|
/* Select the Capture Compare 1 and the Capture Compare 2 as input */
|
|
tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);
|
|
80014d0: 693b ldr r3, [r7, #16]
|
|
80014d2: f423 7340 bic.w r3, r3, #768 ; 0x300
|
|
80014d6: f023 0303 bic.w r3, r3, #3
|
|
80014da: 613b str r3, [r7, #16]
|
|
tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U));
|
|
80014dc: 683b ldr r3, [r7, #0]
|
|
80014de: 689a ldr r2, [r3, #8]
|
|
80014e0: 683b ldr r3, [r7, #0]
|
|
80014e2: 699b ldr r3, [r3, #24]
|
|
80014e4: 021b lsls r3, r3, #8
|
|
80014e6: 4313 orrs r3, r2
|
|
80014e8: 693a ldr r2, [r7, #16]
|
|
80014ea: 4313 orrs r3, r2
|
|
80014ec: 613b str r3, [r7, #16]
|
|
|
|
/* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
|
|
tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);
|
|
80014ee: 693b ldr r3, [r7, #16]
|
|
80014f0: f423 6340 bic.w r3, r3, #3072 ; 0xc00
|
|
80014f4: f023 030c bic.w r3, r3, #12
|
|
80014f8: 613b str r3, [r7, #16]
|
|
tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);
|
|
80014fa: 693b ldr r3, [r7, #16]
|
|
80014fc: f423 4370 bic.w r3, r3, #61440 ; 0xf000
|
|
8001500: f023 03f0 bic.w r3, r3, #240 ; 0xf0
|
|
8001504: 613b str r3, [r7, #16]
|
|
tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U);
|
|
8001506: 683b ldr r3, [r7, #0]
|
|
8001508: 68da ldr r2, [r3, #12]
|
|
800150a: 683b ldr r3, [r7, #0]
|
|
800150c: 69db ldr r3, [r3, #28]
|
|
800150e: 021b lsls r3, r3, #8
|
|
8001510: 4313 orrs r3, r2
|
|
8001512: 693a ldr r2, [r7, #16]
|
|
8001514: 4313 orrs r3, r2
|
|
8001516: 613b str r3, [r7, #16]
|
|
tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U);
|
|
8001518: 683b ldr r3, [r7, #0]
|
|
800151a: 691b ldr r3, [r3, #16]
|
|
800151c: 011a lsls r2, r3, #4
|
|
800151e: 683b ldr r3, [r7, #0]
|
|
8001520: 6a1b ldr r3, [r3, #32]
|
|
8001522: 031b lsls r3, r3, #12
|
|
8001524: 4313 orrs r3, r2
|
|
8001526: 693a ldr r2, [r7, #16]
|
|
8001528: 4313 orrs r3, r2
|
|
800152a: 613b str r3, [r7, #16]
|
|
|
|
/* Set the TI1 and the TI2 Polarities */
|
|
tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P);
|
|
800152c: 68fb ldr r3, [r7, #12]
|
|
800152e: f023 0322 bic.w r3, r3, #34 ; 0x22
|
|
8001532: 60fb str r3, [r7, #12]
|
|
tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U);
|
|
8001534: 683b ldr r3, [r7, #0]
|
|
8001536: 685a ldr r2, [r3, #4]
|
|
8001538: 683b ldr r3, [r7, #0]
|
|
800153a: 695b ldr r3, [r3, #20]
|
|
800153c: 011b lsls r3, r3, #4
|
|
800153e: 4313 orrs r3, r2
|
|
8001540: 68fa ldr r2, [r7, #12]
|
|
8001542: 4313 orrs r3, r2
|
|
8001544: 60fb str r3, [r7, #12]
|
|
|
|
/* Write to TIMx SMCR */
|
|
htim->Instance->SMCR = tmpsmcr;
|
|
8001546: 687b ldr r3, [r7, #4]
|
|
8001548: 681b ldr r3, [r3, #0]
|
|
800154a: 697a ldr r2, [r7, #20]
|
|
800154c: 609a str r2, [r3, #8]
|
|
|
|
/* Write to TIMx CCMR1 */
|
|
htim->Instance->CCMR1 = tmpccmr1;
|
|
800154e: 687b ldr r3, [r7, #4]
|
|
8001550: 681b ldr r3, [r3, #0]
|
|
8001552: 693a ldr r2, [r7, #16]
|
|
8001554: 619a str r2, [r3, #24]
|
|
|
|
/* Write to TIMx CCER */
|
|
htim->Instance->CCER = tmpccer;
|
|
8001556: 687b ldr r3, [r7, #4]
|
|
8001558: 681b ldr r3, [r3, #0]
|
|
800155a: 68fa ldr r2, [r7, #12]
|
|
800155c: 621a str r2, [r3, #32]
|
|
|
|
/* Initialize the DMA burst operation state */
|
|
htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
|
|
800155e: 687b ldr r3, [r7, #4]
|
|
8001560: 2201 movs r2, #1
|
|
8001562: f883 2046 strb.w r2, [r3, #70] ; 0x46
|
|
|
|
/* Set the TIM channels state */
|
|
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
|
|
8001566: 687b ldr r3, [r7, #4]
|
|
8001568: 2201 movs r2, #1
|
|
800156a: f883 203e strb.w r2, [r3, #62] ; 0x3e
|
|
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
|
|
800156e: 687b ldr r3, [r7, #4]
|
|
8001570: 2201 movs r2, #1
|
|
8001572: f883 203f strb.w r2, [r3, #63] ; 0x3f
|
|
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
|
|
8001576: 687b ldr r3, [r7, #4]
|
|
8001578: 2201 movs r2, #1
|
|
800157a: f883 2042 strb.w r2, [r3, #66] ; 0x42
|
|
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
|
|
800157e: 687b ldr r3, [r7, #4]
|
|
8001580: 2201 movs r2, #1
|
|
8001582: f883 2043 strb.w r2, [r3, #67] ; 0x43
|
|
|
|
/* Initialize the TIM state*/
|
|
htim->State = HAL_TIM_STATE_READY;
|
|
8001586: 687b ldr r3, [r7, #4]
|
|
8001588: 2201 movs r2, #1
|
|
800158a: f883 203d strb.w r2, [r3, #61] ; 0x3d
|
|
|
|
return HAL_OK;
|
|
800158e: 2300 movs r3, #0
|
|
}
|
|
8001590: 4618 mov r0, r3
|
|
8001592: 3718 adds r7, #24
|
|
8001594: 46bd mov sp, r7
|
|
8001596: bd80 pop {r7, pc}
|
|
|
|
08001598 <HAL_TIM_Encoder_Start>:
|
|
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
|
|
* @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
|
|
{
|
|
8001598: b580 push {r7, lr}
|
|
800159a: b084 sub sp, #16
|
|
800159c: af00 add r7, sp, #0
|
|
800159e: 6078 str r0, [r7, #4]
|
|
80015a0: 6039 str r1, [r7, #0]
|
|
HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
|
|
80015a2: 687b ldr r3, [r7, #4]
|
|
80015a4: f893 303e ldrb.w r3, [r3, #62] ; 0x3e
|
|
80015a8: 73fb strb r3, [r7, #15]
|
|
HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
|
|
80015aa: 687b ldr r3, [r7, #4]
|
|
80015ac: f893 303f ldrb.w r3, [r3, #63] ; 0x3f
|
|
80015b0: 73bb strb r3, [r7, #14]
|
|
HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
|
|
80015b2: 687b ldr r3, [r7, #4]
|
|
80015b4: f893 3042 ldrb.w r3, [r3, #66] ; 0x42
|
|
80015b8: 737b strb r3, [r7, #13]
|
|
HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
|
|
80015ba: 687b ldr r3, [r7, #4]
|
|
80015bc: f893 3043 ldrb.w r3, [r3, #67] ; 0x43
|
|
80015c0: 733b strb r3, [r7, #12]
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
|
|
|
|
/* Set the TIM channel(s) state */
|
|
if (Channel == TIM_CHANNEL_1)
|
|
80015c2: 683b ldr r3, [r7, #0]
|
|
80015c4: 2b00 cmp r3, #0
|
|
80015c6: d110 bne.n 80015ea <HAL_TIM_Encoder_Start+0x52>
|
|
{
|
|
if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
|
|
80015c8: 7bfb ldrb r3, [r7, #15]
|
|
80015ca: 2b01 cmp r3, #1
|
|
80015cc: d102 bne.n 80015d4 <HAL_TIM_Encoder_Start+0x3c>
|
|
|| (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY))
|
|
80015ce: 7b7b ldrb r3, [r7, #13]
|
|
80015d0: 2b01 cmp r3, #1
|
|
80015d2: d001 beq.n 80015d8 <HAL_TIM_Encoder_Start+0x40>
|
|
{
|
|
return HAL_ERROR;
|
|
80015d4: 2301 movs r3, #1
|
|
80015d6: e069 b.n 80016ac <HAL_TIM_Encoder_Start+0x114>
|
|
}
|
|
else
|
|
{
|
|
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
|
|
80015d8: 687b ldr r3, [r7, #4]
|
|
80015da: 2202 movs r2, #2
|
|
80015dc: f883 203e strb.w r2, [r3, #62] ; 0x3e
|
|
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
|
|
80015e0: 687b ldr r3, [r7, #4]
|
|
80015e2: 2202 movs r2, #2
|
|
80015e4: f883 2042 strb.w r2, [r3, #66] ; 0x42
|
|
80015e8: e031 b.n 800164e <HAL_TIM_Encoder_Start+0xb6>
|
|
}
|
|
}
|
|
else if (Channel == TIM_CHANNEL_2)
|
|
80015ea: 683b ldr r3, [r7, #0]
|
|
80015ec: 2b04 cmp r3, #4
|
|
80015ee: d110 bne.n 8001612 <HAL_TIM_Encoder_Start+0x7a>
|
|
{
|
|
if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
|
|
80015f0: 7bbb ldrb r3, [r7, #14]
|
|
80015f2: 2b01 cmp r3, #1
|
|
80015f4: d102 bne.n 80015fc <HAL_TIM_Encoder_Start+0x64>
|
|
|| (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
|
|
80015f6: 7b3b ldrb r3, [r7, #12]
|
|
80015f8: 2b01 cmp r3, #1
|
|
80015fa: d001 beq.n 8001600 <HAL_TIM_Encoder_Start+0x68>
|
|
{
|
|
return HAL_ERROR;
|
|
80015fc: 2301 movs r3, #1
|
|
80015fe: e055 b.n 80016ac <HAL_TIM_Encoder_Start+0x114>
|
|
}
|
|
else
|
|
{
|
|
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
|
|
8001600: 687b ldr r3, [r7, #4]
|
|
8001602: 2202 movs r2, #2
|
|
8001604: f883 203f strb.w r2, [r3, #63] ; 0x3f
|
|
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
|
|
8001608: 687b ldr r3, [r7, #4]
|
|
800160a: 2202 movs r2, #2
|
|
800160c: f883 2043 strb.w r2, [r3, #67] ; 0x43
|
|
8001610: e01d b.n 800164e <HAL_TIM_Encoder_Start+0xb6>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
|
|
8001612: 7bfb ldrb r3, [r7, #15]
|
|
8001614: 2b01 cmp r3, #1
|
|
8001616: d108 bne.n 800162a <HAL_TIM_Encoder_Start+0x92>
|
|
|| (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
|
|
8001618: 7bbb ldrb r3, [r7, #14]
|
|
800161a: 2b01 cmp r3, #1
|
|
800161c: d105 bne.n 800162a <HAL_TIM_Encoder_Start+0x92>
|
|
|| (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
|
|
800161e: 7b7b ldrb r3, [r7, #13]
|
|
8001620: 2b01 cmp r3, #1
|
|
8001622: d102 bne.n 800162a <HAL_TIM_Encoder_Start+0x92>
|
|
|| (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
|
|
8001624: 7b3b ldrb r3, [r7, #12]
|
|
8001626: 2b01 cmp r3, #1
|
|
8001628: d001 beq.n 800162e <HAL_TIM_Encoder_Start+0x96>
|
|
{
|
|
return HAL_ERROR;
|
|
800162a: 2301 movs r3, #1
|
|
800162c: e03e b.n 80016ac <HAL_TIM_Encoder_Start+0x114>
|
|
}
|
|
else
|
|
{
|
|
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
|
|
800162e: 687b ldr r3, [r7, #4]
|
|
8001630: 2202 movs r2, #2
|
|
8001632: f883 203e strb.w r2, [r3, #62] ; 0x3e
|
|
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
|
|
8001636: 687b ldr r3, [r7, #4]
|
|
8001638: 2202 movs r2, #2
|
|
800163a: f883 203f strb.w r2, [r3, #63] ; 0x3f
|
|
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
|
|
800163e: 687b ldr r3, [r7, #4]
|
|
8001640: 2202 movs r2, #2
|
|
8001642: f883 2042 strb.w r2, [r3, #66] ; 0x42
|
|
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
|
|
8001646: 687b ldr r3, [r7, #4]
|
|
8001648: 2202 movs r2, #2
|
|
800164a: f883 2043 strb.w r2, [r3, #67] ; 0x43
|
|
}
|
|
}
|
|
|
|
/* Enable the encoder interface channels */
|
|
switch (Channel)
|
|
800164e: 683b ldr r3, [r7, #0]
|
|
8001650: 2b00 cmp r3, #0
|
|
8001652: d003 beq.n 800165c <HAL_TIM_Encoder_Start+0xc4>
|
|
8001654: 683b ldr r3, [r7, #0]
|
|
8001656: 2b04 cmp r3, #4
|
|
8001658: d008 beq.n 800166c <HAL_TIM_Encoder_Start+0xd4>
|
|
800165a: e00f b.n 800167c <HAL_TIM_Encoder_Start+0xe4>
|
|
{
|
|
case TIM_CHANNEL_1:
|
|
{
|
|
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
|
|
800165c: 687b ldr r3, [r7, #4]
|
|
800165e: 681b ldr r3, [r3, #0]
|
|
8001660: 2201 movs r2, #1
|
|
8001662: 2100 movs r1, #0
|
|
8001664: 4618 mov r0, r3
|
|
8001666: f000 f887 bl 8001778 <TIM_CCxChannelCmd>
|
|
break;
|
|
800166a: e016 b.n 800169a <HAL_TIM_Encoder_Start+0x102>
|
|
}
|
|
|
|
case TIM_CHANNEL_2:
|
|
{
|
|
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
|
|
800166c: 687b ldr r3, [r7, #4]
|
|
800166e: 681b ldr r3, [r3, #0]
|
|
8001670: 2201 movs r2, #1
|
|
8001672: 2104 movs r1, #4
|
|
8001674: 4618 mov r0, r3
|
|
8001676: f000 f87f bl 8001778 <TIM_CCxChannelCmd>
|
|
break;
|
|
800167a: e00e b.n 800169a <HAL_TIM_Encoder_Start+0x102>
|
|
}
|
|
|
|
default :
|
|
{
|
|
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
|
|
800167c: 687b ldr r3, [r7, #4]
|
|
800167e: 681b ldr r3, [r3, #0]
|
|
8001680: 2201 movs r2, #1
|
|
8001682: 2100 movs r1, #0
|
|
8001684: 4618 mov r0, r3
|
|
8001686: f000 f877 bl 8001778 <TIM_CCxChannelCmd>
|
|
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
|
|
800168a: 687b ldr r3, [r7, #4]
|
|
800168c: 681b ldr r3, [r3, #0]
|
|
800168e: 2201 movs r2, #1
|
|
8001690: 2104 movs r1, #4
|
|
8001692: 4618 mov r0, r3
|
|
8001694: f000 f870 bl 8001778 <TIM_CCxChannelCmd>
|
|
break;
|
|
8001698: bf00 nop
|
|
}
|
|
}
|
|
/* Enable the Peripheral */
|
|
__HAL_TIM_ENABLE(htim);
|
|
800169a: 687b ldr r3, [r7, #4]
|
|
800169c: 681b ldr r3, [r3, #0]
|
|
800169e: 681a ldr r2, [r3, #0]
|
|
80016a0: 687b ldr r3, [r7, #4]
|
|
80016a2: 681b ldr r3, [r3, #0]
|
|
80016a4: f042 0201 orr.w r2, r2, #1
|
|
80016a8: 601a str r2, [r3, #0]
|
|
|
|
/* Return function status */
|
|
return HAL_OK;
|
|
80016aa: 2300 movs r3, #0
|
|
}
|
|
80016ac: 4618 mov r0, r3
|
|
80016ae: 3710 adds r7, #16
|
|
80016b0: 46bd mov sp, r7
|
|
80016b2: bd80 pop {r7, pc}
|
|
|
|
080016b4 <TIM_Base_SetConfig>:
|
|
* @param TIMx TIM peripheral
|
|
* @param Structure TIM Base configuration structure
|
|
* @retval None
|
|
*/
|
|
void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
|
|
{
|
|
80016b4: b480 push {r7}
|
|
80016b6: b085 sub sp, #20
|
|
80016b8: af00 add r7, sp, #0
|
|
80016ba: 6078 str r0, [r7, #4]
|
|
80016bc: 6039 str r1, [r7, #0]
|
|
uint32_t tmpcr1;
|
|
tmpcr1 = TIMx->CR1;
|
|
80016be: 687b ldr r3, [r7, #4]
|
|
80016c0: 681b ldr r3, [r3, #0]
|
|
80016c2: 60fb str r3, [r7, #12]
|
|
|
|
/* Set TIM Time Base Unit parameters ---------------------------------------*/
|
|
if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
|
|
80016c4: 687b ldr r3, [r7, #4]
|
|
80016c6: 4a29 ldr r2, [pc, #164] ; (800176c <TIM_Base_SetConfig+0xb8>)
|
|
80016c8: 4293 cmp r3, r2
|
|
80016ca: d00b beq.n 80016e4 <TIM_Base_SetConfig+0x30>
|
|
80016cc: 687b ldr r3, [r7, #4]
|
|
80016ce: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
|
|
80016d2: d007 beq.n 80016e4 <TIM_Base_SetConfig+0x30>
|
|
80016d4: 687b ldr r3, [r7, #4]
|
|
80016d6: 4a26 ldr r2, [pc, #152] ; (8001770 <TIM_Base_SetConfig+0xbc>)
|
|
80016d8: 4293 cmp r3, r2
|
|
80016da: d003 beq.n 80016e4 <TIM_Base_SetConfig+0x30>
|
|
80016dc: 687b ldr r3, [r7, #4]
|
|
80016de: 4a25 ldr r2, [pc, #148] ; (8001774 <TIM_Base_SetConfig+0xc0>)
|
|
80016e0: 4293 cmp r3, r2
|
|
80016e2: d108 bne.n 80016f6 <TIM_Base_SetConfig+0x42>
|
|
{
|
|
/* Select the Counter Mode */
|
|
tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
|
|
80016e4: 68fb ldr r3, [r7, #12]
|
|
80016e6: f023 0370 bic.w r3, r3, #112 ; 0x70
|
|
80016ea: 60fb str r3, [r7, #12]
|
|
tmpcr1 |= Structure->CounterMode;
|
|
80016ec: 683b ldr r3, [r7, #0]
|
|
80016ee: 685b ldr r3, [r3, #4]
|
|
80016f0: 68fa ldr r2, [r7, #12]
|
|
80016f2: 4313 orrs r3, r2
|
|
80016f4: 60fb str r3, [r7, #12]
|
|
}
|
|
|
|
if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
|
|
80016f6: 687b ldr r3, [r7, #4]
|
|
80016f8: 4a1c ldr r2, [pc, #112] ; (800176c <TIM_Base_SetConfig+0xb8>)
|
|
80016fa: 4293 cmp r3, r2
|
|
80016fc: d00b beq.n 8001716 <TIM_Base_SetConfig+0x62>
|
|
80016fe: 687b ldr r3, [r7, #4]
|
|
8001700: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
|
|
8001704: d007 beq.n 8001716 <TIM_Base_SetConfig+0x62>
|
|
8001706: 687b ldr r3, [r7, #4]
|
|
8001708: 4a19 ldr r2, [pc, #100] ; (8001770 <TIM_Base_SetConfig+0xbc>)
|
|
800170a: 4293 cmp r3, r2
|
|
800170c: d003 beq.n 8001716 <TIM_Base_SetConfig+0x62>
|
|
800170e: 687b ldr r3, [r7, #4]
|
|
8001710: 4a18 ldr r2, [pc, #96] ; (8001774 <TIM_Base_SetConfig+0xc0>)
|
|
8001712: 4293 cmp r3, r2
|
|
8001714: d108 bne.n 8001728 <TIM_Base_SetConfig+0x74>
|
|
{
|
|
/* Set the clock division */
|
|
tmpcr1 &= ~TIM_CR1_CKD;
|
|
8001716: 68fb ldr r3, [r7, #12]
|
|
8001718: f423 7340 bic.w r3, r3, #768 ; 0x300
|
|
800171c: 60fb str r3, [r7, #12]
|
|
tmpcr1 |= (uint32_t)Structure->ClockDivision;
|
|
800171e: 683b ldr r3, [r7, #0]
|
|
8001720: 68db ldr r3, [r3, #12]
|
|
8001722: 68fa ldr r2, [r7, #12]
|
|
8001724: 4313 orrs r3, r2
|
|
8001726: 60fb str r3, [r7, #12]
|
|
}
|
|
|
|
/* Set the auto-reload preload */
|
|
MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
|
|
8001728: 68fb ldr r3, [r7, #12]
|
|
800172a: f023 0280 bic.w r2, r3, #128 ; 0x80
|
|
800172e: 683b ldr r3, [r7, #0]
|
|
8001730: 695b ldr r3, [r3, #20]
|
|
8001732: 4313 orrs r3, r2
|
|
8001734: 60fb str r3, [r7, #12]
|
|
|
|
TIMx->CR1 = tmpcr1;
|
|
8001736: 687b ldr r3, [r7, #4]
|
|
8001738: 68fa ldr r2, [r7, #12]
|
|
800173a: 601a str r2, [r3, #0]
|
|
|
|
/* Set the Autoreload value */
|
|
TIMx->ARR = (uint32_t)Structure->Period ;
|
|
800173c: 683b ldr r3, [r7, #0]
|
|
800173e: 689a ldr r2, [r3, #8]
|
|
8001740: 687b ldr r3, [r7, #4]
|
|
8001742: 62da str r2, [r3, #44] ; 0x2c
|
|
|
|
/* Set the Prescaler value */
|
|
TIMx->PSC = Structure->Prescaler;
|
|
8001744: 683b ldr r3, [r7, #0]
|
|
8001746: 681a ldr r2, [r3, #0]
|
|
8001748: 687b ldr r3, [r7, #4]
|
|
800174a: 629a str r2, [r3, #40] ; 0x28
|
|
|
|
if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
|
|
800174c: 687b ldr r3, [r7, #4]
|
|
800174e: 4a07 ldr r2, [pc, #28] ; (800176c <TIM_Base_SetConfig+0xb8>)
|
|
8001750: 4293 cmp r3, r2
|
|
8001752: d103 bne.n 800175c <TIM_Base_SetConfig+0xa8>
|
|
{
|
|
/* Set the Repetition Counter value */
|
|
TIMx->RCR = Structure->RepetitionCounter;
|
|
8001754: 683b ldr r3, [r7, #0]
|
|
8001756: 691a ldr r2, [r3, #16]
|
|
8001758: 687b ldr r3, [r7, #4]
|
|
800175a: 631a str r2, [r3, #48] ; 0x30
|
|
}
|
|
|
|
/* Generate an update event to reload the Prescaler
|
|
and the repetition counter (only for advanced timer) value immediately */
|
|
TIMx->EGR = TIM_EGR_UG;
|
|
800175c: 687b ldr r3, [r7, #4]
|
|
800175e: 2201 movs r2, #1
|
|
8001760: 615a str r2, [r3, #20]
|
|
}
|
|
8001762: bf00 nop
|
|
8001764: 3714 adds r7, #20
|
|
8001766: 46bd mov sp, r7
|
|
8001768: bc80 pop {r7}
|
|
800176a: 4770 bx lr
|
|
800176c: 40012c00 .word 0x40012c00
|
|
8001770: 40000400 .word 0x40000400
|
|
8001774: 40000800 .word 0x40000800
|
|
|
|
08001778 <TIM_CCxChannelCmd>:
|
|
* @param ChannelState specifies the TIM Channel CCxE bit new state.
|
|
* This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE.
|
|
* @retval None
|
|
*/
|
|
void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)
|
|
{
|
|
8001778: b480 push {r7}
|
|
800177a: b087 sub sp, #28
|
|
800177c: af00 add r7, sp, #0
|
|
800177e: 60f8 str r0, [r7, #12]
|
|
8001780: 60b9 str r1, [r7, #8]
|
|
8001782: 607a str r2, [r7, #4]
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_CC1_INSTANCE(TIMx));
|
|
assert_param(IS_TIM_CHANNELS(Channel));
|
|
|
|
tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */
|
|
8001784: 68bb ldr r3, [r7, #8]
|
|
8001786: f003 031f and.w r3, r3, #31
|
|
800178a: 2201 movs r2, #1
|
|
800178c: fa02 f303 lsl.w r3, r2, r3
|
|
8001790: 617b str r3, [r7, #20]
|
|
|
|
/* Reset the CCxE Bit */
|
|
TIMx->CCER &= ~tmp;
|
|
8001792: 68fb ldr r3, [r7, #12]
|
|
8001794: 6a1a ldr r2, [r3, #32]
|
|
8001796: 697b ldr r3, [r7, #20]
|
|
8001798: 43db mvns r3, r3
|
|
800179a: 401a ands r2, r3
|
|
800179c: 68fb ldr r3, [r7, #12]
|
|
800179e: 621a str r2, [r3, #32]
|
|
|
|
/* Set or reset the CCxE Bit */
|
|
TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
|
|
80017a0: 68fb ldr r3, [r7, #12]
|
|
80017a2: 6a1a ldr r2, [r3, #32]
|
|
80017a4: 68bb ldr r3, [r7, #8]
|
|
80017a6: f003 031f and.w r3, r3, #31
|
|
80017aa: 6879 ldr r1, [r7, #4]
|
|
80017ac: fa01 f303 lsl.w r3, r1, r3
|
|
80017b0: 431a orrs r2, r3
|
|
80017b2: 68fb ldr r3, [r7, #12]
|
|
80017b4: 621a str r2, [r3, #32]
|
|
}
|
|
80017b6: bf00 nop
|
|
80017b8: 371c adds r7, #28
|
|
80017ba: 46bd mov sp, r7
|
|
80017bc: bc80 pop {r7}
|
|
80017be: 4770 bx lr
|
|
|
|
080017c0 <HAL_TIMEx_MasterConfigSynchronization>:
|
|
* mode.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
|
|
TIM_MasterConfigTypeDef *sMasterConfig)
|
|
{
|
|
80017c0: b480 push {r7}
|
|
80017c2: b085 sub sp, #20
|
|
80017c4: af00 add r7, sp, #0
|
|
80017c6: 6078 str r0, [r7, #4]
|
|
80017c8: 6039 str r1, [r7, #0]
|
|
assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
|
|
assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
|
|
assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
|
|
|
|
/* Check input state */
|
|
__HAL_LOCK(htim);
|
|
80017ca: 687b ldr r3, [r7, #4]
|
|
80017cc: f893 303c ldrb.w r3, [r3, #60] ; 0x3c
|
|
80017d0: 2b01 cmp r3, #1
|
|
80017d2: d101 bne.n 80017d8 <HAL_TIMEx_MasterConfigSynchronization+0x18>
|
|
80017d4: 2302 movs r3, #2
|
|
80017d6: e046 b.n 8001866 <HAL_TIMEx_MasterConfigSynchronization+0xa6>
|
|
80017d8: 687b ldr r3, [r7, #4]
|
|
80017da: 2201 movs r2, #1
|
|
80017dc: f883 203c strb.w r2, [r3, #60] ; 0x3c
|
|
|
|
/* Change the handler state */
|
|
htim->State = HAL_TIM_STATE_BUSY;
|
|
80017e0: 687b ldr r3, [r7, #4]
|
|
80017e2: 2202 movs r2, #2
|
|
80017e4: f883 203d strb.w r2, [r3, #61] ; 0x3d
|
|
|
|
/* Get the TIMx CR2 register value */
|
|
tmpcr2 = htim->Instance->CR2;
|
|
80017e8: 687b ldr r3, [r7, #4]
|
|
80017ea: 681b ldr r3, [r3, #0]
|
|
80017ec: 685b ldr r3, [r3, #4]
|
|
80017ee: 60fb str r3, [r7, #12]
|
|
|
|
/* Get the TIMx SMCR register value */
|
|
tmpsmcr = htim->Instance->SMCR;
|
|
80017f0: 687b ldr r3, [r7, #4]
|
|
80017f2: 681b ldr r3, [r3, #0]
|
|
80017f4: 689b ldr r3, [r3, #8]
|
|
80017f6: 60bb str r3, [r7, #8]
|
|
|
|
/* Reset the MMS Bits */
|
|
tmpcr2 &= ~TIM_CR2_MMS;
|
|
80017f8: 68fb ldr r3, [r7, #12]
|
|
80017fa: f023 0370 bic.w r3, r3, #112 ; 0x70
|
|
80017fe: 60fb str r3, [r7, #12]
|
|
/* Select the TRGO source */
|
|
tmpcr2 |= sMasterConfig->MasterOutputTrigger;
|
|
8001800: 683b ldr r3, [r7, #0]
|
|
8001802: 681b ldr r3, [r3, #0]
|
|
8001804: 68fa ldr r2, [r7, #12]
|
|
8001806: 4313 orrs r3, r2
|
|
8001808: 60fb str r3, [r7, #12]
|
|
|
|
/* Update TIMx CR2 */
|
|
htim->Instance->CR2 = tmpcr2;
|
|
800180a: 687b ldr r3, [r7, #4]
|
|
800180c: 681b ldr r3, [r3, #0]
|
|
800180e: 68fa ldr r2, [r7, #12]
|
|
8001810: 605a str r2, [r3, #4]
|
|
|
|
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
|
|
8001812: 687b ldr r3, [r7, #4]
|
|
8001814: 681b ldr r3, [r3, #0]
|
|
8001816: 4a16 ldr r2, [pc, #88] ; (8001870 <HAL_TIMEx_MasterConfigSynchronization+0xb0>)
|
|
8001818: 4293 cmp r3, r2
|
|
800181a: d00e beq.n 800183a <HAL_TIMEx_MasterConfigSynchronization+0x7a>
|
|
800181c: 687b ldr r3, [r7, #4]
|
|
800181e: 681b ldr r3, [r3, #0]
|
|
8001820: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
|
|
8001824: d009 beq.n 800183a <HAL_TIMEx_MasterConfigSynchronization+0x7a>
|
|
8001826: 687b ldr r3, [r7, #4]
|
|
8001828: 681b ldr r3, [r3, #0]
|
|
800182a: 4a12 ldr r2, [pc, #72] ; (8001874 <HAL_TIMEx_MasterConfigSynchronization+0xb4>)
|
|
800182c: 4293 cmp r3, r2
|
|
800182e: d004 beq.n 800183a <HAL_TIMEx_MasterConfigSynchronization+0x7a>
|
|
8001830: 687b ldr r3, [r7, #4]
|
|
8001832: 681b ldr r3, [r3, #0]
|
|
8001834: 4a10 ldr r2, [pc, #64] ; (8001878 <HAL_TIMEx_MasterConfigSynchronization+0xb8>)
|
|
8001836: 4293 cmp r3, r2
|
|
8001838: d10c bne.n 8001854 <HAL_TIMEx_MasterConfigSynchronization+0x94>
|
|
{
|
|
/* Reset the MSM Bit */
|
|
tmpsmcr &= ~TIM_SMCR_MSM;
|
|
800183a: 68bb ldr r3, [r7, #8]
|
|
800183c: f023 0380 bic.w r3, r3, #128 ; 0x80
|
|
8001840: 60bb str r3, [r7, #8]
|
|
/* Set master mode */
|
|
tmpsmcr |= sMasterConfig->MasterSlaveMode;
|
|
8001842: 683b ldr r3, [r7, #0]
|
|
8001844: 685b ldr r3, [r3, #4]
|
|
8001846: 68ba ldr r2, [r7, #8]
|
|
8001848: 4313 orrs r3, r2
|
|
800184a: 60bb str r3, [r7, #8]
|
|
|
|
/* Update TIMx SMCR */
|
|
htim->Instance->SMCR = tmpsmcr;
|
|
800184c: 687b ldr r3, [r7, #4]
|
|
800184e: 681b ldr r3, [r3, #0]
|
|
8001850: 68ba ldr r2, [r7, #8]
|
|
8001852: 609a str r2, [r3, #8]
|
|
}
|
|
|
|
/* Change the htim state */
|
|
htim->State = HAL_TIM_STATE_READY;
|
|
8001854: 687b ldr r3, [r7, #4]
|
|
8001856: 2201 movs r2, #1
|
|
8001858: f883 203d strb.w r2, [r3, #61] ; 0x3d
|
|
|
|
__HAL_UNLOCK(htim);
|
|
800185c: 687b ldr r3, [r7, #4]
|
|
800185e: 2200 movs r2, #0
|
|
8001860: f883 203c strb.w r2, [r3, #60] ; 0x3c
|
|
|
|
return HAL_OK;
|
|
8001864: 2300 movs r3, #0
|
|
}
|
|
8001866: 4618 mov r0, r3
|
|
8001868: 3714 adds r7, #20
|
|
800186a: 46bd mov sp, r7
|
|
800186c: bc80 pop {r7}
|
|
800186e: 4770 bx lr
|
|
8001870: 40012c00 .word 0x40012c00
|
|
8001874: 40000400 .word 0x40000400
|
|
8001878: 40000800 .word 0x40000800
|
|
|
|
0800187c <HAL_UART_Init>:
|
|
* @param huart Pointer to a UART_HandleTypeDef structure that contains
|
|
* the configuration information for the specified UART module.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
|
|
{
|
|
800187c: b580 push {r7, lr}
|
|
800187e: b082 sub sp, #8
|
|
8001880: af00 add r7, sp, #0
|
|
8001882: 6078 str r0, [r7, #4]
|
|
/* Check the UART handle allocation */
|
|
if (huart == NULL)
|
|
8001884: 687b ldr r3, [r7, #4]
|
|
8001886: 2b00 cmp r3, #0
|
|
8001888: d101 bne.n 800188e <HAL_UART_Init+0x12>
|
|
{
|
|
return HAL_ERROR;
|
|
800188a: 2301 movs r3, #1
|
|
800188c: e03f b.n 800190e <HAL_UART_Init+0x92>
|
|
assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));
|
|
#if defined(USART_CR1_OVER8)
|
|
assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling));
|
|
#endif /* USART_CR1_OVER8 */
|
|
|
|
if (huart->gState == HAL_UART_STATE_RESET)
|
|
800188e: 687b ldr r3, [r7, #4]
|
|
8001890: f893 303d ldrb.w r3, [r3, #61] ; 0x3d
|
|
8001894: b2db uxtb r3, r3
|
|
8001896: 2b00 cmp r3, #0
|
|
8001898: d106 bne.n 80018a8 <HAL_UART_Init+0x2c>
|
|
{
|
|
/* Allocate lock resource and initialize it */
|
|
huart->Lock = HAL_UNLOCKED;
|
|
800189a: 687b ldr r3, [r7, #4]
|
|
800189c: 2200 movs r2, #0
|
|
800189e: f883 203c strb.w r2, [r3, #60] ; 0x3c
|
|
|
|
/* Init the low level hardware */
|
|
huart->MspInitCallback(huart);
|
|
#else
|
|
/* Init the low level hardware : GPIO, CLOCK */
|
|
HAL_UART_MspInit(huart);
|
|
80018a2: 6878 ldr r0, [r7, #4]
|
|
80018a4: f7fe fe5e bl 8000564 <HAL_UART_MspInit>
|
|
#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
|
|
}
|
|
|
|
huart->gState = HAL_UART_STATE_BUSY;
|
|
80018a8: 687b ldr r3, [r7, #4]
|
|
80018aa: 2224 movs r2, #36 ; 0x24
|
|
80018ac: f883 203d strb.w r2, [r3, #61] ; 0x3d
|
|
|
|
/* Disable the peripheral */
|
|
__HAL_UART_DISABLE(huart);
|
|
80018b0: 687b ldr r3, [r7, #4]
|
|
80018b2: 681b ldr r3, [r3, #0]
|
|
80018b4: 68da ldr r2, [r3, #12]
|
|
80018b6: 687b ldr r3, [r7, #4]
|
|
80018b8: 681b ldr r3, [r3, #0]
|
|
80018ba: f422 5200 bic.w r2, r2, #8192 ; 0x2000
|
|
80018be: 60da str r2, [r3, #12]
|
|
|
|
/* Set the UART Communication parameters */
|
|
UART_SetConfig(huart);
|
|
80018c0: 6878 ldr r0, [r7, #4]
|
|
80018c2: f000 f905 bl 8001ad0 <UART_SetConfig>
|
|
|
|
/* In asynchronous mode, the following bits must be kept cleared:
|
|
- LINEN and CLKEN bits in the USART_CR2 register,
|
|
- SCEN, HDSEL and IREN bits in the USART_CR3 register.*/
|
|
CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
|
|
80018c6: 687b ldr r3, [r7, #4]
|
|
80018c8: 681b ldr r3, [r3, #0]
|
|
80018ca: 691a ldr r2, [r3, #16]
|
|
80018cc: 687b ldr r3, [r7, #4]
|
|
80018ce: 681b ldr r3, [r3, #0]
|
|
80018d0: f422 4290 bic.w r2, r2, #18432 ; 0x4800
|
|
80018d4: 611a str r2, [r3, #16]
|
|
CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
|
|
80018d6: 687b ldr r3, [r7, #4]
|
|
80018d8: 681b ldr r3, [r3, #0]
|
|
80018da: 695a ldr r2, [r3, #20]
|
|
80018dc: 687b ldr r3, [r7, #4]
|
|
80018de: 681b ldr r3, [r3, #0]
|
|
80018e0: f022 022a bic.w r2, r2, #42 ; 0x2a
|
|
80018e4: 615a str r2, [r3, #20]
|
|
|
|
/* Enable the peripheral */
|
|
__HAL_UART_ENABLE(huart);
|
|
80018e6: 687b ldr r3, [r7, #4]
|
|
80018e8: 681b ldr r3, [r3, #0]
|
|
80018ea: 68da ldr r2, [r3, #12]
|
|
80018ec: 687b ldr r3, [r7, #4]
|
|
80018ee: 681b ldr r3, [r3, #0]
|
|
80018f0: f442 5200 orr.w r2, r2, #8192 ; 0x2000
|
|
80018f4: 60da str r2, [r3, #12]
|
|
|
|
/* Initialize the UART state */
|
|
huart->ErrorCode = HAL_UART_ERROR_NONE;
|
|
80018f6: 687b ldr r3, [r7, #4]
|
|
80018f8: 2200 movs r2, #0
|
|
80018fa: 641a str r2, [r3, #64] ; 0x40
|
|
huart->gState = HAL_UART_STATE_READY;
|
|
80018fc: 687b ldr r3, [r7, #4]
|
|
80018fe: 2220 movs r2, #32
|
|
8001900: f883 203d strb.w r2, [r3, #61] ; 0x3d
|
|
huart->RxState = HAL_UART_STATE_READY;
|
|
8001904: 687b ldr r3, [r7, #4]
|
|
8001906: 2220 movs r2, #32
|
|
8001908: f883 203e strb.w r2, [r3, #62] ; 0x3e
|
|
|
|
return HAL_OK;
|
|
800190c: 2300 movs r3, #0
|
|
}
|
|
800190e: 4618 mov r0, r3
|
|
8001910: 3708 adds r7, #8
|
|
8001912: 46bd mov sp, r7
|
|
8001914: bd80 pop {r7, pc}
|
|
|
|
08001916 <HAL_UART_Transmit>:
|
|
* @param Size Amount of data elements (u8 or u16) to be sent
|
|
* @param Timeout Timeout duration
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
|
|
{
|
|
8001916: b580 push {r7, lr}
|
|
8001918: b08a sub sp, #40 ; 0x28
|
|
800191a: af02 add r7, sp, #8
|
|
800191c: 60f8 str r0, [r7, #12]
|
|
800191e: 60b9 str r1, [r7, #8]
|
|
8001920: 603b str r3, [r7, #0]
|
|
8001922: 4613 mov r3, r2
|
|
8001924: 80fb strh r3, [r7, #6]
|
|
uint8_t *pdata8bits;
|
|
uint16_t *pdata16bits;
|
|
uint32_t tickstart = 0U;
|
|
8001926: 2300 movs r3, #0
|
|
8001928: 617b str r3, [r7, #20]
|
|
|
|
/* Check that a Tx process is not already ongoing */
|
|
if (huart->gState == HAL_UART_STATE_READY)
|
|
800192a: 68fb ldr r3, [r7, #12]
|
|
800192c: f893 303d ldrb.w r3, [r3, #61] ; 0x3d
|
|
8001930: b2db uxtb r3, r3
|
|
8001932: 2b20 cmp r3, #32
|
|
8001934: d17c bne.n 8001a30 <HAL_UART_Transmit+0x11a>
|
|
{
|
|
if ((pData == NULL) || (Size == 0U))
|
|
8001936: 68bb ldr r3, [r7, #8]
|
|
8001938: 2b00 cmp r3, #0
|
|
800193a: d002 beq.n 8001942 <HAL_UART_Transmit+0x2c>
|
|
800193c: 88fb ldrh r3, [r7, #6]
|
|
800193e: 2b00 cmp r3, #0
|
|
8001940: d101 bne.n 8001946 <HAL_UART_Transmit+0x30>
|
|
{
|
|
return HAL_ERROR;
|
|
8001942: 2301 movs r3, #1
|
|
8001944: e075 b.n 8001a32 <HAL_UART_Transmit+0x11c>
|
|
}
|
|
|
|
/* Process Locked */
|
|
__HAL_LOCK(huart);
|
|
8001946: 68fb ldr r3, [r7, #12]
|
|
8001948: f893 303c ldrb.w r3, [r3, #60] ; 0x3c
|
|
800194c: 2b01 cmp r3, #1
|
|
800194e: d101 bne.n 8001954 <HAL_UART_Transmit+0x3e>
|
|
8001950: 2302 movs r3, #2
|
|
8001952: e06e b.n 8001a32 <HAL_UART_Transmit+0x11c>
|
|
8001954: 68fb ldr r3, [r7, #12]
|
|
8001956: 2201 movs r2, #1
|
|
8001958: f883 203c strb.w r2, [r3, #60] ; 0x3c
|
|
|
|
huart->ErrorCode = HAL_UART_ERROR_NONE;
|
|
800195c: 68fb ldr r3, [r7, #12]
|
|
800195e: 2200 movs r2, #0
|
|
8001960: 641a str r2, [r3, #64] ; 0x40
|
|
huart->gState = HAL_UART_STATE_BUSY_TX;
|
|
8001962: 68fb ldr r3, [r7, #12]
|
|
8001964: 2221 movs r2, #33 ; 0x21
|
|
8001966: f883 203d strb.w r2, [r3, #61] ; 0x3d
|
|
|
|
/* Init tickstart for timeout management */
|
|
tickstart = HAL_GetTick();
|
|
800196a: f7fe fec3 bl 80006f4 <HAL_GetTick>
|
|
800196e: 6178 str r0, [r7, #20]
|
|
|
|
huart->TxXferSize = Size;
|
|
8001970: 68fb ldr r3, [r7, #12]
|
|
8001972: 88fa ldrh r2, [r7, #6]
|
|
8001974: 849a strh r2, [r3, #36] ; 0x24
|
|
huart->TxXferCount = Size;
|
|
8001976: 68fb ldr r3, [r7, #12]
|
|
8001978: 88fa ldrh r2, [r7, #6]
|
|
800197a: 84da strh r2, [r3, #38] ; 0x26
|
|
|
|
/* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */
|
|
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
|
|
800197c: 68fb ldr r3, [r7, #12]
|
|
800197e: 689b ldr r3, [r3, #8]
|
|
8001980: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
|
|
8001984: d108 bne.n 8001998 <HAL_UART_Transmit+0x82>
|
|
8001986: 68fb ldr r3, [r7, #12]
|
|
8001988: 691b ldr r3, [r3, #16]
|
|
800198a: 2b00 cmp r3, #0
|
|
800198c: d104 bne.n 8001998 <HAL_UART_Transmit+0x82>
|
|
{
|
|
pdata8bits = NULL;
|
|
800198e: 2300 movs r3, #0
|
|
8001990: 61fb str r3, [r7, #28]
|
|
pdata16bits = (uint16_t *) pData;
|
|
8001992: 68bb ldr r3, [r7, #8]
|
|
8001994: 61bb str r3, [r7, #24]
|
|
8001996: e003 b.n 80019a0 <HAL_UART_Transmit+0x8a>
|
|
}
|
|
else
|
|
{
|
|
pdata8bits = pData;
|
|
8001998: 68bb ldr r3, [r7, #8]
|
|
800199a: 61fb str r3, [r7, #28]
|
|
pdata16bits = NULL;
|
|
800199c: 2300 movs r3, #0
|
|
800199e: 61bb str r3, [r7, #24]
|
|
}
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(huart);
|
|
80019a0: 68fb ldr r3, [r7, #12]
|
|
80019a2: 2200 movs r2, #0
|
|
80019a4: f883 203c strb.w r2, [r3, #60] ; 0x3c
|
|
|
|
while (huart->TxXferCount > 0U)
|
|
80019a8: e02a b.n 8001a00 <HAL_UART_Transmit+0xea>
|
|
{
|
|
if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
|
|
80019aa: 683b ldr r3, [r7, #0]
|
|
80019ac: 9300 str r3, [sp, #0]
|
|
80019ae: 697b ldr r3, [r7, #20]
|
|
80019b0: 2200 movs r2, #0
|
|
80019b2: 2180 movs r1, #128 ; 0x80
|
|
80019b4: 68f8 ldr r0, [r7, #12]
|
|
80019b6: f000 f840 bl 8001a3a <UART_WaitOnFlagUntilTimeout>
|
|
80019ba: 4603 mov r3, r0
|
|
80019bc: 2b00 cmp r3, #0
|
|
80019be: d001 beq.n 80019c4 <HAL_UART_Transmit+0xae>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
80019c0: 2303 movs r3, #3
|
|
80019c2: e036 b.n 8001a32 <HAL_UART_Transmit+0x11c>
|
|
}
|
|
if (pdata8bits == NULL)
|
|
80019c4: 69fb ldr r3, [r7, #28]
|
|
80019c6: 2b00 cmp r3, #0
|
|
80019c8: d10b bne.n 80019e2 <HAL_UART_Transmit+0xcc>
|
|
{
|
|
huart->Instance->DR = (uint16_t)(*pdata16bits & 0x01FFU);
|
|
80019ca: 69bb ldr r3, [r7, #24]
|
|
80019cc: 881b ldrh r3, [r3, #0]
|
|
80019ce: 461a mov r2, r3
|
|
80019d0: 68fb ldr r3, [r7, #12]
|
|
80019d2: 681b ldr r3, [r3, #0]
|
|
80019d4: f3c2 0208 ubfx r2, r2, #0, #9
|
|
80019d8: 605a str r2, [r3, #4]
|
|
pdata16bits++;
|
|
80019da: 69bb ldr r3, [r7, #24]
|
|
80019dc: 3302 adds r3, #2
|
|
80019de: 61bb str r3, [r7, #24]
|
|
80019e0: e007 b.n 80019f2 <HAL_UART_Transmit+0xdc>
|
|
}
|
|
else
|
|
{
|
|
huart->Instance->DR = (uint8_t)(*pdata8bits & 0xFFU);
|
|
80019e2: 69fb ldr r3, [r7, #28]
|
|
80019e4: 781a ldrb r2, [r3, #0]
|
|
80019e6: 68fb ldr r3, [r7, #12]
|
|
80019e8: 681b ldr r3, [r3, #0]
|
|
80019ea: 605a str r2, [r3, #4]
|
|
pdata8bits++;
|
|
80019ec: 69fb ldr r3, [r7, #28]
|
|
80019ee: 3301 adds r3, #1
|
|
80019f0: 61fb str r3, [r7, #28]
|
|
}
|
|
huart->TxXferCount--;
|
|
80019f2: 68fb ldr r3, [r7, #12]
|
|
80019f4: 8cdb ldrh r3, [r3, #38] ; 0x26
|
|
80019f6: b29b uxth r3, r3
|
|
80019f8: 3b01 subs r3, #1
|
|
80019fa: b29a uxth r2, r3
|
|
80019fc: 68fb ldr r3, [r7, #12]
|
|
80019fe: 84da strh r2, [r3, #38] ; 0x26
|
|
while (huart->TxXferCount > 0U)
|
|
8001a00: 68fb ldr r3, [r7, #12]
|
|
8001a02: 8cdb ldrh r3, [r3, #38] ; 0x26
|
|
8001a04: b29b uxth r3, r3
|
|
8001a06: 2b00 cmp r3, #0
|
|
8001a08: d1cf bne.n 80019aa <HAL_UART_Transmit+0x94>
|
|
}
|
|
|
|
if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
|
|
8001a0a: 683b ldr r3, [r7, #0]
|
|
8001a0c: 9300 str r3, [sp, #0]
|
|
8001a0e: 697b ldr r3, [r7, #20]
|
|
8001a10: 2200 movs r2, #0
|
|
8001a12: 2140 movs r1, #64 ; 0x40
|
|
8001a14: 68f8 ldr r0, [r7, #12]
|
|
8001a16: f000 f810 bl 8001a3a <UART_WaitOnFlagUntilTimeout>
|
|
8001a1a: 4603 mov r3, r0
|
|
8001a1c: 2b00 cmp r3, #0
|
|
8001a1e: d001 beq.n 8001a24 <HAL_UART_Transmit+0x10e>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8001a20: 2303 movs r3, #3
|
|
8001a22: e006 b.n 8001a32 <HAL_UART_Transmit+0x11c>
|
|
}
|
|
|
|
/* At end of Tx process, restore huart->gState to Ready */
|
|
huart->gState = HAL_UART_STATE_READY;
|
|
8001a24: 68fb ldr r3, [r7, #12]
|
|
8001a26: 2220 movs r2, #32
|
|
8001a28: f883 203d strb.w r2, [r3, #61] ; 0x3d
|
|
|
|
return HAL_OK;
|
|
8001a2c: 2300 movs r3, #0
|
|
8001a2e: e000 b.n 8001a32 <HAL_UART_Transmit+0x11c>
|
|
}
|
|
else
|
|
{
|
|
return HAL_BUSY;
|
|
8001a30: 2302 movs r3, #2
|
|
}
|
|
}
|
|
8001a32: 4618 mov r0, r3
|
|
8001a34: 3720 adds r7, #32
|
|
8001a36: 46bd mov sp, r7
|
|
8001a38: bd80 pop {r7, pc}
|
|
|
|
08001a3a <UART_WaitOnFlagUntilTimeout>:
|
|
* @param Tickstart Tick start value
|
|
* @param Timeout Timeout duration
|
|
* @retval HAL status
|
|
*/
|
|
static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
|
|
{
|
|
8001a3a: b580 push {r7, lr}
|
|
8001a3c: b084 sub sp, #16
|
|
8001a3e: af00 add r7, sp, #0
|
|
8001a40: 60f8 str r0, [r7, #12]
|
|
8001a42: 60b9 str r1, [r7, #8]
|
|
8001a44: 603b str r3, [r7, #0]
|
|
8001a46: 4613 mov r3, r2
|
|
8001a48: 71fb strb r3, [r7, #7]
|
|
/* Wait until flag is set */
|
|
while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
|
|
8001a4a: e02c b.n 8001aa6 <UART_WaitOnFlagUntilTimeout+0x6c>
|
|
{
|
|
/* Check for the Timeout */
|
|
if (Timeout != HAL_MAX_DELAY)
|
|
8001a4c: 69bb ldr r3, [r7, #24]
|
|
8001a4e: f1b3 3fff cmp.w r3, #4294967295
|
|
8001a52: d028 beq.n 8001aa6 <UART_WaitOnFlagUntilTimeout+0x6c>
|
|
{
|
|
if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout))
|
|
8001a54: 69bb ldr r3, [r7, #24]
|
|
8001a56: 2b00 cmp r3, #0
|
|
8001a58: d007 beq.n 8001a6a <UART_WaitOnFlagUntilTimeout+0x30>
|
|
8001a5a: f7fe fe4b bl 80006f4 <HAL_GetTick>
|
|
8001a5e: 4602 mov r2, r0
|
|
8001a60: 683b ldr r3, [r7, #0]
|
|
8001a62: 1ad3 subs r3, r2, r3
|
|
8001a64: 69ba ldr r2, [r7, #24]
|
|
8001a66: 429a cmp r2, r3
|
|
8001a68: d21d bcs.n 8001aa6 <UART_WaitOnFlagUntilTimeout+0x6c>
|
|
{
|
|
/* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
|
|
CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
|
|
8001a6a: 68fb ldr r3, [r7, #12]
|
|
8001a6c: 681b ldr r3, [r3, #0]
|
|
8001a6e: 68da ldr r2, [r3, #12]
|
|
8001a70: 68fb ldr r3, [r7, #12]
|
|
8001a72: 681b ldr r3, [r3, #0]
|
|
8001a74: f422 72d0 bic.w r2, r2, #416 ; 0x1a0
|
|
8001a78: 60da str r2, [r3, #12]
|
|
CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
|
|
8001a7a: 68fb ldr r3, [r7, #12]
|
|
8001a7c: 681b ldr r3, [r3, #0]
|
|
8001a7e: 695a ldr r2, [r3, #20]
|
|
8001a80: 68fb ldr r3, [r7, #12]
|
|
8001a82: 681b ldr r3, [r3, #0]
|
|
8001a84: f022 0201 bic.w r2, r2, #1
|
|
8001a88: 615a str r2, [r3, #20]
|
|
|
|
huart->gState = HAL_UART_STATE_READY;
|
|
8001a8a: 68fb ldr r3, [r7, #12]
|
|
8001a8c: 2220 movs r2, #32
|
|
8001a8e: f883 203d strb.w r2, [r3, #61] ; 0x3d
|
|
huart->RxState = HAL_UART_STATE_READY;
|
|
8001a92: 68fb ldr r3, [r7, #12]
|
|
8001a94: 2220 movs r2, #32
|
|
8001a96: f883 203e strb.w r2, [r3, #62] ; 0x3e
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(huart);
|
|
8001a9a: 68fb ldr r3, [r7, #12]
|
|
8001a9c: 2200 movs r2, #0
|
|
8001a9e: f883 203c strb.w r2, [r3, #60] ; 0x3c
|
|
|
|
return HAL_TIMEOUT;
|
|
8001aa2: 2303 movs r3, #3
|
|
8001aa4: e00f b.n 8001ac6 <UART_WaitOnFlagUntilTimeout+0x8c>
|
|
while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
|
|
8001aa6: 68fb ldr r3, [r7, #12]
|
|
8001aa8: 681b ldr r3, [r3, #0]
|
|
8001aaa: 681a ldr r2, [r3, #0]
|
|
8001aac: 68bb ldr r3, [r7, #8]
|
|
8001aae: 4013 ands r3, r2
|
|
8001ab0: 68ba ldr r2, [r7, #8]
|
|
8001ab2: 429a cmp r2, r3
|
|
8001ab4: bf0c ite eq
|
|
8001ab6: 2301 moveq r3, #1
|
|
8001ab8: 2300 movne r3, #0
|
|
8001aba: b2db uxtb r3, r3
|
|
8001abc: 461a mov r2, r3
|
|
8001abe: 79fb ldrb r3, [r7, #7]
|
|
8001ac0: 429a cmp r2, r3
|
|
8001ac2: d0c3 beq.n 8001a4c <UART_WaitOnFlagUntilTimeout+0x12>
|
|
}
|
|
}
|
|
}
|
|
return HAL_OK;
|
|
8001ac4: 2300 movs r3, #0
|
|
}
|
|
8001ac6: 4618 mov r0, r3
|
|
8001ac8: 3710 adds r7, #16
|
|
8001aca: 46bd mov sp, r7
|
|
8001acc: bd80 pop {r7, pc}
|
|
...
|
|
|
|
08001ad0 <UART_SetConfig>:
|
|
* @param huart Pointer to a UART_HandleTypeDef structure that contains
|
|
* the configuration information for the specified UART module.
|
|
* @retval None
|
|
*/
|
|
static void UART_SetConfig(UART_HandleTypeDef *huart)
|
|
{
|
|
8001ad0: b580 push {r7, lr}
|
|
8001ad2: b084 sub sp, #16
|
|
8001ad4: af00 add r7, sp, #0
|
|
8001ad6: 6078 str r0, [r7, #4]
|
|
assert_param(IS_UART_MODE(huart->Init.Mode));
|
|
|
|
/*-------------------------- USART CR2 Configuration -----------------------*/
|
|
/* Configure the UART Stop Bits: Set STOP[13:12] bits
|
|
according to huart->Init.StopBits value */
|
|
MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
|
|
8001ad8: 687b ldr r3, [r7, #4]
|
|
8001ada: 681b ldr r3, [r3, #0]
|
|
8001adc: 691b ldr r3, [r3, #16]
|
|
8001ade: f423 5140 bic.w r1, r3, #12288 ; 0x3000
|
|
8001ae2: 687b ldr r3, [r7, #4]
|
|
8001ae4: 68da ldr r2, [r3, #12]
|
|
8001ae6: 687b ldr r3, [r7, #4]
|
|
8001ae8: 681b ldr r3, [r3, #0]
|
|
8001aea: 430a orrs r2, r1
|
|
8001aec: 611a str r2, [r3, #16]
|
|
tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling;
|
|
MODIFY_REG(huart->Instance->CR1,
|
|
(uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8),
|
|
tmpreg);
|
|
#else
|
|
tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode;
|
|
8001aee: 687b ldr r3, [r7, #4]
|
|
8001af0: 689a ldr r2, [r3, #8]
|
|
8001af2: 687b ldr r3, [r7, #4]
|
|
8001af4: 691b ldr r3, [r3, #16]
|
|
8001af6: 431a orrs r2, r3
|
|
8001af8: 687b ldr r3, [r7, #4]
|
|
8001afa: 695b ldr r3, [r3, #20]
|
|
8001afc: 4313 orrs r3, r2
|
|
8001afe: 60bb str r3, [r7, #8]
|
|
MODIFY_REG(huart->Instance->CR1,
|
|
8001b00: 687b ldr r3, [r7, #4]
|
|
8001b02: 681b ldr r3, [r3, #0]
|
|
8001b04: 68db ldr r3, [r3, #12]
|
|
8001b06: f423 53b0 bic.w r3, r3, #5632 ; 0x1600
|
|
8001b0a: f023 030c bic.w r3, r3, #12
|
|
8001b0e: 687a ldr r2, [r7, #4]
|
|
8001b10: 6812 ldr r2, [r2, #0]
|
|
8001b12: 68b9 ldr r1, [r7, #8]
|
|
8001b14: 430b orrs r3, r1
|
|
8001b16: 60d3 str r3, [r2, #12]
|
|
tmpreg);
|
|
#endif /* USART_CR1_OVER8 */
|
|
|
|
/*-------------------------- USART CR3 Configuration -----------------------*/
|
|
/* Configure the UART HFC: Set CTSE and RTSE bits according to huart->Init.HwFlowCtl value */
|
|
MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE), huart->Init.HwFlowCtl);
|
|
8001b18: 687b ldr r3, [r7, #4]
|
|
8001b1a: 681b ldr r3, [r3, #0]
|
|
8001b1c: 695b ldr r3, [r3, #20]
|
|
8001b1e: f423 7140 bic.w r1, r3, #768 ; 0x300
|
|
8001b22: 687b ldr r3, [r7, #4]
|
|
8001b24: 699a ldr r2, [r3, #24]
|
|
8001b26: 687b ldr r3, [r7, #4]
|
|
8001b28: 681b ldr r3, [r3, #0]
|
|
8001b2a: 430a orrs r2, r1
|
|
8001b2c: 615a str r2, [r3, #20]
|
|
|
|
|
|
if(huart->Instance == USART1)
|
|
8001b2e: 687b ldr r3, [r7, #4]
|
|
8001b30: 681b ldr r3, [r3, #0]
|
|
8001b32: 4a2c ldr r2, [pc, #176] ; (8001be4 <UART_SetConfig+0x114>)
|
|
8001b34: 4293 cmp r3, r2
|
|
8001b36: d103 bne.n 8001b40 <UART_SetConfig+0x70>
|
|
{
|
|
pclk = HAL_RCC_GetPCLK2Freq();
|
|
8001b38: f7ff fc5a bl 80013f0 <HAL_RCC_GetPCLK2Freq>
|
|
8001b3c: 60f8 str r0, [r7, #12]
|
|
8001b3e: e002 b.n 8001b46 <UART_SetConfig+0x76>
|
|
}
|
|
else
|
|
{
|
|
pclk = HAL_RCC_GetPCLK1Freq();
|
|
8001b40: f7ff fc42 bl 80013c8 <HAL_RCC_GetPCLK1Freq>
|
|
8001b44: 60f8 str r0, [r7, #12]
|
|
else
|
|
{
|
|
huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate);
|
|
}
|
|
#else
|
|
huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate);
|
|
8001b46: 68fa ldr r2, [r7, #12]
|
|
8001b48: 4613 mov r3, r2
|
|
8001b4a: 009b lsls r3, r3, #2
|
|
8001b4c: 4413 add r3, r2
|
|
8001b4e: 009a lsls r2, r3, #2
|
|
8001b50: 441a add r2, r3
|
|
8001b52: 687b ldr r3, [r7, #4]
|
|
8001b54: 685b ldr r3, [r3, #4]
|
|
8001b56: 009b lsls r3, r3, #2
|
|
8001b58: fbb2 f3f3 udiv r3, r2, r3
|
|
8001b5c: 4a22 ldr r2, [pc, #136] ; (8001be8 <UART_SetConfig+0x118>)
|
|
8001b5e: fba2 2303 umull r2, r3, r2, r3
|
|
8001b62: 095b lsrs r3, r3, #5
|
|
8001b64: 0119 lsls r1, r3, #4
|
|
8001b66: 68fa ldr r2, [r7, #12]
|
|
8001b68: 4613 mov r3, r2
|
|
8001b6a: 009b lsls r3, r3, #2
|
|
8001b6c: 4413 add r3, r2
|
|
8001b6e: 009a lsls r2, r3, #2
|
|
8001b70: 441a add r2, r3
|
|
8001b72: 687b ldr r3, [r7, #4]
|
|
8001b74: 685b ldr r3, [r3, #4]
|
|
8001b76: 009b lsls r3, r3, #2
|
|
8001b78: fbb2 f2f3 udiv r2, r2, r3
|
|
8001b7c: 4b1a ldr r3, [pc, #104] ; (8001be8 <UART_SetConfig+0x118>)
|
|
8001b7e: fba3 0302 umull r0, r3, r3, r2
|
|
8001b82: 095b lsrs r3, r3, #5
|
|
8001b84: 2064 movs r0, #100 ; 0x64
|
|
8001b86: fb00 f303 mul.w r3, r0, r3
|
|
8001b8a: 1ad3 subs r3, r2, r3
|
|
8001b8c: 011b lsls r3, r3, #4
|
|
8001b8e: 3332 adds r3, #50 ; 0x32
|
|
8001b90: 4a15 ldr r2, [pc, #84] ; (8001be8 <UART_SetConfig+0x118>)
|
|
8001b92: fba2 2303 umull r2, r3, r2, r3
|
|
8001b96: 095b lsrs r3, r3, #5
|
|
8001b98: f003 03f0 and.w r3, r3, #240 ; 0xf0
|
|
8001b9c: 4419 add r1, r3
|
|
8001b9e: 68fa ldr r2, [r7, #12]
|
|
8001ba0: 4613 mov r3, r2
|
|
8001ba2: 009b lsls r3, r3, #2
|
|
8001ba4: 4413 add r3, r2
|
|
8001ba6: 009a lsls r2, r3, #2
|
|
8001ba8: 441a add r2, r3
|
|
8001baa: 687b ldr r3, [r7, #4]
|
|
8001bac: 685b ldr r3, [r3, #4]
|
|
8001bae: 009b lsls r3, r3, #2
|
|
8001bb0: fbb2 f2f3 udiv r2, r2, r3
|
|
8001bb4: 4b0c ldr r3, [pc, #48] ; (8001be8 <UART_SetConfig+0x118>)
|
|
8001bb6: fba3 0302 umull r0, r3, r3, r2
|
|
8001bba: 095b lsrs r3, r3, #5
|
|
8001bbc: 2064 movs r0, #100 ; 0x64
|
|
8001bbe: fb00 f303 mul.w r3, r0, r3
|
|
8001bc2: 1ad3 subs r3, r2, r3
|
|
8001bc4: 011b lsls r3, r3, #4
|
|
8001bc6: 3332 adds r3, #50 ; 0x32
|
|
8001bc8: 4a07 ldr r2, [pc, #28] ; (8001be8 <UART_SetConfig+0x118>)
|
|
8001bca: fba2 2303 umull r2, r3, r2, r3
|
|
8001bce: 095b lsrs r3, r3, #5
|
|
8001bd0: f003 020f and.w r2, r3, #15
|
|
8001bd4: 687b ldr r3, [r7, #4]
|
|
8001bd6: 681b ldr r3, [r3, #0]
|
|
8001bd8: 440a add r2, r1
|
|
8001bda: 609a str r2, [r3, #8]
|
|
#endif /* USART_CR1_OVER8 */
|
|
}
|
|
8001bdc: bf00 nop
|
|
8001bde: 3710 adds r7, #16
|
|
8001be0: 46bd mov sp, r7
|
|
8001be2: bd80 pop {r7, pc}
|
|
8001be4: 40013800 .word 0x40013800
|
|
8001be8: 51eb851f .word 0x51eb851f
|
|
|
|
08001bec <__errno>:
|
|
8001bec: 4b01 ldr r3, [pc, #4] ; (8001bf4 <__errno+0x8>)
|
|
8001bee: 6818 ldr r0, [r3, #0]
|
|
8001bf0: 4770 bx lr
|
|
8001bf2: bf00 nop
|
|
8001bf4: 2000000c .word 0x2000000c
|
|
|
|
08001bf8 <__libc_init_array>:
|
|
8001bf8: b570 push {r4, r5, r6, lr}
|
|
8001bfa: 2600 movs r6, #0
|
|
8001bfc: 4d0c ldr r5, [pc, #48] ; (8001c30 <__libc_init_array+0x38>)
|
|
8001bfe: 4c0d ldr r4, [pc, #52] ; (8001c34 <__libc_init_array+0x3c>)
|
|
8001c00: 1b64 subs r4, r4, r5
|
|
8001c02: 10a4 asrs r4, r4, #2
|
|
8001c04: 42a6 cmp r6, r4
|
|
8001c06: d109 bne.n 8001c1c <__libc_init_array+0x24>
|
|
8001c08: f000 fc9c bl 8002544 <_init>
|
|
8001c0c: 2600 movs r6, #0
|
|
8001c0e: 4d0a ldr r5, [pc, #40] ; (8001c38 <__libc_init_array+0x40>)
|
|
8001c10: 4c0a ldr r4, [pc, #40] ; (8001c3c <__libc_init_array+0x44>)
|
|
8001c12: 1b64 subs r4, r4, r5
|
|
8001c14: 10a4 asrs r4, r4, #2
|
|
8001c16: 42a6 cmp r6, r4
|
|
8001c18: d105 bne.n 8001c26 <__libc_init_array+0x2e>
|
|
8001c1a: bd70 pop {r4, r5, r6, pc}
|
|
8001c1c: f855 3b04 ldr.w r3, [r5], #4
|
|
8001c20: 4798 blx r3
|
|
8001c22: 3601 adds r6, #1
|
|
8001c24: e7ee b.n 8001c04 <__libc_init_array+0xc>
|
|
8001c26: f855 3b04 ldr.w r3, [r5], #4
|
|
8001c2a: 4798 blx r3
|
|
8001c2c: 3601 adds r6, #1
|
|
8001c2e: e7f2 b.n 8001c16 <__libc_init_array+0x1e>
|
|
8001c30: 080025c0 .word 0x080025c0
|
|
8001c34: 080025c0 .word 0x080025c0
|
|
8001c38: 080025c0 .word 0x080025c0
|
|
8001c3c: 080025c4 .word 0x080025c4
|
|
|
|
08001c40 <memset>:
|
|
8001c40: 4603 mov r3, r0
|
|
8001c42: 4402 add r2, r0
|
|
8001c44: 4293 cmp r3, r2
|
|
8001c46: d100 bne.n 8001c4a <memset+0xa>
|
|
8001c48: 4770 bx lr
|
|
8001c4a: f803 1b01 strb.w r1, [r3], #1
|
|
8001c4e: e7f9 b.n 8001c44 <memset+0x4>
|
|
|
|
08001c50 <siprintf>:
|
|
8001c50: b40e push {r1, r2, r3}
|
|
8001c52: f06f 4100 mvn.w r1, #2147483648 ; 0x80000000
|
|
8001c56: b500 push {lr}
|
|
8001c58: b09c sub sp, #112 ; 0x70
|
|
8001c5a: ab1d add r3, sp, #116 ; 0x74
|
|
8001c5c: 9002 str r0, [sp, #8]
|
|
8001c5e: 9006 str r0, [sp, #24]
|
|
8001c60: 9107 str r1, [sp, #28]
|
|
8001c62: 9104 str r1, [sp, #16]
|
|
8001c64: 4808 ldr r0, [pc, #32] ; (8001c88 <siprintf+0x38>)
|
|
8001c66: 4909 ldr r1, [pc, #36] ; (8001c8c <siprintf+0x3c>)
|
|
8001c68: f853 2b04 ldr.w r2, [r3], #4
|
|
8001c6c: 9105 str r1, [sp, #20]
|
|
8001c6e: 6800 ldr r0, [r0, #0]
|
|
8001c70: a902 add r1, sp, #8
|
|
8001c72: 9301 str r3, [sp, #4]
|
|
8001c74: f000 f868 bl 8001d48 <_svfiprintf_r>
|
|
8001c78: 2200 movs r2, #0
|
|
8001c7a: 9b02 ldr r3, [sp, #8]
|
|
8001c7c: 701a strb r2, [r3, #0]
|
|
8001c7e: b01c add sp, #112 ; 0x70
|
|
8001c80: f85d eb04 ldr.w lr, [sp], #4
|
|
8001c84: b003 add sp, #12
|
|
8001c86: 4770 bx lr
|
|
8001c88: 2000000c .word 0x2000000c
|
|
8001c8c: ffff0208 .word 0xffff0208
|
|
|
|
08001c90 <__ssputs_r>:
|
|
8001c90: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
|
|
8001c94: 688e ldr r6, [r1, #8]
|
|
8001c96: 4682 mov sl, r0
|
|
8001c98: 429e cmp r6, r3
|
|
8001c9a: 460c mov r4, r1
|
|
8001c9c: 4690 mov r8, r2
|
|
8001c9e: 461f mov r7, r3
|
|
8001ca0: d838 bhi.n 8001d14 <__ssputs_r+0x84>
|
|
8001ca2: 898a ldrh r2, [r1, #12]
|
|
8001ca4: f412 6f90 tst.w r2, #1152 ; 0x480
|
|
8001ca8: d032 beq.n 8001d10 <__ssputs_r+0x80>
|
|
8001caa: 6825 ldr r5, [r4, #0]
|
|
8001cac: 6909 ldr r1, [r1, #16]
|
|
8001cae: 3301 adds r3, #1
|
|
8001cb0: eba5 0901 sub.w r9, r5, r1
|
|
8001cb4: 6965 ldr r5, [r4, #20]
|
|
8001cb6: 444b add r3, r9
|
|
8001cb8: eb05 0545 add.w r5, r5, r5, lsl #1
|
|
8001cbc: eb05 75d5 add.w r5, r5, r5, lsr #31
|
|
8001cc0: 106d asrs r5, r5, #1
|
|
8001cc2: 429d cmp r5, r3
|
|
8001cc4: bf38 it cc
|
|
8001cc6: 461d movcc r5, r3
|
|
8001cc8: 0553 lsls r3, r2, #21
|
|
8001cca: d531 bpl.n 8001d30 <__ssputs_r+0xa0>
|
|
8001ccc: 4629 mov r1, r5
|
|
8001cce: f000 fb6f bl 80023b0 <_malloc_r>
|
|
8001cd2: 4606 mov r6, r0
|
|
8001cd4: b950 cbnz r0, 8001cec <__ssputs_r+0x5c>
|
|
8001cd6: 230c movs r3, #12
|
|
8001cd8: f04f 30ff mov.w r0, #4294967295
|
|
8001cdc: f8ca 3000 str.w r3, [sl]
|
|
8001ce0: 89a3 ldrh r3, [r4, #12]
|
|
8001ce2: f043 0340 orr.w r3, r3, #64 ; 0x40
|
|
8001ce6: 81a3 strh r3, [r4, #12]
|
|
8001ce8: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
|
|
8001cec: 464a mov r2, r9
|
|
8001cee: 6921 ldr r1, [r4, #16]
|
|
8001cf0: f000 face bl 8002290 <memcpy>
|
|
8001cf4: 89a3 ldrh r3, [r4, #12]
|
|
8001cf6: f423 6390 bic.w r3, r3, #1152 ; 0x480
|
|
8001cfa: f043 0380 orr.w r3, r3, #128 ; 0x80
|
|
8001cfe: 81a3 strh r3, [r4, #12]
|
|
8001d00: 6126 str r6, [r4, #16]
|
|
8001d02: 444e add r6, r9
|
|
8001d04: 6026 str r6, [r4, #0]
|
|
8001d06: 463e mov r6, r7
|
|
8001d08: 6165 str r5, [r4, #20]
|
|
8001d0a: eba5 0509 sub.w r5, r5, r9
|
|
8001d0e: 60a5 str r5, [r4, #8]
|
|
8001d10: 42be cmp r6, r7
|
|
8001d12: d900 bls.n 8001d16 <__ssputs_r+0x86>
|
|
8001d14: 463e mov r6, r7
|
|
8001d16: 4632 mov r2, r6
|
|
8001d18: 4641 mov r1, r8
|
|
8001d1a: 6820 ldr r0, [r4, #0]
|
|
8001d1c: f000 fac6 bl 80022ac <memmove>
|
|
8001d20: 68a3 ldr r3, [r4, #8]
|
|
8001d22: 2000 movs r0, #0
|
|
8001d24: 1b9b subs r3, r3, r6
|
|
8001d26: 60a3 str r3, [r4, #8]
|
|
8001d28: 6823 ldr r3, [r4, #0]
|
|
8001d2a: 4433 add r3, r6
|
|
8001d2c: 6023 str r3, [r4, #0]
|
|
8001d2e: e7db b.n 8001ce8 <__ssputs_r+0x58>
|
|
8001d30: 462a mov r2, r5
|
|
8001d32: f000 fbb1 bl 8002498 <_realloc_r>
|
|
8001d36: 4606 mov r6, r0
|
|
8001d38: 2800 cmp r0, #0
|
|
8001d3a: d1e1 bne.n 8001d00 <__ssputs_r+0x70>
|
|
8001d3c: 4650 mov r0, sl
|
|
8001d3e: 6921 ldr r1, [r4, #16]
|
|
8001d40: f000 face bl 80022e0 <_free_r>
|
|
8001d44: e7c7 b.n 8001cd6 <__ssputs_r+0x46>
|
|
...
|
|
|
|
08001d48 <_svfiprintf_r>:
|
|
8001d48: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
|
|
8001d4c: 4698 mov r8, r3
|
|
8001d4e: 898b ldrh r3, [r1, #12]
|
|
8001d50: 4607 mov r7, r0
|
|
8001d52: 061b lsls r3, r3, #24
|
|
8001d54: 460d mov r5, r1
|
|
8001d56: 4614 mov r4, r2
|
|
8001d58: b09d sub sp, #116 ; 0x74
|
|
8001d5a: d50e bpl.n 8001d7a <_svfiprintf_r+0x32>
|
|
8001d5c: 690b ldr r3, [r1, #16]
|
|
8001d5e: b963 cbnz r3, 8001d7a <_svfiprintf_r+0x32>
|
|
8001d60: 2140 movs r1, #64 ; 0x40
|
|
8001d62: f000 fb25 bl 80023b0 <_malloc_r>
|
|
8001d66: 6028 str r0, [r5, #0]
|
|
8001d68: 6128 str r0, [r5, #16]
|
|
8001d6a: b920 cbnz r0, 8001d76 <_svfiprintf_r+0x2e>
|
|
8001d6c: 230c movs r3, #12
|
|
8001d6e: 603b str r3, [r7, #0]
|
|
8001d70: f04f 30ff mov.w r0, #4294967295
|
|
8001d74: e0d1 b.n 8001f1a <_svfiprintf_r+0x1d2>
|
|
8001d76: 2340 movs r3, #64 ; 0x40
|
|
8001d78: 616b str r3, [r5, #20]
|
|
8001d7a: 2300 movs r3, #0
|
|
8001d7c: 9309 str r3, [sp, #36] ; 0x24
|
|
8001d7e: 2320 movs r3, #32
|
|
8001d80: f88d 3029 strb.w r3, [sp, #41] ; 0x29
|
|
8001d84: 2330 movs r3, #48 ; 0x30
|
|
8001d86: f04f 0901 mov.w r9, #1
|
|
8001d8a: f8cd 800c str.w r8, [sp, #12]
|
|
8001d8e: f8df 81a4 ldr.w r8, [pc, #420] ; 8001f34 <_svfiprintf_r+0x1ec>
|
|
8001d92: f88d 302a strb.w r3, [sp, #42] ; 0x2a
|
|
8001d96: 4623 mov r3, r4
|
|
8001d98: 469a mov sl, r3
|
|
8001d9a: f813 2b01 ldrb.w r2, [r3], #1
|
|
8001d9e: b10a cbz r2, 8001da4 <_svfiprintf_r+0x5c>
|
|
8001da0: 2a25 cmp r2, #37 ; 0x25
|
|
8001da2: d1f9 bne.n 8001d98 <_svfiprintf_r+0x50>
|
|
8001da4: ebba 0b04 subs.w fp, sl, r4
|
|
8001da8: d00b beq.n 8001dc2 <_svfiprintf_r+0x7a>
|
|
8001daa: 465b mov r3, fp
|
|
8001dac: 4622 mov r2, r4
|
|
8001dae: 4629 mov r1, r5
|
|
8001db0: 4638 mov r0, r7
|
|
8001db2: f7ff ff6d bl 8001c90 <__ssputs_r>
|
|
8001db6: 3001 adds r0, #1
|
|
8001db8: f000 80aa beq.w 8001f10 <_svfiprintf_r+0x1c8>
|
|
8001dbc: 9a09 ldr r2, [sp, #36] ; 0x24
|
|
8001dbe: 445a add r2, fp
|
|
8001dc0: 9209 str r2, [sp, #36] ; 0x24
|
|
8001dc2: f89a 3000 ldrb.w r3, [sl]
|
|
8001dc6: 2b00 cmp r3, #0
|
|
8001dc8: f000 80a2 beq.w 8001f10 <_svfiprintf_r+0x1c8>
|
|
8001dcc: 2300 movs r3, #0
|
|
8001dce: f04f 32ff mov.w r2, #4294967295
|
|
8001dd2: e9cd 2305 strd r2, r3, [sp, #20]
|
|
8001dd6: f10a 0a01 add.w sl, sl, #1
|
|
8001dda: 9304 str r3, [sp, #16]
|
|
8001ddc: 9307 str r3, [sp, #28]
|
|
8001dde: f88d 3053 strb.w r3, [sp, #83] ; 0x53
|
|
8001de2: 931a str r3, [sp, #104] ; 0x68
|
|
8001de4: 4654 mov r4, sl
|
|
8001de6: 2205 movs r2, #5
|
|
8001de8: f814 1b01 ldrb.w r1, [r4], #1
|
|
8001dec: 4851 ldr r0, [pc, #324] ; (8001f34 <_svfiprintf_r+0x1ec>)
|
|
8001dee: f000 fa41 bl 8002274 <memchr>
|
|
8001df2: 9a04 ldr r2, [sp, #16]
|
|
8001df4: b9d8 cbnz r0, 8001e2e <_svfiprintf_r+0xe6>
|
|
8001df6: 06d0 lsls r0, r2, #27
|
|
8001df8: bf44 itt mi
|
|
8001dfa: 2320 movmi r3, #32
|
|
8001dfc: f88d 3053 strbmi.w r3, [sp, #83] ; 0x53
|
|
8001e00: 0711 lsls r1, r2, #28
|
|
8001e02: bf44 itt mi
|
|
8001e04: 232b movmi r3, #43 ; 0x2b
|
|
8001e06: f88d 3053 strbmi.w r3, [sp, #83] ; 0x53
|
|
8001e0a: f89a 3000 ldrb.w r3, [sl]
|
|
8001e0e: 2b2a cmp r3, #42 ; 0x2a
|
|
8001e10: d015 beq.n 8001e3e <_svfiprintf_r+0xf6>
|
|
8001e12: 4654 mov r4, sl
|
|
8001e14: 2000 movs r0, #0
|
|
8001e16: f04f 0c0a mov.w ip, #10
|
|
8001e1a: 9a07 ldr r2, [sp, #28]
|
|
8001e1c: 4621 mov r1, r4
|
|
8001e1e: f811 3b01 ldrb.w r3, [r1], #1
|
|
8001e22: 3b30 subs r3, #48 ; 0x30
|
|
8001e24: 2b09 cmp r3, #9
|
|
8001e26: d94e bls.n 8001ec6 <_svfiprintf_r+0x17e>
|
|
8001e28: b1b0 cbz r0, 8001e58 <_svfiprintf_r+0x110>
|
|
8001e2a: 9207 str r2, [sp, #28]
|
|
8001e2c: e014 b.n 8001e58 <_svfiprintf_r+0x110>
|
|
8001e2e: eba0 0308 sub.w r3, r0, r8
|
|
8001e32: fa09 f303 lsl.w r3, r9, r3
|
|
8001e36: 4313 orrs r3, r2
|
|
8001e38: 46a2 mov sl, r4
|
|
8001e3a: 9304 str r3, [sp, #16]
|
|
8001e3c: e7d2 b.n 8001de4 <_svfiprintf_r+0x9c>
|
|
8001e3e: 9b03 ldr r3, [sp, #12]
|
|
8001e40: 1d19 adds r1, r3, #4
|
|
8001e42: 681b ldr r3, [r3, #0]
|
|
8001e44: 9103 str r1, [sp, #12]
|
|
8001e46: 2b00 cmp r3, #0
|
|
8001e48: bfbb ittet lt
|
|
8001e4a: 425b neglt r3, r3
|
|
8001e4c: f042 0202 orrlt.w r2, r2, #2
|
|
8001e50: 9307 strge r3, [sp, #28]
|
|
8001e52: 9307 strlt r3, [sp, #28]
|
|
8001e54: bfb8 it lt
|
|
8001e56: 9204 strlt r2, [sp, #16]
|
|
8001e58: 7823 ldrb r3, [r4, #0]
|
|
8001e5a: 2b2e cmp r3, #46 ; 0x2e
|
|
8001e5c: d10c bne.n 8001e78 <_svfiprintf_r+0x130>
|
|
8001e5e: 7863 ldrb r3, [r4, #1]
|
|
8001e60: 2b2a cmp r3, #42 ; 0x2a
|
|
8001e62: d135 bne.n 8001ed0 <_svfiprintf_r+0x188>
|
|
8001e64: 9b03 ldr r3, [sp, #12]
|
|
8001e66: 3402 adds r4, #2
|
|
8001e68: 1d1a adds r2, r3, #4
|
|
8001e6a: 681b ldr r3, [r3, #0]
|
|
8001e6c: 9203 str r2, [sp, #12]
|
|
8001e6e: 2b00 cmp r3, #0
|
|
8001e70: bfb8 it lt
|
|
8001e72: f04f 33ff movlt.w r3, #4294967295
|
|
8001e76: 9305 str r3, [sp, #20]
|
|
8001e78: f8df a0bc ldr.w sl, [pc, #188] ; 8001f38 <_svfiprintf_r+0x1f0>
|
|
8001e7c: 2203 movs r2, #3
|
|
8001e7e: 4650 mov r0, sl
|
|
8001e80: 7821 ldrb r1, [r4, #0]
|
|
8001e82: f000 f9f7 bl 8002274 <memchr>
|
|
8001e86: b140 cbz r0, 8001e9a <_svfiprintf_r+0x152>
|
|
8001e88: 2340 movs r3, #64 ; 0x40
|
|
8001e8a: eba0 000a sub.w r0, r0, sl
|
|
8001e8e: fa03 f000 lsl.w r0, r3, r0
|
|
8001e92: 9b04 ldr r3, [sp, #16]
|
|
8001e94: 3401 adds r4, #1
|
|
8001e96: 4303 orrs r3, r0
|
|
8001e98: 9304 str r3, [sp, #16]
|
|
8001e9a: f814 1b01 ldrb.w r1, [r4], #1
|
|
8001e9e: 2206 movs r2, #6
|
|
8001ea0: 4826 ldr r0, [pc, #152] ; (8001f3c <_svfiprintf_r+0x1f4>)
|
|
8001ea2: f88d 1028 strb.w r1, [sp, #40] ; 0x28
|
|
8001ea6: f000 f9e5 bl 8002274 <memchr>
|
|
8001eaa: 2800 cmp r0, #0
|
|
8001eac: d038 beq.n 8001f20 <_svfiprintf_r+0x1d8>
|
|
8001eae: 4b24 ldr r3, [pc, #144] ; (8001f40 <_svfiprintf_r+0x1f8>)
|
|
8001eb0: bb1b cbnz r3, 8001efa <_svfiprintf_r+0x1b2>
|
|
8001eb2: 9b03 ldr r3, [sp, #12]
|
|
8001eb4: 3307 adds r3, #7
|
|
8001eb6: f023 0307 bic.w r3, r3, #7
|
|
8001eba: 3308 adds r3, #8
|
|
8001ebc: 9303 str r3, [sp, #12]
|
|
8001ebe: 9b09 ldr r3, [sp, #36] ; 0x24
|
|
8001ec0: 4433 add r3, r6
|
|
8001ec2: 9309 str r3, [sp, #36] ; 0x24
|
|
8001ec4: e767 b.n 8001d96 <_svfiprintf_r+0x4e>
|
|
8001ec6: 460c mov r4, r1
|
|
8001ec8: 2001 movs r0, #1
|
|
8001eca: fb0c 3202 mla r2, ip, r2, r3
|
|
8001ece: e7a5 b.n 8001e1c <_svfiprintf_r+0xd4>
|
|
8001ed0: 2300 movs r3, #0
|
|
8001ed2: f04f 0c0a mov.w ip, #10
|
|
8001ed6: 4619 mov r1, r3
|
|
8001ed8: 3401 adds r4, #1
|
|
8001eda: 9305 str r3, [sp, #20]
|
|
8001edc: 4620 mov r0, r4
|
|
8001ede: f810 2b01 ldrb.w r2, [r0], #1
|
|
8001ee2: 3a30 subs r2, #48 ; 0x30
|
|
8001ee4: 2a09 cmp r2, #9
|
|
8001ee6: d903 bls.n 8001ef0 <_svfiprintf_r+0x1a8>
|
|
8001ee8: 2b00 cmp r3, #0
|
|
8001eea: d0c5 beq.n 8001e78 <_svfiprintf_r+0x130>
|
|
8001eec: 9105 str r1, [sp, #20]
|
|
8001eee: e7c3 b.n 8001e78 <_svfiprintf_r+0x130>
|
|
8001ef0: 4604 mov r4, r0
|
|
8001ef2: 2301 movs r3, #1
|
|
8001ef4: fb0c 2101 mla r1, ip, r1, r2
|
|
8001ef8: e7f0 b.n 8001edc <_svfiprintf_r+0x194>
|
|
8001efa: ab03 add r3, sp, #12
|
|
8001efc: 9300 str r3, [sp, #0]
|
|
8001efe: 462a mov r2, r5
|
|
8001f00: 4638 mov r0, r7
|
|
8001f02: 4b10 ldr r3, [pc, #64] ; (8001f44 <_svfiprintf_r+0x1fc>)
|
|
8001f04: a904 add r1, sp, #16
|
|
8001f06: f3af 8000 nop.w
|
|
8001f0a: 1c42 adds r2, r0, #1
|
|
8001f0c: 4606 mov r6, r0
|
|
8001f0e: d1d6 bne.n 8001ebe <_svfiprintf_r+0x176>
|
|
8001f10: 89ab ldrh r3, [r5, #12]
|
|
8001f12: 065b lsls r3, r3, #25
|
|
8001f14: f53f af2c bmi.w 8001d70 <_svfiprintf_r+0x28>
|
|
8001f18: 9809 ldr r0, [sp, #36] ; 0x24
|
|
8001f1a: b01d add sp, #116 ; 0x74
|
|
8001f1c: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
|
|
8001f20: ab03 add r3, sp, #12
|
|
8001f22: 9300 str r3, [sp, #0]
|
|
8001f24: 462a mov r2, r5
|
|
8001f26: 4638 mov r0, r7
|
|
8001f28: 4b06 ldr r3, [pc, #24] ; (8001f44 <_svfiprintf_r+0x1fc>)
|
|
8001f2a: a904 add r1, sp, #16
|
|
8001f2c: f000 f87c bl 8002028 <_printf_i>
|
|
8001f30: e7eb b.n 8001f0a <_svfiprintf_r+0x1c2>
|
|
8001f32: bf00 nop
|
|
8001f34: 0800258c .word 0x0800258c
|
|
8001f38: 08002592 .word 0x08002592
|
|
8001f3c: 08002596 .word 0x08002596
|
|
8001f40: 00000000 .word 0x00000000
|
|
8001f44: 08001c91 .word 0x08001c91
|
|
|
|
08001f48 <_printf_common>:
|
|
8001f48: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
|
|
8001f4c: 4616 mov r6, r2
|
|
8001f4e: 4699 mov r9, r3
|
|
8001f50: 688a ldr r2, [r1, #8]
|
|
8001f52: 690b ldr r3, [r1, #16]
|
|
8001f54: 4607 mov r7, r0
|
|
8001f56: 4293 cmp r3, r2
|
|
8001f58: bfb8 it lt
|
|
8001f5a: 4613 movlt r3, r2
|
|
8001f5c: 6033 str r3, [r6, #0]
|
|
8001f5e: f891 2043 ldrb.w r2, [r1, #67] ; 0x43
|
|
8001f62: 460c mov r4, r1
|
|
8001f64: f8dd 8020 ldr.w r8, [sp, #32]
|
|
8001f68: b10a cbz r2, 8001f6e <_printf_common+0x26>
|
|
8001f6a: 3301 adds r3, #1
|
|
8001f6c: 6033 str r3, [r6, #0]
|
|
8001f6e: 6823 ldr r3, [r4, #0]
|
|
8001f70: 0699 lsls r1, r3, #26
|
|
8001f72: bf42 ittt mi
|
|
8001f74: 6833 ldrmi r3, [r6, #0]
|
|
8001f76: 3302 addmi r3, #2
|
|
8001f78: 6033 strmi r3, [r6, #0]
|
|
8001f7a: 6825 ldr r5, [r4, #0]
|
|
8001f7c: f015 0506 ands.w r5, r5, #6
|
|
8001f80: d106 bne.n 8001f90 <_printf_common+0x48>
|
|
8001f82: f104 0a19 add.w sl, r4, #25
|
|
8001f86: 68e3 ldr r3, [r4, #12]
|
|
8001f88: 6832 ldr r2, [r6, #0]
|
|
8001f8a: 1a9b subs r3, r3, r2
|
|
8001f8c: 42ab cmp r3, r5
|
|
8001f8e: dc28 bgt.n 8001fe2 <_printf_common+0x9a>
|
|
8001f90: f894 2043 ldrb.w r2, [r4, #67] ; 0x43
|
|
8001f94: 1e13 subs r3, r2, #0
|
|
8001f96: 6822 ldr r2, [r4, #0]
|
|
8001f98: bf18 it ne
|
|
8001f9a: 2301 movne r3, #1
|
|
8001f9c: 0692 lsls r2, r2, #26
|
|
8001f9e: d42d bmi.n 8001ffc <_printf_common+0xb4>
|
|
8001fa0: 4649 mov r1, r9
|
|
8001fa2: 4638 mov r0, r7
|
|
8001fa4: f104 0243 add.w r2, r4, #67 ; 0x43
|
|
8001fa8: 47c0 blx r8
|
|
8001faa: 3001 adds r0, #1
|
|
8001fac: d020 beq.n 8001ff0 <_printf_common+0xa8>
|
|
8001fae: 6823 ldr r3, [r4, #0]
|
|
8001fb0: 68e5 ldr r5, [r4, #12]
|
|
8001fb2: f003 0306 and.w r3, r3, #6
|
|
8001fb6: 2b04 cmp r3, #4
|
|
8001fb8: bf18 it ne
|
|
8001fba: 2500 movne r5, #0
|
|
8001fbc: 6832 ldr r2, [r6, #0]
|
|
8001fbe: f04f 0600 mov.w r6, #0
|
|
8001fc2: 68a3 ldr r3, [r4, #8]
|
|
8001fc4: bf08 it eq
|
|
8001fc6: 1aad subeq r5, r5, r2
|
|
8001fc8: 6922 ldr r2, [r4, #16]
|
|
8001fca: bf08 it eq
|
|
8001fcc: ea25 75e5 biceq.w r5, r5, r5, asr #31
|
|
8001fd0: 4293 cmp r3, r2
|
|
8001fd2: bfc4 itt gt
|
|
8001fd4: 1a9b subgt r3, r3, r2
|
|
8001fd6: 18ed addgt r5, r5, r3
|
|
8001fd8: 341a adds r4, #26
|
|
8001fda: 42b5 cmp r5, r6
|
|
8001fdc: d11a bne.n 8002014 <_printf_common+0xcc>
|
|
8001fde: 2000 movs r0, #0
|
|
8001fe0: e008 b.n 8001ff4 <_printf_common+0xac>
|
|
8001fe2: 2301 movs r3, #1
|
|
8001fe4: 4652 mov r2, sl
|
|
8001fe6: 4649 mov r1, r9
|
|
8001fe8: 4638 mov r0, r7
|
|
8001fea: 47c0 blx r8
|
|
8001fec: 3001 adds r0, #1
|
|
8001fee: d103 bne.n 8001ff8 <_printf_common+0xb0>
|
|
8001ff0: f04f 30ff mov.w r0, #4294967295
|
|
8001ff4: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
|
|
8001ff8: 3501 adds r5, #1
|
|
8001ffa: e7c4 b.n 8001f86 <_printf_common+0x3e>
|
|
8001ffc: 2030 movs r0, #48 ; 0x30
|
|
8001ffe: 18e1 adds r1, r4, r3
|
|
8002000: f881 0043 strb.w r0, [r1, #67] ; 0x43
|
|
8002004: 1c5a adds r2, r3, #1
|
|
8002006: f894 1045 ldrb.w r1, [r4, #69] ; 0x45
|
|
800200a: 4422 add r2, r4
|
|
800200c: 3302 adds r3, #2
|
|
800200e: f882 1043 strb.w r1, [r2, #67] ; 0x43
|
|
8002012: e7c5 b.n 8001fa0 <_printf_common+0x58>
|
|
8002014: 2301 movs r3, #1
|
|
8002016: 4622 mov r2, r4
|
|
8002018: 4649 mov r1, r9
|
|
800201a: 4638 mov r0, r7
|
|
800201c: 47c0 blx r8
|
|
800201e: 3001 adds r0, #1
|
|
8002020: d0e6 beq.n 8001ff0 <_printf_common+0xa8>
|
|
8002022: 3601 adds r6, #1
|
|
8002024: e7d9 b.n 8001fda <_printf_common+0x92>
|
|
...
|
|
|
|
08002028 <_printf_i>:
|
|
8002028: e92d 47ff stmdb sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, lr}
|
|
800202c: 7e0f ldrb r7, [r1, #24]
|
|
800202e: 4691 mov r9, r2
|
|
8002030: 2f78 cmp r7, #120 ; 0x78
|
|
8002032: 4680 mov r8, r0
|
|
8002034: 460c mov r4, r1
|
|
8002036: 469a mov sl, r3
|
|
8002038: 9d0c ldr r5, [sp, #48] ; 0x30
|
|
800203a: f101 0243 add.w r2, r1, #67 ; 0x43
|
|
800203e: d807 bhi.n 8002050 <_printf_i+0x28>
|
|
8002040: 2f62 cmp r7, #98 ; 0x62
|
|
8002042: d80a bhi.n 800205a <_printf_i+0x32>
|
|
8002044: 2f00 cmp r7, #0
|
|
8002046: f000 80d9 beq.w 80021fc <_printf_i+0x1d4>
|
|
800204a: 2f58 cmp r7, #88 ; 0x58
|
|
800204c: f000 80a4 beq.w 8002198 <_printf_i+0x170>
|
|
8002050: f104 0542 add.w r5, r4, #66 ; 0x42
|
|
8002054: f884 7042 strb.w r7, [r4, #66] ; 0x42
|
|
8002058: e03a b.n 80020d0 <_printf_i+0xa8>
|
|
800205a: f1a7 0363 sub.w r3, r7, #99 ; 0x63
|
|
800205e: 2b15 cmp r3, #21
|
|
8002060: d8f6 bhi.n 8002050 <_printf_i+0x28>
|
|
8002062: a101 add r1, pc, #4 ; (adr r1, 8002068 <_printf_i+0x40>)
|
|
8002064: f851 f023 ldr.w pc, [r1, r3, lsl #2]
|
|
8002068: 080020c1 .word 0x080020c1
|
|
800206c: 080020d5 .word 0x080020d5
|
|
8002070: 08002051 .word 0x08002051
|
|
8002074: 08002051 .word 0x08002051
|
|
8002078: 08002051 .word 0x08002051
|
|
800207c: 08002051 .word 0x08002051
|
|
8002080: 080020d5 .word 0x080020d5
|
|
8002084: 08002051 .word 0x08002051
|
|
8002088: 08002051 .word 0x08002051
|
|
800208c: 08002051 .word 0x08002051
|
|
8002090: 08002051 .word 0x08002051
|
|
8002094: 080021e3 .word 0x080021e3
|
|
8002098: 08002105 .word 0x08002105
|
|
800209c: 080021c5 .word 0x080021c5
|
|
80020a0: 08002051 .word 0x08002051
|
|
80020a4: 08002051 .word 0x08002051
|
|
80020a8: 08002205 .word 0x08002205
|
|
80020ac: 08002051 .word 0x08002051
|
|
80020b0: 08002105 .word 0x08002105
|
|
80020b4: 08002051 .word 0x08002051
|
|
80020b8: 08002051 .word 0x08002051
|
|
80020bc: 080021cd .word 0x080021cd
|
|
80020c0: 682b ldr r3, [r5, #0]
|
|
80020c2: 1d1a adds r2, r3, #4
|
|
80020c4: 681b ldr r3, [r3, #0]
|
|
80020c6: 602a str r2, [r5, #0]
|
|
80020c8: f104 0542 add.w r5, r4, #66 ; 0x42
|
|
80020cc: f884 3042 strb.w r3, [r4, #66] ; 0x42
|
|
80020d0: 2301 movs r3, #1
|
|
80020d2: e0a4 b.n 800221e <_printf_i+0x1f6>
|
|
80020d4: 6820 ldr r0, [r4, #0]
|
|
80020d6: 6829 ldr r1, [r5, #0]
|
|
80020d8: 0606 lsls r6, r0, #24
|
|
80020da: f101 0304 add.w r3, r1, #4
|
|
80020de: d50a bpl.n 80020f6 <_printf_i+0xce>
|
|
80020e0: 680e ldr r6, [r1, #0]
|
|
80020e2: 602b str r3, [r5, #0]
|
|
80020e4: 2e00 cmp r6, #0
|
|
80020e6: da03 bge.n 80020f0 <_printf_i+0xc8>
|
|
80020e8: 232d movs r3, #45 ; 0x2d
|
|
80020ea: 4276 negs r6, r6
|
|
80020ec: f884 3043 strb.w r3, [r4, #67] ; 0x43
|
|
80020f0: 230a movs r3, #10
|
|
80020f2: 485e ldr r0, [pc, #376] ; (800226c <_printf_i+0x244>)
|
|
80020f4: e019 b.n 800212a <_printf_i+0x102>
|
|
80020f6: 680e ldr r6, [r1, #0]
|
|
80020f8: f010 0f40 tst.w r0, #64 ; 0x40
|
|
80020fc: 602b str r3, [r5, #0]
|
|
80020fe: bf18 it ne
|
|
8002100: b236 sxthne r6, r6
|
|
8002102: e7ef b.n 80020e4 <_printf_i+0xbc>
|
|
8002104: 682b ldr r3, [r5, #0]
|
|
8002106: 6820 ldr r0, [r4, #0]
|
|
8002108: 1d19 adds r1, r3, #4
|
|
800210a: 6029 str r1, [r5, #0]
|
|
800210c: 0601 lsls r1, r0, #24
|
|
800210e: d501 bpl.n 8002114 <_printf_i+0xec>
|
|
8002110: 681e ldr r6, [r3, #0]
|
|
8002112: e002 b.n 800211a <_printf_i+0xf2>
|
|
8002114: 0646 lsls r6, r0, #25
|
|
8002116: d5fb bpl.n 8002110 <_printf_i+0xe8>
|
|
8002118: 881e ldrh r6, [r3, #0]
|
|
800211a: 2f6f cmp r7, #111 ; 0x6f
|
|
800211c: bf0c ite eq
|
|
800211e: 2308 moveq r3, #8
|
|
8002120: 230a movne r3, #10
|
|
8002122: 4852 ldr r0, [pc, #328] ; (800226c <_printf_i+0x244>)
|
|
8002124: 2100 movs r1, #0
|
|
8002126: f884 1043 strb.w r1, [r4, #67] ; 0x43
|
|
800212a: 6865 ldr r5, [r4, #4]
|
|
800212c: 2d00 cmp r5, #0
|
|
800212e: bfa8 it ge
|
|
8002130: 6821 ldrge r1, [r4, #0]
|
|
8002132: 60a5 str r5, [r4, #8]
|
|
8002134: bfa4 itt ge
|
|
8002136: f021 0104 bicge.w r1, r1, #4
|
|
800213a: 6021 strge r1, [r4, #0]
|
|
800213c: b90e cbnz r6, 8002142 <_printf_i+0x11a>
|
|
800213e: 2d00 cmp r5, #0
|
|
8002140: d04d beq.n 80021de <_printf_i+0x1b6>
|
|
8002142: 4615 mov r5, r2
|
|
8002144: fbb6 f1f3 udiv r1, r6, r3
|
|
8002148: fb03 6711 mls r7, r3, r1, r6
|
|
800214c: 5dc7 ldrb r7, [r0, r7]
|
|
800214e: f805 7d01 strb.w r7, [r5, #-1]!
|
|
8002152: 4637 mov r7, r6
|
|
8002154: 42bb cmp r3, r7
|
|
8002156: 460e mov r6, r1
|
|
8002158: d9f4 bls.n 8002144 <_printf_i+0x11c>
|
|
800215a: 2b08 cmp r3, #8
|
|
800215c: d10b bne.n 8002176 <_printf_i+0x14e>
|
|
800215e: 6823 ldr r3, [r4, #0]
|
|
8002160: 07de lsls r6, r3, #31
|
|
8002162: d508 bpl.n 8002176 <_printf_i+0x14e>
|
|
8002164: 6923 ldr r3, [r4, #16]
|
|
8002166: 6861 ldr r1, [r4, #4]
|
|
8002168: 4299 cmp r1, r3
|
|
800216a: bfde ittt le
|
|
800216c: 2330 movle r3, #48 ; 0x30
|
|
800216e: f805 3c01 strble.w r3, [r5, #-1]
|
|
8002172: f105 35ff addle.w r5, r5, #4294967295
|
|
8002176: 1b52 subs r2, r2, r5
|
|
8002178: 6122 str r2, [r4, #16]
|
|
800217a: 464b mov r3, r9
|
|
800217c: 4621 mov r1, r4
|
|
800217e: 4640 mov r0, r8
|
|
8002180: f8cd a000 str.w sl, [sp]
|
|
8002184: aa03 add r2, sp, #12
|
|
8002186: f7ff fedf bl 8001f48 <_printf_common>
|
|
800218a: 3001 adds r0, #1
|
|
800218c: d14c bne.n 8002228 <_printf_i+0x200>
|
|
800218e: f04f 30ff mov.w r0, #4294967295
|
|
8002192: b004 add sp, #16
|
|
8002194: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
|
|
8002198: 4834 ldr r0, [pc, #208] ; (800226c <_printf_i+0x244>)
|
|
800219a: f881 7045 strb.w r7, [r1, #69] ; 0x45
|
|
800219e: 6829 ldr r1, [r5, #0]
|
|
80021a0: 6823 ldr r3, [r4, #0]
|
|
80021a2: f851 6b04 ldr.w r6, [r1], #4
|
|
80021a6: 6029 str r1, [r5, #0]
|
|
80021a8: 061d lsls r5, r3, #24
|
|
80021aa: d514 bpl.n 80021d6 <_printf_i+0x1ae>
|
|
80021ac: 07df lsls r7, r3, #31
|
|
80021ae: bf44 itt mi
|
|
80021b0: f043 0320 orrmi.w r3, r3, #32
|
|
80021b4: 6023 strmi r3, [r4, #0]
|
|
80021b6: b91e cbnz r6, 80021c0 <_printf_i+0x198>
|
|
80021b8: 6823 ldr r3, [r4, #0]
|
|
80021ba: f023 0320 bic.w r3, r3, #32
|
|
80021be: 6023 str r3, [r4, #0]
|
|
80021c0: 2310 movs r3, #16
|
|
80021c2: e7af b.n 8002124 <_printf_i+0xfc>
|
|
80021c4: 6823 ldr r3, [r4, #0]
|
|
80021c6: f043 0320 orr.w r3, r3, #32
|
|
80021ca: 6023 str r3, [r4, #0]
|
|
80021cc: 2378 movs r3, #120 ; 0x78
|
|
80021ce: 4828 ldr r0, [pc, #160] ; (8002270 <_printf_i+0x248>)
|
|
80021d0: f884 3045 strb.w r3, [r4, #69] ; 0x45
|
|
80021d4: e7e3 b.n 800219e <_printf_i+0x176>
|
|
80021d6: 0659 lsls r1, r3, #25
|
|
80021d8: bf48 it mi
|
|
80021da: b2b6 uxthmi r6, r6
|
|
80021dc: e7e6 b.n 80021ac <_printf_i+0x184>
|
|
80021de: 4615 mov r5, r2
|
|
80021e0: e7bb b.n 800215a <_printf_i+0x132>
|
|
80021e2: 682b ldr r3, [r5, #0]
|
|
80021e4: 6826 ldr r6, [r4, #0]
|
|
80021e6: 1d18 adds r0, r3, #4
|
|
80021e8: 6961 ldr r1, [r4, #20]
|
|
80021ea: 6028 str r0, [r5, #0]
|
|
80021ec: 0635 lsls r5, r6, #24
|
|
80021ee: 681b ldr r3, [r3, #0]
|
|
80021f0: d501 bpl.n 80021f6 <_printf_i+0x1ce>
|
|
80021f2: 6019 str r1, [r3, #0]
|
|
80021f4: e002 b.n 80021fc <_printf_i+0x1d4>
|
|
80021f6: 0670 lsls r0, r6, #25
|
|
80021f8: d5fb bpl.n 80021f2 <_printf_i+0x1ca>
|
|
80021fa: 8019 strh r1, [r3, #0]
|
|
80021fc: 2300 movs r3, #0
|
|
80021fe: 4615 mov r5, r2
|
|
8002200: 6123 str r3, [r4, #16]
|
|
8002202: e7ba b.n 800217a <_printf_i+0x152>
|
|
8002204: 682b ldr r3, [r5, #0]
|
|
8002206: 2100 movs r1, #0
|
|
8002208: 1d1a adds r2, r3, #4
|
|
800220a: 602a str r2, [r5, #0]
|
|
800220c: 681d ldr r5, [r3, #0]
|
|
800220e: 6862 ldr r2, [r4, #4]
|
|
8002210: 4628 mov r0, r5
|
|
8002212: f000 f82f bl 8002274 <memchr>
|
|
8002216: b108 cbz r0, 800221c <_printf_i+0x1f4>
|
|
8002218: 1b40 subs r0, r0, r5
|
|
800221a: 6060 str r0, [r4, #4]
|
|
800221c: 6863 ldr r3, [r4, #4]
|
|
800221e: 6123 str r3, [r4, #16]
|
|
8002220: 2300 movs r3, #0
|
|
8002222: f884 3043 strb.w r3, [r4, #67] ; 0x43
|
|
8002226: e7a8 b.n 800217a <_printf_i+0x152>
|
|
8002228: 462a mov r2, r5
|
|
800222a: 4649 mov r1, r9
|
|
800222c: 4640 mov r0, r8
|
|
800222e: 6923 ldr r3, [r4, #16]
|
|
8002230: 47d0 blx sl
|
|
8002232: 3001 adds r0, #1
|
|
8002234: d0ab beq.n 800218e <_printf_i+0x166>
|
|
8002236: 6823 ldr r3, [r4, #0]
|
|
8002238: 079b lsls r3, r3, #30
|
|
800223a: d413 bmi.n 8002264 <_printf_i+0x23c>
|
|
800223c: 68e0 ldr r0, [r4, #12]
|
|
800223e: 9b03 ldr r3, [sp, #12]
|
|
8002240: 4298 cmp r0, r3
|
|
8002242: bfb8 it lt
|
|
8002244: 4618 movlt r0, r3
|
|
8002246: e7a4 b.n 8002192 <_printf_i+0x16a>
|
|
8002248: 2301 movs r3, #1
|
|
800224a: 4632 mov r2, r6
|
|
800224c: 4649 mov r1, r9
|
|
800224e: 4640 mov r0, r8
|
|
8002250: 47d0 blx sl
|
|
8002252: 3001 adds r0, #1
|
|
8002254: d09b beq.n 800218e <_printf_i+0x166>
|
|
8002256: 3501 adds r5, #1
|
|
8002258: 68e3 ldr r3, [r4, #12]
|
|
800225a: 9903 ldr r1, [sp, #12]
|
|
800225c: 1a5b subs r3, r3, r1
|
|
800225e: 42ab cmp r3, r5
|
|
8002260: dcf2 bgt.n 8002248 <_printf_i+0x220>
|
|
8002262: e7eb b.n 800223c <_printf_i+0x214>
|
|
8002264: 2500 movs r5, #0
|
|
8002266: f104 0619 add.w r6, r4, #25
|
|
800226a: e7f5 b.n 8002258 <_printf_i+0x230>
|
|
800226c: 0800259d .word 0x0800259d
|
|
8002270: 080025ae .word 0x080025ae
|
|
|
|
08002274 <memchr>:
|
|
8002274: 4603 mov r3, r0
|
|
8002276: b510 push {r4, lr}
|
|
8002278: b2c9 uxtb r1, r1
|
|
800227a: 4402 add r2, r0
|
|
800227c: 4293 cmp r3, r2
|
|
800227e: 4618 mov r0, r3
|
|
8002280: d101 bne.n 8002286 <memchr+0x12>
|
|
8002282: 2000 movs r0, #0
|
|
8002284: e003 b.n 800228e <memchr+0x1a>
|
|
8002286: 7804 ldrb r4, [r0, #0]
|
|
8002288: 3301 adds r3, #1
|
|
800228a: 428c cmp r4, r1
|
|
800228c: d1f6 bne.n 800227c <memchr+0x8>
|
|
800228e: bd10 pop {r4, pc}
|
|
|
|
08002290 <memcpy>:
|
|
8002290: 440a add r2, r1
|
|
8002292: 4291 cmp r1, r2
|
|
8002294: f100 33ff add.w r3, r0, #4294967295
|
|
8002298: d100 bne.n 800229c <memcpy+0xc>
|
|
800229a: 4770 bx lr
|
|
800229c: b510 push {r4, lr}
|
|
800229e: f811 4b01 ldrb.w r4, [r1], #1
|
|
80022a2: 4291 cmp r1, r2
|
|
80022a4: f803 4f01 strb.w r4, [r3, #1]!
|
|
80022a8: d1f9 bne.n 800229e <memcpy+0xe>
|
|
80022aa: bd10 pop {r4, pc}
|
|
|
|
080022ac <memmove>:
|
|
80022ac: 4288 cmp r0, r1
|
|
80022ae: b510 push {r4, lr}
|
|
80022b0: eb01 0402 add.w r4, r1, r2
|
|
80022b4: d902 bls.n 80022bc <memmove+0x10>
|
|
80022b6: 4284 cmp r4, r0
|
|
80022b8: 4623 mov r3, r4
|
|
80022ba: d807 bhi.n 80022cc <memmove+0x20>
|
|
80022bc: 1e43 subs r3, r0, #1
|
|
80022be: 42a1 cmp r1, r4
|
|
80022c0: d008 beq.n 80022d4 <memmove+0x28>
|
|
80022c2: f811 2b01 ldrb.w r2, [r1], #1
|
|
80022c6: f803 2f01 strb.w r2, [r3, #1]!
|
|
80022ca: e7f8 b.n 80022be <memmove+0x12>
|
|
80022cc: 4601 mov r1, r0
|
|
80022ce: 4402 add r2, r0
|
|
80022d0: 428a cmp r2, r1
|
|
80022d2: d100 bne.n 80022d6 <memmove+0x2a>
|
|
80022d4: bd10 pop {r4, pc}
|
|
80022d6: f813 4d01 ldrb.w r4, [r3, #-1]!
|
|
80022da: f802 4d01 strb.w r4, [r2, #-1]!
|
|
80022de: e7f7 b.n 80022d0 <memmove+0x24>
|
|
|
|
080022e0 <_free_r>:
|
|
80022e0: b538 push {r3, r4, r5, lr}
|
|
80022e2: 4605 mov r5, r0
|
|
80022e4: 2900 cmp r1, #0
|
|
80022e6: d040 beq.n 800236a <_free_r+0x8a>
|
|
80022e8: f851 3c04 ldr.w r3, [r1, #-4]
|
|
80022ec: 1f0c subs r4, r1, #4
|
|
80022ee: 2b00 cmp r3, #0
|
|
80022f0: bfb8 it lt
|
|
80022f2: 18e4 addlt r4, r4, r3
|
|
80022f4: f000 f910 bl 8002518 <__malloc_lock>
|
|
80022f8: 4a1c ldr r2, [pc, #112] ; (800236c <_free_r+0x8c>)
|
|
80022fa: 6813 ldr r3, [r2, #0]
|
|
80022fc: b933 cbnz r3, 800230c <_free_r+0x2c>
|
|
80022fe: 6063 str r3, [r4, #4]
|
|
8002300: 6014 str r4, [r2, #0]
|
|
8002302: 4628 mov r0, r5
|
|
8002304: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr}
|
|
8002308: f000 b90c b.w 8002524 <__malloc_unlock>
|
|
800230c: 42a3 cmp r3, r4
|
|
800230e: d908 bls.n 8002322 <_free_r+0x42>
|
|
8002310: 6820 ldr r0, [r4, #0]
|
|
8002312: 1821 adds r1, r4, r0
|
|
8002314: 428b cmp r3, r1
|
|
8002316: bf01 itttt eq
|
|
8002318: 6819 ldreq r1, [r3, #0]
|
|
800231a: 685b ldreq r3, [r3, #4]
|
|
800231c: 1809 addeq r1, r1, r0
|
|
800231e: 6021 streq r1, [r4, #0]
|
|
8002320: e7ed b.n 80022fe <_free_r+0x1e>
|
|
8002322: 461a mov r2, r3
|
|
8002324: 685b ldr r3, [r3, #4]
|
|
8002326: b10b cbz r3, 800232c <_free_r+0x4c>
|
|
8002328: 42a3 cmp r3, r4
|
|
800232a: d9fa bls.n 8002322 <_free_r+0x42>
|
|
800232c: 6811 ldr r1, [r2, #0]
|
|
800232e: 1850 adds r0, r2, r1
|
|
8002330: 42a0 cmp r0, r4
|
|
8002332: d10b bne.n 800234c <_free_r+0x6c>
|
|
8002334: 6820 ldr r0, [r4, #0]
|
|
8002336: 4401 add r1, r0
|
|
8002338: 1850 adds r0, r2, r1
|
|
800233a: 4283 cmp r3, r0
|
|
800233c: 6011 str r1, [r2, #0]
|
|
800233e: d1e0 bne.n 8002302 <_free_r+0x22>
|
|
8002340: 6818 ldr r0, [r3, #0]
|
|
8002342: 685b ldr r3, [r3, #4]
|
|
8002344: 4401 add r1, r0
|
|
8002346: 6011 str r1, [r2, #0]
|
|
8002348: 6053 str r3, [r2, #4]
|
|
800234a: e7da b.n 8002302 <_free_r+0x22>
|
|
800234c: d902 bls.n 8002354 <_free_r+0x74>
|
|
800234e: 230c movs r3, #12
|
|
8002350: 602b str r3, [r5, #0]
|
|
8002352: e7d6 b.n 8002302 <_free_r+0x22>
|
|
8002354: 6820 ldr r0, [r4, #0]
|
|
8002356: 1821 adds r1, r4, r0
|
|
8002358: 428b cmp r3, r1
|
|
800235a: bf01 itttt eq
|
|
800235c: 6819 ldreq r1, [r3, #0]
|
|
800235e: 685b ldreq r3, [r3, #4]
|
|
8002360: 1809 addeq r1, r1, r0
|
|
8002362: 6021 streq r1, [r4, #0]
|
|
8002364: 6063 str r3, [r4, #4]
|
|
8002366: 6054 str r4, [r2, #4]
|
|
8002368: e7cb b.n 8002302 <_free_r+0x22>
|
|
800236a: bd38 pop {r3, r4, r5, pc}
|
|
800236c: 20000120 .word 0x20000120
|
|
|
|
08002370 <sbrk_aligned>:
|
|
8002370: b570 push {r4, r5, r6, lr}
|
|
8002372: 4e0e ldr r6, [pc, #56] ; (80023ac <sbrk_aligned+0x3c>)
|
|
8002374: 460c mov r4, r1
|
|
8002376: 6831 ldr r1, [r6, #0]
|
|
8002378: 4605 mov r5, r0
|
|
800237a: b911 cbnz r1, 8002382 <sbrk_aligned+0x12>
|
|
800237c: f000 f8bc bl 80024f8 <_sbrk_r>
|
|
8002380: 6030 str r0, [r6, #0]
|
|
8002382: 4621 mov r1, r4
|
|
8002384: 4628 mov r0, r5
|
|
8002386: f000 f8b7 bl 80024f8 <_sbrk_r>
|
|
800238a: 1c43 adds r3, r0, #1
|
|
800238c: d00a beq.n 80023a4 <sbrk_aligned+0x34>
|
|
800238e: 1cc4 adds r4, r0, #3
|
|
8002390: f024 0403 bic.w r4, r4, #3
|
|
8002394: 42a0 cmp r0, r4
|
|
8002396: d007 beq.n 80023a8 <sbrk_aligned+0x38>
|
|
8002398: 1a21 subs r1, r4, r0
|
|
800239a: 4628 mov r0, r5
|
|
800239c: f000 f8ac bl 80024f8 <_sbrk_r>
|
|
80023a0: 3001 adds r0, #1
|
|
80023a2: d101 bne.n 80023a8 <sbrk_aligned+0x38>
|
|
80023a4: f04f 34ff mov.w r4, #4294967295
|
|
80023a8: 4620 mov r0, r4
|
|
80023aa: bd70 pop {r4, r5, r6, pc}
|
|
80023ac: 20000124 .word 0x20000124
|
|
|
|
080023b0 <_malloc_r>:
|
|
80023b0: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr}
|
|
80023b4: 1ccd adds r5, r1, #3
|
|
80023b6: f025 0503 bic.w r5, r5, #3
|
|
80023ba: 3508 adds r5, #8
|
|
80023bc: 2d0c cmp r5, #12
|
|
80023be: bf38 it cc
|
|
80023c0: 250c movcc r5, #12
|
|
80023c2: 2d00 cmp r5, #0
|
|
80023c4: 4607 mov r7, r0
|
|
80023c6: db01 blt.n 80023cc <_malloc_r+0x1c>
|
|
80023c8: 42a9 cmp r1, r5
|
|
80023ca: d905 bls.n 80023d8 <_malloc_r+0x28>
|
|
80023cc: 230c movs r3, #12
|
|
80023ce: 2600 movs r6, #0
|
|
80023d0: 603b str r3, [r7, #0]
|
|
80023d2: 4630 mov r0, r6
|
|
80023d4: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc}
|
|
80023d8: 4e2e ldr r6, [pc, #184] ; (8002494 <_malloc_r+0xe4>)
|
|
80023da: f000 f89d bl 8002518 <__malloc_lock>
|
|
80023de: 6833 ldr r3, [r6, #0]
|
|
80023e0: 461c mov r4, r3
|
|
80023e2: bb34 cbnz r4, 8002432 <_malloc_r+0x82>
|
|
80023e4: 4629 mov r1, r5
|
|
80023e6: 4638 mov r0, r7
|
|
80023e8: f7ff ffc2 bl 8002370 <sbrk_aligned>
|
|
80023ec: 1c43 adds r3, r0, #1
|
|
80023ee: 4604 mov r4, r0
|
|
80023f0: d14d bne.n 800248e <_malloc_r+0xde>
|
|
80023f2: 6834 ldr r4, [r6, #0]
|
|
80023f4: 4626 mov r6, r4
|
|
80023f6: 2e00 cmp r6, #0
|
|
80023f8: d140 bne.n 800247c <_malloc_r+0xcc>
|
|
80023fa: 6823 ldr r3, [r4, #0]
|
|
80023fc: 4631 mov r1, r6
|
|
80023fe: 4638 mov r0, r7
|
|
8002400: eb04 0803 add.w r8, r4, r3
|
|
8002404: f000 f878 bl 80024f8 <_sbrk_r>
|
|
8002408: 4580 cmp r8, r0
|
|
800240a: d13a bne.n 8002482 <_malloc_r+0xd2>
|
|
800240c: 6821 ldr r1, [r4, #0]
|
|
800240e: 3503 adds r5, #3
|
|
8002410: 1a6d subs r5, r5, r1
|
|
8002412: f025 0503 bic.w r5, r5, #3
|
|
8002416: 3508 adds r5, #8
|
|
8002418: 2d0c cmp r5, #12
|
|
800241a: bf38 it cc
|
|
800241c: 250c movcc r5, #12
|
|
800241e: 4638 mov r0, r7
|
|
8002420: 4629 mov r1, r5
|
|
8002422: f7ff ffa5 bl 8002370 <sbrk_aligned>
|
|
8002426: 3001 adds r0, #1
|
|
8002428: d02b beq.n 8002482 <_malloc_r+0xd2>
|
|
800242a: 6823 ldr r3, [r4, #0]
|
|
800242c: 442b add r3, r5
|
|
800242e: 6023 str r3, [r4, #0]
|
|
8002430: e00e b.n 8002450 <_malloc_r+0xa0>
|
|
8002432: 6822 ldr r2, [r4, #0]
|
|
8002434: 1b52 subs r2, r2, r5
|
|
8002436: d41e bmi.n 8002476 <_malloc_r+0xc6>
|
|
8002438: 2a0b cmp r2, #11
|
|
800243a: d916 bls.n 800246a <_malloc_r+0xba>
|
|
800243c: 1961 adds r1, r4, r5
|
|
800243e: 42a3 cmp r3, r4
|
|
8002440: 6025 str r5, [r4, #0]
|
|
8002442: bf18 it ne
|
|
8002444: 6059 strne r1, [r3, #4]
|
|
8002446: 6863 ldr r3, [r4, #4]
|
|
8002448: bf08 it eq
|
|
800244a: 6031 streq r1, [r6, #0]
|
|
800244c: 5162 str r2, [r4, r5]
|
|
800244e: 604b str r3, [r1, #4]
|
|
8002450: 4638 mov r0, r7
|
|
8002452: f104 060b add.w r6, r4, #11
|
|
8002456: f000 f865 bl 8002524 <__malloc_unlock>
|
|
800245a: f026 0607 bic.w r6, r6, #7
|
|
800245e: 1d23 adds r3, r4, #4
|
|
8002460: 1af2 subs r2, r6, r3
|
|
8002462: d0b6 beq.n 80023d2 <_malloc_r+0x22>
|
|
8002464: 1b9b subs r3, r3, r6
|
|
8002466: 50a3 str r3, [r4, r2]
|
|
8002468: e7b3 b.n 80023d2 <_malloc_r+0x22>
|
|
800246a: 6862 ldr r2, [r4, #4]
|
|
800246c: 42a3 cmp r3, r4
|
|
800246e: bf0c ite eq
|
|
8002470: 6032 streq r2, [r6, #0]
|
|
8002472: 605a strne r2, [r3, #4]
|
|
8002474: e7ec b.n 8002450 <_malloc_r+0xa0>
|
|
8002476: 4623 mov r3, r4
|
|
8002478: 6864 ldr r4, [r4, #4]
|
|
800247a: e7b2 b.n 80023e2 <_malloc_r+0x32>
|
|
800247c: 4634 mov r4, r6
|
|
800247e: 6876 ldr r6, [r6, #4]
|
|
8002480: e7b9 b.n 80023f6 <_malloc_r+0x46>
|
|
8002482: 230c movs r3, #12
|
|
8002484: 4638 mov r0, r7
|
|
8002486: 603b str r3, [r7, #0]
|
|
8002488: f000 f84c bl 8002524 <__malloc_unlock>
|
|
800248c: e7a1 b.n 80023d2 <_malloc_r+0x22>
|
|
800248e: 6025 str r5, [r4, #0]
|
|
8002490: e7de b.n 8002450 <_malloc_r+0xa0>
|
|
8002492: bf00 nop
|
|
8002494: 20000120 .word 0x20000120
|
|
|
|
08002498 <_realloc_r>:
|
|
8002498: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr}
|
|
800249c: 4680 mov r8, r0
|
|
800249e: 4614 mov r4, r2
|
|
80024a0: 460e mov r6, r1
|
|
80024a2: b921 cbnz r1, 80024ae <_realloc_r+0x16>
|
|
80024a4: 4611 mov r1, r2
|
|
80024a6: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr}
|
|
80024aa: f7ff bf81 b.w 80023b0 <_malloc_r>
|
|
80024ae: b92a cbnz r2, 80024bc <_realloc_r+0x24>
|
|
80024b0: f7ff ff16 bl 80022e0 <_free_r>
|
|
80024b4: 4625 mov r5, r4
|
|
80024b6: 4628 mov r0, r5
|
|
80024b8: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc}
|
|
80024bc: f000 f838 bl 8002530 <_malloc_usable_size_r>
|
|
80024c0: 4284 cmp r4, r0
|
|
80024c2: 4607 mov r7, r0
|
|
80024c4: d802 bhi.n 80024cc <_realloc_r+0x34>
|
|
80024c6: ebb4 0f50 cmp.w r4, r0, lsr #1
|
|
80024ca: d812 bhi.n 80024f2 <_realloc_r+0x5a>
|
|
80024cc: 4621 mov r1, r4
|
|
80024ce: 4640 mov r0, r8
|
|
80024d0: f7ff ff6e bl 80023b0 <_malloc_r>
|
|
80024d4: 4605 mov r5, r0
|
|
80024d6: 2800 cmp r0, #0
|
|
80024d8: d0ed beq.n 80024b6 <_realloc_r+0x1e>
|
|
80024da: 42bc cmp r4, r7
|
|
80024dc: 4622 mov r2, r4
|
|
80024de: 4631 mov r1, r6
|
|
80024e0: bf28 it cs
|
|
80024e2: 463a movcs r2, r7
|
|
80024e4: f7ff fed4 bl 8002290 <memcpy>
|
|
80024e8: 4631 mov r1, r6
|
|
80024ea: 4640 mov r0, r8
|
|
80024ec: f7ff fef8 bl 80022e0 <_free_r>
|
|
80024f0: e7e1 b.n 80024b6 <_realloc_r+0x1e>
|
|
80024f2: 4635 mov r5, r6
|
|
80024f4: e7df b.n 80024b6 <_realloc_r+0x1e>
|
|
...
|
|
|
|
080024f8 <_sbrk_r>:
|
|
80024f8: b538 push {r3, r4, r5, lr}
|
|
80024fa: 2300 movs r3, #0
|
|
80024fc: 4d05 ldr r5, [pc, #20] ; (8002514 <_sbrk_r+0x1c>)
|
|
80024fe: 4604 mov r4, r0
|
|
8002500: 4608 mov r0, r1
|
|
8002502: 602b str r3, [r5, #0]
|
|
8002504: f7fd ff30 bl 8000368 <_sbrk>
|
|
8002508: 1c43 adds r3, r0, #1
|
|
800250a: d102 bne.n 8002512 <_sbrk_r+0x1a>
|
|
800250c: 682b ldr r3, [r5, #0]
|
|
800250e: b103 cbz r3, 8002512 <_sbrk_r+0x1a>
|
|
8002510: 6023 str r3, [r4, #0]
|
|
8002512: bd38 pop {r3, r4, r5, pc}
|
|
8002514: 20000128 .word 0x20000128
|
|
|
|
08002518 <__malloc_lock>:
|
|
8002518: 4801 ldr r0, [pc, #4] ; (8002520 <__malloc_lock+0x8>)
|
|
800251a: f000 b811 b.w 8002540 <__retarget_lock_acquire_recursive>
|
|
800251e: bf00 nop
|
|
8002520: 2000012c .word 0x2000012c
|
|
|
|
08002524 <__malloc_unlock>:
|
|
8002524: 4801 ldr r0, [pc, #4] ; (800252c <__malloc_unlock+0x8>)
|
|
8002526: f000 b80c b.w 8002542 <__retarget_lock_release_recursive>
|
|
800252a: bf00 nop
|
|
800252c: 2000012c .word 0x2000012c
|
|
|
|
08002530 <_malloc_usable_size_r>:
|
|
8002530: f851 3c04 ldr.w r3, [r1, #-4]
|
|
8002534: 1f18 subs r0, r3, #4
|
|
8002536: 2b00 cmp r3, #0
|
|
8002538: bfbc itt lt
|
|
800253a: 580b ldrlt r3, [r1, r0]
|
|
800253c: 18c0 addlt r0, r0, r3
|
|
800253e: 4770 bx lr
|
|
|
|
08002540 <__retarget_lock_acquire_recursive>:
|
|
8002540: 4770 bx lr
|
|
|
|
08002542 <__retarget_lock_release_recursive>:
|
|
8002542: 4770 bx lr
|
|
|
|
08002544 <_init>:
|
|
8002544: b5f8 push {r3, r4, r5, r6, r7, lr}
|
|
8002546: bf00 nop
|
|
8002548: bcf8 pop {r3, r4, r5, r6, r7}
|
|
800254a: bc08 pop {r3}
|
|
800254c: 469e mov lr, r3
|
|
800254e: 4770 bx lr
|
|
|
|
08002550 <_fini>:
|
|
8002550: b5f8 push {r3, r4, r5, r6, r7, lr}
|
|
8002552: bf00 nop
|
|
8002554: bcf8 pop {r3, r4, r5, r6, r7}
|
|
8002556: bc08 pop {r3}
|
|
8002558: 469e mov lr, r3
|
|
800255a: 4770 bx lr
|