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Timer_UltraSonic.elf: file format elf32-littlearm
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Sections:
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Idx Name Size VMA LMA File off Algn
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0 .isr_vector 0000010c 08000000 08000000 00010000 2**0
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CONTENTS, ALLOC, LOAD, READONLY, DATA
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1 .text 00002ee0 08000110 08000110 00010110 2**3
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CONTENTS, ALLOC, LOAD, READONLY, CODE
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2 .rodata 0000006c 08002ff0 08002ff0 00012ff0 2**2
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CONTENTS, ALLOC, LOAD, READONLY, DATA
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3 .ARM.extab 00000000 0800305c 0800305c 00020070 2**0
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CONTENTS
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4 .ARM 00000000 0800305c 0800305c 00020070 2**0
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CONTENTS
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5 .preinit_array 00000000 0800305c 0800305c 00020070 2**0
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CONTENTS, ALLOC, LOAD, DATA
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6 .init_array 00000004 0800305c 0800305c 0001305c 2**2
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CONTENTS, ALLOC, LOAD, DATA
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7 .fini_array 00000004 08003060 08003060 00013060 2**2
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CONTENTS, ALLOC, LOAD, DATA
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8 .data 00000070 20000000 08003064 00020000 2**2
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CONTENTS, ALLOC, LOAD, DATA
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9 .bss 000000c0 20000070 080030d4 00020070 2**2
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ALLOC
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10 ._user_heap_stack 00000600 20000130 080030d4 00020130 2**0
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ALLOC
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11 .ARM.attributes 00000029 00000000 00000000 00020070 2**0
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CONTENTS, READONLY
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12 .debug_info 00009c31 00000000 00000000 00020099 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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13 .debug_abbrev 00001aed 00000000 00000000 00029cca 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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14 .debug_aranges 00000ba0 00000000 00000000 0002b7b8 2**3
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CONTENTS, READONLY, DEBUGGING, OCTETS
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15 .debug_ranges 00000ad8 00000000 00000000 0002c358 2**3
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CONTENTS, READONLY, DEBUGGING, OCTETS
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16 .debug_macro 00017f0d 00000000 00000000 0002ce30 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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17 .debug_line 0000c834 00000000 00000000 00044d3d 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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18 .debug_str 0008a4a2 00000000 00000000 00051571 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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19 .comment 00000050 00000000 00000000 000dba13 2**0
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CONTENTS, READONLY
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20 .debug_frame 000034fc 00000000 00000000 000dba64 2**2
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CONTENTS, READONLY, DEBUGGING, OCTETS
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Disassembly of section .text:
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08000110 <__do_global_dtors_aux>:
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8000110: b510 push {r4, lr}
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8000112: 4c05 ldr r4, [pc, #20] ; (8000128 <__do_global_dtors_aux+0x18>)
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8000114: 7823 ldrb r3, [r4, #0]
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8000116: b933 cbnz r3, 8000126 <__do_global_dtors_aux+0x16>
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8000118: 4b04 ldr r3, [pc, #16] ; (800012c <__do_global_dtors_aux+0x1c>)
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800011a: b113 cbz r3, 8000122 <__do_global_dtors_aux+0x12>
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800011c: 4804 ldr r0, [pc, #16] ; (8000130 <__do_global_dtors_aux+0x20>)
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800011e: f3af 8000 nop.w
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8000122: 2301 movs r3, #1
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8000124: 7023 strb r3, [r4, #0]
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8000126: bd10 pop {r4, pc}
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8000128: 20000070 .word 0x20000070
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800012c: 00000000 .word 0x00000000
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8000130: 08002fd8 .word 0x08002fd8
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08000134 <frame_dummy>:
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8000134: b508 push {r3, lr}
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8000136: 4b03 ldr r3, [pc, #12] ; (8000144 <frame_dummy+0x10>)
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8000138: b11b cbz r3, 8000142 <frame_dummy+0xe>
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800013a: 4903 ldr r1, [pc, #12] ; (8000148 <frame_dummy+0x14>)
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800013c: 4803 ldr r0, [pc, #12] ; (800014c <frame_dummy+0x18>)
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800013e: f3af 8000 nop.w
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8000142: bd08 pop {r3, pc}
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8000144: 00000000 .word 0x00000000
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8000148: 20000074 .word 0x20000074
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800014c: 08002fd8 .word 0x08002fd8
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08000150 <strlen>:
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8000150: 4603 mov r3, r0
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8000152: f813 2b01 ldrb.w r2, [r3], #1
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8000156: 2a00 cmp r2, #0
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8000158: d1fb bne.n 8000152 <strlen+0x2>
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800015a: 1a18 subs r0, r3, r0
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800015c: 3801 subs r0, #1
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800015e: 4770 bx lr
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08000160 <__aeabi_dmul>:
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8000160: b570 push {r4, r5, r6, lr}
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8000162: f04f 0cff mov.w ip, #255 ; 0xff
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8000166: f44c 6ce0 orr.w ip, ip, #1792 ; 0x700
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800016a: ea1c 5411 ands.w r4, ip, r1, lsr #20
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800016e: bf1d ittte ne
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8000170: ea1c 5513 andsne.w r5, ip, r3, lsr #20
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8000174: ea94 0f0c teqne r4, ip
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8000178: ea95 0f0c teqne r5, ip
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800017c: f000 f8de bleq 800033c <__aeabi_dmul+0x1dc>
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8000180: 442c add r4, r5
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8000182: ea81 0603 eor.w r6, r1, r3
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8000186: ea21 514c bic.w r1, r1, ip, lsl #21
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800018a: ea23 534c bic.w r3, r3, ip, lsl #21
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800018e: ea50 3501 orrs.w r5, r0, r1, lsl #12
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8000192: bf18 it ne
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8000194: ea52 3503 orrsne.w r5, r2, r3, lsl #12
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8000198: f441 1180 orr.w r1, r1, #1048576 ; 0x100000
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800019c: f443 1380 orr.w r3, r3, #1048576 ; 0x100000
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80001a0: d038 beq.n 8000214 <__aeabi_dmul+0xb4>
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80001a2: fba0 ce02 umull ip, lr, r0, r2
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80001a6: f04f 0500 mov.w r5, #0
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80001aa: fbe1 e502 umlal lr, r5, r1, r2
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80001ae: f006 4200 and.w r2, r6, #2147483648 ; 0x80000000
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80001b2: fbe0 e503 umlal lr, r5, r0, r3
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80001b6: f04f 0600 mov.w r6, #0
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80001ba: fbe1 5603 umlal r5, r6, r1, r3
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80001be: f09c 0f00 teq ip, #0
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80001c2: bf18 it ne
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80001c4: f04e 0e01 orrne.w lr, lr, #1
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80001c8: f1a4 04ff sub.w r4, r4, #255 ; 0xff
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80001cc: f5b6 7f00 cmp.w r6, #512 ; 0x200
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80001d0: f564 7440 sbc.w r4, r4, #768 ; 0x300
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80001d4: d204 bcs.n 80001e0 <__aeabi_dmul+0x80>
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80001d6: ea5f 0e4e movs.w lr, lr, lsl #1
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80001da: 416d adcs r5, r5
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80001dc: eb46 0606 adc.w r6, r6, r6
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80001e0: ea42 21c6 orr.w r1, r2, r6, lsl #11
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80001e4: ea41 5155 orr.w r1, r1, r5, lsr #21
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80001e8: ea4f 20c5 mov.w r0, r5, lsl #11
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80001ec: ea40 505e orr.w r0, r0, lr, lsr #21
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80001f0: ea4f 2ece mov.w lr, lr, lsl #11
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80001f4: f1b4 0cfd subs.w ip, r4, #253 ; 0xfd
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80001f8: bf88 it hi
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80001fa: f5bc 6fe0 cmphi.w ip, #1792 ; 0x700
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80001fe: d81e bhi.n 800023e <__aeabi_dmul+0xde>
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8000200: f1be 4f00 cmp.w lr, #2147483648 ; 0x80000000
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8000204: bf08 it eq
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8000206: ea5f 0e50 movseq.w lr, r0, lsr #1
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800020a: f150 0000 adcs.w r0, r0, #0
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800020e: eb41 5104 adc.w r1, r1, r4, lsl #20
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8000212: bd70 pop {r4, r5, r6, pc}
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8000214: f006 4600 and.w r6, r6, #2147483648 ; 0x80000000
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8000218: ea46 0101 orr.w r1, r6, r1
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800021c: ea40 0002 orr.w r0, r0, r2
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8000220: ea81 0103 eor.w r1, r1, r3
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8000224: ebb4 045c subs.w r4, r4, ip, lsr #1
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8000228: bfc2 ittt gt
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800022a: ebd4 050c rsbsgt r5, r4, ip
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800022e: ea41 5104 orrgt.w r1, r1, r4, lsl #20
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8000232: bd70 popgt {r4, r5, r6, pc}
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8000234: f441 1180 orr.w r1, r1, #1048576 ; 0x100000
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8000238: f04f 0e00 mov.w lr, #0
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800023c: 3c01 subs r4, #1
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800023e: f300 80ab bgt.w 8000398 <__aeabi_dmul+0x238>
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8000242: f114 0f36 cmn.w r4, #54 ; 0x36
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8000246: bfde ittt le
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8000248: 2000 movle r0, #0
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800024a: f001 4100 andle.w r1, r1, #2147483648 ; 0x80000000
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800024e: bd70 pople {r4, r5, r6, pc}
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8000250: f1c4 0400 rsb r4, r4, #0
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8000254: 3c20 subs r4, #32
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8000256: da35 bge.n 80002c4 <__aeabi_dmul+0x164>
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8000258: 340c adds r4, #12
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800025a: dc1b bgt.n 8000294 <__aeabi_dmul+0x134>
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800025c: f104 0414 add.w r4, r4, #20
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8000260: f1c4 0520 rsb r5, r4, #32
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8000264: fa00 f305 lsl.w r3, r0, r5
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8000268: fa20 f004 lsr.w r0, r0, r4
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800026c: fa01 f205 lsl.w r2, r1, r5
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8000270: ea40 0002 orr.w r0, r0, r2
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8000274: f001 4200 and.w r2, r1, #2147483648 ; 0x80000000
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8000278: f021 4100 bic.w r1, r1, #2147483648 ; 0x80000000
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800027c: eb10 70d3 adds.w r0, r0, r3, lsr #31
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8000280: fa21 f604 lsr.w r6, r1, r4
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8000284: eb42 0106 adc.w r1, r2, r6
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8000288: ea5e 0e43 orrs.w lr, lr, r3, lsl #1
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800028c: bf08 it eq
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800028e: ea20 70d3 biceq.w r0, r0, r3, lsr #31
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8000292: bd70 pop {r4, r5, r6, pc}
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8000294: f1c4 040c rsb r4, r4, #12
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8000298: f1c4 0520 rsb r5, r4, #32
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800029c: fa00 f304 lsl.w r3, r0, r4
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80002a0: fa20 f005 lsr.w r0, r0, r5
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80002a4: fa01 f204 lsl.w r2, r1, r4
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80002a8: ea40 0002 orr.w r0, r0, r2
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80002ac: f001 4100 and.w r1, r1, #2147483648 ; 0x80000000
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80002b0: eb10 70d3 adds.w r0, r0, r3, lsr #31
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80002b4: f141 0100 adc.w r1, r1, #0
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80002b8: ea5e 0e43 orrs.w lr, lr, r3, lsl #1
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80002bc: bf08 it eq
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80002be: ea20 70d3 biceq.w r0, r0, r3, lsr #31
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80002c2: bd70 pop {r4, r5, r6, pc}
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80002c4: f1c4 0520 rsb r5, r4, #32
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80002c8: fa00 f205 lsl.w r2, r0, r5
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80002cc: ea4e 0e02 orr.w lr, lr, r2
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80002d0: fa20 f304 lsr.w r3, r0, r4
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80002d4: fa01 f205 lsl.w r2, r1, r5
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80002d8: ea43 0302 orr.w r3, r3, r2
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80002dc: fa21 f004 lsr.w r0, r1, r4
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80002e0: f001 4100 and.w r1, r1, #2147483648 ; 0x80000000
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80002e4: fa21 f204 lsr.w r2, r1, r4
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80002e8: ea20 0002 bic.w r0, r0, r2
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80002ec: eb00 70d3 add.w r0, r0, r3, lsr #31
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80002f0: ea5e 0e43 orrs.w lr, lr, r3, lsl #1
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80002f4: bf08 it eq
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80002f6: ea20 70d3 biceq.w r0, r0, r3, lsr #31
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80002fa: bd70 pop {r4, r5, r6, pc}
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80002fc: f094 0f00 teq r4, #0
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8000300: d10f bne.n 8000322 <__aeabi_dmul+0x1c2>
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8000302: f001 4600 and.w r6, r1, #2147483648 ; 0x80000000
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8000306: 0040 lsls r0, r0, #1
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8000308: eb41 0101 adc.w r1, r1, r1
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800030c: f411 1f80 tst.w r1, #1048576 ; 0x100000
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8000310: bf08 it eq
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8000312: 3c01 subeq r4, #1
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8000314: d0f7 beq.n 8000306 <__aeabi_dmul+0x1a6>
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8000316: ea41 0106 orr.w r1, r1, r6
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800031a: f095 0f00 teq r5, #0
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800031e: bf18 it ne
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8000320: 4770 bxne lr
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8000322: f003 4600 and.w r6, r3, #2147483648 ; 0x80000000
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8000326: 0052 lsls r2, r2, #1
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8000328: eb43 0303 adc.w r3, r3, r3
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800032c: f413 1f80 tst.w r3, #1048576 ; 0x100000
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8000330: bf08 it eq
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8000332: 3d01 subeq r5, #1
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8000334: d0f7 beq.n 8000326 <__aeabi_dmul+0x1c6>
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8000336: ea43 0306 orr.w r3, r3, r6
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800033a: 4770 bx lr
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800033c: ea94 0f0c teq r4, ip
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8000340: ea0c 5513 and.w r5, ip, r3, lsr #20
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8000344: bf18 it ne
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8000346: ea95 0f0c teqne r5, ip
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800034a: d00c beq.n 8000366 <__aeabi_dmul+0x206>
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800034c: ea50 0641 orrs.w r6, r0, r1, lsl #1
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8000350: bf18 it ne
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8000352: ea52 0643 orrsne.w r6, r2, r3, lsl #1
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8000356: d1d1 bne.n 80002fc <__aeabi_dmul+0x19c>
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8000358: ea81 0103 eor.w r1, r1, r3
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800035c: f001 4100 and.w r1, r1, #2147483648 ; 0x80000000
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8000360: f04f 0000 mov.w r0, #0
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8000364: bd70 pop {r4, r5, r6, pc}
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8000366: ea50 0641 orrs.w r6, r0, r1, lsl #1
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800036a: bf06 itte eq
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800036c: 4610 moveq r0, r2
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800036e: 4619 moveq r1, r3
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8000370: ea52 0643 orrsne.w r6, r2, r3, lsl #1
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8000374: d019 beq.n 80003aa <__aeabi_dmul+0x24a>
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8000376: ea94 0f0c teq r4, ip
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800037a: d102 bne.n 8000382 <__aeabi_dmul+0x222>
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800037c: ea50 3601 orrs.w r6, r0, r1, lsl #12
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8000380: d113 bne.n 80003aa <__aeabi_dmul+0x24a>
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8000382: ea95 0f0c teq r5, ip
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8000386: d105 bne.n 8000394 <__aeabi_dmul+0x234>
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8000388: ea52 3603 orrs.w r6, r2, r3, lsl #12
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800038c: bf1c itt ne
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800038e: 4610 movne r0, r2
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8000390: 4619 movne r1, r3
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8000392: d10a bne.n 80003aa <__aeabi_dmul+0x24a>
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8000394: ea81 0103 eor.w r1, r1, r3
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8000398: f001 4100 and.w r1, r1, #2147483648 ; 0x80000000
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800039c: f041 41fe orr.w r1, r1, #2130706432 ; 0x7f000000
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80003a0: f441 0170 orr.w r1, r1, #15728640 ; 0xf00000
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80003a4: f04f 0000 mov.w r0, #0
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80003a8: bd70 pop {r4, r5, r6, pc}
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80003aa: f041 41fe orr.w r1, r1, #2130706432 ; 0x7f000000
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80003ae: f441 0178 orr.w r1, r1, #16252928 ; 0xf80000
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80003b2: bd70 pop {r4, r5, r6, pc}
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080003b4 <__aeabi_drsub>:
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80003b4: f081 4100 eor.w r1, r1, #2147483648 ; 0x80000000
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80003b8: e002 b.n 80003c0 <__adddf3>
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80003ba: bf00 nop
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080003bc <__aeabi_dsub>:
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80003bc: f083 4300 eor.w r3, r3, #2147483648 ; 0x80000000
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080003c0 <__adddf3>:
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|
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80003c0: b530 push {r4, r5, lr}
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80003c2: ea4f 0441 mov.w r4, r1, lsl #1
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80003c6: ea4f 0543 mov.w r5, r3, lsl #1
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80003ca: ea94 0f05 teq r4, r5
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80003ce: bf08 it eq
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|
80003d0: ea90 0f02 teqeq r0, r2
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80003d4: bf1f itttt ne
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|
80003d6: ea54 0c00 orrsne.w ip, r4, r0
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80003da: ea55 0c02 orrsne.w ip, r5, r2
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80003de: ea7f 5c64 mvnsne.w ip, r4, asr #21
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80003e2: ea7f 5c65 mvnsne.w ip, r5, asr #21
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80003e6: f000 80e2 beq.w 80005ae <__adddf3+0x1ee>
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80003ea: ea4f 5454 mov.w r4, r4, lsr #21
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80003ee: ebd4 5555 rsbs r5, r4, r5, lsr #21
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80003f2: bfb8 it lt
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80003f4: 426d neglt r5, r5
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80003f6: dd0c ble.n 8000412 <__adddf3+0x52>
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80003f8: 442c add r4, r5
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80003fa: ea80 0202 eor.w r2, r0, r2
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80003fe: ea81 0303 eor.w r3, r1, r3
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8000402: ea82 0000 eor.w r0, r2, r0
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8000406: ea83 0101 eor.w r1, r3, r1
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800040a: ea80 0202 eor.w r2, r0, r2
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800040e: ea81 0303 eor.w r3, r1, r3
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8000412: 2d36 cmp r5, #54 ; 0x36
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8000414: bf88 it hi
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8000416: bd30 pophi {r4, r5, pc}
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8000418: f011 4f00 tst.w r1, #2147483648 ; 0x80000000
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800041c: ea4f 3101 mov.w r1, r1, lsl #12
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8000420: f44f 1c80 mov.w ip, #1048576 ; 0x100000
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8000424: ea4c 3111 orr.w r1, ip, r1, lsr #12
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8000428: d002 beq.n 8000430 <__adddf3+0x70>
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800042a: 4240 negs r0, r0
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800042c: eb61 0141 sbc.w r1, r1, r1, lsl #1
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8000430: f013 4f00 tst.w r3, #2147483648 ; 0x80000000
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8000434: ea4f 3303 mov.w r3, r3, lsl #12
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8000438: ea4c 3313 orr.w r3, ip, r3, lsr #12
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800043c: d002 beq.n 8000444 <__adddf3+0x84>
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800043e: 4252 negs r2, r2
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8000440: eb63 0343 sbc.w r3, r3, r3, lsl #1
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8000444: ea94 0f05 teq r4, r5
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8000448: f000 80a7 beq.w 800059a <__adddf3+0x1da>
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800044c: f1a4 0401 sub.w r4, r4, #1
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8000450: f1d5 0e20 rsbs lr, r5, #32
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8000454: db0d blt.n 8000472 <__adddf3+0xb2>
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8000456: fa02 fc0e lsl.w ip, r2, lr
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800045a: fa22 f205 lsr.w r2, r2, r5
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800045e: 1880 adds r0, r0, r2
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8000460: f141 0100 adc.w r1, r1, #0
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8000464: fa03 f20e lsl.w r2, r3, lr
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8000468: 1880 adds r0, r0, r2
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800046a: fa43 f305 asr.w r3, r3, r5
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800046e: 4159 adcs r1, r3
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8000470: e00e b.n 8000490 <__adddf3+0xd0>
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8000472: f1a5 0520 sub.w r5, r5, #32
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8000476: f10e 0e20 add.w lr, lr, #32
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800047a: 2a01 cmp r2, #1
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800047c: fa03 fc0e lsl.w ip, r3, lr
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8000480: bf28 it cs
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8000482: f04c 0c02 orrcs.w ip, ip, #2
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8000486: fa43 f305 asr.w r3, r3, r5
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800048a: 18c0 adds r0, r0, r3
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800048c: eb51 71e3 adcs.w r1, r1, r3, asr #31
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8000490: f001 4500 and.w r5, r1, #2147483648 ; 0x80000000
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8000494: d507 bpl.n 80004a6 <__adddf3+0xe6>
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8000496: f04f 0e00 mov.w lr, #0
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800049a: f1dc 0c00 rsbs ip, ip, #0
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800049e: eb7e 0000 sbcs.w r0, lr, r0
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80004a2: eb6e 0101 sbc.w r1, lr, r1
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80004a6: f5b1 1f80 cmp.w r1, #1048576 ; 0x100000
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80004aa: d31b bcc.n 80004e4 <__adddf3+0x124>
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80004ac: f5b1 1f00 cmp.w r1, #2097152 ; 0x200000
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80004b0: d30c bcc.n 80004cc <__adddf3+0x10c>
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80004b2: 0849 lsrs r1, r1, #1
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80004b4: ea5f 0030 movs.w r0, r0, rrx
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80004b8: ea4f 0c3c mov.w ip, ip, rrx
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80004bc: f104 0401 add.w r4, r4, #1
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80004c0: ea4f 5244 mov.w r2, r4, lsl #21
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80004c4: f512 0f80 cmn.w r2, #4194304 ; 0x400000
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80004c8: f080 809a bcs.w 8000600 <__adddf3+0x240>
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80004cc: f1bc 4f00 cmp.w ip, #2147483648 ; 0x80000000
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80004d0: bf08 it eq
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80004d2: ea5f 0c50 movseq.w ip, r0, lsr #1
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80004d6: f150 0000 adcs.w r0, r0, #0
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80004da: eb41 5104 adc.w r1, r1, r4, lsl #20
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80004de: ea41 0105 orr.w r1, r1, r5
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80004e2: bd30 pop {r4, r5, pc}
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80004e4: ea5f 0c4c movs.w ip, ip, lsl #1
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80004e8: 4140 adcs r0, r0
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80004ea: eb41 0101 adc.w r1, r1, r1
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80004ee: 3c01 subs r4, #1
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80004f0: bf28 it cs
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80004f2: f5b1 1f80 cmpcs.w r1, #1048576 ; 0x100000
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80004f6: d2e9 bcs.n 80004cc <__adddf3+0x10c>
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80004f8: f091 0f00 teq r1, #0
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80004fc: bf04 itt eq
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80004fe: 4601 moveq r1, r0
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8000500: 2000 moveq r0, #0
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8000502: fab1 f381 clz r3, r1
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8000506: bf08 it eq
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8000508: 3320 addeq r3, #32
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800050a: f1a3 030b sub.w r3, r3, #11
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800050e: f1b3 0220 subs.w r2, r3, #32
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8000512: da0c bge.n 800052e <__adddf3+0x16e>
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8000514: 320c adds r2, #12
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8000516: dd08 ble.n 800052a <__adddf3+0x16a>
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8000518: f102 0c14 add.w ip, r2, #20
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800051c: f1c2 020c rsb r2, r2, #12
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8000520: fa01 f00c lsl.w r0, r1, ip
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8000524: fa21 f102 lsr.w r1, r1, r2
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8000528: e00c b.n 8000544 <__adddf3+0x184>
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800052a: f102 0214 add.w r2, r2, #20
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800052e: bfd8 it le
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8000530: f1c2 0c20 rsble ip, r2, #32
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8000534: fa01 f102 lsl.w r1, r1, r2
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8000538: fa20 fc0c lsr.w ip, r0, ip
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800053c: bfdc itt le
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800053e: ea41 010c orrle.w r1, r1, ip
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8000542: 4090 lslle r0, r2
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8000544: 1ae4 subs r4, r4, r3
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8000546: bfa2 ittt ge
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8000548: eb01 5104 addge.w r1, r1, r4, lsl #20
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800054c: 4329 orrge r1, r5
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800054e: bd30 popge {r4, r5, pc}
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8000550: ea6f 0404 mvn.w r4, r4
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8000554: 3c1f subs r4, #31
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8000556: da1c bge.n 8000592 <__adddf3+0x1d2>
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8000558: 340c adds r4, #12
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800055a: dc0e bgt.n 800057a <__adddf3+0x1ba>
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800055c: f104 0414 add.w r4, r4, #20
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8000560: f1c4 0220 rsb r2, r4, #32
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8000564: fa20 f004 lsr.w r0, r0, r4
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8000568: fa01 f302 lsl.w r3, r1, r2
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800056c: ea40 0003 orr.w r0, r0, r3
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8000570: fa21 f304 lsr.w r3, r1, r4
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8000574: ea45 0103 orr.w r1, r5, r3
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8000578: bd30 pop {r4, r5, pc}
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800057a: f1c4 040c rsb r4, r4, #12
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800057e: f1c4 0220 rsb r2, r4, #32
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8000582: fa20 f002 lsr.w r0, r0, r2
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8000586: fa01 f304 lsl.w r3, r1, r4
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800058a: ea40 0003 orr.w r0, r0, r3
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800058e: 4629 mov r1, r5
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8000590: bd30 pop {r4, r5, pc}
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8000592: fa21 f004 lsr.w r0, r1, r4
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8000596: 4629 mov r1, r5
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8000598: bd30 pop {r4, r5, pc}
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800059a: f094 0f00 teq r4, #0
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800059e: f483 1380 eor.w r3, r3, #1048576 ; 0x100000
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80005a2: bf06 itte eq
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80005a4: f481 1180 eoreq.w r1, r1, #1048576 ; 0x100000
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80005a8: 3401 addeq r4, #1
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80005aa: 3d01 subne r5, #1
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80005ac: e74e b.n 800044c <__adddf3+0x8c>
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80005ae: ea7f 5c64 mvns.w ip, r4, asr #21
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80005b2: bf18 it ne
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80005b4: ea7f 5c65 mvnsne.w ip, r5, asr #21
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80005b8: d029 beq.n 800060e <__adddf3+0x24e>
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80005ba: ea94 0f05 teq r4, r5
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80005be: bf08 it eq
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80005c0: ea90 0f02 teqeq r0, r2
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80005c4: d005 beq.n 80005d2 <__adddf3+0x212>
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80005c6: ea54 0c00 orrs.w ip, r4, r0
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80005ca: bf04 itt eq
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80005cc: 4619 moveq r1, r3
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80005ce: 4610 moveq r0, r2
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80005d0: bd30 pop {r4, r5, pc}
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80005d2: ea91 0f03 teq r1, r3
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80005d6: bf1e ittt ne
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|
|
80005d8: 2100 movne r1, #0
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|
80005da: 2000 movne r0, #0
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|
80005dc: bd30 popne {r4, r5, pc}
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|
80005de: ea5f 5c54 movs.w ip, r4, lsr #21
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80005e2: d105 bne.n 80005f0 <__adddf3+0x230>
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|
80005e4: 0040 lsls r0, r0, #1
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80005e6: 4149 adcs r1, r1
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80005e8: bf28 it cs
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|
80005ea: f041 4100 orrcs.w r1, r1, #2147483648 ; 0x80000000
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80005ee: bd30 pop {r4, r5, pc}
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80005f0: f514 0480 adds.w r4, r4, #4194304 ; 0x400000
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80005f4: bf3c itt cc
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80005f6: f501 1180 addcc.w r1, r1, #1048576 ; 0x100000
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80005fa: bd30 popcc {r4, r5, pc}
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|
80005fc: f001 4500 and.w r5, r1, #2147483648 ; 0x80000000
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8000600: f045 41fe orr.w r1, r5, #2130706432 ; 0x7f000000
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|
8000604: f441 0170 orr.w r1, r1, #15728640 ; 0xf00000
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|
8000608: f04f 0000 mov.w r0, #0
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800060c: bd30 pop {r4, r5, pc}
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800060e: ea7f 5c64 mvns.w ip, r4, asr #21
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|
8000612: bf1a itte ne
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|
8000614: 4619 movne r1, r3
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|
8000616: 4610 movne r0, r2
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|
8000618: ea7f 5c65 mvnseq.w ip, r5, asr #21
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|
800061c: bf1c itt ne
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|
800061e: 460b movne r3, r1
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8000620: 4602 movne r2, r0
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8000622: ea50 3401 orrs.w r4, r0, r1, lsl #12
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8000626: bf06 itte eq
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8000628: ea52 3503 orrseq.w r5, r2, r3, lsl #12
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|
800062c: ea91 0f03 teqeq r1, r3
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|
8000630: f441 2100 orrne.w r1, r1, #524288 ; 0x80000
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|
8000634: bd30 pop {r4, r5, pc}
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|
8000636: bf00 nop
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|
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|
08000638 <__aeabi_ui2d>:
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|
8000638: f090 0f00 teq r0, #0
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800063c: bf04 itt eq
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|
|
800063e: 2100 moveq r1, #0
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8000640: 4770 bxeq lr
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|
8000642: b530 push {r4, r5, lr}
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|
8000644: f44f 6480 mov.w r4, #1024 ; 0x400
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|
8000648: f104 0432 add.w r4, r4, #50 ; 0x32
|
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|
800064c: f04f 0500 mov.w r5, #0
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|
|
8000650: f04f 0100 mov.w r1, #0
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|
|
8000654: e750 b.n 80004f8 <__adddf3+0x138>
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|
8000656: bf00 nop
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|
08000658 <__aeabi_i2d>:
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|
|
8000658: f090 0f00 teq r0, #0
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|
800065c: bf04 itt eq
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|
800065e: 2100 moveq r1, #0
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|
8000660: 4770 bxeq lr
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|
|
8000662: b530 push {r4, r5, lr}
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|
|
8000664: f44f 6480 mov.w r4, #1024 ; 0x400
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|
8000668: f104 0432 add.w r4, r4, #50 ; 0x32
|
|
|
800066c: f010 4500 ands.w r5, r0, #2147483648 ; 0x80000000
|
|
|
8000670: bf48 it mi
|
|
|
8000672: 4240 negmi r0, r0
|
|
|
8000674: f04f 0100 mov.w r1, #0
|
|
|
8000678: e73e b.n 80004f8 <__adddf3+0x138>
|
|
|
800067a: bf00 nop
|
|
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|
|
|
0800067c <__aeabi_f2d>:
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|
|
800067c: 0042 lsls r2, r0, #1
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|
800067e: ea4f 01e2 mov.w r1, r2, asr #3
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|
8000682: ea4f 0131 mov.w r1, r1, rrx
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|
8000686: ea4f 7002 mov.w r0, r2, lsl #28
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|
800068a: bf1f itttt ne
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|
800068c: f012 437f andsne.w r3, r2, #4278190080 ; 0xff000000
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|
8000690: f093 4f7f teqne r3, #4278190080 ; 0xff000000
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|
|
8000694: f081 5160 eorne.w r1, r1, #939524096 ; 0x38000000
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|
|
8000698: 4770 bxne lr
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|
|
800069a: f032 427f bics.w r2, r2, #4278190080 ; 0xff000000
|
|
|
800069e: bf08 it eq
|
|
|
80006a0: 4770 bxeq lr
|
|
|
80006a2: f093 4f7f teq r3, #4278190080 ; 0xff000000
|
|
|
80006a6: bf04 itt eq
|
|
|
80006a8: f441 2100 orreq.w r1, r1, #524288 ; 0x80000
|
|
|
80006ac: 4770 bxeq lr
|
|
|
80006ae: b530 push {r4, r5, lr}
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|
|
80006b0: f44f 7460 mov.w r4, #896 ; 0x380
|
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|
80006b4: f001 4500 and.w r5, r1, #2147483648 ; 0x80000000
|
|
|
80006b8: f021 4100 bic.w r1, r1, #2147483648 ; 0x80000000
|
|
|
80006bc: e71c b.n 80004f8 <__adddf3+0x138>
|
|
|
80006be: bf00 nop
|
|
|
|
|
|
080006c0 <__aeabi_ul2d>:
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|
|
80006c0: ea50 0201 orrs.w r2, r0, r1
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|
|
80006c4: bf08 it eq
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|
|
80006c6: 4770 bxeq lr
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|
|
80006c8: b530 push {r4, r5, lr}
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|
|
80006ca: f04f 0500 mov.w r5, #0
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|
|
80006ce: e00a b.n 80006e6 <__aeabi_l2d+0x16>
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|
|
|
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|
080006d0 <__aeabi_l2d>:
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|
|
80006d0: ea50 0201 orrs.w r2, r0, r1
|
|
|
80006d4: bf08 it eq
|
|
|
80006d6: 4770 bxeq lr
|
|
|
80006d8: b530 push {r4, r5, lr}
|
|
|
80006da: f011 4500 ands.w r5, r1, #2147483648 ; 0x80000000
|
|
|
80006de: d502 bpl.n 80006e6 <__aeabi_l2d+0x16>
|
|
|
80006e0: 4240 negs r0, r0
|
|
|
80006e2: eb61 0141 sbc.w r1, r1, r1, lsl #1
|
|
|
80006e6: f44f 6480 mov.w r4, #1024 ; 0x400
|
|
|
80006ea: f104 0432 add.w r4, r4, #50 ; 0x32
|
|
|
80006ee: ea5f 5c91 movs.w ip, r1, lsr #22
|
|
|
80006f2: f43f aed8 beq.w 80004a6 <__adddf3+0xe6>
|
|
|
80006f6: f04f 0203 mov.w r2, #3
|
|
|
80006fa: ea5f 0cdc movs.w ip, ip, lsr #3
|
|
|
80006fe: bf18 it ne
|
|
|
8000700: 3203 addne r2, #3
|
|
|
8000702: ea5f 0cdc movs.w ip, ip, lsr #3
|
|
|
8000706: bf18 it ne
|
|
|
8000708: 3203 addne r2, #3
|
|
|
800070a: eb02 02dc add.w r2, r2, ip, lsr #3
|
|
|
800070e: f1c2 0320 rsb r3, r2, #32
|
|
|
8000712: fa00 fc03 lsl.w ip, r0, r3
|
|
|
8000716: fa20 f002 lsr.w r0, r0, r2
|
|
|
800071a: fa01 fe03 lsl.w lr, r1, r3
|
|
|
800071e: ea40 000e orr.w r0, r0, lr
|
|
|
8000722: fa21 f102 lsr.w r1, r1, r2
|
|
|
8000726: 4414 add r4, r2
|
|
|
8000728: e6bd b.n 80004a6 <__adddf3+0xe6>
|
|
|
800072a: bf00 nop
|
|
|
|
|
|
0800072c <__aeabi_d2uiz>:
|
|
|
800072c: 004a lsls r2, r1, #1
|
|
|
800072e: d211 bcs.n 8000754 <__aeabi_d2uiz+0x28>
|
|
|
8000730: f512 1200 adds.w r2, r2, #2097152 ; 0x200000
|
|
|
8000734: d211 bcs.n 800075a <__aeabi_d2uiz+0x2e>
|
|
|
8000736: d50d bpl.n 8000754 <__aeabi_d2uiz+0x28>
|
|
|
8000738: f46f 7378 mvn.w r3, #992 ; 0x3e0
|
|
|
800073c: ebb3 5262 subs.w r2, r3, r2, asr #21
|
|
|
8000740: d40e bmi.n 8000760 <__aeabi_d2uiz+0x34>
|
|
|
8000742: ea4f 23c1 mov.w r3, r1, lsl #11
|
|
|
8000746: f043 4300 orr.w r3, r3, #2147483648 ; 0x80000000
|
|
|
800074a: ea43 5350 orr.w r3, r3, r0, lsr #21
|
|
|
800074e: fa23 f002 lsr.w r0, r3, r2
|
|
|
8000752: 4770 bx lr
|
|
|
8000754: f04f 0000 mov.w r0, #0
|
|
|
8000758: 4770 bx lr
|
|
|
800075a: ea50 3001 orrs.w r0, r0, r1, lsl #12
|
|
|
800075e: d102 bne.n 8000766 <__aeabi_d2uiz+0x3a>
|
|
|
8000760: f04f 30ff mov.w r0, #4294967295
|
|
|
8000764: 4770 bx lr
|
|
|
8000766: f04f 0000 mov.w r0, #0
|
|
|
800076a: 4770 bx lr
|
|
|
|
|
|
0800076c <__aeabi_frsub>:
|
|
|
800076c: f080 4000 eor.w r0, r0, #2147483648 ; 0x80000000
|
|
|
8000770: e002 b.n 8000778 <__addsf3>
|
|
|
8000772: bf00 nop
|
|
|
|
|
|
08000774 <__aeabi_fsub>:
|
|
|
8000774: f081 4100 eor.w r1, r1, #2147483648 ; 0x80000000
|
|
|
|
|
|
08000778 <__addsf3>:
|
|
|
8000778: 0042 lsls r2, r0, #1
|
|
|
800077a: bf1f itttt ne
|
|
|
800077c: ea5f 0341 movsne.w r3, r1, lsl #1
|
|
|
8000780: ea92 0f03 teqne r2, r3
|
|
|
8000784: ea7f 6c22 mvnsne.w ip, r2, asr #24
|
|
|
8000788: ea7f 6c23 mvnsne.w ip, r3, asr #24
|
|
|
800078c: d06a beq.n 8000864 <__addsf3+0xec>
|
|
|
800078e: ea4f 6212 mov.w r2, r2, lsr #24
|
|
|
8000792: ebd2 6313 rsbs r3, r2, r3, lsr #24
|
|
|
8000796: bfc1 itttt gt
|
|
|
8000798: 18d2 addgt r2, r2, r3
|
|
|
800079a: 4041 eorgt r1, r0
|
|
|
800079c: 4048 eorgt r0, r1
|
|
|
800079e: 4041 eorgt r1, r0
|
|
|
80007a0: bfb8 it lt
|
|
|
80007a2: 425b neglt r3, r3
|
|
|
80007a4: 2b19 cmp r3, #25
|
|
|
80007a6: bf88 it hi
|
|
|
80007a8: 4770 bxhi lr
|
|
|
80007aa: f010 4f00 tst.w r0, #2147483648 ; 0x80000000
|
|
|
80007ae: f440 0000 orr.w r0, r0, #8388608 ; 0x800000
|
|
|
80007b2: f020 407f bic.w r0, r0, #4278190080 ; 0xff000000
|
|
|
80007b6: bf18 it ne
|
|
|
80007b8: 4240 negne r0, r0
|
|
|
80007ba: f011 4f00 tst.w r1, #2147483648 ; 0x80000000
|
|
|
80007be: f441 0100 orr.w r1, r1, #8388608 ; 0x800000
|
|
|
80007c2: f021 417f bic.w r1, r1, #4278190080 ; 0xff000000
|
|
|
80007c6: bf18 it ne
|
|
|
80007c8: 4249 negne r1, r1
|
|
|
80007ca: ea92 0f03 teq r2, r3
|
|
|
80007ce: d03f beq.n 8000850 <__addsf3+0xd8>
|
|
|
80007d0: f1a2 0201 sub.w r2, r2, #1
|
|
|
80007d4: fa41 fc03 asr.w ip, r1, r3
|
|
|
80007d8: eb10 000c adds.w r0, r0, ip
|
|
|
80007dc: f1c3 0320 rsb r3, r3, #32
|
|
|
80007e0: fa01 f103 lsl.w r1, r1, r3
|
|
|
80007e4: f000 4300 and.w r3, r0, #2147483648 ; 0x80000000
|
|
|
80007e8: d502 bpl.n 80007f0 <__addsf3+0x78>
|
|
|
80007ea: 4249 negs r1, r1
|
|
|
80007ec: eb60 0040 sbc.w r0, r0, r0, lsl #1
|
|
|
80007f0: f5b0 0f00 cmp.w r0, #8388608 ; 0x800000
|
|
|
80007f4: d313 bcc.n 800081e <__addsf3+0xa6>
|
|
|
80007f6: f1b0 7f80 cmp.w r0, #16777216 ; 0x1000000
|
|
|
80007fa: d306 bcc.n 800080a <__addsf3+0x92>
|
|
|
80007fc: 0840 lsrs r0, r0, #1
|
|
|
80007fe: ea4f 0131 mov.w r1, r1, rrx
|
|
|
8000802: f102 0201 add.w r2, r2, #1
|
|
|
8000806: 2afe cmp r2, #254 ; 0xfe
|
|
|
8000808: d251 bcs.n 80008ae <__addsf3+0x136>
|
|
|
800080a: f1b1 4f00 cmp.w r1, #2147483648 ; 0x80000000
|
|
|
800080e: eb40 50c2 adc.w r0, r0, r2, lsl #23
|
|
|
8000812: bf08 it eq
|
|
|
8000814: f020 0001 biceq.w r0, r0, #1
|
|
|
8000818: ea40 0003 orr.w r0, r0, r3
|
|
|
800081c: 4770 bx lr
|
|
|
800081e: 0049 lsls r1, r1, #1
|
|
|
8000820: eb40 0000 adc.w r0, r0, r0
|
|
|
8000824: 3a01 subs r2, #1
|
|
|
8000826: bf28 it cs
|
|
|
8000828: f5b0 0f00 cmpcs.w r0, #8388608 ; 0x800000
|
|
|
800082c: d2ed bcs.n 800080a <__addsf3+0x92>
|
|
|
800082e: fab0 fc80 clz ip, r0
|
|
|
8000832: f1ac 0c08 sub.w ip, ip, #8
|
|
|
8000836: ebb2 020c subs.w r2, r2, ip
|
|
|
800083a: fa00 f00c lsl.w r0, r0, ip
|
|
|
800083e: bfaa itet ge
|
|
|
8000840: eb00 50c2 addge.w r0, r0, r2, lsl #23
|
|
|
8000844: 4252 neglt r2, r2
|
|
|
8000846: 4318 orrge r0, r3
|
|
|
8000848: bfbc itt lt
|
|
|
800084a: 40d0 lsrlt r0, r2
|
|
|
800084c: 4318 orrlt r0, r3
|
|
|
800084e: 4770 bx lr
|
|
|
8000850: f092 0f00 teq r2, #0
|
|
|
8000854: f481 0100 eor.w r1, r1, #8388608 ; 0x800000
|
|
|
8000858: bf06 itte eq
|
|
|
800085a: f480 0000 eoreq.w r0, r0, #8388608 ; 0x800000
|
|
|
800085e: 3201 addeq r2, #1
|
|
|
8000860: 3b01 subne r3, #1
|
|
|
8000862: e7b5 b.n 80007d0 <__addsf3+0x58>
|
|
|
8000864: ea4f 0341 mov.w r3, r1, lsl #1
|
|
|
8000868: ea7f 6c22 mvns.w ip, r2, asr #24
|
|
|
800086c: bf18 it ne
|
|
|
800086e: ea7f 6c23 mvnsne.w ip, r3, asr #24
|
|
|
8000872: d021 beq.n 80008b8 <__addsf3+0x140>
|
|
|
8000874: ea92 0f03 teq r2, r3
|
|
|
8000878: d004 beq.n 8000884 <__addsf3+0x10c>
|
|
|
800087a: f092 0f00 teq r2, #0
|
|
|
800087e: bf08 it eq
|
|
|
8000880: 4608 moveq r0, r1
|
|
|
8000882: 4770 bx lr
|
|
|
8000884: ea90 0f01 teq r0, r1
|
|
|
8000888: bf1c itt ne
|
|
|
800088a: 2000 movne r0, #0
|
|
|
800088c: 4770 bxne lr
|
|
|
800088e: f012 4f7f tst.w r2, #4278190080 ; 0xff000000
|
|
|
8000892: d104 bne.n 800089e <__addsf3+0x126>
|
|
|
8000894: 0040 lsls r0, r0, #1
|
|
|
8000896: bf28 it cs
|
|
|
8000898: f040 4000 orrcs.w r0, r0, #2147483648 ; 0x80000000
|
|
|
800089c: 4770 bx lr
|
|
|
800089e: f112 7200 adds.w r2, r2, #33554432 ; 0x2000000
|
|
|
80008a2: bf3c itt cc
|
|
|
80008a4: f500 0000 addcc.w r0, r0, #8388608 ; 0x800000
|
|
|
80008a8: 4770 bxcc lr
|
|
|
80008aa: f000 4300 and.w r3, r0, #2147483648 ; 0x80000000
|
|
|
80008ae: f043 40fe orr.w r0, r3, #2130706432 ; 0x7f000000
|
|
|
80008b2: f440 0000 orr.w r0, r0, #8388608 ; 0x800000
|
|
|
80008b6: 4770 bx lr
|
|
|
80008b8: ea7f 6222 mvns.w r2, r2, asr #24
|
|
|
80008bc: bf16 itet ne
|
|
|
80008be: 4608 movne r0, r1
|
|
|
80008c0: ea7f 6323 mvnseq.w r3, r3, asr #24
|
|
|
80008c4: 4601 movne r1, r0
|
|
|
80008c6: 0242 lsls r2, r0, #9
|
|
|
80008c8: bf06 itte eq
|
|
|
80008ca: ea5f 2341 movseq.w r3, r1, lsl #9
|
|
|
80008ce: ea90 0f01 teqeq r0, r1
|
|
|
80008d2: f440 0080 orrne.w r0, r0, #4194304 ; 0x400000
|
|
|
80008d6: 4770 bx lr
|
|
|
|
|
|
080008d8 <__aeabi_ui2f>:
|
|
|
80008d8: f04f 0300 mov.w r3, #0
|
|
|
80008dc: e004 b.n 80008e8 <__aeabi_i2f+0x8>
|
|
|
80008de: bf00 nop
|
|
|
|
|
|
080008e0 <__aeabi_i2f>:
|
|
|
80008e0: f010 4300 ands.w r3, r0, #2147483648 ; 0x80000000
|
|
|
80008e4: bf48 it mi
|
|
|
80008e6: 4240 negmi r0, r0
|
|
|
80008e8: ea5f 0c00 movs.w ip, r0
|
|
|
80008ec: bf08 it eq
|
|
|
80008ee: 4770 bxeq lr
|
|
|
80008f0: f043 4396 orr.w r3, r3, #1258291200 ; 0x4b000000
|
|
|
80008f4: 4601 mov r1, r0
|
|
|
80008f6: f04f 0000 mov.w r0, #0
|
|
|
80008fa: e01c b.n 8000936 <__aeabi_l2f+0x2a>
|
|
|
|
|
|
080008fc <__aeabi_ul2f>:
|
|
|
80008fc: ea50 0201 orrs.w r2, r0, r1
|
|
|
8000900: bf08 it eq
|
|
|
8000902: 4770 bxeq lr
|
|
|
8000904: f04f 0300 mov.w r3, #0
|
|
|
8000908: e00a b.n 8000920 <__aeabi_l2f+0x14>
|
|
|
800090a: bf00 nop
|
|
|
|
|
|
0800090c <__aeabi_l2f>:
|
|
|
800090c: ea50 0201 orrs.w r2, r0, r1
|
|
|
8000910: bf08 it eq
|
|
|
8000912: 4770 bxeq lr
|
|
|
8000914: f011 4300 ands.w r3, r1, #2147483648 ; 0x80000000
|
|
|
8000918: d502 bpl.n 8000920 <__aeabi_l2f+0x14>
|
|
|
800091a: 4240 negs r0, r0
|
|
|
800091c: eb61 0141 sbc.w r1, r1, r1, lsl #1
|
|
|
8000920: ea5f 0c01 movs.w ip, r1
|
|
|
8000924: bf02 ittt eq
|
|
|
8000926: 4684 moveq ip, r0
|
|
|
8000928: 4601 moveq r1, r0
|
|
|
800092a: 2000 moveq r0, #0
|
|
|
800092c: f043 43b6 orr.w r3, r3, #1526726656 ; 0x5b000000
|
|
|
8000930: bf08 it eq
|
|
|
8000932: f1a3 5380 subeq.w r3, r3, #268435456 ; 0x10000000
|
|
|
8000936: f5a3 0300 sub.w r3, r3, #8388608 ; 0x800000
|
|
|
800093a: fabc f28c clz r2, ip
|
|
|
800093e: 3a08 subs r2, #8
|
|
|
8000940: eba3 53c2 sub.w r3, r3, r2, lsl #23
|
|
|
8000944: db10 blt.n 8000968 <__aeabi_l2f+0x5c>
|
|
|
8000946: fa01 fc02 lsl.w ip, r1, r2
|
|
|
800094a: 4463 add r3, ip
|
|
|
800094c: fa00 fc02 lsl.w ip, r0, r2
|
|
|
8000950: f1c2 0220 rsb r2, r2, #32
|
|
|
8000954: f1bc 4f00 cmp.w ip, #2147483648 ; 0x80000000
|
|
|
8000958: fa20 f202 lsr.w r2, r0, r2
|
|
|
800095c: eb43 0002 adc.w r0, r3, r2
|
|
|
8000960: bf08 it eq
|
|
|
8000962: f020 0001 biceq.w r0, r0, #1
|
|
|
8000966: 4770 bx lr
|
|
|
8000968: f102 0220 add.w r2, r2, #32
|
|
|
800096c: fa01 fc02 lsl.w ip, r1, r2
|
|
|
8000970: f1c2 0220 rsb r2, r2, #32
|
|
|
8000974: ea50 004c orrs.w r0, r0, ip, lsl #1
|
|
|
8000978: fa21 f202 lsr.w r2, r1, r2
|
|
|
800097c: eb43 0002 adc.w r0, r3, r2
|
|
|
8000980: bf08 it eq
|
|
|
8000982: ea20 70dc biceq.w r0, r0, ip, lsr #31
|
|
|
8000986: 4770 bx lr
|
|
|
|
|
|
08000988 <MX_GPIO_Init>:
|
|
|
* Output
|
|
|
* EVENT_OUT
|
|
|
* EXTI
|
|
|
*/
|
|
|
void MX_GPIO_Init(void)
|
|
|
{
|
|
|
8000988: b580 push {r7, lr}
|
|
|
800098a: b086 sub sp, #24
|
|
|
800098c: af00 add r7, sp, #0
|
|
|
|
|
|
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
|
|
800098e: f107 0308 add.w r3, r7, #8
|
|
|
8000992: 2200 movs r2, #0
|
|
|
8000994: 601a str r2, [r3, #0]
|
|
|
8000996: 605a str r2, [r3, #4]
|
|
|
8000998: 609a str r2, [r3, #8]
|
|
|
800099a: 60da str r2, [r3, #12]
|
|
|
|
|
|
/* GPIO Ports Clock Enable */
|
|
|
__HAL_RCC_GPIOD_CLK_ENABLE();
|
|
|
800099c: 4b1e ldr r3, [pc, #120] ; (8000a18 <MX_GPIO_Init+0x90>)
|
|
|
800099e: 699b ldr r3, [r3, #24]
|
|
|
80009a0: 4a1d ldr r2, [pc, #116] ; (8000a18 <MX_GPIO_Init+0x90>)
|
|
|
80009a2: f043 0320 orr.w r3, r3, #32
|
|
|
80009a6: 6193 str r3, [r2, #24]
|
|
|
80009a8: 4b1b ldr r3, [pc, #108] ; (8000a18 <MX_GPIO_Init+0x90>)
|
|
|
80009aa: 699b ldr r3, [r3, #24]
|
|
|
80009ac: f003 0320 and.w r3, r3, #32
|
|
|
80009b0: 607b str r3, [r7, #4]
|
|
|
80009b2: 687b ldr r3, [r7, #4]
|
|
|
__HAL_RCC_GPIOA_CLK_ENABLE();
|
|
|
80009b4: 4b18 ldr r3, [pc, #96] ; (8000a18 <MX_GPIO_Init+0x90>)
|
|
|
80009b6: 699b ldr r3, [r3, #24]
|
|
|
80009b8: 4a17 ldr r2, [pc, #92] ; (8000a18 <MX_GPIO_Init+0x90>)
|
|
|
80009ba: f043 0304 orr.w r3, r3, #4
|
|
|
80009be: 6193 str r3, [r2, #24]
|
|
|
80009c0: 4b15 ldr r3, [pc, #84] ; (8000a18 <MX_GPIO_Init+0x90>)
|
|
|
80009c2: 699b ldr r3, [r3, #24]
|
|
|
80009c4: f003 0304 and.w r3, r3, #4
|
|
|
80009c8: 603b str r3, [r7, #0]
|
|
|
80009ca: 683b ldr r3, [r7, #0]
|
|
|
|
|
|
/*Configure GPIO pin Output Level */
|
|
|
HAL_GPIO_WritePin(TRIG_GPIO_Port, TRIG_Pin, GPIO_PIN_RESET);
|
|
|
80009cc: 2200 movs r2, #0
|
|
|
80009ce: f44f 6100 mov.w r1, #2048 ; 0x800
|
|
|
80009d2: 4812 ldr r0, [pc, #72] ; (8000a1c <MX_GPIO_Init+0x94>)
|
|
|
80009d4: f000 fd8f bl 80014f6 <HAL_GPIO_WritePin>
|
|
|
|
|
|
/*Configure GPIO pin : PtPin */
|
|
|
GPIO_InitStruct.Pin = ECHO_Pin;
|
|
|
80009d8: f44f 6380 mov.w r3, #1024 ; 0x400
|
|
|
80009dc: 60bb str r3, [r7, #8]
|
|
|
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
|
|
|
80009de: 2300 movs r3, #0
|
|
|
80009e0: 60fb str r3, [r7, #12]
|
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
|
80009e2: 2300 movs r3, #0
|
|
|
80009e4: 613b str r3, [r7, #16]
|
|
|
HAL_GPIO_Init(ECHO_GPIO_Port, &GPIO_InitStruct);
|
|
|
80009e6: f107 0308 add.w r3, r7, #8
|
|
|
80009ea: 4619 mov r1, r3
|
|
|
80009ec: 480b ldr r0, [pc, #44] ; (8000a1c <MX_GPIO_Init+0x94>)
|
|
|
80009ee: f000 fbe7 bl 80011c0 <HAL_GPIO_Init>
|
|
|
|
|
|
/*Configure GPIO pin : PtPin */
|
|
|
GPIO_InitStruct.Pin = TRIG_Pin;
|
|
|
80009f2: f44f 6300 mov.w r3, #2048 ; 0x800
|
|
|
80009f6: 60bb str r3, [r7, #8]
|
|
|
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
|
|
|
80009f8: 2301 movs r3, #1
|
|
|
80009fa: 60fb str r3, [r7, #12]
|
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
|
80009fc: 2300 movs r3, #0
|
|
|
80009fe: 613b str r3, [r7, #16]
|
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
|
|
8000a00: 2302 movs r3, #2
|
|
|
8000a02: 617b str r3, [r7, #20]
|
|
|
HAL_GPIO_Init(TRIG_GPIO_Port, &GPIO_InitStruct);
|
|
|
8000a04: f107 0308 add.w r3, r7, #8
|
|
|
8000a08: 4619 mov r1, r3
|
|
|
8000a0a: 4804 ldr r0, [pc, #16] ; (8000a1c <MX_GPIO_Init+0x94>)
|
|
|
8000a0c: f000 fbd8 bl 80011c0 <HAL_GPIO_Init>
|
|
|
|
|
|
}
|
|
|
8000a10: bf00 nop
|
|
|
8000a12: 3718 adds r7, #24
|
|
|
8000a14: 46bd mov sp, r7
|
|
|
8000a16: bd80 pop {r7, pc}
|
|
|
8000a18: 40021000 .word 0x40021000
|
|
|
8000a1c: 40010800 .word 0x40010800
|
|
|
|
|
|
08000a20 <main>:
|
|
|
|
|
|
/**
|
|
|
* @brief The application entry point.
|
|
|
* @retval int
|
|
|
*/
|
|
|
int main(void) {
|
|
|
8000a20: b580 push {r7, lr}
|
|
|
8000a22: b08e sub sp, #56 ; 0x38
|
|
|
8000a24: af00 add r7, sp, #0
|
|
|
/* USER CODE END 1 */
|
|
|
|
|
|
/* MCU Configuration--------------------------------------------------------*/
|
|
|
|
|
|
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
|
|
|
HAL_Init();
|
|
|
8000a26: f000 fa61 bl 8000eec <HAL_Init>
|
|
|
/* USER CODE BEGIN Init */
|
|
|
|
|
|
/* USER CODE END Init */
|
|
|
|
|
|
/* Configure the system clock */
|
|
|
SystemClock_Config();
|
|
|
8000a2a: f000 f875 bl 8000b18 <SystemClock_Config>
|
|
|
/* USER CODE BEGIN SysInit */
|
|
|
|
|
|
/* USER CODE END SysInit */
|
|
|
|
|
|
/* Initialize all configured peripherals */
|
|
|
MX_GPIO_Init();
|
|
|
8000a2e: f7ff ffab bl 8000988 <MX_GPIO_Init>
|
|
|
MX_TIM1_Init();
|
|
|
8000a32: f000 f951 bl 8000cd8 <MX_TIM1_Init>
|
|
|
MX_USART2_UART_Init();
|
|
|
8000a36: f000 f9bf bl 8000db8 <MX_USART2_UART_Init>
|
|
|
|
|
|
/* USER CODE END 2 */
|
|
|
|
|
|
/* Infinite loop */
|
|
|
/* USER CODE BEGIN WHILE */
|
|
|
char send_buf[50] = { 0 };
|
|
|
8000a3a: 2300 movs r3, #0
|
|
|
8000a3c: 607b str r3, [r7, #4]
|
|
|
8000a3e: f107 0308 add.w r3, r7, #8
|
|
|
8000a42: 222e movs r2, #46 ; 0x2e
|
|
|
8000a44: 2100 movs r1, #0
|
|
|
8000a46: 4618 mov r0, r3
|
|
|
8000a48: f001 fe44 bl 80026d4 <memset>
|
|
|
while (1) {
|
|
|
HAL_Delay(500);
|
|
|
8000a4c: f44f 70fa mov.w r0, #500 ; 0x1f4
|
|
|
8000a50: f000 faae bl 8000fb0 <HAL_Delay>
|
|
|
//触发模块输出
|
|
|
HAL_GPIO_WritePin(TRIG_GPIO_Port, TRIG_Pin, 1);
|
|
|
8000a54: 2201 movs r2, #1
|
|
|
8000a56: f44f 6100 mov.w r1, #2048 ; 0x800
|
|
|
8000a5a: 482b ldr r0, [pc, #172] ; (8000b08 <main+0xe8>)
|
|
|
8000a5c: f000 fd4b bl 80014f6 <HAL_GPIO_WritePin>
|
|
|
HAL_Delay(5);
|
|
|
8000a60: 2005 movs r0, #5
|
|
|
8000a62: f000 faa5 bl 8000fb0 <HAL_Delay>
|
|
|
HAL_GPIO_WritePin(TRIG_GPIO_Port, TRIG_Pin, 0);
|
|
|
8000a66: 2200 movs r2, #0
|
|
|
8000a68: f44f 6100 mov.w r1, #2048 ; 0x800
|
|
|
8000a6c: 4826 ldr r0, [pc, #152] ; (8000b08 <main+0xe8>)
|
|
|
8000a6e: f000 fd42 bl 80014f6 <HAL_GPIO_WritePin>
|
|
|
//清零TIM1的计<E79A84>??
|
|
|
htim1.Instance->CNT = 0;
|
|
|
8000a72: 4b26 ldr r3, [pc, #152] ; (8000b0c <main+0xec>)
|
|
|
8000a74: 681b ldr r3, [r3, #0]
|
|
|
8000a76: 2200 movs r2, #0
|
|
|
8000a78: 625a str r2, [r3, #36] ; 0x24
|
|
|
//等待echo引脚拉高
|
|
|
while (!HAL_GPIO_ReadPin(ECHO_GPIO_Port, ECHO_Pin)) {
|
|
|
8000a7a: bf00 nop
|
|
|
8000a7c: f44f 6180 mov.w r1, #1024 ; 0x400
|
|
|
8000a80: 4821 ldr r0, [pc, #132] ; (8000b08 <main+0xe8>)
|
|
|
8000a82: f000 fd21 bl 80014c8 <HAL_GPIO_ReadPin>
|
|
|
8000a86: 4603 mov r3, r0
|
|
|
8000a88: 2b00 cmp r3, #0
|
|
|
8000a8a: d0f7 beq.n 8000a7c <main+0x5c>
|
|
|
}
|
|
|
//echo引脚拉高时，<E697B6>??始计<E5A78B>??
|
|
|
HAL_TIM_Base_Start(&htim1);
|
|
|
8000a8c: 481f ldr r0, [pc, #124] ; (8000b0c <main+0xec>)
|
|
|
8000a8e: f001 f9b5 bl 8001dfc <HAL_TIM_Base_Start>
|
|
|
//等待echo引脚拉低
|
|
|
while (HAL_GPIO_ReadPin(ECHO_GPIO_Port, ECHO_Pin)) {
|
|
|
8000a92: bf00 nop
|
|
|
8000a94: f44f 6180 mov.w r1, #1024 ; 0x400
|
|
|
8000a98: 481b ldr r0, [pc, #108] ; (8000b08 <main+0xe8>)
|
|
|
8000a9a: f000 fd15 bl 80014c8 <HAL_GPIO_ReadPin>
|
|
|
8000a9e: 4603 mov r3, r0
|
|
|
8000aa0: 2b00 cmp r3, #0
|
|
|
8000aa2: d1f7 bne.n 8000a94 <main+0x74>
|
|
|
}
|
|
|
//echo拉低，停止计<E6ADA2>??
|
|
|
HAL_TIM_Base_Stop(&htim1);
|
|
|
8000aa4: 4819 ldr r0, [pc, #100] ; (8000b0c <main+0xec>)
|
|
|
8000aa6: f001 f9f3 bl 8001e90 <HAL_TIM_Base_Stop>
|
|
|
//计算、输出距<E587BA>??
|
|
|
//定时器每10us计数<E8AEA1>??次，因此 距离=计数*3.4/2（毫米）
|
|
|
sprintf(send_buf, "%u millimeter\r\n",
|
|
|
(uint16_t) ((float) htim1.Instance->CNT * 1.7));
|
|
|
8000aaa: 4b18 ldr r3, [pc, #96] ; (8000b0c <main+0xec>)
|
|
|
8000aac: 681b ldr r3, [r3, #0]
|
|
|
8000aae: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
|
8000ab0: 4618 mov r0, r3
|
|
|
8000ab2: f7ff ff11 bl 80008d8 <__aeabi_ui2f>
|
|
|
8000ab6: 4603 mov r3, r0
|
|
|
8000ab8: 4618 mov r0, r3
|
|
|
8000aba: f7ff fddf bl 800067c <__aeabi_f2d>
|
|
|
8000abe: a310 add r3, pc, #64 ; (adr r3, 8000b00 <main+0xe0>)
|
|
|
8000ac0: e9d3 2300 ldrd r2, r3, [r3]
|
|
|
8000ac4: f7ff fb4c bl 8000160 <__aeabi_dmul>
|
|
|
8000ac8: 4602 mov r2, r0
|
|
|
8000aca: 460b mov r3, r1
|
|
|
8000acc: 4610 mov r0, r2
|
|
|
8000ace: 4619 mov r1, r3
|
|
|
8000ad0: f7ff fe2c bl 800072c <__aeabi_d2uiz>
|
|
|
8000ad4: 4603 mov r3, r0
|
|
|
8000ad6: b29b uxth r3, r3
|
|
|
sprintf(send_buf, "%u millimeter\r\n",
|
|
|
8000ad8: 461a mov r2, r3
|
|
|
8000ada: 1d3b adds r3, r7, #4
|
|
|
8000adc: 490c ldr r1, [pc, #48] ; (8000b10 <main+0xf0>)
|
|
|
8000ade: 4618 mov r0, r3
|
|
|
8000ae0: f001 fe00 bl 80026e4 <siprintf>
|
|
|
HAL_UART_Transmit(&huart2, (uint8_t*) send_buf, strlen(send_buf), 10);
|
|
|
8000ae4: 1d3b adds r3, r7, #4
|
|
|
8000ae6: 4618 mov r0, r3
|
|
|
8000ae8: f7ff fb32 bl 8000150 <strlen>
|
|
|
8000aec: 4603 mov r3, r0
|
|
|
8000aee: b29a uxth r2, r3
|
|
|
8000af0: 1d39 adds r1, r7, #4
|
|
|
8000af2: 230a movs r3, #10
|
|
|
8000af4: 4807 ldr r0, [pc, #28] ; (8000b14 <main+0xf4>)
|
|
|
8000af6: f001 fc58 bl 80023aa <HAL_UART_Transmit>
|
|
|
HAL_Delay(500);
|
|
|
8000afa: e7a7 b.n 8000a4c <main+0x2c>
|
|
|
8000afc: f3af 8000 nop.w
|
|
|
8000b00: 33333333 .word 0x33333333
|
|
|
8000b04: 3ffb3333 .word 0x3ffb3333
|
|
|
8000b08: 40010800 .word 0x40010800
|
|
|
8000b0c: 20000090 .word 0x20000090
|
|
|
8000b10: 08002ff0 .word 0x08002ff0
|
|
|
8000b14: 200000d8 .word 0x200000d8
|
|
|
|
|
|
08000b18 <SystemClock_Config>:
|
|
|
|
|
|
/**
|
|
|
* @brief System Clock Configuration
|
|
|
* @retval None
|
|
|
*/
|
|
|
void SystemClock_Config(void) {
|
|
|
8000b18: b580 push {r7, lr}
|
|
|
8000b1a: b090 sub sp, #64 ; 0x40
|
|
|
8000b1c: af00 add r7, sp, #0
|
|
|
RCC_OscInitTypeDef RCC_OscInitStruct = { 0 };
|
|
|
8000b1e: f107 0318 add.w r3, r7, #24
|
|
|
8000b22: 2228 movs r2, #40 ; 0x28
|
|
|
8000b24: 2100 movs r1, #0
|
|
|
8000b26: 4618 mov r0, r3
|
|
|
8000b28: f001 fdd4 bl 80026d4 <memset>
|
|
|
RCC_ClkInitTypeDef RCC_ClkInitStruct = { 0 };
|
|
|
8000b2c: 1d3b adds r3, r7, #4
|
|
|
8000b2e: 2200 movs r2, #0
|
|
|
8000b30: 601a str r2, [r3, #0]
|
|
|
8000b32: 605a str r2, [r3, #4]
|
|
|
8000b34: 609a str r2, [r3, #8]
|
|
|
8000b36: 60da str r2, [r3, #12]
|
|
|
8000b38: 611a str r2, [r3, #16]
|
|
|
|
|
|
/** Initializes the RCC Oscillators according to the specified parameters
|
|
|
* in the RCC_OscInitTypeDef structure.
|
|
|
*/
|
|
|
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
|
|
|
8000b3a: 2301 movs r3, #1
|
|
|
8000b3c: 61bb str r3, [r7, #24]
|
|
|
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
|
|
|
8000b3e: f44f 3380 mov.w r3, #65536 ; 0x10000
|
|
|
8000b42: 61fb str r3, [r7, #28]
|
|
|
RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV1;
|
|
|
8000b44: 2300 movs r3, #0
|
|
|
8000b46: 623b str r3, [r7, #32]
|
|
|
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
|
|
|
8000b48: 2301 movs r3, #1
|
|
|
8000b4a: 62bb str r3, [r7, #40] ; 0x28
|
|
|
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
|
|
|
8000b4c: 2302 movs r3, #2
|
|
|
8000b4e: 637b str r3, [r7, #52] ; 0x34
|
|
|
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
|
|
|
8000b50: f44f 3380 mov.w r3, #65536 ; 0x10000
|
|
|
8000b54: 63bb str r3, [r7, #56] ; 0x38
|
|
|
RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9;
|
|
|
8000b56: f44f 13e0 mov.w r3, #1835008 ; 0x1c0000
|
|
|
8000b5a: 63fb str r3, [r7, #60] ; 0x3c
|
|
|
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
|
|
|
8000b5c: f107 0318 add.w r3, r7, #24
|
|
|
8000b60: 4618 mov r0, r3
|
|
|
8000b62: f000 fce1 bl 8001528 <HAL_RCC_OscConfig>
|
|
|
8000b66: 4603 mov r3, r0
|
|
|
8000b68: 2b00 cmp r3, #0
|
|
|
8000b6a: d001 beq.n 8000b70 <SystemClock_Config+0x58>
|
|
|
Error_Handler();
|
|
|
8000b6c: f000 f819 bl 8000ba2 <Error_Handler>
|
|
|
}
|
|
|
|
|
|
/** Initializes the CPU, AHB and APB buses clocks
|
|
|
*/
|
|
|
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
|
|
|
8000b70: 230f movs r3, #15
|
|
|
8000b72: 607b str r3, [r7, #4]
|
|
|
| RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
|
|
|
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
|
|
|
8000b74: 2302 movs r3, #2
|
|
|
8000b76: 60bb str r3, [r7, #8]
|
|
|
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
|
|
|
8000b78: 2300 movs r3, #0
|
|
|
8000b7a: 60fb str r3, [r7, #12]
|
|
|
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
|
|
|
8000b7c: f44f 6380 mov.w r3, #1024 ; 0x400
|
|
|
8000b80: 613b str r3, [r7, #16]
|
|
|
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
|
|
|
8000b82: 2300 movs r3, #0
|
|
|
8000b84: 617b str r3, [r7, #20]
|
|
|
|
|
|
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) {
|
|
|
8000b86: 1d3b adds r3, r7, #4
|
|
|
8000b88: 2102 movs r1, #2
|
|
|
8000b8a: 4618 mov r0, r3
|
|
|
8000b8c: f000 ff4e bl 8001a2c <HAL_RCC_ClockConfig>
|
|
|
8000b90: 4603 mov r3, r0
|
|
|
8000b92: 2b00 cmp r3, #0
|
|
|
8000b94: d001 beq.n 8000b9a <SystemClock_Config+0x82>
|
|
|
Error_Handler();
|
|
|
8000b96: f000 f804 bl 8000ba2 <Error_Handler>
|
|
|
}
|
|
|
}
|
|
|
8000b9a: bf00 nop
|
|
|
8000b9c: 3740 adds r7, #64 ; 0x40
|
|
|
8000b9e: 46bd mov sp, r7
|
|
|
8000ba0: bd80 pop {r7, pc}
|
|
|
|
|
|
08000ba2 <Error_Handler>:
|
|
|
|
|
|
/**
|
|
|
* @brief This function is executed in case of error occurrence.
|
|
|
* @retval None
|
|
|
*/
|
|
|
void Error_Handler(void) {
|
|
|
8000ba2: b480 push {r7}
|
|
|
8000ba4: af00 add r7, sp, #0
|
|
|
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
|
|
|
Can only be executed in Privileged modes.
|
|
|
*/
|
|
|
__STATIC_FORCEINLINE void __disable_irq(void)
|
|
|
{
|
|
|
__ASM volatile ("cpsid i" : : : "memory");
|
|
|
8000ba6: b672 cpsid i
|
|
|
}
|
|
|
8000ba8: bf00 nop
|
|
|
/* USER CODE BEGIN Error_Handler_Debug */
|
|
|
/* User can add his own implementation to report the HAL error return state */
|
|
|
__disable_irq();
|
|
|
while (1) {
|
|
|
8000baa: e7fe b.n 8000baa <Error_Handler+0x8>
|
|
|
|
|
|
08000bac <HAL_MspInit>:
|
|
|
/* USER CODE END 0 */
|
|
|
/**
|
|
|
* Initializes the Global MSP.
|
|
|
*/
|
|
|
void HAL_MspInit(void)
|
|
|
{
|
|
|
8000bac: b480 push {r7}
|
|
|
8000bae: b085 sub sp, #20
|
|
|
8000bb0: af00 add r7, sp, #0
|
|
|
/* USER CODE BEGIN MspInit 0 */
|
|
|
|
|
|
/* USER CODE END MspInit 0 */
|
|
|
|
|
|
__HAL_RCC_AFIO_CLK_ENABLE();
|
|
|
8000bb2: 4b15 ldr r3, [pc, #84] ; (8000c08 <HAL_MspInit+0x5c>)
|
|
|
8000bb4: 699b ldr r3, [r3, #24]
|
|
|
8000bb6: 4a14 ldr r2, [pc, #80] ; (8000c08 <HAL_MspInit+0x5c>)
|
|
|
8000bb8: f043 0301 orr.w r3, r3, #1
|
|
|
8000bbc: 6193 str r3, [r2, #24]
|
|
|
8000bbe: 4b12 ldr r3, [pc, #72] ; (8000c08 <HAL_MspInit+0x5c>)
|
|
|
8000bc0: 699b ldr r3, [r3, #24]
|
|
|
8000bc2: f003 0301 and.w r3, r3, #1
|
|
|
8000bc6: 60bb str r3, [r7, #8]
|
|
|
8000bc8: 68bb ldr r3, [r7, #8]
|
|
|
__HAL_RCC_PWR_CLK_ENABLE();
|
|
|
8000bca: 4b0f ldr r3, [pc, #60] ; (8000c08 <HAL_MspInit+0x5c>)
|
|
|
8000bcc: 69db ldr r3, [r3, #28]
|
|
|
8000bce: 4a0e ldr r2, [pc, #56] ; (8000c08 <HAL_MspInit+0x5c>)
|
|
|
8000bd0: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
|
|
|
8000bd4: 61d3 str r3, [r2, #28]
|
|
|
8000bd6: 4b0c ldr r3, [pc, #48] ; (8000c08 <HAL_MspInit+0x5c>)
|
|
|
8000bd8: 69db ldr r3, [r3, #28]
|
|
|
8000bda: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
|
|
|
8000bde: 607b str r3, [r7, #4]
|
|
|
8000be0: 687b ldr r3, [r7, #4]
|
|
|
|
|
|
/* System interrupt init*/
|
|
|
|
|
|
/** NOJTAG: JTAG-DP Disabled and SW-DP Enabled
|
|
|
*/
|
|
|
__HAL_AFIO_REMAP_SWJ_NOJTAG();
|
|
|
8000be2: 4b0a ldr r3, [pc, #40] ; (8000c0c <HAL_MspInit+0x60>)
|
|
|
8000be4: 685b ldr r3, [r3, #4]
|
|
|
8000be6: 60fb str r3, [r7, #12]
|
|
|
8000be8: 68fb ldr r3, [r7, #12]
|
|
|
8000bea: f023 63e0 bic.w r3, r3, #117440512 ; 0x7000000
|
|
|
8000bee: 60fb str r3, [r7, #12]
|
|
|
8000bf0: 68fb ldr r3, [r7, #12]
|
|
|
8000bf2: f043 7300 orr.w r3, r3, #33554432 ; 0x2000000
|
|
|
8000bf6: 60fb str r3, [r7, #12]
|
|
|
8000bf8: 4a04 ldr r2, [pc, #16] ; (8000c0c <HAL_MspInit+0x60>)
|
|
|
8000bfa: 68fb ldr r3, [r7, #12]
|
|
|
8000bfc: 6053 str r3, [r2, #4]
|
|
|
|
|
|
/* USER CODE BEGIN MspInit 1 */
|
|
|
|
|
|
/* USER CODE END MspInit 1 */
|
|
|
}
|
|
|
8000bfe: bf00 nop
|
|
|
8000c00: 3714 adds r7, #20
|
|
|
8000c02: 46bd mov sp, r7
|
|
|
8000c04: bc80 pop {r7}
|
|
|
8000c06: 4770 bx lr
|
|
|
8000c08: 40021000 .word 0x40021000
|
|
|
8000c0c: 40010000 .word 0x40010000
|
|
|
|
|
|
08000c10 <NMI_Handler>:
|
|
|
/******************************************************************************/
|
|
|
/**
|
|
|
* @brief This function handles Non maskable interrupt.
|
|
|
*/
|
|
|
void NMI_Handler(void)
|
|
|
{
|
|
|
8000c10: b480 push {r7}
|
|
|
8000c12: af00 add r7, sp, #0
|
|
|
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
|
|
|
|
|
|
/* USER CODE END NonMaskableInt_IRQn 0 */
|
|
|
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
|
|
|
while (1)
|
|
|
8000c14: e7fe b.n 8000c14 <NMI_Handler+0x4>
|
|
|
|
|
|
08000c16 <HardFault_Handler>:
|
|
|
|
|
|
/**
|
|
|
* @brief This function handles Hard fault interrupt.
|
|
|
*/
|
|
|
void HardFault_Handler(void)
|
|
|
{
|
|
|
8000c16: b480 push {r7}
|
|
|
8000c18: af00 add r7, sp, #0
|
|
|
/* USER CODE BEGIN HardFault_IRQn 0 */
|
|
|
|
|
|
/* USER CODE END HardFault_IRQn 0 */
|
|
|
while (1)
|
|
|
8000c1a: e7fe b.n 8000c1a <HardFault_Handler+0x4>
|
|
|
|
|
|
08000c1c <MemManage_Handler>:
|
|
|
|
|
|
/**
|
|
|
* @brief This function handles Memory management fault.
|
|
|
*/
|
|
|
void MemManage_Handler(void)
|
|
|
{
|
|
|
8000c1c: b480 push {r7}
|
|
|
8000c1e: af00 add r7, sp, #0
|
|
|
/* USER CODE BEGIN MemoryManagement_IRQn 0 */
|
|
|
|
|
|
/* USER CODE END MemoryManagement_IRQn 0 */
|
|
|
while (1)
|
|
|
8000c20: e7fe b.n 8000c20 <MemManage_Handler+0x4>
|
|
|
|
|
|
08000c22 <BusFault_Handler>:
|
|
|
|
|
|
/**
|
|
|
* @brief This function handles Prefetch fault, memory access fault.
|
|
|
*/
|
|
|
void BusFault_Handler(void)
|
|
|
{
|
|
|
8000c22: b480 push {r7}
|
|
|
8000c24: af00 add r7, sp, #0
|
|
|
/* USER CODE BEGIN BusFault_IRQn 0 */
|
|
|
|
|
|
/* USER CODE END BusFault_IRQn 0 */
|
|
|
while (1)
|
|
|
8000c26: e7fe b.n 8000c26 <BusFault_Handler+0x4>
|
|
|
|
|
|
08000c28 <UsageFault_Handler>:
|
|
|
|
|
|
/**
|
|
|
* @brief This function handles Undefined instruction or illegal state.
|
|
|
*/
|
|
|
void UsageFault_Handler(void)
|
|
|
{
|
|
|
8000c28: b480 push {r7}
|
|
|
8000c2a: af00 add r7, sp, #0
|
|
|
/* USER CODE BEGIN UsageFault_IRQn 0 */
|
|
|
|
|
|
/* USER CODE END UsageFault_IRQn 0 */
|
|
|
while (1)
|
|
|
8000c2c: e7fe b.n 8000c2c <UsageFault_Handler+0x4>
|
|
|
|
|
|
08000c2e <SVC_Handler>:
|
|
|
|
|
|
/**
|
|
|
* @brief This function handles System service call via SWI instruction.
|
|
|
*/
|
|
|
void SVC_Handler(void)
|
|
|
{
|
|
|
8000c2e: b480 push {r7}
|
|
|
8000c30: af00 add r7, sp, #0
|
|
|
|
|
|
/* USER CODE END SVCall_IRQn 0 */
|
|
|
/* USER CODE BEGIN SVCall_IRQn 1 */
|
|
|
|
|
|
/* USER CODE END SVCall_IRQn 1 */
|
|
|
}
|
|
|
8000c32: bf00 nop
|
|
|
8000c34: 46bd mov sp, r7
|
|
|
8000c36: bc80 pop {r7}
|
|
|
8000c38: 4770 bx lr
|
|
|
|
|
|
08000c3a <DebugMon_Handler>:
|
|
|
|
|
|
/**
|
|
|
* @brief This function handles Debug monitor.
|
|
|
*/
|
|
|
void DebugMon_Handler(void)
|
|
|
{
|
|
|
8000c3a: b480 push {r7}
|
|
|
8000c3c: af00 add r7, sp, #0
|
|
|
|
|
|
/* USER CODE END DebugMonitor_IRQn 0 */
|
|
|
/* USER CODE BEGIN DebugMonitor_IRQn 1 */
|
|
|
|
|
|
/* USER CODE END DebugMonitor_IRQn 1 */
|
|
|
}
|
|
|
8000c3e: bf00 nop
|
|
|
8000c40: 46bd mov sp, r7
|
|
|
8000c42: bc80 pop {r7}
|
|
|
8000c44: 4770 bx lr
|
|
|
|
|
|
08000c46 <PendSV_Handler>:
|
|
|
|
|
|
/**
|
|
|
* @brief This function handles Pendable request for system service.
|
|
|
*/
|
|
|
void PendSV_Handler(void)
|
|
|
{
|
|
|
8000c46: b480 push {r7}
|
|
|
8000c48: af00 add r7, sp, #0
|
|
|
|
|
|
/* USER CODE END PendSV_IRQn 0 */
|
|
|
/* USER CODE BEGIN PendSV_IRQn 1 */
|
|
|
|
|
|
/* USER CODE END PendSV_IRQn 1 */
|
|
|
}
|
|
|
8000c4a: bf00 nop
|
|
|
8000c4c: 46bd mov sp, r7
|
|
|
8000c4e: bc80 pop {r7}
|
|
|
8000c50: 4770 bx lr
|
|
|
|
|
|
08000c52 <SysTick_Handler>:
|
|
|
|
|
|
/**
|
|
|
* @brief This function handles System tick timer.
|
|
|
*/
|
|
|
void SysTick_Handler(void)
|
|
|
{
|
|
|
8000c52: b580 push {r7, lr}
|
|
|
8000c54: af00 add r7, sp, #0
|
|
|
/* USER CODE BEGIN SysTick_IRQn 0 */
|
|
|
|
|
|
/* USER CODE END SysTick_IRQn 0 */
|
|
|
HAL_IncTick();
|
|
|
8000c56: f000 f98f bl 8000f78 <HAL_IncTick>
|
|
|
/* USER CODE BEGIN SysTick_IRQn 1 */
|
|
|
|
|
|
/* USER CODE END SysTick_IRQn 1 */
|
|
|
}
|
|
|
8000c5a: bf00 nop
|
|
|
8000c5c: bd80 pop {r7, pc}
|
|
|
...
|
|
|
|
|
|
08000c60 <_sbrk>:
|
|
|
*
|
|
|
* @param incr Memory size
|
|
|
* @return Pointer to allocated memory
|
|
|
*/
|
|
|
void *_sbrk(ptrdiff_t incr)
|
|
|
{
|
|
|
8000c60: b580 push {r7, lr}
|
|
|
8000c62: b086 sub sp, #24
|
|
|
8000c64: af00 add r7, sp, #0
|
|
|
8000c66: 6078 str r0, [r7, #4]
|
|
|
extern uint8_t _end; /* Symbol defined in the linker script */
|
|
|
extern uint8_t _estack; /* Symbol defined in the linker script */
|
|
|
extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */
|
|
|
const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size;
|
|
|
8000c68: 4a14 ldr r2, [pc, #80] ; (8000cbc <_sbrk+0x5c>)
|
|
|
8000c6a: 4b15 ldr r3, [pc, #84] ; (8000cc0 <_sbrk+0x60>)
|
|
|
8000c6c: 1ad3 subs r3, r2, r3
|
|
|
8000c6e: 617b str r3, [r7, #20]
|
|
|
const uint8_t *max_heap = (uint8_t *)stack_limit;
|
|
|
8000c70: 697b ldr r3, [r7, #20]
|
|
|
8000c72: 613b str r3, [r7, #16]
|
|
|
uint8_t *prev_heap_end;
|
|
|
|
|
|
/* Initialize heap end at first call */
|
|
|
if (NULL == __sbrk_heap_end)
|
|
|
8000c74: 4b13 ldr r3, [pc, #76] ; (8000cc4 <_sbrk+0x64>)
|
|
|
8000c76: 681b ldr r3, [r3, #0]
|
|
|
8000c78: 2b00 cmp r3, #0
|
|
|
8000c7a: d102 bne.n 8000c82 <_sbrk+0x22>
|
|
|
{
|
|
|
__sbrk_heap_end = &_end;
|
|
|
8000c7c: 4b11 ldr r3, [pc, #68] ; (8000cc4 <_sbrk+0x64>)
|
|
|
8000c7e: 4a12 ldr r2, [pc, #72] ; (8000cc8 <_sbrk+0x68>)
|
|
|
8000c80: 601a str r2, [r3, #0]
|
|
|
}
|
|
|
|
|
|
/* Protect heap from growing into the reserved MSP stack */
|
|
|
if (__sbrk_heap_end + incr > max_heap)
|
|
|
8000c82: 4b10 ldr r3, [pc, #64] ; (8000cc4 <_sbrk+0x64>)
|
|
|
8000c84: 681a ldr r2, [r3, #0]
|
|
|
8000c86: 687b ldr r3, [r7, #4]
|
|
|
8000c88: 4413 add r3, r2
|
|
|
8000c8a: 693a ldr r2, [r7, #16]
|
|
|
8000c8c: 429a cmp r2, r3
|
|
|
8000c8e: d207 bcs.n 8000ca0 <_sbrk+0x40>
|
|
|
{
|
|
|
errno = ENOMEM;
|
|
|
8000c90: f001 fcf6 bl 8002680 <__errno>
|
|
|
8000c94: 4603 mov r3, r0
|
|
|
8000c96: 220c movs r2, #12
|
|
|
8000c98: 601a str r2, [r3, #0]
|
|
|
return (void *)-1;
|
|
|
8000c9a: f04f 33ff mov.w r3, #4294967295
|
|
|
8000c9e: e009 b.n 8000cb4 <_sbrk+0x54>
|
|
|
}
|
|
|
|
|
|
prev_heap_end = __sbrk_heap_end;
|
|
|
8000ca0: 4b08 ldr r3, [pc, #32] ; (8000cc4 <_sbrk+0x64>)
|
|
|
8000ca2: 681b ldr r3, [r3, #0]
|
|
|
8000ca4: 60fb str r3, [r7, #12]
|
|
|
__sbrk_heap_end += incr;
|
|
|
8000ca6: 4b07 ldr r3, [pc, #28] ; (8000cc4 <_sbrk+0x64>)
|
|
|
8000ca8: 681a ldr r2, [r3, #0]
|
|
|
8000caa: 687b ldr r3, [r7, #4]
|
|
|
8000cac: 4413 add r3, r2
|
|
|
8000cae: 4a05 ldr r2, [pc, #20] ; (8000cc4 <_sbrk+0x64>)
|
|
|
8000cb0: 6013 str r3, [r2, #0]
|
|
|
|
|
|
return (void *)prev_heap_end;
|
|
|
8000cb2: 68fb ldr r3, [r7, #12]
|
|
|
}
|
|
|
8000cb4: 4618 mov r0, r3
|
|
|
8000cb6: 3718 adds r7, #24
|
|
|
8000cb8: 46bd mov sp, r7
|
|
|
8000cba: bd80 pop {r7, pc}
|
|
|
8000cbc: 20005000 .word 0x20005000
|
|
|
8000cc0: 00000400 .word 0x00000400
|
|
|
8000cc4: 2000008c .word 0x2000008c
|
|
|
8000cc8: 20000130 .word 0x20000130
|
|
|
|
|
|
08000ccc <SystemInit>:
|
|
|
* @note This function should be used only after reset.
|
|
|
* @param None
|
|
|
* @retval None
|
|
|
*/
|
|
|
void SystemInit (void)
|
|
|
{
|
|
|
8000ccc: b480 push {r7}
|
|
|
8000cce: af00 add r7, sp, #0
|
|
|
|
|
|
/* Configure the Vector Table location -------------------------------------*/
|
|
|
#if defined(USER_VECT_TAB_ADDRESS)
|
|
|
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
|
|
|
#endif /* USER_VECT_TAB_ADDRESS */
|
|
|
}
|
|
|
8000cd0: bf00 nop
|
|
|
8000cd2: 46bd mov sp, r7
|
|
|
8000cd4: bc80 pop {r7}
|
|
|
8000cd6: 4770 bx lr
|
|
|
|
|
|
08000cd8 <MX_TIM1_Init>:
|
|
|
|
|
|
TIM_HandleTypeDef htim1;
|
|
|
|
|
|
/* TIM1 init function */
|
|
|
void MX_TIM1_Init(void)
|
|
|
{
|
|
|
8000cd8: b580 push {r7, lr}
|
|
|
8000cda: b086 sub sp, #24
|
|
|
8000cdc: af00 add r7, sp, #0
|
|
|
|
|
|
/* USER CODE BEGIN TIM1_Init 0 */
|
|
|
|
|
|
/* USER CODE END TIM1_Init 0 */
|
|
|
|
|
|
TIM_ClockConfigTypeDef sClockSourceConfig = {0};
|
|
|
8000cde: f107 0308 add.w r3, r7, #8
|
|
|
8000ce2: 2200 movs r2, #0
|
|
|
8000ce4: 601a str r2, [r3, #0]
|
|
|
8000ce6: 605a str r2, [r3, #4]
|
|
|
8000ce8: 609a str r2, [r3, #8]
|
|
|
8000cea: 60da str r2, [r3, #12]
|
|
|
TIM_MasterConfigTypeDef sMasterConfig = {0};
|
|
|
8000cec: 463b mov r3, r7
|
|
|
8000cee: 2200 movs r2, #0
|
|
|
8000cf0: 601a str r2, [r3, #0]
|
|
|
8000cf2: 605a str r2, [r3, #4]
|
|
|
|
|
|
/* USER CODE BEGIN TIM1_Init 1 */
|
|
|
|
|
|
/* USER CODE END TIM1_Init 1 */
|
|
|
htim1.Instance = TIM1;
|
|
|
8000cf4: 4b1f ldr r3, [pc, #124] ; (8000d74 <MX_TIM1_Init+0x9c>)
|
|
|
8000cf6: 4a20 ldr r2, [pc, #128] ; (8000d78 <MX_TIM1_Init+0xa0>)
|
|
|
8000cf8: 601a str r2, [r3, #0]
|
|
|
htim1.Init.Prescaler = 720-1;
|
|
|
8000cfa: 4b1e ldr r3, [pc, #120] ; (8000d74 <MX_TIM1_Init+0x9c>)
|
|
|
8000cfc: f240 22cf movw r2, #719 ; 0x2cf
|
|
|
8000d00: 605a str r2, [r3, #4]
|
|
|
htim1.Init.CounterMode = TIM_COUNTERMODE_UP;
|
|
|
8000d02: 4b1c ldr r3, [pc, #112] ; (8000d74 <MX_TIM1_Init+0x9c>)
|
|
|
8000d04: 2200 movs r2, #0
|
|
|
8000d06: 609a str r2, [r3, #8]
|
|
|
htim1.Init.Period = 65535;
|
|
|
8000d08: 4b1a ldr r3, [pc, #104] ; (8000d74 <MX_TIM1_Init+0x9c>)
|
|
|
8000d0a: f64f 72ff movw r2, #65535 ; 0xffff
|
|
|
8000d0e: 60da str r2, [r3, #12]
|
|
|
htim1.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
|
|
|
8000d10: 4b18 ldr r3, [pc, #96] ; (8000d74 <MX_TIM1_Init+0x9c>)
|
|
|
8000d12: 2200 movs r2, #0
|
|
|
8000d14: 611a str r2, [r3, #16]
|
|
|
htim1.Init.RepetitionCounter = 0;
|
|
|
8000d16: 4b17 ldr r3, [pc, #92] ; (8000d74 <MX_TIM1_Init+0x9c>)
|
|
|
8000d18: 2200 movs r2, #0
|
|
|
8000d1a: 615a str r2, [r3, #20]
|
|
|
htim1.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
|
|
|
8000d1c: 4b15 ldr r3, [pc, #84] ; (8000d74 <MX_TIM1_Init+0x9c>)
|
|
|
8000d1e: 2200 movs r2, #0
|
|
|
8000d20: 619a str r2, [r3, #24]
|
|
|
if (HAL_TIM_Base_Init(&htim1) != HAL_OK)
|
|
|
8000d22: 4814 ldr r0, [pc, #80] ; (8000d74 <MX_TIM1_Init+0x9c>)
|
|
|
8000d24: f001 f81a bl 8001d5c <HAL_TIM_Base_Init>
|
|
|
8000d28: 4603 mov r3, r0
|
|
|
8000d2a: 2b00 cmp r3, #0
|
|
|
8000d2c: d001 beq.n 8000d32 <MX_TIM1_Init+0x5a>
|
|
|
{
|
|
|
Error_Handler();
|
|
|
8000d2e: f7ff ff38 bl 8000ba2 <Error_Handler>
|
|
|
}
|
|
|
sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
|
|
|
8000d32: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
|
8000d36: 60bb str r3, [r7, #8]
|
|
|
if (HAL_TIM_ConfigClockSource(&htim1, &sClockSourceConfig) != HAL_OK)
|
|
|
8000d38: f107 0308 add.w r3, r7, #8
|
|
|
8000d3c: 4619 mov r1, r3
|
|
|
8000d3e: 480d ldr r0, [pc, #52] ; (8000d74 <MX_TIM1_Init+0x9c>)
|
|
|
8000d40: f001 f8cc bl 8001edc <HAL_TIM_ConfigClockSource>
|
|
|
8000d44: 4603 mov r3, r0
|
|
|
8000d46: 2b00 cmp r3, #0
|
|
|
8000d48: d001 beq.n 8000d4e <MX_TIM1_Init+0x76>
|
|
|
{
|
|
|
Error_Handler();
|
|
|
8000d4a: f7ff ff2a bl 8000ba2 <Error_Handler>
|
|
|
}
|
|
|
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
|
|
|
8000d4e: 2300 movs r3, #0
|
|
|
8000d50: 603b str r3, [r7, #0]
|
|
|
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
|
|
|
8000d52: 2300 movs r3, #0
|
|
|
8000d54: 607b str r3, [r7, #4]
|
|
|
if (HAL_TIMEx_MasterConfigSynchronization(&htim1, &sMasterConfig) != HAL_OK)
|
|
|
8000d56: 463b mov r3, r7
|
|
|
8000d58: 4619 mov r1, r3
|
|
|
8000d5a: 4806 ldr r0, [pc, #24] ; (8000d74 <MX_TIM1_Init+0x9c>)
|
|
|
8000d5c: f001 fa7a bl 8002254 <HAL_TIMEx_MasterConfigSynchronization>
|
|
|
8000d60: 4603 mov r3, r0
|
|
|
8000d62: 2b00 cmp r3, #0
|
|
|
8000d64: d001 beq.n 8000d6a <MX_TIM1_Init+0x92>
|
|
|
{
|
|
|
Error_Handler();
|
|
|
8000d66: f7ff ff1c bl 8000ba2 <Error_Handler>
|
|
|
}
|
|
|
/* USER CODE BEGIN TIM1_Init 2 */
|
|
|
|
|
|
/* USER CODE END TIM1_Init 2 */
|
|
|
|
|
|
}
|
|
|
8000d6a: bf00 nop
|
|
|
8000d6c: 3718 adds r7, #24
|
|
|
8000d6e: 46bd mov sp, r7
|
|
|
8000d70: bd80 pop {r7, pc}
|
|
|
8000d72: bf00 nop
|
|
|
8000d74: 20000090 .word 0x20000090
|
|
|
8000d78: 40012c00 .word 0x40012c00
|
|
|
|
|
|
08000d7c <HAL_TIM_Base_MspInit>:
|
|
|
|
|
|
void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* tim_baseHandle)
|
|
|
{
|
|
|
8000d7c: b480 push {r7}
|
|
|
8000d7e: b085 sub sp, #20
|
|
|
8000d80: af00 add r7, sp, #0
|
|
|
8000d82: 6078 str r0, [r7, #4]
|
|
|
|
|
|
if(tim_baseHandle->Instance==TIM1)
|
|
|
8000d84: 687b ldr r3, [r7, #4]
|
|
|
8000d86: 681b ldr r3, [r3, #0]
|
|
|
8000d88: 4a09 ldr r2, [pc, #36] ; (8000db0 <HAL_TIM_Base_MspInit+0x34>)
|
|
|
8000d8a: 4293 cmp r3, r2
|
|
|
8000d8c: d10b bne.n 8000da6 <HAL_TIM_Base_MspInit+0x2a>
|
|
|
{
|
|
|
/* USER CODE BEGIN TIM1_MspInit 0 */
|
|
|
|
|
|
/* USER CODE END TIM1_MspInit 0 */
|
|
|
/* TIM1 clock enable */
|
|
|
__HAL_RCC_TIM1_CLK_ENABLE();
|
|
|
8000d8e: 4b09 ldr r3, [pc, #36] ; (8000db4 <HAL_TIM_Base_MspInit+0x38>)
|
|
|
8000d90: 699b ldr r3, [r3, #24]
|
|
|
8000d92: 4a08 ldr r2, [pc, #32] ; (8000db4 <HAL_TIM_Base_MspInit+0x38>)
|
|
|
8000d94: f443 6300 orr.w r3, r3, #2048 ; 0x800
|
|
|
8000d98: 6193 str r3, [r2, #24]
|
|
|
8000d9a: 4b06 ldr r3, [pc, #24] ; (8000db4 <HAL_TIM_Base_MspInit+0x38>)
|
|
|
8000d9c: 699b ldr r3, [r3, #24]
|
|
|
8000d9e: f403 6300 and.w r3, r3, #2048 ; 0x800
|
|
|
8000da2: 60fb str r3, [r7, #12]
|
|
|
8000da4: 68fb ldr r3, [r7, #12]
|
|
|
/* USER CODE BEGIN TIM1_MspInit 1 */
|
|
|
|
|
|
/* USER CODE END TIM1_MspInit 1 */
|
|
|
}
|
|
|
}
|
|
|
8000da6: bf00 nop
|
|
|
8000da8: 3714 adds r7, #20
|
|
|
8000daa: 46bd mov sp, r7
|
|
|
8000dac: bc80 pop {r7}
|
|
|
8000dae: 4770 bx lr
|
|
|
8000db0: 40012c00 .word 0x40012c00
|
|
|
8000db4: 40021000 .word 0x40021000
|
|
|
|
|
|
08000db8 <MX_USART2_UART_Init>:
|
|
|
UART_HandleTypeDef huart2;
|
|
|
|
|
|
/* USART2 init function */
|
|
|
|
|
|
void MX_USART2_UART_Init(void)
|
|
|
{
|
|
|
8000db8: b580 push {r7, lr}
|
|
|
8000dba: af00 add r7, sp, #0
|
|
|
/* USER CODE END USART2_Init 0 */
|
|
|
|
|
|
/* USER CODE BEGIN USART2_Init 1 */
|
|
|
|
|
|
/* USER CODE END USART2_Init 1 */
|
|
|
huart2.Instance = USART2;
|
|
|
8000dbc: 4b11 ldr r3, [pc, #68] ; (8000e04 <MX_USART2_UART_Init+0x4c>)
|
|
|
8000dbe: 4a12 ldr r2, [pc, #72] ; (8000e08 <MX_USART2_UART_Init+0x50>)
|
|
|
8000dc0: 601a str r2, [r3, #0]
|
|
|
huart2.Init.BaudRate = 115200;
|
|
|
8000dc2: 4b10 ldr r3, [pc, #64] ; (8000e04 <MX_USART2_UART_Init+0x4c>)
|
|
|
8000dc4: f44f 32e1 mov.w r2, #115200 ; 0x1c200
|
|
|
8000dc8: 605a str r2, [r3, #4]
|
|
|
huart2.Init.WordLength = UART_WORDLENGTH_8B;
|
|
|
8000dca: 4b0e ldr r3, [pc, #56] ; (8000e04 <MX_USART2_UART_Init+0x4c>)
|
|
|
8000dcc: 2200 movs r2, #0
|
|
|
8000dce: 609a str r2, [r3, #8]
|
|
|
huart2.Init.StopBits = UART_STOPBITS_1;
|
|
|
8000dd0: 4b0c ldr r3, [pc, #48] ; (8000e04 <MX_USART2_UART_Init+0x4c>)
|
|
|
8000dd2: 2200 movs r2, #0
|
|
|
8000dd4: 60da str r2, [r3, #12]
|
|
|
huart2.Init.Parity = UART_PARITY_NONE;
|
|
|
8000dd6: 4b0b ldr r3, [pc, #44] ; (8000e04 <MX_USART2_UART_Init+0x4c>)
|
|
|
8000dd8: 2200 movs r2, #0
|
|
|
8000dda: 611a str r2, [r3, #16]
|
|
|
huart2.Init.Mode = UART_MODE_TX_RX;
|
|
|
8000ddc: 4b09 ldr r3, [pc, #36] ; (8000e04 <MX_USART2_UART_Init+0x4c>)
|
|
|
8000dde: 220c movs r2, #12
|
|
|
8000de0: 615a str r2, [r3, #20]
|
|
|
huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE;
|
|
|
8000de2: 4b08 ldr r3, [pc, #32] ; (8000e04 <MX_USART2_UART_Init+0x4c>)
|
|
|
8000de4: 2200 movs r2, #0
|
|
|
8000de6: 619a str r2, [r3, #24]
|
|
|
huart2.Init.OverSampling = UART_OVERSAMPLING_16;
|
|
|
8000de8: 4b06 ldr r3, [pc, #24] ; (8000e04 <MX_USART2_UART_Init+0x4c>)
|
|
|
8000dea: 2200 movs r2, #0
|
|
|
8000dec: 61da str r2, [r3, #28]
|
|
|
if (HAL_UART_Init(&huart2) != HAL_OK)
|
|
|
8000dee: 4805 ldr r0, [pc, #20] ; (8000e04 <MX_USART2_UART_Init+0x4c>)
|
|
|
8000df0: f001 fa8e bl 8002310 <HAL_UART_Init>
|
|
|
8000df4: 4603 mov r3, r0
|
|
|
8000df6: 2b00 cmp r3, #0
|
|
|
8000df8: d001 beq.n 8000dfe <MX_USART2_UART_Init+0x46>
|
|
|
{
|
|
|
Error_Handler();
|
|
|
8000dfa: f7ff fed2 bl 8000ba2 <Error_Handler>
|
|
|
}
|
|
|
/* USER CODE BEGIN USART2_Init 2 */
|
|
|
|
|
|
/* USER CODE END USART2_Init 2 */
|
|
|
|
|
|
}
|
|
|
8000dfe: bf00 nop
|
|
|
8000e00: bd80 pop {r7, pc}
|
|
|
8000e02: bf00 nop
|
|
|
8000e04: 200000d8 .word 0x200000d8
|
|
|
8000e08: 40004400 .word 0x40004400
|
|
|
|
|
|
08000e0c <HAL_UART_MspInit>:
|
|
|
|
|
|
void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle)
|
|
|
{
|
|
|
8000e0c: b580 push {r7, lr}
|
|
|
8000e0e: b088 sub sp, #32
|
|
|
8000e10: af00 add r7, sp, #0
|
|
|
8000e12: 6078 str r0, [r7, #4]
|
|
|
|
|
|
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
|
|
8000e14: f107 0310 add.w r3, r7, #16
|
|
|
8000e18: 2200 movs r2, #0
|
|
|
8000e1a: 601a str r2, [r3, #0]
|
|
|
8000e1c: 605a str r2, [r3, #4]
|
|
|
8000e1e: 609a str r2, [r3, #8]
|
|
|
8000e20: 60da str r2, [r3, #12]
|
|
|
if(uartHandle->Instance==USART2)
|
|
|
8000e22: 687b ldr r3, [r7, #4]
|
|
|
8000e24: 681b ldr r3, [r3, #0]
|
|
|
8000e26: 4a1b ldr r2, [pc, #108] ; (8000e94 <HAL_UART_MspInit+0x88>)
|
|
|
8000e28: 4293 cmp r3, r2
|
|
|
8000e2a: d12f bne.n 8000e8c <HAL_UART_MspInit+0x80>
|
|
|
{
|
|
|
/* USER CODE BEGIN USART2_MspInit 0 */
|
|
|
|
|
|
/* USER CODE END USART2_MspInit 0 */
|
|
|
/* USART2 clock enable */
|
|
|
__HAL_RCC_USART2_CLK_ENABLE();
|
|
|
8000e2c: 4b1a ldr r3, [pc, #104] ; (8000e98 <HAL_UART_MspInit+0x8c>)
|
|
|
8000e2e: 69db ldr r3, [r3, #28]
|
|
|
8000e30: 4a19 ldr r2, [pc, #100] ; (8000e98 <HAL_UART_MspInit+0x8c>)
|
|
|
8000e32: f443 3300 orr.w r3, r3, #131072 ; 0x20000
|
|
|
8000e36: 61d3 str r3, [r2, #28]
|
|
|
8000e38: 4b17 ldr r3, [pc, #92] ; (8000e98 <HAL_UART_MspInit+0x8c>)
|
|
|
8000e3a: 69db ldr r3, [r3, #28]
|
|
|
8000e3c: f403 3300 and.w r3, r3, #131072 ; 0x20000
|
|
|
8000e40: 60fb str r3, [r7, #12]
|
|
|
8000e42: 68fb ldr r3, [r7, #12]
|
|
|
|
|
|
__HAL_RCC_GPIOA_CLK_ENABLE();
|
|
|
8000e44: 4b14 ldr r3, [pc, #80] ; (8000e98 <HAL_UART_MspInit+0x8c>)
|
|
|
8000e46: 699b ldr r3, [r3, #24]
|
|
|
8000e48: 4a13 ldr r2, [pc, #76] ; (8000e98 <HAL_UART_MspInit+0x8c>)
|
|
|
8000e4a: f043 0304 orr.w r3, r3, #4
|
|
|
8000e4e: 6193 str r3, [r2, #24]
|
|
|
8000e50: 4b11 ldr r3, [pc, #68] ; (8000e98 <HAL_UART_MspInit+0x8c>)
|
|
|
8000e52: 699b ldr r3, [r3, #24]
|
|
|
8000e54: f003 0304 and.w r3, r3, #4
|
|
|
8000e58: 60bb str r3, [r7, #8]
|
|
|
8000e5a: 68bb ldr r3, [r7, #8]
|
|
|
/**USART2 GPIO Configuration
|
|
|
PA2 ------> USART2_TX
|
|
|
PA3 ------> USART2_RX
|
|
|
*/
|
|
|
GPIO_InitStruct.Pin = GPIO_PIN_2;
|
|
|
8000e5c: 2304 movs r3, #4
|
|
|
8000e5e: 613b str r3, [r7, #16]
|
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
|
8000e60: 2302 movs r3, #2
|
|
|
8000e62: 617b str r3, [r7, #20]
|
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
|
|
|
8000e64: 2303 movs r3, #3
|
|
|
8000e66: 61fb str r3, [r7, #28]
|
|
|
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
|
|
8000e68: f107 0310 add.w r3, r7, #16
|
|
|
8000e6c: 4619 mov r1, r3
|
|
|
8000e6e: 480b ldr r0, [pc, #44] ; (8000e9c <HAL_UART_MspInit+0x90>)
|
|
|
8000e70: f000 f9a6 bl 80011c0 <HAL_GPIO_Init>
|
|
|
|
|
|
GPIO_InitStruct.Pin = GPIO_PIN_3;
|
|
|
8000e74: 2308 movs r3, #8
|
|
|
8000e76: 613b str r3, [r7, #16]
|
|
|
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
|
|
|
8000e78: 2300 movs r3, #0
|
|
|
8000e7a: 617b str r3, [r7, #20]
|
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
|
8000e7c: 2300 movs r3, #0
|
|
|
8000e7e: 61bb str r3, [r7, #24]
|
|
|
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
|
|
8000e80: f107 0310 add.w r3, r7, #16
|
|
|
8000e84: 4619 mov r1, r3
|
|
|
8000e86: 4805 ldr r0, [pc, #20] ; (8000e9c <HAL_UART_MspInit+0x90>)
|
|
|
8000e88: f000 f99a bl 80011c0 <HAL_GPIO_Init>
|
|
|
|
|
|
/* USER CODE BEGIN USART2_MspInit 1 */
|
|
|
|
|
|
/* USER CODE END USART2_MspInit 1 */
|
|
|
}
|
|
|
}
|
|
|
8000e8c: bf00 nop
|
|
|
8000e8e: 3720 adds r7, #32
|
|
|
8000e90: 46bd mov sp, r7
|
|
|
8000e92: bd80 pop {r7, pc}
|
|
|
8000e94: 40004400 .word 0x40004400
|
|
|
8000e98: 40021000 .word 0x40021000
|
|
|
8000e9c: 40010800 .word 0x40010800
|
|
|
|
|
|
08000ea0 <Reset_Handler>:
|
|
|
.weak Reset_Handler
|
|
|
.type Reset_Handler, %function
|
|
|
Reset_Handler:
|
|
|
|
|
|
/* Copy the data segment initializers from flash to SRAM */
|
|
|
ldr r0, =_sdata
|
|
|
8000ea0: 480c ldr r0, [pc, #48] ; (8000ed4 <LoopFillZerobss+0x12>)
|
|
|
ldr r1, =_edata
|
|
|
8000ea2: 490d ldr r1, [pc, #52] ; (8000ed8 <LoopFillZerobss+0x16>)
|
|
|
ldr r2, =_sidata
|
|
|
8000ea4: 4a0d ldr r2, [pc, #52] ; (8000edc <LoopFillZerobss+0x1a>)
|
|
|
movs r3, #0
|
|
|
8000ea6: 2300 movs r3, #0
|
|
|
b LoopCopyDataInit
|
|
|
8000ea8: e002 b.n 8000eb0 <LoopCopyDataInit>
|
|
|
|
|
|
08000eaa <CopyDataInit>:
|
|
|
|
|
|
CopyDataInit:
|
|
|
ldr r4, [r2, r3]
|
|
|
8000eaa: 58d4 ldr r4, [r2, r3]
|
|
|
str r4, [r0, r3]
|
|
|
8000eac: 50c4 str r4, [r0, r3]
|
|
|
adds r3, r3, #4
|
|
|
8000eae: 3304 adds r3, #4
|
|
|
|
|
|
08000eb0 <LoopCopyDataInit>:
|
|
|
|
|
|
LoopCopyDataInit:
|
|
|
adds r4, r0, r3
|
|
|
8000eb0: 18c4 adds r4, r0, r3
|
|
|
cmp r4, r1
|
|
|
8000eb2: 428c cmp r4, r1
|
|
|
bcc CopyDataInit
|
|
|
8000eb4: d3f9 bcc.n 8000eaa <CopyDataInit>
|
|
|
|
|
|
/* Zero fill the bss segment. */
|
|
|
ldr r2, =_sbss
|
|
|
8000eb6: 4a0a ldr r2, [pc, #40] ; (8000ee0 <LoopFillZerobss+0x1e>)
|
|
|
ldr r4, =_ebss
|
|
|
8000eb8: 4c0a ldr r4, [pc, #40] ; (8000ee4 <LoopFillZerobss+0x22>)
|
|
|
movs r3, #0
|
|
|
8000eba: 2300 movs r3, #0
|
|
|
b LoopFillZerobss
|
|
|
8000ebc: e001 b.n 8000ec2 <LoopFillZerobss>
|
|
|
|
|
|
08000ebe <FillZerobss>:
|
|
|
|
|
|
FillZerobss:
|
|
|
str r3, [r2]
|
|
|
8000ebe: 6013 str r3, [r2, #0]
|
|
|
adds r2, r2, #4
|
|
|
8000ec0: 3204 adds r2, #4
|
|
|
|
|
|
08000ec2 <LoopFillZerobss>:
|
|
|
|
|
|
LoopFillZerobss:
|
|
|
cmp r2, r4
|
|
|
8000ec2: 42a2 cmp r2, r4
|
|
|
bcc FillZerobss
|
|
|
8000ec4: d3fb bcc.n 8000ebe <FillZerobss>
|
|
|
|
|
|
/* Call the clock system intitialization function.*/
|
|
|
bl SystemInit
|
|
|
8000ec6: f7ff ff01 bl 8000ccc <SystemInit>
|
|
|
/* Call static constructors */
|
|
|
bl __libc_init_array
|
|
|
8000eca: f001 fbdf bl 800268c <__libc_init_array>
|
|
|
/* Call the application's entry point.*/
|
|
|
bl main
|
|
|
8000ece: f7ff fda7 bl 8000a20 <main>
|
|
|
bx lr
|
|
|
8000ed2: 4770 bx lr
|
|
|
ldr r0, =_sdata
|
|
|
8000ed4: 20000000 .word 0x20000000
|
|
|
ldr r1, =_edata
|
|
|
8000ed8: 20000070 .word 0x20000070
|
|
|
ldr r2, =_sidata
|
|
|
8000edc: 08003064 .word 0x08003064
|
|
|
ldr r2, =_sbss
|
|
|
8000ee0: 20000070 .word 0x20000070
|
|
|
ldr r4, =_ebss
|
|
|
8000ee4: 20000130 .word 0x20000130
|
|
|
|
|
|
08000ee8 <ADC1_2_IRQHandler>:
|
|
|
* @retval : None
|
|
|
*/
|
|
|
.section .text.Default_Handler,"ax",%progbits
|
|
|
Default_Handler:
|
|
|
Infinite_Loop:
|
|
|
b Infinite_Loop
|
|
|
8000ee8: e7fe b.n 8000ee8 <ADC1_2_IRQHandler>
|
|
|
...
|
|
|
|
|
|
08000eec <HAL_Init>:
|
|
|
* need to ensure that the SysTick time base is always set to 1 millisecond
|
|
|
* to have correct HAL operation.
|
|
|
* @retval HAL status
|
|
|
*/
|
|
|
HAL_StatusTypeDef HAL_Init(void)
|
|
|
{
|
|
|
8000eec: b580 push {r7, lr}
|
|
|
8000eee: af00 add r7, sp, #0
|
|
|
defined(STM32F102x6) || defined(STM32F102xB) || \
|
|
|
defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || \
|
|
|
defined(STM32F105xC) || defined(STM32F107xC)
|
|
|
|
|
|
/* Prefetch buffer is not available on value line devices */
|
|
|
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
|
|
|
8000ef0: 4b08 ldr r3, [pc, #32] ; (8000f14 <HAL_Init+0x28>)
|
|
|
8000ef2: 681b ldr r3, [r3, #0]
|
|
|
8000ef4: 4a07 ldr r2, [pc, #28] ; (8000f14 <HAL_Init+0x28>)
|
|
|
8000ef6: f043 0310 orr.w r3, r3, #16
|
|
|
8000efa: 6013 str r3, [r2, #0]
|
|
|
#endif
|
|
|
#endif /* PREFETCH_ENABLE */
|
|
|
|
|
|
/* Set Interrupt Group Priority */
|
|
|
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
|
|
|
8000efc: 2003 movs r0, #3
|
|
|
8000efe: f000 f92b bl 8001158 <HAL_NVIC_SetPriorityGrouping>
|
|
|
|
|
|
/* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
|
|
|
HAL_InitTick(TICK_INT_PRIORITY);
|
|
|
8000f02: 200f movs r0, #15
|
|
|
8000f04: f000 f808 bl 8000f18 <HAL_InitTick>
|
|
|
|
|
|
/* Init the low level hardware */
|
|
|
HAL_MspInit();
|
|
|
8000f08: f7ff fe50 bl 8000bac <HAL_MspInit>
|
|
|
|
|
|
/* Return function status */
|
|
|
return HAL_OK;
|
|
|
8000f0c: 2300 movs r3, #0
|
|
|
}
|
|
|
8000f0e: 4618 mov r0, r3
|
|
|
8000f10: bd80 pop {r7, pc}
|
|
|
8000f12: bf00 nop
|
|
|
8000f14: 40022000 .word 0x40022000
|
|
|
|
|
|
08000f18 <HAL_InitTick>:
|
|
|
* implementation in user file.
|
|
|
* @param TickPriority Tick interrupt priority.
|
|
|
* @retval HAL status
|
|
|
*/
|
|
|
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
|
|
|
{
|
|
|
8000f18: b580 push {r7, lr}
|
|
|
8000f1a: b082 sub sp, #8
|
|
|
8000f1c: af00 add r7, sp, #0
|
|
|
8000f1e: 6078 str r0, [r7, #4]
|
|
|
/* Configure the SysTick to have interrupt in 1ms time basis*/
|
|
|
if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U)
|
|
|
8000f20: 4b12 ldr r3, [pc, #72] ; (8000f6c <HAL_InitTick+0x54>)
|
|
|
8000f22: 681a ldr r2, [r3, #0]
|
|
|
8000f24: 4b12 ldr r3, [pc, #72] ; (8000f70 <HAL_InitTick+0x58>)
|
|
|
8000f26: 781b ldrb r3, [r3, #0]
|
|
|
8000f28: 4619 mov r1, r3
|
|
|
8000f2a: f44f 737a mov.w r3, #1000 ; 0x3e8
|
|
|
8000f2e: fbb3 f3f1 udiv r3, r3, r1
|
|
|
8000f32: fbb2 f3f3 udiv r3, r2, r3
|
|
|
8000f36: 4618 mov r0, r3
|
|
|
8000f38: f000 f935 bl 80011a6 <HAL_SYSTICK_Config>
|
|
|
8000f3c: 4603 mov r3, r0
|
|
|
8000f3e: 2b00 cmp r3, #0
|
|
|
8000f40: d001 beq.n 8000f46 <HAL_InitTick+0x2e>
|
|
|
{
|
|
|
return HAL_ERROR;
|
|
|
8000f42: 2301 movs r3, #1
|
|
|
8000f44: e00e b.n 8000f64 <HAL_InitTick+0x4c>
|
|
|
}
|
|
|
|
|
|
/* Configure the SysTick IRQ priority */
|
|
|
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
|
|
|
8000f46: 687b ldr r3, [r7, #4]
|
|
|
8000f48: 2b0f cmp r3, #15
|
|
|
8000f4a: d80a bhi.n 8000f62 <HAL_InitTick+0x4a>
|
|
|
{
|
|
|
HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
|
|
|
8000f4c: 2200 movs r2, #0
|
|
|
8000f4e: 6879 ldr r1, [r7, #4]
|
|
|
8000f50: f04f 30ff mov.w r0, #4294967295
|
|
|
8000f54: f000 f90b bl 800116e <HAL_NVIC_SetPriority>
|
|
|
uwTickPrio = TickPriority;
|
|
|
8000f58: 4a06 ldr r2, [pc, #24] ; (8000f74 <HAL_InitTick+0x5c>)
|
|
|
8000f5a: 687b ldr r3, [r7, #4]
|
|
|
8000f5c: 6013 str r3, [r2, #0]
|
|
|
{
|
|
|
return HAL_ERROR;
|
|
|
}
|
|
|
|
|
|
/* Return function status */
|
|
|
return HAL_OK;
|
|
|
8000f5e: 2300 movs r3, #0
|
|
|
8000f60: e000 b.n 8000f64 <HAL_InitTick+0x4c>
|
|
|
return HAL_ERROR;
|
|
|
8000f62: 2301 movs r3, #1
|
|
|
}
|
|
|
8000f64: 4618 mov r0, r3
|
|
|
8000f66: 3708 adds r7, #8
|
|
|
8000f68: 46bd mov sp, r7
|
|
|
8000f6a: bd80 pop {r7, pc}
|
|
|
8000f6c: 20000000 .word 0x20000000
|
|
|
8000f70: 20000008 .word 0x20000008
|
|
|
8000f74: 20000004 .word 0x20000004
|
|
|
|
|
|
08000f78 <HAL_IncTick>:
|
|
|
* @note This function is declared as __weak to be overwritten in case of other
|
|
|
* implementations in user file.
|
|
|
* @retval None
|
|
|
*/
|
|
|
__weak void HAL_IncTick(void)
|
|
|
{
|
|
|
8000f78: b480 push {r7}
|
|
|
8000f7a: af00 add r7, sp, #0
|
|
|
uwTick += uwTickFreq;
|
|
|
8000f7c: 4b05 ldr r3, [pc, #20] ; (8000f94 <HAL_IncTick+0x1c>)
|
|
|
8000f7e: 781b ldrb r3, [r3, #0]
|
|
|
8000f80: 461a mov r2, r3
|
|
|
8000f82: 4b05 ldr r3, [pc, #20] ; (8000f98 <HAL_IncTick+0x20>)
|
|
|
8000f84: 681b ldr r3, [r3, #0]
|
|
|
8000f86: 4413 add r3, r2
|
|
|
8000f88: 4a03 ldr r2, [pc, #12] ; (8000f98 <HAL_IncTick+0x20>)
|
|
|
8000f8a: 6013 str r3, [r2, #0]
|
|
|
}
|
|
|
8000f8c: bf00 nop
|
|
|
8000f8e: 46bd mov sp, r7
|
|
|
8000f90: bc80 pop {r7}
|
|
|
8000f92: 4770 bx lr
|
|
|
8000f94: 20000008 .word 0x20000008
|
|
|
8000f98: 2000011c .word 0x2000011c
|
|
|
|
|
|
08000f9c <HAL_GetTick>:
|
|
|
* @note This function is declared as __weak to be overwritten in case of other
|
|
|
* implementations in user file.
|
|
|
* @retval tick value
|
|
|
*/
|
|
|
__weak uint32_t HAL_GetTick(void)
|
|
|
{
|
|
|
8000f9c: b480 push {r7}
|
|
|
8000f9e: af00 add r7, sp, #0
|
|
|
return uwTick;
|
|
|
8000fa0: 4b02 ldr r3, [pc, #8] ; (8000fac <HAL_GetTick+0x10>)
|
|
|
8000fa2: 681b ldr r3, [r3, #0]
|
|
|
}
|
|
|
8000fa4: 4618 mov r0, r3
|
|
|
8000fa6: 46bd mov sp, r7
|
|
|
8000fa8: bc80 pop {r7}
|
|
|
8000faa: 4770 bx lr
|
|
|
8000fac: 2000011c .word 0x2000011c
|
|
|
|
|
|
08000fb0 <HAL_Delay>:
|
|
|
* implementations in user file.
|
|
|
* @param Delay specifies the delay time length, in milliseconds.
|
|
|
* @retval None
|
|
|
*/
|
|
|
__weak void HAL_Delay(uint32_t Delay)
|
|
|
{
|
|
|
8000fb0: b580 push {r7, lr}
|
|
|
8000fb2: b084 sub sp, #16
|
|
|
8000fb4: af00 add r7, sp, #0
|
|
|
8000fb6: 6078 str r0, [r7, #4]
|
|
|
uint32_t tickstart = HAL_GetTick();
|
|
|
8000fb8: f7ff fff0 bl 8000f9c <HAL_GetTick>
|
|
|
8000fbc: 60b8 str r0, [r7, #8]
|
|
|
uint32_t wait = Delay;
|
|
|
8000fbe: 687b ldr r3, [r7, #4]
|
|
|
8000fc0: 60fb str r3, [r7, #12]
|
|
|
|
|
|
/* Add a freq to guarantee minimum wait */
|
|
|
if (wait < HAL_MAX_DELAY)
|
|
|
8000fc2: 68fb ldr r3, [r7, #12]
|
|
|
8000fc4: f1b3 3fff cmp.w r3, #4294967295
|
|
|
8000fc8: d005 beq.n 8000fd6 <HAL_Delay+0x26>
|
|
|
{
|
|
|
wait += (uint32_t)(uwTickFreq);
|
|
|
8000fca: 4b0a ldr r3, [pc, #40] ; (8000ff4 <HAL_Delay+0x44>)
|
|
|
8000fcc: 781b ldrb r3, [r3, #0]
|
|
|
8000fce: 461a mov r2, r3
|
|
|
8000fd0: 68fb ldr r3, [r7, #12]
|
|
|
8000fd2: 4413 add r3, r2
|
|
|
8000fd4: 60fb str r3, [r7, #12]
|
|
|
}
|
|
|
|
|
|
while ((HAL_GetTick() - tickstart) < wait)
|
|
|
8000fd6: bf00 nop
|
|
|
8000fd8: f7ff ffe0 bl 8000f9c <HAL_GetTick>
|
|
|
8000fdc: 4602 mov r2, r0
|
|
|
8000fde: 68bb ldr r3, [r7, #8]
|
|
|
8000fe0: 1ad3 subs r3, r2, r3
|
|
|
8000fe2: 68fa ldr r2, [r7, #12]
|
|
|
8000fe4: 429a cmp r2, r3
|
|
|
8000fe6: d8f7 bhi.n 8000fd8 <HAL_Delay+0x28>
|
|
|
{
|
|
|
}
|
|
|
}
|
|
|
8000fe8: bf00 nop
|
|
|
8000fea: bf00 nop
|
|
|
8000fec: 3710 adds r7, #16
|
|
|
8000fee: 46bd mov sp, r7
|
|
|
8000ff0: bd80 pop {r7, pc}
|
|
|
8000ff2: bf00 nop
|
|
|
8000ff4: 20000008 .word 0x20000008
|
|
|
|
|
|
08000ff8 <__NVIC_SetPriorityGrouping>:
|
|
|
In case of a conflict between priority grouping and available
|
|
|
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
|
|
|
\param [in] PriorityGroup Priority grouping field.
|
|
|
*/
|
|
|
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
|
|
|
{
|
|
|
8000ff8: b480 push {r7}
|
|
|
8000ffa: b085 sub sp, #20
|
|
|
8000ffc: af00 add r7, sp, #0
|
|
|
8000ffe: 6078 str r0, [r7, #4]
|
|
|
uint32_t reg_value;
|
|
|
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
|
|
|
8001000: 687b ldr r3, [r7, #4]
|
|
|
8001002: f003 0307 and.w r3, r3, #7
|
|
|
8001006: 60fb str r3, [r7, #12]
|
|
|
|
|
|
reg_value = SCB->AIRCR; /* read old register configuration */
|
|
|
8001008: 4b0c ldr r3, [pc, #48] ; (800103c <__NVIC_SetPriorityGrouping+0x44>)
|
|
|
800100a: 68db ldr r3, [r3, #12]
|
|
|
800100c: 60bb str r3, [r7, #8]
|
|
|
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
|
|
|
800100e: 68ba ldr r2, [r7, #8]
|
|
|
8001010: f64f 03ff movw r3, #63743 ; 0xf8ff
|
|
|
8001014: 4013 ands r3, r2
|
|
|
8001016: 60bb str r3, [r7, #8]
|
|
|
reg_value = (reg_value |
|
|
|
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
|
|
|
(PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
|
|
|
8001018: 68fb ldr r3, [r7, #12]
|
|
|
800101a: 021a lsls r2, r3, #8
|
|
|
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
|
|
|
800101c: 68bb ldr r3, [r7, #8]
|
|
|
800101e: 4313 orrs r3, r2
|
|
|
reg_value = (reg_value |
|
|
|
8001020: f043 63bf orr.w r3, r3, #100139008 ; 0x5f80000
|
|
|
8001024: f443 3300 orr.w r3, r3, #131072 ; 0x20000
|
|
|
8001028: 60bb str r3, [r7, #8]
|
|
|
SCB->AIRCR = reg_value;
|
|
|
800102a: 4a04 ldr r2, [pc, #16] ; (800103c <__NVIC_SetPriorityGrouping+0x44>)
|
|
|
800102c: 68bb ldr r3, [r7, #8]
|
|
|
800102e: 60d3 str r3, [r2, #12]
|
|
|
}
|
|
|
8001030: bf00 nop
|
|
|
8001032: 3714 adds r7, #20
|
|
|
8001034: 46bd mov sp, r7
|
|
|
8001036: bc80 pop {r7}
|
|
|
8001038: 4770 bx lr
|
|
|
800103a: bf00 nop
|
|
|
800103c: e000ed00 .word 0xe000ed00
|
|
|
|
|
|
08001040 <__NVIC_GetPriorityGrouping>:
|
|
|
\brief Get Priority Grouping
|
|
|
\details Reads the priority grouping field from the NVIC Interrupt Controller.
|
|
|
\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
|
|
|
*/
|
|
|
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
|
|
|
{
|
|
|
8001040: b480 push {r7}
|
|
|
8001042: af00 add r7, sp, #0
|
|
|
return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
|
|
|
8001044: 4b04 ldr r3, [pc, #16] ; (8001058 <__NVIC_GetPriorityGrouping+0x18>)
|
|
|
8001046: 68db ldr r3, [r3, #12]
|
|
|
8001048: 0a1b lsrs r3, r3, #8
|
|
|
800104a: f003 0307 and.w r3, r3, #7
|
|
|
}
|
|
|
800104e: 4618 mov r0, r3
|
|
|
8001050: 46bd mov sp, r7
|
|
|
8001052: bc80 pop {r7}
|
|
|
8001054: 4770 bx lr
|
|
|
8001056: bf00 nop
|
|
|
8001058: e000ed00 .word 0xe000ed00
|
|
|
|
|
|
0800105c <__NVIC_SetPriority>:
|
|
|
\param [in] IRQn Interrupt number.
|
|
|
\param [in] priority Priority to set.
|
|
|
\note The priority cannot be set for every processor exception.
|
|
|
*/
|
|
|
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
|
|
|
{
|
|
|
800105c: b480 push {r7}
|
|
|
800105e: b083 sub sp, #12
|
|
|
8001060: af00 add r7, sp, #0
|
|
|
8001062: 4603 mov r3, r0
|
|
|
8001064: 6039 str r1, [r7, #0]
|
|
|
8001066: 71fb strb r3, [r7, #7]
|
|
|
if ((int32_t)(IRQn) >= 0)
|
|
|
8001068: f997 3007 ldrsb.w r3, [r7, #7]
|
|
|
800106c: 2b00 cmp r3, #0
|
|
|
800106e: db0a blt.n 8001086 <__NVIC_SetPriority+0x2a>
|
|
|
{
|
|
|
NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
|
|
|
8001070: 683b ldr r3, [r7, #0]
|
|
|
8001072: b2da uxtb r2, r3
|
|
|
8001074: 490c ldr r1, [pc, #48] ; (80010a8 <__NVIC_SetPriority+0x4c>)
|
|
|
8001076: f997 3007 ldrsb.w r3, [r7, #7]
|
|
|
800107a: 0112 lsls r2, r2, #4
|
|
|
800107c: b2d2 uxtb r2, r2
|
|
|
800107e: 440b add r3, r1
|
|
|
8001080: f883 2300 strb.w r2, [r3, #768] ; 0x300
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
|
|
|
}
|
|
|
}
|
|
|
8001084: e00a b.n 800109c <__NVIC_SetPriority+0x40>
|
|
|
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
|
|
|
8001086: 683b ldr r3, [r7, #0]
|
|
|
8001088: b2da uxtb r2, r3
|
|
|
800108a: 4908 ldr r1, [pc, #32] ; (80010ac <__NVIC_SetPriority+0x50>)
|
|
|
800108c: 79fb ldrb r3, [r7, #7]
|
|
|
800108e: f003 030f and.w r3, r3, #15
|
|
|
8001092: 3b04 subs r3, #4
|
|
|
8001094: 0112 lsls r2, r2, #4
|
|
|
8001096: b2d2 uxtb r2, r2
|
|
|
8001098: 440b add r3, r1
|
|
|
800109a: 761a strb r2, [r3, #24]
|
|
|
}
|
|
|
800109c: bf00 nop
|
|
|
800109e: 370c adds r7, #12
|
|
|
80010a0: 46bd mov sp, r7
|
|
|
80010a2: bc80 pop {r7}
|
|
|
80010a4: 4770 bx lr
|
|
|
80010a6: bf00 nop
|
|
|
80010a8: e000e100 .word 0xe000e100
|
|
|
80010ac: e000ed00 .word 0xe000ed00
|
|
|
|
|
|
080010b0 <NVIC_EncodePriority>:
|
|
|
\param [in] PreemptPriority Preemptive priority value (starting from 0).
|
|
|
\param [in] SubPriority Subpriority value (starting from 0).
|
|
|
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
|
|
|
*/
|
|
|
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
|
|
|
{
|
|
|
80010b0: b480 push {r7}
|
|
|
80010b2: b089 sub sp, #36 ; 0x24
|
|
|
80010b4: af00 add r7, sp, #0
|
|
|
80010b6: 60f8 str r0, [r7, #12]
|
|
|
80010b8: 60b9 str r1, [r7, #8]
|
|
|
80010ba: 607a str r2, [r7, #4]
|
|
|
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
|
|
|
80010bc: 68fb ldr r3, [r7, #12]
|
|
|
80010be: f003 0307 and.w r3, r3, #7
|
|
|
80010c2: 61fb str r3, [r7, #28]
|
|
|
uint32_t PreemptPriorityBits;
|
|
|
uint32_t SubPriorityBits;
|
|
|
|
|
|
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
|
|
|
80010c4: 69fb ldr r3, [r7, #28]
|
|
|
80010c6: f1c3 0307 rsb r3, r3, #7
|
|
|
80010ca: 2b04 cmp r3, #4
|
|
|
80010cc: bf28 it cs
|
|
|
80010ce: 2304 movcs r3, #4
|
|
|
80010d0: 61bb str r3, [r7, #24]
|
|
|
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
|
|
|
80010d2: 69fb ldr r3, [r7, #28]
|
|
|
80010d4: 3304 adds r3, #4
|
|
|
80010d6: 2b06 cmp r3, #6
|
|
|
80010d8: d902 bls.n 80010e0 <NVIC_EncodePriority+0x30>
|
|
|
80010da: 69fb ldr r3, [r7, #28]
|
|
|
80010dc: 3b03 subs r3, #3
|
|
|
80010de: e000 b.n 80010e2 <NVIC_EncodePriority+0x32>
|
|
|
80010e0: 2300 movs r3, #0
|
|
|
80010e2: 617b str r3, [r7, #20]
|
|
|
|
|
|
return (
|
|
|
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
|
|
|
80010e4: f04f 32ff mov.w r2, #4294967295
|
|
|
80010e8: 69bb ldr r3, [r7, #24]
|
|
|
80010ea: fa02 f303 lsl.w r3, r2, r3
|
|
|
80010ee: 43da mvns r2, r3
|
|
|
80010f0: 68bb ldr r3, [r7, #8]
|
|
|
80010f2: 401a ands r2, r3
|
|
|
80010f4: 697b ldr r3, [r7, #20]
|
|
|
80010f6: 409a lsls r2, r3
|
|
|
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
|
|
|
80010f8: f04f 31ff mov.w r1, #4294967295
|
|
|
80010fc: 697b ldr r3, [r7, #20]
|
|
|
80010fe: fa01 f303 lsl.w r3, r1, r3
|
|
|
8001102: 43d9 mvns r1, r3
|
|
|
8001104: 687b ldr r3, [r7, #4]
|
|
|
8001106: 400b ands r3, r1
|
|
|
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
|
|
|
8001108: 4313 orrs r3, r2
|
|
|
);
|
|
|
}
|
|
|
800110a: 4618 mov r0, r3
|
|
|
800110c: 3724 adds r7, #36 ; 0x24
|
|
|
800110e: 46bd mov sp, r7
|
|
|
8001110: bc80 pop {r7}
|
|
|
8001112: 4770 bx lr
|
|
|
|
|
|
08001114 <SysTick_Config>:
|
|
|
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
|
|
|
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
|
|
|
must contain a vendor-specific implementation of this function.
|
|
|
*/
|
|
|
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
|
|
|
{
|
|
|
8001114: b580 push {r7, lr}
|
|
|
8001116: b082 sub sp, #8
|
|
|
8001118: af00 add r7, sp, #0
|
|
|
800111a: 6078 str r0, [r7, #4]
|
|
|
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
|
|
|
800111c: 687b ldr r3, [r7, #4]
|
|
|
800111e: 3b01 subs r3, #1
|
|
|
8001120: f1b3 7f80 cmp.w r3, #16777216 ; 0x1000000
|
|
|
8001124: d301 bcc.n 800112a <SysTick_Config+0x16>
|
|
|
{
|
|
|
return (1UL); /* Reload value impossible */
|
|
|
8001126: 2301 movs r3, #1
|
|
|
8001128: e00f b.n 800114a <SysTick_Config+0x36>
|
|
|
}
|
|
|
|
|
|
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
|
|
|
800112a: 4a0a ldr r2, [pc, #40] ; (8001154 <SysTick_Config+0x40>)
|
|
|
800112c: 687b ldr r3, [r7, #4]
|
|
|
800112e: 3b01 subs r3, #1
|
|
|
8001130: 6053 str r3, [r2, #4]
|
|
|
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
|
|
|
8001132: 210f movs r1, #15
|
|
|
8001134: f04f 30ff mov.w r0, #4294967295
|
|
|
8001138: f7ff ff90 bl 800105c <__NVIC_SetPriority>
|
|
|
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
|
|
|
800113c: 4b05 ldr r3, [pc, #20] ; (8001154 <SysTick_Config+0x40>)
|
|
|
800113e: 2200 movs r2, #0
|
|
|
8001140: 609a str r2, [r3, #8]
|
|
|
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
|
|
|
8001142: 4b04 ldr r3, [pc, #16] ; (8001154 <SysTick_Config+0x40>)
|
|
|
8001144: 2207 movs r2, #7
|
|
|
8001146: 601a str r2, [r3, #0]
|
|
|
SysTick_CTRL_TICKINT_Msk |
|
|
|
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
|
|
|
return (0UL); /* Function successful */
|
|
|
8001148: 2300 movs r3, #0
|
|
|
}
|
|
|
800114a: 4618 mov r0, r3
|
|
|
800114c: 3708 adds r7, #8
|
|
|
800114e: 46bd mov sp, r7
|
|
|
8001150: bd80 pop {r7, pc}
|
|
|
8001152: bf00 nop
|
|
|
8001154: e000e010 .word 0xe000e010
|
|
|
|
|
|
08001158 <HAL_NVIC_SetPriorityGrouping>:
|
|
|
* @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible.
|
|
|
* The pending IRQ priority will be managed only by the subpriority.
|
|
|
* @retval None
|
|
|
*/
|
|
|
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
|
|
|
{
|
|
|
8001158: b580 push {r7, lr}
|
|
|
800115a: b082 sub sp, #8
|
|
|
800115c: af00 add r7, sp, #0
|
|
|
800115e: 6078 str r0, [r7, #4]
|
|
|
/* Check the parameters */
|
|
|
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
|
|
|
|
|
|
/* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
|
|
|
NVIC_SetPriorityGrouping(PriorityGroup);
|
|
|
8001160: 6878 ldr r0, [r7, #4]
|
|
|
8001162: f7ff ff49 bl 8000ff8 <__NVIC_SetPriorityGrouping>
|
|
|
}
|
|
|
8001166: bf00 nop
|
|
|
8001168: 3708 adds r7, #8
|
|
|
800116a: 46bd mov sp, r7
|
|
|
800116c: bd80 pop {r7, pc}
|
|
|
|
|
|
0800116e <HAL_NVIC_SetPriority>:
|
|
|
* This parameter can be a value between 0 and 15
|
|
|
* A lower priority value indicates a higher priority.
|
|
|
* @retval None
|
|
|
*/
|
|
|
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
|
|
|
{
|
|
|
800116e: b580 push {r7, lr}
|
|
|
8001170: b086 sub sp, #24
|
|
|
8001172: af00 add r7, sp, #0
|
|
|
8001174: 4603 mov r3, r0
|
|
|
8001176: 60b9 str r1, [r7, #8]
|
|
|
8001178: 607a str r2, [r7, #4]
|
|
|
800117a: 73fb strb r3, [r7, #15]
|
|
|
uint32_t prioritygroup = 0x00U;
|
|
|
800117c: 2300 movs r3, #0
|
|
|
800117e: 617b str r3, [r7, #20]
|
|
|
|
|
|
/* Check the parameters */
|
|
|
assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
|
|
|
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
|
|
|
|
|
|
prioritygroup = NVIC_GetPriorityGrouping();
|
|
|
8001180: f7ff ff5e bl 8001040 <__NVIC_GetPriorityGrouping>
|
|
|
8001184: 6178 str r0, [r7, #20]
|
|
|
|
|
|
NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
|
|
|
8001186: 687a ldr r2, [r7, #4]
|
|
|
8001188: 68b9 ldr r1, [r7, #8]
|
|
|
800118a: 6978 ldr r0, [r7, #20]
|
|
|
800118c: f7ff ff90 bl 80010b0 <NVIC_EncodePriority>
|
|
|
8001190: 4602 mov r2, r0
|
|
|
8001192: f997 300f ldrsb.w r3, [r7, #15]
|
|
|
8001196: 4611 mov r1, r2
|
|
|
8001198: 4618 mov r0, r3
|
|
|
800119a: f7ff ff5f bl 800105c <__NVIC_SetPriority>
|
|
|
}
|
|
|
800119e: bf00 nop
|
|
|
80011a0: 3718 adds r7, #24
|
|
|
80011a2: 46bd mov sp, r7
|
|
|
80011a4: bd80 pop {r7, pc}
|
|
|
|
|
|
080011a6 <HAL_SYSTICK_Config>:
|
|
|
* @param TicksNumb: Specifies the ticks Number of ticks between two interrupts.
|
|
|
* @retval status: - 0 Function succeeded.
|
|
|
* - 1 Function failed.
|
|
|
*/
|
|
|
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
|
|
|
{
|
|
|
80011a6: b580 push {r7, lr}
|
|
|
80011a8: b082 sub sp, #8
|
|
|
80011aa: af00 add r7, sp, #0
|
|
|
80011ac: 6078 str r0, [r7, #4]
|
|
|
return SysTick_Config(TicksNumb);
|
|
|
80011ae: 6878 ldr r0, [r7, #4]
|
|
|
80011b0: f7ff ffb0 bl 8001114 <SysTick_Config>
|
|
|
80011b4: 4603 mov r3, r0
|
|
|
}
|
|
|
80011b6: 4618 mov r0, r3
|
|
|
80011b8: 3708 adds r7, #8
|
|
|
80011ba: 46bd mov sp, r7
|
|
|
80011bc: bd80 pop {r7, pc}
|
|
|
...
|
|
|
|
|
|
080011c0 <HAL_GPIO_Init>:
|
|
|
* @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains
|
|
|
* the configuration information for the specified GPIO peripheral.
|
|
|
* @retval None
|
|
|
*/
|
|
|
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
|
|
|
{
|
|
|
80011c0: b480 push {r7}
|
|
|
80011c2: b08b sub sp, #44 ; 0x2c
|
|
|
80011c4: af00 add r7, sp, #0
|
|
|
80011c6: 6078 str r0, [r7, #4]
|
|
|
80011c8: 6039 str r1, [r7, #0]
|
|
|
uint32_t position = 0x00u;
|
|
|
80011ca: 2300 movs r3, #0
|
|
|
80011cc: 627b str r3, [r7, #36] ; 0x24
|
|
|
uint32_t ioposition;
|
|
|
uint32_t iocurrent;
|
|
|
uint32_t temp;
|
|
|
uint32_t config = 0x00u;
|
|
|
80011ce: 2300 movs r3, #0
|
|
|
80011d0: 623b str r3, [r7, #32]
|
|
|
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
|
|
|
assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
|
|
|
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
|
|
|
|
|
|
/* Configure the port pins */
|
|
|
while (((GPIO_Init->Pin) >> position) != 0x00u)
|
|
|
80011d2: e169 b.n 80014a8 <HAL_GPIO_Init+0x2e8>
|
|
|
{
|
|
|
/* Get the IO position */
|
|
|
ioposition = (0x01uL << position);
|
|
|
80011d4: 2201 movs r2, #1
|
|
|
80011d6: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
|
80011d8: fa02 f303 lsl.w r3, r2, r3
|
|
|
80011dc: 61fb str r3, [r7, #28]
|
|
|
|
|
|
/* Get the current IO position */
|
|
|
iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition;
|
|
|
80011de: 683b ldr r3, [r7, #0]
|
|
|
80011e0: 681b ldr r3, [r3, #0]
|
|
|
80011e2: 69fa ldr r2, [r7, #28]
|
|
|
80011e4: 4013 ands r3, r2
|
|
|
80011e6: 61bb str r3, [r7, #24]
|
|
|
|
|
|
if (iocurrent == ioposition)
|
|
|
80011e8: 69ba ldr r2, [r7, #24]
|
|
|
80011ea: 69fb ldr r3, [r7, #28]
|
|
|
80011ec: 429a cmp r2, r3
|
|
|
80011ee: f040 8158 bne.w 80014a2 <HAL_GPIO_Init+0x2e2>
|
|
|
{
|
|
|
/* Check the Alternate function parameters */
|
|
|
assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
|
|
|
|
|
|
/* Based on the required mode, filling config variable with MODEy[1:0] and CNFy[3:2] corresponding bits */
|
|
|
switch (GPIO_Init->Mode)
|
|
|
80011f2: 683b ldr r3, [r7, #0]
|
|
|
80011f4: 685b ldr r3, [r3, #4]
|
|
|
80011f6: 4a9a ldr r2, [pc, #616] ; (8001460 <HAL_GPIO_Init+0x2a0>)
|
|
|
80011f8: 4293 cmp r3, r2
|
|
|
80011fa: d05e beq.n 80012ba <HAL_GPIO_Init+0xfa>
|
|
|
80011fc: 4a98 ldr r2, [pc, #608] ; (8001460 <HAL_GPIO_Init+0x2a0>)
|
|
|
80011fe: 4293 cmp r3, r2
|
|
|
8001200: d875 bhi.n 80012ee <HAL_GPIO_Init+0x12e>
|
|
|
8001202: 4a98 ldr r2, [pc, #608] ; (8001464 <HAL_GPIO_Init+0x2a4>)
|
|
|
8001204: 4293 cmp r3, r2
|
|
|
8001206: d058 beq.n 80012ba <HAL_GPIO_Init+0xfa>
|
|
|
8001208: 4a96 ldr r2, [pc, #600] ; (8001464 <HAL_GPIO_Init+0x2a4>)
|
|
|
800120a: 4293 cmp r3, r2
|
|
|
800120c: d86f bhi.n 80012ee <HAL_GPIO_Init+0x12e>
|
|
|
800120e: 4a96 ldr r2, [pc, #600] ; (8001468 <HAL_GPIO_Init+0x2a8>)
|
|
|
8001210: 4293 cmp r3, r2
|
|
|
8001212: d052 beq.n 80012ba <HAL_GPIO_Init+0xfa>
|
|
|
8001214: 4a94 ldr r2, [pc, #592] ; (8001468 <HAL_GPIO_Init+0x2a8>)
|
|
|
8001216: 4293 cmp r3, r2
|
|
|
8001218: d869 bhi.n 80012ee <HAL_GPIO_Init+0x12e>
|
|
|
800121a: 4a94 ldr r2, [pc, #592] ; (800146c <HAL_GPIO_Init+0x2ac>)
|
|
|
800121c: 4293 cmp r3, r2
|
|
|
800121e: d04c beq.n 80012ba <HAL_GPIO_Init+0xfa>
|
|
|
8001220: 4a92 ldr r2, [pc, #584] ; (800146c <HAL_GPIO_Init+0x2ac>)
|
|
|
8001222: 4293 cmp r3, r2
|
|
|
8001224: d863 bhi.n 80012ee <HAL_GPIO_Init+0x12e>
|
|
|
8001226: 4a92 ldr r2, [pc, #584] ; (8001470 <HAL_GPIO_Init+0x2b0>)
|
|
|
8001228: 4293 cmp r3, r2
|
|
|
800122a: d046 beq.n 80012ba <HAL_GPIO_Init+0xfa>
|
|
|
800122c: 4a90 ldr r2, [pc, #576] ; (8001470 <HAL_GPIO_Init+0x2b0>)
|
|
|
800122e: 4293 cmp r3, r2
|
|
|
8001230: d85d bhi.n 80012ee <HAL_GPIO_Init+0x12e>
|
|
|
8001232: 2b12 cmp r3, #18
|
|
|
8001234: d82a bhi.n 800128c <HAL_GPIO_Init+0xcc>
|
|
|
8001236: 2b12 cmp r3, #18
|
|
|
8001238: d859 bhi.n 80012ee <HAL_GPIO_Init+0x12e>
|
|
|
800123a: a201 add r2, pc, #4 ; (adr r2, 8001240 <HAL_GPIO_Init+0x80>)
|
|
|
800123c: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
|
8001240: 080012bb .word 0x080012bb
|
|
|
8001244: 08001295 .word 0x08001295
|
|
|
8001248: 080012a7 .word 0x080012a7
|
|
|
800124c: 080012e9 .word 0x080012e9
|
|
|
8001250: 080012ef .word 0x080012ef
|
|
|
8001254: 080012ef .word 0x080012ef
|
|
|
8001258: 080012ef .word 0x080012ef
|
|
|
800125c: 080012ef .word 0x080012ef
|
|
|
8001260: 080012ef .word 0x080012ef
|
|
|
8001264: 080012ef .word 0x080012ef
|
|
|
8001268: 080012ef .word 0x080012ef
|
|
|
800126c: 080012ef .word 0x080012ef
|
|
|
8001270: 080012ef .word 0x080012ef
|
|
|
8001274: 080012ef .word 0x080012ef
|
|
|
8001278: 080012ef .word 0x080012ef
|
|
|
800127c: 080012ef .word 0x080012ef
|
|
|
8001280: 080012ef .word 0x080012ef
|
|
|
8001284: 0800129d .word 0x0800129d
|
|
|
8001288: 080012b1 .word 0x080012b1
|
|
|
800128c: 4a79 ldr r2, [pc, #484] ; (8001474 <HAL_GPIO_Init+0x2b4>)
|
|
|
800128e: 4293 cmp r3, r2
|
|
|
8001290: d013 beq.n 80012ba <HAL_GPIO_Init+0xfa>
|
|
|
config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG;
|
|
|
break;
|
|
|
|
|
|
/* Parameters are checked with assert_param */
|
|
|
default:
|
|
|
break;
|
|
|
8001292: e02c b.n 80012ee <HAL_GPIO_Init+0x12e>
|
|
|
config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_PP;
|
|
|
8001294: 683b ldr r3, [r7, #0]
|
|
|
8001296: 68db ldr r3, [r3, #12]
|
|
|
8001298: 623b str r3, [r7, #32]
|
|
|
break;
|
|
|
800129a: e029 b.n 80012f0 <HAL_GPIO_Init+0x130>
|
|
|
config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_OD;
|
|
|
800129c: 683b ldr r3, [r7, #0]
|
|
|
800129e: 68db ldr r3, [r3, #12]
|
|
|
80012a0: 3304 adds r3, #4
|
|
|
80012a2: 623b str r3, [r7, #32]
|
|
|
break;
|
|
|
80012a4: e024 b.n 80012f0 <HAL_GPIO_Init+0x130>
|
|
|
config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_PP;
|
|
|
80012a6: 683b ldr r3, [r7, #0]
|
|
|
80012a8: 68db ldr r3, [r3, #12]
|
|
|
80012aa: 3308 adds r3, #8
|
|
|
80012ac: 623b str r3, [r7, #32]
|
|
|
break;
|
|
|
80012ae: e01f b.n 80012f0 <HAL_GPIO_Init+0x130>
|
|
|
config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_OD;
|
|
|
80012b0: 683b ldr r3, [r7, #0]
|
|
|
80012b2: 68db ldr r3, [r3, #12]
|
|
|
80012b4: 330c adds r3, #12
|
|
|
80012b6: 623b str r3, [r7, #32]
|
|
|
break;
|
|
|
80012b8: e01a b.n 80012f0 <HAL_GPIO_Init+0x130>
|
|
|
if (GPIO_Init->Pull == GPIO_NOPULL)
|
|
|
80012ba: 683b ldr r3, [r7, #0]
|
|
|
80012bc: 689b ldr r3, [r3, #8]
|
|
|
80012be: 2b00 cmp r3, #0
|
|
|
80012c0: d102 bne.n 80012c8 <HAL_GPIO_Init+0x108>
|
|
|
config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_FLOATING;
|
|
|
80012c2: 2304 movs r3, #4
|
|
|
80012c4: 623b str r3, [r7, #32]
|
|
|
break;
|
|
|
80012c6: e013 b.n 80012f0 <HAL_GPIO_Init+0x130>
|
|
|
else if (GPIO_Init->Pull == GPIO_PULLUP)
|
|
|
80012c8: 683b ldr r3, [r7, #0]
|
|
|
80012ca: 689b ldr r3, [r3, #8]
|
|
|
80012cc: 2b01 cmp r3, #1
|
|
|
80012ce: d105 bne.n 80012dc <HAL_GPIO_Init+0x11c>
|
|
|
config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD;
|
|
|
80012d0: 2308 movs r3, #8
|
|
|
80012d2: 623b str r3, [r7, #32]
|
|
|
GPIOx->BSRR = ioposition;
|
|
|
80012d4: 687b ldr r3, [r7, #4]
|
|
|
80012d6: 69fa ldr r2, [r7, #28]
|
|
|
80012d8: 611a str r2, [r3, #16]
|
|
|
break;
|
|
|
80012da: e009 b.n 80012f0 <HAL_GPIO_Init+0x130>
|
|
|
config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD;
|
|
|
80012dc: 2308 movs r3, #8
|
|
|
80012de: 623b str r3, [r7, #32]
|
|
|
GPIOx->BRR = ioposition;
|
|
|
80012e0: 687b ldr r3, [r7, #4]
|
|
|
80012e2: 69fa ldr r2, [r7, #28]
|
|
|
80012e4: 615a str r2, [r3, #20]
|
|
|
break;
|
|
|
80012e6: e003 b.n 80012f0 <HAL_GPIO_Init+0x130>
|
|
|
config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG;
|
|
|
80012e8: 2300 movs r3, #0
|
|
|
80012ea: 623b str r3, [r7, #32]
|
|
|
break;
|
|
|
80012ec: e000 b.n 80012f0 <HAL_GPIO_Init+0x130>
|
|
|
break;
|
|
|
80012ee: bf00 nop
|
|
|
}
|
|
|
|
|
|
/* Check if the current bit belongs to first half or last half of the pin count number
|
|
|
in order to address CRH or CRL register*/
|
|
|
configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL : &GPIOx->CRH;
|
|
|
80012f0: 69bb ldr r3, [r7, #24]
|
|
|
80012f2: 2bff cmp r3, #255 ; 0xff
|
|
|
80012f4: d801 bhi.n 80012fa <HAL_GPIO_Init+0x13a>
|
|
|
80012f6: 687b ldr r3, [r7, #4]
|
|
|
80012f8: e001 b.n 80012fe <HAL_GPIO_Init+0x13e>
|
|
|
80012fa: 687b ldr r3, [r7, #4]
|
|
|
80012fc: 3304 adds r3, #4
|
|
|
80012fe: 617b str r3, [r7, #20]
|
|
|
registeroffset = (iocurrent < GPIO_PIN_8) ? (position << 2u) : ((position - 8u) << 2u);
|
|
|
8001300: 69bb ldr r3, [r7, #24]
|
|
|
8001302: 2bff cmp r3, #255 ; 0xff
|
|
|
8001304: d802 bhi.n 800130c <HAL_GPIO_Init+0x14c>
|
|
|
8001306: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
|
8001308: 009b lsls r3, r3, #2
|
|
|
800130a: e002 b.n 8001312 <HAL_GPIO_Init+0x152>
|
|
|
800130c: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
|
800130e: 3b08 subs r3, #8
|
|
|
8001310: 009b lsls r3, r3, #2
|
|
|
8001312: 613b str r3, [r7, #16]
|
|
|
|
|
|
/* Apply the new configuration of the pin to the register */
|
|
|
MODIFY_REG((*configregister), ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset), (config << registeroffset));
|
|
|
8001314: 697b ldr r3, [r7, #20]
|
|
|
8001316: 681a ldr r2, [r3, #0]
|
|
|
8001318: 210f movs r1, #15
|
|
|
800131a: 693b ldr r3, [r7, #16]
|
|
|
800131c: fa01 f303 lsl.w r3, r1, r3
|
|
|
8001320: 43db mvns r3, r3
|
|
|
8001322: 401a ands r2, r3
|
|
|
8001324: 6a39 ldr r1, [r7, #32]
|
|
|
8001326: 693b ldr r3, [r7, #16]
|
|
|
8001328: fa01 f303 lsl.w r3, r1, r3
|
|
|
800132c: 431a orrs r2, r3
|
|
|
800132e: 697b ldr r3, [r7, #20]
|
|
|
8001330: 601a str r2, [r3, #0]
|
|
|
|
|
|
/*--------------------- EXTI Mode Configuration ------------------------*/
|
|
|
/* Configure the External Interrupt or event for the current IO */
|
|
|
if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
|
|
|
8001332: 683b ldr r3, [r7, #0]
|
|
|
8001334: 685b ldr r3, [r3, #4]
|
|
|
8001336: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
|
|
|
800133a: 2b00 cmp r3, #0
|
|
|
800133c: f000 80b1 beq.w 80014a2 <HAL_GPIO_Init+0x2e2>
|
|
|
{
|
|
|
/* Enable AFIO Clock */
|
|
|
__HAL_RCC_AFIO_CLK_ENABLE();
|
|
|
8001340: 4b4d ldr r3, [pc, #308] ; (8001478 <HAL_GPIO_Init+0x2b8>)
|
|
|
8001342: 699b ldr r3, [r3, #24]
|
|
|
8001344: 4a4c ldr r2, [pc, #304] ; (8001478 <HAL_GPIO_Init+0x2b8>)
|
|
|
8001346: f043 0301 orr.w r3, r3, #1
|
|
|
800134a: 6193 str r3, [r2, #24]
|
|
|
800134c: 4b4a ldr r3, [pc, #296] ; (8001478 <HAL_GPIO_Init+0x2b8>)
|
|
|
800134e: 699b ldr r3, [r3, #24]
|
|
|
8001350: f003 0301 and.w r3, r3, #1
|
|
|
8001354: 60bb str r3, [r7, #8]
|
|
|
8001356: 68bb ldr r3, [r7, #8]
|
|
|
temp = AFIO->EXTICR[position >> 2u];
|
|
|
8001358: 4a48 ldr r2, [pc, #288] ; (800147c <HAL_GPIO_Init+0x2bc>)
|
|
|
800135a: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
|
800135c: 089b lsrs r3, r3, #2
|
|
|
800135e: 3302 adds r3, #2
|
|
|
8001360: f852 3023 ldr.w r3, [r2, r3, lsl #2]
|
|
|
8001364: 60fb str r3, [r7, #12]
|
|
|
CLEAR_BIT(temp, (0x0Fu) << (4u * (position & 0x03u)));
|
|
|
8001366: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
|
8001368: f003 0303 and.w r3, r3, #3
|
|
|
800136c: 009b lsls r3, r3, #2
|
|
|
800136e: 220f movs r2, #15
|
|
|
8001370: fa02 f303 lsl.w r3, r2, r3
|
|
|
8001374: 43db mvns r3, r3
|
|
|
8001376: 68fa ldr r2, [r7, #12]
|
|
|
8001378: 4013 ands r3, r2
|
|
|
800137a: 60fb str r3, [r7, #12]
|
|
|
SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4u * (position & 0x03u)));
|
|
|
800137c: 687b ldr r3, [r7, #4]
|
|
|
800137e: 4a40 ldr r2, [pc, #256] ; (8001480 <HAL_GPIO_Init+0x2c0>)
|
|
|
8001380: 4293 cmp r3, r2
|
|
|
8001382: d013 beq.n 80013ac <HAL_GPIO_Init+0x1ec>
|
|
|
8001384: 687b ldr r3, [r7, #4]
|
|
|
8001386: 4a3f ldr r2, [pc, #252] ; (8001484 <HAL_GPIO_Init+0x2c4>)
|
|
|
8001388: 4293 cmp r3, r2
|
|
|
800138a: d00d beq.n 80013a8 <HAL_GPIO_Init+0x1e8>
|
|
|
800138c: 687b ldr r3, [r7, #4]
|
|
|
800138e: 4a3e ldr r2, [pc, #248] ; (8001488 <HAL_GPIO_Init+0x2c8>)
|
|
|
8001390: 4293 cmp r3, r2
|
|
|
8001392: d007 beq.n 80013a4 <HAL_GPIO_Init+0x1e4>
|
|
|
8001394: 687b ldr r3, [r7, #4]
|
|
|
8001396: 4a3d ldr r2, [pc, #244] ; (800148c <HAL_GPIO_Init+0x2cc>)
|
|
|
8001398: 4293 cmp r3, r2
|
|
|
800139a: d101 bne.n 80013a0 <HAL_GPIO_Init+0x1e0>
|
|
|
800139c: 2303 movs r3, #3
|
|
|
800139e: e006 b.n 80013ae <HAL_GPIO_Init+0x1ee>
|
|
|
80013a0: 2304 movs r3, #4
|
|
|
80013a2: e004 b.n 80013ae <HAL_GPIO_Init+0x1ee>
|
|
|
80013a4: 2302 movs r3, #2
|
|
|
80013a6: e002 b.n 80013ae <HAL_GPIO_Init+0x1ee>
|
|
|
80013a8: 2301 movs r3, #1
|
|
|
80013aa: e000 b.n 80013ae <HAL_GPIO_Init+0x1ee>
|
|
|
80013ac: 2300 movs r3, #0
|
|
|
80013ae: 6a7a ldr r2, [r7, #36] ; 0x24
|
|
|
80013b0: f002 0203 and.w r2, r2, #3
|
|
|
80013b4: 0092 lsls r2, r2, #2
|
|
|
80013b6: 4093 lsls r3, r2
|
|
|
80013b8: 68fa ldr r2, [r7, #12]
|
|
|
80013ba: 4313 orrs r3, r2
|
|
|
80013bc: 60fb str r3, [r7, #12]
|
|
|
AFIO->EXTICR[position >> 2u] = temp;
|
|
|
80013be: 492f ldr r1, [pc, #188] ; (800147c <HAL_GPIO_Init+0x2bc>)
|
|
|
80013c0: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
|
80013c2: 089b lsrs r3, r3, #2
|
|
|
80013c4: 3302 adds r3, #2
|
|
|
80013c6: 68fa ldr r2, [r7, #12]
|
|
|
80013c8: f841 2023 str.w r2, [r1, r3, lsl #2]
|
|
|
|
|
|
|
|
|
/* Configure the interrupt mask */
|
|
|
if ((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
|
|
|
80013cc: 683b ldr r3, [r7, #0]
|
|
|
80013ce: 685b ldr r3, [r3, #4]
|
|
|
80013d0: f403 3380 and.w r3, r3, #65536 ; 0x10000
|
|
|
80013d4: 2b00 cmp r3, #0
|
|
|
80013d6: d006 beq.n 80013e6 <HAL_GPIO_Init+0x226>
|
|
|
{
|
|
|
SET_BIT(EXTI->IMR, iocurrent);
|
|
|
80013d8: 4b2d ldr r3, [pc, #180] ; (8001490 <HAL_GPIO_Init+0x2d0>)
|
|
|
80013da: 681a ldr r2, [r3, #0]
|
|
|
80013dc: 492c ldr r1, [pc, #176] ; (8001490 <HAL_GPIO_Init+0x2d0>)
|
|
|
80013de: 69bb ldr r3, [r7, #24]
|
|
|
80013e0: 4313 orrs r3, r2
|
|
|
80013e2: 600b str r3, [r1, #0]
|
|
|
80013e4: e006 b.n 80013f4 <HAL_GPIO_Init+0x234>
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
CLEAR_BIT(EXTI->IMR, iocurrent);
|
|
|
80013e6: 4b2a ldr r3, [pc, #168] ; (8001490 <HAL_GPIO_Init+0x2d0>)
|
|
|
80013e8: 681a ldr r2, [r3, #0]
|
|
|
80013ea: 69bb ldr r3, [r7, #24]
|
|
|
80013ec: 43db mvns r3, r3
|
|
|
80013ee: 4928 ldr r1, [pc, #160] ; (8001490 <HAL_GPIO_Init+0x2d0>)
|
|
|
80013f0: 4013 ands r3, r2
|
|
|
80013f2: 600b str r3, [r1, #0]
|
|
|
}
|
|
|
|
|
|
/* Configure the event mask */
|
|
|
if ((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
|
|
|
80013f4: 683b ldr r3, [r7, #0]
|
|
|
80013f6: 685b ldr r3, [r3, #4]
|
|
|
80013f8: f403 3300 and.w r3, r3, #131072 ; 0x20000
|
|
|
80013fc: 2b00 cmp r3, #0
|
|
|
80013fe: d006 beq.n 800140e <HAL_GPIO_Init+0x24e>
|
|
|
{
|
|
|
SET_BIT(EXTI->EMR, iocurrent);
|
|
|
8001400: 4b23 ldr r3, [pc, #140] ; (8001490 <HAL_GPIO_Init+0x2d0>)
|
|
|
8001402: 685a ldr r2, [r3, #4]
|
|
|
8001404: 4922 ldr r1, [pc, #136] ; (8001490 <HAL_GPIO_Init+0x2d0>)
|
|
|
8001406: 69bb ldr r3, [r7, #24]
|
|
|
8001408: 4313 orrs r3, r2
|
|
|
800140a: 604b str r3, [r1, #4]
|
|
|
800140c: e006 b.n 800141c <HAL_GPIO_Init+0x25c>
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
CLEAR_BIT(EXTI->EMR, iocurrent);
|
|
|
800140e: 4b20 ldr r3, [pc, #128] ; (8001490 <HAL_GPIO_Init+0x2d0>)
|
|
|
8001410: 685a ldr r2, [r3, #4]
|
|
|
8001412: 69bb ldr r3, [r7, #24]
|
|
|
8001414: 43db mvns r3, r3
|
|
|
8001416: 491e ldr r1, [pc, #120] ; (8001490 <HAL_GPIO_Init+0x2d0>)
|
|
|
8001418: 4013 ands r3, r2
|
|
|
800141a: 604b str r3, [r1, #4]
|
|
|
}
|
|
|
|
|
|
/* Enable or disable the rising trigger */
|
|
|
if ((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
|
|
|
800141c: 683b ldr r3, [r7, #0]
|
|
|
800141e: 685b ldr r3, [r3, #4]
|
|
|
8001420: f403 1380 and.w r3, r3, #1048576 ; 0x100000
|
|
|
8001424: 2b00 cmp r3, #0
|
|
|
8001426: d006 beq.n 8001436 <HAL_GPIO_Init+0x276>
|
|
|
{
|
|
|
SET_BIT(EXTI->RTSR, iocurrent);
|
|
|
8001428: 4b19 ldr r3, [pc, #100] ; (8001490 <HAL_GPIO_Init+0x2d0>)
|
|
|
800142a: 689a ldr r2, [r3, #8]
|
|
|
800142c: 4918 ldr r1, [pc, #96] ; (8001490 <HAL_GPIO_Init+0x2d0>)
|
|
|
800142e: 69bb ldr r3, [r7, #24]
|
|
|
8001430: 4313 orrs r3, r2
|
|
|
8001432: 608b str r3, [r1, #8]
|
|
|
8001434: e006 b.n 8001444 <HAL_GPIO_Init+0x284>
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
CLEAR_BIT(EXTI->RTSR, iocurrent);
|
|
|
8001436: 4b16 ldr r3, [pc, #88] ; (8001490 <HAL_GPIO_Init+0x2d0>)
|
|
|
8001438: 689a ldr r2, [r3, #8]
|
|
|
800143a: 69bb ldr r3, [r7, #24]
|
|
|
800143c: 43db mvns r3, r3
|
|
|
800143e: 4914 ldr r1, [pc, #80] ; (8001490 <HAL_GPIO_Init+0x2d0>)
|
|
|
8001440: 4013 ands r3, r2
|
|
|
8001442: 608b str r3, [r1, #8]
|
|
|
}
|
|
|
|
|
|
/* Enable or disable the falling trigger */
|
|
|
if ((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
|
|
|
8001444: 683b ldr r3, [r7, #0]
|
|
|
8001446: 685b ldr r3, [r3, #4]
|
|
|
8001448: f403 1300 and.w r3, r3, #2097152 ; 0x200000
|
|
|
800144c: 2b00 cmp r3, #0
|
|
|
800144e: d021 beq.n 8001494 <HAL_GPIO_Init+0x2d4>
|
|
|
{
|
|
|
SET_BIT(EXTI->FTSR, iocurrent);
|
|
|
8001450: 4b0f ldr r3, [pc, #60] ; (8001490 <HAL_GPIO_Init+0x2d0>)
|
|
|
8001452: 68da ldr r2, [r3, #12]
|
|
|
8001454: 490e ldr r1, [pc, #56] ; (8001490 <HAL_GPIO_Init+0x2d0>)
|
|
|
8001456: 69bb ldr r3, [r7, #24]
|
|
|
8001458: 4313 orrs r3, r2
|
|
|
800145a: 60cb str r3, [r1, #12]
|
|
|
800145c: e021 b.n 80014a2 <HAL_GPIO_Init+0x2e2>
|
|
|
800145e: bf00 nop
|
|
|
8001460: 10320000 .word 0x10320000
|
|
|
8001464: 10310000 .word 0x10310000
|
|
|
8001468: 10220000 .word 0x10220000
|
|
|
800146c: 10210000 .word 0x10210000
|
|
|
8001470: 10120000 .word 0x10120000
|
|
|
8001474: 10110000 .word 0x10110000
|
|
|
8001478: 40021000 .word 0x40021000
|
|
|
800147c: 40010000 .word 0x40010000
|
|
|
8001480: 40010800 .word 0x40010800
|
|
|
8001484: 40010c00 .word 0x40010c00
|
|
|
8001488: 40011000 .word 0x40011000
|
|
|
800148c: 40011400 .word 0x40011400
|
|
|
8001490: 40010400 .word 0x40010400
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
CLEAR_BIT(EXTI->FTSR, iocurrent);
|
|
|
8001494: 4b0b ldr r3, [pc, #44] ; (80014c4 <HAL_GPIO_Init+0x304>)
|
|
|
8001496: 68da ldr r2, [r3, #12]
|
|
|
8001498: 69bb ldr r3, [r7, #24]
|
|
|
800149a: 43db mvns r3, r3
|
|
|
800149c: 4909 ldr r1, [pc, #36] ; (80014c4 <HAL_GPIO_Init+0x304>)
|
|
|
800149e: 4013 ands r3, r2
|
|
|
80014a0: 60cb str r3, [r1, #12]
|
|
|
}
|
|
|
}
|
|
|
}
|
|
|
|
|
|
position++;
|
|
|
80014a2: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
|
80014a4: 3301 adds r3, #1
|
|
|
80014a6: 627b str r3, [r7, #36] ; 0x24
|
|
|
while (((GPIO_Init->Pin) >> position) != 0x00u)
|
|
|
80014a8: 683b ldr r3, [r7, #0]
|
|
|
80014aa: 681a ldr r2, [r3, #0]
|
|
|
80014ac: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
|
80014ae: fa22 f303 lsr.w r3, r2, r3
|
|
|
80014b2: 2b00 cmp r3, #0
|
|
|
80014b4: f47f ae8e bne.w 80011d4 <HAL_GPIO_Init+0x14>
|
|
|
}
|
|
|
}
|
|
|
80014b8: bf00 nop
|
|
|
80014ba: bf00 nop
|
|
|
80014bc: 372c adds r7, #44 ; 0x2c
|
|
|
80014be: 46bd mov sp, r7
|
|
|
80014c0: bc80 pop {r7}
|
|
|
80014c2: 4770 bx lr
|
|
|
80014c4: 40010400 .word 0x40010400
|
|
|
|
|
|
080014c8 <HAL_GPIO_ReadPin>:
|
|
|
* @param GPIO_Pin: specifies the port bit to read.
|
|
|
* This parameter can be GPIO_PIN_x where x can be (0..15).
|
|
|
* @retval The input port pin value.
|
|
|
*/
|
|
|
GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
|
|
|
{
|
|
|
80014c8: b480 push {r7}
|
|
|
80014ca: b085 sub sp, #20
|
|
|
80014cc: af00 add r7, sp, #0
|
|
|
80014ce: 6078 str r0, [r7, #4]
|
|
|
80014d0: 460b mov r3, r1
|
|
|
80014d2: 807b strh r3, [r7, #2]
|
|
|
GPIO_PinState bitstatus;
|
|
|
|
|
|
/* Check the parameters */
|
|
|
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
|
|
|
|
|
if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET)
|
|
|
80014d4: 687b ldr r3, [r7, #4]
|
|
|
80014d6: 689a ldr r2, [r3, #8]
|
|
|
80014d8: 887b ldrh r3, [r7, #2]
|
|
|
80014da: 4013 ands r3, r2
|
|
|
80014dc: 2b00 cmp r3, #0
|
|
|
80014de: d002 beq.n 80014e6 <HAL_GPIO_ReadPin+0x1e>
|
|
|
{
|
|
|
bitstatus = GPIO_PIN_SET;
|
|
|
80014e0: 2301 movs r3, #1
|
|
|
80014e2: 73fb strb r3, [r7, #15]
|
|
|
80014e4: e001 b.n 80014ea <HAL_GPIO_ReadPin+0x22>
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
bitstatus = GPIO_PIN_RESET;
|
|
|
80014e6: 2300 movs r3, #0
|
|
|
80014e8: 73fb strb r3, [r7, #15]
|
|
|
}
|
|
|
return bitstatus;
|
|
|
80014ea: 7bfb ldrb r3, [r7, #15]
|
|
|
}
|
|
|
80014ec: 4618 mov r0, r3
|
|
|
80014ee: 3714 adds r7, #20
|
|
|
80014f0: 46bd mov sp, r7
|
|
|
80014f2: bc80 pop {r7}
|
|
|
80014f4: 4770 bx lr
|
|
|
|
|
|
080014f6 <HAL_GPIO_WritePin>:
|
|
|
* @arg GPIO_PIN_RESET: to clear the port pin
|
|
|
* @arg GPIO_PIN_SET: to set the port pin
|
|
|
* @retval None
|
|
|
*/
|
|
|
void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
|
|
|
{
|
|
|
80014f6: b480 push {r7}
|
|
|
80014f8: b083 sub sp, #12
|
|
|
80014fa: af00 add r7, sp, #0
|
|
|
80014fc: 6078 str r0, [r7, #4]
|
|
|
80014fe: 460b mov r3, r1
|
|
|
8001500: 807b strh r3, [r7, #2]
|
|
|
8001502: 4613 mov r3, r2
|
|
|
8001504: 707b strb r3, [r7, #1]
|
|
|
/* Check the parameters */
|
|
|
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
|
|
assert_param(IS_GPIO_PIN_ACTION(PinState));
|
|
|
|
|
|
if (PinState != GPIO_PIN_RESET)
|
|
|
8001506: 787b ldrb r3, [r7, #1]
|
|
|
8001508: 2b00 cmp r3, #0
|
|
|
800150a: d003 beq.n 8001514 <HAL_GPIO_WritePin+0x1e>
|
|
|
{
|
|
|
GPIOx->BSRR = GPIO_Pin;
|
|
|
800150c: 887a ldrh r2, [r7, #2]
|
|
|
800150e: 687b ldr r3, [r7, #4]
|
|
|
8001510: 611a str r2, [r3, #16]
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
GPIOx->BSRR = (uint32_t)GPIO_Pin << 16u;
|
|
|
}
|
|
|
}
|
|
|
8001512: e003 b.n 800151c <HAL_GPIO_WritePin+0x26>
|
|
|
GPIOx->BSRR = (uint32_t)GPIO_Pin << 16u;
|
|
|
8001514: 887b ldrh r3, [r7, #2]
|
|
|
8001516: 041a lsls r2, r3, #16
|
|
|
8001518: 687b ldr r3, [r7, #4]
|
|
|
800151a: 611a str r2, [r3, #16]
|
|
|
}
|
|
|
800151c: bf00 nop
|
|
|
800151e: 370c adds r7, #12
|
|
|
8001520: 46bd mov sp, r7
|
|
|
8001522: bc80 pop {r7}
|
|
|
8001524: 4770 bx lr
|
|
|
...
|
|
|
|
|
|
08001528 <HAL_RCC_OscConfig>:
|
|
|
* supported by this macro. User should request a transition to HSE Off
|
|
|
* first and then HSE On or HSE Bypass.
|
|
|
* @retval HAL status
|
|
|
*/
|
|
|
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
|
|
|
{
|
|
|
8001528: b580 push {r7, lr}
|
|
|
800152a: b086 sub sp, #24
|
|
|
800152c: af00 add r7, sp, #0
|
|
|
800152e: 6078 str r0, [r7, #4]
|
|
|
uint32_t tickstart;
|
|
|
uint32_t pll_config;
|
|
|
|
|
|
/* Check Null pointer */
|
|
|
if (RCC_OscInitStruct == NULL)
|
|
|
8001530: 687b ldr r3, [r7, #4]
|
|
|
8001532: 2b00 cmp r3, #0
|
|
|
8001534: d101 bne.n 800153a <HAL_RCC_OscConfig+0x12>
|
|
|
{
|
|
|
return HAL_ERROR;
|
|
|
8001536: 2301 movs r3, #1
|
|
|
8001538: e272 b.n 8001a20 <HAL_RCC_OscConfig+0x4f8>
|
|
|
|
|
|
/* Check the parameters */
|
|
|
assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
|
|
|
|
|
|
/*------------------------------- HSE Configuration ------------------------*/
|
|
|
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
|
|
|
800153a: 687b ldr r3, [r7, #4]
|
|
|
800153c: 681b ldr r3, [r3, #0]
|
|
|
800153e: f003 0301 and.w r3, r3, #1
|
|
|
8001542: 2b00 cmp r3, #0
|
|
|
8001544: f000 8087 beq.w 8001656 <HAL_RCC_OscConfig+0x12e>
|
|
|
{
|
|
|
/* Check the parameters */
|
|
|
assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
|
|
|
|
|
|
/* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
|
|
|
if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)
|
|
|
8001548: 4b92 ldr r3, [pc, #584] ; (8001794 <HAL_RCC_OscConfig+0x26c>)
|
|
|
800154a: 685b ldr r3, [r3, #4]
|
|
|
800154c: f003 030c and.w r3, r3, #12
|
|
|
8001550: 2b04 cmp r3, #4
|
|
|
8001552: d00c beq.n 800156e <HAL_RCC_OscConfig+0x46>
|
|
|
|| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE)))
|
|
|
8001554: 4b8f ldr r3, [pc, #572] ; (8001794 <HAL_RCC_OscConfig+0x26c>)
|
|
|
8001556: 685b ldr r3, [r3, #4]
|
|
|
8001558: f003 030c and.w r3, r3, #12
|
|
|
800155c: 2b08 cmp r3, #8
|
|
|
800155e: d112 bne.n 8001586 <HAL_RCC_OscConfig+0x5e>
|
|
|
8001560: 4b8c ldr r3, [pc, #560] ; (8001794 <HAL_RCC_OscConfig+0x26c>)
|
|
|
8001562: 685b ldr r3, [r3, #4]
|
|
|
8001564: f403 3380 and.w r3, r3, #65536 ; 0x10000
|
|
|
8001568: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
|
|
|
800156c: d10b bne.n 8001586 <HAL_RCC_OscConfig+0x5e>
|
|
|
{
|
|
|
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
|
|
|
800156e: 4b89 ldr r3, [pc, #548] ; (8001794 <HAL_RCC_OscConfig+0x26c>)
|
|
|
8001570: 681b ldr r3, [r3, #0]
|
|
|
8001572: f403 3300 and.w r3, r3, #131072 ; 0x20000
|
|
|
8001576: 2b00 cmp r3, #0
|
|
|
8001578: d06c beq.n 8001654 <HAL_RCC_OscConfig+0x12c>
|
|
|
800157a: 687b ldr r3, [r7, #4]
|
|
|
800157c: 685b ldr r3, [r3, #4]
|
|
|
800157e: 2b00 cmp r3, #0
|
|
|
8001580: d168 bne.n 8001654 <HAL_RCC_OscConfig+0x12c>
|
|
|
{
|
|
|
return HAL_ERROR;
|
|
|
8001582: 2301 movs r3, #1
|
|
|
8001584: e24c b.n 8001a20 <HAL_RCC_OscConfig+0x4f8>
|
|
|
}
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
/* Set the new HSE configuration ---------------------------------------*/
|
|
|
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
|
|
|
8001586: 687b ldr r3, [r7, #4]
|
|
|
8001588: 685b ldr r3, [r3, #4]
|
|
|
800158a: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
|
|
|
800158e: d106 bne.n 800159e <HAL_RCC_OscConfig+0x76>
|
|
|
8001590: 4b80 ldr r3, [pc, #512] ; (8001794 <HAL_RCC_OscConfig+0x26c>)
|
|
|
8001592: 681b ldr r3, [r3, #0]
|
|
|
8001594: 4a7f ldr r2, [pc, #508] ; (8001794 <HAL_RCC_OscConfig+0x26c>)
|
|
|
8001596: f443 3380 orr.w r3, r3, #65536 ; 0x10000
|
|
|
800159a: 6013 str r3, [r2, #0]
|
|
|
800159c: e02e b.n 80015fc <HAL_RCC_OscConfig+0xd4>
|
|
|
800159e: 687b ldr r3, [r7, #4]
|
|
|
80015a0: 685b ldr r3, [r3, #4]
|
|
|
80015a2: 2b00 cmp r3, #0
|
|
|
80015a4: d10c bne.n 80015c0 <HAL_RCC_OscConfig+0x98>
|
|
|
80015a6: 4b7b ldr r3, [pc, #492] ; (8001794 <HAL_RCC_OscConfig+0x26c>)
|
|
|
80015a8: 681b ldr r3, [r3, #0]
|
|
|
80015aa: 4a7a ldr r2, [pc, #488] ; (8001794 <HAL_RCC_OscConfig+0x26c>)
|
|
|
80015ac: f423 3380 bic.w r3, r3, #65536 ; 0x10000
|
|
|
80015b0: 6013 str r3, [r2, #0]
|
|
|
80015b2: 4b78 ldr r3, [pc, #480] ; (8001794 <HAL_RCC_OscConfig+0x26c>)
|
|
|
80015b4: 681b ldr r3, [r3, #0]
|
|
|
80015b6: 4a77 ldr r2, [pc, #476] ; (8001794 <HAL_RCC_OscConfig+0x26c>)
|
|
|
80015b8: f423 2380 bic.w r3, r3, #262144 ; 0x40000
|
|
|
80015bc: 6013 str r3, [r2, #0]
|
|
|
80015be: e01d b.n 80015fc <HAL_RCC_OscConfig+0xd4>
|
|
|
80015c0: 687b ldr r3, [r7, #4]
|
|
|
80015c2: 685b ldr r3, [r3, #4]
|
|
|
80015c4: f5b3 2fa0 cmp.w r3, #327680 ; 0x50000
|
|
|
80015c8: d10c bne.n 80015e4 <HAL_RCC_OscConfig+0xbc>
|
|
|
80015ca: 4b72 ldr r3, [pc, #456] ; (8001794 <HAL_RCC_OscConfig+0x26c>)
|
|
|
80015cc: 681b ldr r3, [r3, #0]
|
|
|
80015ce: 4a71 ldr r2, [pc, #452] ; (8001794 <HAL_RCC_OscConfig+0x26c>)
|
|
|
80015d0: f443 2380 orr.w r3, r3, #262144 ; 0x40000
|
|
|
80015d4: 6013 str r3, [r2, #0]
|
|
|
80015d6: 4b6f ldr r3, [pc, #444] ; (8001794 <HAL_RCC_OscConfig+0x26c>)
|
|
|
80015d8: 681b ldr r3, [r3, #0]
|
|
|
80015da: 4a6e ldr r2, [pc, #440] ; (8001794 <HAL_RCC_OscConfig+0x26c>)
|
|
|
80015dc: f443 3380 orr.w r3, r3, #65536 ; 0x10000
|
|
|
80015e0: 6013 str r3, [r2, #0]
|
|
|
80015e2: e00b b.n 80015fc <HAL_RCC_OscConfig+0xd4>
|
|
|
80015e4: 4b6b ldr r3, [pc, #428] ; (8001794 <HAL_RCC_OscConfig+0x26c>)
|
|
|
80015e6: 681b ldr r3, [r3, #0]
|
|
|
80015e8: 4a6a ldr r2, [pc, #424] ; (8001794 <HAL_RCC_OscConfig+0x26c>)
|
|
|
80015ea: f423 3380 bic.w r3, r3, #65536 ; 0x10000
|
|
|
80015ee: 6013 str r3, [r2, #0]
|
|
|
80015f0: 4b68 ldr r3, [pc, #416] ; (8001794 <HAL_RCC_OscConfig+0x26c>)
|
|
|
80015f2: 681b ldr r3, [r3, #0]
|
|
|
80015f4: 4a67 ldr r2, [pc, #412] ; (8001794 <HAL_RCC_OscConfig+0x26c>)
|
|
|
80015f6: f423 2380 bic.w r3, r3, #262144 ; 0x40000
|
|
|
80015fa: 6013 str r3, [r2, #0]
|
|
|
|
|
|
|
|
|
/* Check the HSE State */
|
|
|
if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
|
|
|
80015fc: 687b ldr r3, [r7, #4]
|
|
|
80015fe: 685b ldr r3, [r3, #4]
|
|
|
8001600: 2b00 cmp r3, #0
|
|
|
8001602: d013 beq.n 800162c <HAL_RCC_OscConfig+0x104>
|
|
|
{
|
|
|
/* Get Start Tick */
|
|
|
tickstart = HAL_GetTick();
|
|
|
8001604: f7ff fcca bl 8000f9c <HAL_GetTick>
|
|
|
8001608: 6138 str r0, [r7, #16]
|
|
|
|
|
|
/* Wait till HSE is ready */
|
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
|
|
|
800160a: e008 b.n 800161e <HAL_RCC_OscConfig+0xf6>
|
|
|
{
|
|
|
if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
|
|
|
800160c: f7ff fcc6 bl 8000f9c <HAL_GetTick>
|
|
|
8001610: 4602 mov r2, r0
|
|
|
8001612: 693b ldr r3, [r7, #16]
|
|
|
8001614: 1ad3 subs r3, r2, r3
|
|
|
8001616: 2b64 cmp r3, #100 ; 0x64
|
|
|
8001618: d901 bls.n 800161e <HAL_RCC_OscConfig+0xf6>
|
|
|
{
|
|
|
return HAL_TIMEOUT;
|
|
|
800161a: 2303 movs r3, #3
|
|
|
800161c: e200 b.n 8001a20 <HAL_RCC_OscConfig+0x4f8>
|
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
|
|
|
800161e: 4b5d ldr r3, [pc, #372] ; (8001794 <HAL_RCC_OscConfig+0x26c>)
|
|
|
8001620: 681b ldr r3, [r3, #0]
|
|
|
8001622: f403 3300 and.w r3, r3, #131072 ; 0x20000
|
|
|
8001626: 2b00 cmp r3, #0
|
|
|
8001628: d0f0 beq.n 800160c <HAL_RCC_OscConfig+0xe4>
|
|
|
800162a: e014 b.n 8001656 <HAL_RCC_OscConfig+0x12e>
|
|
|
}
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
/* Get Start Tick */
|
|
|
tickstart = HAL_GetTick();
|
|
|
800162c: f7ff fcb6 bl 8000f9c <HAL_GetTick>
|
|
|
8001630: 6138 str r0, [r7, #16]
|
|
|
|
|
|
/* Wait till HSE is disabled */
|
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
|
|
|
8001632: e008 b.n 8001646 <HAL_RCC_OscConfig+0x11e>
|
|
|
{
|
|
|
if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
|
|
|
8001634: f7ff fcb2 bl 8000f9c <HAL_GetTick>
|
|
|
8001638: 4602 mov r2, r0
|
|
|
800163a: 693b ldr r3, [r7, #16]
|
|
|
800163c: 1ad3 subs r3, r2, r3
|
|
|
800163e: 2b64 cmp r3, #100 ; 0x64
|
|
|
8001640: d901 bls.n 8001646 <HAL_RCC_OscConfig+0x11e>
|
|
|
{
|
|
|
return HAL_TIMEOUT;
|
|
|
8001642: 2303 movs r3, #3
|
|
|
8001644: e1ec b.n 8001a20 <HAL_RCC_OscConfig+0x4f8>
|
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
|
|
|
8001646: 4b53 ldr r3, [pc, #332] ; (8001794 <HAL_RCC_OscConfig+0x26c>)
|
|
|
8001648: 681b ldr r3, [r3, #0]
|
|
|
800164a: f403 3300 and.w r3, r3, #131072 ; 0x20000
|
|
|
800164e: 2b00 cmp r3, #0
|
|
|
8001650: d1f0 bne.n 8001634 <HAL_RCC_OscConfig+0x10c>
|
|
|
8001652: e000 b.n 8001656 <HAL_RCC_OscConfig+0x12e>
|
|
|
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
|
|
|
8001654: bf00 nop
|
|
|
}
|
|
|
}
|
|
|
}
|
|
|
}
|
|
|
/*----------------------------- HSI Configuration --------------------------*/
|
|
|
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
|
|
|
8001656: 687b ldr r3, [r7, #4]
|
|
|
8001658: 681b ldr r3, [r3, #0]
|
|
|
800165a: f003 0302 and.w r3, r3, #2
|
|
|
800165e: 2b00 cmp r3, #0
|
|
|
8001660: d063 beq.n 800172a <HAL_RCC_OscConfig+0x202>
|
|
|
/* Check the parameters */
|
|
|
assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
|
|
|
assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
|
|
|
|
|
|
/* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
|
|
|
if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)
|
|
|
8001662: 4b4c ldr r3, [pc, #304] ; (8001794 <HAL_RCC_OscConfig+0x26c>)
|
|
|
8001664: 685b ldr r3, [r3, #4]
|
|
|
8001666: f003 030c and.w r3, r3, #12
|
|
|
800166a: 2b00 cmp r3, #0
|
|
|
800166c: d00b beq.n 8001686 <HAL_RCC_OscConfig+0x15e>
|
|
|
|| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI_DIV2)))
|
|
|
800166e: 4b49 ldr r3, [pc, #292] ; (8001794 <HAL_RCC_OscConfig+0x26c>)
|
|
|
8001670: 685b ldr r3, [r3, #4]
|
|
|
8001672: f003 030c and.w r3, r3, #12
|
|
|
8001676: 2b08 cmp r3, #8
|
|
|
8001678: d11c bne.n 80016b4 <HAL_RCC_OscConfig+0x18c>
|
|
|
800167a: 4b46 ldr r3, [pc, #280] ; (8001794 <HAL_RCC_OscConfig+0x26c>)
|
|
|
800167c: 685b ldr r3, [r3, #4]
|
|
|
800167e: f403 3380 and.w r3, r3, #65536 ; 0x10000
|
|
|
8001682: 2b00 cmp r3, #0
|
|
|
8001684: d116 bne.n 80016b4 <HAL_RCC_OscConfig+0x18c>
|
|
|
{
|
|
|
/* When HSI is used as system clock it will not disabled */
|
|
|
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
|
|
|
8001686: 4b43 ldr r3, [pc, #268] ; (8001794 <HAL_RCC_OscConfig+0x26c>)
|
|
|
8001688: 681b ldr r3, [r3, #0]
|
|
|
800168a: f003 0302 and.w r3, r3, #2
|
|
|
800168e: 2b00 cmp r3, #0
|
|
|
8001690: d005 beq.n 800169e <HAL_RCC_OscConfig+0x176>
|
|
|
8001692: 687b ldr r3, [r7, #4]
|
|
|
8001694: 691b ldr r3, [r3, #16]
|
|
|
8001696: 2b01 cmp r3, #1
|
|
|
8001698: d001 beq.n 800169e <HAL_RCC_OscConfig+0x176>
|
|
|
{
|
|
|
return HAL_ERROR;
|
|
|
800169a: 2301 movs r3, #1
|
|
|
800169c: e1c0 b.n 8001a20 <HAL_RCC_OscConfig+0x4f8>
|
|
|
}
|
|
|
/* Otherwise, just the calibration is allowed */
|
|
|
else
|
|
|
{
|
|
|
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
|
|
|
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
|
|
|
800169e: 4b3d ldr r3, [pc, #244] ; (8001794 <HAL_RCC_OscConfig+0x26c>)
|
|
|
80016a0: 681b ldr r3, [r3, #0]
|
|
|
80016a2: f023 02f8 bic.w r2, r3, #248 ; 0xf8
|
|
|
80016a6: 687b ldr r3, [r7, #4]
|
|
|
80016a8: 695b ldr r3, [r3, #20]
|
|
|
80016aa: 00db lsls r3, r3, #3
|
|
|
80016ac: 4939 ldr r1, [pc, #228] ; (8001794 <HAL_RCC_OscConfig+0x26c>)
|
|
|
80016ae: 4313 orrs r3, r2
|
|
|
80016b0: 600b str r3, [r1, #0]
|
|
|
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
|
|
|
80016b2: e03a b.n 800172a <HAL_RCC_OscConfig+0x202>
|
|
|
}
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
/* Check the HSI State */
|
|
|
if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
|
|
|
80016b4: 687b ldr r3, [r7, #4]
|
|
|
80016b6: 691b ldr r3, [r3, #16]
|
|
|
80016b8: 2b00 cmp r3, #0
|
|
|
80016ba: d020 beq.n 80016fe <HAL_RCC_OscConfig+0x1d6>
|
|
|
{
|
|
|
/* Enable the Internal High Speed oscillator (HSI). */
|
|
|
__HAL_RCC_HSI_ENABLE();
|
|
|
80016bc: 4b36 ldr r3, [pc, #216] ; (8001798 <HAL_RCC_OscConfig+0x270>)
|
|
|
80016be: 2201 movs r2, #1
|
|
|
80016c0: 601a str r2, [r3, #0]
|
|
|
|
|
|
/* Get Start Tick */
|
|
|
tickstart = HAL_GetTick();
|
|
|
80016c2: f7ff fc6b bl 8000f9c <HAL_GetTick>
|
|
|
80016c6: 6138 str r0, [r7, #16]
|
|
|
|
|
|
/* Wait till HSI is ready */
|
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
|
|
|
80016c8: e008 b.n 80016dc <HAL_RCC_OscConfig+0x1b4>
|
|
|
{
|
|
|
if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
|
|
|
80016ca: f7ff fc67 bl 8000f9c <HAL_GetTick>
|
|
|
80016ce: 4602 mov r2, r0
|
|
|
80016d0: 693b ldr r3, [r7, #16]
|
|
|
80016d2: 1ad3 subs r3, r2, r3
|
|
|
80016d4: 2b02 cmp r3, #2
|
|
|
80016d6: d901 bls.n 80016dc <HAL_RCC_OscConfig+0x1b4>
|
|
|
{
|
|
|
return HAL_TIMEOUT;
|
|
|
80016d8: 2303 movs r3, #3
|
|
|
80016da: e1a1 b.n 8001a20 <HAL_RCC_OscConfig+0x4f8>
|
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
|
|
|
80016dc: 4b2d ldr r3, [pc, #180] ; (8001794 <HAL_RCC_OscConfig+0x26c>)
|
|
|
80016de: 681b ldr r3, [r3, #0]
|
|
|
80016e0: f003 0302 and.w r3, r3, #2
|
|
|
80016e4: 2b00 cmp r3, #0
|
|
|
80016e6: d0f0 beq.n 80016ca <HAL_RCC_OscConfig+0x1a2>
|
|
|
}
|
|
|
}
|
|
|
|
|
|
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
|
|
|
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
|
|
|
80016e8: 4b2a ldr r3, [pc, #168] ; (8001794 <HAL_RCC_OscConfig+0x26c>)
|
|
|
80016ea: 681b ldr r3, [r3, #0]
|
|
|
80016ec: f023 02f8 bic.w r2, r3, #248 ; 0xf8
|
|
|
80016f0: 687b ldr r3, [r7, #4]
|
|
|
80016f2: 695b ldr r3, [r3, #20]
|
|
|
80016f4: 00db lsls r3, r3, #3
|
|
|
80016f6: 4927 ldr r1, [pc, #156] ; (8001794 <HAL_RCC_OscConfig+0x26c>)
|
|
|
80016f8: 4313 orrs r3, r2
|
|
|
80016fa: 600b str r3, [r1, #0]
|
|
|
80016fc: e015 b.n 800172a <HAL_RCC_OscConfig+0x202>
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
/* Disable the Internal High Speed oscillator (HSI). */
|
|
|
__HAL_RCC_HSI_DISABLE();
|
|
|
80016fe: 4b26 ldr r3, [pc, #152] ; (8001798 <HAL_RCC_OscConfig+0x270>)
|
|
|
8001700: 2200 movs r2, #0
|
|
|
8001702: 601a str r2, [r3, #0]
|
|
|
|
|
|
/* Get Start Tick */
|
|
|
tickstart = HAL_GetTick();
|
|
|
8001704: f7ff fc4a bl 8000f9c <HAL_GetTick>
|
|
|
8001708: 6138 str r0, [r7, #16]
|
|
|
|
|
|
/* Wait till HSI is disabled */
|
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
|
|
|
800170a: e008 b.n 800171e <HAL_RCC_OscConfig+0x1f6>
|
|
|
{
|
|
|
if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
|
|
|
800170c: f7ff fc46 bl 8000f9c <HAL_GetTick>
|
|
|
8001710: 4602 mov r2, r0
|
|
|
8001712: 693b ldr r3, [r7, #16]
|
|
|
8001714: 1ad3 subs r3, r2, r3
|
|
|
8001716: 2b02 cmp r3, #2
|
|
|
8001718: d901 bls.n 800171e <HAL_RCC_OscConfig+0x1f6>
|
|
|
{
|
|
|
return HAL_TIMEOUT;
|
|
|
800171a: 2303 movs r3, #3
|
|
|
800171c: e180 b.n 8001a20 <HAL_RCC_OscConfig+0x4f8>
|
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
|
|
|
800171e: 4b1d ldr r3, [pc, #116] ; (8001794 <HAL_RCC_OscConfig+0x26c>)
|
|
|
8001720: 681b ldr r3, [r3, #0]
|
|
|
8001722: f003 0302 and.w r3, r3, #2
|
|
|
8001726: 2b00 cmp r3, #0
|
|
|
8001728: d1f0 bne.n 800170c <HAL_RCC_OscConfig+0x1e4>
|
|
|
}
|
|
|
}
|
|
|
}
|
|
|
}
|
|
|
/*------------------------------ LSI Configuration -------------------------*/
|
|
|
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
|
|
|
800172a: 687b ldr r3, [r7, #4]
|
|
|
800172c: 681b ldr r3, [r3, #0]
|
|
|
800172e: f003 0308 and.w r3, r3, #8
|
|
|
8001732: 2b00 cmp r3, #0
|
|
|
8001734: d03a beq.n 80017ac <HAL_RCC_OscConfig+0x284>
|
|
|
{
|
|
|
/* Check the parameters */
|
|
|
assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
|
|
|
|
|
|
/* Check the LSI State */
|
|
|
if (RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
|
|
|
8001736: 687b ldr r3, [r7, #4]
|
|
|
8001738: 699b ldr r3, [r3, #24]
|
|
|
800173a: 2b00 cmp r3, #0
|
|
|
800173c: d019 beq.n 8001772 <HAL_RCC_OscConfig+0x24a>
|
|
|
{
|
|
|
/* Enable the Internal Low Speed oscillator (LSI). */
|
|
|
__HAL_RCC_LSI_ENABLE();
|
|
|
800173e: 4b17 ldr r3, [pc, #92] ; (800179c <HAL_RCC_OscConfig+0x274>)
|
|
|
8001740: 2201 movs r2, #1
|
|
|
8001742: 601a str r2, [r3, #0]
|
|
|
|
|
|
/* Get Start Tick */
|
|
|
tickstart = HAL_GetTick();
|
|
|
8001744: f7ff fc2a bl 8000f9c <HAL_GetTick>
|
|
|
8001748: 6138 str r0, [r7, #16]
|
|
|
|
|
|
/* Wait till LSI is ready */
|
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
|
|
|
800174a: e008 b.n 800175e <HAL_RCC_OscConfig+0x236>
|
|
|
{
|
|
|
if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
|
|
|
800174c: f7ff fc26 bl 8000f9c <HAL_GetTick>
|
|
|
8001750: 4602 mov r2, r0
|
|
|
8001752: 693b ldr r3, [r7, #16]
|
|
|
8001754: 1ad3 subs r3, r2, r3
|
|
|
8001756: 2b02 cmp r3, #2
|
|
|
8001758: d901 bls.n 800175e <HAL_RCC_OscConfig+0x236>
|
|
|
{
|
|
|
return HAL_TIMEOUT;
|
|
|
800175a: 2303 movs r3, #3
|
|
|
800175c: e160 b.n 8001a20 <HAL_RCC_OscConfig+0x4f8>
|
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
|
|
|
800175e: 4b0d ldr r3, [pc, #52] ; (8001794 <HAL_RCC_OscConfig+0x26c>)
|
|
|
8001760: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
|
8001762: f003 0302 and.w r3, r3, #2
|
|
|
8001766: 2b00 cmp r3, #0
|
|
|
8001768: d0f0 beq.n 800174c <HAL_RCC_OscConfig+0x224>
|
|
|
}
|
|
|
}
|
|
|
/* To have a fully stabilized clock in the specified range, a software delay of 1ms
|
|
|
should be added.*/
|
|
|
RCC_Delay(1);
|
|
|
800176a: 2001 movs r0, #1
|
|
|
800176c: f000 fad8 bl 8001d20 <RCC_Delay>
|
|
|
8001770: e01c b.n 80017ac <HAL_RCC_OscConfig+0x284>
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
/* Disable the Internal Low Speed oscillator (LSI). */
|
|
|
__HAL_RCC_LSI_DISABLE();
|
|
|
8001772: 4b0a ldr r3, [pc, #40] ; (800179c <HAL_RCC_OscConfig+0x274>)
|
|
|
8001774: 2200 movs r2, #0
|
|
|
8001776: 601a str r2, [r3, #0]
|
|
|
|
|
|
/* Get Start Tick */
|
|
|
tickstart = HAL_GetTick();
|
|
|
8001778: f7ff fc10 bl 8000f9c <HAL_GetTick>
|
|
|
800177c: 6138 str r0, [r7, #16]
|
|
|
|
|
|
/* Wait till LSI is disabled */
|
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
|
|
|
800177e: e00f b.n 80017a0 <HAL_RCC_OscConfig+0x278>
|
|
|
{
|
|
|
if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
|
|
|
8001780: f7ff fc0c bl 8000f9c <HAL_GetTick>
|
|
|
8001784: 4602 mov r2, r0
|
|
|
8001786: 693b ldr r3, [r7, #16]
|
|
|
8001788: 1ad3 subs r3, r2, r3
|
|
|
800178a: 2b02 cmp r3, #2
|
|
|
800178c: d908 bls.n 80017a0 <HAL_RCC_OscConfig+0x278>
|
|
|
{
|
|
|
return HAL_TIMEOUT;
|
|
|
800178e: 2303 movs r3, #3
|
|
|
8001790: e146 b.n 8001a20 <HAL_RCC_OscConfig+0x4f8>
|
|
|
8001792: bf00 nop
|
|
|
8001794: 40021000 .word 0x40021000
|
|
|
8001798: 42420000 .word 0x42420000
|
|
|
800179c: 42420480 .word 0x42420480
|
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
|
|
|
80017a0: 4b92 ldr r3, [pc, #584] ; (80019ec <HAL_RCC_OscConfig+0x4c4>)
|
|
|
80017a2: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
|
80017a4: f003 0302 and.w r3, r3, #2
|
|
|
80017a8: 2b00 cmp r3, #0
|
|
|
80017aa: d1e9 bne.n 8001780 <HAL_RCC_OscConfig+0x258>
|
|
|
}
|
|
|
}
|
|
|
}
|
|
|
}
|
|
|
/*------------------------------ LSE Configuration -------------------------*/
|
|
|
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
|
|
|
80017ac: 687b ldr r3, [r7, #4]
|
|
|
80017ae: 681b ldr r3, [r3, #0]
|
|
|
80017b0: f003 0304 and.w r3, r3, #4
|
|
|
80017b4: 2b00 cmp r3, #0
|
|
|
80017b6: f000 80a6 beq.w 8001906 <HAL_RCC_OscConfig+0x3de>
|
|
|
{
|
|
|
FlagStatus pwrclkchanged = RESET;
|
|
|
80017ba: 2300 movs r3, #0
|
|
|
80017bc: 75fb strb r3, [r7, #23]
|
|
|
/* Check the parameters */
|
|
|
assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
|
|
|
|
|
|
/* Update LSE configuration in Backup Domain control register */
|
|
|
/* Requires to enable write access to Backup Domain of necessary */
|
|
|
if (__HAL_RCC_PWR_IS_CLK_DISABLED())
|
|
|
80017be: 4b8b ldr r3, [pc, #556] ; (80019ec <HAL_RCC_OscConfig+0x4c4>)
|
|
|
80017c0: 69db ldr r3, [r3, #28]
|
|
|
80017c2: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
|
|
|
80017c6: 2b00 cmp r3, #0
|
|
|
80017c8: d10d bne.n 80017e6 <HAL_RCC_OscConfig+0x2be>
|
|
|
{
|
|
|
__HAL_RCC_PWR_CLK_ENABLE();
|
|
|
80017ca: 4b88 ldr r3, [pc, #544] ; (80019ec <HAL_RCC_OscConfig+0x4c4>)
|
|
|
80017cc: 69db ldr r3, [r3, #28]
|
|
|
80017ce: 4a87 ldr r2, [pc, #540] ; (80019ec <HAL_RCC_OscConfig+0x4c4>)
|
|
|
80017d0: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
|
|
|
80017d4: 61d3 str r3, [r2, #28]
|
|
|
80017d6: 4b85 ldr r3, [pc, #532] ; (80019ec <HAL_RCC_OscConfig+0x4c4>)
|
|
|
80017d8: 69db ldr r3, [r3, #28]
|
|
|
80017da: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
|
|
|
80017de: 60bb str r3, [r7, #8]
|
|
|
80017e0: 68bb ldr r3, [r7, #8]
|
|
|
pwrclkchanged = SET;
|
|
|
80017e2: 2301 movs r3, #1
|
|
|
80017e4: 75fb strb r3, [r7, #23]
|
|
|
}
|
|
|
|
|
|
if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
|
|
|
80017e6: 4b82 ldr r3, [pc, #520] ; (80019f0 <HAL_RCC_OscConfig+0x4c8>)
|
|
|
80017e8: 681b ldr r3, [r3, #0]
|
|
|
80017ea: f403 7380 and.w r3, r3, #256 ; 0x100
|
|
|
80017ee: 2b00 cmp r3, #0
|
|
|
80017f0: d118 bne.n 8001824 <HAL_RCC_OscConfig+0x2fc>
|
|
|
{
|
|
|
/* Enable write access to Backup domain */
|
|
|
SET_BIT(PWR->CR, PWR_CR_DBP);
|
|
|
80017f2: 4b7f ldr r3, [pc, #508] ; (80019f0 <HAL_RCC_OscConfig+0x4c8>)
|
|
|
80017f4: 681b ldr r3, [r3, #0]
|
|
|
80017f6: 4a7e ldr r2, [pc, #504] ; (80019f0 <HAL_RCC_OscConfig+0x4c8>)
|
|
|
80017f8: f443 7380 orr.w r3, r3, #256 ; 0x100
|
|
|
80017fc: 6013 str r3, [r2, #0]
|
|
|
|
|
|
/* Wait for Backup domain Write protection disable */
|
|
|
tickstart = HAL_GetTick();
|
|
|
80017fe: f7ff fbcd bl 8000f9c <HAL_GetTick>
|
|
|
8001802: 6138 str r0, [r7, #16]
|
|
|
|
|
|
while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
|
|
|
8001804: e008 b.n 8001818 <HAL_RCC_OscConfig+0x2f0>
|
|
|
{
|
|
|
if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
|
|
|
8001806: f7ff fbc9 bl 8000f9c <HAL_GetTick>
|
|
|
800180a: 4602 mov r2, r0
|
|
|
800180c: 693b ldr r3, [r7, #16]
|
|
|
800180e: 1ad3 subs r3, r2, r3
|
|
|
8001810: 2b64 cmp r3, #100 ; 0x64
|
|
|
8001812: d901 bls.n 8001818 <HAL_RCC_OscConfig+0x2f0>
|
|
|
{
|
|
|
return HAL_TIMEOUT;
|
|
|
8001814: 2303 movs r3, #3
|
|
|
8001816: e103 b.n 8001a20 <HAL_RCC_OscConfig+0x4f8>
|
|
|
while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
|
|
|
8001818: 4b75 ldr r3, [pc, #468] ; (80019f0 <HAL_RCC_OscConfig+0x4c8>)
|
|
|
800181a: 681b ldr r3, [r3, #0]
|
|
|
800181c: f403 7380 and.w r3, r3, #256 ; 0x100
|
|
|
8001820: 2b00 cmp r3, #0
|
|
|
8001822: d0f0 beq.n 8001806 <HAL_RCC_OscConfig+0x2de>
|
|
|
}
|
|
|
}
|
|
|
}
|
|
|
|
|
|
/* Set the new LSE configuration -----------------------------------------*/
|
|
|
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
|
|
|
8001824: 687b ldr r3, [r7, #4]
|
|
|
8001826: 68db ldr r3, [r3, #12]
|
|
|
8001828: 2b01 cmp r3, #1
|
|
|
800182a: d106 bne.n 800183a <HAL_RCC_OscConfig+0x312>
|
|
|
800182c: 4b6f ldr r3, [pc, #444] ; (80019ec <HAL_RCC_OscConfig+0x4c4>)
|
|
|
800182e: 6a1b ldr r3, [r3, #32]
|
|
|
8001830: 4a6e ldr r2, [pc, #440] ; (80019ec <HAL_RCC_OscConfig+0x4c4>)
|
|
|
8001832: f043 0301 orr.w r3, r3, #1
|
|
|
8001836: 6213 str r3, [r2, #32]
|
|
|
8001838: e02d b.n 8001896 <HAL_RCC_OscConfig+0x36e>
|
|
|
800183a: 687b ldr r3, [r7, #4]
|
|
|
800183c: 68db ldr r3, [r3, #12]
|
|
|
800183e: 2b00 cmp r3, #0
|
|
|
8001840: d10c bne.n 800185c <HAL_RCC_OscConfig+0x334>
|
|
|
8001842: 4b6a ldr r3, [pc, #424] ; (80019ec <HAL_RCC_OscConfig+0x4c4>)
|
|
|
8001844: 6a1b ldr r3, [r3, #32]
|
|
|
8001846: 4a69 ldr r2, [pc, #420] ; (80019ec <HAL_RCC_OscConfig+0x4c4>)
|
|
|
8001848: f023 0301 bic.w r3, r3, #1
|
|
|
800184c: 6213 str r3, [r2, #32]
|
|
|
800184e: 4b67 ldr r3, [pc, #412] ; (80019ec <HAL_RCC_OscConfig+0x4c4>)
|
|
|
8001850: 6a1b ldr r3, [r3, #32]
|
|
|
8001852: 4a66 ldr r2, [pc, #408] ; (80019ec <HAL_RCC_OscConfig+0x4c4>)
|
|
|
8001854: f023 0304 bic.w r3, r3, #4
|
|
|
8001858: 6213 str r3, [r2, #32]
|
|
|
800185a: e01c b.n 8001896 <HAL_RCC_OscConfig+0x36e>
|
|
|
800185c: 687b ldr r3, [r7, #4]
|
|
|
800185e: 68db ldr r3, [r3, #12]
|
|
|
8001860: 2b05 cmp r3, #5
|
|
|
8001862: d10c bne.n 800187e <HAL_RCC_OscConfig+0x356>
|
|
|
8001864: 4b61 ldr r3, [pc, #388] ; (80019ec <HAL_RCC_OscConfig+0x4c4>)
|
|
|
8001866: 6a1b ldr r3, [r3, #32]
|
|
|
8001868: 4a60 ldr r2, [pc, #384] ; (80019ec <HAL_RCC_OscConfig+0x4c4>)
|
|
|
800186a: f043 0304 orr.w r3, r3, #4
|
|
|
800186e: 6213 str r3, [r2, #32]
|
|
|
8001870: 4b5e ldr r3, [pc, #376] ; (80019ec <HAL_RCC_OscConfig+0x4c4>)
|
|
|
8001872: 6a1b ldr r3, [r3, #32]
|
|
|
8001874: 4a5d ldr r2, [pc, #372] ; (80019ec <HAL_RCC_OscConfig+0x4c4>)
|
|
|
8001876: f043 0301 orr.w r3, r3, #1
|
|
|
800187a: 6213 str r3, [r2, #32]
|
|
|
800187c: e00b b.n 8001896 <HAL_RCC_OscConfig+0x36e>
|
|
|
800187e: 4b5b ldr r3, [pc, #364] ; (80019ec <HAL_RCC_OscConfig+0x4c4>)
|
|
|
8001880: 6a1b ldr r3, [r3, #32]
|
|
|
8001882: 4a5a ldr r2, [pc, #360] ; (80019ec <HAL_RCC_OscConfig+0x4c4>)
|
|
|
8001884: f023 0301 bic.w r3, r3, #1
|
|
|
8001888: 6213 str r3, [r2, #32]
|
|
|
800188a: 4b58 ldr r3, [pc, #352] ; (80019ec <HAL_RCC_OscConfig+0x4c4>)
|
|
|
800188c: 6a1b ldr r3, [r3, #32]
|
|
|
800188e: 4a57 ldr r2, [pc, #348] ; (80019ec <HAL_RCC_OscConfig+0x4c4>)
|
|
|
8001890: f023 0304 bic.w r3, r3, #4
|
|
|
8001894: 6213 str r3, [r2, #32]
|
|
|
/* Check the LSE State */
|
|
|
if (RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
|
|
|
8001896: 687b ldr r3, [r7, #4]
|
|
|
8001898: 68db ldr r3, [r3, #12]
|
|
|
800189a: 2b00 cmp r3, #0
|
|
|
800189c: d015 beq.n 80018ca <HAL_RCC_OscConfig+0x3a2>
|
|
|
{
|
|
|
/* Get Start Tick */
|
|
|
tickstart = HAL_GetTick();
|
|
|
800189e: f7ff fb7d bl 8000f9c <HAL_GetTick>
|
|
|
80018a2: 6138 str r0, [r7, #16]
|
|
|
|
|
|
/* Wait till LSE is ready */
|
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
|
|
|
80018a4: e00a b.n 80018bc <HAL_RCC_OscConfig+0x394>
|
|
|
{
|
|
|
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
|
|
|
80018a6: f7ff fb79 bl 8000f9c <HAL_GetTick>
|
|
|
80018aa: 4602 mov r2, r0
|
|
|
80018ac: 693b ldr r3, [r7, #16]
|
|
|
80018ae: 1ad3 subs r3, r2, r3
|
|
|
80018b0: f241 3288 movw r2, #5000 ; 0x1388
|
|
|
80018b4: 4293 cmp r3, r2
|
|
|
80018b6: d901 bls.n 80018bc <HAL_RCC_OscConfig+0x394>
|
|
|
{
|
|
|
return HAL_TIMEOUT;
|
|
|
80018b8: 2303 movs r3, #3
|
|
|
80018ba: e0b1 b.n 8001a20 <HAL_RCC_OscConfig+0x4f8>
|
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
|
|
|
80018bc: 4b4b ldr r3, [pc, #300] ; (80019ec <HAL_RCC_OscConfig+0x4c4>)
|
|
|
80018be: 6a1b ldr r3, [r3, #32]
|
|
|
80018c0: f003 0302 and.w r3, r3, #2
|
|
|
80018c4: 2b00 cmp r3, #0
|
|
|
80018c6: d0ee beq.n 80018a6 <HAL_RCC_OscConfig+0x37e>
|
|
|
80018c8: e014 b.n 80018f4 <HAL_RCC_OscConfig+0x3cc>
|
|
|
}
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
/* Get Start Tick */
|
|
|
tickstart = HAL_GetTick();
|
|
|
80018ca: f7ff fb67 bl 8000f9c <HAL_GetTick>
|
|
|
80018ce: 6138 str r0, [r7, #16]
|
|
|
|
|
|
/* Wait till LSE is disabled */
|
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
|
|
|
80018d0: e00a b.n 80018e8 <HAL_RCC_OscConfig+0x3c0>
|
|
|
{
|
|
|
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
|
|
|
80018d2: f7ff fb63 bl 8000f9c <HAL_GetTick>
|
|
|
80018d6: 4602 mov r2, r0
|
|
|
80018d8: 693b ldr r3, [r7, #16]
|
|
|
80018da: 1ad3 subs r3, r2, r3
|
|
|
80018dc: f241 3288 movw r2, #5000 ; 0x1388
|
|
|
80018e0: 4293 cmp r3, r2
|
|
|
80018e2: d901 bls.n 80018e8 <HAL_RCC_OscConfig+0x3c0>
|
|
|
{
|
|
|
return HAL_TIMEOUT;
|
|
|
80018e4: 2303 movs r3, #3
|
|
|
80018e6: e09b b.n 8001a20 <HAL_RCC_OscConfig+0x4f8>
|
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
|
|
|
80018e8: 4b40 ldr r3, [pc, #256] ; (80019ec <HAL_RCC_OscConfig+0x4c4>)
|
|
|
80018ea: 6a1b ldr r3, [r3, #32]
|
|
|
80018ec: f003 0302 and.w r3, r3, #2
|
|
|
80018f0: 2b00 cmp r3, #0
|
|
|
80018f2: d1ee bne.n 80018d2 <HAL_RCC_OscConfig+0x3aa>
|
|
|
}
|
|
|
}
|
|
|
}
|
|
|
|
|
|
/* Require to disable power clock if necessary */
|
|
|
if (pwrclkchanged == SET)
|
|
|
80018f4: 7dfb ldrb r3, [r7, #23]
|
|
|
80018f6: 2b01 cmp r3, #1
|
|
|
80018f8: d105 bne.n 8001906 <HAL_RCC_OscConfig+0x3de>
|
|
|
{
|
|
|
__HAL_RCC_PWR_CLK_DISABLE();
|
|
|
80018fa: 4b3c ldr r3, [pc, #240] ; (80019ec <HAL_RCC_OscConfig+0x4c4>)
|
|
|
80018fc: 69db ldr r3, [r3, #28]
|
|
|
80018fe: 4a3b ldr r2, [pc, #236] ; (80019ec <HAL_RCC_OscConfig+0x4c4>)
|
|
|
8001900: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000
|
|
|
8001904: 61d3 str r3, [r2, #28]
|
|
|
|
|
|
#endif /* RCC_CR_PLL2ON */
|
|
|
/*-------------------------------- PLL Configuration -----------------------*/
|
|
|
/* Check the parameters */
|
|
|
assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
|
|
|
if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
|
|
|
8001906: 687b ldr r3, [r7, #4]
|
|
|
8001908: 69db ldr r3, [r3, #28]
|
|
|
800190a: 2b00 cmp r3, #0
|
|
|
800190c: f000 8087 beq.w 8001a1e <HAL_RCC_OscConfig+0x4f6>
|
|
|
{
|
|
|
/* Check if the PLL is used as system clock or not */
|
|
|
if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
|
|
|
8001910: 4b36 ldr r3, [pc, #216] ; (80019ec <HAL_RCC_OscConfig+0x4c4>)
|
|
|
8001912: 685b ldr r3, [r3, #4]
|
|
|
8001914: f003 030c and.w r3, r3, #12
|
|
|
8001918: 2b08 cmp r3, #8
|
|
|
800191a: d061 beq.n 80019e0 <HAL_RCC_OscConfig+0x4b8>
|
|
|
{
|
|
|
if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
|
|
|
800191c: 687b ldr r3, [r7, #4]
|
|
|
800191e: 69db ldr r3, [r3, #28]
|
|
|
8001920: 2b02 cmp r3, #2
|
|
|
8001922: d146 bne.n 80019b2 <HAL_RCC_OscConfig+0x48a>
|
|
|
/* Check the parameters */
|
|
|
assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
|
|
|
assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL));
|
|
|
|
|
|
/* Disable the main PLL. */
|
|
|
__HAL_RCC_PLL_DISABLE();
|
|
|
8001924: 4b33 ldr r3, [pc, #204] ; (80019f4 <HAL_RCC_OscConfig+0x4cc>)
|
|
|
8001926: 2200 movs r2, #0
|
|
|
8001928: 601a str r2, [r3, #0]
|
|
|
|
|
|
/* Get Start Tick */
|
|
|
tickstart = HAL_GetTick();
|
|
|
800192a: f7ff fb37 bl 8000f9c <HAL_GetTick>
|
|
|
800192e: 6138 str r0, [r7, #16]
|
|
|
|
|
|
/* Wait till PLL is disabled */
|
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
|
|
|
8001930: e008 b.n 8001944 <HAL_RCC_OscConfig+0x41c>
|
|
|
{
|
|
|
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
|
|
|
8001932: f7ff fb33 bl 8000f9c <HAL_GetTick>
|
|
|
8001936: 4602 mov r2, r0
|
|
|
8001938: 693b ldr r3, [r7, #16]
|
|
|
800193a: 1ad3 subs r3, r2, r3
|
|
|
800193c: 2b02 cmp r3, #2
|
|
|
800193e: d901 bls.n 8001944 <HAL_RCC_OscConfig+0x41c>
|
|
|
{
|
|
|
return HAL_TIMEOUT;
|
|
|
8001940: 2303 movs r3, #3
|
|
|
8001942: e06d b.n 8001a20 <HAL_RCC_OscConfig+0x4f8>
|
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
|
|
|
8001944: 4b29 ldr r3, [pc, #164] ; (80019ec <HAL_RCC_OscConfig+0x4c4>)
|
|
|
8001946: 681b ldr r3, [r3, #0]
|
|
|
8001948: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
|
|
|
800194c: 2b00 cmp r3, #0
|
|
|
800194e: d1f0 bne.n 8001932 <HAL_RCC_OscConfig+0x40a>
|
|
|
}
|
|
|
}
|
|
|
|
|
|
/* Configure the HSE prediv factor --------------------------------*/
|
|
|
/* It can be written only when the PLL is disabled. Not used in PLL source is different than HSE */
|
|
|
if (RCC_OscInitStruct->PLL.PLLSource == RCC_PLLSOURCE_HSE)
|
|
|
8001950: 687b ldr r3, [r7, #4]
|
|
|
8001952: 6a1b ldr r3, [r3, #32]
|
|
|
8001954: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
|
|
|
8001958: d108 bne.n 800196c <HAL_RCC_OscConfig+0x444>
|
|
|
/* Set PREDIV1 source */
|
|
|
SET_BIT(RCC->CFGR2, RCC_OscInitStruct->Prediv1Source);
|
|
|
#endif /* RCC_CFGR2_PREDIV1SRC */
|
|
|
|
|
|
/* Set PREDIV1 Value */
|
|
|
__HAL_RCC_HSE_PREDIV_CONFIG(RCC_OscInitStruct->HSEPredivValue);
|
|
|
800195a: 4b24 ldr r3, [pc, #144] ; (80019ec <HAL_RCC_OscConfig+0x4c4>)
|
|
|
800195c: 685b ldr r3, [r3, #4]
|
|
|
800195e: f423 3200 bic.w r2, r3, #131072 ; 0x20000
|
|
|
8001962: 687b ldr r3, [r7, #4]
|
|
|
8001964: 689b ldr r3, [r3, #8]
|
|
|
8001966: 4921 ldr r1, [pc, #132] ; (80019ec <HAL_RCC_OscConfig+0x4c4>)
|
|
|
8001968: 4313 orrs r3, r2
|
|
|
800196a: 604b str r3, [r1, #4]
|
|
|
}
|
|
|
|
|
|
/* Configure the main PLL clock source and multiplication factors. */
|
|
|
__HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
|
|
|
800196c: 4b1f ldr r3, [pc, #124] ; (80019ec <HAL_RCC_OscConfig+0x4c4>)
|
|
|
800196e: 685b ldr r3, [r3, #4]
|
|
|
8001970: f423 1274 bic.w r2, r3, #3997696 ; 0x3d0000
|
|
|
8001974: 687b ldr r3, [r7, #4]
|
|
|
8001976: 6a19 ldr r1, [r3, #32]
|
|
|
8001978: 687b ldr r3, [r7, #4]
|
|
|
800197a: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
|
800197c: 430b orrs r3, r1
|
|
|
800197e: 491b ldr r1, [pc, #108] ; (80019ec <HAL_RCC_OscConfig+0x4c4>)
|
|
|
8001980: 4313 orrs r3, r2
|
|
|
8001982: 604b str r3, [r1, #4]
|
|
|
RCC_OscInitStruct->PLL.PLLMUL);
|
|
|
/* Enable the main PLL. */
|
|
|
__HAL_RCC_PLL_ENABLE();
|
|
|
8001984: 4b1b ldr r3, [pc, #108] ; (80019f4 <HAL_RCC_OscConfig+0x4cc>)
|
|
|
8001986: 2201 movs r2, #1
|
|
|
8001988: 601a str r2, [r3, #0]
|
|
|
|
|
|
/* Get Start Tick */
|
|
|
tickstart = HAL_GetTick();
|
|
|
800198a: f7ff fb07 bl 8000f9c <HAL_GetTick>
|
|
|
800198e: 6138 str r0, [r7, #16]
|
|
|
|
|
|
/* Wait till PLL is ready */
|
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
|
|
|
8001990: e008 b.n 80019a4 <HAL_RCC_OscConfig+0x47c>
|
|
|
{
|
|
|
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
|
|
|
8001992: f7ff fb03 bl 8000f9c <HAL_GetTick>
|
|
|
8001996: 4602 mov r2, r0
|
|
|
8001998: 693b ldr r3, [r7, #16]
|
|
|
800199a: 1ad3 subs r3, r2, r3
|
|
|
800199c: 2b02 cmp r3, #2
|
|
|
800199e: d901 bls.n 80019a4 <HAL_RCC_OscConfig+0x47c>
|
|
|
{
|
|
|
return HAL_TIMEOUT;
|
|
|
80019a0: 2303 movs r3, #3
|
|
|
80019a2: e03d b.n 8001a20 <HAL_RCC_OscConfig+0x4f8>
|
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
|
|
|
80019a4: 4b11 ldr r3, [pc, #68] ; (80019ec <HAL_RCC_OscConfig+0x4c4>)
|
|
|
80019a6: 681b ldr r3, [r3, #0]
|
|
|
80019a8: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
|
|
|
80019ac: 2b00 cmp r3, #0
|
|
|
80019ae: d0f0 beq.n 8001992 <HAL_RCC_OscConfig+0x46a>
|
|
|
80019b0: e035 b.n 8001a1e <HAL_RCC_OscConfig+0x4f6>
|
|
|
}
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
/* Disable the main PLL. */
|
|
|
__HAL_RCC_PLL_DISABLE();
|
|
|
80019b2: 4b10 ldr r3, [pc, #64] ; (80019f4 <HAL_RCC_OscConfig+0x4cc>)
|
|
|
80019b4: 2200 movs r2, #0
|
|
|
80019b6: 601a str r2, [r3, #0]
|
|
|
|
|
|
/* Get Start Tick */
|
|
|
tickstart = HAL_GetTick();
|
|
|
80019b8: f7ff faf0 bl 8000f9c <HAL_GetTick>
|
|
|
80019bc: 6138 str r0, [r7, #16]
|
|
|
|
|
|
/* Wait till PLL is disabled */
|
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
|
|
|
80019be: e008 b.n 80019d2 <HAL_RCC_OscConfig+0x4aa>
|
|
|
{
|
|
|
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
|
|
|
80019c0: f7ff faec bl 8000f9c <HAL_GetTick>
|
|
|
80019c4: 4602 mov r2, r0
|
|
|
80019c6: 693b ldr r3, [r7, #16]
|
|
|
80019c8: 1ad3 subs r3, r2, r3
|
|
|
80019ca: 2b02 cmp r3, #2
|
|
|
80019cc: d901 bls.n 80019d2 <HAL_RCC_OscConfig+0x4aa>
|
|
|
{
|
|
|
return HAL_TIMEOUT;
|
|
|
80019ce: 2303 movs r3, #3
|
|
|
80019d0: e026 b.n 8001a20 <HAL_RCC_OscConfig+0x4f8>
|
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
|
|
|
80019d2: 4b06 ldr r3, [pc, #24] ; (80019ec <HAL_RCC_OscConfig+0x4c4>)
|
|
|
80019d4: 681b ldr r3, [r3, #0]
|
|
|
80019d6: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
|
|
|
80019da: 2b00 cmp r3, #0
|
|
|
80019dc: d1f0 bne.n 80019c0 <HAL_RCC_OscConfig+0x498>
|
|
|
80019de: e01e b.n 8001a1e <HAL_RCC_OscConfig+0x4f6>
|
|
|
}
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
/* Check if there is a request to disable the PLL used as System clock source */
|
|
|
if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
|
|
|
80019e0: 687b ldr r3, [r7, #4]
|
|
|
80019e2: 69db ldr r3, [r3, #28]
|
|
|
80019e4: 2b01 cmp r3, #1
|
|
|
80019e6: d107 bne.n 80019f8 <HAL_RCC_OscConfig+0x4d0>
|
|
|
{
|
|
|
return HAL_ERROR;
|
|
|
80019e8: 2301 movs r3, #1
|
|
|
80019ea: e019 b.n 8001a20 <HAL_RCC_OscConfig+0x4f8>
|
|
|
80019ec: 40021000 .word 0x40021000
|
|
|
80019f0: 40007000 .word 0x40007000
|
|
|
80019f4: 42420060 .word 0x42420060
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
/* Do not return HAL_ERROR if request repeats the current configuration */
|
|
|
pll_config = RCC->CFGR;
|
|
|
80019f8: 4b0b ldr r3, [pc, #44] ; (8001a28 <HAL_RCC_OscConfig+0x500>)
|
|
|
80019fa: 685b ldr r3, [r3, #4]
|
|
|
80019fc: 60fb str r3, [r7, #12]
|
|
|
if ((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
|
|
|
80019fe: 68fb ldr r3, [r7, #12]
|
|
|
8001a00: f403 3280 and.w r2, r3, #65536 ; 0x10000
|
|
|
8001a04: 687b ldr r3, [r7, #4]
|
|
|
8001a06: 6a1b ldr r3, [r3, #32]
|
|
|
8001a08: 429a cmp r2, r3
|
|
|
8001a0a: d106 bne.n 8001a1a <HAL_RCC_OscConfig+0x4f2>
|
|
|
(READ_BIT(pll_config, RCC_CFGR_PLLMULL) != RCC_OscInitStruct->PLL.PLLMUL))
|
|
|
8001a0c: 68fb ldr r3, [r7, #12]
|
|
|
8001a0e: f403 1270 and.w r2, r3, #3932160 ; 0x3c0000
|
|
|
8001a12: 687b ldr r3, [r7, #4]
|
|
|
8001a14: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
|
if ((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
|
|
|
8001a16: 429a cmp r2, r3
|
|
|
8001a18: d001 beq.n 8001a1e <HAL_RCC_OscConfig+0x4f6>
|
|
|
{
|
|
|
return HAL_ERROR;
|
|
|
8001a1a: 2301 movs r3, #1
|
|
|
8001a1c: e000 b.n 8001a20 <HAL_RCC_OscConfig+0x4f8>
|
|
|
}
|
|
|
}
|
|
|
}
|
|
|
}
|
|
|
|
|
|
return HAL_OK;
|
|
|
8001a1e: 2300 movs r3, #0
|
|
|
}
|
|
|
8001a20: 4618 mov r0, r3
|
|
|
8001a22: 3718 adds r7, #24
|
|
|
8001a24: 46bd mov sp, r7
|
|
|
8001a26: bd80 pop {r7, pc}
|
|
|
8001a28: 40021000 .word 0x40021000
|
|
|
|
|
|
08001a2c <HAL_RCC_ClockConfig>:
|
|
|
* You can use @ref HAL_RCC_GetClockConfig() function to know which clock is
|
|
|
* currently used as system clock source.
|
|
|
* @retval HAL status
|
|
|
*/
|
|
|
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
|
|
|
{
|
|
|
8001a2c: b580 push {r7, lr}
|
|
|
8001a2e: b084 sub sp, #16
|
|
|
8001a30: af00 add r7, sp, #0
|
|
|
8001a32: 6078 str r0, [r7, #4]
|
|
|
8001a34: 6039 str r1, [r7, #0]
|
|
|
uint32_t tickstart;
|
|
|
|
|
|
/* Check Null pointer */
|
|
|
if (RCC_ClkInitStruct == NULL)
|
|
|
8001a36: 687b ldr r3, [r7, #4]
|
|
|
8001a38: 2b00 cmp r3, #0
|
|
|
8001a3a: d101 bne.n 8001a40 <HAL_RCC_ClockConfig+0x14>
|
|
|
{
|
|
|
return HAL_ERROR;
|
|
|
8001a3c: 2301 movs r3, #1
|
|
|
8001a3e: e0d0 b.n 8001be2 <HAL_RCC_ClockConfig+0x1b6>
|
|
|
must be correctly programmed according to the frequency of the CPU clock
|
|
|
(HCLK) of the device. */
|
|
|
|
|
|
#if defined(FLASH_ACR_LATENCY)
|
|
|
/* Increasing the number of wait states because of higher CPU frequency */
|
|
|
if (FLatency > __HAL_FLASH_GET_LATENCY())
|
|
|
8001a40: 4b6a ldr r3, [pc, #424] ; (8001bec <HAL_RCC_ClockConfig+0x1c0>)
|
|
|
8001a42: 681b ldr r3, [r3, #0]
|
|
|
8001a44: f003 0307 and.w r3, r3, #7
|
|
|
8001a48: 683a ldr r2, [r7, #0]
|
|
|
8001a4a: 429a cmp r2, r3
|
|
|
8001a4c: d910 bls.n 8001a70 <HAL_RCC_ClockConfig+0x44>
|
|
|
{
|
|
|
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
|
|
|
__HAL_FLASH_SET_LATENCY(FLatency);
|
|
|
8001a4e: 4b67 ldr r3, [pc, #412] ; (8001bec <HAL_RCC_ClockConfig+0x1c0>)
|
|
|
8001a50: 681b ldr r3, [r3, #0]
|
|
|
8001a52: f023 0207 bic.w r2, r3, #7
|
|
|
8001a56: 4965 ldr r1, [pc, #404] ; (8001bec <HAL_RCC_ClockConfig+0x1c0>)
|
|
|
8001a58: 683b ldr r3, [r7, #0]
|
|
|
8001a5a: 4313 orrs r3, r2
|
|
|
8001a5c: 600b str r3, [r1, #0]
|
|
|
|
|
|
/* Check that the new number of wait states is taken into account to access the Flash
|
|
|
memory by reading the FLASH_ACR register */
|
|
|
if (__HAL_FLASH_GET_LATENCY() != FLatency)
|
|
|
8001a5e: 4b63 ldr r3, [pc, #396] ; (8001bec <HAL_RCC_ClockConfig+0x1c0>)
|
|
|
8001a60: 681b ldr r3, [r3, #0]
|
|
|
8001a62: f003 0307 and.w r3, r3, #7
|
|
|
8001a66: 683a ldr r2, [r7, #0]
|
|
|
8001a68: 429a cmp r2, r3
|
|
|
8001a6a: d001 beq.n 8001a70 <HAL_RCC_ClockConfig+0x44>
|
|
|
{
|
|
|
return HAL_ERROR;
|
|
|
8001a6c: 2301 movs r3, #1
|
|
|
8001a6e: e0b8 b.n 8001be2 <HAL_RCC_ClockConfig+0x1b6>
|
|
|
}
|
|
|
}
|
|
|
|
|
|
#endif /* FLASH_ACR_LATENCY */
|
|
|
/*-------------------------- HCLK Configuration --------------------------*/
|
|
|
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
|
|
|
8001a70: 687b ldr r3, [r7, #4]
|
|
|
8001a72: 681b ldr r3, [r3, #0]
|
|
|
8001a74: f003 0302 and.w r3, r3, #2
|
|
|
8001a78: 2b00 cmp r3, #0
|
|
|
8001a7a: d020 beq.n 8001abe <HAL_RCC_ClockConfig+0x92>
|
|
|
{
|
|
|
/* Set the highest APBx dividers in order to ensure that we do not go through
|
|
|
a non-spec phase whatever we decrease or increase HCLK. */
|
|
|
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
|
|
|
8001a7c: 687b ldr r3, [r7, #4]
|
|
|
8001a7e: 681b ldr r3, [r3, #0]
|
|
|
8001a80: f003 0304 and.w r3, r3, #4
|
|
|
8001a84: 2b00 cmp r3, #0
|
|
|
8001a86: d005 beq.n 8001a94 <HAL_RCC_ClockConfig+0x68>
|
|
|
{
|
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16);
|
|
|
8001a88: 4b59 ldr r3, [pc, #356] ; (8001bf0 <HAL_RCC_ClockConfig+0x1c4>)
|
|
|
8001a8a: 685b ldr r3, [r3, #4]
|
|
|
8001a8c: 4a58 ldr r2, [pc, #352] ; (8001bf0 <HAL_RCC_ClockConfig+0x1c4>)
|
|
|
8001a8e: f443 63e0 orr.w r3, r3, #1792 ; 0x700
|
|
|
8001a92: 6053 str r3, [r2, #4]
|
|
|
}
|
|
|
|
|
|
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
|
|
|
8001a94: 687b ldr r3, [r7, #4]
|
|
|
8001a96: 681b ldr r3, [r3, #0]
|
|
|
8001a98: f003 0308 and.w r3, r3, #8
|
|
|
8001a9c: 2b00 cmp r3, #0
|
|
|
8001a9e: d005 beq.n 8001aac <HAL_RCC_ClockConfig+0x80>
|
|
|
{
|
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3));
|
|
|
8001aa0: 4b53 ldr r3, [pc, #332] ; (8001bf0 <HAL_RCC_ClockConfig+0x1c4>)
|
|
|
8001aa2: 685b ldr r3, [r3, #4]
|
|
|
8001aa4: 4a52 ldr r2, [pc, #328] ; (8001bf0 <HAL_RCC_ClockConfig+0x1c4>)
|
|
|
8001aa6: f443 5360 orr.w r3, r3, #14336 ; 0x3800
|
|
|
8001aaa: 6053 str r3, [r2, #4]
|
|
|
}
|
|
|
|
|
|
/* Set the new HCLK clock divider */
|
|
|
assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
|
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
|
|
|
8001aac: 4b50 ldr r3, [pc, #320] ; (8001bf0 <HAL_RCC_ClockConfig+0x1c4>)
|
|
|
8001aae: 685b ldr r3, [r3, #4]
|
|
|
8001ab0: f023 02f0 bic.w r2, r3, #240 ; 0xf0
|
|
|
8001ab4: 687b ldr r3, [r7, #4]
|
|
|
8001ab6: 689b ldr r3, [r3, #8]
|
|
|
8001ab8: 494d ldr r1, [pc, #308] ; (8001bf0 <HAL_RCC_ClockConfig+0x1c4>)
|
|
|
8001aba: 4313 orrs r3, r2
|
|
|
8001abc: 604b str r3, [r1, #4]
|
|
|
}
|
|
|
|
|
|
/*------------------------- SYSCLK Configuration ---------------------------*/
|
|
|
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
|
|
|
8001abe: 687b ldr r3, [r7, #4]
|
|
|
8001ac0: 681b ldr r3, [r3, #0]
|
|
|
8001ac2: f003 0301 and.w r3, r3, #1
|
|
|
8001ac6: 2b00 cmp r3, #0
|
|
|
8001ac8: d040 beq.n 8001b4c <HAL_RCC_ClockConfig+0x120>
|
|
|
{
|
|
|
assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
|
|
|
|
|
|
/* HSE is selected as System Clock Source */
|
|
|
if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
|
|
|
8001aca: 687b ldr r3, [r7, #4]
|
|
|
8001acc: 685b ldr r3, [r3, #4]
|
|
|
8001ace: 2b01 cmp r3, #1
|
|
|
8001ad0: d107 bne.n 8001ae2 <HAL_RCC_ClockConfig+0xb6>
|
|
|
{
|
|
|
/* Check the HSE ready flag */
|
|
|
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
|
|
|
8001ad2: 4b47 ldr r3, [pc, #284] ; (8001bf0 <HAL_RCC_ClockConfig+0x1c4>)
|
|
|
8001ad4: 681b ldr r3, [r3, #0]
|
|
|
8001ad6: f403 3300 and.w r3, r3, #131072 ; 0x20000
|
|
|
8001ada: 2b00 cmp r3, #0
|
|
|
8001adc: d115 bne.n 8001b0a <HAL_RCC_ClockConfig+0xde>
|
|
|
{
|
|
|
return HAL_ERROR;
|
|
|
8001ade: 2301 movs r3, #1
|
|
|
8001ae0: e07f b.n 8001be2 <HAL_RCC_ClockConfig+0x1b6>
|
|
|
}
|
|
|
}
|
|
|
/* PLL is selected as System Clock Source */
|
|
|
else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
|
|
|
8001ae2: 687b ldr r3, [r7, #4]
|
|
|
8001ae4: 685b ldr r3, [r3, #4]
|
|
|
8001ae6: 2b02 cmp r3, #2
|
|
|
8001ae8: d107 bne.n 8001afa <HAL_RCC_ClockConfig+0xce>
|
|
|
{
|
|
|
/* Check the PLL ready flag */
|
|
|
if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
|
|
|
8001aea: 4b41 ldr r3, [pc, #260] ; (8001bf0 <HAL_RCC_ClockConfig+0x1c4>)
|
|
|
8001aec: 681b ldr r3, [r3, #0]
|
|
|
8001aee: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
|
|
|
8001af2: 2b00 cmp r3, #0
|
|
|
8001af4: d109 bne.n 8001b0a <HAL_RCC_ClockConfig+0xde>
|
|
|
{
|
|
|
return HAL_ERROR;
|
|
|
8001af6: 2301 movs r3, #1
|
|
|
8001af8: e073 b.n 8001be2 <HAL_RCC_ClockConfig+0x1b6>
|
|
|
}
|
|
|
/* HSI is selected as System Clock Source */
|
|
|
else
|
|
|
{
|
|
|
/* Check the HSI ready flag */
|
|
|
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
|
|
|
8001afa: 4b3d ldr r3, [pc, #244] ; (8001bf0 <HAL_RCC_ClockConfig+0x1c4>)
|
|
|
8001afc: 681b ldr r3, [r3, #0]
|
|
|
8001afe: f003 0302 and.w r3, r3, #2
|
|
|
8001b02: 2b00 cmp r3, #0
|
|
|
8001b04: d101 bne.n 8001b0a <HAL_RCC_ClockConfig+0xde>
|
|
|
{
|
|
|
return HAL_ERROR;
|
|
|
8001b06: 2301 movs r3, #1
|
|
|
8001b08: e06b b.n 8001be2 <HAL_RCC_ClockConfig+0x1b6>
|
|
|
}
|
|
|
}
|
|
|
__HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
|
|
|
8001b0a: 4b39 ldr r3, [pc, #228] ; (8001bf0 <HAL_RCC_ClockConfig+0x1c4>)
|
|
|
8001b0c: 685b ldr r3, [r3, #4]
|
|
|
8001b0e: f023 0203 bic.w r2, r3, #3
|
|
|
8001b12: 687b ldr r3, [r7, #4]
|
|
|
8001b14: 685b ldr r3, [r3, #4]
|
|
|
8001b16: 4936 ldr r1, [pc, #216] ; (8001bf0 <HAL_RCC_ClockConfig+0x1c4>)
|
|
|
8001b18: 4313 orrs r3, r2
|
|
|
8001b1a: 604b str r3, [r1, #4]
|
|
|
|
|
|
/* Get Start Tick */
|
|
|
tickstart = HAL_GetTick();
|
|
|
8001b1c: f7ff fa3e bl 8000f9c <HAL_GetTick>
|
|
|
8001b20: 60f8 str r0, [r7, #12]
|
|
|
|
|
|
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
|
|
|
8001b22: e00a b.n 8001b3a <HAL_RCC_ClockConfig+0x10e>
|
|
|
{
|
|
|
if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
|
|
|
8001b24: f7ff fa3a bl 8000f9c <HAL_GetTick>
|
|
|
8001b28: 4602 mov r2, r0
|
|
|
8001b2a: 68fb ldr r3, [r7, #12]
|
|
|
8001b2c: 1ad3 subs r3, r2, r3
|
|
|
8001b2e: f241 3288 movw r2, #5000 ; 0x1388
|
|
|
8001b32: 4293 cmp r3, r2
|
|
|
8001b34: d901 bls.n 8001b3a <HAL_RCC_ClockConfig+0x10e>
|
|
|
{
|
|
|
return HAL_TIMEOUT;
|
|
|
8001b36: 2303 movs r3, #3
|
|
|
8001b38: e053 b.n 8001be2 <HAL_RCC_ClockConfig+0x1b6>
|
|
|
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
|
|
|
8001b3a: 4b2d ldr r3, [pc, #180] ; (8001bf0 <HAL_RCC_ClockConfig+0x1c4>)
|
|
|
8001b3c: 685b ldr r3, [r3, #4]
|
|
|
8001b3e: f003 020c and.w r2, r3, #12
|
|
|
8001b42: 687b ldr r3, [r7, #4]
|
|
|
8001b44: 685b ldr r3, [r3, #4]
|
|
|
8001b46: 009b lsls r3, r3, #2
|
|
|
8001b48: 429a cmp r2, r3
|
|
|
8001b4a: d1eb bne.n 8001b24 <HAL_RCC_ClockConfig+0xf8>
|
|
|
}
|
|
|
}
|
|
|
|
|
|
#if defined(FLASH_ACR_LATENCY)
|
|
|
/* Decreasing the number of wait states because of lower CPU frequency */
|
|
|
if (FLatency < __HAL_FLASH_GET_LATENCY())
|
|
|
8001b4c: 4b27 ldr r3, [pc, #156] ; (8001bec <HAL_RCC_ClockConfig+0x1c0>)
|
|
|
8001b4e: 681b ldr r3, [r3, #0]
|
|
|
8001b50: f003 0307 and.w r3, r3, #7
|
|
|
8001b54: 683a ldr r2, [r7, #0]
|
|
|
8001b56: 429a cmp r2, r3
|
|
|
8001b58: d210 bcs.n 8001b7c <HAL_RCC_ClockConfig+0x150>
|
|
|
{
|
|
|
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
|
|
|
__HAL_FLASH_SET_LATENCY(FLatency);
|
|
|
8001b5a: 4b24 ldr r3, [pc, #144] ; (8001bec <HAL_RCC_ClockConfig+0x1c0>)
|
|
|
8001b5c: 681b ldr r3, [r3, #0]
|
|
|
8001b5e: f023 0207 bic.w r2, r3, #7
|
|
|
8001b62: 4922 ldr r1, [pc, #136] ; (8001bec <HAL_RCC_ClockConfig+0x1c0>)
|
|
|
8001b64: 683b ldr r3, [r7, #0]
|
|
|
8001b66: 4313 orrs r3, r2
|
|
|
8001b68: 600b str r3, [r1, #0]
|
|
|
|
|
|
/* Check that the new number of wait states is taken into account to access the Flash
|
|
|
memory by reading the FLASH_ACR register */
|
|
|
if (__HAL_FLASH_GET_LATENCY() != FLatency)
|
|
|
8001b6a: 4b20 ldr r3, [pc, #128] ; (8001bec <HAL_RCC_ClockConfig+0x1c0>)
|
|
|
8001b6c: 681b ldr r3, [r3, #0]
|
|
|
8001b6e: f003 0307 and.w r3, r3, #7
|
|
|
8001b72: 683a ldr r2, [r7, #0]
|
|
|
8001b74: 429a cmp r2, r3
|
|
|
8001b76: d001 beq.n 8001b7c <HAL_RCC_ClockConfig+0x150>
|
|
|
{
|
|
|
return HAL_ERROR;
|
|
|
8001b78: 2301 movs r3, #1
|
|
|
8001b7a: e032 b.n 8001be2 <HAL_RCC_ClockConfig+0x1b6>
|
|
|
}
|
|
|
}
|
|
|
#endif /* FLASH_ACR_LATENCY */
|
|
|
|
|
|
/*-------------------------- PCLK1 Configuration ---------------------------*/
|
|
|
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
|
|
|
8001b7c: 687b ldr r3, [r7, #4]
|
|
|
8001b7e: 681b ldr r3, [r3, #0]
|
|
|
8001b80: f003 0304 and.w r3, r3, #4
|
|
|
8001b84: 2b00 cmp r3, #0
|
|
|
8001b86: d008 beq.n 8001b9a <HAL_RCC_ClockConfig+0x16e>
|
|
|
{
|
|
|
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
|
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
|
|
|
8001b88: 4b19 ldr r3, [pc, #100] ; (8001bf0 <HAL_RCC_ClockConfig+0x1c4>)
|
|
|
8001b8a: 685b ldr r3, [r3, #4]
|
|
|
8001b8c: f423 62e0 bic.w r2, r3, #1792 ; 0x700
|
|
|
8001b90: 687b ldr r3, [r7, #4]
|
|
|
8001b92: 68db ldr r3, [r3, #12]
|
|
|
8001b94: 4916 ldr r1, [pc, #88] ; (8001bf0 <HAL_RCC_ClockConfig+0x1c4>)
|
|
|
8001b96: 4313 orrs r3, r2
|
|
|
8001b98: 604b str r3, [r1, #4]
|
|
|
}
|
|
|
|
|
|
/*-------------------------- PCLK2 Configuration ---------------------------*/
|
|
|
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
|
|
|
8001b9a: 687b ldr r3, [r7, #4]
|
|
|
8001b9c: 681b ldr r3, [r3, #0]
|
|
|
8001b9e: f003 0308 and.w r3, r3, #8
|
|
|
8001ba2: 2b00 cmp r3, #0
|
|
|
8001ba4: d009 beq.n 8001bba <HAL_RCC_ClockConfig+0x18e>
|
|
|
{
|
|
|
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
|
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3));
|
|
|
8001ba6: 4b12 ldr r3, [pc, #72] ; (8001bf0 <HAL_RCC_ClockConfig+0x1c4>)
|
|
|
8001ba8: 685b ldr r3, [r3, #4]
|
|
|
8001baa: f423 5260 bic.w r2, r3, #14336 ; 0x3800
|
|
|
8001bae: 687b ldr r3, [r7, #4]
|
|
|
8001bb0: 691b ldr r3, [r3, #16]
|
|
|
8001bb2: 00db lsls r3, r3, #3
|
|
|
8001bb4: 490e ldr r1, [pc, #56] ; (8001bf0 <HAL_RCC_ClockConfig+0x1c4>)
|
|
|
8001bb6: 4313 orrs r3, r2
|
|
|
8001bb8: 604b str r3, [r1, #4]
|
|
|
}
|
|
|
|
|
|
/* Update the SystemCoreClock global variable */
|
|
|
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos];
|
|
|
8001bba: f000 f821 bl 8001c00 <HAL_RCC_GetSysClockFreq>
|
|
|
8001bbe: 4602 mov r2, r0
|
|
|
8001bc0: 4b0b ldr r3, [pc, #44] ; (8001bf0 <HAL_RCC_ClockConfig+0x1c4>)
|
|
|
8001bc2: 685b ldr r3, [r3, #4]
|
|
|
8001bc4: 091b lsrs r3, r3, #4
|
|
|
8001bc6: f003 030f and.w r3, r3, #15
|
|
|
8001bca: 490a ldr r1, [pc, #40] ; (8001bf4 <HAL_RCC_ClockConfig+0x1c8>)
|
|
|
8001bcc: 5ccb ldrb r3, [r1, r3]
|
|
|
8001bce: fa22 f303 lsr.w r3, r2, r3
|
|
|
8001bd2: 4a09 ldr r2, [pc, #36] ; (8001bf8 <HAL_RCC_ClockConfig+0x1cc>)
|
|
|
8001bd4: 6013 str r3, [r2, #0]
|
|
|
|
|
|
/* Configure the source of time base considering new system clocks settings*/
|
|
|
HAL_InitTick(uwTickPrio);
|
|
|
8001bd6: 4b09 ldr r3, [pc, #36] ; (8001bfc <HAL_RCC_ClockConfig+0x1d0>)
|
|
|
8001bd8: 681b ldr r3, [r3, #0]
|
|
|
8001bda: 4618 mov r0, r3
|
|
|
8001bdc: f7ff f99c bl 8000f18 <HAL_InitTick>
|
|
|
|
|
|
return HAL_OK;
|
|
|
8001be0: 2300 movs r3, #0
|
|
|
}
|
|
|
8001be2: 4618 mov r0, r3
|
|
|
8001be4: 3710 adds r7, #16
|
|
|
8001be6: 46bd mov sp, r7
|
|
|
8001be8: bd80 pop {r7, pc}
|
|
|
8001bea: bf00 nop
|
|
|
8001bec: 40022000 .word 0x40022000
|
|
|
8001bf0: 40021000 .word 0x40021000
|
|
|
8001bf4: 08003010 .word 0x08003010
|
|
|
8001bf8: 20000000 .word 0x20000000
|
|
|
8001bfc: 20000004 .word 0x20000004
|
|
|
|
|
|
08001c00 <HAL_RCC_GetSysClockFreq>:
|
|
|
* right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
|
|
|
*
|
|
|
* @retval SYSCLK frequency
|
|
|
*/
|
|
|
uint32_t HAL_RCC_GetSysClockFreq(void)
|
|
|
{
|
|
|
8001c00: b490 push {r4, r7}
|
|
|
8001c02: b08a sub sp, #40 ; 0x28
|
|
|
8001c04: af00 add r7, sp, #0
|
|
|
#if defined(RCC_CFGR2_PREDIV1SRC)
|
|
|
const uint8_t aPLLMULFactorTable[14] = {0, 0, 4, 5, 6, 7, 8, 9, 0, 0, 0, 0, 0, 13};
|
|
|
const uint8_t aPredivFactorTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16};
|
|
|
#else
|
|
|
const uint8_t aPLLMULFactorTable[16] = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16};
|
|
|
8001c06: 4b29 ldr r3, [pc, #164] ; (8001cac <HAL_RCC_GetSysClockFreq+0xac>)
|
|
|
8001c08: 1d3c adds r4, r7, #4
|
|
|
8001c0a: cb0f ldmia r3, {r0, r1, r2, r3}
|
|
|
8001c0c: e884 000f stmia.w r4, {r0, r1, r2, r3}
|
|
|
#if defined(RCC_CFGR2_PREDIV1)
|
|
|
const uint8_t aPredivFactorTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16};
|
|
|
#else
|
|
|
const uint8_t aPredivFactorTable[2] = {1, 2};
|
|
|
8001c10: f240 2301 movw r3, #513 ; 0x201
|
|
|
8001c14: 803b strh r3, [r7, #0]
|
|
|
#endif /*RCC_CFGR2_PREDIV1*/
|
|
|
|
|
|
#endif
|
|
|
uint32_t tmpreg = 0U, prediv = 0U, pllclk = 0U, pllmul = 0U;
|
|
|
8001c16: 2300 movs r3, #0
|
|
|
8001c18: 61fb str r3, [r7, #28]
|
|
|
8001c1a: 2300 movs r3, #0
|
|
|
8001c1c: 61bb str r3, [r7, #24]
|
|
|
8001c1e: 2300 movs r3, #0
|
|
|
8001c20: 627b str r3, [r7, #36] ; 0x24
|
|
|
8001c22: 2300 movs r3, #0
|
|
|
8001c24: 617b str r3, [r7, #20]
|
|
|
uint32_t sysclockfreq = 0U;
|
|
|
8001c26: 2300 movs r3, #0
|
|
|
8001c28: 623b str r3, [r7, #32]
|
|
|
#if defined(RCC_CFGR2_PREDIV1SRC)
|
|
|
uint32_t prediv2 = 0U, pll2mul = 0U;
|
|
|
#endif /*RCC_CFGR2_PREDIV1SRC*/
|
|
|
|
|
|
tmpreg = RCC->CFGR;
|
|
|
8001c2a: 4b21 ldr r3, [pc, #132] ; (8001cb0 <HAL_RCC_GetSysClockFreq+0xb0>)
|
|
|
8001c2c: 685b ldr r3, [r3, #4]
|
|
|
8001c2e: 61fb str r3, [r7, #28]
|
|
|
|
|
|
/* Get SYSCLK source -------------------------------------------------------*/
|
|
|
switch (tmpreg & RCC_CFGR_SWS)
|
|
|
8001c30: 69fb ldr r3, [r7, #28]
|
|
|
8001c32: f003 030c and.w r3, r3, #12
|
|
|
8001c36: 2b04 cmp r3, #4
|
|
|
8001c38: d002 beq.n 8001c40 <HAL_RCC_GetSysClockFreq+0x40>
|
|
|
8001c3a: 2b08 cmp r3, #8
|
|
|
8001c3c: d003 beq.n 8001c46 <HAL_RCC_GetSysClockFreq+0x46>
|
|
|
8001c3e: e02b b.n 8001c98 <HAL_RCC_GetSysClockFreq+0x98>
|
|
|
{
|
|
|
case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */
|
|
|
{
|
|
|
sysclockfreq = HSE_VALUE;
|
|
|
8001c40: 4b1c ldr r3, [pc, #112] ; (8001cb4 <HAL_RCC_GetSysClockFreq+0xb4>)
|
|
|
8001c42: 623b str r3, [r7, #32]
|
|
|
break;
|
|
|
8001c44: e02b b.n 8001c9e <HAL_RCC_GetSysClockFreq+0x9e>
|
|
|
}
|
|
|
case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */
|
|
|
{
|
|
|
pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos];
|
|
|
8001c46: 69fb ldr r3, [r7, #28]
|
|
|
8001c48: 0c9b lsrs r3, r3, #18
|
|
|
8001c4a: f003 030f and.w r3, r3, #15
|
|
|
8001c4e: 3328 adds r3, #40 ; 0x28
|
|
|
8001c50: 443b add r3, r7
|
|
|
8001c52: f813 3c24 ldrb.w r3, [r3, #-36]
|
|
|
8001c56: 617b str r3, [r7, #20]
|
|
|
if ((tmpreg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2)
|
|
|
8001c58: 69fb ldr r3, [r7, #28]
|
|
|
8001c5a: f403 3380 and.w r3, r3, #65536 ; 0x10000
|
|
|
8001c5e: 2b00 cmp r3, #0
|
|
|
8001c60: d012 beq.n 8001c88 <HAL_RCC_GetSysClockFreq+0x88>
|
|
|
{
|
|
|
#if defined(RCC_CFGR2_PREDIV1)
|
|
|
prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> RCC_CFGR2_PREDIV1_Pos];
|
|
|
#else
|
|
|
prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos];
|
|
|
8001c62: 4b13 ldr r3, [pc, #76] ; (8001cb0 <HAL_RCC_GetSysClockFreq+0xb0>)
|
|
|
8001c64: 685b ldr r3, [r3, #4]
|
|
|
8001c66: 0c5b lsrs r3, r3, #17
|
|
|
8001c68: f003 0301 and.w r3, r3, #1
|
|
|
8001c6c: 3328 adds r3, #40 ; 0x28
|
|
|
8001c6e: 443b add r3, r7
|
|
|
8001c70: f813 3c28 ldrb.w r3, [r3, #-40]
|
|
|
8001c74: 61bb str r3, [r7, #24]
|
|
|
{
|
|
|
pllclk = pllclk / 2;
|
|
|
}
|
|
|
#else
|
|
|
/* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */
|
|
|
pllclk = (uint32_t)((HSE_VALUE * pllmul) / prediv);
|
|
|
8001c76: 697b ldr r3, [r7, #20]
|
|
|
8001c78: 4a0e ldr r2, [pc, #56] ; (8001cb4 <HAL_RCC_GetSysClockFreq+0xb4>)
|
|
|
8001c7a: fb03 f202 mul.w r2, r3, r2
|
|
|
8001c7e: 69bb ldr r3, [r7, #24]
|
|
|
8001c80: fbb2 f3f3 udiv r3, r2, r3
|
|
|
8001c84: 627b str r3, [r7, #36] ; 0x24
|
|
|
8001c86: e004 b.n 8001c92 <HAL_RCC_GetSysClockFreq+0x92>
|
|
|
#endif /*RCC_CFGR2_PREDIV1SRC*/
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
/* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */
|
|
|
pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul);
|
|
|
8001c88: 697b ldr r3, [r7, #20]
|
|
|
8001c8a: 4a0b ldr r2, [pc, #44] ; (8001cb8 <HAL_RCC_GetSysClockFreq+0xb8>)
|
|
|
8001c8c: fb02 f303 mul.w r3, r2, r3
|
|
|
8001c90: 627b str r3, [r7, #36] ; 0x24
|
|
|
}
|
|
|
sysclockfreq = pllclk;
|
|
|
8001c92: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
|
8001c94: 623b str r3, [r7, #32]
|
|
|
break;
|
|
|
8001c96: e002 b.n 8001c9e <HAL_RCC_GetSysClockFreq+0x9e>
|
|
|
}
|
|
|
case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
|
|
|
default: /* HSI used as system clock */
|
|
|
{
|
|
|
sysclockfreq = HSI_VALUE;
|
|
|
8001c98: 4b06 ldr r3, [pc, #24] ; (8001cb4 <HAL_RCC_GetSysClockFreq+0xb4>)
|
|
|
8001c9a: 623b str r3, [r7, #32]
|
|
|
break;
|
|
|
8001c9c: bf00 nop
|
|
|
}
|
|
|
}
|
|
|
return sysclockfreq;
|
|
|
8001c9e: 6a3b ldr r3, [r7, #32]
|
|
|
}
|
|
|
8001ca0: 4618 mov r0, r3
|
|
|
8001ca2: 3728 adds r7, #40 ; 0x28
|
|
|
8001ca4: 46bd mov sp, r7
|
|
|
8001ca6: bc90 pop {r4, r7}
|
|
|
8001ca8: 4770 bx lr
|
|
|
8001caa: bf00 nop
|
|
|
8001cac: 08003000 .word 0x08003000
|
|
|
8001cb0: 40021000 .word 0x40021000
|
|
|
8001cb4: 007a1200 .word 0x007a1200
|
|
|
8001cb8: 003d0900 .word 0x003d0900
|
|
|
|
|
|
08001cbc <HAL_RCC_GetHCLKFreq>:
|
|
|
* @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
|
|
|
* and updated within this function
|
|
|
* @retval HCLK frequency
|
|
|
*/
|
|
|
uint32_t HAL_RCC_GetHCLKFreq(void)
|
|
|
{
|
|
|
8001cbc: b480 push {r7}
|
|
|
8001cbe: af00 add r7, sp, #0
|
|
|
return SystemCoreClock;
|
|
|
8001cc0: 4b02 ldr r3, [pc, #8] ; (8001ccc <HAL_RCC_GetHCLKFreq+0x10>)
|
|
|
8001cc2: 681b ldr r3, [r3, #0]
|
|
|
}
|
|
|
8001cc4: 4618 mov r0, r3
|
|
|
8001cc6: 46bd mov sp, r7
|
|
|
8001cc8: bc80 pop {r7}
|
|
|
8001cca: 4770 bx lr
|
|
|
8001ccc: 20000000 .word 0x20000000
|
|
|
|
|
|
08001cd0 <HAL_RCC_GetPCLK1Freq>:
|
|
|
* @note Each time PCLK1 changes, this function must be called to update the
|
|
|
* right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
|
|
|
* @retval PCLK1 frequency
|
|
|
*/
|
|
|
uint32_t HAL_RCC_GetPCLK1Freq(void)
|
|
|
{
|
|
|
8001cd0: b580 push {r7, lr}
|
|
|
8001cd2: af00 add r7, sp, #0
|
|
|
/* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
|
|
|
return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]);
|
|
|
8001cd4: f7ff fff2 bl 8001cbc <HAL_RCC_GetHCLKFreq>
|
|
|
8001cd8: 4602 mov r2, r0
|
|
|
8001cda: 4b05 ldr r3, [pc, #20] ; (8001cf0 <HAL_RCC_GetPCLK1Freq+0x20>)
|
|
|
8001cdc: 685b ldr r3, [r3, #4]
|
|
|
8001cde: 0a1b lsrs r3, r3, #8
|
|
|
8001ce0: f003 0307 and.w r3, r3, #7
|
|
|
8001ce4: 4903 ldr r1, [pc, #12] ; (8001cf4 <HAL_RCC_GetPCLK1Freq+0x24>)
|
|
|
8001ce6: 5ccb ldrb r3, [r1, r3]
|
|
|
8001ce8: fa22 f303 lsr.w r3, r2, r3
|
|
|
}
|
|
|
8001cec: 4618 mov r0, r3
|
|
|
8001cee: bd80 pop {r7, pc}
|
|
|
8001cf0: 40021000 .word 0x40021000
|
|
|
8001cf4: 08003020 .word 0x08003020
|
|
|
|
|
|
08001cf8 <HAL_RCC_GetPCLK2Freq>:
|
|
|
* @note Each time PCLK2 changes, this function must be called to update the
|
|
|
* right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
|
|
|
* @retval PCLK2 frequency
|
|
|
*/
|
|
|
uint32_t HAL_RCC_GetPCLK2Freq(void)
|
|
|
{
|
|
|
8001cf8: b580 push {r7, lr}
|
|
|
8001cfa: af00 add r7, sp, #0
|
|
|
/* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
|
|
|
return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]);
|
|
|
8001cfc: f7ff ffde bl 8001cbc <HAL_RCC_GetHCLKFreq>
|
|
|
8001d00: 4602 mov r2, r0
|
|
|
8001d02: 4b05 ldr r3, [pc, #20] ; (8001d18 <HAL_RCC_GetPCLK2Freq+0x20>)
|
|
|
8001d04: 685b ldr r3, [r3, #4]
|
|
|
8001d06: 0adb lsrs r3, r3, #11
|
|
|
8001d08: f003 0307 and.w r3, r3, #7
|
|
|
8001d0c: 4903 ldr r1, [pc, #12] ; (8001d1c <HAL_RCC_GetPCLK2Freq+0x24>)
|
|
|
8001d0e: 5ccb ldrb r3, [r1, r3]
|
|
|
8001d10: fa22 f303 lsr.w r3, r2, r3
|
|
|
}
|
|
|
8001d14: 4618 mov r0, r3
|
|
|
8001d16: bd80 pop {r7, pc}
|
|
|
8001d18: 40021000 .word 0x40021000
|
|
|
8001d1c: 08003020 .word 0x08003020
|
|
|
|
|
|
08001d20 <RCC_Delay>:
|
|
|
* @brief This function provides delay (in milliseconds) based on CPU cycles method.
|
|
|
* @param mdelay: specifies the delay time length, in milliseconds.
|
|
|
* @retval None
|
|
|
*/
|
|
|
static void RCC_Delay(uint32_t mdelay)
|
|
|
{
|
|
|
8001d20: b480 push {r7}
|
|
|
8001d22: b085 sub sp, #20
|
|
|
8001d24: af00 add r7, sp, #0
|
|
|
8001d26: 6078 str r0, [r7, #4]
|
|
|
__IO uint32_t Delay = mdelay * (SystemCoreClock / 8U / 1000U);
|
|
|
8001d28: 4b0a ldr r3, [pc, #40] ; (8001d54 <RCC_Delay+0x34>)
|
|
|
8001d2a: 681b ldr r3, [r3, #0]
|
|
|
8001d2c: 4a0a ldr r2, [pc, #40] ; (8001d58 <RCC_Delay+0x38>)
|
|
|
8001d2e: fba2 2303 umull r2, r3, r2, r3
|
|
|
8001d32: 0a5b lsrs r3, r3, #9
|
|
|
8001d34: 687a ldr r2, [r7, #4]
|
|
|
8001d36: fb02 f303 mul.w r3, r2, r3
|
|
|
8001d3a: 60fb str r3, [r7, #12]
|
|
|
do
|
|
|
{
|
|
|
__NOP();
|
|
|
8001d3c: bf00 nop
|
|
|
}
|
|
|
while (Delay --);
|
|
|
8001d3e: 68fb ldr r3, [r7, #12]
|
|
|
8001d40: 1e5a subs r2, r3, #1
|
|
|
8001d42: 60fa str r2, [r7, #12]
|
|
|
8001d44: 2b00 cmp r3, #0
|
|
|
8001d46: d1f9 bne.n 8001d3c <RCC_Delay+0x1c>
|
|
|
}
|
|
|
8001d48: bf00 nop
|
|
|
8001d4a: bf00 nop
|
|
|
8001d4c: 3714 adds r7, #20
|
|
|
8001d4e: 46bd mov sp, r7
|
|
|
8001d50: bc80 pop {r7}
|
|
|
8001d52: 4770 bx lr
|
|
|
8001d54: 20000000 .word 0x20000000
|
|
|
8001d58: 10624dd3 .word 0x10624dd3
|
|
|
|
|
|
08001d5c <HAL_TIM_Base_Init>:
|
|
|
* Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
|
|
|
* @param htim TIM Base handle
|
|
|
* @retval HAL status
|
|
|
*/
|
|
|
HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
|
|
|
{
|
|
|
8001d5c: b580 push {r7, lr}
|
|
|
8001d5e: b082 sub sp, #8
|
|
|
8001d60: af00 add r7, sp, #0
|
|
|
8001d62: 6078 str r0, [r7, #4]
|
|
|
/* Check the TIM handle allocation */
|
|
|
if (htim == NULL)
|
|
|
8001d64: 687b ldr r3, [r7, #4]
|
|
|
8001d66: 2b00 cmp r3, #0
|
|
|
8001d68: d101 bne.n 8001d6e <HAL_TIM_Base_Init+0x12>
|
|
|
{
|
|
|
return HAL_ERROR;
|
|
|
8001d6a: 2301 movs r3, #1
|
|
|
8001d6c: e041 b.n 8001df2 <HAL_TIM_Base_Init+0x96>
|
|
|
assert_param(IS_TIM_INSTANCE(htim->Instance));
|
|
|
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
|
|
|
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
|
|
|
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
|
|
|
|
|
|
if (htim->State == HAL_TIM_STATE_RESET)
|
|
|
8001d6e: 687b ldr r3, [r7, #4]
|
|
|
8001d70: f893 303d ldrb.w r3, [r3, #61] ; 0x3d
|
|
|
8001d74: b2db uxtb r3, r3
|
|
|
8001d76: 2b00 cmp r3, #0
|
|
|
8001d78: d106 bne.n 8001d88 <HAL_TIM_Base_Init+0x2c>
|
|
|
{
|
|
|
/* Allocate lock resource and initialize it */
|
|
|
htim->Lock = HAL_UNLOCKED;
|
|
|
8001d7a: 687b ldr r3, [r7, #4]
|
|
|
8001d7c: 2200 movs r2, #0
|
|
|
8001d7e: f883 203c strb.w r2, [r3, #60] ; 0x3c
|
|
|
}
|
|
|
/* Init the low level hardware : GPIO, CLOCK, NVIC */
|
|
|
htim->Base_MspInitCallback(htim);
|
|
|
#else
|
|
|
/* Init the low level hardware : GPIO, CLOCK, NVIC */
|
|
|
HAL_TIM_Base_MspInit(htim);
|
|
|
8001d82: 6878 ldr r0, [r7, #4]
|
|
|
8001d84: f7fe fffa bl 8000d7c <HAL_TIM_Base_MspInit>
|
|
|
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
|
|
|
}
|
|
|
|
|
|
/* Set the TIM state */
|
|
|
htim->State = HAL_TIM_STATE_BUSY;
|
|
|
8001d88: 687b ldr r3, [r7, #4]
|
|
|
8001d8a: 2202 movs r2, #2
|
|
|
8001d8c: f883 203d strb.w r2, [r3, #61] ; 0x3d
|
|
|
|
|
|
/* Set the Time Base configuration */
|
|
|
TIM_Base_SetConfig(htim->Instance, &htim->Init);
|
|
|
8001d90: 687b ldr r3, [r7, #4]
|
|
|
8001d92: 681a ldr r2, [r3, #0]
|
|
|
8001d94: 687b ldr r3, [r7, #4]
|
|
|
8001d96: 3304 adds r3, #4
|
|
|
8001d98: 4619 mov r1, r3
|
|
|
8001d9a: 4610 mov r0, r2
|
|
|
8001d9c: f000 f962 bl 8002064 <TIM_Base_SetConfig>
|
|
|
|
|
|
/* Initialize the DMA burst operation state */
|
|
|
htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
|
|
|
8001da0: 687b ldr r3, [r7, #4]
|
|
|
8001da2: 2201 movs r2, #1
|
|
|
8001da4: f883 2046 strb.w r2, [r3, #70] ; 0x46
|
|
|
|
|
|
/* Initialize the TIM channels state */
|
|
|
TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
|
|
|
8001da8: 687b ldr r3, [r7, #4]
|
|
|
8001daa: 2201 movs r2, #1
|
|
|
8001dac: f883 203e strb.w r2, [r3, #62] ; 0x3e
|
|
|
8001db0: 687b ldr r3, [r7, #4]
|
|
|
8001db2: 2201 movs r2, #1
|
|
|
8001db4: f883 203f strb.w r2, [r3, #63] ; 0x3f
|
|
|
8001db8: 687b ldr r3, [r7, #4]
|
|
|
8001dba: 2201 movs r2, #1
|
|
|
8001dbc: f883 2040 strb.w r2, [r3, #64] ; 0x40
|
|
|
8001dc0: 687b ldr r3, [r7, #4]
|
|
|
8001dc2: 2201 movs r2, #1
|
|
|
8001dc4: f883 2041 strb.w r2, [r3, #65] ; 0x41
|
|
|
TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
|
|
|
8001dc8: 687b ldr r3, [r7, #4]
|
|
|
8001dca: 2201 movs r2, #1
|
|
|
8001dcc: f883 2042 strb.w r2, [r3, #66] ; 0x42
|
|
|
8001dd0: 687b ldr r3, [r7, #4]
|
|
|
8001dd2: 2201 movs r2, #1
|
|
|
8001dd4: f883 2043 strb.w r2, [r3, #67] ; 0x43
|
|
|
8001dd8: 687b ldr r3, [r7, #4]
|
|
|
8001dda: 2201 movs r2, #1
|
|
|
8001ddc: f883 2044 strb.w r2, [r3, #68] ; 0x44
|
|
|
8001de0: 687b ldr r3, [r7, #4]
|
|
|
8001de2: 2201 movs r2, #1
|
|
|
8001de4: f883 2045 strb.w r2, [r3, #69] ; 0x45
|
|
|
|
|
|
/* Initialize the TIM state*/
|
|
|
htim->State = HAL_TIM_STATE_READY;
|
|
|
8001de8: 687b ldr r3, [r7, #4]
|
|
|
8001dea: 2201 movs r2, #1
|
|
|
8001dec: f883 203d strb.w r2, [r3, #61] ; 0x3d
|
|
|
|
|
|
return HAL_OK;
|
|
|
8001df0: 2300 movs r3, #0
|
|
|
}
|
|
|
8001df2: 4618 mov r0, r3
|
|
|
8001df4: 3708 adds r7, #8
|
|
|
8001df6: 46bd mov sp, r7
|
|
|
8001df8: bd80 pop {r7, pc}
|
|
|
...
|
|
|
|
|
|
08001dfc <HAL_TIM_Base_Start>:
|
|
|
* @brief Starts the TIM Base generation.
|
|
|
* @param htim TIM Base handle
|
|
|
* @retval HAL status
|
|
|
*/
|
|
|
HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
|
|
|
{
|
|
|
8001dfc: b480 push {r7}
|
|
|
8001dfe: b085 sub sp, #20
|
|
|
8001e00: af00 add r7, sp, #0
|
|
|
8001e02: 6078 str r0, [r7, #4]
|
|
|
|
|
|
/* Check the parameters */
|
|
|
assert_param(IS_TIM_INSTANCE(htim->Instance));
|
|
|
|
|
|
/* Check the TIM state */
|
|
|
if (htim->State != HAL_TIM_STATE_READY)
|
|
|
8001e04: 687b ldr r3, [r7, #4]
|
|
|
8001e06: f893 303d ldrb.w r3, [r3, #61] ; 0x3d
|
|
|
8001e0a: b2db uxtb r3, r3
|
|
|
8001e0c: 2b01 cmp r3, #1
|
|
|
8001e0e: d001 beq.n 8001e14 <HAL_TIM_Base_Start+0x18>
|
|
|
{
|
|
|
return HAL_ERROR;
|
|
|
8001e10: 2301 movs r3, #1
|
|
|
8001e12: e032 b.n 8001e7a <HAL_TIM_Base_Start+0x7e>
|
|
|
}
|
|
|
|
|
|
/* Set the TIM state */
|
|
|
htim->State = HAL_TIM_STATE_BUSY;
|
|
|
8001e14: 687b ldr r3, [r7, #4]
|
|
|
8001e16: 2202 movs r2, #2
|
|
|
8001e18: f883 203d strb.w r2, [r3, #61] ; 0x3d
|
|
|
|
|
|
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
|
|
|
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
|
|
|
8001e1c: 687b ldr r3, [r7, #4]
|
|
|
8001e1e: 681b ldr r3, [r3, #0]
|
|
|
8001e20: 4a18 ldr r2, [pc, #96] ; (8001e84 <HAL_TIM_Base_Start+0x88>)
|
|
|
8001e22: 4293 cmp r3, r2
|
|
|
8001e24: d00e beq.n 8001e44 <HAL_TIM_Base_Start+0x48>
|
|
|
8001e26: 687b ldr r3, [r7, #4]
|
|
|
8001e28: 681b ldr r3, [r3, #0]
|
|
|
8001e2a: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
|
|
|
8001e2e: d009 beq.n 8001e44 <HAL_TIM_Base_Start+0x48>
|
|
|
8001e30: 687b ldr r3, [r7, #4]
|
|
|
8001e32: 681b ldr r3, [r3, #0]
|
|
|
8001e34: 4a14 ldr r2, [pc, #80] ; (8001e88 <HAL_TIM_Base_Start+0x8c>)
|
|
|
8001e36: 4293 cmp r3, r2
|
|
|
8001e38: d004 beq.n 8001e44 <HAL_TIM_Base_Start+0x48>
|
|
|
8001e3a: 687b ldr r3, [r7, #4]
|
|
|
8001e3c: 681b ldr r3, [r3, #0]
|
|
|
8001e3e: 4a13 ldr r2, [pc, #76] ; (8001e8c <HAL_TIM_Base_Start+0x90>)
|
|
|
8001e40: 4293 cmp r3, r2
|
|
|
8001e42: d111 bne.n 8001e68 <HAL_TIM_Base_Start+0x6c>
|
|
|
{
|
|
|
tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
|
|
|
8001e44: 687b ldr r3, [r7, #4]
|
|
|
8001e46: 681b ldr r3, [r3, #0]
|
|
|
8001e48: 689b ldr r3, [r3, #8]
|
|
|
8001e4a: f003 0307 and.w r3, r3, #7
|
|
|
8001e4e: 60fb str r3, [r7, #12]
|
|
|
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
|
|
|
8001e50: 68fb ldr r3, [r7, #12]
|
|
|
8001e52: 2b06 cmp r3, #6
|
|
|
8001e54: d010 beq.n 8001e78 <HAL_TIM_Base_Start+0x7c>
|
|
|
{
|
|
|
__HAL_TIM_ENABLE(htim);
|
|
|
8001e56: 687b ldr r3, [r7, #4]
|
|
|
8001e58: 681b ldr r3, [r3, #0]
|
|
|
8001e5a: 681a ldr r2, [r3, #0]
|
|
|
8001e5c: 687b ldr r3, [r7, #4]
|
|
|
8001e5e: 681b ldr r3, [r3, #0]
|
|
|
8001e60: f042 0201 orr.w r2, r2, #1
|
|
|
8001e64: 601a str r2, [r3, #0]
|
|
|
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
|
|
|
8001e66: e007 b.n 8001e78 <HAL_TIM_Base_Start+0x7c>
|
|
|
}
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
__HAL_TIM_ENABLE(htim);
|
|
|
8001e68: 687b ldr r3, [r7, #4]
|
|
|
8001e6a: 681b ldr r3, [r3, #0]
|
|
|
8001e6c: 681a ldr r2, [r3, #0]
|
|
|
8001e6e: 687b ldr r3, [r7, #4]
|
|
|
8001e70: 681b ldr r3, [r3, #0]
|
|
|
8001e72: f042 0201 orr.w r2, r2, #1
|
|
|
8001e76: 601a str r2, [r3, #0]
|
|
|
}
|
|
|
|
|
|
/* Return function status */
|
|
|
return HAL_OK;
|
|
|
8001e78: 2300 movs r3, #0
|
|
|
}
|
|
|
8001e7a: 4618 mov r0, r3
|
|
|
8001e7c: 3714 adds r7, #20
|
|
|
8001e7e: 46bd mov sp, r7
|
|
|
8001e80: bc80 pop {r7}
|
|
|
8001e82: 4770 bx lr
|
|
|
8001e84: 40012c00 .word 0x40012c00
|
|
|
8001e88: 40000400 .word 0x40000400
|
|
|
8001e8c: 40000800 .word 0x40000800
|
|
|
|
|
|
08001e90 <HAL_TIM_Base_Stop>:
|
|
|
* @brief Stops the TIM Base generation.
|
|
|
* @param htim TIM Base handle
|
|
|
* @retval HAL status
|
|
|
*/
|
|
|
HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
|
|
|
{
|
|
|
8001e90: b480 push {r7}
|
|
|
8001e92: b083 sub sp, #12
|
|
|
8001e94: af00 add r7, sp, #0
|
|
|
8001e96: 6078 str r0, [r7, #4]
|
|
|
/* Check the parameters */
|
|
|
assert_param(IS_TIM_INSTANCE(htim->Instance));
|
|
|
|
|
|
/* Disable the Peripheral */
|
|
|
__HAL_TIM_DISABLE(htim);
|
|
|
8001e98: 687b ldr r3, [r7, #4]
|
|
|
8001e9a: 681b ldr r3, [r3, #0]
|
|
|
8001e9c: 6a1a ldr r2, [r3, #32]
|
|
|
8001e9e: f241 1311 movw r3, #4369 ; 0x1111
|
|
|
8001ea2: 4013 ands r3, r2
|
|
|
8001ea4: 2b00 cmp r3, #0
|
|
|
8001ea6: d10f bne.n 8001ec8 <HAL_TIM_Base_Stop+0x38>
|
|
|
8001ea8: 687b ldr r3, [r7, #4]
|
|
|
8001eaa: 681b ldr r3, [r3, #0]
|
|
|
8001eac: 6a1a ldr r2, [r3, #32]
|
|
|
8001eae: f240 4344 movw r3, #1092 ; 0x444
|
|
|
8001eb2: 4013 ands r3, r2
|
|
|
8001eb4: 2b00 cmp r3, #0
|
|
|
8001eb6: d107 bne.n 8001ec8 <HAL_TIM_Base_Stop+0x38>
|
|
|
8001eb8: 687b ldr r3, [r7, #4]
|
|
|
8001eba: 681b ldr r3, [r3, #0]
|
|
|
8001ebc: 681a ldr r2, [r3, #0]
|
|
|
8001ebe: 687b ldr r3, [r7, #4]
|
|
|
8001ec0: 681b ldr r3, [r3, #0]
|
|
|
8001ec2: f022 0201 bic.w r2, r2, #1
|
|
|
8001ec6: 601a str r2, [r3, #0]
|
|
|
|
|
|
/* Set the TIM state */
|
|
|
htim->State = HAL_TIM_STATE_READY;
|
|
|
8001ec8: 687b ldr r3, [r7, #4]
|
|
|
8001eca: 2201 movs r2, #1
|
|
|
8001ecc: f883 203d strb.w r2, [r3, #61] ; 0x3d
|
|
|
|
|
|
/* Return function status */
|
|
|
return HAL_OK;
|
|
|
8001ed0: 2300 movs r3, #0
|
|
|
}
|
|
|
8001ed2: 4618 mov r0, r3
|
|
|
8001ed4: 370c adds r7, #12
|
|
|
8001ed6: 46bd mov sp, r7
|
|
|
8001ed8: bc80 pop {r7}
|
|
|
8001eda: 4770 bx lr
|
|
|
|
|
|
08001edc <HAL_TIM_ConfigClockSource>:
|
|
|
* @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that
|
|
|
* contains the clock source information for the TIM peripheral.
|
|
|
* @retval HAL status
|
|
|
*/
|
|
|
HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig)
|
|
|
{
|
|
|
8001edc: b580 push {r7, lr}
|
|
|
8001ede: b084 sub sp, #16
|
|
|
8001ee0: af00 add r7, sp, #0
|
|
|
8001ee2: 6078 str r0, [r7, #4]
|
|
|
8001ee4: 6039 str r1, [r7, #0]
|
|
|
uint32_t tmpsmcr;
|
|
|
|
|
|
/* Process Locked */
|
|
|
__HAL_LOCK(htim);
|
|
|
8001ee6: 687b ldr r3, [r7, #4]
|
|
|
8001ee8: f893 303c ldrb.w r3, [r3, #60] ; 0x3c
|
|
|
8001eec: 2b01 cmp r3, #1
|
|
|
8001eee: d101 bne.n 8001ef4 <HAL_TIM_ConfigClockSource+0x18>
|
|
|
8001ef0: 2302 movs r3, #2
|
|
|
8001ef2: e0b3 b.n 800205c <HAL_TIM_ConfigClockSource+0x180>
|
|
|
8001ef4: 687b ldr r3, [r7, #4]
|
|
|
8001ef6: 2201 movs r2, #1
|
|
|
8001ef8: f883 203c strb.w r2, [r3, #60] ; 0x3c
|
|
|
|
|
|
htim->State = HAL_TIM_STATE_BUSY;
|
|
|
8001efc: 687b ldr r3, [r7, #4]
|
|
|
8001efe: 2202 movs r2, #2
|
|
|
8001f00: f883 203d strb.w r2, [r3, #61] ; 0x3d
|
|
|
|
|
|
/* Check the parameters */
|
|
|
assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
|
|
|
|
|
|
/* Reset the SMS, TS, ECE, ETPS and ETRF bits */
|
|
|
tmpsmcr = htim->Instance->SMCR;
|
|
|
8001f04: 687b ldr r3, [r7, #4]
|
|
|
8001f06: 681b ldr r3, [r3, #0]
|
|
|
8001f08: 689b ldr r3, [r3, #8]
|
|
|
8001f0a: 60fb str r3, [r7, #12]
|
|
|
tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
|
|
|
8001f0c: 68fb ldr r3, [r7, #12]
|
|
|
8001f0e: f023 0377 bic.w r3, r3, #119 ; 0x77
|
|
|
8001f12: 60fb str r3, [r7, #12]
|
|
|
tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
|
|
|
8001f14: 68fb ldr r3, [r7, #12]
|
|
|
8001f16: f423 437f bic.w r3, r3, #65280 ; 0xff00
|
|
|
8001f1a: 60fb str r3, [r7, #12]
|
|
|
htim->Instance->SMCR = tmpsmcr;
|
|
|
8001f1c: 687b ldr r3, [r7, #4]
|
|
|
8001f1e: 681b ldr r3, [r3, #0]
|
|
|
8001f20: 68fa ldr r2, [r7, #12]
|
|
|
8001f22: 609a str r2, [r3, #8]
|
|
|
|
|
|
switch (sClockSourceConfig->ClockSource)
|
|
|
8001f24: 683b ldr r3, [r7, #0]
|
|
|
8001f26: 681b ldr r3, [r3, #0]
|
|
|
8001f28: f5b3 5f00 cmp.w r3, #8192 ; 0x2000
|
|
|
8001f2c: d03e beq.n 8001fac <HAL_TIM_ConfigClockSource+0xd0>
|
|
|
8001f2e: f5b3 5f00 cmp.w r3, #8192 ; 0x2000
|
|
|
8001f32: f200 8087 bhi.w 8002044 <HAL_TIM_ConfigClockSource+0x168>
|
|
|
8001f36: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
|
|
|
8001f3a: f000 8085 beq.w 8002048 <HAL_TIM_ConfigClockSource+0x16c>
|
|
|
8001f3e: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
|
|
|
8001f42: d87f bhi.n 8002044 <HAL_TIM_ConfigClockSource+0x168>
|
|
|
8001f44: 2b70 cmp r3, #112 ; 0x70
|
|
|
8001f46: d01a beq.n 8001f7e <HAL_TIM_ConfigClockSource+0xa2>
|
|
|
8001f48: 2b70 cmp r3, #112 ; 0x70
|
|
|
8001f4a: d87b bhi.n 8002044 <HAL_TIM_ConfigClockSource+0x168>
|
|
|
8001f4c: 2b60 cmp r3, #96 ; 0x60
|
|
|
8001f4e: d050 beq.n 8001ff2 <HAL_TIM_ConfigClockSource+0x116>
|
|
|
8001f50: 2b60 cmp r3, #96 ; 0x60
|
|
|
8001f52: d877 bhi.n 8002044 <HAL_TIM_ConfigClockSource+0x168>
|
|
|
8001f54: 2b50 cmp r3, #80 ; 0x50
|
|
|
8001f56: d03c beq.n 8001fd2 <HAL_TIM_ConfigClockSource+0xf6>
|
|
|
8001f58: 2b50 cmp r3, #80 ; 0x50
|
|
|
8001f5a: d873 bhi.n 8002044 <HAL_TIM_ConfigClockSource+0x168>
|
|
|
8001f5c: 2b40 cmp r3, #64 ; 0x40
|
|
|
8001f5e: d058 beq.n 8002012 <HAL_TIM_ConfigClockSource+0x136>
|
|
|
8001f60: 2b40 cmp r3, #64 ; 0x40
|
|
|
8001f62: d86f bhi.n 8002044 <HAL_TIM_ConfigClockSource+0x168>
|
|
|
8001f64: 2b30 cmp r3, #48 ; 0x30
|
|
|
8001f66: d064 beq.n 8002032 <HAL_TIM_ConfigClockSource+0x156>
|
|
|
8001f68: 2b30 cmp r3, #48 ; 0x30
|
|
|
8001f6a: d86b bhi.n 8002044 <HAL_TIM_ConfigClockSource+0x168>
|
|
|
8001f6c: 2b20 cmp r3, #32
|
|
|
8001f6e: d060 beq.n 8002032 <HAL_TIM_ConfigClockSource+0x156>
|
|
|
8001f70: 2b20 cmp r3, #32
|
|
|
8001f72: d867 bhi.n 8002044 <HAL_TIM_ConfigClockSource+0x168>
|
|
|
8001f74: 2b00 cmp r3, #0
|
|
|
8001f76: d05c beq.n 8002032 <HAL_TIM_ConfigClockSource+0x156>
|
|
|
8001f78: 2b10 cmp r3, #16
|
|
|
8001f7a: d05a beq.n 8002032 <HAL_TIM_ConfigClockSource+0x156>
|
|
|
TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
|
|
|
break;
|
|
|
}
|
|
|
|
|
|
default:
|
|
|
break;
|
|
|
8001f7c: e062 b.n 8002044 <HAL_TIM_ConfigClockSource+0x168>
|
|
|
TIM_ETR_SetConfig(htim->Instance,
|
|
|
8001f7e: 687b ldr r3, [r7, #4]
|
|
|
8001f80: 6818 ldr r0, [r3, #0]
|
|
|
8001f82: 683b ldr r3, [r7, #0]
|
|
|
8001f84: 6899 ldr r1, [r3, #8]
|
|
|
8001f86: 683b ldr r3, [r7, #0]
|
|
|
8001f88: 685a ldr r2, [r3, #4]
|
|
|
8001f8a: 683b ldr r3, [r7, #0]
|
|
|
8001f8c: 68db ldr r3, [r3, #12]
|
|
|
8001f8e: f000 f942 bl 8002216 <TIM_ETR_SetConfig>
|
|
|
tmpsmcr = htim->Instance->SMCR;
|
|
|
8001f92: 687b ldr r3, [r7, #4]
|
|
|
8001f94: 681b ldr r3, [r3, #0]
|
|
|
8001f96: 689b ldr r3, [r3, #8]
|
|
|
8001f98: 60fb str r3, [r7, #12]
|
|
|
tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
|
|
|
8001f9a: 68fb ldr r3, [r7, #12]
|
|
|
8001f9c: f043 0377 orr.w r3, r3, #119 ; 0x77
|
|
|
8001fa0: 60fb str r3, [r7, #12]
|
|
|
htim->Instance->SMCR = tmpsmcr;
|
|
|
8001fa2: 687b ldr r3, [r7, #4]
|
|
|
8001fa4: 681b ldr r3, [r3, #0]
|
|
|
8001fa6: 68fa ldr r2, [r7, #12]
|
|
|
8001fa8: 609a str r2, [r3, #8]
|
|
|
break;
|
|
|
8001faa: e04e b.n 800204a <HAL_TIM_ConfigClockSource+0x16e>
|
|
|
TIM_ETR_SetConfig(htim->Instance,
|
|
|
8001fac: 687b ldr r3, [r7, #4]
|
|
|
8001fae: 6818 ldr r0, [r3, #0]
|
|
|
8001fb0: 683b ldr r3, [r7, #0]
|
|
|
8001fb2: 6899 ldr r1, [r3, #8]
|
|
|
8001fb4: 683b ldr r3, [r7, #0]
|
|
|
8001fb6: 685a ldr r2, [r3, #4]
|
|
|
8001fb8: 683b ldr r3, [r7, #0]
|
|
|
8001fba: 68db ldr r3, [r3, #12]
|
|
|
8001fbc: f000 f92b bl 8002216 <TIM_ETR_SetConfig>
|
|
|
htim->Instance->SMCR |= TIM_SMCR_ECE;
|
|
|
8001fc0: 687b ldr r3, [r7, #4]
|
|
|
8001fc2: 681b ldr r3, [r3, #0]
|
|
|
8001fc4: 689a ldr r2, [r3, #8]
|
|
|
8001fc6: 687b ldr r3, [r7, #4]
|
|
|
8001fc8: 681b ldr r3, [r3, #0]
|
|
|
8001fca: f442 4280 orr.w r2, r2, #16384 ; 0x4000
|
|
|
8001fce: 609a str r2, [r3, #8]
|
|
|
break;
|
|
|
8001fd0: e03b b.n 800204a <HAL_TIM_ConfigClockSource+0x16e>
|
|
|
TIM_TI1_ConfigInputStage(htim->Instance,
|
|
|
8001fd2: 687b ldr r3, [r7, #4]
|
|
|
8001fd4: 6818 ldr r0, [r3, #0]
|
|
|
8001fd6: 683b ldr r3, [r7, #0]
|
|
|
8001fd8: 6859 ldr r1, [r3, #4]
|
|
|
8001fda: 683b ldr r3, [r7, #0]
|
|
|
8001fdc: 68db ldr r3, [r3, #12]
|
|
|
8001fde: 461a mov r2, r3
|
|
|
8001fe0: f000 f8a2 bl 8002128 <TIM_TI1_ConfigInputStage>
|
|
|
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
|
|
|
8001fe4: 687b ldr r3, [r7, #4]
|
|
|
8001fe6: 681b ldr r3, [r3, #0]
|
|
|
8001fe8: 2150 movs r1, #80 ; 0x50
|
|
|
8001fea: 4618 mov r0, r3
|
|
|
8001fec: f000 f8f9 bl 80021e2 <TIM_ITRx_SetConfig>
|
|
|
break;
|
|
|
8001ff0: e02b b.n 800204a <HAL_TIM_ConfigClockSource+0x16e>
|
|
|
TIM_TI2_ConfigInputStage(htim->Instance,
|
|
|
8001ff2: 687b ldr r3, [r7, #4]
|
|
|
8001ff4: 6818 ldr r0, [r3, #0]
|
|
|
8001ff6: 683b ldr r3, [r7, #0]
|
|
|
8001ff8: 6859 ldr r1, [r3, #4]
|
|
|
8001ffa: 683b ldr r3, [r7, #0]
|
|
|
8001ffc: 68db ldr r3, [r3, #12]
|
|
|
8001ffe: 461a mov r2, r3
|
|
|
8002000: f000 f8c0 bl 8002184 <TIM_TI2_ConfigInputStage>
|
|
|
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
|
|
|
8002004: 687b ldr r3, [r7, #4]
|
|
|
8002006: 681b ldr r3, [r3, #0]
|
|
|
8002008: 2160 movs r1, #96 ; 0x60
|
|
|
800200a: 4618 mov r0, r3
|
|
|
800200c: f000 f8e9 bl 80021e2 <TIM_ITRx_SetConfig>
|
|
|
break;
|
|
|
8002010: e01b b.n 800204a <HAL_TIM_ConfigClockSource+0x16e>
|
|
|
TIM_TI1_ConfigInputStage(htim->Instance,
|
|
|
8002012: 687b ldr r3, [r7, #4]
|
|
|
8002014: 6818 ldr r0, [r3, #0]
|
|
|
8002016: 683b ldr r3, [r7, #0]
|
|
|
8002018: 6859 ldr r1, [r3, #4]
|
|
|
800201a: 683b ldr r3, [r7, #0]
|
|
|
800201c: 68db ldr r3, [r3, #12]
|
|
|
800201e: 461a mov r2, r3
|
|
|
8002020: f000 f882 bl 8002128 <TIM_TI1_ConfigInputStage>
|
|
|
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
|
|
|
8002024: 687b ldr r3, [r7, #4]
|
|
|
8002026: 681b ldr r3, [r3, #0]
|
|
|
8002028: 2140 movs r1, #64 ; 0x40
|
|
|
800202a: 4618 mov r0, r3
|
|
|
800202c: f000 f8d9 bl 80021e2 <TIM_ITRx_SetConfig>
|
|
|
break;
|
|
|
8002030: e00b b.n 800204a <HAL_TIM_ConfigClockSource+0x16e>
|
|
|
TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
|
|
|
8002032: 687b ldr r3, [r7, #4]
|
|
|
8002034: 681a ldr r2, [r3, #0]
|
|
|
8002036: 683b ldr r3, [r7, #0]
|
|
|
8002038: 681b ldr r3, [r3, #0]
|
|
|
800203a: 4619 mov r1, r3
|
|
|
800203c: 4610 mov r0, r2
|
|
|
800203e: f000 f8d0 bl 80021e2 <TIM_ITRx_SetConfig>
|
|
|
break;
|
|
|
8002042: e002 b.n 800204a <HAL_TIM_ConfigClockSource+0x16e>
|
|
|
break;
|
|
|
8002044: bf00 nop
|
|
|
8002046: e000 b.n 800204a <HAL_TIM_ConfigClockSource+0x16e>
|
|
|
break;
|
|
|
8002048: bf00 nop
|
|
|
}
|
|
|
htim->State = HAL_TIM_STATE_READY;
|
|
|
800204a: 687b ldr r3, [r7, #4]
|
|
|
800204c: 2201 movs r2, #1
|
|
|
800204e: f883 203d strb.w r2, [r3, #61] ; 0x3d
|
|
|
|
|
|
__HAL_UNLOCK(htim);
|
|
|
8002052: 687b ldr r3, [r7, #4]
|
|
|
8002054: 2200 movs r2, #0
|
|
|
8002056: f883 203c strb.w r2, [r3, #60] ; 0x3c
|
|
|
|
|
|
return HAL_OK;
|
|
|
800205a: 2300 movs r3, #0
|
|
|
}
|
|
|
800205c: 4618 mov r0, r3
|
|
|
800205e: 3710 adds r7, #16
|
|
|
8002060: 46bd mov sp, r7
|
|
|
8002062: bd80 pop {r7, pc}
|
|
|
|
|
|
08002064 <TIM_Base_SetConfig>:
|
|
|
* @param TIMx TIM peripheral
|
|
|
* @param Structure TIM Base configuration structure
|
|
|
* @retval None
|
|
|
*/
|
|
|
void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
|
|
|
{
|
|
|
8002064: b480 push {r7}
|
|
|
8002066: b085 sub sp, #20
|
|
|
8002068: af00 add r7, sp, #0
|
|
|
800206a: 6078 str r0, [r7, #4]
|
|
|
800206c: 6039 str r1, [r7, #0]
|
|
|
uint32_t tmpcr1;
|
|
|
tmpcr1 = TIMx->CR1;
|
|
|
800206e: 687b ldr r3, [r7, #4]
|
|
|
8002070: 681b ldr r3, [r3, #0]
|
|
|
8002072: 60fb str r3, [r7, #12]
|
|
|
|
|
|
/* Set TIM Time Base Unit parameters ---------------------------------------*/
|
|
|
if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
|
|
|
8002074: 687b ldr r3, [r7, #4]
|
|
|
8002076: 4a29 ldr r2, [pc, #164] ; (800211c <TIM_Base_SetConfig+0xb8>)
|
|
|
8002078: 4293 cmp r3, r2
|
|
|
800207a: d00b beq.n 8002094 <TIM_Base_SetConfig+0x30>
|
|
|
800207c: 687b ldr r3, [r7, #4]
|
|
|
800207e: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
|
|
|
8002082: d007 beq.n 8002094 <TIM_Base_SetConfig+0x30>
|
|
|
8002084: 687b ldr r3, [r7, #4]
|
|
|
8002086: 4a26 ldr r2, [pc, #152] ; (8002120 <TIM_Base_SetConfig+0xbc>)
|
|
|
8002088: 4293 cmp r3, r2
|
|
|
800208a: d003 beq.n 8002094 <TIM_Base_SetConfig+0x30>
|
|
|
800208c: 687b ldr r3, [r7, #4]
|
|
|
800208e: 4a25 ldr r2, [pc, #148] ; (8002124 <TIM_Base_SetConfig+0xc0>)
|
|
|
8002090: 4293 cmp r3, r2
|
|
|
8002092: d108 bne.n 80020a6 <TIM_Base_SetConfig+0x42>
|
|
|
{
|
|
|
/* Select the Counter Mode */
|
|
|
tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
|
|
|
8002094: 68fb ldr r3, [r7, #12]
|
|
|
8002096: f023 0370 bic.w r3, r3, #112 ; 0x70
|
|
|
800209a: 60fb str r3, [r7, #12]
|
|
|
tmpcr1 |= Structure->CounterMode;
|
|
|
800209c: 683b ldr r3, [r7, #0]
|
|
|
800209e: 685b ldr r3, [r3, #4]
|
|
|
80020a0: 68fa ldr r2, [r7, #12]
|
|
|
80020a2: 4313 orrs r3, r2
|
|
|
80020a4: 60fb str r3, [r7, #12]
|
|
|
}
|
|
|
|
|
|
if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
|
|
|
80020a6: 687b ldr r3, [r7, #4]
|
|
|
80020a8: 4a1c ldr r2, [pc, #112] ; (800211c <TIM_Base_SetConfig+0xb8>)
|
|
|
80020aa: 4293 cmp r3, r2
|
|
|
80020ac: d00b beq.n 80020c6 <TIM_Base_SetConfig+0x62>
|
|
|
80020ae: 687b ldr r3, [r7, #4]
|
|
|
80020b0: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
|
|
|
80020b4: d007 beq.n 80020c6 <TIM_Base_SetConfig+0x62>
|
|
|
80020b6: 687b ldr r3, [r7, #4]
|
|
|
80020b8: 4a19 ldr r2, [pc, #100] ; (8002120 <TIM_Base_SetConfig+0xbc>)
|
|
|
80020ba: 4293 cmp r3, r2
|
|
|
80020bc: d003 beq.n 80020c6 <TIM_Base_SetConfig+0x62>
|
|
|
80020be: 687b ldr r3, [r7, #4]
|
|
|
80020c0: 4a18 ldr r2, [pc, #96] ; (8002124 <TIM_Base_SetConfig+0xc0>)
|
|
|
80020c2: 4293 cmp r3, r2
|
|
|
80020c4: d108 bne.n 80020d8 <TIM_Base_SetConfig+0x74>
|
|
|
{
|
|
|
/* Set the clock division */
|
|
|
tmpcr1 &= ~TIM_CR1_CKD;
|
|
|
80020c6: 68fb ldr r3, [r7, #12]
|
|
|
80020c8: f423 7340 bic.w r3, r3, #768 ; 0x300
|
|
|
80020cc: 60fb str r3, [r7, #12]
|
|
|
tmpcr1 |= (uint32_t)Structure->ClockDivision;
|
|
|
80020ce: 683b ldr r3, [r7, #0]
|
|
|
80020d0: 68db ldr r3, [r3, #12]
|
|
|
80020d2: 68fa ldr r2, [r7, #12]
|
|
|
80020d4: 4313 orrs r3, r2
|
|
|
80020d6: 60fb str r3, [r7, #12]
|
|
|
}
|
|
|
|
|
|
/* Set the auto-reload preload */
|
|
|
MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
|
|
|
80020d8: 68fb ldr r3, [r7, #12]
|
|
|
80020da: f023 0280 bic.w r2, r3, #128 ; 0x80
|
|
|
80020de: 683b ldr r3, [r7, #0]
|
|
|
80020e0: 695b ldr r3, [r3, #20]
|
|
|
80020e2: 4313 orrs r3, r2
|
|
|
80020e4: 60fb str r3, [r7, #12]
|
|
|
|
|
|
TIMx->CR1 = tmpcr1;
|
|
|
80020e6: 687b ldr r3, [r7, #4]
|
|
|
80020e8: 68fa ldr r2, [r7, #12]
|
|
|
80020ea: 601a str r2, [r3, #0]
|
|
|
|
|
|
/* Set the Autoreload value */
|
|
|
TIMx->ARR = (uint32_t)Structure->Period ;
|
|
|
80020ec: 683b ldr r3, [r7, #0]
|
|
|
80020ee: 689a ldr r2, [r3, #8]
|
|
|
80020f0: 687b ldr r3, [r7, #4]
|
|
|
80020f2: 62da str r2, [r3, #44] ; 0x2c
|
|
|
|
|
|
/* Set the Prescaler value */
|
|
|
TIMx->PSC = Structure->Prescaler;
|
|
|
80020f4: 683b ldr r3, [r7, #0]
|
|
|
80020f6: 681a ldr r2, [r3, #0]
|
|
|
80020f8: 687b ldr r3, [r7, #4]
|
|
|
80020fa: 629a str r2, [r3, #40] ; 0x28
|
|
|
|
|
|
if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
|
|
|
80020fc: 687b ldr r3, [r7, #4]
|
|
|
80020fe: 4a07 ldr r2, [pc, #28] ; (800211c <TIM_Base_SetConfig+0xb8>)
|
|
|
8002100: 4293 cmp r3, r2
|
|
|
8002102: d103 bne.n 800210c <TIM_Base_SetConfig+0xa8>
|
|
|
{
|
|
|
/* Set the Repetition Counter value */
|
|
|
TIMx->RCR = Structure->RepetitionCounter;
|
|
|
8002104: 683b ldr r3, [r7, #0]
|
|
|
8002106: 691a ldr r2, [r3, #16]
|
|
|
8002108: 687b ldr r3, [r7, #4]
|
|
|
800210a: 631a str r2, [r3, #48] ; 0x30
|
|
|
}
|
|
|
|
|
|
/* Generate an update event to reload the Prescaler
|
|
|
and the repetition counter (only for advanced timer) value immediately */
|
|
|
TIMx->EGR = TIM_EGR_UG;
|
|
|
800210c: 687b ldr r3, [r7, #4]
|
|
|
800210e: 2201 movs r2, #1
|
|
|
8002110: 615a str r2, [r3, #20]
|
|
|
}
|
|
|
8002112: bf00 nop
|
|
|
8002114: 3714 adds r7, #20
|
|
|
8002116: 46bd mov sp, r7
|
|
|
8002118: bc80 pop {r7}
|
|
|
800211a: 4770 bx lr
|
|
|
800211c: 40012c00 .word 0x40012c00
|
|
|
8002120: 40000400 .word 0x40000400
|
|
|
8002124: 40000800 .word 0x40000800
|
|
|
|
|
|
08002128 <TIM_TI1_ConfigInputStage>:
|
|
|
* @param TIM_ICFilter Specifies the Input Capture Filter.
|
|
|
* This parameter must be a value between 0x00 and 0x0F.
|
|
|
* @retval None
|
|
|
*/
|
|
|
static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
|
|
|
{
|
|
|
8002128: b480 push {r7}
|
|
|
800212a: b087 sub sp, #28
|
|
|
800212c: af00 add r7, sp, #0
|
|
|
800212e: 60f8 str r0, [r7, #12]
|
|
|
8002130: 60b9 str r1, [r7, #8]
|
|
|
8002132: 607a str r2, [r7, #4]
|
|
|
uint32_t tmpccmr1;
|
|
|
uint32_t tmpccer;
|
|
|
|
|
|
/* Disable the Channel 1: Reset the CC1E Bit */
|
|
|
tmpccer = TIMx->CCER;
|
|
|
8002134: 68fb ldr r3, [r7, #12]
|
|
|
8002136: 6a1b ldr r3, [r3, #32]
|
|
|
8002138: 617b str r3, [r7, #20]
|
|
|
TIMx->CCER &= ~TIM_CCER_CC1E;
|
|
|
800213a: 68fb ldr r3, [r7, #12]
|
|
|
800213c: 6a1b ldr r3, [r3, #32]
|
|
|
800213e: f023 0201 bic.w r2, r3, #1
|
|
|
8002142: 68fb ldr r3, [r7, #12]
|
|
|
8002144: 621a str r2, [r3, #32]
|
|
|
tmpccmr1 = TIMx->CCMR1;
|
|
|
8002146: 68fb ldr r3, [r7, #12]
|
|
|
8002148: 699b ldr r3, [r3, #24]
|
|
|
800214a: 613b str r3, [r7, #16]
|
|
|
|
|
|
/* Set the filter */
|
|
|
tmpccmr1 &= ~TIM_CCMR1_IC1F;
|
|
|
800214c: 693b ldr r3, [r7, #16]
|
|
|
800214e: f023 03f0 bic.w r3, r3, #240 ; 0xf0
|
|
|
8002152: 613b str r3, [r7, #16]
|
|
|
tmpccmr1 |= (TIM_ICFilter << 4U);
|
|
|
8002154: 687b ldr r3, [r7, #4]
|
|
|
8002156: 011b lsls r3, r3, #4
|
|
|
8002158: 693a ldr r2, [r7, #16]
|
|
|
800215a: 4313 orrs r3, r2
|
|
|
800215c: 613b str r3, [r7, #16]
|
|
|
|
|
|
/* Select the Polarity and set the CC1E Bit */
|
|
|
tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
|
|
|
800215e: 697b ldr r3, [r7, #20]
|
|
|
8002160: f023 030a bic.w r3, r3, #10
|
|
|
8002164: 617b str r3, [r7, #20]
|
|
|
tmpccer |= TIM_ICPolarity;
|
|
|
8002166: 697a ldr r2, [r7, #20]
|
|
|
8002168: 68bb ldr r3, [r7, #8]
|
|
|
800216a: 4313 orrs r3, r2
|
|
|
800216c: 617b str r3, [r7, #20]
|
|
|
|
|
|
/* Write to TIMx CCMR1 and CCER registers */
|
|
|
TIMx->CCMR1 = tmpccmr1;
|
|
|
800216e: 68fb ldr r3, [r7, #12]
|
|
|
8002170: 693a ldr r2, [r7, #16]
|
|
|
8002172: 619a str r2, [r3, #24]
|
|
|
TIMx->CCER = tmpccer;
|
|
|
8002174: 68fb ldr r3, [r7, #12]
|
|
|
8002176: 697a ldr r2, [r7, #20]
|
|
|
8002178: 621a str r2, [r3, #32]
|
|
|
}
|
|
|
800217a: bf00 nop
|
|
|
800217c: 371c adds r7, #28
|
|
|
800217e: 46bd mov sp, r7
|
|
|
8002180: bc80 pop {r7}
|
|
|
8002182: 4770 bx lr
|
|
|
|
|
|
08002184 <TIM_TI2_ConfigInputStage>:
|
|
|
* @param TIM_ICFilter Specifies the Input Capture Filter.
|
|
|
* This parameter must be a value between 0x00 and 0x0F.
|
|
|
* @retval None
|
|
|
*/
|
|
|
static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
|
|
|
{
|
|
|
8002184: b480 push {r7}
|
|
|
8002186: b087 sub sp, #28
|
|
|
8002188: af00 add r7, sp, #0
|
|
|
800218a: 60f8 str r0, [r7, #12]
|
|
|
800218c: 60b9 str r1, [r7, #8]
|
|
|
800218e: 607a str r2, [r7, #4]
|
|
|
uint32_t tmpccmr1;
|
|
|
uint32_t tmpccer;
|
|
|
|
|
|
/* Disable the Channel 2: Reset the CC2E Bit */
|
|
|
TIMx->CCER &= ~TIM_CCER_CC2E;
|
|
|
8002190: 68fb ldr r3, [r7, #12]
|
|
|
8002192: 6a1b ldr r3, [r3, #32]
|
|
|
8002194: f023 0210 bic.w r2, r3, #16
|
|
|
8002198: 68fb ldr r3, [r7, #12]
|
|
|
800219a: 621a str r2, [r3, #32]
|
|
|
tmpccmr1 = TIMx->CCMR1;
|
|
|
800219c: 68fb ldr r3, [r7, #12]
|
|
|
800219e: 699b ldr r3, [r3, #24]
|
|
|
80021a0: 617b str r3, [r7, #20]
|
|
|
tmpccer = TIMx->CCER;
|
|
|
80021a2: 68fb ldr r3, [r7, #12]
|
|
|
80021a4: 6a1b ldr r3, [r3, #32]
|
|
|
80021a6: 613b str r3, [r7, #16]
|
|
|
|
|
|
/* Set the filter */
|
|
|
tmpccmr1 &= ~TIM_CCMR1_IC2F;
|
|
|
80021a8: 697b ldr r3, [r7, #20]
|
|
|
80021aa: f423 4370 bic.w r3, r3, #61440 ; 0xf000
|
|
|
80021ae: 617b str r3, [r7, #20]
|
|
|
tmpccmr1 |= (TIM_ICFilter << 12U);
|
|
|
80021b0: 687b ldr r3, [r7, #4]
|
|
|
80021b2: 031b lsls r3, r3, #12
|
|
|
80021b4: 697a ldr r2, [r7, #20]
|
|
|
80021b6: 4313 orrs r3, r2
|
|
|
80021b8: 617b str r3, [r7, #20]
|
|
|
|
|
|
/* Select the Polarity and set the CC2E Bit */
|
|
|
tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
|
|
|
80021ba: 693b ldr r3, [r7, #16]
|
|
|
80021bc: f023 03a0 bic.w r3, r3, #160 ; 0xa0
|
|
|
80021c0: 613b str r3, [r7, #16]
|
|
|
tmpccer |= (TIM_ICPolarity << 4U);
|
|
|
80021c2: 68bb ldr r3, [r7, #8]
|
|
|
80021c4: 011b lsls r3, r3, #4
|
|
|
80021c6: 693a ldr r2, [r7, #16]
|
|
|
80021c8: 4313 orrs r3, r2
|
|
|
80021ca: 613b str r3, [r7, #16]
|
|
|
|
|
|
/* Write to TIMx CCMR1 and CCER registers */
|
|
|
TIMx->CCMR1 = tmpccmr1 ;
|
|
|
80021cc: 68fb ldr r3, [r7, #12]
|
|
|
80021ce: 697a ldr r2, [r7, #20]
|
|
|
80021d0: 619a str r2, [r3, #24]
|
|
|
TIMx->CCER = tmpccer;
|
|
|
80021d2: 68fb ldr r3, [r7, #12]
|
|
|
80021d4: 693a ldr r2, [r7, #16]
|
|
|
80021d6: 621a str r2, [r3, #32]
|
|
|
}
|
|
|
80021d8: bf00 nop
|
|
|
80021da: 371c adds r7, #28
|
|
|
80021dc: 46bd mov sp, r7
|
|
|
80021de: bc80 pop {r7}
|
|
|
80021e0: 4770 bx lr
|
|
|
|
|
|
080021e2 <TIM_ITRx_SetConfig>:
|
|
|
* @arg TIM_TS_TI2FP2: Filtered Timer Input 2
|
|
|
* @arg TIM_TS_ETRF: External Trigger input
|
|
|
* @retval None
|
|
|
*/
|
|
|
static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource)
|
|
|
{
|
|
|
80021e2: b480 push {r7}
|
|
|
80021e4: b085 sub sp, #20
|
|
|
80021e6: af00 add r7, sp, #0
|
|
|
80021e8: 6078 str r0, [r7, #4]
|
|
|
80021ea: 6039 str r1, [r7, #0]
|
|
|
uint32_t tmpsmcr;
|
|
|
|
|
|
/* Get the TIMx SMCR register value */
|
|
|
tmpsmcr = TIMx->SMCR;
|
|
|
80021ec: 687b ldr r3, [r7, #4]
|
|
|
80021ee: 689b ldr r3, [r3, #8]
|
|
|
80021f0: 60fb str r3, [r7, #12]
|
|
|
/* Reset the TS Bits */
|
|
|
tmpsmcr &= ~TIM_SMCR_TS;
|
|
|
80021f2: 68fb ldr r3, [r7, #12]
|
|
|
80021f4: f023 0370 bic.w r3, r3, #112 ; 0x70
|
|
|
80021f8: 60fb str r3, [r7, #12]
|
|
|
/* Set the Input Trigger source and the slave mode*/
|
|
|
tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1);
|
|
|
80021fa: 683a ldr r2, [r7, #0]
|
|
|
80021fc: 68fb ldr r3, [r7, #12]
|
|
|
80021fe: 4313 orrs r3, r2
|
|
|
8002200: f043 0307 orr.w r3, r3, #7
|
|
|
8002204: 60fb str r3, [r7, #12]
|
|
|
/* Write to TIMx SMCR */
|
|
|
TIMx->SMCR = tmpsmcr;
|
|
|
8002206: 687b ldr r3, [r7, #4]
|
|
|
8002208: 68fa ldr r2, [r7, #12]
|
|
|
800220a: 609a str r2, [r3, #8]
|
|
|
}
|
|
|
800220c: bf00 nop
|
|
|
800220e: 3714 adds r7, #20
|
|
|
8002210: 46bd mov sp, r7
|
|
|
8002212: bc80 pop {r7}
|
|
|
8002214: 4770 bx lr
|
|
|
|
|
|
08002216 <TIM_ETR_SetConfig>:
|
|
|
* This parameter must be a value between 0x00 and 0x0F
|
|
|
* @retval None
|
|
|
*/
|
|
|
void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
|
|
|
uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
|
|
|
{
|
|
|
8002216: b480 push {r7}
|
|
|
8002218: b087 sub sp, #28
|
|
|
800221a: af00 add r7, sp, #0
|
|
|
800221c: 60f8 str r0, [r7, #12]
|
|
|
800221e: 60b9 str r1, [r7, #8]
|
|
|
8002220: 607a str r2, [r7, #4]
|
|
|
8002222: 603b str r3, [r7, #0]
|
|
|
uint32_t tmpsmcr;
|
|
|
|
|
|
tmpsmcr = TIMx->SMCR;
|
|
|
8002224: 68fb ldr r3, [r7, #12]
|
|
|
8002226: 689b ldr r3, [r3, #8]
|
|
|
8002228: 617b str r3, [r7, #20]
|
|
|
|
|
|
/* Reset the ETR Bits */
|
|
|
tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
|
|
|
800222a: 697b ldr r3, [r7, #20]
|
|
|
800222c: f423 437f bic.w r3, r3, #65280 ; 0xff00
|
|
|
8002230: 617b str r3, [r7, #20]
|
|
|
|
|
|
/* Set the Prescaler, the Filter value and the Polarity */
|
|
|
tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));
|
|
|
8002232: 683b ldr r3, [r7, #0]
|
|
|
8002234: 021a lsls r2, r3, #8
|
|
|
8002236: 687b ldr r3, [r7, #4]
|
|
|
8002238: 431a orrs r2, r3
|
|
|
800223a: 68bb ldr r3, [r7, #8]
|
|
|
800223c: 4313 orrs r3, r2
|
|
|
800223e: 697a ldr r2, [r7, #20]
|
|
|
8002240: 4313 orrs r3, r2
|
|
|
8002242: 617b str r3, [r7, #20]
|
|
|
|
|
|
/* Write to TIMx SMCR */
|
|
|
TIMx->SMCR = tmpsmcr;
|
|
|
8002244: 68fb ldr r3, [r7, #12]
|
|
|
8002246: 697a ldr r2, [r7, #20]
|
|
|
8002248: 609a str r2, [r3, #8]
|
|
|
}
|
|
|
800224a: bf00 nop
|
|
|
800224c: 371c adds r7, #28
|
|
|
800224e: 46bd mov sp, r7
|
|
|
8002250: bc80 pop {r7}
|
|
|
8002252: 4770 bx lr
|
|
|
|
|
|
08002254 <HAL_TIMEx_MasterConfigSynchronization>:
|
|
|
* mode.
|
|
|
* @retval HAL status
|
|
|
*/
|
|
|
HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
|
|
|
TIM_MasterConfigTypeDef *sMasterConfig)
|
|
|
{
|
|
|
8002254: b480 push {r7}
|
|
|
8002256: b085 sub sp, #20
|
|
|
8002258: af00 add r7, sp, #0
|
|
|
800225a: 6078 str r0, [r7, #4]
|
|
|
800225c: 6039 str r1, [r7, #0]
|
|
|
assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
|
|
|
assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
|
|
|
assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
|
|
|
|
|
|
/* Check input state */
|
|
|
__HAL_LOCK(htim);
|
|
|
800225e: 687b ldr r3, [r7, #4]
|
|
|
8002260: f893 303c ldrb.w r3, [r3, #60] ; 0x3c
|
|
|
8002264: 2b01 cmp r3, #1
|
|
|
8002266: d101 bne.n 800226c <HAL_TIMEx_MasterConfigSynchronization+0x18>
|
|
|
8002268: 2302 movs r3, #2
|
|
|
800226a: e046 b.n 80022fa <HAL_TIMEx_MasterConfigSynchronization+0xa6>
|
|
|
800226c: 687b ldr r3, [r7, #4]
|
|
|
800226e: 2201 movs r2, #1
|
|
|
8002270: f883 203c strb.w r2, [r3, #60] ; 0x3c
|
|
|
|
|
|
/* Change the handler state */
|
|
|
htim->State = HAL_TIM_STATE_BUSY;
|
|
|
8002274: 687b ldr r3, [r7, #4]
|
|
|
8002276: 2202 movs r2, #2
|
|
|
8002278: f883 203d strb.w r2, [r3, #61] ; 0x3d
|
|
|
|
|
|
/* Get the TIMx CR2 register value */
|
|
|
tmpcr2 = htim->Instance->CR2;
|
|
|
800227c: 687b ldr r3, [r7, #4]
|
|
|
800227e: 681b ldr r3, [r3, #0]
|
|
|
8002280: 685b ldr r3, [r3, #4]
|
|
|
8002282: 60fb str r3, [r7, #12]
|
|
|
|
|
|
/* Get the TIMx SMCR register value */
|
|
|
tmpsmcr = htim->Instance->SMCR;
|
|
|
8002284: 687b ldr r3, [r7, #4]
|
|
|
8002286: 681b ldr r3, [r3, #0]
|
|
|
8002288: 689b ldr r3, [r3, #8]
|
|
|
800228a: 60bb str r3, [r7, #8]
|
|
|
|
|
|
/* Reset the MMS Bits */
|
|
|
tmpcr2 &= ~TIM_CR2_MMS;
|
|
|
800228c: 68fb ldr r3, [r7, #12]
|
|
|
800228e: f023 0370 bic.w r3, r3, #112 ; 0x70
|
|
|
8002292: 60fb str r3, [r7, #12]
|
|
|
/* Select the TRGO source */
|
|
|
tmpcr2 |= sMasterConfig->MasterOutputTrigger;
|
|
|
8002294: 683b ldr r3, [r7, #0]
|
|
|
8002296: 681b ldr r3, [r3, #0]
|
|
|
8002298: 68fa ldr r2, [r7, #12]
|
|
|
800229a: 4313 orrs r3, r2
|
|
|
800229c: 60fb str r3, [r7, #12]
|
|
|
|
|
|
/* Update TIMx CR2 */
|
|
|
htim->Instance->CR2 = tmpcr2;
|
|
|
800229e: 687b ldr r3, [r7, #4]
|
|
|
80022a0: 681b ldr r3, [r3, #0]
|
|
|
80022a2: 68fa ldr r2, [r7, #12]
|
|
|
80022a4: 605a str r2, [r3, #4]
|
|
|
|
|
|
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
|
|
|
80022a6: 687b ldr r3, [r7, #4]
|
|
|
80022a8: 681b ldr r3, [r3, #0]
|
|
|
80022aa: 4a16 ldr r2, [pc, #88] ; (8002304 <HAL_TIMEx_MasterConfigSynchronization+0xb0>)
|
|
|
80022ac: 4293 cmp r3, r2
|
|
|
80022ae: d00e beq.n 80022ce <HAL_TIMEx_MasterConfigSynchronization+0x7a>
|
|
|
80022b0: 687b ldr r3, [r7, #4]
|
|
|
80022b2: 681b ldr r3, [r3, #0]
|
|
|
80022b4: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
|
|
|
80022b8: d009 beq.n 80022ce <HAL_TIMEx_MasterConfigSynchronization+0x7a>
|
|
|
80022ba: 687b ldr r3, [r7, #4]
|
|
|
80022bc: 681b ldr r3, [r3, #0]
|
|
|
80022be: 4a12 ldr r2, [pc, #72] ; (8002308 <HAL_TIMEx_MasterConfigSynchronization+0xb4>)
|
|
|
80022c0: 4293 cmp r3, r2
|
|
|
80022c2: d004 beq.n 80022ce <HAL_TIMEx_MasterConfigSynchronization+0x7a>
|
|
|
80022c4: 687b ldr r3, [r7, #4]
|
|
|
80022c6: 681b ldr r3, [r3, #0]
|
|
|
80022c8: 4a10 ldr r2, [pc, #64] ; (800230c <HAL_TIMEx_MasterConfigSynchronization+0xb8>)
|
|
|
80022ca: 4293 cmp r3, r2
|
|
|
80022cc: d10c bne.n 80022e8 <HAL_TIMEx_MasterConfigSynchronization+0x94>
|
|
|
{
|
|
|
/* Reset the MSM Bit */
|
|
|
tmpsmcr &= ~TIM_SMCR_MSM;
|
|
|
80022ce: 68bb ldr r3, [r7, #8]
|
|
|
80022d0: f023 0380 bic.w r3, r3, #128 ; 0x80
|
|
|
80022d4: 60bb str r3, [r7, #8]
|
|
|
/* Set master mode */
|
|
|
tmpsmcr |= sMasterConfig->MasterSlaveMode;
|
|
|
80022d6: 683b ldr r3, [r7, #0]
|
|
|
80022d8: 685b ldr r3, [r3, #4]
|
|
|
80022da: 68ba ldr r2, [r7, #8]
|
|
|
80022dc: 4313 orrs r3, r2
|
|
|
80022de: 60bb str r3, [r7, #8]
|
|
|
|
|
|
/* Update TIMx SMCR */
|
|
|
htim->Instance->SMCR = tmpsmcr;
|
|
|
80022e0: 687b ldr r3, [r7, #4]
|
|
|
80022e2: 681b ldr r3, [r3, #0]
|
|
|
80022e4: 68ba ldr r2, [r7, #8]
|
|
|
80022e6: 609a str r2, [r3, #8]
|
|
|
}
|
|
|
|
|
|
/* Change the htim state */
|
|
|
htim->State = HAL_TIM_STATE_READY;
|
|
|
80022e8: 687b ldr r3, [r7, #4]
|
|
|
80022ea: 2201 movs r2, #1
|
|
|
80022ec: f883 203d strb.w r2, [r3, #61] ; 0x3d
|
|
|
|
|
|
__HAL_UNLOCK(htim);
|
|
|
80022f0: 687b ldr r3, [r7, #4]
|
|
|
80022f2: 2200 movs r2, #0
|
|
|
80022f4: f883 203c strb.w r2, [r3, #60] ; 0x3c
|
|
|
|
|
|
return HAL_OK;
|
|
|
80022f8: 2300 movs r3, #0
|
|
|
}
|
|
|
80022fa: 4618 mov r0, r3
|
|
|
80022fc: 3714 adds r7, #20
|
|
|
80022fe: 46bd mov sp, r7
|
|
|
8002300: bc80 pop {r7}
|
|
|
8002302: 4770 bx lr
|
|
|
8002304: 40012c00 .word 0x40012c00
|
|
|
8002308: 40000400 .word 0x40000400
|
|
|
800230c: 40000800 .word 0x40000800
|
|
|
|
|
|
08002310 <HAL_UART_Init>:
|
|
|
* @param huart Pointer to a UART_HandleTypeDef structure that contains
|
|
|
* the configuration information for the specified UART module.
|
|
|
* @retval HAL status
|
|
|
*/
|
|
|
HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
|
|
|
{
|
|
|
8002310: b580 push {r7, lr}
|
|
|
8002312: b082 sub sp, #8
|
|
|
8002314: af00 add r7, sp, #0
|
|
|
8002316: 6078 str r0, [r7, #4]
|
|
|
/* Check the UART handle allocation */
|
|
|
if (huart == NULL)
|
|
|
8002318: 687b ldr r3, [r7, #4]
|
|
|
800231a: 2b00 cmp r3, #0
|
|
|
800231c: d101 bne.n 8002322 <HAL_UART_Init+0x12>
|
|
|
{
|
|
|
return HAL_ERROR;
|
|
|
800231e: 2301 movs r3, #1
|
|
|
8002320: e03f b.n 80023a2 <HAL_UART_Init+0x92>
|
|
|
assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));
|
|
|
#if defined(USART_CR1_OVER8)
|
|
|
assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling));
|
|
|
#endif /* USART_CR1_OVER8 */
|
|
|
|
|
|
if (huart->gState == HAL_UART_STATE_RESET)
|
|
|
8002322: 687b ldr r3, [r7, #4]
|
|
|
8002324: f893 303d ldrb.w r3, [r3, #61] ; 0x3d
|
|
|
8002328: b2db uxtb r3, r3
|
|
|
800232a: 2b00 cmp r3, #0
|
|
|
800232c: d106 bne.n 800233c <HAL_UART_Init+0x2c>
|
|
|
{
|
|
|
/* Allocate lock resource and initialize it */
|
|
|
huart->Lock = HAL_UNLOCKED;
|
|
|
800232e: 687b ldr r3, [r7, #4]
|
|
|
8002330: 2200 movs r2, #0
|
|
|
8002332: f883 203c strb.w r2, [r3, #60] ; 0x3c
|
|
|
|
|
|
/* Init the low level hardware */
|
|
|
huart->MspInitCallback(huart);
|
|
|
#else
|
|
|
/* Init the low level hardware : GPIO, CLOCK */
|
|
|
HAL_UART_MspInit(huart);
|
|
|
8002336: 6878 ldr r0, [r7, #4]
|
|
|
8002338: f7fe fd68 bl 8000e0c <HAL_UART_MspInit>
|
|
|
#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
|
|
|
}
|
|
|
|
|
|
huart->gState = HAL_UART_STATE_BUSY;
|
|
|
800233c: 687b ldr r3, [r7, #4]
|
|
|
800233e: 2224 movs r2, #36 ; 0x24
|
|
|
8002340: f883 203d strb.w r2, [r3, #61] ; 0x3d
|
|
|
|
|
|
/* Disable the peripheral */
|
|
|
__HAL_UART_DISABLE(huart);
|
|
|
8002344: 687b ldr r3, [r7, #4]
|
|
|
8002346: 681b ldr r3, [r3, #0]
|
|
|
8002348: 68da ldr r2, [r3, #12]
|
|
|
800234a: 687b ldr r3, [r7, #4]
|
|
|
800234c: 681b ldr r3, [r3, #0]
|
|
|
800234e: f422 5200 bic.w r2, r2, #8192 ; 0x2000
|
|
|
8002352: 60da str r2, [r3, #12]
|
|
|
|
|
|
/* Set the UART Communication parameters */
|
|
|
UART_SetConfig(huart);
|
|
|
8002354: 6878 ldr r0, [r7, #4]
|
|
|
8002356: f000 f905 bl 8002564 <UART_SetConfig>
|
|
|
|
|
|
/* In asynchronous mode, the following bits must be kept cleared:
|
|
|
- LINEN and CLKEN bits in the USART_CR2 register,
|
|
|
- SCEN, HDSEL and IREN bits in the USART_CR3 register.*/
|
|
|
CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
|
|
|
800235a: 687b ldr r3, [r7, #4]
|
|
|
800235c: 681b ldr r3, [r3, #0]
|
|
|
800235e: 691a ldr r2, [r3, #16]
|
|
|
8002360: 687b ldr r3, [r7, #4]
|
|
|
8002362: 681b ldr r3, [r3, #0]
|
|
|
8002364: f422 4290 bic.w r2, r2, #18432 ; 0x4800
|
|
|
8002368: 611a str r2, [r3, #16]
|
|
|
CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
|
|
|
800236a: 687b ldr r3, [r7, #4]
|
|
|
800236c: 681b ldr r3, [r3, #0]
|
|
|
800236e: 695a ldr r2, [r3, #20]
|
|
|
8002370: 687b ldr r3, [r7, #4]
|
|
|
8002372: 681b ldr r3, [r3, #0]
|
|
|
8002374: f022 022a bic.w r2, r2, #42 ; 0x2a
|
|
|
8002378: 615a str r2, [r3, #20]
|
|
|
|
|
|
/* Enable the peripheral */
|
|
|
__HAL_UART_ENABLE(huart);
|
|
|
800237a: 687b ldr r3, [r7, #4]
|
|
|
800237c: 681b ldr r3, [r3, #0]
|
|
|
800237e: 68da ldr r2, [r3, #12]
|
|
|
8002380: 687b ldr r3, [r7, #4]
|
|
|
8002382: 681b ldr r3, [r3, #0]
|
|
|
8002384: f442 5200 orr.w r2, r2, #8192 ; 0x2000
|
|
|
8002388: 60da str r2, [r3, #12]
|
|
|
|
|
|
/* Initialize the UART state */
|
|
|
huart->ErrorCode = HAL_UART_ERROR_NONE;
|
|
|
800238a: 687b ldr r3, [r7, #4]
|
|
|
800238c: 2200 movs r2, #0
|
|
|
800238e: 641a str r2, [r3, #64] ; 0x40
|
|
|
huart->gState = HAL_UART_STATE_READY;
|
|
|
8002390: 687b ldr r3, [r7, #4]
|
|
|
8002392: 2220 movs r2, #32
|
|
|
8002394: f883 203d strb.w r2, [r3, #61] ; 0x3d
|
|
|
huart->RxState = HAL_UART_STATE_READY;
|
|
|
8002398: 687b ldr r3, [r7, #4]
|
|
|
800239a: 2220 movs r2, #32
|
|
|
800239c: f883 203e strb.w r2, [r3, #62] ; 0x3e
|
|
|
|
|
|
return HAL_OK;
|
|
|
80023a0: 2300 movs r3, #0
|
|
|
}
|
|
|
80023a2: 4618 mov r0, r3
|
|
|
80023a4: 3708 adds r7, #8
|
|
|
80023a6: 46bd mov sp, r7
|
|
|
80023a8: bd80 pop {r7, pc}
|
|
|
|
|
|
080023aa <HAL_UART_Transmit>:
|
|
|
* @param Size Amount of data elements (u8 or u16) to be sent
|
|
|
* @param Timeout Timeout duration
|
|
|
* @retval HAL status
|
|
|
*/
|
|
|
HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
|
|
|
{
|
|
|
80023aa: b580 push {r7, lr}
|
|
|
80023ac: b08a sub sp, #40 ; 0x28
|
|
|
80023ae: af02 add r7, sp, #8
|
|
|
80023b0: 60f8 str r0, [r7, #12]
|
|
|
80023b2: 60b9 str r1, [r7, #8]
|
|
|
80023b4: 603b str r3, [r7, #0]
|
|
|
80023b6: 4613 mov r3, r2
|
|
|
80023b8: 80fb strh r3, [r7, #6]
|
|
|
uint8_t *pdata8bits;
|
|
|
uint16_t *pdata16bits;
|
|
|
uint32_t tickstart = 0U;
|
|
|
80023ba: 2300 movs r3, #0
|
|
|
80023bc: 617b str r3, [r7, #20]
|
|
|
|
|
|
/* Check that a Tx process is not already ongoing */
|
|
|
if (huart->gState == HAL_UART_STATE_READY)
|
|
|
80023be: 68fb ldr r3, [r7, #12]
|
|
|
80023c0: f893 303d ldrb.w r3, [r3, #61] ; 0x3d
|
|
|
80023c4: b2db uxtb r3, r3
|
|
|
80023c6: 2b20 cmp r3, #32
|
|
|
80023c8: d17c bne.n 80024c4 <HAL_UART_Transmit+0x11a>
|
|
|
{
|
|
|
if ((pData == NULL) || (Size == 0U))
|
|
|
80023ca: 68bb ldr r3, [r7, #8]
|
|
|
80023cc: 2b00 cmp r3, #0
|
|
|
80023ce: d002 beq.n 80023d6 <HAL_UART_Transmit+0x2c>
|
|
|
80023d0: 88fb ldrh r3, [r7, #6]
|
|
|
80023d2: 2b00 cmp r3, #0
|
|
|
80023d4: d101 bne.n 80023da <HAL_UART_Transmit+0x30>
|
|
|
{
|
|
|
return HAL_ERROR;
|
|
|
80023d6: 2301 movs r3, #1
|
|
|
80023d8: e075 b.n 80024c6 <HAL_UART_Transmit+0x11c>
|
|
|
}
|
|
|
|
|
|
/* Process Locked */
|
|
|
__HAL_LOCK(huart);
|
|
|
80023da: 68fb ldr r3, [r7, #12]
|
|
|
80023dc: f893 303c ldrb.w r3, [r3, #60] ; 0x3c
|
|
|
80023e0: 2b01 cmp r3, #1
|
|
|
80023e2: d101 bne.n 80023e8 <HAL_UART_Transmit+0x3e>
|
|
|
80023e4: 2302 movs r3, #2
|
|
|
80023e6: e06e b.n 80024c6 <HAL_UART_Transmit+0x11c>
|
|
|
80023e8: 68fb ldr r3, [r7, #12]
|
|
|
80023ea: 2201 movs r2, #1
|
|
|
80023ec: f883 203c strb.w r2, [r3, #60] ; 0x3c
|
|
|
|
|
|
huart->ErrorCode = HAL_UART_ERROR_NONE;
|
|
|
80023f0: 68fb ldr r3, [r7, #12]
|
|
|
80023f2: 2200 movs r2, #0
|
|
|
80023f4: 641a str r2, [r3, #64] ; 0x40
|
|
|
huart->gState = HAL_UART_STATE_BUSY_TX;
|
|
|
80023f6: 68fb ldr r3, [r7, #12]
|
|
|
80023f8: 2221 movs r2, #33 ; 0x21
|
|
|
80023fa: f883 203d strb.w r2, [r3, #61] ; 0x3d
|
|
|
|
|
|
/* Init tickstart for timeout management */
|
|
|
tickstart = HAL_GetTick();
|
|
|
80023fe: f7fe fdcd bl 8000f9c <HAL_GetTick>
|
|
|
8002402: 6178 str r0, [r7, #20]
|
|
|
|
|
|
huart->TxXferSize = Size;
|
|
|
8002404: 68fb ldr r3, [r7, #12]
|
|
|
8002406: 88fa ldrh r2, [r7, #6]
|
|
|
8002408: 849a strh r2, [r3, #36] ; 0x24
|
|
|
huart->TxXferCount = Size;
|
|
|
800240a: 68fb ldr r3, [r7, #12]
|
|
|
800240c: 88fa ldrh r2, [r7, #6]
|
|
|
800240e: 84da strh r2, [r3, #38] ; 0x26
|
|
|
|
|
|
/* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */
|
|
|
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
|
|
|
8002410: 68fb ldr r3, [r7, #12]
|
|
|
8002412: 689b ldr r3, [r3, #8]
|
|
|
8002414: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
|
|
|
8002418: d108 bne.n 800242c <HAL_UART_Transmit+0x82>
|
|
|
800241a: 68fb ldr r3, [r7, #12]
|
|
|
800241c: 691b ldr r3, [r3, #16]
|
|
|
800241e: 2b00 cmp r3, #0
|
|
|
8002420: d104 bne.n 800242c <HAL_UART_Transmit+0x82>
|
|
|
{
|
|
|
pdata8bits = NULL;
|
|
|
8002422: 2300 movs r3, #0
|
|
|
8002424: 61fb str r3, [r7, #28]
|
|
|
pdata16bits = (uint16_t *) pData;
|
|
|
8002426: 68bb ldr r3, [r7, #8]
|
|
|
8002428: 61bb str r3, [r7, #24]
|
|
|
800242a: e003 b.n 8002434 <HAL_UART_Transmit+0x8a>
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
pdata8bits = pData;
|
|
|
800242c: 68bb ldr r3, [r7, #8]
|
|
|
800242e: 61fb str r3, [r7, #28]
|
|
|
pdata16bits = NULL;
|
|
|
8002430: 2300 movs r3, #0
|
|
|
8002432: 61bb str r3, [r7, #24]
|
|
|
}
|
|
|
|
|
|
/* Process Unlocked */
|
|
|
__HAL_UNLOCK(huart);
|
|
|
8002434: 68fb ldr r3, [r7, #12]
|
|
|
8002436: 2200 movs r2, #0
|
|
|
8002438: f883 203c strb.w r2, [r3, #60] ; 0x3c
|
|
|
|
|
|
while (huart->TxXferCount > 0U)
|
|
|
800243c: e02a b.n 8002494 <HAL_UART_Transmit+0xea>
|
|
|
{
|
|
|
if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
|
|
|
800243e: 683b ldr r3, [r7, #0]
|
|
|
8002440: 9300 str r3, [sp, #0]
|
|
|
8002442: 697b ldr r3, [r7, #20]
|
|
|
8002444: 2200 movs r2, #0
|
|
|
8002446: 2180 movs r1, #128 ; 0x80
|
|
|
8002448: 68f8 ldr r0, [r7, #12]
|
|
|
800244a: f000 f840 bl 80024ce <UART_WaitOnFlagUntilTimeout>
|
|
|
800244e: 4603 mov r3, r0
|
|
|
8002450: 2b00 cmp r3, #0
|
|
|
8002452: d001 beq.n 8002458 <HAL_UART_Transmit+0xae>
|
|
|
{
|
|
|
return HAL_TIMEOUT;
|
|
|
8002454: 2303 movs r3, #3
|
|
|
8002456: e036 b.n 80024c6 <HAL_UART_Transmit+0x11c>
|
|
|
}
|
|
|
if (pdata8bits == NULL)
|
|
|
8002458: 69fb ldr r3, [r7, #28]
|
|
|
800245a: 2b00 cmp r3, #0
|
|
|
800245c: d10b bne.n 8002476 <HAL_UART_Transmit+0xcc>
|
|
|
{
|
|
|
huart->Instance->DR = (uint16_t)(*pdata16bits & 0x01FFU);
|
|
|
800245e: 69bb ldr r3, [r7, #24]
|
|
|
8002460: 881b ldrh r3, [r3, #0]
|
|
|
8002462: 461a mov r2, r3
|
|
|
8002464: 68fb ldr r3, [r7, #12]
|
|
|
8002466: 681b ldr r3, [r3, #0]
|
|
|
8002468: f3c2 0208 ubfx r2, r2, #0, #9
|
|
|
800246c: 605a str r2, [r3, #4]
|
|
|
pdata16bits++;
|
|
|
800246e: 69bb ldr r3, [r7, #24]
|
|
|
8002470: 3302 adds r3, #2
|
|
|
8002472: 61bb str r3, [r7, #24]
|
|
|
8002474: e007 b.n 8002486 <HAL_UART_Transmit+0xdc>
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
huart->Instance->DR = (uint8_t)(*pdata8bits & 0xFFU);
|
|
|
8002476: 69fb ldr r3, [r7, #28]
|
|
|
8002478: 781a ldrb r2, [r3, #0]
|
|
|
800247a: 68fb ldr r3, [r7, #12]
|
|
|
800247c: 681b ldr r3, [r3, #0]
|
|
|
800247e: 605a str r2, [r3, #4]
|
|
|
pdata8bits++;
|
|
|
8002480: 69fb ldr r3, [r7, #28]
|
|
|
8002482: 3301 adds r3, #1
|
|
|
8002484: 61fb str r3, [r7, #28]
|
|
|
}
|
|
|
huart->TxXferCount--;
|
|
|
8002486: 68fb ldr r3, [r7, #12]
|
|
|
8002488: 8cdb ldrh r3, [r3, #38] ; 0x26
|
|
|
800248a: b29b uxth r3, r3
|
|
|
800248c: 3b01 subs r3, #1
|
|
|
800248e: b29a uxth r2, r3
|
|
|
8002490: 68fb ldr r3, [r7, #12]
|
|
|
8002492: 84da strh r2, [r3, #38] ; 0x26
|
|
|
while (huart->TxXferCount > 0U)
|
|
|
8002494: 68fb ldr r3, [r7, #12]
|
|
|
8002496: 8cdb ldrh r3, [r3, #38] ; 0x26
|
|
|
8002498: b29b uxth r3, r3
|
|
|
800249a: 2b00 cmp r3, #0
|
|
|
800249c: d1cf bne.n 800243e <HAL_UART_Transmit+0x94>
|
|
|
}
|
|
|
|
|
|
if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
|
|
|
800249e: 683b ldr r3, [r7, #0]
|
|
|
80024a0: 9300 str r3, [sp, #0]
|
|
|
80024a2: 697b ldr r3, [r7, #20]
|
|
|
80024a4: 2200 movs r2, #0
|
|
|
80024a6: 2140 movs r1, #64 ; 0x40
|
|
|
80024a8: 68f8 ldr r0, [r7, #12]
|
|
|
80024aa: f000 f810 bl 80024ce <UART_WaitOnFlagUntilTimeout>
|
|
|
80024ae: 4603 mov r3, r0
|
|
|
80024b0: 2b00 cmp r3, #0
|
|
|
80024b2: d001 beq.n 80024b8 <HAL_UART_Transmit+0x10e>
|
|
|
{
|
|
|
return HAL_TIMEOUT;
|
|
|
80024b4: 2303 movs r3, #3
|
|
|
80024b6: e006 b.n 80024c6 <HAL_UART_Transmit+0x11c>
|
|
|
}
|
|
|
|
|
|
/* At end of Tx process, restore huart->gState to Ready */
|
|
|
huart->gState = HAL_UART_STATE_READY;
|
|
|
80024b8: 68fb ldr r3, [r7, #12]
|
|
|
80024ba: 2220 movs r2, #32
|
|
|
80024bc: f883 203d strb.w r2, [r3, #61] ; 0x3d
|
|
|
|
|
|
return HAL_OK;
|
|
|
80024c0: 2300 movs r3, #0
|
|
|
80024c2: e000 b.n 80024c6 <HAL_UART_Transmit+0x11c>
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
return HAL_BUSY;
|
|
|
80024c4: 2302 movs r3, #2
|
|
|
}
|
|
|
}
|
|
|
80024c6: 4618 mov r0, r3
|
|
|
80024c8: 3720 adds r7, #32
|
|
|
80024ca: 46bd mov sp, r7
|
|
|
80024cc: bd80 pop {r7, pc}
|
|
|
|
|
|
080024ce <UART_WaitOnFlagUntilTimeout>:
|
|
|
* @param Tickstart Tick start value
|
|
|
* @param Timeout Timeout duration
|
|
|
* @retval HAL status
|
|
|
*/
|
|
|
static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
|
|
|
{
|
|
|
80024ce: b580 push {r7, lr}
|
|
|
80024d0: b084 sub sp, #16
|
|
|
80024d2: af00 add r7, sp, #0
|
|
|
80024d4: 60f8 str r0, [r7, #12]
|
|
|
80024d6: 60b9 str r1, [r7, #8]
|
|
|
80024d8: 603b str r3, [r7, #0]
|
|
|
80024da: 4613 mov r3, r2
|
|
|
80024dc: 71fb strb r3, [r7, #7]
|
|
|
/* Wait until flag is set */
|
|
|
while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
|
|
|
80024de: e02c b.n 800253a <UART_WaitOnFlagUntilTimeout+0x6c>
|
|
|
{
|
|
|
/* Check for the Timeout */
|
|
|
if (Timeout != HAL_MAX_DELAY)
|
|
|
80024e0: 69bb ldr r3, [r7, #24]
|
|
|
80024e2: f1b3 3fff cmp.w r3, #4294967295
|
|
|
80024e6: d028 beq.n 800253a <UART_WaitOnFlagUntilTimeout+0x6c>
|
|
|
{
|
|
|
if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout))
|
|
|
80024e8: 69bb ldr r3, [r7, #24]
|
|
|
80024ea: 2b00 cmp r3, #0
|
|
|
80024ec: d007 beq.n 80024fe <UART_WaitOnFlagUntilTimeout+0x30>
|
|
|
80024ee: f7fe fd55 bl 8000f9c <HAL_GetTick>
|
|
|
80024f2: 4602 mov r2, r0
|
|
|
80024f4: 683b ldr r3, [r7, #0]
|
|
|
80024f6: 1ad3 subs r3, r2, r3
|
|
|
80024f8: 69ba ldr r2, [r7, #24]
|
|
|
80024fa: 429a cmp r2, r3
|
|
|
80024fc: d21d bcs.n 800253a <UART_WaitOnFlagUntilTimeout+0x6c>
|
|
|
{
|
|
|
/* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
|
|
|
CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
|
|
|
80024fe: 68fb ldr r3, [r7, #12]
|
|
|
8002500: 681b ldr r3, [r3, #0]
|
|
|
8002502: 68da ldr r2, [r3, #12]
|
|
|
8002504: 68fb ldr r3, [r7, #12]
|
|
|
8002506: 681b ldr r3, [r3, #0]
|
|
|
8002508: f422 72d0 bic.w r2, r2, #416 ; 0x1a0
|
|
|
800250c: 60da str r2, [r3, #12]
|
|
|
CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
|
|
|
800250e: 68fb ldr r3, [r7, #12]
|
|
|
8002510: 681b ldr r3, [r3, #0]
|
|
|
8002512: 695a ldr r2, [r3, #20]
|
|
|
8002514: 68fb ldr r3, [r7, #12]
|
|
|
8002516: 681b ldr r3, [r3, #0]
|
|
|
8002518: f022 0201 bic.w r2, r2, #1
|
|
|
800251c: 615a str r2, [r3, #20]
|
|
|
|
|
|
huart->gState = HAL_UART_STATE_READY;
|
|
|
800251e: 68fb ldr r3, [r7, #12]
|
|
|
8002520: 2220 movs r2, #32
|
|
|
8002522: f883 203d strb.w r2, [r3, #61] ; 0x3d
|
|
|
huart->RxState = HAL_UART_STATE_READY;
|
|
|
8002526: 68fb ldr r3, [r7, #12]
|
|
|
8002528: 2220 movs r2, #32
|
|
|
800252a: f883 203e strb.w r2, [r3, #62] ; 0x3e
|
|
|
|
|
|
/* Process Unlocked */
|
|
|
__HAL_UNLOCK(huart);
|
|
|
800252e: 68fb ldr r3, [r7, #12]
|
|
|
8002530: 2200 movs r2, #0
|
|
|
8002532: f883 203c strb.w r2, [r3, #60] ; 0x3c
|
|
|
|
|
|
return HAL_TIMEOUT;
|
|
|
8002536: 2303 movs r3, #3
|
|
|
8002538: e00f b.n 800255a <UART_WaitOnFlagUntilTimeout+0x8c>
|
|
|
while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
|
|
|
800253a: 68fb ldr r3, [r7, #12]
|
|
|
800253c: 681b ldr r3, [r3, #0]
|
|
|
800253e: 681a ldr r2, [r3, #0]
|
|
|
8002540: 68bb ldr r3, [r7, #8]
|
|
|
8002542: 4013 ands r3, r2
|
|
|
8002544: 68ba ldr r2, [r7, #8]
|
|
|
8002546: 429a cmp r2, r3
|
|
|
8002548: bf0c ite eq
|
|
|
800254a: 2301 moveq r3, #1
|
|
|
800254c: 2300 movne r3, #0
|
|
|
800254e: b2db uxtb r3, r3
|
|
|
8002550: 461a mov r2, r3
|
|
|
8002552: 79fb ldrb r3, [r7, #7]
|
|
|
8002554: 429a cmp r2, r3
|
|
|
8002556: d0c3 beq.n 80024e0 <UART_WaitOnFlagUntilTimeout+0x12>
|
|
|
}
|
|
|
}
|
|
|
}
|
|
|
return HAL_OK;
|
|
|
8002558: 2300 movs r3, #0
|
|
|
}
|
|
|
800255a: 4618 mov r0, r3
|
|
|
800255c: 3710 adds r7, #16
|
|
|
800255e: 46bd mov sp, r7
|
|
|
8002560: bd80 pop {r7, pc}
|
|
|
...
|
|
|
|
|
|
08002564 <UART_SetConfig>:
|
|
|
* @param huart Pointer to a UART_HandleTypeDef structure that contains
|
|
|
* the configuration information for the specified UART module.
|
|
|
* @retval None
|
|
|
*/
|
|
|
static void UART_SetConfig(UART_HandleTypeDef *huart)
|
|
|
{
|
|
|
8002564: b580 push {r7, lr}
|
|
|
8002566: b084 sub sp, #16
|
|
|
8002568: af00 add r7, sp, #0
|
|
|
800256a: 6078 str r0, [r7, #4]
|
|
|
assert_param(IS_UART_MODE(huart->Init.Mode));
|
|
|
|
|
|
/*-------------------------- USART CR2 Configuration -----------------------*/
|
|
|
/* Configure the UART Stop Bits: Set STOP[13:12] bits
|
|
|
according to huart->Init.StopBits value */
|
|
|
MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
|
|
|
800256c: 687b ldr r3, [r7, #4]
|
|
|
800256e: 681b ldr r3, [r3, #0]
|
|
|
8002570: 691b ldr r3, [r3, #16]
|
|
|
8002572: f423 5140 bic.w r1, r3, #12288 ; 0x3000
|
|
|
8002576: 687b ldr r3, [r7, #4]
|
|
|
8002578: 68da ldr r2, [r3, #12]
|
|
|
800257a: 687b ldr r3, [r7, #4]
|
|
|
800257c: 681b ldr r3, [r3, #0]
|
|
|
800257e: 430a orrs r2, r1
|
|
|
8002580: 611a str r2, [r3, #16]
|
|
|
tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling;
|
|
|
MODIFY_REG(huart->Instance->CR1,
|
|
|
(uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8),
|
|
|
tmpreg);
|
|
|
#else
|
|
|
tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode;
|
|
|
8002582: 687b ldr r3, [r7, #4]
|
|
|
8002584: 689a ldr r2, [r3, #8]
|
|
|
8002586: 687b ldr r3, [r7, #4]
|
|
|
8002588: 691b ldr r3, [r3, #16]
|
|
|
800258a: 431a orrs r2, r3
|
|
|
800258c: 687b ldr r3, [r7, #4]
|
|
|
800258e: 695b ldr r3, [r3, #20]
|
|
|
8002590: 4313 orrs r3, r2
|
|
|
8002592: 60bb str r3, [r7, #8]
|
|
|
MODIFY_REG(huart->Instance->CR1,
|
|
|
8002594: 687b ldr r3, [r7, #4]
|
|
|
8002596: 681b ldr r3, [r3, #0]
|
|
|
8002598: 68db ldr r3, [r3, #12]
|
|
|
800259a: f423 53b0 bic.w r3, r3, #5632 ; 0x1600
|
|
|
800259e: f023 030c bic.w r3, r3, #12
|
|
|
80025a2: 687a ldr r2, [r7, #4]
|
|
|
80025a4: 6812 ldr r2, [r2, #0]
|
|
|
80025a6: 68b9 ldr r1, [r7, #8]
|
|
|
80025a8: 430b orrs r3, r1
|
|
|
80025aa: 60d3 str r3, [r2, #12]
|
|
|
tmpreg);
|
|
|
#endif /* USART_CR1_OVER8 */
|
|
|
|
|
|
/*-------------------------- USART CR3 Configuration -----------------------*/
|
|
|
/* Configure the UART HFC: Set CTSE and RTSE bits according to huart->Init.HwFlowCtl value */
|
|
|
MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE), huart->Init.HwFlowCtl);
|
|
|
80025ac: 687b ldr r3, [r7, #4]
|
|
|
80025ae: 681b ldr r3, [r3, #0]
|
|
|
80025b0: 695b ldr r3, [r3, #20]
|
|
|
80025b2: f423 7140 bic.w r1, r3, #768 ; 0x300
|
|
|
80025b6: 687b ldr r3, [r7, #4]
|
|
|
80025b8: 699a ldr r2, [r3, #24]
|
|
|
80025ba: 687b ldr r3, [r7, #4]
|
|
|
80025bc: 681b ldr r3, [r3, #0]
|
|
|
80025be: 430a orrs r2, r1
|
|
|
80025c0: 615a str r2, [r3, #20]
|
|
|
|
|
|
|
|
|
if(huart->Instance == USART1)
|
|
|
80025c2: 687b ldr r3, [r7, #4]
|
|
|
80025c4: 681b ldr r3, [r3, #0]
|
|
|
80025c6: 4a2c ldr r2, [pc, #176] ; (8002678 <UART_SetConfig+0x114>)
|
|
|
80025c8: 4293 cmp r3, r2
|
|
|
80025ca: d103 bne.n 80025d4 <UART_SetConfig+0x70>
|
|
|
{
|
|
|
pclk = HAL_RCC_GetPCLK2Freq();
|
|
|
80025cc: f7ff fb94 bl 8001cf8 <HAL_RCC_GetPCLK2Freq>
|
|
|
80025d0: 60f8 str r0, [r7, #12]
|
|
|
80025d2: e002 b.n 80025da <UART_SetConfig+0x76>
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
pclk = HAL_RCC_GetPCLK1Freq();
|
|
|
80025d4: f7ff fb7c bl 8001cd0 <HAL_RCC_GetPCLK1Freq>
|
|
|
80025d8: 60f8 str r0, [r7, #12]
|
|
|
else
|
|
|
{
|
|
|
huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate);
|
|
|
}
|
|
|
#else
|
|
|
huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate);
|
|
|
80025da: 68fa ldr r2, [r7, #12]
|
|
|
80025dc: 4613 mov r3, r2
|
|
|
80025de: 009b lsls r3, r3, #2
|
|
|
80025e0: 4413 add r3, r2
|
|
|
80025e2: 009a lsls r2, r3, #2
|
|
|
80025e4: 441a add r2, r3
|
|
|
80025e6: 687b ldr r3, [r7, #4]
|
|
|
80025e8: 685b ldr r3, [r3, #4]
|
|
|
80025ea: 009b lsls r3, r3, #2
|
|
|
80025ec: fbb2 f3f3 udiv r3, r2, r3
|
|
|
80025f0: 4a22 ldr r2, [pc, #136] ; (800267c <UART_SetConfig+0x118>)
|
|
|
80025f2: fba2 2303 umull r2, r3, r2, r3
|
|
|
80025f6: 095b lsrs r3, r3, #5
|
|
|
80025f8: 0119 lsls r1, r3, #4
|
|
|
80025fa: 68fa ldr r2, [r7, #12]
|
|
|
80025fc: 4613 mov r3, r2
|
|
|
80025fe: 009b lsls r3, r3, #2
|
|
|
8002600: 4413 add r3, r2
|
|
|
8002602: 009a lsls r2, r3, #2
|
|
|
8002604: 441a add r2, r3
|
|
|
8002606: 687b ldr r3, [r7, #4]
|
|
|
8002608: 685b ldr r3, [r3, #4]
|
|
|
800260a: 009b lsls r3, r3, #2
|
|
|
800260c: fbb2 f2f3 udiv r2, r2, r3
|
|
|
8002610: 4b1a ldr r3, [pc, #104] ; (800267c <UART_SetConfig+0x118>)
|
|
|
8002612: fba3 0302 umull r0, r3, r3, r2
|
|
|
8002616: 095b lsrs r3, r3, #5
|
|
|
8002618: 2064 movs r0, #100 ; 0x64
|
|
|
800261a: fb00 f303 mul.w r3, r0, r3
|
|
|
800261e: 1ad3 subs r3, r2, r3
|
|
|
8002620: 011b lsls r3, r3, #4
|
|
|
8002622: 3332 adds r3, #50 ; 0x32
|
|
|
8002624: 4a15 ldr r2, [pc, #84] ; (800267c <UART_SetConfig+0x118>)
|
|
|
8002626: fba2 2303 umull r2, r3, r2, r3
|
|
|
800262a: 095b lsrs r3, r3, #5
|
|
|
800262c: f003 03f0 and.w r3, r3, #240 ; 0xf0
|
|
|
8002630: 4419 add r1, r3
|
|
|
8002632: 68fa ldr r2, [r7, #12]
|
|
|
8002634: 4613 mov r3, r2
|
|
|
8002636: 009b lsls r3, r3, #2
|
|
|
8002638: 4413 add r3, r2
|
|
|
800263a: 009a lsls r2, r3, #2
|
|
|
800263c: 441a add r2, r3
|
|
|
800263e: 687b ldr r3, [r7, #4]
|
|
|
8002640: 685b ldr r3, [r3, #4]
|
|
|
8002642: 009b lsls r3, r3, #2
|
|
|
8002644: fbb2 f2f3 udiv r2, r2, r3
|
|
|
8002648: 4b0c ldr r3, [pc, #48] ; (800267c <UART_SetConfig+0x118>)
|
|
|
800264a: fba3 0302 umull r0, r3, r3, r2
|
|
|
800264e: 095b lsrs r3, r3, #5
|
|
|
8002650: 2064 movs r0, #100 ; 0x64
|
|
|
8002652: fb00 f303 mul.w r3, r0, r3
|
|
|
8002656: 1ad3 subs r3, r2, r3
|
|
|
8002658: 011b lsls r3, r3, #4
|
|
|
800265a: 3332 adds r3, #50 ; 0x32
|
|
|
800265c: 4a07 ldr r2, [pc, #28] ; (800267c <UART_SetConfig+0x118>)
|
|
|
800265e: fba2 2303 umull r2, r3, r2, r3
|
|
|
8002662: 095b lsrs r3, r3, #5
|
|
|
8002664: f003 020f and.w r2, r3, #15
|
|
|
8002668: 687b ldr r3, [r7, #4]
|
|
|
800266a: 681b ldr r3, [r3, #0]
|
|
|
800266c: 440a add r2, r1
|
|
|
800266e: 609a str r2, [r3, #8]
|
|
|
#endif /* USART_CR1_OVER8 */
|
|
|
}
|
|
|
8002670: bf00 nop
|
|
|
8002672: 3710 adds r7, #16
|
|
|
8002674: 46bd mov sp, r7
|
|
|
8002676: bd80 pop {r7, pc}
|
|
|
8002678: 40013800 .word 0x40013800
|
|
|
800267c: 51eb851f .word 0x51eb851f
|
|
|
|
|
|
08002680 <__errno>:
|
|
|
8002680: 4b01 ldr r3, [pc, #4] ; (8002688 <__errno+0x8>)
|
|
|
8002682: 6818 ldr r0, [r3, #0]
|
|
|
8002684: 4770 bx lr
|
|
|
8002686: bf00 nop
|
|
|
8002688: 2000000c .word 0x2000000c
|
|
|
|
|
|
0800268c <__libc_init_array>:
|
|
|
800268c: b570 push {r4, r5, r6, lr}
|
|
|
800268e: 2600 movs r6, #0
|
|
|
8002690: 4d0c ldr r5, [pc, #48] ; (80026c4 <__libc_init_array+0x38>)
|
|
|
8002692: 4c0d ldr r4, [pc, #52] ; (80026c8 <__libc_init_array+0x3c>)
|
|
|
8002694: 1b64 subs r4, r4, r5
|
|
|
8002696: 10a4 asrs r4, r4, #2
|
|
|
8002698: 42a6 cmp r6, r4
|
|
|
800269a: d109 bne.n 80026b0 <__libc_init_array+0x24>
|
|
|
800269c: f000 fc9c bl 8002fd8 <_init>
|
|
|
80026a0: 2600 movs r6, #0
|
|
|
80026a2: 4d0a ldr r5, [pc, #40] ; (80026cc <__libc_init_array+0x40>)
|
|
|
80026a4: 4c0a ldr r4, [pc, #40] ; (80026d0 <__libc_init_array+0x44>)
|
|
|
80026a6: 1b64 subs r4, r4, r5
|
|
|
80026a8: 10a4 asrs r4, r4, #2
|
|
|
80026aa: 42a6 cmp r6, r4
|
|
|
80026ac: d105 bne.n 80026ba <__libc_init_array+0x2e>
|
|
|
80026ae: bd70 pop {r4, r5, r6, pc}
|
|
|
80026b0: f855 3b04 ldr.w r3, [r5], #4
|
|
|
80026b4: 4798 blx r3
|
|
|
80026b6: 3601 adds r6, #1
|
|
|
80026b8: e7ee b.n 8002698 <__libc_init_array+0xc>
|
|
|
80026ba: f855 3b04 ldr.w r3, [r5], #4
|
|
|
80026be: 4798 blx r3
|
|
|
80026c0: 3601 adds r6, #1
|
|
|
80026c2: e7f2 b.n 80026aa <__libc_init_array+0x1e>
|
|
|
80026c4: 0800305c .word 0x0800305c
|
|
|
80026c8: 0800305c .word 0x0800305c
|
|
|
80026cc: 0800305c .word 0x0800305c
|
|
|
80026d0: 08003060 .word 0x08003060
|
|
|
|
|
|
080026d4 <memset>:
|
|
|
80026d4: 4603 mov r3, r0
|
|
|
80026d6: 4402 add r2, r0
|
|
|
80026d8: 4293 cmp r3, r2
|
|
|
80026da: d100 bne.n 80026de <memset+0xa>
|
|
|
80026dc: 4770 bx lr
|
|
|
80026de: f803 1b01 strb.w r1, [r3], #1
|
|
|
80026e2: e7f9 b.n 80026d8 <memset+0x4>
|
|
|
|
|
|
080026e4 <siprintf>:
|
|
|
80026e4: b40e push {r1, r2, r3}
|
|
|
80026e6: f06f 4100 mvn.w r1, #2147483648 ; 0x80000000
|
|
|
80026ea: b500 push {lr}
|
|
|
80026ec: b09c sub sp, #112 ; 0x70
|
|
|
80026ee: ab1d add r3, sp, #116 ; 0x74
|
|
|
80026f0: 9002 str r0, [sp, #8]
|
|
|
80026f2: 9006 str r0, [sp, #24]
|
|
|
80026f4: 9107 str r1, [sp, #28]
|
|
|
80026f6: 9104 str r1, [sp, #16]
|
|
|
80026f8: 4808 ldr r0, [pc, #32] ; (800271c <siprintf+0x38>)
|
|
|
80026fa: 4909 ldr r1, [pc, #36] ; (8002720 <siprintf+0x3c>)
|
|
|
80026fc: f853 2b04 ldr.w r2, [r3], #4
|
|
|
8002700: 9105 str r1, [sp, #20]
|
|
|
8002702: 6800 ldr r0, [r0, #0]
|
|
|
8002704: a902 add r1, sp, #8
|
|
|
8002706: 9301 str r3, [sp, #4]
|
|
|
8002708: f000 f868 bl 80027dc <_svfiprintf_r>
|
|
|
800270c: 2200 movs r2, #0
|
|
|
800270e: 9b02 ldr r3, [sp, #8]
|
|
|
8002710: 701a strb r2, [r3, #0]
|
|
|
8002712: b01c add sp, #112 ; 0x70
|
|
|
8002714: f85d eb04 ldr.w lr, [sp], #4
|
|
|
8002718: b003 add sp, #12
|
|
|
800271a: 4770 bx lr
|
|
|
800271c: 2000000c .word 0x2000000c
|
|
|
8002720: ffff0208 .word 0xffff0208
|
|
|
|
|
|
08002724 <__ssputs_r>:
|
|
|
8002724: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
|
|
|
8002728: 688e ldr r6, [r1, #8]
|
|
|
800272a: 4682 mov sl, r0
|
|
|
800272c: 429e cmp r6, r3
|
|
|
800272e: 460c mov r4, r1
|
|
|
8002730: 4690 mov r8, r2
|
|
|
8002732: 461f mov r7, r3
|
|
|
8002734: d838 bhi.n 80027a8 <__ssputs_r+0x84>
|
|
|
8002736: 898a ldrh r2, [r1, #12]
|
|
|
8002738: f412 6f90 tst.w r2, #1152 ; 0x480
|
|
|
800273c: d032 beq.n 80027a4 <__ssputs_r+0x80>
|
|
|
800273e: 6825 ldr r5, [r4, #0]
|
|
|
8002740: 6909 ldr r1, [r1, #16]
|
|
|
8002742: 3301 adds r3, #1
|
|
|
8002744: eba5 0901 sub.w r9, r5, r1
|
|
|
8002748: 6965 ldr r5, [r4, #20]
|
|
|
800274a: 444b add r3, r9
|
|
|
800274c: eb05 0545 add.w r5, r5, r5, lsl #1
|
|
|
8002750: eb05 75d5 add.w r5, r5, r5, lsr #31
|
|
|
8002754: 106d asrs r5, r5, #1
|
|
|
8002756: 429d cmp r5, r3
|
|
|
8002758: bf38 it cc
|
|
|
800275a: 461d movcc r5, r3
|
|
|
800275c: 0553 lsls r3, r2, #21
|
|
|
800275e: d531 bpl.n 80027c4 <__ssputs_r+0xa0>
|
|
|
8002760: 4629 mov r1, r5
|
|
|
8002762: f000 fb6f bl 8002e44 <_malloc_r>
|
|
|
8002766: 4606 mov r6, r0
|
|
|
8002768: b950 cbnz r0, 8002780 <__ssputs_r+0x5c>
|
|
|
800276a: 230c movs r3, #12
|
|
|
800276c: f04f 30ff mov.w r0, #4294967295
|
|
|
8002770: f8ca 3000 str.w r3, [sl]
|
|
|
8002774: 89a3 ldrh r3, [r4, #12]
|
|
|
8002776: f043 0340 orr.w r3, r3, #64 ; 0x40
|
|
|
800277a: 81a3 strh r3, [r4, #12]
|
|
|
800277c: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
|
|
|
8002780: 464a mov r2, r9
|
|
|
8002782: 6921 ldr r1, [r4, #16]
|
|
|
8002784: f000 face bl 8002d24 <memcpy>
|
|
|
8002788: 89a3 ldrh r3, [r4, #12]
|
|
|
800278a: f423 6390 bic.w r3, r3, #1152 ; 0x480
|
|
|
800278e: f043 0380 orr.w r3, r3, #128 ; 0x80
|
|
|
8002792: 81a3 strh r3, [r4, #12]
|
|
|
8002794: 6126 str r6, [r4, #16]
|
|
|
8002796: 444e add r6, r9
|
|
|
8002798: 6026 str r6, [r4, #0]
|
|
|
800279a: 463e mov r6, r7
|
|
|
800279c: 6165 str r5, [r4, #20]
|
|
|
800279e: eba5 0509 sub.w r5, r5, r9
|
|
|
80027a2: 60a5 str r5, [r4, #8]
|
|
|
80027a4: 42be cmp r6, r7
|
|
|
80027a6: d900 bls.n 80027aa <__ssputs_r+0x86>
|
|
|
80027a8: 463e mov r6, r7
|
|
|
80027aa: 4632 mov r2, r6
|
|
|
80027ac: 4641 mov r1, r8
|
|
|
80027ae: 6820 ldr r0, [r4, #0]
|
|
|
80027b0: f000 fac6 bl 8002d40 <memmove>
|
|
|
80027b4: 68a3 ldr r3, [r4, #8]
|
|
|
80027b6: 2000 movs r0, #0
|
|
|
80027b8: 1b9b subs r3, r3, r6
|
|
|
80027ba: 60a3 str r3, [r4, #8]
|
|
|
80027bc: 6823 ldr r3, [r4, #0]
|
|
|
80027be: 4433 add r3, r6
|
|
|
80027c0: 6023 str r3, [r4, #0]
|
|
|
80027c2: e7db b.n 800277c <__ssputs_r+0x58>
|
|
|
80027c4: 462a mov r2, r5
|
|
|
80027c6: f000 fbb1 bl 8002f2c <_realloc_r>
|
|
|
80027ca: 4606 mov r6, r0
|
|
|
80027cc: 2800 cmp r0, #0
|
|
|
80027ce: d1e1 bne.n 8002794 <__ssputs_r+0x70>
|
|
|
80027d0: 4650 mov r0, sl
|
|
|
80027d2: 6921 ldr r1, [r4, #16]
|
|
|
80027d4: f000 face bl 8002d74 <_free_r>
|
|
|
80027d8: e7c7 b.n 800276a <__ssputs_r+0x46>
|
|
|
...
|
|
|
|
|
|
080027dc <_svfiprintf_r>:
|
|
|
80027dc: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
|
|
|
80027e0: 4698 mov r8, r3
|
|
|
80027e2: 898b ldrh r3, [r1, #12]
|
|
|
80027e4: 4607 mov r7, r0
|
|
|
80027e6: 061b lsls r3, r3, #24
|
|
|
80027e8: 460d mov r5, r1
|
|
|
80027ea: 4614 mov r4, r2
|
|
|
80027ec: b09d sub sp, #116 ; 0x74
|
|
|
80027ee: d50e bpl.n 800280e <_svfiprintf_r+0x32>
|
|
|
80027f0: 690b ldr r3, [r1, #16]
|
|
|
80027f2: b963 cbnz r3, 800280e <_svfiprintf_r+0x32>
|
|
|
80027f4: 2140 movs r1, #64 ; 0x40
|
|
|
80027f6: f000 fb25 bl 8002e44 <_malloc_r>
|
|
|
80027fa: 6028 str r0, [r5, #0]
|
|
|
80027fc: 6128 str r0, [r5, #16]
|
|
|
80027fe: b920 cbnz r0, 800280a <_svfiprintf_r+0x2e>
|
|
|
8002800: 230c movs r3, #12
|
|
|
8002802: 603b str r3, [r7, #0]
|
|
|
8002804: f04f 30ff mov.w r0, #4294967295
|
|
|
8002808: e0d1 b.n 80029ae <_svfiprintf_r+0x1d2>
|
|
|
800280a: 2340 movs r3, #64 ; 0x40
|
|
|
800280c: 616b str r3, [r5, #20]
|
|
|
800280e: 2300 movs r3, #0
|
|
|
8002810: 9309 str r3, [sp, #36] ; 0x24
|
|
|
8002812: 2320 movs r3, #32
|
|
|
8002814: f88d 3029 strb.w r3, [sp, #41] ; 0x29
|
|
|
8002818: 2330 movs r3, #48 ; 0x30
|
|
|
800281a: f04f 0901 mov.w r9, #1
|
|
|
800281e: f8cd 800c str.w r8, [sp, #12]
|
|
|
8002822: f8df 81a4 ldr.w r8, [pc, #420] ; 80029c8 <_svfiprintf_r+0x1ec>
|
|
|
8002826: f88d 302a strb.w r3, [sp, #42] ; 0x2a
|
|
|
800282a: 4623 mov r3, r4
|
|
|
800282c: 469a mov sl, r3
|
|
|
800282e: f813 2b01 ldrb.w r2, [r3], #1
|
|
|
8002832: b10a cbz r2, 8002838 <_svfiprintf_r+0x5c>
|
|
|
8002834: 2a25 cmp r2, #37 ; 0x25
|
|
|
8002836: d1f9 bne.n 800282c <_svfiprintf_r+0x50>
|
|
|
8002838: ebba 0b04 subs.w fp, sl, r4
|
|
|
800283c: d00b beq.n 8002856 <_svfiprintf_r+0x7a>
|
|
|
800283e: 465b mov r3, fp
|
|
|
8002840: 4622 mov r2, r4
|
|
|
8002842: 4629 mov r1, r5
|
|
|
8002844: 4638 mov r0, r7
|
|
|
8002846: f7ff ff6d bl 8002724 <__ssputs_r>
|
|
|
800284a: 3001 adds r0, #1
|
|
|
800284c: f000 80aa beq.w 80029a4 <_svfiprintf_r+0x1c8>
|
|
|
8002850: 9a09 ldr r2, [sp, #36] ; 0x24
|
|
|
8002852: 445a add r2, fp
|
|
|
8002854: 9209 str r2, [sp, #36] ; 0x24
|
|
|
8002856: f89a 3000 ldrb.w r3, [sl]
|
|
|
800285a: 2b00 cmp r3, #0
|
|
|
800285c: f000 80a2 beq.w 80029a4 <_svfiprintf_r+0x1c8>
|
|
|
8002860: 2300 movs r3, #0
|
|
|
8002862: f04f 32ff mov.w r2, #4294967295
|
|
|
8002866: e9cd 2305 strd r2, r3, [sp, #20]
|
|
|
800286a: f10a 0a01 add.w sl, sl, #1
|
|
|
800286e: 9304 str r3, [sp, #16]
|
|
|
8002870: 9307 str r3, [sp, #28]
|
|
|
8002872: f88d 3053 strb.w r3, [sp, #83] ; 0x53
|
|
|
8002876: 931a str r3, [sp, #104] ; 0x68
|
|
|
8002878: 4654 mov r4, sl
|
|
|
800287a: 2205 movs r2, #5
|
|
|
800287c: f814 1b01 ldrb.w r1, [r4], #1
|
|
|
8002880: 4851 ldr r0, [pc, #324] ; (80029c8 <_svfiprintf_r+0x1ec>)
|
|
|
8002882: f000 fa41 bl 8002d08 <memchr>
|
|
|
8002886: 9a04 ldr r2, [sp, #16]
|
|
|
8002888: b9d8 cbnz r0, 80028c2 <_svfiprintf_r+0xe6>
|
|
|
800288a: 06d0 lsls r0, r2, #27
|
|
|
800288c: bf44 itt mi
|
|
|
800288e: 2320 movmi r3, #32
|
|
|
8002890: f88d 3053 strbmi.w r3, [sp, #83] ; 0x53
|
|
|
8002894: 0711 lsls r1, r2, #28
|
|
|
8002896: bf44 itt mi
|
|
|
8002898: 232b movmi r3, #43 ; 0x2b
|
|
|
800289a: f88d 3053 strbmi.w r3, [sp, #83] ; 0x53
|
|
|
800289e: f89a 3000 ldrb.w r3, [sl]
|
|
|
80028a2: 2b2a cmp r3, #42 ; 0x2a
|
|
|
80028a4: d015 beq.n 80028d2 <_svfiprintf_r+0xf6>
|
|
|
80028a6: 4654 mov r4, sl
|
|
|
80028a8: 2000 movs r0, #0
|
|
|
80028aa: f04f 0c0a mov.w ip, #10
|
|
|
80028ae: 9a07 ldr r2, [sp, #28]
|
|
|
80028b0: 4621 mov r1, r4
|
|
|
80028b2: f811 3b01 ldrb.w r3, [r1], #1
|
|
|
80028b6: 3b30 subs r3, #48 ; 0x30
|
|
|
80028b8: 2b09 cmp r3, #9
|
|
|
80028ba: d94e bls.n 800295a <_svfiprintf_r+0x17e>
|
|
|
80028bc: b1b0 cbz r0, 80028ec <_svfiprintf_r+0x110>
|
|
|
80028be: 9207 str r2, [sp, #28]
|
|
|
80028c0: e014 b.n 80028ec <_svfiprintf_r+0x110>
|
|
|
80028c2: eba0 0308 sub.w r3, r0, r8
|
|
|
80028c6: fa09 f303 lsl.w r3, r9, r3
|
|
|
80028ca: 4313 orrs r3, r2
|
|
|
80028cc: 46a2 mov sl, r4
|
|
|
80028ce: 9304 str r3, [sp, #16]
|
|
|
80028d0: e7d2 b.n 8002878 <_svfiprintf_r+0x9c>
|
|
|
80028d2: 9b03 ldr r3, [sp, #12]
|
|
|
80028d4: 1d19 adds r1, r3, #4
|
|
|
80028d6: 681b ldr r3, [r3, #0]
|
|
|
80028d8: 9103 str r1, [sp, #12]
|
|
|
80028da: 2b00 cmp r3, #0
|
|
|
80028dc: bfbb ittet lt
|
|
|
80028de: 425b neglt r3, r3
|
|
|
80028e0: f042 0202 orrlt.w r2, r2, #2
|
|
|
80028e4: 9307 strge r3, [sp, #28]
|
|
|
80028e6: 9307 strlt r3, [sp, #28]
|
|
|
80028e8: bfb8 it lt
|
|
|
80028ea: 9204 strlt r2, [sp, #16]
|
|
|
80028ec: 7823 ldrb r3, [r4, #0]
|
|
|
80028ee: 2b2e cmp r3, #46 ; 0x2e
|
|
|
80028f0: d10c bne.n 800290c <_svfiprintf_r+0x130>
|
|
|
80028f2: 7863 ldrb r3, [r4, #1]
|
|
|
80028f4: 2b2a cmp r3, #42 ; 0x2a
|
|
|
80028f6: d135 bne.n 8002964 <_svfiprintf_r+0x188>
|
|
|
80028f8: 9b03 ldr r3, [sp, #12]
|
|
|
80028fa: 3402 adds r4, #2
|
|
|
80028fc: 1d1a adds r2, r3, #4
|
|
|
80028fe: 681b ldr r3, [r3, #0]
|
|
|
8002900: 9203 str r2, [sp, #12]
|
|
|
8002902: 2b00 cmp r3, #0
|
|
|
8002904: bfb8 it lt
|
|
|
8002906: f04f 33ff movlt.w r3, #4294967295
|
|
|
800290a: 9305 str r3, [sp, #20]
|
|
|
800290c: f8df a0bc ldr.w sl, [pc, #188] ; 80029cc <_svfiprintf_r+0x1f0>
|
|
|
8002910: 2203 movs r2, #3
|
|
|
8002912: 4650 mov r0, sl
|
|
|
8002914: 7821 ldrb r1, [r4, #0]
|
|
|
8002916: f000 f9f7 bl 8002d08 <memchr>
|
|
|
800291a: b140 cbz r0, 800292e <_svfiprintf_r+0x152>
|
|
|
800291c: 2340 movs r3, #64 ; 0x40
|
|
|
800291e: eba0 000a sub.w r0, r0, sl
|
|
|
8002922: fa03 f000 lsl.w r0, r3, r0
|
|
|
8002926: 9b04 ldr r3, [sp, #16]
|
|
|
8002928: 3401 adds r4, #1
|
|
|
800292a: 4303 orrs r3, r0
|
|
|
800292c: 9304 str r3, [sp, #16]
|
|
|
800292e: f814 1b01 ldrb.w r1, [r4], #1
|
|
|
8002932: 2206 movs r2, #6
|
|
|
8002934: 4826 ldr r0, [pc, #152] ; (80029d0 <_svfiprintf_r+0x1f4>)
|
|
|
8002936: f88d 1028 strb.w r1, [sp, #40] ; 0x28
|
|
|
800293a: f000 f9e5 bl 8002d08 <memchr>
|
|
|
800293e: 2800 cmp r0, #0
|
|
|
8002940: d038 beq.n 80029b4 <_svfiprintf_r+0x1d8>
|
|
|
8002942: 4b24 ldr r3, [pc, #144] ; (80029d4 <_svfiprintf_r+0x1f8>)
|
|
|
8002944: bb1b cbnz r3, 800298e <_svfiprintf_r+0x1b2>
|
|
|
8002946: 9b03 ldr r3, [sp, #12]
|
|
|
8002948: 3307 adds r3, #7
|
|
|
800294a: f023 0307 bic.w r3, r3, #7
|
|
|
800294e: 3308 adds r3, #8
|
|
|
8002950: 9303 str r3, [sp, #12]
|
|
|
8002952: 9b09 ldr r3, [sp, #36] ; 0x24
|
|
|
8002954: 4433 add r3, r6
|
|
|
8002956: 9309 str r3, [sp, #36] ; 0x24
|
|
|
8002958: e767 b.n 800282a <_svfiprintf_r+0x4e>
|
|
|
800295a: 460c mov r4, r1
|
|
|
800295c: 2001 movs r0, #1
|
|
|
800295e: fb0c 3202 mla r2, ip, r2, r3
|
|
|
8002962: e7a5 b.n 80028b0 <_svfiprintf_r+0xd4>
|
|
|
8002964: 2300 movs r3, #0
|
|
|
8002966: f04f 0c0a mov.w ip, #10
|
|
|
800296a: 4619 mov r1, r3
|
|
|
800296c: 3401 adds r4, #1
|
|
|
800296e: 9305 str r3, [sp, #20]
|
|
|
8002970: 4620 mov r0, r4
|
|
|
8002972: f810 2b01 ldrb.w r2, [r0], #1
|
|
|
8002976: 3a30 subs r2, #48 ; 0x30
|
|
|
8002978: 2a09 cmp r2, #9
|
|
|
800297a: d903 bls.n 8002984 <_svfiprintf_r+0x1a8>
|
|
|
800297c: 2b00 cmp r3, #0
|
|
|
800297e: d0c5 beq.n 800290c <_svfiprintf_r+0x130>
|
|
|
8002980: 9105 str r1, [sp, #20]
|
|
|
8002982: e7c3 b.n 800290c <_svfiprintf_r+0x130>
|
|
|
8002984: 4604 mov r4, r0
|
|
|
8002986: 2301 movs r3, #1
|
|
|
8002988: fb0c 2101 mla r1, ip, r1, r2
|
|
|
800298c: e7f0 b.n 8002970 <_svfiprintf_r+0x194>
|
|
|
800298e: ab03 add r3, sp, #12
|
|
|
8002990: 9300 str r3, [sp, #0]
|
|
|
8002992: 462a mov r2, r5
|
|
|
8002994: 4638 mov r0, r7
|
|
|
8002996: 4b10 ldr r3, [pc, #64] ; (80029d8 <_svfiprintf_r+0x1fc>)
|
|
|
8002998: a904 add r1, sp, #16
|
|
|
800299a: f3af 8000 nop.w
|
|
|
800299e: 1c42 adds r2, r0, #1
|
|
|
80029a0: 4606 mov r6, r0
|
|
|
80029a2: d1d6 bne.n 8002952 <_svfiprintf_r+0x176>
|
|
|
80029a4: 89ab ldrh r3, [r5, #12]
|
|
|
80029a6: 065b lsls r3, r3, #25
|
|
|
80029a8: f53f af2c bmi.w 8002804 <_svfiprintf_r+0x28>
|
|
|
80029ac: 9809 ldr r0, [sp, #36] ; 0x24
|
|
|
80029ae: b01d add sp, #116 ; 0x74
|
|
|
80029b0: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
|
|
|
80029b4: ab03 add r3, sp, #12
|
|
|
80029b6: 9300 str r3, [sp, #0]
|
|
|
80029b8: 462a mov r2, r5
|
|
|
80029ba: 4638 mov r0, r7
|
|
|
80029bc: 4b06 ldr r3, [pc, #24] ; (80029d8 <_svfiprintf_r+0x1fc>)
|
|
|
80029be: a904 add r1, sp, #16
|
|
|
80029c0: f000 f87c bl 8002abc <_printf_i>
|
|
|
80029c4: e7eb b.n 800299e <_svfiprintf_r+0x1c2>
|
|
|
80029c6: bf00 nop
|
|
|
80029c8: 08003028 .word 0x08003028
|
|
|
80029cc: 0800302e .word 0x0800302e
|
|
|
80029d0: 08003032 .word 0x08003032
|
|
|
80029d4: 00000000 .word 0x00000000
|
|
|
80029d8: 08002725 .word 0x08002725
|
|
|
|
|
|
080029dc <_printf_common>:
|
|
|
80029dc: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
|
|
|
80029e0: 4616 mov r6, r2
|
|
|
80029e2: 4699 mov r9, r3
|
|
|
80029e4: 688a ldr r2, [r1, #8]
|
|
|
80029e6: 690b ldr r3, [r1, #16]
|
|
|
80029e8: 4607 mov r7, r0
|
|
|
80029ea: 4293 cmp r3, r2
|
|
|
80029ec: bfb8 it lt
|
|
|
80029ee: 4613 movlt r3, r2
|
|
|
80029f0: 6033 str r3, [r6, #0]
|
|
|
80029f2: f891 2043 ldrb.w r2, [r1, #67] ; 0x43
|
|
|
80029f6: 460c mov r4, r1
|
|
|
80029f8: f8dd 8020 ldr.w r8, [sp, #32]
|
|
|
80029fc: b10a cbz r2, 8002a02 <_printf_common+0x26>
|
|
|
80029fe: 3301 adds r3, #1
|
|
|
8002a00: 6033 str r3, [r6, #0]
|
|
|
8002a02: 6823 ldr r3, [r4, #0]
|
|
|
8002a04: 0699 lsls r1, r3, #26
|
|
|
8002a06: bf42 ittt mi
|
|
|
8002a08: 6833 ldrmi r3, [r6, #0]
|
|
|
8002a0a: 3302 addmi r3, #2
|
|
|
8002a0c: 6033 strmi r3, [r6, #0]
|
|
|
8002a0e: 6825 ldr r5, [r4, #0]
|
|
|
8002a10: f015 0506 ands.w r5, r5, #6
|
|
|
8002a14: d106 bne.n 8002a24 <_printf_common+0x48>
|
|
|
8002a16: f104 0a19 add.w sl, r4, #25
|
|
|
8002a1a: 68e3 ldr r3, [r4, #12]
|
|
|
8002a1c: 6832 ldr r2, [r6, #0]
|
|
|
8002a1e: 1a9b subs r3, r3, r2
|
|
|
8002a20: 42ab cmp r3, r5
|
|
|
8002a22: dc28 bgt.n 8002a76 <_printf_common+0x9a>
|
|
|
8002a24: f894 2043 ldrb.w r2, [r4, #67] ; 0x43
|
|
|
8002a28: 1e13 subs r3, r2, #0
|
|
|
8002a2a: 6822 ldr r2, [r4, #0]
|
|
|
8002a2c: bf18 it ne
|
|
|
8002a2e: 2301 movne r3, #1
|
|
|
8002a30: 0692 lsls r2, r2, #26
|
|
|
8002a32: d42d bmi.n 8002a90 <_printf_common+0xb4>
|
|
|
8002a34: 4649 mov r1, r9
|
|
|
8002a36: 4638 mov r0, r7
|
|
|
8002a38: f104 0243 add.w r2, r4, #67 ; 0x43
|
|
|
8002a3c: 47c0 blx r8
|
|
|
8002a3e: 3001 adds r0, #1
|
|
|
8002a40: d020 beq.n 8002a84 <_printf_common+0xa8>
|
|
|
8002a42: 6823 ldr r3, [r4, #0]
|
|
|
8002a44: 68e5 ldr r5, [r4, #12]
|
|
|
8002a46: f003 0306 and.w r3, r3, #6
|
|
|
8002a4a: 2b04 cmp r3, #4
|
|
|
8002a4c: bf18 it ne
|
|
|
8002a4e: 2500 movne r5, #0
|
|
|
8002a50: 6832 ldr r2, [r6, #0]
|
|
|
8002a52: f04f 0600 mov.w r6, #0
|
|
|
8002a56: 68a3 ldr r3, [r4, #8]
|
|
|
8002a58: bf08 it eq
|
|
|
8002a5a: 1aad subeq r5, r5, r2
|
|
|
8002a5c: 6922 ldr r2, [r4, #16]
|
|
|
8002a5e: bf08 it eq
|
|
|
8002a60: ea25 75e5 biceq.w r5, r5, r5, asr #31
|
|
|
8002a64: 4293 cmp r3, r2
|
|
|
8002a66: bfc4 itt gt
|
|
|
8002a68: 1a9b subgt r3, r3, r2
|
|
|
8002a6a: 18ed addgt r5, r5, r3
|
|
|
8002a6c: 341a adds r4, #26
|
|
|
8002a6e: 42b5 cmp r5, r6
|
|
|
8002a70: d11a bne.n 8002aa8 <_printf_common+0xcc>
|
|
|
8002a72: 2000 movs r0, #0
|
|
|
8002a74: e008 b.n 8002a88 <_printf_common+0xac>
|
|
|
8002a76: 2301 movs r3, #1
|
|
|
8002a78: 4652 mov r2, sl
|
|
|
8002a7a: 4649 mov r1, r9
|
|
|
8002a7c: 4638 mov r0, r7
|
|
|
8002a7e: 47c0 blx r8
|
|
|
8002a80: 3001 adds r0, #1
|
|
|
8002a82: d103 bne.n 8002a8c <_printf_common+0xb0>
|
|
|
8002a84: f04f 30ff mov.w r0, #4294967295
|
|
|
8002a88: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
|
|
|
8002a8c: 3501 adds r5, #1
|
|
|
8002a8e: e7c4 b.n 8002a1a <_printf_common+0x3e>
|
|
|
8002a90: 2030 movs r0, #48 ; 0x30
|
|
|
8002a92: 18e1 adds r1, r4, r3
|
|
|
8002a94: f881 0043 strb.w r0, [r1, #67] ; 0x43
|
|
|
8002a98: 1c5a adds r2, r3, #1
|
|
|
8002a9a: f894 1045 ldrb.w r1, [r4, #69] ; 0x45
|
|
|
8002a9e: 4422 add r2, r4
|
|
|
8002aa0: 3302 adds r3, #2
|
|
|
8002aa2: f882 1043 strb.w r1, [r2, #67] ; 0x43
|
|
|
8002aa6: e7c5 b.n 8002a34 <_printf_common+0x58>
|
|
|
8002aa8: 2301 movs r3, #1
|
|
|
8002aaa: 4622 mov r2, r4
|
|
|
8002aac: 4649 mov r1, r9
|
|
|
8002aae: 4638 mov r0, r7
|
|
|
8002ab0: 47c0 blx r8
|
|
|
8002ab2: 3001 adds r0, #1
|
|
|
8002ab4: d0e6 beq.n 8002a84 <_printf_common+0xa8>
|
|
|
8002ab6: 3601 adds r6, #1
|
|
|
8002ab8: e7d9 b.n 8002a6e <_printf_common+0x92>
|
|
|
...
|
|
|
|
|
|
08002abc <_printf_i>:
|
|
|
8002abc: e92d 47ff stmdb sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, lr}
|
|
|
8002ac0: 7e0f ldrb r7, [r1, #24]
|
|
|
8002ac2: 4691 mov r9, r2
|
|
|
8002ac4: 2f78 cmp r7, #120 ; 0x78
|
|
|
8002ac6: 4680 mov r8, r0
|
|
|
8002ac8: 460c mov r4, r1
|
|
|
8002aca: 469a mov sl, r3
|
|
|
8002acc: 9d0c ldr r5, [sp, #48] ; 0x30
|
|
|
8002ace: f101 0243 add.w r2, r1, #67 ; 0x43
|
|
|
8002ad2: d807 bhi.n 8002ae4 <_printf_i+0x28>
|
|
|
8002ad4: 2f62 cmp r7, #98 ; 0x62
|
|
|
8002ad6: d80a bhi.n 8002aee <_printf_i+0x32>
|
|
|
8002ad8: 2f00 cmp r7, #0
|
|
|
8002ada: f000 80d9 beq.w 8002c90 <_printf_i+0x1d4>
|
|
|
8002ade: 2f58 cmp r7, #88 ; 0x58
|
|
|
8002ae0: f000 80a4 beq.w 8002c2c <_printf_i+0x170>
|
|
|
8002ae4: f104 0542 add.w r5, r4, #66 ; 0x42
|
|
|
8002ae8: f884 7042 strb.w r7, [r4, #66] ; 0x42
|
|
|
8002aec: e03a b.n 8002b64 <_printf_i+0xa8>
|
|
|
8002aee: f1a7 0363 sub.w r3, r7, #99 ; 0x63
|
|
|
8002af2: 2b15 cmp r3, #21
|
|
|
8002af4: d8f6 bhi.n 8002ae4 <_printf_i+0x28>
|
|
|
8002af6: a101 add r1, pc, #4 ; (adr r1, 8002afc <_printf_i+0x40>)
|
|
|
8002af8: f851 f023 ldr.w pc, [r1, r3, lsl #2]
|
|
|
8002afc: 08002b55 .word 0x08002b55
|
|
|
8002b00: 08002b69 .word 0x08002b69
|
|
|
8002b04: 08002ae5 .word 0x08002ae5
|
|
|
8002b08: 08002ae5 .word 0x08002ae5
|
|
|
8002b0c: 08002ae5 .word 0x08002ae5
|
|
|
8002b10: 08002ae5 .word 0x08002ae5
|
|
|
8002b14: 08002b69 .word 0x08002b69
|
|
|
8002b18: 08002ae5 .word 0x08002ae5
|
|
|
8002b1c: 08002ae5 .word 0x08002ae5
|
|
|
8002b20: 08002ae5 .word 0x08002ae5
|
|
|
8002b24: 08002ae5 .word 0x08002ae5
|
|
|
8002b28: 08002c77 .word 0x08002c77
|
|
|
8002b2c: 08002b99 .word 0x08002b99
|
|
|
8002b30: 08002c59 .word 0x08002c59
|
|
|
8002b34: 08002ae5 .word 0x08002ae5
|
|
|
8002b38: 08002ae5 .word 0x08002ae5
|
|
|
8002b3c: 08002c99 .word 0x08002c99
|
|
|
8002b40: 08002ae5 .word 0x08002ae5
|
|
|
8002b44: 08002b99 .word 0x08002b99
|
|
|
8002b48: 08002ae5 .word 0x08002ae5
|
|
|
8002b4c: 08002ae5 .word 0x08002ae5
|
|
|
8002b50: 08002c61 .word 0x08002c61
|
|
|
8002b54: 682b ldr r3, [r5, #0]
|
|
|
8002b56: 1d1a adds r2, r3, #4
|
|
|
8002b58: 681b ldr r3, [r3, #0]
|
|
|
8002b5a: 602a str r2, [r5, #0]
|
|
|
8002b5c: f104 0542 add.w r5, r4, #66 ; 0x42
|
|
|
8002b60: f884 3042 strb.w r3, [r4, #66] ; 0x42
|
|
|
8002b64: 2301 movs r3, #1
|
|
|
8002b66: e0a4 b.n 8002cb2 <_printf_i+0x1f6>
|
|
|
8002b68: 6820 ldr r0, [r4, #0]
|
|
|
8002b6a: 6829 ldr r1, [r5, #0]
|
|
|
8002b6c: 0606 lsls r6, r0, #24
|
|
|
8002b6e: f101 0304 add.w r3, r1, #4
|
|
|
8002b72: d50a bpl.n 8002b8a <_printf_i+0xce>
|
|
|
8002b74: 680e ldr r6, [r1, #0]
|
|
|
8002b76: 602b str r3, [r5, #0]
|
|
|
8002b78: 2e00 cmp r6, #0
|
|
|
8002b7a: da03 bge.n 8002b84 <_printf_i+0xc8>
|
|
|
8002b7c: 232d movs r3, #45 ; 0x2d
|
|
|
8002b7e: 4276 negs r6, r6
|
|
|
8002b80: f884 3043 strb.w r3, [r4, #67] ; 0x43
|
|
|
8002b84: 230a movs r3, #10
|
|
|
8002b86: 485e ldr r0, [pc, #376] ; (8002d00 <_printf_i+0x244>)
|
|
|
8002b88: e019 b.n 8002bbe <_printf_i+0x102>
|
|
|
8002b8a: 680e ldr r6, [r1, #0]
|
|
|
8002b8c: f010 0f40 tst.w r0, #64 ; 0x40
|
|
|
8002b90: 602b str r3, [r5, #0]
|
|
|
8002b92: bf18 it ne
|
|
|
8002b94: b236 sxthne r6, r6
|
|
|
8002b96: e7ef b.n 8002b78 <_printf_i+0xbc>
|
|
|
8002b98: 682b ldr r3, [r5, #0]
|
|
|
8002b9a: 6820 ldr r0, [r4, #0]
|
|
|
8002b9c: 1d19 adds r1, r3, #4
|
|
|
8002b9e: 6029 str r1, [r5, #0]
|
|
|
8002ba0: 0601 lsls r1, r0, #24
|
|
|
8002ba2: d501 bpl.n 8002ba8 <_printf_i+0xec>
|
|
|
8002ba4: 681e ldr r6, [r3, #0]
|
|
|
8002ba6: e002 b.n 8002bae <_printf_i+0xf2>
|
|
|
8002ba8: 0646 lsls r6, r0, #25
|
|
|
8002baa: d5fb bpl.n 8002ba4 <_printf_i+0xe8>
|
|
|
8002bac: 881e ldrh r6, [r3, #0]
|
|
|
8002bae: 2f6f cmp r7, #111 ; 0x6f
|
|
|
8002bb0: bf0c ite eq
|
|
|
8002bb2: 2308 moveq r3, #8
|
|
|
8002bb4: 230a movne r3, #10
|
|
|
8002bb6: 4852 ldr r0, [pc, #328] ; (8002d00 <_printf_i+0x244>)
|
|
|
8002bb8: 2100 movs r1, #0
|
|
|
8002bba: f884 1043 strb.w r1, [r4, #67] ; 0x43
|
|
|
8002bbe: 6865 ldr r5, [r4, #4]
|
|
|
8002bc0: 2d00 cmp r5, #0
|
|
|
8002bc2: bfa8 it ge
|
|
|
8002bc4: 6821 ldrge r1, [r4, #0]
|
|
|
8002bc6: 60a5 str r5, [r4, #8]
|
|
|
8002bc8: bfa4 itt ge
|
|
|
8002bca: f021 0104 bicge.w r1, r1, #4
|
|
|
8002bce: 6021 strge r1, [r4, #0]
|
|
|
8002bd0: b90e cbnz r6, 8002bd6 <_printf_i+0x11a>
|
|
|
8002bd2: 2d00 cmp r5, #0
|
|
|
8002bd4: d04d beq.n 8002c72 <_printf_i+0x1b6>
|
|
|
8002bd6: 4615 mov r5, r2
|
|
|
8002bd8: fbb6 f1f3 udiv r1, r6, r3
|
|
|
8002bdc: fb03 6711 mls r7, r3, r1, r6
|
|
|
8002be0: 5dc7 ldrb r7, [r0, r7]
|
|
|
8002be2: f805 7d01 strb.w r7, [r5, #-1]!
|
|
|
8002be6: 4637 mov r7, r6
|
|
|
8002be8: 42bb cmp r3, r7
|
|
|
8002bea: 460e mov r6, r1
|
|
|
8002bec: d9f4 bls.n 8002bd8 <_printf_i+0x11c>
|
|
|
8002bee: 2b08 cmp r3, #8
|
|
|
8002bf0: d10b bne.n 8002c0a <_printf_i+0x14e>
|
|
|
8002bf2: 6823 ldr r3, [r4, #0]
|
|
|
8002bf4: 07de lsls r6, r3, #31
|
|
|
8002bf6: d508 bpl.n 8002c0a <_printf_i+0x14e>
|
|
|
8002bf8: 6923 ldr r3, [r4, #16]
|
|
|
8002bfa: 6861 ldr r1, [r4, #4]
|
|
|
8002bfc: 4299 cmp r1, r3
|
|
|
8002bfe: bfde ittt le
|
|
|
8002c00: 2330 movle r3, #48 ; 0x30
|
|
|
8002c02: f805 3c01 strble.w r3, [r5, #-1]
|
|
|
8002c06: f105 35ff addle.w r5, r5, #4294967295
|
|
|
8002c0a: 1b52 subs r2, r2, r5
|
|
|
8002c0c: 6122 str r2, [r4, #16]
|
|
|
8002c0e: 464b mov r3, r9
|
|
|
8002c10: 4621 mov r1, r4
|
|
|
8002c12: 4640 mov r0, r8
|
|
|
8002c14: f8cd a000 str.w sl, [sp]
|
|
|
8002c18: aa03 add r2, sp, #12
|
|
|
8002c1a: f7ff fedf bl 80029dc <_printf_common>
|
|
|
8002c1e: 3001 adds r0, #1
|
|
|
8002c20: d14c bne.n 8002cbc <_printf_i+0x200>
|
|
|
8002c22: f04f 30ff mov.w r0, #4294967295
|
|
|
8002c26: b004 add sp, #16
|
|
|
8002c28: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
|
|
|
8002c2c: 4834 ldr r0, [pc, #208] ; (8002d00 <_printf_i+0x244>)
|
|
|
8002c2e: f881 7045 strb.w r7, [r1, #69] ; 0x45
|
|
|
8002c32: 6829 ldr r1, [r5, #0]
|
|
|
8002c34: 6823 ldr r3, [r4, #0]
|
|
|
8002c36: f851 6b04 ldr.w r6, [r1], #4
|
|
|
8002c3a: 6029 str r1, [r5, #0]
|
|
|
8002c3c: 061d lsls r5, r3, #24
|
|
|
8002c3e: d514 bpl.n 8002c6a <_printf_i+0x1ae>
|
|
|
8002c40: 07df lsls r7, r3, #31
|
|
|
8002c42: bf44 itt mi
|
|
|
8002c44: f043 0320 orrmi.w r3, r3, #32
|
|
|
8002c48: 6023 strmi r3, [r4, #0]
|
|
|
8002c4a: b91e cbnz r6, 8002c54 <_printf_i+0x198>
|
|
|
8002c4c: 6823 ldr r3, [r4, #0]
|
|
|
8002c4e: f023 0320 bic.w r3, r3, #32
|
|
|
8002c52: 6023 str r3, [r4, #0]
|
|
|
8002c54: 2310 movs r3, #16
|
|
|
8002c56: e7af b.n 8002bb8 <_printf_i+0xfc>
|
|
|
8002c58: 6823 ldr r3, [r4, #0]
|
|
|
8002c5a: f043 0320 orr.w r3, r3, #32
|
|
|
8002c5e: 6023 str r3, [r4, #0]
|
|
|
8002c60: 2378 movs r3, #120 ; 0x78
|
|
|
8002c62: 4828 ldr r0, [pc, #160] ; (8002d04 <_printf_i+0x248>)
|
|
|
8002c64: f884 3045 strb.w r3, [r4, #69] ; 0x45
|
|
|
8002c68: e7e3 b.n 8002c32 <_printf_i+0x176>
|
|
|
8002c6a: 0659 lsls r1, r3, #25
|
|
|
8002c6c: bf48 it mi
|
|
|
8002c6e: b2b6 uxthmi r6, r6
|
|
|
8002c70: e7e6 b.n 8002c40 <_printf_i+0x184>
|
|
|
8002c72: 4615 mov r5, r2
|
|
|
8002c74: e7bb b.n 8002bee <_printf_i+0x132>
|
|
|
8002c76: 682b ldr r3, [r5, #0]
|
|
|
8002c78: 6826 ldr r6, [r4, #0]
|
|
|
8002c7a: 1d18 adds r0, r3, #4
|
|
|
8002c7c: 6961 ldr r1, [r4, #20]
|
|
|
8002c7e: 6028 str r0, [r5, #0]
|
|
|
8002c80: 0635 lsls r5, r6, #24
|
|
|
8002c82: 681b ldr r3, [r3, #0]
|
|
|
8002c84: d501 bpl.n 8002c8a <_printf_i+0x1ce>
|
|
|
8002c86: 6019 str r1, [r3, #0]
|
|
|
8002c88: e002 b.n 8002c90 <_printf_i+0x1d4>
|
|
|
8002c8a: 0670 lsls r0, r6, #25
|
|
|
8002c8c: d5fb bpl.n 8002c86 <_printf_i+0x1ca>
|
|
|
8002c8e: 8019 strh r1, [r3, #0]
|
|
|
8002c90: 2300 movs r3, #0
|
|
|
8002c92: 4615 mov r5, r2
|
|
|
8002c94: 6123 str r3, [r4, #16]
|
|
|
8002c96: e7ba b.n 8002c0e <_printf_i+0x152>
|
|
|
8002c98: 682b ldr r3, [r5, #0]
|
|
|
8002c9a: 2100 movs r1, #0
|
|
|
8002c9c: 1d1a adds r2, r3, #4
|
|
|
8002c9e: 602a str r2, [r5, #0]
|
|
|
8002ca0: 681d ldr r5, [r3, #0]
|
|
|
8002ca2: 6862 ldr r2, [r4, #4]
|
|
|
8002ca4: 4628 mov r0, r5
|
|
|
8002ca6: f000 f82f bl 8002d08 <memchr>
|
|
|
8002caa: b108 cbz r0, 8002cb0 <_printf_i+0x1f4>
|
|
|
8002cac: 1b40 subs r0, r0, r5
|
|
|
8002cae: 6060 str r0, [r4, #4]
|
|
|
8002cb0: 6863 ldr r3, [r4, #4]
|
|
|
8002cb2: 6123 str r3, [r4, #16]
|
|
|
8002cb4: 2300 movs r3, #0
|
|
|
8002cb6: f884 3043 strb.w r3, [r4, #67] ; 0x43
|
|
|
8002cba: e7a8 b.n 8002c0e <_printf_i+0x152>
|
|
|
8002cbc: 462a mov r2, r5
|
|
|
8002cbe: 4649 mov r1, r9
|
|
|
8002cc0: 4640 mov r0, r8
|
|
|
8002cc2: 6923 ldr r3, [r4, #16]
|
|
|
8002cc4: 47d0 blx sl
|
|
|
8002cc6: 3001 adds r0, #1
|
|
|
8002cc8: d0ab beq.n 8002c22 <_printf_i+0x166>
|
|
|
8002cca: 6823 ldr r3, [r4, #0]
|
|
|
8002ccc: 079b lsls r3, r3, #30
|
|
|
8002cce: d413 bmi.n 8002cf8 <_printf_i+0x23c>
|
|
|
8002cd0: 68e0 ldr r0, [r4, #12]
|
|
|
8002cd2: 9b03 ldr r3, [sp, #12]
|
|
|
8002cd4: 4298 cmp r0, r3
|
|
|
8002cd6: bfb8 it lt
|
|
|
8002cd8: 4618 movlt r0, r3
|
|
|
8002cda: e7a4 b.n 8002c26 <_printf_i+0x16a>
|
|
|
8002cdc: 2301 movs r3, #1
|
|
|
8002cde: 4632 mov r2, r6
|
|
|
8002ce0: 4649 mov r1, r9
|
|
|
8002ce2: 4640 mov r0, r8
|
|
|
8002ce4: 47d0 blx sl
|
|
|
8002ce6: 3001 adds r0, #1
|
|
|
8002ce8: d09b beq.n 8002c22 <_printf_i+0x166>
|
|
|
8002cea: 3501 adds r5, #1
|
|
|
8002cec: 68e3 ldr r3, [r4, #12]
|
|
|
8002cee: 9903 ldr r1, [sp, #12]
|
|
|
8002cf0: 1a5b subs r3, r3, r1
|
|
|
8002cf2: 42ab cmp r3, r5
|
|
|
8002cf4: dcf2 bgt.n 8002cdc <_printf_i+0x220>
|
|
|
8002cf6: e7eb b.n 8002cd0 <_printf_i+0x214>
|
|
|
8002cf8: 2500 movs r5, #0
|
|
|
8002cfa: f104 0619 add.w r6, r4, #25
|
|
|
8002cfe: e7f5 b.n 8002cec <_printf_i+0x230>
|
|
|
8002d00: 08003039 .word 0x08003039
|
|
|
8002d04: 0800304a .word 0x0800304a
|
|
|
|
|
|
08002d08 <memchr>:
|
|
|
8002d08: 4603 mov r3, r0
|
|
|
8002d0a: b510 push {r4, lr}
|
|
|
8002d0c: b2c9 uxtb r1, r1
|
|
|
8002d0e: 4402 add r2, r0
|
|
|
8002d10: 4293 cmp r3, r2
|
|
|
8002d12: 4618 mov r0, r3
|
|
|
8002d14: d101 bne.n 8002d1a <memchr+0x12>
|
|
|
8002d16: 2000 movs r0, #0
|
|
|
8002d18: e003 b.n 8002d22 <memchr+0x1a>
|
|
|
8002d1a: 7804 ldrb r4, [r0, #0]
|
|
|
8002d1c: 3301 adds r3, #1
|
|
|
8002d1e: 428c cmp r4, r1
|
|
|
8002d20: d1f6 bne.n 8002d10 <memchr+0x8>
|
|
|
8002d22: bd10 pop {r4, pc}
|
|
|
|
|
|
08002d24 <memcpy>:
|
|
|
8002d24: 440a add r2, r1
|
|
|
8002d26: 4291 cmp r1, r2
|
|
|
8002d28: f100 33ff add.w r3, r0, #4294967295
|
|
|
8002d2c: d100 bne.n 8002d30 <memcpy+0xc>
|
|
|
8002d2e: 4770 bx lr
|
|
|
8002d30: b510 push {r4, lr}
|
|
|
8002d32: f811 4b01 ldrb.w r4, [r1], #1
|
|
|
8002d36: 4291 cmp r1, r2
|
|
|
8002d38: f803 4f01 strb.w r4, [r3, #1]!
|
|
|
8002d3c: d1f9 bne.n 8002d32 <memcpy+0xe>
|
|
|
8002d3e: bd10 pop {r4, pc}
|
|
|
|
|
|
08002d40 <memmove>:
|
|
|
8002d40: 4288 cmp r0, r1
|
|
|
8002d42: b510 push {r4, lr}
|
|
|
8002d44: eb01 0402 add.w r4, r1, r2
|
|
|
8002d48: d902 bls.n 8002d50 <memmove+0x10>
|
|
|
8002d4a: 4284 cmp r4, r0
|
|
|
8002d4c: 4623 mov r3, r4
|
|
|
8002d4e: d807 bhi.n 8002d60 <memmove+0x20>
|
|
|
8002d50: 1e43 subs r3, r0, #1
|
|
|
8002d52: 42a1 cmp r1, r4
|
|
|
8002d54: d008 beq.n 8002d68 <memmove+0x28>
|
|
|
8002d56: f811 2b01 ldrb.w r2, [r1], #1
|
|
|
8002d5a: f803 2f01 strb.w r2, [r3, #1]!
|
|
|
8002d5e: e7f8 b.n 8002d52 <memmove+0x12>
|
|
|
8002d60: 4601 mov r1, r0
|
|
|
8002d62: 4402 add r2, r0
|
|
|
8002d64: 428a cmp r2, r1
|
|
|
8002d66: d100 bne.n 8002d6a <memmove+0x2a>
|
|
|
8002d68: bd10 pop {r4, pc}
|
|
|
8002d6a: f813 4d01 ldrb.w r4, [r3, #-1]!
|
|
|
8002d6e: f802 4d01 strb.w r4, [r2, #-1]!
|
|
|
8002d72: e7f7 b.n 8002d64 <memmove+0x24>
|
|
|
|
|
|
08002d74 <_free_r>:
|
|
|
8002d74: b538 push {r3, r4, r5, lr}
|
|
|
8002d76: 4605 mov r5, r0
|
|
|
8002d78: 2900 cmp r1, #0
|
|
|
8002d7a: d040 beq.n 8002dfe <_free_r+0x8a>
|
|
|
8002d7c: f851 3c04 ldr.w r3, [r1, #-4]
|
|
|
8002d80: 1f0c subs r4, r1, #4
|
|
|
8002d82: 2b00 cmp r3, #0
|
|
|
8002d84: bfb8 it lt
|
|
|
8002d86: 18e4 addlt r4, r4, r3
|
|
|
8002d88: f000 f910 bl 8002fac <__malloc_lock>
|
|
|
8002d8c: 4a1c ldr r2, [pc, #112] ; (8002e00 <_free_r+0x8c>)
|
|
|
8002d8e: 6813 ldr r3, [r2, #0]
|
|
|
8002d90: b933 cbnz r3, 8002da0 <_free_r+0x2c>
|
|
|
8002d92: 6063 str r3, [r4, #4]
|
|
|
8002d94: 6014 str r4, [r2, #0]
|
|
|
8002d96: 4628 mov r0, r5
|
|
|
8002d98: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr}
|
|
|
8002d9c: f000 b90c b.w 8002fb8 <__malloc_unlock>
|
|
|
8002da0: 42a3 cmp r3, r4
|
|
|
8002da2: d908 bls.n 8002db6 <_free_r+0x42>
|
|
|
8002da4: 6820 ldr r0, [r4, #0]
|
|
|
8002da6: 1821 adds r1, r4, r0
|
|
|
8002da8: 428b cmp r3, r1
|
|
|
8002daa: bf01 itttt eq
|
|
|
8002dac: 6819 ldreq r1, [r3, #0]
|
|
|
8002dae: 685b ldreq r3, [r3, #4]
|
|
|
8002db0: 1809 addeq r1, r1, r0
|
|
|
8002db2: 6021 streq r1, [r4, #0]
|
|
|
8002db4: e7ed b.n 8002d92 <_free_r+0x1e>
|
|
|
8002db6: 461a mov r2, r3
|
|
|
8002db8: 685b ldr r3, [r3, #4]
|
|
|
8002dba: b10b cbz r3, 8002dc0 <_free_r+0x4c>
|
|
|
8002dbc: 42a3 cmp r3, r4
|
|
|
8002dbe: d9fa bls.n 8002db6 <_free_r+0x42>
|
|
|
8002dc0: 6811 ldr r1, [r2, #0]
|
|
|
8002dc2: 1850 adds r0, r2, r1
|
|
|
8002dc4: 42a0 cmp r0, r4
|
|
|
8002dc6: d10b bne.n 8002de0 <_free_r+0x6c>
|
|
|
8002dc8: 6820 ldr r0, [r4, #0]
|
|
|
8002dca: 4401 add r1, r0
|
|
|
8002dcc: 1850 adds r0, r2, r1
|
|
|
8002dce: 4283 cmp r3, r0
|
|
|
8002dd0: 6011 str r1, [r2, #0]
|
|
|
8002dd2: d1e0 bne.n 8002d96 <_free_r+0x22>
|
|
|
8002dd4: 6818 ldr r0, [r3, #0]
|
|
|
8002dd6: 685b ldr r3, [r3, #4]
|
|
|
8002dd8: 4401 add r1, r0
|
|
|
8002dda: 6011 str r1, [r2, #0]
|
|
|
8002ddc: 6053 str r3, [r2, #4]
|
|
|
8002dde: e7da b.n 8002d96 <_free_r+0x22>
|
|
|
8002de0: d902 bls.n 8002de8 <_free_r+0x74>
|
|
|
8002de2: 230c movs r3, #12
|
|
|
8002de4: 602b str r3, [r5, #0]
|
|
|
8002de6: e7d6 b.n 8002d96 <_free_r+0x22>
|
|
|
8002de8: 6820 ldr r0, [r4, #0]
|
|
|
8002dea: 1821 adds r1, r4, r0
|
|
|
8002dec: 428b cmp r3, r1
|
|
|
8002dee: bf01 itttt eq
|
|
|
8002df0: 6819 ldreq r1, [r3, #0]
|
|
|
8002df2: 685b ldreq r3, [r3, #4]
|
|
|
8002df4: 1809 addeq r1, r1, r0
|
|
|
8002df6: 6021 streq r1, [r4, #0]
|
|
|
8002df8: 6063 str r3, [r4, #4]
|
|
|
8002dfa: 6054 str r4, [r2, #4]
|
|
|
8002dfc: e7cb b.n 8002d96 <_free_r+0x22>
|
|
|
8002dfe: bd38 pop {r3, r4, r5, pc}
|
|
|
8002e00: 20000120 .word 0x20000120
|
|
|
|
|
|
08002e04 <sbrk_aligned>:
|
|
|
8002e04: b570 push {r4, r5, r6, lr}
|
|
|
8002e06: 4e0e ldr r6, [pc, #56] ; (8002e40 <sbrk_aligned+0x3c>)
|
|
|
8002e08: 460c mov r4, r1
|
|
|
8002e0a: 6831 ldr r1, [r6, #0]
|
|
|
8002e0c: 4605 mov r5, r0
|
|
|
8002e0e: b911 cbnz r1, 8002e16 <sbrk_aligned+0x12>
|
|
|
8002e10: f000 f8bc bl 8002f8c <_sbrk_r>
|
|
|
8002e14: 6030 str r0, [r6, #0]
|
|
|
8002e16: 4621 mov r1, r4
|
|
|
8002e18: 4628 mov r0, r5
|
|
|
8002e1a: f000 f8b7 bl 8002f8c <_sbrk_r>
|
|
|
8002e1e: 1c43 adds r3, r0, #1
|
|
|
8002e20: d00a beq.n 8002e38 <sbrk_aligned+0x34>
|
|
|
8002e22: 1cc4 adds r4, r0, #3
|
|
|
8002e24: f024 0403 bic.w r4, r4, #3
|
|
|
8002e28: 42a0 cmp r0, r4
|
|
|
8002e2a: d007 beq.n 8002e3c <sbrk_aligned+0x38>
|
|
|
8002e2c: 1a21 subs r1, r4, r0
|
|
|
8002e2e: 4628 mov r0, r5
|
|
|
8002e30: f000 f8ac bl 8002f8c <_sbrk_r>
|
|
|
8002e34: 3001 adds r0, #1
|
|
|
8002e36: d101 bne.n 8002e3c <sbrk_aligned+0x38>
|
|
|
8002e38: f04f 34ff mov.w r4, #4294967295
|
|
|
8002e3c: 4620 mov r0, r4
|
|
|
8002e3e: bd70 pop {r4, r5, r6, pc}
|
|
|
8002e40: 20000124 .word 0x20000124
|
|
|
|
|
|
08002e44 <_malloc_r>:
|
|
|
8002e44: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr}
|
|
|
8002e48: 1ccd adds r5, r1, #3
|
|
|
8002e4a: f025 0503 bic.w r5, r5, #3
|
|
|
8002e4e: 3508 adds r5, #8
|
|
|
8002e50: 2d0c cmp r5, #12
|
|
|
8002e52: bf38 it cc
|
|
|
8002e54: 250c movcc r5, #12
|
|
|
8002e56: 2d00 cmp r5, #0
|
|
|
8002e58: 4607 mov r7, r0
|
|
|
8002e5a: db01 blt.n 8002e60 <_malloc_r+0x1c>
|
|
|
8002e5c: 42a9 cmp r1, r5
|
|
|
8002e5e: d905 bls.n 8002e6c <_malloc_r+0x28>
|
|
|
8002e60: 230c movs r3, #12
|
|
|
8002e62: 2600 movs r6, #0
|
|
|
8002e64: 603b str r3, [r7, #0]
|
|
|
8002e66: 4630 mov r0, r6
|
|
|
8002e68: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc}
|
|
|
8002e6c: 4e2e ldr r6, [pc, #184] ; (8002f28 <_malloc_r+0xe4>)
|
|
|
8002e6e: f000 f89d bl 8002fac <__malloc_lock>
|
|
|
8002e72: 6833 ldr r3, [r6, #0]
|
|
|
8002e74: 461c mov r4, r3
|
|
|
8002e76: bb34 cbnz r4, 8002ec6 <_malloc_r+0x82>
|
|
|
8002e78: 4629 mov r1, r5
|
|
|
8002e7a: 4638 mov r0, r7
|
|
|
8002e7c: f7ff ffc2 bl 8002e04 <sbrk_aligned>
|
|
|
8002e80: 1c43 adds r3, r0, #1
|
|
|
8002e82: 4604 mov r4, r0
|
|
|
8002e84: d14d bne.n 8002f22 <_malloc_r+0xde>
|
|
|
8002e86: 6834 ldr r4, [r6, #0]
|
|
|
8002e88: 4626 mov r6, r4
|
|
|
8002e8a: 2e00 cmp r6, #0
|
|
|
8002e8c: d140 bne.n 8002f10 <_malloc_r+0xcc>
|
|
|
8002e8e: 6823 ldr r3, [r4, #0]
|
|
|
8002e90: 4631 mov r1, r6
|
|
|
8002e92: 4638 mov r0, r7
|
|
|
8002e94: eb04 0803 add.w r8, r4, r3
|
|
|
8002e98: f000 f878 bl 8002f8c <_sbrk_r>
|
|
|
8002e9c: 4580 cmp r8, r0
|
|
|
8002e9e: d13a bne.n 8002f16 <_malloc_r+0xd2>
|
|
|
8002ea0: 6821 ldr r1, [r4, #0]
|
|
|
8002ea2: 3503 adds r5, #3
|
|
|
8002ea4: 1a6d subs r5, r5, r1
|
|
|
8002ea6: f025 0503 bic.w r5, r5, #3
|
|
|
8002eaa: 3508 adds r5, #8
|
|
|
8002eac: 2d0c cmp r5, #12
|
|
|
8002eae: bf38 it cc
|
|
|
8002eb0: 250c movcc r5, #12
|
|
|
8002eb2: 4638 mov r0, r7
|
|
|
8002eb4: 4629 mov r1, r5
|
|
|
8002eb6: f7ff ffa5 bl 8002e04 <sbrk_aligned>
|
|
|
8002eba: 3001 adds r0, #1
|
|
|
8002ebc: d02b beq.n 8002f16 <_malloc_r+0xd2>
|
|
|
8002ebe: 6823 ldr r3, [r4, #0]
|
|
|
8002ec0: 442b add r3, r5
|
|
|
8002ec2: 6023 str r3, [r4, #0]
|
|
|
8002ec4: e00e b.n 8002ee4 <_malloc_r+0xa0>
|
|
|
8002ec6: 6822 ldr r2, [r4, #0]
|
|
|
8002ec8: 1b52 subs r2, r2, r5
|
|
|
8002eca: d41e bmi.n 8002f0a <_malloc_r+0xc6>
|
|
|
8002ecc: 2a0b cmp r2, #11
|
|
|
8002ece: d916 bls.n 8002efe <_malloc_r+0xba>
|
|
|
8002ed0: 1961 adds r1, r4, r5
|
|
|
8002ed2: 42a3 cmp r3, r4
|
|
|
8002ed4: 6025 str r5, [r4, #0]
|
|
|
8002ed6: bf18 it ne
|
|
|
8002ed8: 6059 strne r1, [r3, #4]
|
|
|
8002eda: 6863 ldr r3, [r4, #4]
|
|
|
8002edc: bf08 it eq
|
|
|
8002ede: 6031 streq r1, [r6, #0]
|
|
|
8002ee0: 5162 str r2, [r4, r5]
|
|
|
8002ee2: 604b str r3, [r1, #4]
|
|
|
8002ee4: 4638 mov r0, r7
|
|
|
8002ee6: f104 060b add.w r6, r4, #11
|
|
|
8002eea: f000 f865 bl 8002fb8 <__malloc_unlock>
|
|
|
8002eee: f026 0607 bic.w r6, r6, #7
|
|
|
8002ef2: 1d23 adds r3, r4, #4
|
|
|
8002ef4: 1af2 subs r2, r6, r3
|
|
|
8002ef6: d0b6 beq.n 8002e66 <_malloc_r+0x22>
|
|
|
8002ef8: 1b9b subs r3, r3, r6
|
|
|
8002efa: 50a3 str r3, [r4, r2]
|
|
|
8002efc: e7b3 b.n 8002e66 <_malloc_r+0x22>
|
|
|
8002efe: 6862 ldr r2, [r4, #4]
|
|
|
8002f00: 42a3 cmp r3, r4
|
|
|
8002f02: bf0c ite eq
|
|
|
8002f04: 6032 streq r2, [r6, #0]
|
|
|
8002f06: 605a strne r2, [r3, #4]
|
|
|
8002f08: e7ec b.n 8002ee4 <_malloc_r+0xa0>
|
|
|
8002f0a: 4623 mov r3, r4
|
|
|
8002f0c: 6864 ldr r4, [r4, #4]
|
|
|
8002f0e: e7b2 b.n 8002e76 <_malloc_r+0x32>
|
|
|
8002f10: 4634 mov r4, r6
|
|
|
8002f12: 6876 ldr r6, [r6, #4]
|
|
|
8002f14: e7b9 b.n 8002e8a <_malloc_r+0x46>
|
|
|
8002f16: 230c movs r3, #12
|
|
|
8002f18: 4638 mov r0, r7
|
|
|
8002f1a: 603b str r3, [r7, #0]
|
|
|
8002f1c: f000 f84c bl 8002fb8 <__malloc_unlock>
|
|
|
8002f20: e7a1 b.n 8002e66 <_malloc_r+0x22>
|
|
|
8002f22: 6025 str r5, [r4, #0]
|
|
|
8002f24: e7de b.n 8002ee4 <_malloc_r+0xa0>
|
|
|
8002f26: bf00 nop
|
|
|
8002f28: 20000120 .word 0x20000120
|
|
|
|
|
|
08002f2c <_realloc_r>:
|
|
|
8002f2c: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr}
|
|
|
8002f30: 4680 mov r8, r0
|
|
|
8002f32: 4614 mov r4, r2
|
|
|
8002f34: 460e mov r6, r1
|
|
|
8002f36: b921 cbnz r1, 8002f42 <_realloc_r+0x16>
|
|
|
8002f38: 4611 mov r1, r2
|
|
|
8002f3a: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr}
|
|
|
8002f3e: f7ff bf81 b.w 8002e44 <_malloc_r>
|
|
|
8002f42: b92a cbnz r2, 8002f50 <_realloc_r+0x24>
|
|
|
8002f44: f7ff ff16 bl 8002d74 <_free_r>
|
|
|
8002f48: 4625 mov r5, r4
|
|
|
8002f4a: 4628 mov r0, r5
|
|
|
8002f4c: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc}
|
|
|
8002f50: f000 f838 bl 8002fc4 <_malloc_usable_size_r>
|
|
|
8002f54: 4284 cmp r4, r0
|
|
|
8002f56: 4607 mov r7, r0
|
|
|
8002f58: d802 bhi.n 8002f60 <_realloc_r+0x34>
|
|
|
8002f5a: ebb4 0f50 cmp.w r4, r0, lsr #1
|
|
|
8002f5e: d812 bhi.n 8002f86 <_realloc_r+0x5a>
|
|
|
8002f60: 4621 mov r1, r4
|
|
|
8002f62: 4640 mov r0, r8
|
|
|
8002f64: f7ff ff6e bl 8002e44 <_malloc_r>
|
|
|
8002f68: 4605 mov r5, r0
|
|
|
8002f6a: 2800 cmp r0, #0
|
|
|
8002f6c: d0ed beq.n 8002f4a <_realloc_r+0x1e>
|
|
|
8002f6e: 42bc cmp r4, r7
|
|
|
8002f70: 4622 mov r2, r4
|
|
|
8002f72: 4631 mov r1, r6
|
|
|
8002f74: bf28 it cs
|
|
|
8002f76: 463a movcs r2, r7
|
|
|
8002f78: f7ff fed4 bl 8002d24 <memcpy>
|
|
|
8002f7c: 4631 mov r1, r6
|
|
|
8002f7e: 4640 mov r0, r8
|
|
|
8002f80: f7ff fef8 bl 8002d74 <_free_r>
|
|
|
8002f84: e7e1 b.n 8002f4a <_realloc_r+0x1e>
|
|
|
8002f86: 4635 mov r5, r6
|
|
|
8002f88: e7df b.n 8002f4a <_realloc_r+0x1e>
|
|
|
...
|
|
|
|
|
|
08002f8c <_sbrk_r>:
|
|
|
8002f8c: b538 push {r3, r4, r5, lr}
|
|
|
8002f8e: 2300 movs r3, #0
|
|
|
8002f90: 4d05 ldr r5, [pc, #20] ; (8002fa8 <_sbrk_r+0x1c>)
|
|
|
8002f92: 4604 mov r4, r0
|
|
|
8002f94: 4608 mov r0, r1
|
|
|
8002f96: 602b str r3, [r5, #0]
|
|
|
8002f98: f7fd fe62 bl 8000c60 <_sbrk>
|
|
|
8002f9c: 1c43 adds r3, r0, #1
|
|
|
8002f9e: d102 bne.n 8002fa6 <_sbrk_r+0x1a>
|
|
|
8002fa0: 682b ldr r3, [r5, #0]
|
|
|
8002fa2: b103 cbz r3, 8002fa6 <_sbrk_r+0x1a>
|
|
|
8002fa4: 6023 str r3, [r4, #0]
|
|
|
8002fa6: bd38 pop {r3, r4, r5, pc}
|
|
|
8002fa8: 20000128 .word 0x20000128
|
|
|
|
|
|
08002fac <__malloc_lock>:
|
|
|
8002fac: 4801 ldr r0, [pc, #4] ; (8002fb4 <__malloc_lock+0x8>)
|
|
|
8002fae: f000 b811 b.w 8002fd4 <__retarget_lock_acquire_recursive>
|
|
|
8002fb2: bf00 nop
|
|
|
8002fb4: 2000012c .word 0x2000012c
|
|
|
|
|
|
08002fb8 <__malloc_unlock>:
|
|
|
8002fb8: 4801 ldr r0, [pc, #4] ; (8002fc0 <__malloc_unlock+0x8>)
|
|
|
8002fba: f000 b80c b.w 8002fd6 <__retarget_lock_release_recursive>
|
|
|
8002fbe: bf00 nop
|
|
|
8002fc0: 2000012c .word 0x2000012c
|
|
|
|
|
|
08002fc4 <_malloc_usable_size_r>:
|
|
|
8002fc4: f851 3c04 ldr.w r3, [r1, #-4]
|
|
|
8002fc8: 1f18 subs r0, r3, #4
|
|
|
8002fca: 2b00 cmp r3, #0
|
|
|
8002fcc: bfbc itt lt
|
|
|
8002fce: 580b ldrlt r3, [r1, r0]
|
|
|
8002fd0: 18c0 addlt r0, r0, r3
|
|
|
8002fd2: 4770 bx lr
|
|
|
|
|
|
08002fd4 <__retarget_lock_acquire_recursive>:
|
|
|
8002fd4: 4770 bx lr
|
|
|
|
|
|
08002fd6 <__retarget_lock_release_recursive>:
|
|
|
8002fd6: 4770 bx lr
|
|
|
|
|
|
08002fd8 <_init>:
|
|
|
8002fd8: b5f8 push {r3, r4, r5, r6, r7, lr}
|
|
|
8002fda: bf00 nop
|
|
|
8002fdc: bcf8 pop {r3, r4, r5, r6, r7}
|
|
|
8002fde: bc08 pop {r3}
|
|
|
8002fe0: 469e mov lr, r3
|
|
|
8002fe2: 4770 bx lr
|
|
|
|
|
|
08002fe4 <_fini>:
|
|
|
8002fe4: b5f8 push {r3, r4, r5, r6, r7, lr}
|
|
|
8002fe6: bf00 nop
|
|
|
8002fe8: bcf8 pop {r3, r4, r5, r6, r7}
|
|
|
8002fea: bc08 pop {r3}
|
|
|
8002fec: 469e mov lr, r3
|
|
|
8002fee: 4770 bx lr
|