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stm32-course/Examples/UART/Debug/UART.list

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UART.elf: file format elf32-littlearm
Sections:
Idx Name Size VMA LMA File off Algn
0 .isr_vector 0000010c 08000000 08000000 00010000 2**0
CONTENTS, ALLOC, LOAD, READONLY, DATA
1 .text 00001eb4 0800010c 0800010c 0001010c 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
2 .rodata 00000070 08001fc0 08001fc0 00011fc0 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
3 .ARM.extab 00000000 08002030 08002030 00020070 2**0
CONTENTS
4 .ARM 00000000 08002030 08002030 00020070 2**0
CONTENTS
5 .preinit_array 00000000 08002030 08002030 00020070 2**0
CONTENTS, ALLOC, LOAD, DATA
6 .init_array 00000004 08002030 08002030 00012030 2**2
CONTENTS, ALLOC, LOAD, DATA
7 .fini_array 00000004 08002034 08002034 00012034 2**2
CONTENTS, ALLOC, LOAD, DATA
8 .data 00000070 20000000 08002038 00020000 2**2
CONTENTS, ALLOC, LOAD, DATA
9 .bss 00000078 20000070 080020a8 00020070 2**2
ALLOC
10 ._user_heap_stack 00000600 200000e8 080020a8 000200e8 2**0
ALLOC
11 .ARM.attributes 00000029 00000000 00000000 00020070 2**0
CONTENTS, READONLY
12 .debug_info 00004f07 00000000 00000000 00020099 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
13 .debug_abbrev 000013ad 00000000 00000000 00024fa0 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
14 .debug_aranges 00000638 00000000 00000000 00026350 2**3
CONTENTS, READONLY, DEBUGGING, OCTETS
15 .debug_ranges 000005a0 00000000 00000000 00026988 2**3
CONTENTS, READONLY, DEBUGGING, OCTETS
16 .debug_macro 0001700d 00000000 00000000 00026f28 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
17 .debug_line 000073b7 00000000 00000000 0003df35 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
18 .debug_str 000821cf 00000000 00000000 000452ec 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
19 .comment 00000050 00000000 00000000 000c74bb 2**0
CONTENTS, READONLY
20 .debug_frame 00001b40 00000000 00000000 000c750c 2**2
CONTENTS, READONLY, DEBUGGING, OCTETS
Disassembly of section .text:
0800010c <__do_global_dtors_aux>:
800010c: b510 push {r4, lr}
800010e: 4c05 ldr r4, [pc, #20] ; (8000124 <__do_global_dtors_aux+0x18>)
8000110: 7823 ldrb r3, [r4, #0]
8000112: b933 cbnz r3, 8000122 <__do_global_dtors_aux+0x16>
8000114: 4b04 ldr r3, [pc, #16] ; (8000128 <__do_global_dtors_aux+0x1c>)
8000116: b113 cbz r3, 800011e <__do_global_dtors_aux+0x12>
8000118: 4804 ldr r0, [pc, #16] ; (800012c <__do_global_dtors_aux+0x20>)
800011a: f3af 8000 nop.w
800011e: 2301 movs r3, #1
8000120: 7023 strb r3, [r4, #0]
8000122: bd10 pop {r4, pc}
8000124: 20000070 .word 0x20000070
8000128: 00000000 .word 0x00000000
800012c: 08001fa8 .word 0x08001fa8
08000130 <frame_dummy>:
8000130: b508 push {r3, lr}
8000132: 4b03 ldr r3, [pc, #12] ; (8000140 <frame_dummy+0x10>)
8000134: b11b cbz r3, 800013e <frame_dummy+0xe>
8000136: 4903 ldr r1, [pc, #12] ; (8000144 <frame_dummy+0x14>)
8000138: 4803 ldr r0, [pc, #12] ; (8000148 <frame_dummy+0x18>)
800013a: f3af 8000 nop.w
800013e: bd08 pop {r3, pc}
8000140: 00000000 .word 0x00000000
8000144: 20000074 .word 0x20000074
8000148: 08001fa8 .word 0x08001fa8
0800014c <strlen>:
800014c: 4603 mov r3, r0
800014e: f813 2b01 ldrb.w r2, [r3], #1
8000152: 2a00 cmp r2, #0
8000154: d1fb bne.n 800014e <strlen+0x2>
8000156: 1a18 subs r0, r3, r0
8000158: 3801 subs r0, #1
800015a: 4770 bx lr
0800015c <MX_GPIO_Init>:
* Output
* EVENT_OUT
* EXTI
*/
void MX_GPIO_Init(void)
{
800015c: b480 push {r7}
800015e: b083 sub sp, #12
8000160: af00 add r7, sp, #0
/* GPIO Ports Clock Enable */
__HAL_RCC_GPIOA_CLK_ENABLE();
8000162: 4b08 ldr r3, [pc, #32] ; (8000184 <MX_GPIO_Init+0x28>)
8000164: 699b ldr r3, [r3, #24]
8000166: 4a07 ldr r2, [pc, #28] ; (8000184 <MX_GPIO_Init+0x28>)
8000168: f043 0304 orr.w r3, r3, #4
800016c: 6193 str r3, [r2, #24]
800016e: 4b05 ldr r3, [pc, #20] ; (8000184 <MX_GPIO_Init+0x28>)
8000170: 699b ldr r3, [r3, #24]
8000172: f003 0304 and.w r3, r3, #4
8000176: 607b str r3, [r7, #4]
8000178: 687b ldr r3, [r7, #4]
}
800017a: bf00 nop
800017c: 370c adds r7, #12
800017e: 46bd mov sp, r7
8000180: bc80 pop {r7}
8000182: 4770 bx lr
8000184: 40021000 .word 0x40021000
08000188 <main>:
/**
* @brief The application entry point.
* @retval int
*/
int main(void) {
8000188: b580 push {r7, lr}
800018a: b08e sub sp, #56 ; 0x38
800018c: af00 add r7, sp, #0
/* USER CODE END 1 */
/* MCU Configuration--------------------------------------------------------*/
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
HAL_Init();
800018e: f000 f99f bl 80004d0 <HAL_Init>
/* USER CODE BEGIN Init */
/* USER CODE END Init */
/* Configure the system clock */
SystemClock_Config();
8000192: f000 f82d bl 80001f0 <SystemClock_Config>
/* USER CODE BEGIN SysInit */
/* USER CODE END SysInit */
/* Initialize all configured peripherals */
MX_GPIO_Init();
8000196: f7ff ffe1 bl 800015c <MX_GPIO_Init>
MX_USART2_UART_Init();
800019a: f000 f8ff bl 800039c <MX_USART2_UART_Init>
/* USER CODE END 2 */
/* Infinite loop */
/* USER CODE BEGIN WHILE */
char send_buffer[50] = { 0 };
800019e: 2300 movs r3, #0
80001a0: 607b str r3, [r7, #4]
80001a2: f107 0308 add.w r3, r7, #8
80001a6: 222e movs r2, #46 ; 0x2e
80001a8: 2100 movs r1, #0
80001aa: 4618 mov r0, r3
80001ac: f001 fa7a bl 80016a4 <memset>
uint16_t send_cnt = 0;
80001b0: 2300 movs r3, #0
80001b2: 86fb strh r3, [r7, #54] ; 0x36
while (1) {
sprintf(send_buffer, "Send %d packets\r\n", send_cnt++);
80001b4: 8efb ldrh r3, [r7, #54] ; 0x36
80001b6: 1c5a adds r2, r3, #1
80001b8: 86fa strh r2, [r7, #54] ; 0x36
80001ba: 461a mov r2, r3
80001bc: 1d3b adds r3, r7, #4
80001be: 490a ldr r1, [pc, #40] ; (80001e8 <main+0x60>)
80001c0: 4618 mov r0, r3
80001c2: f001 fa77 bl 80016b4 <siprintf>
HAL_UART_Transmit(&huart2, (uint8_t*) send_buffer, strlen(send_buffer),
80001c6: 1d3b adds r3, r7, #4
80001c8: 4618 mov r0, r3
80001ca: f7ff ffbf bl 800014c <strlen>
80001ce: 4603 mov r3, r0
80001d0: b29a uxth r2, r3
80001d2: 1d39 adds r1, r7, #4
80001d4: 230a movs r3, #10
80001d6: 4805 ldr r0, [pc, #20] ; (80001ec <main+0x64>)
80001d8: f001 f8cf bl 800137a <HAL_UART_Transmit>
10);
HAL_Delay(500);
80001dc: f44f 70fa mov.w r0, #500 ; 0x1f4
80001e0: f000 f9d8 bl 8000594 <HAL_Delay>
sprintf(send_buffer, "Send %d packets\r\n", send_cnt++);
80001e4: e7e6 b.n 80001b4 <main+0x2c>
80001e6: bf00 nop
80001e8: 08001fc0 .word 0x08001fc0
80001ec: 20000090 .word 0x20000090
080001f0 <SystemClock_Config>:
/**
* @brief System Clock Configuration
* @retval None
*/
void SystemClock_Config(void) {
80001f0: b580 push {r7, lr}
80001f2: b090 sub sp, #64 ; 0x40
80001f4: af00 add r7, sp, #0
RCC_OscInitTypeDef RCC_OscInitStruct = { 0 };
80001f6: f107 0318 add.w r3, r7, #24
80001fa: 2228 movs r2, #40 ; 0x28
80001fc: 2100 movs r1, #0
80001fe: 4618 mov r0, r3
8000200: f001 fa50 bl 80016a4 <memset>
RCC_ClkInitTypeDef RCC_ClkInitStruct = { 0 };
8000204: 1d3b adds r3, r7, #4
8000206: 2200 movs r2, #0
8000208: 601a str r2, [r3, #0]
800020a: 605a str r2, [r3, #4]
800020c: 609a str r2, [r3, #8]
800020e: 60da str r2, [r3, #12]
8000210: 611a str r2, [r3, #16]
/** Initializes the RCC Oscillators according to the specified parameters
* in the RCC_OscInitTypeDef structure.
*/
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
8000212: 2302 movs r3, #2
8000214: 61bb str r3, [r7, #24]
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
8000216: 2301 movs r3, #1
8000218: 62bb str r3, [r7, #40] ; 0x28
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
800021a: 2310 movs r3, #16
800021c: 62fb str r3, [r7, #44] ; 0x2c
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
800021e: 2300 movs r3, #0
8000220: 637b str r3, [r7, #52] ; 0x34
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
8000222: f107 0318 add.w r3, r7, #24
8000226: 4618 mov r0, r3
8000228: f000 fc40 bl 8000aac <HAL_RCC_OscConfig>
800022c: 4603 mov r3, r0
800022e: 2b00 cmp r3, #0
8000230: d001 beq.n 8000236 <SystemClock_Config+0x46>
Error_Handler();
8000232: f000 f818 bl 8000266 <Error_Handler>
}
/** Initializes the CPU, AHB and APB buses clocks
*/
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
8000236: 230f movs r3, #15
8000238: 607b str r3, [r7, #4]
| RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;
800023a: 2300 movs r3, #0
800023c: 60bb str r3, [r7, #8]
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
800023e: 2300 movs r3, #0
8000240: 60fb str r3, [r7, #12]
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
8000242: 2300 movs r3, #0
8000244: 613b str r3, [r7, #16]
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
8000246: 2300 movs r3, #0
8000248: 617b str r3, [r7, #20]
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK) {
800024a: 1d3b adds r3, r7, #4
800024c: 2100 movs r1, #0
800024e: 4618 mov r0, r3
8000250: f000 feae bl 8000fb0 <HAL_RCC_ClockConfig>
8000254: 4603 mov r3, r0
8000256: 2b00 cmp r3, #0
8000258: d001 beq.n 800025e <SystemClock_Config+0x6e>
Error_Handler();
800025a: f000 f804 bl 8000266 <Error_Handler>
}
}
800025e: bf00 nop
8000260: 3740 adds r7, #64 ; 0x40
8000262: 46bd mov sp, r7
8000264: bd80 pop {r7, pc}
08000266 <Error_Handler>:
/**
* @brief This function is executed in case of error occurrence.
* @retval None
*/
void Error_Handler(void) {
8000266: b480 push {r7}
8000268: af00 add r7, sp, #0
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__STATIC_FORCEINLINE void __disable_irq(void)
{
__ASM volatile ("cpsid i" : : : "memory");
800026a: b672 cpsid i
}
800026c: bf00 nop
/* USER CODE BEGIN Error_Handler_Debug */
/* User can add his own implementation to report the HAL error return state */
__disable_irq();
while (1) {
800026e: e7fe b.n 800026e <Error_Handler+0x8>
08000270 <HAL_MspInit>:
/* USER CODE END 0 */
/**
* Initializes the Global MSP.
*/
void HAL_MspInit(void)
{
8000270: b480 push {r7}
8000272: b085 sub sp, #20
8000274: af00 add r7, sp, #0
/* USER CODE BEGIN MspInit 0 */
/* USER CODE END MspInit 0 */
__HAL_RCC_AFIO_CLK_ENABLE();
8000276: 4b15 ldr r3, [pc, #84] ; (80002cc <HAL_MspInit+0x5c>)
8000278: 699b ldr r3, [r3, #24]
800027a: 4a14 ldr r2, [pc, #80] ; (80002cc <HAL_MspInit+0x5c>)
800027c: f043 0301 orr.w r3, r3, #1
8000280: 6193 str r3, [r2, #24]
8000282: 4b12 ldr r3, [pc, #72] ; (80002cc <HAL_MspInit+0x5c>)
8000284: 699b ldr r3, [r3, #24]
8000286: f003 0301 and.w r3, r3, #1
800028a: 60bb str r3, [r7, #8]
800028c: 68bb ldr r3, [r7, #8]
__HAL_RCC_PWR_CLK_ENABLE();
800028e: 4b0f ldr r3, [pc, #60] ; (80002cc <HAL_MspInit+0x5c>)
8000290: 69db ldr r3, [r3, #28]
8000292: 4a0e ldr r2, [pc, #56] ; (80002cc <HAL_MspInit+0x5c>)
8000294: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
8000298: 61d3 str r3, [r2, #28]
800029a: 4b0c ldr r3, [pc, #48] ; (80002cc <HAL_MspInit+0x5c>)
800029c: 69db ldr r3, [r3, #28]
800029e: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
80002a2: 607b str r3, [r7, #4]
80002a4: 687b ldr r3, [r7, #4]
/* System interrupt init*/
/** NOJTAG: JTAG-DP Disabled and SW-DP Enabled
*/
__HAL_AFIO_REMAP_SWJ_NOJTAG();
80002a6: 4b0a ldr r3, [pc, #40] ; (80002d0 <HAL_MspInit+0x60>)
80002a8: 685b ldr r3, [r3, #4]
80002aa: 60fb str r3, [r7, #12]
80002ac: 68fb ldr r3, [r7, #12]
80002ae: f023 63e0 bic.w r3, r3, #117440512 ; 0x7000000
80002b2: 60fb str r3, [r7, #12]
80002b4: 68fb ldr r3, [r7, #12]
80002b6: f043 7300 orr.w r3, r3, #33554432 ; 0x2000000
80002ba: 60fb str r3, [r7, #12]
80002bc: 4a04 ldr r2, [pc, #16] ; (80002d0 <HAL_MspInit+0x60>)
80002be: 68fb ldr r3, [r7, #12]
80002c0: 6053 str r3, [r2, #4]
/* USER CODE BEGIN MspInit 1 */
/* USER CODE END MspInit 1 */
}
80002c2: bf00 nop
80002c4: 3714 adds r7, #20
80002c6: 46bd mov sp, r7
80002c8: bc80 pop {r7}
80002ca: 4770 bx lr
80002cc: 40021000 .word 0x40021000
80002d0: 40010000 .word 0x40010000
080002d4 <NMI_Handler>:
/******************************************************************************/
/**
* @brief This function handles Non maskable interrupt.
*/
void NMI_Handler(void)
{
80002d4: b480 push {r7}
80002d6: af00 add r7, sp, #0
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
/* USER CODE END NonMaskableInt_IRQn 0 */
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
while (1)
80002d8: e7fe b.n 80002d8 <NMI_Handler+0x4>
080002da <HardFault_Handler>:
/**
* @brief This function handles Hard fault interrupt.
*/
void HardFault_Handler(void)
{
80002da: b480 push {r7}
80002dc: af00 add r7, sp, #0
/* USER CODE BEGIN HardFault_IRQn 0 */
/* USER CODE END HardFault_IRQn 0 */
while (1)
80002de: e7fe b.n 80002de <HardFault_Handler+0x4>
080002e0 <MemManage_Handler>:
/**
* @brief This function handles Memory management fault.
*/
void MemManage_Handler(void)
{
80002e0: b480 push {r7}
80002e2: af00 add r7, sp, #0
/* USER CODE BEGIN MemoryManagement_IRQn 0 */
/* USER CODE END MemoryManagement_IRQn 0 */
while (1)
80002e4: e7fe b.n 80002e4 <MemManage_Handler+0x4>
080002e6 <BusFault_Handler>:
/**
* @brief This function handles Prefetch fault, memory access fault.
*/
void BusFault_Handler(void)
{
80002e6: b480 push {r7}
80002e8: af00 add r7, sp, #0
/* USER CODE BEGIN BusFault_IRQn 0 */
/* USER CODE END BusFault_IRQn 0 */
while (1)
80002ea: e7fe b.n 80002ea <BusFault_Handler+0x4>
080002ec <UsageFault_Handler>:
/**
* @brief This function handles Undefined instruction or illegal state.
*/
void UsageFault_Handler(void)
{
80002ec: b480 push {r7}
80002ee: af00 add r7, sp, #0
/* USER CODE BEGIN UsageFault_IRQn 0 */
/* USER CODE END UsageFault_IRQn 0 */
while (1)
80002f0: e7fe b.n 80002f0 <UsageFault_Handler+0x4>
080002f2 <SVC_Handler>:
/**
* @brief This function handles System service call via SWI instruction.
*/
void SVC_Handler(void)
{
80002f2: b480 push {r7}
80002f4: af00 add r7, sp, #0
/* USER CODE END SVCall_IRQn 0 */
/* USER CODE BEGIN SVCall_IRQn 1 */
/* USER CODE END SVCall_IRQn 1 */
}
80002f6: bf00 nop
80002f8: 46bd mov sp, r7
80002fa: bc80 pop {r7}
80002fc: 4770 bx lr
080002fe <DebugMon_Handler>:
/**
* @brief This function handles Debug monitor.
*/
void DebugMon_Handler(void)
{
80002fe: b480 push {r7}
8000300: af00 add r7, sp, #0
/* USER CODE END DebugMonitor_IRQn 0 */
/* USER CODE BEGIN DebugMonitor_IRQn 1 */
/* USER CODE END DebugMonitor_IRQn 1 */
}
8000302: bf00 nop
8000304: 46bd mov sp, r7
8000306: bc80 pop {r7}
8000308: 4770 bx lr
0800030a <PendSV_Handler>:
/**
* @brief This function handles Pendable request for system service.
*/
void PendSV_Handler(void)
{
800030a: b480 push {r7}
800030c: af00 add r7, sp, #0
/* USER CODE END PendSV_IRQn 0 */
/* USER CODE BEGIN PendSV_IRQn 1 */
/* USER CODE END PendSV_IRQn 1 */
}
800030e: bf00 nop
8000310: 46bd mov sp, r7
8000312: bc80 pop {r7}
8000314: 4770 bx lr
08000316 <SysTick_Handler>:
/**
* @brief This function handles System tick timer.
*/
void SysTick_Handler(void)
{
8000316: b580 push {r7, lr}
8000318: af00 add r7, sp, #0
/* USER CODE BEGIN SysTick_IRQn 0 */
/* USER CODE END SysTick_IRQn 0 */
HAL_IncTick();
800031a: f000 f91f bl 800055c <HAL_IncTick>
/* USER CODE BEGIN SysTick_IRQn 1 */
/* USER CODE END SysTick_IRQn 1 */
}
800031e: bf00 nop
8000320: bd80 pop {r7, pc}
...
08000324 <_sbrk>:
*
* @param incr Memory size
* @return Pointer to allocated memory
*/
void *_sbrk(ptrdiff_t incr)
{
8000324: b580 push {r7, lr}
8000326: b086 sub sp, #24
8000328: af00 add r7, sp, #0
800032a: 6078 str r0, [r7, #4]
extern uint8_t _end; /* Symbol defined in the linker script */
extern uint8_t _estack; /* Symbol defined in the linker script */
extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */
const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size;
800032c: 4a14 ldr r2, [pc, #80] ; (8000380 <_sbrk+0x5c>)
800032e: 4b15 ldr r3, [pc, #84] ; (8000384 <_sbrk+0x60>)
8000330: 1ad3 subs r3, r2, r3
8000332: 617b str r3, [r7, #20]
const uint8_t *max_heap = (uint8_t *)stack_limit;
8000334: 697b ldr r3, [r7, #20]
8000336: 613b str r3, [r7, #16]
uint8_t *prev_heap_end;
/* Initialize heap end at first call */
if (NULL == __sbrk_heap_end)
8000338: 4b13 ldr r3, [pc, #76] ; (8000388 <_sbrk+0x64>)
800033a: 681b ldr r3, [r3, #0]
800033c: 2b00 cmp r3, #0
800033e: d102 bne.n 8000346 <_sbrk+0x22>
{
__sbrk_heap_end = &_end;
8000340: 4b11 ldr r3, [pc, #68] ; (8000388 <_sbrk+0x64>)
8000342: 4a12 ldr r2, [pc, #72] ; (800038c <_sbrk+0x68>)
8000344: 601a str r2, [r3, #0]
}
/* Protect heap from growing into the reserved MSP stack */
if (__sbrk_heap_end + incr > max_heap)
8000346: 4b10 ldr r3, [pc, #64] ; (8000388 <_sbrk+0x64>)
8000348: 681a ldr r2, [r3, #0]
800034a: 687b ldr r3, [r7, #4]
800034c: 4413 add r3, r2
800034e: 693a ldr r2, [r7, #16]
8000350: 429a cmp r2, r3
8000352: d207 bcs.n 8000364 <_sbrk+0x40>
{
errno = ENOMEM;
8000354: f001 f97c bl 8001650 <__errno>
8000358: 4603 mov r3, r0
800035a: 220c movs r2, #12
800035c: 601a str r2, [r3, #0]
return (void *)-1;
800035e: f04f 33ff mov.w r3, #4294967295
8000362: e009 b.n 8000378 <_sbrk+0x54>
}
prev_heap_end = __sbrk_heap_end;
8000364: 4b08 ldr r3, [pc, #32] ; (8000388 <_sbrk+0x64>)
8000366: 681b ldr r3, [r3, #0]
8000368: 60fb str r3, [r7, #12]
__sbrk_heap_end += incr;
800036a: 4b07 ldr r3, [pc, #28] ; (8000388 <_sbrk+0x64>)
800036c: 681a ldr r2, [r3, #0]
800036e: 687b ldr r3, [r7, #4]
8000370: 4413 add r3, r2
8000372: 4a05 ldr r2, [pc, #20] ; (8000388 <_sbrk+0x64>)
8000374: 6013 str r3, [r2, #0]
return (void *)prev_heap_end;
8000376: 68fb ldr r3, [r7, #12]
}
8000378: 4618 mov r0, r3
800037a: 3718 adds r7, #24
800037c: 46bd mov sp, r7
800037e: bd80 pop {r7, pc}
8000380: 20005000 .word 0x20005000
8000384: 00000400 .word 0x00000400
8000388: 2000008c .word 0x2000008c
800038c: 200000e8 .word 0x200000e8
08000390 <SystemInit>:
* @note This function should be used only after reset.
* @param None
* @retval None
*/
void SystemInit (void)
{
8000390: b480 push {r7}
8000392: af00 add r7, sp, #0
/* Configure the Vector Table location -------------------------------------*/
#if defined(USER_VECT_TAB_ADDRESS)
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
#endif /* USER_VECT_TAB_ADDRESS */
}
8000394: bf00 nop
8000396: 46bd mov sp, r7
8000398: bc80 pop {r7}
800039a: 4770 bx lr
0800039c <MX_USART2_UART_Init>:
UART_HandleTypeDef huart2;
/* USART2 init function */
void MX_USART2_UART_Init(void)
{
800039c: b580 push {r7, lr}
800039e: af00 add r7, sp, #0
/* USER CODE END USART2_Init 0 */
/* USER CODE BEGIN USART2_Init 1 */
/* USER CODE END USART2_Init 1 */
huart2.Instance = USART2;
80003a0: 4b11 ldr r3, [pc, #68] ; (80003e8 <MX_USART2_UART_Init+0x4c>)
80003a2: 4a12 ldr r2, [pc, #72] ; (80003ec <MX_USART2_UART_Init+0x50>)
80003a4: 601a str r2, [r3, #0]
huart2.Init.BaudRate = 115200;
80003a6: 4b10 ldr r3, [pc, #64] ; (80003e8 <MX_USART2_UART_Init+0x4c>)
80003a8: f44f 32e1 mov.w r2, #115200 ; 0x1c200
80003ac: 605a str r2, [r3, #4]
huart2.Init.WordLength = UART_WORDLENGTH_8B;
80003ae: 4b0e ldr r3, [pc, #56] ; (80003e8 <MX_USART2_UART_Init+0x4c>)
80003b0: 2200 movs r2, #0
80003b2: 609a str r2, [r3, #8]
huart2.Init.StopBits = UART_STOPBITS_1;
80003b4: 4b0c ldr r3, [pc, #48] ; (80003e8 <MX_USART2_UART_Init+0x4c>)
80003b6: 2200 movs r2, #0
80003b8: 60da str r2, [r3, #12]
huart2.Init.Parity = UART_PARITY_NONE;
80003ba: 4b0b ldr r3, [pc, #44] ; (80003e8 <MX_USART2_UART_Init+0x4c>)
80003bc: 2200 movs r2, #0
80003be: 611a str r2, [r3, #16]
huart2.Init.Mode = UART_MODE_TX_RX;
80003c0: 4b09 ldr r3, [pc, #36] ; (80003e8 <MX_USART2_UART_Init+0x4c>)
80003c2: 220c movs r2, #12
80003c4: 615a str r2, [r3, #20]
huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE;
80003c6: 4b08 ldr r3, [pc, #32] ; (80003e8 <MX_USART2_UART_Init+0x4c>)
80003c8: 2200 movs r2, #0
80003ca: 619a str r2, [r3, #24]
huart2.Init.OverSampling = UART_OVERSAMPLING_16;
80003cc: 4b06 ldr r3, [pc, #24] ; (80003e8 <MX_USART2_UART_Init+0x4c>)
80003ce: 2200 movs r2, #0
80003d0: 61da str r2, [r3, #28]
if (HAL_UART_Init(&huart2) != HAL_OK)
80003d2: 4805 ldr r0, [pc, #20] ; (80003e8 <MX_USART2_UART_Init+0x4c>)
80003d4: f000 ff84 bl 80012e0 <HAL_UART_Init>
80003d8: 4603 mov r3, r0
80003da: 2b00 cmp r3, #0
80003dc: d001 beq.n 80003e2 <MX_USART2_UART_Init+0x46>
{
Error_Handler();
80003de: f7ff ff42 bl 8000266 <Error_Handler>
}
/* USER CODE BEGIN USART2_Init 2 */
/* USER CODE END USART2_Init 2 */
}
80003e2: bf00 nop
80003e4: bd80 pop {r7, pc}
80003e6: bf00 nop
80003e8: 20000090 .word 0x20000090
80003ec: 40004400 .word 0x40004400
080003f0 <HAL_UART_MspInit>:
void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle)
{
80003f0: b580 push {r7, lr}
80003f2: b088 sub sp, #32
80003f4: af00 add r7, sp, #0
80003f6: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
80003f8: f107 0310 add.w r3, r7, #16
80003fc: 2200 movs r2, #0
80003fe: 601a str r2, [r3, #0]
8000400: 605a str r2, [r3, #4]
8000402: 609a str r2, [r3, #8]
8000404: 60da str r2, [r3, #12]
if(uartHandle->Instance==USART2)
8000406: 687b ldr r3, [r7, #4]
8000408: 681b ldr r3, [r3, #0]
800040a: 4a1b ldr r2, [pc, #108] ; (8000478 <HAL_UART_MspInit+0x88>)
800040c: 4293 cmp r3, r2
800040e: d12f bne.n 8000470 <HAL_UART_MspInit+0x80>
{
/* USER CODE BEGIN USART2_MspInit 0 */
/* USER CODE END USART2_MspInit 0 */
/* USART2 clock enable */
__HAL_RCC_USART2_CLK_ENABLE();
8000410: 4b1a ldr r3, [pc, #104] ; (800047c <HAL_UART_MspInit+0x8c>)
8000412: 69db ldr r3, [r3, #28]
8000414: 4a19 ldr r2, [pc, #100] ; (800047c <HAL_UART_MspInit+0x8c>)
8000416: f443 3300 orr.w r3, r3, #131072 ; 0x20000
800041a: 61d3 str r3, [r2, #28]
800041c: 4b17 ldr r3, [pc, #92] ; (800047c <HAL_UART_MspInit+0x8c>)
800041e: 69db ldr r3, [r3, #28]
8000420: f403 3300 and.w r3, r3, #131072 ; 0x20000
8000424: 60fb str r3, [r7, #12]
8000426: 68fb ldr r3, [r7, #12]
__HAL_RCC_GPIOA_CLK_ENABLE();
8000428: 4b14 ldr r3, [pc, #80] ; (800047c <HAL_UART_MspInit+0x8c>)
800042a: 699b ldr r3, [r3, #24]
800042c: 4a13 ldr r2, [pc, #76] ; (800047c <HAL_UART_MspInit+0x8c>)
800042e: f043 0304 orr.w r3, r3, #4
8000432: 6193 str r3, [r2, #24]
8000434: 4b11 ldr r3, [pc, #68] ; (800047c <HAL_UART_MspInit+0x8c>)
8000436: 699b ldr r3, [r3, #24]
8000438: f003 0304 and.w r3, r3, #4
800043c: 60bb str r3, [r7, #8]
800043e: 68bb ldr r3, [r7, #8]
/**USART2 GPIO Configuration
PA2 ------> USART2_TX
PA3 ------> USART2_RX
*/
GPIO_InitStruct.Pin = GPIO_PIN_2;
8000440: 2304 movs r3, #4
8000442: 613b str r3, [r7, #16]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000444: 2302 movs r3, #2
8000446: 617b str r3, [r7, #20]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
8000448: 2303 movs r3, #3
800044a: 61fb str r3, [r7, #28]
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
800044c: f107 0310 add.w r3, r7, #16
8000450: 4619 mov r1, r3
8000452: 480b ldr r0, [pc, #44] ; (8000480 <HAL_UART_MspInit+0x90>)
8000454: f000 f9a6 bl 80007a4 <HAL_GPIO_Init>
GPIO_InitStruct.Pin = GPIO_PIN_3;
8000458: 2308 movs r3, #8
800045a: 613b str r3, [r7, #16]
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
800045c: 2300 movs r3, #0
800045e: 617b str r3, [r7, #20]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000460: 2300 movs r3, #0
8000462: 61bb str r3, [r7, #24]
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8000464: f107 0310 add.w r3, r7, #16
8000468: 4619 mov r1, r3
800046a: 4805 ldr r0, [pc, #20] ; (8000480 <HAL_UART_MspInit+0x90>)
800046c: f000 f99a bl 80007a4 <HAL_GPIO_Init>
/* USER CODE BEGIN USART2_MspInit 1 */
/* USER CODE END USART2_MspInit 1 */
}
}
8000470: bf00 nop
8000472: 3720 adds r7, #32
8000474: 46bd mov sp, r7
8000476: bd80 pop {r7, pc}
8000478: 40004400 .word 0x40004400
800047c: 40021000 .word 0x40021000
8000480: 40010800 .word 0x40010800
08000484 <Reset_Handler>:
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
8000484: 480c ldr r0, [pc, #48] ; (80004b8 <LoopFillZerobss+0x12>)
ldr r1, =_edata
8000486: 490d ldr r1, [pc, #52] ; (80004bc <LoopFillZerobss+0x16>)
ldr r2, =_sidata
8000488: 4a0d ldr r2, [pc, #52] ; (80004c0 <LoopFillZerobss+0x1a>)
movs r3, #0
800048a: 2300 movs r3, #0
b LoopCopyDataInit
800048c: e002 b.n 8000494 <LoopCopyDataInit>
0800048e <CopyDataInit>:
CopyDataInit:
ldr r4, [r2, r3]
800048e: 58d4 ldr r4, [r2, r3]
str r4, [r0, r3]
8000490: 50c4 str r4, [r0, r3]
adds r3, r3, #4
8000492: 3304 adds r3, #4
08000494 <LoopCopyDataInit>:
LoopCopyDataInit:
adds r4, r0, r3
8000494: 18c4 adds r4, r0, r3
cmp r4, r1
8000496: 428c cmp r4, r1
bcc CopyDataInit
8000498: d3f9 bcc.n 800048e <CopyDataInit>
/* Zero fill the bss segment. */
ldr r2, =_sbss
800049a: 4a0a ldr r2, [pc, #40] ; (80004c4 <LoopFillZerobss+0x1e>)
ldr r4, =_ebss
800049c: 4c0a ldr r4, [pc, #40] ; (80004c8 <LoopFillZerobss+0x22>)
movs r3, #0
800049e: 2300 movs r3, #0
b LoopFillZerobss
80004a0: e001 b.n 80004a6 <LoopFillZerobss>
080004a2 <FillZerobss>:
FillZerobss:
str r3, [r2]
80004a2: 6013 str r3, [r2, #0]
adds r2, r2, #4
80004a4: 3204 adds r2, #4
080004a6 <LoopFillZerobss>:
LoopFillZerobss:
cmp r2, r4
80004a6: 42a2 cmp r2, r4
bcc FillZerobss
80004a8: d3fb bcc.n 80004a2 <FillZerobss>
/* Call the clock system intitialization function.*/
bl SystemInit
80004aa: f7ff ff71 bl 8000390 <SystemInit>
/* Call static constructors */
bl __libc_init_array
80004ae: f001 f8d5 bl 800165c <__libc_init_array>
/* Call the application's entry point.*/
bl main
80004b2: f7ff fe69 bl 8000188 <main>
bx lr
80004b6: 4770 bx lr
ldr r0, =_sdata
80004b8: 20000000 .word 0x20000000
ldr r1, =_edata
80004bc: 20000070 .word 0x20000070
ldr r2, =_sidata
80004c0: 08002038 .word 0x08002038
ldr r2, =_sbss
80004c4: 20000070 .word 0x20000070
ldr r4, =_ebss
80004c8: 200000e8 .word 0x200000e8
080004cc <ADC1_2_IRQHandler>:
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
80004cc: e7fe b.n 80004cc <ADC1_2_IRQHandler>
...
080004d0 <HAL_Init>:
* need to ensure that the SysTick time base is always set to 1 millisecond
* to have correct HAL operation.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_Init(void)
{
80004d0: b580 push {r7, lr}
80004d2: af00 add r7, sp, #0
defined(STM32F102x6) || defined(STM32F102xB) || \
defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || \
defined(STM32F105xC) || defined(STM32F107xC)
/* Prefetch buffer is not available on value line devices */
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
80004d4: 4b08 ldr r3, [pc, #32] ; (80004f8 <HAL_Init+0x28>)
80004d6: 681b ldr r3, [r3, #0]
80004d8: 4a07 ldr r2, [pc, #28] ; (80004f8 <HAL_Init+0x28>)
80004da: f043 0310 orr.w r3, r3, #16
80004de: 6013 str r3, [r2, #0]
#endif
#endif /* PREFETCH_ENABLE */
/* Set Interrupt Group Priority */
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
80004e0: 2003 movs r0, #3
80004e2: f000 f92b bl 800073c <HAL_NVIC_SetPriorityGrouping>
/* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
HAL_InitTick(TICK_INT_PRIORITY);
80004e6: 200f movs r0, #15
80004e8: f000 f808 bl 80004fc <HAL_InitTick>
/* Init the low level hardware */
HAL_MspInit();
80004ec: f7ff fec0 bl 8000270 <HAL_MspInit>
/* Return function status */
return HAL_OK;
80004f0: 2300 movs r3, #0
}
80004f2: 4618 mov r0, r3
80004f4: bd80 pop {r7, pc}
80004f6: bf00 nop
80004f8: 40022000 .word 0x40022000
080004fc <HAL_InitTick>:
* implementation in user file.
* @param TickPriority Tick interrupt priority.
* @retval HAL status
*/
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
80004fc: b580 push {r7, lr}
80004fe: b082 sub sp, #8
8000500: af00 add r7, sp, #0
8000502: 6078 str r0, [r7, #4]
/* Configure the SysTick to have interrupt in 1ms time basis*/
if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U)
8000504: 4b12 ldr r3, [pc, #72] ; (8000550 <HAL_InitTick+0x54>)
8000506: 681a ldr r2, [r3, #0]
8000508: 4b12 ldr r3, [pc, #72] ; (8000554 <HAL_InitTick+0x58>)
800050a: 781b ldrb r3, [r3, #0]
800050c: 4619 mov r1, r3
800050e: f44f 737a mov.w r3, #1000 ; 0x3e8
8000512: fbb3 f3f1 udiv r3, r3, r1
8000516: fbb2 f3f3 udiv r3, r2, r3
800051a: 4618 mov r0, r3
800051c: f000 f935 bl 800078a <HAL_SYSTICK_Config>
8000520: 4603 mov r3, r0
8000522: 2b00 cmp r3, #0
8000524: d001 beq.n 800052a <HAL_InitTick+0x2e>
{
return HAL_ERROR;
8000526: 2301 movs r3, #1
8000528: e00e b.n 8000548 <HAL_InitTick+0x4c>
}
/* Configure the SysTick IRQ priority */
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
800052a: 687b ldr r3, [r7, #4]
800052c: 2b0f cmp r3, #15
800052e: d80a bhi.n 8000546 <HAL_InitTick+0x4a>
{
HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
8000530: 2200 movs r2, #0
8000532: 6879 ldr r1, [r7, #4]
8000534: f04f 30ff mov.w r0, #4294967295
8000538: f000 f90b bl 8000752 <HAL_NVIC_SetPriority>
uwTickPrio = TickPriority;
800053c: 4a06 ldr r2, [pc, #24] ; (8000558 <HAL_InitTick+0x5c>)
800053e: 687b ldr r3, [r7, #4]
8000540: 6013 str r3, [r2, #0]
{
return HAL_ERROR;
}
/* Return function status */
return HAL_OK;
8000542: 2300 movs r3, #0
8000544: e000 b.n 8000548 <HAL_InitTick+0x4c>
return HAL_ERROR;
8000546: 2301 movs r3, #1
}
8000548: 4618 mov r0, r3
800054a: 3708 adds r7, #8
800054c: 46bd mov sp, r7
800054e: bd80 pop {r7, pc}
8000550: 20000000 .word 0x20000000
8000554: 20000008 .word 0x20000008
8000558: 20000004 .word 0x20000004
0800055c <HAL_IncTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval None
*/
__weak void HAL_IncTick(void)
{
800055c: b480 push {r7}
800055e: af00 add r7, sp, #0
uwTick += uwTickFreq;
8000560: 4b05 ldr r3, [pc, #20] ; (8000578 <HAL_IncTick+0x1c>)
8000562: 781b ldrb r3, [r3, #0]
8000564: 461a mov r2, r3
8000566: 4b05 ldr r3, [pc, #20] ; (800057c <HAL_IncTick+0x20>)
8000568: 681b ldr r3, [r3, #0]
800056a: 4413 add r3, r2
800056c: 4a03 ldr r2, [pc, #12] ; (800057c <HAL_IncTick+0x20>)
800056e: 6013 str r3, [r2, #0]
}
8000570: bf00 nop
8000572: 46bd mov sp, r7
8000574: bc80 pop {r7}
8000576: 4770 bx lr
8000578: 20000008 .word 0x20000008
800057c: 200000d4 .word 0x200000d4
08000580 <HAL_GetTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval tick value
*/
__weak uint32_t HAL_GetTick(void)
{
8000580: b480 push {r7}
8000582: af00 add r7, sp, #0
return uwTick;
8000584: 4b02 ldr r3, [pc, #8] ; (8000590 <HAL_GetTick+0x10>)
8000586: 681b ldr r3, [r3, #0]
}
8000588: 4618 mov r0, r3
800058a: 46bd mov sp, r7
800058c: bc80 pop {r7}
800058e: 4770 bx lr
8000590: 200000d4 .word 0x200000d4
08000594 <HAL_Delay>:
* implementations in user file.
* @param Delay specifies the delay time length, in milliseconds.
* @retval None
*/
__weak void HAL_Delay(uint32_t Delay)
{
8000594: b580 push {r7, lr}
8000596: b084 sub sp, #16
8000598: af00 add r7, sp, #0
800059a: 6078 str r0, [r7, #4]
uint32_t tickstart = HAL_GetTick();
800059c: f7ff fff0 bl 8000580 <HAL_GetTick>
80005a0: 60b8 str r0, [r7, #8]
uint32_t wait = Delay;
80005a2: 687b ldr r3, [r7, #4]
80005a4: 60fb str r3, [r7, #12]
/* Add a freq to guarantee minimum wait */
if (wait < HAL_MAX_DELAY)
80005a6: 68fb ldr r3, [r7, #12]
80005a8: f1b3 3fff cmp.w r3, #4294967295
80005ac: d005 beq.n 80005ba <HAL_Delay+0x26>
{
wait += (uint32_t)(uwTickFreq);
80005ae: 4b0a ldr r3, [pc, #40] ; (80005d8 <HAL_Delay+0x44>)
80005b0: 781b ldrb r3, [r3, #0]
80005b2: 461a mov r2, r3
80005b4: 68fb ldr r3, [r7, #12]
80005b6: 4413 add r3, r2
80005b8: 60fb str r3, [r7, #12]
}
while ((HAL_GetTick() - tickstart) < wait)
80005ba: bf00 nop
80005bc: f7ff ffe0 bl 8000580 <HAL_GetTick>
80005c0: 4602 mov r2, r0
80005c2: 68bb ldr r3, [r7, #8]
80005c4: 1ad3 subs r3, r2, r3
80005c6: 68fa ldr r2, [r7, #12]
80005c8: 429a cmp r2, r3
80005ca: d8f7 bhi.n 80005bc <HAL_Delay+0x28>
{
}
}
80005cc: bf00 nop
80005ce: bf00 nop
80005d0: 3710 adds r7, #16
80005d2: 46bd mov sp, r7
80005d4: bd80 pop {r7, pc}
80005d6: bf00 nop
80005d8: 20000008 .word 0x20000008
080005dc <__NVIC_SetPriorityGrouping>:
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Priority grouping field.
*/
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
80005dc: b480 push {r7}
80005de: b085 sub sp, #20
80005e0: af00 add r7, sp, #0
80005e2: 6078 str r0, [r7, #4]
uint32_t reg_value;
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
80005e4: 687b ldr r3, [r7, #4]
80005e6: f003 0307 and.w r3, r3, #7
80005ea: 60fb str r3, [r7, #12]
reg_value = SCB->AIRCR; /* read old register configuration */
80005ec: 4b0c ldr r3, [pc, #48] ; (8000620 <__NVIC_SetPriorityGrouping+0x44>)
80005ee: 68db ldr r3, [r3, #12]
80005f0: 60bb str r3, [r7, #8]
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
80005f2: 68ba ldr r2, [r7, #8]
80005f4: f64f 03ff movw r3, #63743 ; 0xf8ff
80005f8: 4013 ands r3, r2
80005fa: 60bb str r3, [r7, #8]
reg_value = (reg_value |
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
(PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
80005fc: 68fb ldr r3, [r7, #12]
80005fe: 021a lsls r2, r3, #8
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
8000600: 68bb ldr r3, [r7, #8]
8000602: 4313 orrs r3, r2
reg_value = (reg_value |
8000604: f043 63bf orr.w r3, r3, #100139008 ; 0x5f80000
8000608: f443 3300 orr.w r3, r3, #131072 ; 0x20000
800060c: 60bb str r3, [r7, #8]
SCB->AIRCR = reg_value;
800060e: 4a04 ldr r2, [pc, #16] ; (8000620 <__NVIC_SetPriorityGrouping+0x44>)
8000610: 68bb ldr r3, [r7, #8]
8000612: 60d3 str r3, [r2, #12]
}
8000614: bf00 nop
8000616: 3714 adds r7, #20
8000618: 46bd mov sp, r7
800061a: bc80 pop {r7}
800061c: 4770 bx lr
800061e: bf00 nop
8000620: e000ed00 .word 0xe000ed00
08000624 <__NVIC_GetPriorityGrouping>:
\brief Get Priority Grouping
\details Reads the priority grouping field from the NVIC Interrupt Controller.
\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
*/
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
{
8000624: b480 push {r7}
8000626: af00 add r7, sp, #0
return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
8000628: 4b04 ldr r3, [pc, #16] ; (800063c <__NVIC_GetPriorityGrouping+0x18>)
800062a: 68db ldr r3, [r3, #12]
800062c: 0a1b lsrs r3, r3, #8
800062e: f003 0307 and.w r3, r3, #7
}
8000632: 4618 mov r0, r3
8000634: 46bd mov sp, r7
8000636: bc80 pop {r7}
8000638: 4770 bx lr
800063a: bf00 nop
800063c: e000ed00 .word 0xe000ed00
08000640 <__NVIC_SetPriority>:
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
8000640: b480 push {r7}
8000642: b083 sub sp, #12
8000644: af00 add r7, sp, #0
8000646: 4603 mov r3, r0
8000648: 6039 str r1, [r7, #0]
800064a: 71fb strb r3, [r7, #7]
if ((int32_t)(IRQn) >= 0)
800064c: f997 3007 ldrsb.w r3, [r7, #7]
8000650: 2b00 cmp r3, #0
8000652: db0a blt.n 800066a <__NVIC_SetPriority+0x2a>
{
NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
8000654: 683b ldr r3, [r7, #0]
8000656: b2da uxtb r2, r3
8000658: 490c ldr r1, [pc, #48] ; (800068c <__NVIC_SetPriority+0x4c>)
800065a: f997 3007 ldrsb.w r3, [r7, #7]
800065e: 0112 lsls r2, r2, #4
8000660: b2d2 uxtb r2, r2
8000662: 440b add r3, r1
8000664: f883 2300 strb.w r2, [r3, #768] ; 0x300
}
else
{
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
}
}
8000668: e00a b.n 8000680 <__NVIC_SetPriority+0x40>
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
800066a: 683b ldr r3, [r7, #0]
800066c: b2da uxtb r2, r3
800066e: 4908 ldr r1, [pc, #32] ; (8000690 <__NVIC_SetPriority+0x50>)
8000670: 79fb ldrb r3, [r7, #7]
8000672: f003 030f and.w r3, r3, #15
8000676: 3b04 subs r3, #4
8000678: 0112 lsls r2, r2, #4
800067a: b2d2 uxtb r2, r2
800067c: 440b add r3, r1
800067e: 761a strb r2, [r3, #24]
}
8000680: bf00 nop
8000682: 370c adds r7, #12
8000684: 46bd mov sp, r7
8000686: bc80 pop {r7}
8000688: 4770 bx lr
800068a: bf00 nop
800068c: e000e100 .word 0xe000e100
8000690: e000ed00 .word 0xe000ed00
08000694 <NVIC_EncodePriority>:
\param [in] PreemptPriority Preemptive priority value (starting from 0).
\param [in] SubPriority Subpriority value (starting from 0).
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
8000694: b480 push {r7}
8000696: b089 sub sp, #36 ; 0x24
8000698: af00 add r7, sp, #0
800069a: 60f8 str r0, [r7, #12]
800069c: 60b9 str r1, [r7, #8]
800069e: 607a str r2, [r7, #4]
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
80006a0: 68fb ldr r3, [r7, #12]
80006a2: f003 0307 and.w r3, r3, #7
80006a6: 61fb str r3, [r7, #28]
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
80006a8: 69fb ldr r3, [r7, #28]
80006aa: f1c3 0307 rsb r3, r3, #7
80006ae: 2b04 cmp r3, #4
80006b0: bf28 it cs
80006b2: 2304 movcs r3, #4
80006b4: 61bb str r3, [r7, #24]
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
80006b6: 69fb ldr r3, [r7, #28]
80006b8: 3304 adds r3, #4
80006ba: 2b06 cmp r3, #6
80006bc: d902 bls.n 80006c4 <NVIC_EncodePriority+0x30>
80006be: 69fb ldr r3, [r7, #28]
80006c0: 3b03 subs r3, #3
80006c2: e000 b.n 80006c6 <NVIC_EncodePriority+0x32>
80006c4: 2300 movs r3, #0
80006c6: 617b str r3, [r7, #20]
return (
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
80006c8: f04f 32ff mov.w r2, #4294967295
80006cc: 69bb ldr r3, [r7, #24]
80006ce: fa02 f303 lsl.w r3, r2, r3
80006d2: 43da mvns r2, r3
80006d4: 68bb ldr r3, [r7, #8]
80006d6: 401a ands r2, r3
80006d8: 697b ldr r3, [r7, #20]
80006da: 409a lsls r2, r3
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
80006dc: f04f 31ff mov.w r1, #4294967295
80006e0: 697b ldr r3, [r7, #20]
80006e2: fa01 f303 lsl.w r3, r1, r3
80006e6: 43d9 mvns r1, r3
80006e8: 687b ldr r3, [r7, #4]
80006ea: 400b ands r3, r1
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
80006ec: 4313 orrs r3, r2
);
}
80006ee: 4618 mov r0, r3
80006f0: 3724 adds r7, #36 ; 0x24
80006f2: 46bd mov sp, r7
80006f4: bc80 pop {r7}
80006f6: 4770 bx lr
080006f8 <SysTick_Config>:
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
80006f8: b580 push {r7, lr}
80006fa: b082 sub sp, #8
80006fc: af00 add r7, sp, #0
80006fe: 6078 str r0, [r7, #4]
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
8000700: 687b ldr r3, [r7, #4]
8000702: 3b01 subs r3, #1
8000704: f1b3 7f80 cmp.w r3, #16777216 ; 0x1000000
8000708: d301 bcc.n 800070e <SysTick_Config+0x16>
{
return (1UL); /* Reload value impossible */
800070a: 2301 movs r3, #1
800070c: e00f b.n 800072e <SysTick_Config+0x36>
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
800070e: 4a0a ldr r2, [pc, #40] ; (8000738 <SysTick_Config+0x40>)
8000710: 687b ldr r3, [r7, #4]
8000712: 3b01 subs r3, #1
8000714: 6053 str r3, [r2, #4]
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
8000716: 210f movs r1, #15
8000718: f04f 30ff mov.w r0, #4294967295
800071c: f7ff ff90 bl 8000640 <__NVIC_SetPriority>
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
8000720: 4b05 ldr r3, [pc, #20] ; (8000738 <SysTick_Config+0x40>)
8000722: 2200 movs r2, #0
8000724: 609a str r2, [r3, #8]
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
8000726: 4b04 ldr r3, [pc, #16] ; (8000738 <SysTick_Config+0x40>)
8000728: 2207 movs r2, #7
800072a: 601a str r2, [r3, #0]
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
800072c: 2300 movs r3, #0
}
800072e: 4618 mov r0, r3
8000730: 3708 adds r7, #8
8000732: 46bd mov sp, r7
8000734: bd80 pop {r7, pc}
8000736: bf00 nop
8000738: e000e010 .word 0xe000e010
0800073c <HAL_NVIC_SetPriorityGrouping>:
* @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible.
* The pending IRQ priority will be managed only by the subpriority.
* @retval None
*/
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
800073c: b580 push {r7, lr}
800073e: b082 sub sp, #8
8000740: af00 add r7, sp, #0
8000742: 6078 str r0, [r7, #4]
/* Check the parameters */
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
/* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
NVIC_SetPriorityGrouping(PriorityGroup);
8000744: 6878 ldr r0, [r7, #4]
8000746: f7ff ff49 bl 80005dc <__NVIC_SetPriorityGrouping>
}
800074a: bf00 nop
800074c: 3708 adds r7, #8
800074e: 46bd mov sp, r7
8000750: bd80 pop {r7, pc}
08000752 <HAL_NVIC_SetPriority>:
* This parameter can be a value between 0 and 15
* A lower priority value indicates a higher priority.
* @retval None
*/
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
{
8000752: b580 push {r7, lr}
8000754: b086 sub sp, #24
8000756: af00 add r7, sp, #0
8000758: 4603 mov r3, r0
800075a: 60b9 str r1, [r7, #8]
800075c: 607a str r2, [r7, #4]
800075e: 73fb strb r3, [r7, #15]
uint32_t prioritygroup = 0x00U;
8000760: 2300 movs r3, #0
8000762: 617b str r3, [r7, #20]
/* Check the parameters */
assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
prioritygroup = NVIC_GetPriorityGrouping();
8000764: f7ff ff5e bl 8000624 <__NVIC_GetPriorityGrouping>
8000768: 6178 str r0, [r7, #20]
NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
800076a: 687a ldr r2, [r7, #4]
800076c: 68b9 ldr r1, [r7, #8]
800076e: 6978 ldr r0, [r7, #20]
8000770: f7ff ff90 bl 8000694 <NVIC_EncodePriority>
8000774: 4602 mov r2, r0
8000776: f997 300f ldrsb.w r3, [r7, #15]
800077a: 4611 mov r1, r2
800077c: 4618 mov r0, r3
800077e: f7ff ff5f bl 8000640 <__NVIC_SetPriority>
}
8000782: bf00 nop
8000784: 3718 adds r7, #24
8000786: 46bd mov sp, r7
8000788: bd80 pop {r7, pc}
0800078a <HAL_SYSTICK_Config>:
* @param TicksNumb: Specifies the ticks Number of ticks between two interrupts.
* @retval status: - 0 Function succeeded.
* - 1 Function failed.
*/
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
{
800078a: b580 push {r7, lr}
800078c: b082 sub sp, #8
800078e: af00 add r7, sp, #0
8000790: 6078 str r0, [r7, #4]
return SysTick_Config(TicksNumb);
8000792: 6878 ldr r0, [r7, #4]
8000794: f7ff ffb0 bl 80006f8 <SysTick_Config>
8000798: 4603 mov r3, r0
}
800079a: 4618 mov r0, r3
800079c: 3708 adds r7, #8
800079e: 46bd mov sp, r7
80007a0: bd80 pop {r7, pc}
...
080007a4 <HAL_GPIO_Init>:
* @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains
* the configuration information for the specified GPIO peripheral.
* @retval None
*/
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
{
80007a4: b480 push {r7}
80007a6: b08b sub sp, #44 ; 0x2c
80007a8: af00 add r7, sp, #0
80007aa: 6078 str r0, [r7, #4]
80007ac: 6039 str r1, [r7, #0]
uint32_t position = 0x00u;
80007ae: 2300 movs r3, #0
80007b0: 627b str r3, [r7, #36] ; 0x24
uint32_t ioposition;
uint32_t iocurrent;
uint32_t temp;
uint32_t config = 0x00u;
80007b2: 2300 movs r3, #0
80007b4: 623b str r3, [r7, #32]
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
/* Configure the port pins */
while (((GPIO_Init->Pin) >> position) != 0x00u)
80007b6: e169 b.n 8000a8c <HAL_GPIO_Init+0x2e8>
{
/* Get the IO position */
ioposition = (0x01uL << position);
80007b8: 2201 movs r2, #1
80007ba: 6a7b ldr r3, [r7, #36] ; 0x24
80007bc: fa02 f303 lsl.w r3, r2, r3
80007c0: 61fb str r3, [r7, #28]
/* Get the current IO position */
iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition;
80007c2: 683b ldr r3, [r7, #0]
80007c4: 681b ldr r3, [r3, #0]
80007c6: 69fa ldr r2, [r7, #28]
80007c8: 4013 ands r3, r2
80007ca: 61bb str r3, [r7, #24]
if (iocurrent == ioposition)
80007cc: 69ba ldr r2, [r7, #24]
80007ce: 69fb ldr r3, [r7, #28]
80007d0: 429a cmp r2, r3
80007d2: f040 8158 bne.w 8000a86 <HAL_GPIO_Init+0x2e2>
{
/* Check the Alternate function parameters */
assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
/* Based on the required mode, filling config variable with MODEy[1:0] and CNFy[3:2] corresponding bits */
switch (GPIO_Init->Mode)
80007d6: 683b ldr r3, [r7, #0]
80007d8: 685b ldr r3, [r3, #4]
80007da: 4a9a ldr r2, [pc, #616] ; (8000a44 <HAL_GPIO_Init+0x2a0>)
80007dc: 4293 cmp r3, r2
80007de: d05e beq.n 800089e <HAL_GPIO_Init+0xfa>
80007e0: 4a98 ldr r2, [pc, #608] ; (8000a44 <HAL_GPIO_Init+0x2a0>)
80007e2: 4293 cmp r3, r2
80007e4: d875 bhi.n 80008d2 <HAL_GPIO_Init+0x12e>
80007e6: 4a98 ldr r2, [pc, #608] ; (8000a48 <HAL_GPIO_Init+0x2a4>)
80007e8: 4293 cmp r3, r2
80007ea: d058 beq.n 800089e <HAL_GPIO_Init+0xfa>
80007ec: 4a96 ldr r2, [pc, #600] ; (8000a48 <HAL_GPIO_Init+0x2a4>)
80007ee: 4293 cmp r3, r2
80007f0: d86f bhi.n 80008d2 <HAL_GPIO_Init+0x12e>
80007f2: 4a96 ldr r2, [pc, #600] ; (8000a4c <HAL_GPIO_Init+0x2a8>)
80007f4: 4293 cmp r3, r2
80007f6: d052 beq.n 800089e <HAL_GPIO_Init+0xfa>
80007f8: 4a94 ldr r2, [pc, #592] ; (8000a4c <HAL_GPIO_Init+0x2a8>)
80007fa: 4293 cmp r3, r2
80007fc: d869 bhi.n 80008d2 <HAL_GPIO_Init+0x12e>
80007fe: 4a94 ldr r2, [pc, #592] ; (8000a50 <HAL_GPIO_Init+0x2ac>)
8000800: 4293 cmp r3, r2
8000802: d04c beq.n 800089e <HAL_GPIO_Init+0xfa>
8000804: 4a92 ldr r2, [pc, #584] ; (8000a50 <HAL_GPIO_Init+0x2ac>)
8000806: 4293 cmp r3, r2
8000808: d863 bhi.n 80008d2 <HAL_GPIO_Init+0x12e>
800080a: 4a92 ldr r2, [pc, #584] ; (8000a54 <HAL_GPIO_Init+0x2b0>)
800080c: 4293 cmp r3, r2
800080e: d046 beq.n 800089e <HAL_GPIO_Init+0xfa>
8000810: 4a90 ldr r2, [pc, #576] ; (8000a54 <HAL_GPIO_Init+0x2b0>)
8000812: 4293 cmp r3, r2
8000814: d85d bhi.n 80008d2 <HAL_GPIO_Init+0x12e>
8000816: 2b12 cmp r3, #18
8000818: d82a bhi.n 8000870 <HAL_GPIO_Init+0xcc>
800081a: 2b12 cmp r3, #18
800081c: d859 bhi.n 80008d2 <HAL_GPIO_Init+0x12e>
800081e: a201 add r2, pc, #4 ; (adr r2, 8000824 <HAL_GPIO_Init+0x80>)
8000820: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8000824: 0800089f .word 0x0800089f
8000828: 08000879 .word 0x08000879
800082c: 0800088b .word 0x0800088b
8000830: 080008cd .word 0x080008cd
8000834: 080008d3 .word 0x080008d3
8000838: 080008d3 .word 0x080008d3
800083c: 080008d3 .word 0x080008d3
8000840: 080008d3 .word 0x080008d3
8000844: 080008d3 .word 0x080008d3
8000848: 080008d3 .word 0x080008d3
800084c: 080008d3 .word 0x080008d3
8000850: 080008d3 .word 0x080008d3
8000854: 080008d3 .word 0x080008d3
8000858: 080008d3 .word 0x080008d3
800085c: 080008d3 .word 0x080008d3
8000860: 080008d3 .word 0x080008d3
8000864: 080008d3 .word 0x080008d3
8000868: 08000881 .word 0x08000881
800086c: 08000895 .word 0x08000895
8000870: 4a79 ldr r2, [pc, #484] ; (8000a58 <HAL_GPIO_Init+0x2b4>)
8000872: 4293 cmp r3, r2
8000874: d013 beq.n 800089e <HAL_GPIO_Init+0xfa>
config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG;
break;
/* Parameters are checked with assert_param */
default:
break;
8000876: e02c b.n 80008d2 <HAL_GPIO_Init+0x12e>
config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_PP;
8000878: 683b ldr r3, [r7, #0]
800087a: 68db ldr r3, [r3, #12]
800087c: 623b str r3, [r7, #32]
break;
800087e: e029 b.n 80008d4 <HAL_GPIO_Init+0x130>
config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_OD;
8000880: 683b ldr r3, [r7, #0]
8000882: 68db ldr r3, [r3, #12]
8000884: 3304 adds r3, #4
8000886: 623b str r3, [r7, #32]
break;
8000888: e024 b.n 80008d4 <HAL_GPIO_Init+0x130>
config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_PP;
800088a: 683b ldr r3, [r7, #0]
800088c: 68db ldr r3, [r3, #12]
800088e: 3308 adds r3, #8
8000890: 623b str r3, [r7, #32]
break;
8000892: e01f b.n 80008d4 <HAL_GPIO_Init+0x130>
config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_OD;
8000894: 683b ldr r3, [r7, #0]
8000896: 68db ldr r3, [r3, #12]
8000898: 330c adds r3, #12
800089a: 623b str r3, [r7, #32]
break;
800089c: e01a b.n 80008d4 <HAL_GPIO_Init+0x130>
if (GPIO_Init->Pull == GPIO_NOPULL)
800089e: 683b ldr r3, [r7, #0]
80008a0: 689b ldr r3, [r3, #8]
80008a2: 2b00 cmp r3, #0
80008a4: d102 bne.n 80008ac <HAL_GPIO_Init+0x108>
config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_FLOATING;
80008a6: 2304 movs r3, #4
80008a8: 623b str r3, [r7, #32]
break;
80008aa: e013 b.n 80008d4 <HAL_GPIO_Init+0x130>
else if (GPIO_Init->Pull == GPIO_PULLUP)
80008ac: 683b ldr r3, [r7, #0]
80008ae: 689b ldr r3, [r3, #8]
80008b0: 2b01 cmp r3, #1
80008b2: d105 bne.n 80008c0 <HAL_GPIO_Init+0x11c>
config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD;
80008b4: 2308 movs r3, #8
80008b6: 623b str r3, [r7, #32]
GPIOx->BSRR = ioposition;
80008b8: 687b ldr r3, [r7, #4]
80008ba: 69fa ldr r2, [r7, #28]
80008bc: 611a str r2, [r3, #16]
break;
80008be: e009 b.n 80008d4 <HAL_GPIO_Init+0x130>
config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD;
80008c0: 2308 movs r3, #8
80008c2: 623b str r3, [r7, #32]
GPIOx->BRR = ioposition;
80008c4: 687b ldr r3, [r7, #4]
80008c6: 69fa ldr r2, [r7, #28]
80008c8: 615a str r2, [r3, #20]
break;
80008ca: e003 b.n 80008d4 <HAL_GPIO_Init+0x130>
config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG;
80008cc: 2300 movs r3, #0
80008ce: 623b str r3, [r7, #32]
break;
80008d0: e000 b.n 80008d4 <HAL_GPIO_Init+0x130>
break;
80008d2: bf00 nop
}
/* Check if the current bit belongs to first half or last half of the pin count number
in order to address CRH or CRL register*/
configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL : &GPIOx->CRH;
80008d4: 69bb ldr r3, [r7, #24]
80008d6: 2bff cmp r3, #255 ; 0xff
80008d8: d801 bhi.n 80008de <HAL_GPIO_Init+0x13a>
80008da: 687b ldr r3, [r7, #4]
80008dc: e001 b.n 80008e2 <HAL_GPIO_Init+0x13e>
80008de: 687b ldr r3, [r7, #4]
80008e0: 3304 adds r3, #4
80008e2: 617b str r3, [r7, #20]
registeroffset = (iocurrent < GPIO_PIN_8) ? (position << 2u) : ((position - 8u) << 2u);
80008e4: 69bb ldr r3, [r7, #24]
80008e6: 2bff cmp r3, #255 ; 0xff
80008e8: d802 bhi.n 80008f0 <HAL_GPIO_Init+0x14c>
80008ea: 6a7b ldr r3, [r7, #36] ; 0x24
80008ec: 009b lsls r3, r3, #2
80008ee: e002 b.n 80008f6 <HAL_GPIO_Init+0x152>
80008f0: 6a7b ldr r3, [r7, #36] ; 0x24
80008f2: 3b08 subs r3, #8
80008f4: 009b lsls r3, r3, #2
80008f6: 613b str r3, [r7, #16]
/* Apply the new configuration of the pin to the register */
MODIFY_REG((*configregister), ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset), (config << registeroffset));
80008f8: 697b ldr r3, [r7, #20]
80008fa: 681a ldr r2, [r3, #0]
80008fc: 210f movs r1, #15
80008fe: 693b ldr r3, [r7, #16]
8000900: fa01 f303 lsl.w r3, r1, r3
8000904: 43db mvns r3, r3
8000906: 401a ands r2, r3
8000908: 6a39 ldr r1, [r7, #32]
800090a: 693b ldr r3, [r7, #16]
800090c: fa01 f303 lsl.w r3, r1, r3
8000910: 431a orrs r2, r3
8000912: 697b ldr r3, [r7, #20]
8000914: 601a str r2, [r3, #0]
/*--------------------- EXTI Mode Configuration ------------------------*/
/* Configure the External Interrupt or event for the current IO */
if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
8000916: 683b ldr r3, [r7, #0]
8000918: 685b ldr r3, [r3, #4]
800091a: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
800091e: 2b00 cmp r3, #0
8000920: f000 80b1 beq.w 8000a86 <HAL_GPIO_Init+0x2e2>
{
/* Enable AFIO Clock */
__HAL_RCC_AFIO_CLK_ENABLE();
8000924: 4b4d ldr r3, [pc, #308] ; (8000a5c <HAL_GPIO_Init+0x2b8>)
8000926: 699b ldr r3, [r3, #24]
8000928: 4a4c ldr r2, [pc, #304] ; (8000a5c <HAL_GPIO_Init+0x2b8>)
800092a: f043 0301 orr.w r3, r3, #1
800092e: 6193 str r3, [r2, #24]
8000930: 4b4a ldr r3, [pc, #296] ; (8000a5c <HAL_GPIO_Init+0x2b8>)
8000932: 699b ldr r3, [r3, #24]
8000934: f003 0301 and.w r3, r3, #1
8000938: 60bb str r3, [r7, #8]
800093a: 68bb ldr r3, [r7, #8]
temp = AFIO->EXTICR[position >> 2u];
800093c: 4a48 ldr r2, [pc, #288] ; (8000a60 <HAL_GPIO_Init+0x2bc>)
800093e: 6a7b ldr r3, [r7, #36] ; 0x24
8000940: 089b lsrs r3, r3, #2
8000942: 3302 adds r3, #2
8000944: f852 3023 ldr.w r3, [r2, r3, lsl #2]
8000948: 60fb str r3, [r7, #12]
CLEAR_BIT(temp, (0x0Fu) << (4u * (position & 0x03u)));
800094a: 6a7b ldr r3, [r7, #36] ; 0x24
800094c: f003 0303 and.w r3, r3, #3
8000950: 009b lsls r3, r3, #2
8000952: 220f movs r2, #15
8000954: fa02 f303 lsl.w r3, r2, r3
8000958: 43db mvns r3, r3
800095a: 68fa ldr r2, [r7, #12]
800095c: 4013 ands r3, r2
800095e: 60fb str r3, [r7, #12]
SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4u * (position & 0x03u)));
8000960: 687b ldr r3, [r7, #4]
8000962: 4a40 ldr r2, [pc, #256] ; (8000a64 <HAL_GPIO_Init+0x2c0>)
8000964: 4293 cmp r3, r2
8000966: d013 beq.n 8000990 <HAL_GPIO_Init+0x1ec>
8000968: 687b ldr r3, [r7, #4]
800096a: 4a3f ldr r2, [pc, #252] ; (8000a68 <HAL_GPIO_Init+0x2c4>)
800096c: 4293 cmp r3, r2
800096e: d00d beq.n 800098c <HAL_GPIO_Init+0x1e8>
8000970: 687b ldr r3, [r7, #4]
8000972: 4a3e ldr r2, [pc, #248] ; (8000a6c <HAL_GPIO_Init+0x2c8>)
8000974: 4293 cmp r3, r2
8000976: d007 beq.n 8000988 <HAL_GPIO_Init+0x1e4>
8000978: 687b ldr r3, [r7, #4]
800097a: 4a3d ldr r2, [pc, #244] ; (8000a70 <HAL_GPIO_Init+0x2cc>)
800097c: 4293 cmp r3, r2
800097e: d101 bne.n 8000984 <HAL_GPIO_Init+0x1e0>
8000980: 2303 movs r3, #3
8000982: e006 b.n 8000992 <HAL_GPIO_Init+0x1ee>
8000984: 2304 movs r3, #4
8000986: e004 b.n 8000992 <HAL_GPIO_Init+0x1ee>
8000988: 2302 movs r3, #2
800098a: e002 b.n 8000992 <HAL_GPIO_Init+0x1ee>
800098c: 2301 movs r3, #1
800098e: e000 b.n 8000992 <HAL_GPIO_Init+0x1ee>
8000990: 2300 movs r3, #0
8000992: 6a7a ldr r2, [r7, #36] ; 0x24
8000994: f002 0203 and.w r2, r2, #3
8000998: 0092 lsls r2, r2, #2
800099a: 4093 lsls r3, r2
800099c: 68fa ldr r2, [r7, #12]
800099e: 4313 orrs r3, r2
80009a0: 60fb str r3, [r7, #12]
AFIO->EXTICR[position >> 2u] = temp;
80009a2: 492f ldr r1, [pc, #188] ; (8000a60 <HAL_GPIO_Init+0x2bc>)
80009a4: 6a7b ldr r3, [r7, #36] ; 0x24
80009a6: 089b lsrs r3, r3, #2
80009a8: 3302 adds r3, #2
80009aa: 68fa ldr r2, [r7, #12]
80009ac: f841 2023 str.w r2, [r1, r3, lsl #2]
/* Configure the interrupt mask */
if ((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
80009b0: 683b ldr r3, [r7, #0]
80009b2: 685b ldr r3, [r3, #4]
80009b4: f403 3380 and.w r3, r3, #65536 ; 0x10000
80009b8: 2b00 cmp r3, #0
80009ba: d006 beq.n 80009ca <HAL_GPIO_Init+0x226>
{
SET_BIT(EXTI->IMR, iocurrent);
80009bc: 4b2d ldr r3, [pc, #180] ; (8000a74 <HAL_GPIO_Init+0x2d0>)
80009be: 681a ldr r2, [r3, #0]
80009c0: 492c ldr r1, [pc, #176] ; (8000a74 <HAL_GPIO_Init+0x2d0>)
80009c2: 69bb ldr r3, [r7, #24]
80009c4: 4313 orrs r3, r2
80009c6: 600b str r3, [r1, #0]
80009c8: e006 b.n 80009d8 <HAL_GPIO_Init+0x234>
}
else
{
CLEAR_BIT(EXTI->IMR, iocurrent);
80009ca: 4b2a ldr r3, [pc, #168] ; (8000a74 <HAL_GPIO_Init+0x2d0>)
80009cc: 681a ldr r2, [r3, #0]
80009ce: 69bb ldr r3, [r7, #24]
80009d0: 43db mvns r3, r3
80009d2: 4928 ldr r1, [pc, #160] ; (8000a74 <HAL_GPIO_Init+0x2d0>)
80009d4: 4013 ands r3, r2
80009d6: 600b str r3, [r1, #0]
}
/* Configure the event mask */
if ((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
80009d8: 683b ldr r3, [r7, #0]
80009da: 685b ldr r3, [r3, #4]
80009dc: f403 3300 and.w r3, r3, #131072 ; 0x20000
80009e0: 2b00 cmp r3, #0
80009e2: d006 beq.n 80009f2 <HAL_GPIO_Init+0x24e>
{
SET_BIT(EXTI->EMR, iocurrent);
80009e4: 4b23 ldr r3, [pc, #140] ; (8000a74 <HAL_GPIO_Init+0x2d0>)
80009e6: 685a ldr r2, [r3, #4]
80009e8: 4922 ldr r1, [pc, #136] ; (8000a74 <HAL_GPIO_Init+0x2d0>)
80009ea: 69bb ldr r3, [r7, #24]
80009ec: 4313 orrs r3, r2
80009ee: 604b str r3, [r1, #4]
80009f0: e006 b.n 8000a00 <HAL_GPIO_Init+0x25c>
}
else
{
CLEAR_BIT(EXTI->EMR, iocurrent);
80009f2: 4b20 ldr r3, [pc, #128] ; (8000a74 <HAL_GPIO_Init+0x2d0>)
80009f4: 685a ldr r2, [r3, #4]
80009f6: 69bb ldr r3, [r7, #24]
80009f8: 43db mvns r3, r3
80009fa: 491e ldr r1, [pc, #120] ; (8000a74 <HAL_GPIO_Init+0x2d0>)
80009fc: 4013 ands r3, r2
80009fe: 604b str r3, [r1, #4]
}
/* Enable or disable the rising trigger */
if ((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
8000a00: 683b ldr r3, [r7, #0]
8000a02: 685b ldr r3, [r3, #4]
8000a04: f403 1380 and.w r3, r3, #1048576 ; 0x100000
8000a08: 2b00 cmp r3, #0
8000a0a: d006 beq.n 8000a1a <HAL_GPIO_Init+0x276>
{
SET_BIT(EXTI->RTSR, iocurrent);
8000a0c: 4b19 ldr r3, [pc, #100] ; (8000a74 <HAL_GPIO_Init+0x2d0>)
8000a0e: 689a ldr r2, [r3, #8]
8000a10: 4918 ldr r1, [pc, #96] ; (8000a74 <HAL_GPIO_Init+0x2d0>)
8000a12: 69bb ldr r3, [r7, #24]
8000a14: 4313 orrs r3, r2
8000a16: 608b str r3, [r1, #8]
8000a18: e006 b.n 8000a28 <HAL_GPIO_Init+0x284>
}
else
{
CLEAR_BIT(EXTI->RTSR, iocurrent);
8000a1a: 4b16 ldr r3, [pc, #88] ; (8000a74 <HAL_GPIO_Init+0x2d0>)
8000a1c: 689a ldr r2, [r3, #8]
8000a1e: 69bb ldr r3, [r7, #24]
8000a20: 43db mvns r3, r3
8000a22: 4914 ldr r1, [pc, #80] ; (8000a74 <HAL_GPIO_Init+0x2d0>)
8000a24: 4013 ands r3, r2
8000a26: 608b str r3, [r1, #8]
}
/* Enable or disable the falling trigger */
if ((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
8000a28: 683b ldr r3, [r7, #0]
8000a2a: 685b ldr r3, [r3, #4]
8000a2c: f403 1300 and.w r3, r3, #2097152 ; 0x200000
8000a30: 2b00 cmp r3, #0
8000a32: d021 beq.n 8000a78 <HAL_GPIO_Init+0x2d4>
{
SET_BIT(EXTI->FTSR, iocurrent);
8000a34: 4b0f ldr r3, [pc, #60] ; (8000a74 <HAL_GPIO_Init+0x2d0>)
8000a36: 68da ldr r2, [r3, #12]
8000a38: 490e ldr r1, [pc, #56] ; (8000a74 <HAL_GPIO_Init+0x2d0>)
8000a3a: 69bb ldr r3, [r7, #24]
8000a3c: 4313 orrs r3, r2
8000a3e: 60cb str r3, [r1, #12]
8000a40: e021 b.n 8000a86 <HAL_GPIO_Init+0x2e2>
8000a42: bf00 nop
8000a44: 10320000 .word 0x10320000
8000a48: 10310000 .word 0x10310000
8000a4c: 10220000 .word 0x10220000
8000a50: 10210000 .word 0x10210000
8000a54: 10120000 .word 0x10120000
8000a58: 10110000 .word 0x10110000
8000a5c: 40021000 .word 0x40021000
8000a60: 40010000 .word 0x40010000
8000a64: 40010800 .word 0x40010800
8000a68: 40010c00 .word 0x40010c00
8000a6c: 40011000 .word 0x40011000
8000a70: 40011400 .word 0x40011400
8000a74: 40010400 .word 0x40010400
}
else
{
CLEAR_BIT(EXTI->FTSR, iocurrent);
8000a78: 4b0b ldr r3, [pc, #44] ; (8000aa8 <HAL_GPIO_Init+0x304>)
8000a7a: 68da ldr r2, [r3, #12]
8000a7c: 69bb ldr r3, [r7, #24]
8000a7e: 43db mvns r3, r3
8000a80: 4909 ldr r1, [pc, #36] ; (8000aa8 <HAL_GPIO_Init+0x304>)
8000a82: 4013 ands r3, r2
8000a84: 60cb str r3, [r1, #12]
}
}
}
position++;
8000a86: 6a7b ldr r3, [r7, #36] ; 0x24
8000a88: 3301 adds r3, #1
8000a8a: 627b str r3, [r7, #36] ; 0x24
while (((GPIO_Init->Pin) >> position) != 0x00u)
8000a8c: 683b ldr r3, [r7, #0]
8000a8e: 681a ldr r2, [r3, #0]
8000a90: 6a7b ldr r3, [r7, #36] ; 0x24
8000a92: fa22 f303 lsr.w r3, r2, r3
8000a96: 2b00 cmp r3, #0
8000a98: f47f ae8e bne.w 80007b8 <HAL_GPIO_Init+0x14>
}
}
8000a9c: bf00 nop
8000a9e: bf00 nop
8000aa0: 372c adds r7, #44 ; 0x2c
8000aa2: 46bd mov sp, r7
8000aa4: bc80 pop {r7}
8000aa6: 4770 bx lr
8000aa8: 40010400 .word 0x40010400
08000aac <HAL_RCC_OscConfig>:
* supported by this macro. User should request a transition to HSE Off
* first and then HSE On or HSE Bypass.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
{
8000aac: b580 push {r7, lr}
8000aae: b086 sub sp, #24
8000ab0: af00 add r7, sp, #0
8000ab2: 6078 str r0, [r7, #4]
uint32_t tickstart;
uint32_t pll_config;
/* Check Null pointer */
if (RCC_OscInitStruct == NULL)
8000ab4: 687b ldr r3, [r7, #4]
8000ab6: 2b00 cmp r3, #0
8000ab8: d101 bne.n 8000abe <HAL_RCC_OscConfig+0x12>
{
return HAL_ERROR;
8000aba: 2301 movs r3, #1
8000abc: e272 b.n 8000fa4 <HAL_RCC_OscConfig+0x4f8>
/* Check the parameters */
assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
/*------------------------------- HSE Configuration ------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
8000abe: 687b ldr r3, [r7, #4]
8000ac0: 681b ldr r3, [r3, #0]
8000ac2: f003 0301 and.w r3, r3, #1
8000ac6: 2b00 cmp r3, #0
8000ac8: f000 8087 beq.w 8000bda <HAL_RCC_OscConfig+0x12e>
{
/* Check the parameters */
assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
/* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)
8000acc: 4b92 ldr r3, [pc, #584] ; (8000d18 <HAL_RCC_OscConfig+0x26c>)
8000ace: 685b ldr r3, [r3, #4]
8000ad0: f003 030c and.w r3, r3, #12
8000ad4: 2b04 cmp r3, #4
8000ad6: d00c beq.n 8000af2 <HAL_RCC_OscConfig+0x46>
|| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE)))
8000ad8: 4b8f ldr r3, [pc, #572] ; (8000d18 <HAL_RCC_OscConfig+0x26c>)
8000ada: 685b ldr r3, [r3, #4]
8000adc: f003 030c and.w r3, r3, #12
8000ae0: 2b08 cmp r3, #8
8000ae2: d112 bne.n 8000b0a <HAL_RCC_OscConfig+0x5e>
8000ae4: 4b8c ldr r3, [pc, #560] ; (8000d18 <HAL_RCC_OscConfig+0x26c>)
8000ae6: 685b ldr r3, [r3, #4]
8000ae8: f403 3380 and.w r3, r3, #65536 ; 0x10000
8000aec: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
8000af0: d10b bne.n 8000b0a <HAL_RCC_OscConfig+0x5e>
{
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
8000af2: 4b89 ldr r3, [pc, #548] ; (8000d18 <HAL_RCC_OscConfig+0x26c>)
8000af4: 681b ldr r3, [r3, #0]
8000af6: f403 3300 and.w r3, r3, #131072 ; 0x20000
8000afa: 2b00 cmp r3, #0
8000afc: d06c beq.n 8000bd8 <HAL_RCC_OscConfig+0x12c>
8000afe: 687b ldr r3, [r7, #4]
8000b00: 685b ldr r3, [r3, #4]
8000b02: 2b00 cmp r3, #0
8000b04: d168 bne.n 8000bd8 <HAL_RCC_OscConfig+0x12c>
{
return HAL_ERROR;
8000b06: 2301 movs r3, #1
8000b08: e24c b.n 8000fa4 <HAL_RCC_OscConfig+0x4f8>
}
}
else
{
/* Set the new HSE configuration ---------------------------------------*/
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
8000b0a: 687b ldr r3, [r7, #4]
8000b0c: 685b ldr r3, [r3, #4]
8000b0e: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
8000b12: d106 bne.n 8000b22 <HAL_RCC_OscConfig+0x76>
8000b14: 4b80 ldr r3, [pc, #512] ; (8000d18 <HAL_RCC_OscConfig+0x26c>)
8000b16: 681b ldr r3, [r3, #0]
8000b18: 4a7f ldr r2, [pc, #508] ; (8000d18 <HAL_RCC_OscConfig+0x26c>)
8000b1a: f443 3380 orr.w r3, r3, #65536 ; 0x10000
8000b1e: 6013 str r3, [r2, #0]
8000b20: e02e b.n 8000b80 <HAL_RCC_OscConfig+0xd4>
8000b22: 687b ldr r3, [r7, #4]
8000b24: 685b ldr r3, [r3, #4]
8000b26: 2b00 cmp r3, #0
8000b28: d10c bne.n 8000b44 <HAL_RCC_OscConfig+0x98>
8000b2a: 4b7b ldr r3, [pc, #492] ; (8000d18 <HAL_RCC_OscConfig+0x26c>)
8000b2c: 681b ldr r3, [r3, #0]
8000b2e: 4a7a ldr r2, [pc, #488] ; (8000d18 <HAL_RCC_OscConfig+0x26c>)
8000b30: f423 3380 bic.w r3, r3, #65536 ; 0x10000
8000b34: 6013 str r3, [r2, #0]
8000b36: 4b78 ldr r3, [pc, #480] ; (8000d18 <HAL_RCC_OscConfig+0x26c>)
8000b38: 681b ldr r3, [r3, #0]
8000b3a: 4a77 ldr r2, [pc, #476] ; (8000d18 <HAL_RCC_OscConfig+0x26c>)
8000b3c: f423 2380 bic.w r3, r3, #262144 ; 0x40000
8000b40: 6013 str r3, [r2, #0]
8000b42: e01d b.n 8000b80 <HAL_RCC_OscConfig+0xd4>
8000b44: 687b ldr r3, [r7, #4]
8000b46: 685b ldr r3, [r3, #4]
8000b48: f5b3 2fa0 cmp.w r3, #327680 ; 0x50000
8000b4c: d10c bne.n 8000b68 <HAL_RCC_OscConfig+0xbc>
8000b4e: 4b72 ldr r3, [pc, #456] ; (8000d18 <HAL_RCC_OscConfig+0x26c>)
8000b50: 681b ldr r3, [r3, #0]
8000b52: 4a71 ldr r2, [pc, #452] ; (8000d18 <HAL_RCC_OscConfig+0x26c>)
8000b54: f443 2380 orr.w r3, r3, #262144 ; 0x40000
8000b58: 6013 str r3, [r2, #0]
8000b5a: 4b6f ldr r3, [pc, #444] ; (8000d18 <HAL_RCC_OscConfig+0x26c>)
8000b5c: 681b ldr r3, [r3, #0]
8000b5e: 4a6e ldr r2, [pc, #440] ; (8000d18 <HAL_RCC_OscConfig+0x26c>)
8000b60: f443 3380 orr.w r3, r3, #65536 ; 0x10000
8000b64: 6013 str r3, [r2, #0]
8000b66: e00b b.n 8000b80 <HAL_RCC_OscConfig+0xd4>
8000b68: 4b6b ldr r3, [pc, #428] ; (8000d18 <HAL_RCC_OscConfig+0x26c>)
8000b6a: 681b ldr r3, [r3, #0]
8000b6c: 4a6a ldr r2, [pc, #424] ; (8000d18 <HAL_RCC_OscConfig+0x26c>)
8000b6e: f423 3380 bic.w r3, r3, #65536 ; 0x10000
8000b72: 6013 str r3, [r2, #0]
8000b74: 4b68 ldr r3, [pc, #416] ; (8000d18 <HAL_RCC_OscConfig+0x26c>)
8000b76: 681b ldr r3, [r3, #0]
8000b78: 4a67 ldr r2, [pc, #412] ; (8000d18 <HAL_RCC_OscConfig+0x26c>)
8000b7a: f423 2380 bic.w r3, r3, #262144 ; 0x40000
8000b7e: 6013 str r3, [r2, #0]
/* Check the HSE State */
if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
8000b80: 687b ldr r3, [r7, #4]
8000b82: 685b ldr r3, [r3, #4]
8000b84: 2b00 cmp r3, #0
8000b86: d013 beq.n 8000bb0 <HAL_RCC_OscConfig+0x104>
{
/* Get Start Tick */
tickstart = HAL_GetTick();
8000b88: f7ff fcfa bl 8000580 <HAL_GetTick>
8000b8c: 6138 str r0, [r7, #16]
/* Wait till HSE is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
8000b8e: e008 b.n 8000ba2 <HAL_RCC_OscConfig+0xf6>
{
if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
8000b90: f7ff fcf6 bl 8000580 <HAL_GetTick>
8000b94: 4602 mov r2, r0
8000b96: 693b ldr r3, [r7, #16]
8000b98: 1ad3 subs r3, r2, r3
8000b9a: 2b64 cmp r3, #100 ; 0x64
8000b9c: d901 bls.n 8000ba2 <HAL_RCC_OscConfig+0xf6>
{
return HAL_TIMEOUT;
8000b9e: 2303 movs r3, #3
8000ba0: e200 b.n 8000fa4 <HAL_RCC_OscConfig+0x4f8>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
8000ba2: 4b5d ldr r3, [pc, #372] ; (8000d18 <HAL_RCC_OscConfig+0x26c>)
8000ba4: 681b ldr r3, [r3, #0]
8000ba6: f403 3300 and.w r3, r3, #131072 ; 0x20000
8000baa: 2b00 cmp r3, #0
8000bac: d0f0 beq.n 8000b90 <HAL_RCC_OscConfig+0xe4>
8000bae: e014 b.n 8000bda <HAL_RCC_OscConfig+0x12e>
}
}
else
{
/* Get Start Tick */
tickstart = HAL_GetTick();
8000bb0: f7ff fce6 bl 8000580 <HAL_GetTick>
8000bb4: 6138 str r0, [r7, #16]
/* Wait till HSE is disabled */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
8000bb6: e008 b.n 8000bca <HAL_RCC_OscConfig+0x11e>
{
if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
8000bb8: f7ff fce2 bl 8000580 <HAL_GetTick>
8000bbc: 4602 mov r2, r0
8000bbe: 693b ldr r3, [r7, #16]
8000bc0: 1ad3 subs r3, r2, r3
8000bc2: 2b64 cmp r3, #100 ; 0x64
8000bc4: d901 bls.n 8000bca <HAL_RCC_OscConfig+0x11e>
{
return HAL_TIMEOUT;
8000bc6: 2303 movs r3, #3
8000bc8: e1ec b.n 8000fa4 <HAL_RCC_OscConfig+0x4f8>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
8000bca: 4b53 ldr r3, [pc, #332] ; (8000d18 <HAL_RCC_OscConfig+0x26c>)
8000bcc: 681b ldr r3, [r3, #0]
8000bce: f403 3300 and.w r3, r3, #131072 ; 0x20000
8000bd2: 2b00 cmp r3, #0
8000bd4: d1f0 bne.n 8000bb8 <HAL_RCC_OscConfig+0x10c>
8000bd6: e000 b.n 8000bda <HAL_RCC_OscConfig+0x12e>
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
8000bd8: bf00 nop
}
}
}
}
/*----------------------------- HSI Configuration --------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
8000bda: 687b ldr r3, [r7, #4]
8000bdc: 681b ldr r3, [r3, #0]
8000bde: f003 0302 and.w r3, r3, #2
8000be2: 2b00 cmp r3, #0
8000be4: d063 beq.n 8000cae <HAL_RCC_OscConfig+0x202>
/* Check the parameters */
assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
/* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)
8000be6: 4b4c ldr r3, [pc, #304] ; (8000d18 <HAL_RCC_OscConfig+0x26c>)
8000be8: 685b ldr r3, [r3, #4]
8000bea: f003 030c and.w r3, r3, #12
8000bee: 2b00 cmp r3, #0
8000bf0: d00b beq.n 8000c0a <HAL_RCC_OscConfig+0x15e>
|| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI_DIV2)))
8000bf2: 4b49 ldr r3, [pc, #292] ; (8000d18 <HAL_RCC_OscConfig+0x26c>)
8000bf4: 685b ldr r3, [r3, #4]
8000bf6: f003 030c and.w r3, r3, #12
8000bfa: 2b08 cmp r3, #8
8000bfc: d11c bne.n 8000c38 <HAL_RCC_OscConfig+0x18c>
8000bfe: 4b46 ldr r3, [pc, #280] ; (8000d18 <HAL_RCC_OscConfig+0x26c>)
8000c00: 685b ldr r3, [r3, #4]
8000c02: f403 3380 and.w r3, r3, #65536 ; 0x10000
8000c06: 2b00 cmp r3, #0
8000c08: d116 bne.n 8000c38 <HAL_RCC_OscConfig+0x18c>
{
/* When HSI is used as system clock it will not disabled */
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
8000c0a: 4b43 ldr r3, [pc, #268] ; (8000d18 <HAL_RCC_OscConfig+0x26c>)
8000c0c: 681b ldr r3, [r3, #0]
8000c0e: f003 0302 and.w r3, r3, #2
8000c12: 2b00 cmp r3, #0
8000c14: d005 beq.n 8000c22 <HAL_RCC_OscConfig+0x176>
8000c16: 687b ldr r3, [r7, #4]
8000c18: 691b ldr r3, [r3, #16]
8000c1a: 2b01 cmp r3, #1
8000c1c: d001 beq.n 8000c22 <HAL_RCC_OscConfig+0x176>
{
return HAL_ERROR;
8000c1e: 2301 movs r3, #1
8000c20: e1c0 b.n 8000fa4 <HAL_RCC_OscConfig+0x4f8>
}
/* Otherwise, just the calibration is allowed */
else
{
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
8000c22: 4b3d ldr r3, [pc, #244] ; (8000d18 <HAL_RCC_OscConfig+0x26c>)
8000c24: 681b ldr r3, [r3, #0]
8000c26: f023 02f8 bic.w r2, r3, #248 ; 0xf8
8000c2a: 687b ldr r3, [r7, #4]
8000c2c: 695b ldr r3, [r3, #20]
8000c2e: 00db lsls r3, r3, #3
8000c30: 4939 ldr r1, [pc, #228] ; (8000d18 <HAL_RCC_OscConfig+0x26c>)
8000c32: 4313 orrs r3, r2
8000c34: 600b str r3, [r1, #0]
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
8000c36: e03a b.n 8000cae <HAL_RCC_OscConfig+0x202>
}
}
else
{
/* Check the HSI State */
if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
8000c38: 687b ldr r3, [r7, #4]
8000c3a: 691b ldr r3, [r3, #16]
8000c3c: 2b00 cmp r3, #0
8000c3e: d020 beq.n 8000c82 <HAL_RCC_OscConfig+0x1d6>
{
/* Enable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_ENABLE();
8000c40: 4b36 ldr r3, [pc, #216] ; (8000d1c <HAL_RCC_OscConfig+0x270>)
8000c42: 2201 movs r2, #1
8000c44: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8000c46: f7ff fc9b bl 8000580 <HAL_GetTick>
8000c4a: 6138 str r0, [r7, #16]
/* Wait till HSI is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
8000c4c: e008 b.n 8000c60 <HAL_RCC_OscConfig+0x1b4>
{
if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
8000c4e: f7ff fc97 bl 8000580 <HAL_GetTick>
8000c52: 4602 mov r2, r0
8000c54: 693b ldr r3, [r7, #16]
8000c56: 1ad3 subs r3, r2, r3
8000c58: 2b02 cmp r3, #2
8000c5a: d901 bls.n 8000c60 <HAL_RCC_OscConfig+0x1b4>
{
return HAL_TIMEOUT;
8000c5c: 2303 movs r3, #3
8000c5e: e1a1 b.n 8000fa4 <HAL_RCC_OscConfig+0x4f8>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
8000c60: 4b2d ldr r3, [pc, #180] ; (8000d18 <HAL_RCC_OscConfig+0x26c>)
8000c62: 681b ldr r3, [r3, #0]
8000c64: f003 0302 and.w r3, r3, #2
8000c68: 2b00 cmp r3, #0
8000c6a: d0f0 beq.n 8000c4e <HAL_RCC_OscConfig+0x1a2>
}
}
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
8000c6c: 4b2a ldr r3, [pc, #168] ; (8000d18 <HAL_RCC_OscConfig+0x26c>)
8000c6e: 681b ldr r3, [r3, #0]
8000c70: f023 02f8 bic.w r2, r3, #248 ; 0xf8
8000c74: 687b ldr r3, [r7, #4]
8000c76: 695b ldr r3, [r3, #20]
8000c78: 00db lsls r3, r3, #3
8000c7a: 4927 ldr r1, [pc, #156] ; (8000d18 <HAL_RCC_OscConfig+0x26c>)
8000c7c: 4313 orrs r3, r2
8000c7e: 600b str r3, [r1, #0]
8000c80: e015 b.n 8000cae <HAL_RCC_OscConfig+0x202>
}
else
{
/* Disable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_DISABLE();
8000c82: 4b26 ldr r3, [pc, #152] ; (8000d1c <HAL_RCC_OscConfig+0x270>)
8000c84: 2200 movs r2, #0
8000c86: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8000c88: f7ff fc7a bl 8000580 <HAL_GetTick>
8000c8c: 6138 str r0, [r7, #16]
/* Wait till HSI is disabled */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
8000c8e: e008 b.n 8000ca2 <HAL_RCC_OscConfig+0x1f6>
{
if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
8000c90: f7ff fc76 bl 8000580 <HAL_GetTick>
8000c94: 4602 mov r2, r0
8000c96: 693b ldr r3, [r7, #16]
8000c98: 1ad3 subs r3, r2, r3
8000c9a: 2b02 cmp r3, #2
8000c9c: d901 bls.n 8000ca2 <HAL_RCC_OscConfig+0x1f6>
{
return HAL_TIMEOUT;
8000c9e: 2303 movs r3, #3
8000ca0: e180 b.n 8000fa4 <HAL_RCC_OscConfig+0x4f8>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
8000ca2: 4b1d ldr r3, [pc, #116] ; (8000d18 <HAL_RCC_OscConfig+0x26c>)
8000ca4: 681b ldr r3, [r3, #0]
8000ca6: f003 0302 and.w r3, r3, #2
8000caa: 2b00 cmp r3, #0
8000cac: d1f0 bne.n 8000c90 <HAL_RCC_OscConfig+0x1e4>
}
}
}
}
/*------------------------------ LSI Configuration -------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
8000cae: 687b ldr r3, [r7, #4]
8000cb0: 681b ldr r3, [r3, #0]
8000cb2: f003 0308 and.w r3, r3, #8
8000cb6: 2b00 cmp r3, #0
8000cb8: d03a beq.n 8000d30 <HAL_RCC_OscConfig+0x284>
{
/* Check the parameters */
assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
/* Check the LSI State */
if (RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
8000cba: 687b ldr r3, [r7, #4]
8000cbc: 699b ldr r3, [r3, #24]
8000cbe: 2b00 cmp r3, #0
8000cc0: d019 beq.n 8000cf6 <HAL_RCC_OscConfig+0x24a>
{
/* Enable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_ENABLE();
8000cc2: 4b17 ldr r3, [pc, #92] ; (8000d20 <HAL_RCC_OscConfig+0x274>)
8000cc4: 2201 movs r2, #1
8000cc6: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8000cc8: f7ff fc5a bl 8000580 <HAL_GetTick>
8000ccc: 6138 str r0, [r7, #16]
/* Wait till LSI is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
8000cce: e008 b.n 8000ce2 <HAL_RCC_OscConfig+0x236>
{
if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
8000cd0: f7ff fc56 bl 8000580 <HAL_GetTick>
8000cd4: 4602 mov r2, r0
8000cd6: 693b ldr r3, [r7, #16]
8000cd8: 1ad3 subs r3, r2, r3
8000cda: 2b02 cmp r3, #2
8000cdc: d901 bls.n 8000ce2 <HAL_RCC_OscConfig+0x236>
{
return HAL_TIMEOUT;
8000cde: 2303 movs r3, #3
8000ce0: e160 b.n 8000fa4 <HAL_RCC_OscConfig+0x4f8>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
8000ce2: 4b0d ldr r3, [pc, #52] ; (8000d18 <HAL_RCC_OscConfig+0x26c>)
8000ce4: 6a5b ldr r3, [r3, #36] ; 0x24
8000ce6: f003 0302 and.w r3, r3, #2
8000cea: 2b00 cmp r3, #0
8000cec: d0f0 beq.n 8000cd0 <HAL_RCC_OscConfig+0x224>
}
}
/* To have a fully stabilized clock in the specified range, a software delay of 1ms
should be added.*/
RCC_Delay(1);
8000cee: 2001 movs r0, #1
8000cf0: f000 fad8 bl 80012a4 <RCC_Delay>
8000cf4: e01c b.n 8000d30 <HAL_RCC_OscConfig+0x284>
}
else
{
/* Disable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_DISABLE();
8000cf6: 4b0a ldr r3, [pc, #40] ; (8000d20 <HAL_RCC_OscConfig+0x274>)
8000cf8: 2200 movs r2, #0
8000cfa: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8000cfc: f7ff fc40 bl 8000580 <HAL_GetTick>
8000d00: 6138 str r0, [r7, #16]
/* Wait till LSI is disabled */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
8000d02: e00f b.n 8000d24 <HAL_RCC_OscConfig+0x278>
{
if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
8000d04: f7ff fc3c bl 8000580 <HAL_GetTick>
8000d08: 4602 mov r2, r0
8000d0a: 693b ldr r3, [r7, #16]
8000d0c: 1ad3 subs r3, r2, r3
8000d0e: 2b02 cmp r3, #2
8000d10: d908 bls.n 8000d24 <HAL_RCC_OscConfig+0x278>
{
return HAL_TIMEOUT;
8000d12: 2303 movs r3, #3
8000d14: e146 b.n 8000fa4 <HAL_RCC_OscConfig+0x4f8>
8000d16: bf00 nop
8000d18: 40021000 .word 0x40021000
8000d1c: 42420000 .word 0x42420000
8000d20: 42420480 .word 0x42420480
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
8000d24: 4b92 ldr r3, [pc, #584] ; (8000f70 <HAL_RCC_OscConfig+0x4c4>)
8000d26: 6a5b ldr r3, [r3, #36] ; 0x24
8000d28: f003 0302 and.w r3, r3, #2
8000d2c: 2b00 cmp r3, #0
8000d2e: d1e9 bne.n 8000d04 <HAL_RCC_OscConfig+0x258>
}
}
}
}
/*------------------------------ LSE Configuration -------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
8000d30: 687b ldr r3, [r7, #4]
8000d32: 681b ldr r3, [r3, #0]
8000d34: f003 0304 and.w r3, r3, #4
8000d38: 2b00 cmp r3, #0
8000d3a: f000 80a6 beq.w 8000e8a <HAL_RCC_OscConfig+0x3de>
{
FlagStatus pwrclkchanged = RESET;
8000d3e: 2300 movs r3, #0
8000d40: 75fb strb r3, [r7, #23]
/* Check the parameters */
assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
/* Update LSE configuration in Backup Domain control register */
/* Requires to enable write access to Backup Domain of necessary */
if (__HAL_RCC_PWR_IS_CLK_DISABLED())
8000d42: 4b8b ldr r3, [pc, #556] ; (8000f70 <HAL_RCC_OscConfig+0x4c4>)
8000d44: 69db ldr r3, [r3, #28]
8000d46: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
8000d4a: 2b00 cmp r3, #0
8000d4c: d10d bne.n 8000d6a <HAL_RCC_OscConfig+0x2be>
{
__HAL_RCC_PWR_CLK_ENABLE();
8000d4e: 4b88 ldr r3, [pc, #544] ; (8000f70 <HAL_RCC_OscConfig+0x4c4>)
8000d50: 69db ldr r3, [r3, #28]
8000d52: 4a87 ldr r2, [pc, #540] ; (8000f70 <HAL_RCC_OscConfig+0x4c4>)
8000d54: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
8000d58: 61d3 str r3, [r2, #28]
8000d5a: 4b85 ldr r3, [pc, #532] ; (8000f70 <HAL_RCC_OscConfig+0x4c4>)
8000d5c: 69db ldr r3, [r3, #28]
8000d5e: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
8000d62: 60bb str r3, [r7, #8]
8000d64: 68bb ldr r3, [r7, #8]
pwrclkchanged = SET;
8000d66: 2301 movs r3, #1
8000d68: 75fb strb r3, [r7, #23]
}
if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
8000d6a: 4b82 ldr r3, [pc, #520] ; (8000f74 <HAL_RCC_OscConfig+0x4c8>)
8000d6c: 681b ldr r3, [r3, #0]
8000d6e: f403 7380 and.w r3, r3, #256 ; 0x100
8000d72: 2b00 cmp r3, #0
8000d74: d118 bne.n 8000da8 <HAL_RCC_OscConfig+0x2fc>
{
/* Enable write access to Backup domain */
SET_BIT(PWR->CR, PWR_CR_DBP);
8000d76: 4b7f ldr r3, [pc, #508] ; (8000f74 <HAL_RCC_OscConfig+0x4c8>)
8000d78: 681b ldr r3, [r3, #0]
8000d7a: 4a7e ldr r2, [pc, #504] ; (8000f74 <HAL_RCC_OscConfig+0x4c8>)
8000d7c: f443 7380 orr.w r3, r3, #256 ; 0x100
8000d80: 6013 str r3, [r2, #0]
/* Wait for Backup domain Write protection disable */
tickstart = HAL_GetTick();
8000d82: f7ff fbfd bl 8000580 <HAL_GetTick>
8000d86: 6138 str r0, [r7, #16]
while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
8000d88: e008 b.n 8000d9c <HAL_RCC_OscConfig+0x2f0>
{
if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
8000d8a: f7ff fbf9 bl 8000580 <HAL_GetTick>
8000d8e: 4602 mov r2, r0
8000d90: 693b ldr r3, [r7, #16]
8000d92: 1ad3 subs r3, r2, r3
8000d94: 2b64 cmp r3, #100 ; 0x64
8000d96: d901 bls.n 8000d9c <HAL_RCC_OscConfig+0x2f0>
{
return HAL_TIMEOUT;
8000d98: 2303 movs r3, #3
8000d9a: e103 b.n 8000fa4 <HAL_RCC_OscConfig+0x4f8>
while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
8000d9c: 4b75 ldr r3, [pc, #468] ; (8000f74 <HAL_RCC_OscConfig+0x4c8>)
8000d9e: 681b ldr r3, [r3, #0]
8000da0: f403 7380 and.w r3, r3, #256 ; 0x100
8000da4: 2b00 cmp r3, #0
8000da6: d0f0 beq.n 8000d8a <HAL_RCC_OscConfig+0x2de>
}
}
}
/* Set the new LSE configuration -----------------------------------------*/
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
8000da8: 687b ldr r3, [r7, #4]
8000daa: 68db ldr r3, [r3, #12]
8000dac: 2b01 cmp r3, #1
8000dae: d106 bne.n 8000dbe <HAL_RCC_OscConfig+0x312>
8000db0: 4b6f ldr r3, [pc, #444] ; (8000f70 <HAL_RCC_OscConfig+0x4c4>)
8000db2: 6a1b ldr r3, [r3, #32]
8000db4: 4a6e ldr r2, [pc, #440] ; (8000f70 <HAL_RCC_OscConfig+0x4c4>)
8000db6: f043 0301 orr.w r3, r3, #1
8000dba: 6213 str r3, [r2, #32]
8000dbc: e02d b.n 8000e1a <HAL_RCC_OscConfig+0x36e>
8000dbe: 687b ldr r3, [r7, #4]
8000dc0: 68db ldr r3, [r3, #12]
8000dc2: 2b00 cmp r3, #0
8000dc4: d10c bne.n 8000de0 <HAL_RCC_OscConfig+0x334>
8000dc6: 4b6a ldr r3, [pc, #424] ; (8000f70 <HAL_RCC_OscConfig+0x4c4>)
8000dc8: 6a1b ldr r3, [r3, #32]
8000dca: 4a69 ldr r2, [pc, #420] ; (8000f70 <HAL_RCC_OscConfig+0x4c4>)
8000dcc: f023 0301 bic.w r3, r3, #1
8000dd0: 6213 str r3, [r2, #32]
8000dd2: 4b67 ldr r3, [pc, #412] ; (8000f70 <HAL_RCC_OscConfig+0x4c4>)
8000dd4: 6a1b ldr r3, [r3, #32]
8000dd6: 4a66 ldr r2, [pc, #408] ; (8000f70 <HAL_RCC_OscConfig+0x4c4>)
8000dd8: f023 0304 bic.w r3, r3, #4
8000ddc: 6213 str r3, [r2, #32]
8000dde: e01c b.n 8000e1a <HAL_RCC_OscConfig+0x36e>
8000de0: 687b ldr r3, [r7, #4]
8000de2: 68db ldr r3, [r3, #12]
8000de4: 2b05 cmp r3, #5
8000de6: d10c bne.n 8000e02 <HAL_RCC_OscConfig+0x356>
8000de8: 4b61 ldr r3, [pc, #388] ; (8000f70 <HAL_RCC_OscConfig+0x4c4>)
8000dea: 6a1b ldr r3, [r3, #32]
8000dec: 4a60 ldr r2, [pc, #384] ; (8000f70 <HAL_RCC_OscConfig+0x4c4>)
8000dee: f043 0304 orr.w r3, r3, #4
8000df2: 6213 str r3, [r2, #32]
8000df4: 4b5e ldr r3, [pc, #376] ; (8000f70 <HAL_RCC_OscConfig+0x4c4>)
8000df6: 6a1b ldr r3, [r3, #32]
8000df8: 4a5d ldr r2, [pc, #372] ; (8000f70 <HAL_RCC_OscConfig+0x4c4>)
8000dfa: f043 0301 orr.w r3, r3, #1
8000dfe: 6213 str r3, [r2, #32]
8000e00: e00b b.n 8000e1a <HAL_RCC_OscConfig+0x36e>
8000e02: 4b5b ldr r3, [pc, #364] ; (8000f70 <HAL_RCC_OscConfig+0x4c4>)
8000e04: 6a1b ldr r3, [r3, #32]
8000e06: 4a5a ldr r2, [pc, #360] ; (8000f70 <HAL_RCC_OscConfig+0x4c4>)
8000e08: f023 0301 bic.w r3, r3, #1
8000e0c: 6213 str r3, [r2, #32]
8000e0e: 4b58 ldr r3, [pc, #352] ; (8000f70 <HAL_RCC_OscConfig+0x4c4>)
8000e10: 6a1b ldr r3, [r3, #32]
8000e12: 4a57 ldr r2, [pc, #348] ; (8000f70 <HAL_RCC_OscConfig+0x4c4>)
8000e14: f023 0304 bic.w r3, r3, #4
8000e18: 6213 str r3, [r2, #32]
/* Check the LSE State */
if (RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
8000e1a: 687b ldr r3, [r7, #4]
8000e1c: 68db ldr r3, [r3, #12]
8000e1e: 2b00 cmp r3, #0
8000e20: d015 beq.n 8000e4e <HAL_RCC_OscConfig+0x3a2>
{
/* Get Start Tick */
tickstart = HAL_GetTick();
8000e22: f7ff fbad bl 8000580 <HAL_GetTick>
8000e26: 6138 str r0, [r7, #16]
/* Wait till LSE is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
8000e28: e00a b.n 8000e40 <HAL_RCC_OscConfig+0x394>
{
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
8000e2a: f7ff fba9 bl 8000580 <HAL_GetTick>
8000e2e: 4602 mov r2, r0
8000e30: 693b ldr r3, [r7, #16]
8000e32: 1ad3 subs r3, r2, r3
8000e34: f241 3288 movw r2, #5000 ; 0x1388
8000e38: 4293 cmp r3, r2
8000e3a: d901 bls.n 8000e40 <HAL_RCC_OscConfig+0x394>
{
return HAL_TIMEOUT;
8000e3c: 2303 movs r3, #3
8000e3e: e0b1 b.n 8000fa4 <HAL_RCC_OscConfig+0x4f8>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
8000e40: 4b4b ldr r3, [pc, #300] ; (8000f70 <HAL_RCC_OscConfig+0x4c4>)
8000e42: 6a1b ldr r3, [r3, #32]
8000e44: f003 0302 and.w r3, r3, #2
8000e48: 2b00 cmp r3, #0
8000e4a: d0ee beq.n 8000e2a <HAL_RCC_OscConfig+0x37e>
8000e4c: e014 b.n 8000e78 <HAL_RCC_OscConfig+0x3cc>
}
}
else
{
/* Get Start Tick */
tickstart = HAL_GetTick();
8000e4e: f7ff fb97 bl 8000580 <HAL_GetTick>
8000e52: 6138 str r0, [r7, #16]
/* Wait till LSE is disabled */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
8000e54: e00a b.n 8000e6c <HAL_RCC_OscConfig+0x3c0>
{
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
8000e56: f7ff fb93 bl 8000580 <HAL_GetTick>
8000e5a: 4602 mov r2, r0
8000e5c: 693b ldr r3, [r7, #16]
8000e5e: 1ad3 subs r3, r2, r3
8000e60: f241 3288 movw r2, #5000 ; 0x1388
8000e64: 4293 cmp r3, r2
8000e66: d901 bls.n 8000e6c <HAL_RCC_OscConfig+0x3c0>
{
return HAL_TIMEOUT;
8000e68: 2303 movs r3, #3
8000e6a: e09b b.n 8000fa4 <HAL_RCC_OscConfig+0x4f8>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
8000e6c: 4b40 ldr r3, [pc, #256] ; (8000f70 <HAL_RCC_OscConfig+0x4c4>)
8000e6e: 6a1b ldr r3, [r3, #32]
8000e70: f003 0302 and.w r3, r3, #2
8000e74: 2b00 cmp r3, #0
8000e76: d1ee bne.n 8000e56 <HAL_RCC_OscConfig+0x3aa>
}
}
}
/* Require to disable power clock if necessary */
if (pwrclkchanged == SET)
8000e78: 7dfb ldrb r3, [r7, #23]
8000e7a: 2b01 cmp r3, #1
8000e7c: d105 bne.n 8000e8a <HAL_RCC_OscConfig+0x3de>
{
__HAL_RCC_PWR_CLK_DISABLE();
8000e7e: 4b3c ldr r3, [pc, #240] ; (8000f70 <HAL_RCC_OscConfig+0x4c4>)
8000e80: 69db ldr r3, [r3, #28]
8000e82: 4a3b ldr r2, [pc, #236] ; (8000f70 <HAL_RCC_OscConfig+0x4c4>)
8000e84: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000
8000e88: 61d3 str r3, [r2, #28]
#endif /* RCC_CR_PLL2ON */
/*-------------------------------- PLL Configuration -----------------------*/
/* Check the parameters */
assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
8000e8a: 687b ldr r3, [r7, #4]
8000e8c: 69db ldr r3, [r3, #28]
8000e8e: 2b00 cmp r3, #0
8000e90: f000 8087 beq.w 8000fa2 <HAL_RCC_OscConfig+0x4f6>
{
/* Check if the PLL is used as system clock or not */
if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
8000e94: 4b36 ldr r3, [pc, #216] ; (8000f70 <HAL_RCC_OscConfig+0x4c4>)
8000e96: 685b ldr r3, [r3, #4]
8000e98: f003 030c and.w r3, r3, #12
8000e9c: 2b08 cmp r3, #8
8000e9e: d061 beq.n 8000f64 <HAL_RCC_OscConfig+0x4b8>
{
if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
8000ea0: 687b ldr r3, [r7, #4]
8000ea2: 69db ldr r3, [r3, #28]
8000ea4: 2b02 cmp r3, #2
8000ea6: d146 bne.n 8000f36 <HAL_RCC_OscConfig+0x48a>
/* Check the parameters */
assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL));
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
8000ea8: 4b33 ldr r3, [pc, #204] ; (8000f78 <HAL_RCC_OscConfig+0x4cc>)
8000eaa: 2200 movs r2, #0
8000eac: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8000eae: f7ff fb67 bl 8000580 <HAL_GetTick>
8000eb2: 6138 str r0, [r7, #16]
/* Wait till PLL is disabled */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8000eb4: e008 b.n 8000ec8 <HAL_RCC_OscConfig+0x41c>
{
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
8000eb6: f7ff fb63 bl 8000580 <HAL_GetTick>
8000eba: 4602 mov r2, r0
8000ebc: 693b ldr r3, [r7, #16]
8000ebe: 1ad3 subs r3, r2, r3
8000ec0: 2b02 cmp r3, #2
8000ec2: d901 bls.n 8000ec8 <HAL_RCC_OscConfig+0x41c>
{
return HAL_TIMEOUT;
8000ec4: 2303 movs r3, #3
8000ec6: e06d b.n 8000fa4 <HAL_RCC_OscConfig+0x4f8>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8000ec8: 4b29 ldr r3, [pc, #164] ; (8000f70 <HAL_RCC_OscConfig+0x4c4>)
8000eca: 681b ldr r3, [r3, #0]
8000ecc: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
8000ed0: 2b00 cmp r3, #0
8000ed2: d1f0 bne.n 8000eb6 <HAL_RCC_OscConfig+0x40a>
}
}
/* Configure the HSE prediv factor --------------------------------*/
/* It can be written only when the PLL is disabled. Not used in PLL source is different than HSE */
if (RCC_OscInitStruct->PLL.PLLSource == RCC_PLLSOURCE_HSE)
8000ed4: 687b ldr r3, [r7, #4]
8000ed6: 6a1b ldr r3, [r3, #32]
8000ed8: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
8000edc: d108 bne.n 8000ef0 <HAL_RCC_OscConfig+0x444>
/* Set PREDIV1 source */
SET_BIT(RCC->CFGR2, RCC_OscInitStruct->Prediv1Source);
#endif /* RCC_CFGR2_PREDIV1SRC */
/* Set PREDIV1 Value */
__HAL_RCC_HSE_PREDIV_CONFIG(RCC_OscInitStruct->HSEPredivValue);
8000ede: 4b24 ldr r3, [pc, #144] ; (8000f70 <HAL_RCC_OscConfig+0x4c4>)
8000ee0: 685b ldr r3, [r3, #4]
8000ee2: f423 3200 bic.w r2, r3, #131072 ; 0x20000
8000ee6: 687b ldr r3, [r7, #4]
8000ee8: 689b ldr r3, [r3, #8]
8000eea: 4921 ldr r1, [pc, #132] ; (8000f70 <HAL_RCC_OscConfig+0x4c4>)
8000eec: 4313 orrs r3, r2
8000eee: 604b str r3, [r1, #4]
}
/* Configure the main PLL clock source and multiplication factors. */
__HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
8000ef0: 4b1f ldr r3, [pc, #124] ; (8000f70 <HAL_RCC_OscConfig+0x4c4>)
8000ef2: 685b ldr r3, [r3, #4]
8000ef4: f423 1274 bic.w r2, r3, #3997696 ; 0x3d0000
8000ef8: 687b ldr r3, [r7, #4]
8000efa: 6a19 ldr r1, [r3, #32]
8000efc: 687b ldr r3, [r7, #4]
8000efe: 6a5b ldr r3, [r3, #36] ; 0x24
8000f00: 430b orrs r3, r1
8000f02: 491b ldr r1, [pc, #108] ; (8000f70 <HAL_RCC_OscConfig+0x4c4>)
8000f04: 4313 orrs r3, r2
8000f06: 604b str r3, [r1, #4]
RCC_OscInitStruct->PLL.PLLMUL);
/* Enable the main PLL. */
__HAL_RCC_PLL_ENABLE();
8000f08: 4b1b ldr r3, [pc, #108] ; (8000f78 <HAL_RCC_OscConfig+0x4cc>)
8000f0a: 2201 movs r2, #1
8000f0c: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8000f0e: f7ff fb37 bl 8000580 <HAL_GetTick>
8000f12: 6138 str r0, [r7, #16]
/* Wait till PLL is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
8000f14: e008 b.n 8000f28 <HAL_RCC_OscConfig+0x47c>
{
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
8000f16: f7ff fb33 bl 8000580 <HAL_GetTick>
8000f1a: 4602 mov r2, r0
8000f1c: 693b ldr r3, [r7, #16]
8000f1e: 1ad3 subs r3, r2, r3
8000f20: 2b02 cmp r3, #2
8000f22: d901 bls.n 8000f28 <HAL_RCC_OscConfig+0x47c>
{
return HAL_TIMEOUT;
8000f24: 2303 movs r3, #3
8000f26: e03d b.n 8000fa4 <HAL_RCC_OscConfig+0x4f8>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
8000f28: 4b11 ldr r3, [pc, #68] ; (8000f70 <HAL_RCC_OscConfig+0x4c4>)
8000f2a: 681b ldr r3, [r3, #0]
8000f2c: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
8000f30: 2b00 cmp r3, #0
8000f32: d0f0 beq.n 8000f16 <HAL_RCC_OscConfig+0x46a>
8000f34: e035 b.n 8000fa2 <HAL_RCC_OscConfig+0x4f6>
}
}
else
{
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
8000f36: 4b10 ldr r3, [pc, #64] ; (8000f78 <HAL_RCC_OscConfig+0x4cc>)
8000f38: 2200 movs r2, #0
8000f3a: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8000f3c: f7ff fb20 bl 8000580 <HAL_GetTick>
8000f40: 6138 str r0, [r7, #16]
/* Wait till PLL is disabled */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8000f42: e008 b.n 8000f56 <HAL_RCC_OscConfig+0x4aa>
{
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
8000f44: f7ff fb1c bl 8000580 <HAL_GetTick>
8000f48: 4602 mov r2, r0
8000f4a: 693b ldr r3, [r7, #16]
8000f4c: 1ad3 subs r3, r2, r3
8000f4e: 2b02 cmp r3, #2
8000f50: d901 bls.n 8000f56 <HAL_RCC_OscConfig+0x4aa>
{
return HAL_TIMEOUT;
8000f52: 2303 movs r3, #3
8000f54: e026 b.n 8000fa4 <HAL_RCC_OscConfig+0x4f8>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8000f56: 4b06 ldr r3, [pc, #24] ; (8000f70 <HAL_RCC_OscConfig+0x4c4>)
8000f58: 681b ldr r3, [r3, #0]
8000f5a: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
8000f5e: 2b00 cmp r3, #0
8000f60: d1f0 bne.n 8000f44 <HAL_RCC_OscConfig+0x498>
8000f62: e01e b.n 8000fa2 <HAL_RCC_OscConfig+0x4f6>
}
}
else
{
/* Check if there is a request to disable the PLL used as System clock source */
if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
8000f64: 687b ldr r3, [r7, #4]
8000f66: 69db ldr r3, [r3, #28]
8000f68: 2b01 cmp r3, #1
8000f6a: d107 bne.n 8000f7c <HAL_RCC_OscConfig+0x4d0>
{
return HAL_ERROR;
8000f6c: 2301 movs r3, #1
8000f6e: e019 b.n 8000fa4 <HAL_RCC_OscConfig+0x4f8>
8000f70: 40021000 .word 0x40021000
8000f74: 40007000 .word 0x40007000
8000f78: 42420060 .word 0x42420060
}
else
{
/* Do not return HAL_ERROR if request repeats the current configuration */
pll_config = RCC->CFGR;
8000f7c: 4b0b ldr r3, [pc, #44] ; (8000fac <HAL_RCC_OscConfig+0x500>)
8000f7e: 685b ldr r3, [r3, #4]
8000f80: 60fb str r3, [r7, #12]
if ((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
8000f82: 68fb ldr r3, [r7, #12]
8000f84: f403 3280 and.w r2, r3, #65536 ; 0x10000
8000f88: 687b ldr r3, [r7, #4]
8000f8a: 6a1b ldr r3, [r3, #32]
8000f8c: 429a cmp r2, r3
8000f8e: d106 bne.n 8000f9e <HAL_RCC_OscConfig+0x4f2>
(READ_BIT(pll_config, RCC_CFGR_PLLMULL) != RCC_OscInitStruct->PLL.PLLMUL))
8000f90: 68fb ldr r3, [r7, #12]
8000f92: f403 1270 and.w r2, r3, #3932160 ; 0x3c0000
8000f96: 687b ldr r3, [r7, #4]
8000f98: 6a5b ldr r3, [r3, #36] ; 0x24
if ((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
8000f9a: 429a cmp r2, r3
8000f9c: d001 beq.n 8000fa2 <HAL_RCC_OscConfig+0x4f6>
{
return HAL_ERROR;
8000f9e: 2301 movs r3, #1
8000fa0: e000 b.n 8000fa4 <HAL_RCC_OscConfig+0x4f8>
}
}
}
}
return HAL_OK;
8000fa2: 2300 movs r3, #0
}
8000fa4: 4618 mov r0, r3
8000fa6: 3718 adds r7, #24
8000fa8: 46bd mov sp, r7
8000faa: bd80 pop {r7, pc}
8000fac: 40021000 .word 0x40021000
08000fb0 <HAL_RCC_ClockConfig>:
* You can use @ref HAL_RCC_GetClockConfig() function to know which clock is
* currently used as system clock source.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
{
8000fb0: b580 push {r7, lr}
8000fb2: b084 sub sp, #16
8000fb4: af00 add r7, sp, #0
8000fb6: 6078 str r0, [r7, #4]
8000fb8: 6039 str r1, [r7, #0]
uint32_t tickstart;
/* Check Null pointer */
if (RCC_ClkInitStruct == NULL)
8000fba: 687b ldr r3, [r7, #4]
8000fbc: 2b00 cmp r3, #0
8000fbe: d101 bne.n 8000fc4 <HAL_RCC_ClockConfig+0x14>
{
return HAL_ERROR;
8000fc0: 2301 movs r3, #1
8000fc2: e0d0 b.n 8001166 <HAL_RCC_ClockConfig+0x1b6>
must be correctly programmed according to the frequency of the CPU clock
(HCLK) of the device. */
#if defined(FLASH_ACR_LATENCY)
/* Increasing the number of wait states because of higher CPU frequency */
if (FLatency > __HAL_FLASH_GET_LATENCY())
8000fc4: 4b6a ldr r3, [pc, #424] ; (8001170 <HAL_RCC_ClockConfig+0x1c0>)
8000fc6: 681b ldr r3, [r3, #0]
8000fc8: f003 0307 and.w r3, r3, #7
8000fcc: 683a ldr r2, [r7, #0]
8000fce: 429a cmp r2, r3
8000fd0: d910 bls.n 8000ff4 <HAL_RCC_ClockConfig+0x44>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
8000fd2: 4b67 ldr r3, [pc, #412] ; (8001170 <HAL_RCC_ClockConfig+0x1c0>)
8000fd4: 681b ldr r3, [r3, #0]
8000fd6: f023 0207 bic.w r2, r3, #7
8000fda: 4965 ldr r1, [pc, #404] ; (8001170 <HAL_RCC_ClockConfig+0x1c0>)
8000fdc: 683b ldr r3, [r7, #0]
8000fde: 4313 orrs r3, r2
8000fe0: 600b str r3, [r1, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if (__HAL_FLASH_GET_LATENCY() != FLatency)
8000fe2: 4b63 ldr r3, [pc, #396] ; (8001170 <HAL_RCC_ClockConfig+0x1c0>)
8000fe4: 681b ldr r3, [r3, #0]
8000fe6: f003 0307 and.w r3, r3, #7
8000fea: 683a ldr r2, [r7, #0]
8000fec: 429a cmp r2, r3
8000fee: d001 beq.n 8000ff4 <HAL_RCC_ClockConfig+0x44>
{
return HAL_ERROR;
8000ff0: 2301 movs r3, #1
8000ff2: e0b8 b.n 8001166 <HAL_RCC_ClockConfig+0x1b6>
}
}
#endif /* FLASH_ACR_LATENCY */
/*-------------------------- HCLK Configuration --------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
8000ff4: 687b ldr r3, [r7, #4]
8000ff6: 681b ldr r3, [r3, #0]
8000ff8: f003 0302 and.w r3, r3, #2
8000ffc: 2b00 cmp r3, #0
8000ffe: d020 beq.n 8001042 <HAL_RCC_ClockConfig+0x92>
{
/* Set the highest APBx dividers in order to ensure that we do not go through
a non-spec phase whatever we decrease or increase HCLK. */
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
8001000: 687b ldr r3, [r7, #4]
8001002: 681b ldr r3, [r3, #0]
8001004: f003 0304 and.w r3, r3, #4
8001008: 2b00 cmp r3, #0
800100a: d005 beq.n 8001018 <HAL_RCC_ClockConfig+0x68>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16);
800100c: 4b59 ldr r3, [pc, #356] ; (8001174 <HAL_RCC_ClockConfig+0x1c4>)
800100e: 685b ldr r3, [r3, #4]
8001010: 4a58 ldr r2, [pc, #352] ; (8001174 <HAL_RCC_ClockConfig+0x1c4>)
8001012: f443 63e0 orr.w r3, r3, #1792 ; 0x700
8001016: 6053 str r3, [r2, #4]
}
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
8001018: 687b ldr r3, [r7, #4]
800101a: 681b ldr r3, [r3, #0]
800101c: f003 0308 and.w r3, r3, #8
8001020: 2b00 cmp r3, #0
8001022: d005 beq.n 8001030 <HAL_RCC_ClockConfig+0x80>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3));
8001024: 4b53 ldr r3, [pc, #332] ; (8001174 <HAL_RCC_ClockConfig+0x1c4>)
8001026: 685b ldr r3, [r3, #4]
8001028: 4a52 ldr r2, [pc, #328] ; (8001174 <HAL_RCC_ClockConfig+0x1c4>)
800102a: f443 5360 orr.w r3, r3, #14336 ; 0x3800
800102e: 6053 str r3, [r2, #4]
}
/* Set the new HCLK clock divider */
assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
8001030: 4b50 ldr r3, [pc, #320] ; (8001174 <HAL_RCC_ClockConfig+0x1c4>)
8001032: 685b ldr r3, [r3, #4]
8001034: f023 02f0 bic.w r2, r3, #240 ; 0xf0
8001038: 687b ldr r3, [r7, #4]
800103a: 689b ldr r3, [r3, #8]
800103c: 494d ldr r1, [pc, #308] ; (8001174 <HAL_RCC_ClockConfig+0x1c4>)
800103e: 4313 orrs r3, r2
8001040: 604b str r3, [r1, #4]
}
/*------------------------- SYSCLK Configuration ---------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
8001042: 687b ldr r3, [r7, #4]
8001044: 681b ldr r3, [r3, #0]
8001046: f003 0301 and.w r3, r3, #1
800104a: 2b00 cmp r3, #0
800104c: d040 beq.n 80010d0 <HAL_RCC_ClockConfig+0x120>
{
assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
/* HSE is selected as System Clock Source */
if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
800104e: 687b ldr r3, [r7, #4]
8001050: 685b ldr r3, [r3, #4]
8001052: 2b01 cmp r3, #1
8001054: d107 bne.n 8001066 <HAL_RCC_ClockConfig+0xb6>
{
/* Check the HSE ready flag */
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
8001056: 4b47 ldr r3, [pc, #284] ; (8001174 <HAL_RCC_ClockConfig+0x1c4>)
8001058: 681b ldr r3, [r3, #0]
800105a: f403 3300 and.w r3, r3, #131072 ; 0x20000
800105e: 2b00 cmp r3, #0
8001060: d115 bne.n 800108e <HAL_RCC_ClockConfig+0xde>
{
return HAL_ERROR;
8001062: 2301 movs r3, #1
8001064: e07f b.n 8001166 <HAL_RCC_ClockConfig+0x1b6>
}
}
/* PLL is selected as System Clock Source */
else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
8001066: 687b ldr r3, [r7, #4]
8001068: 685b ldr r3, [r3, #4]
800106a: 2b02 cmp r3, #2
800106c: d107 bne.n 800107e <HAL_RCC_ClockConfig+0xce>
{
/* Check the PLL ready flag */
if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
800106e: 4b41 ldr r3, [pc, #260] ; (8001174 <HAL_RCC_ClockConfig+0x1c4>)
8001070: 681b ldr r3, [r3, #0]
8001072: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
8001076: 2b00 cmp r3, #0
8001078: d109 bne.n 800108e <HAL_RCC_ClockConfig+0xde>
{
return HAL_ERROR;
800107a: 2301 movs r3, #1
800107c: e073 b.n 8001166 <HAL_RCC_ClockConfig+0x1b6>
}
/* HSI is selected as System Clock Source */
else
{
/* Check the HSI ready flag */
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
800107e: 4b3d ldr r3, [pc, #244] ; (8001174 <HAL_RCC_ClockConfig+0x1c4>)
8001080: 681b ldr r3, [r3, #0]
8001082: f003 0302 and.w r3, r3, #2
8001086: 2b00 cmp r3, #0
8001088: d101 bne.n 800108e <HAL_RCC_ClockConfig+0xde>
{
return HAL_ERROR;
800108a: 2301 movs r3, #1
800108c: e06b b.n 8001166 <HAL_RCC_ClockConfig+0x1b6>
}
}
__HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
800108e: 4b39 ldr r3, [pc, #228] ; (8001174 <HAL_RCC_ClockConfig+0x1c4>)
8001090: 685b ldr r3, [r3, #4]
8001092: f023 0203 bic.w r2, r3, #3
8001096: 687b ldr r3, [r7, #4]
8001098: 685b ldr r3, [r3, #4]
800109a: 4936 ldr r1, [pc, #216] ; (8001174 <HAL_RCC_ClockConfig+0x1c4>)
800109c: 4313 orrs r3, r2
800109e: 604b str r3, [r1, #4]
/* Get Start Tick */
tickstart = HAL_GetTick();
80010a0: f7ff fa6e bl 8000580 <HAL_GetTick>
80010a4: 60f8 str r0, [r7, #12]
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
80010a6: e00a b.n 80010be <HAL_RCC_ClockConfig+0x10e>
{
if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
80010a8: f7ff fa6a bl 8000580 <HAL_GetTick>
80010ac: 4602 mov r2, r0
80010ae: 68fb ldr r3, [r7, #12]
80010b0: 1ad3 subs r3, r2, r3
80010b2: f241 3288 movw r2, #5000 ; 0x1388
80010b6: 4293 cmp r3, r2
80010b8: d901 bls.n 80010be <HAL_RCC_ClockConfig+0x10e>
{
return HAL_TIMEOUT;
80010ba: 2303 movs r3, #3
80010bc: e053 b.n 8001166 <HAL_RCC_ClockConfig+0x1b6>
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
80010be: 4b2d ldr r3, [pc, #180] ; (8001174 <HAL_RCC_ClockConfig+0x1c4>)
80010c0: 685b ldr r3, [r3, #4]
80010c2: f003 020c and.w r2, r3, #12
80010c6: 687b ldr r3, [r7, #4]
80010c8: 685b ldr r3, [r3, #4]
80010ca: 009b lsls r3, r3, #2
80010cc: 429a cmp r2, r3
80010ce: d1eb bne.n 80010a8 <HAL_RCC_ClockConfig+0xf8>
}
}
#if defined(FLASH_ACR_LATENCY)
/* Decreasing the number of wait states because of lower CPU frequency */
if (FLatency < __HAL_FLASH_GET_LATENCY())
80010d0: 4b27 ldr r3, [pc, #156] ; (8001170 <HAL_RCC_ClockConfig+0x1c0>)
80010d2: 681b ldr r3, [r3, #0]
80010d4: f003 0307 and.w r3, r3, #7
80010d8: 683a ldr r2, [r7, #0]
80010da: 429a cmp r2, r3
80010dc: d210 bcs.n 8001100 <HAL_RCC_ClockConfig+0x150>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
80010de: 4b24 ldr r3, [pc, #144] ; (8001170 <HAL_RCC_ClockConfig+0x1c0>)
80010e0: 681b ldr r3, [r3, #0]
80010e2: f023 0207 bic.w r2, r3, #7
80010e6: 4922 ldr r1, [pc, #136] ; (8001170 <HAL_RCC_ClockConfig+0x1c0>)
80010e8: 683b ldr r3, [r7, #0]
80010ea: 4313 orrs r3, r2
80010ec: 600b str r3, [r1, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if (__HAL_FLASH_GET_LATENCY() != FLatency)
80010ee: 4b20 ldr r3, [pc, #128] ; (8001170 <HAL_RCC_ClockConfig+0x1c0>)
80010f0: 681b ldr r3, [r3, #0]
80010f2: f003 0307 and.w r3, r3, #7
80010f6: 683a ldr r2, [r7, #0]
80010f8: 429a cmp r2, r3
80010fa: d001 beq.n 8001100 <HAL_RCC_ClockConfig+0x150>
{
return HAL_ERROR;
80010fc: 2301 movs r3, #1
80010fe: e032 b.n 8001166 <HAL_RCC_ClockConfig+0x1b6>
}
}
#endif /* FLASH_ACR_LATENCY */
/*-------------------------- PCLK1 Configuration ---------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
8001100: 687b ldr r3, [r7, #4]
8001102: 681b ldr r3, [r3, #0]
8001104: f003 0304 and.w r3, r3, #4
8001108: 2b00 cmp r3, #0
800110a: d008 beq.n 800111e <HAL_RCC_ClockConfig+0x16e>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
800110c: 4b19 ldr r3, [pc, #100] ; (8001174 <HAL_RCC_ClockConfig+0x1c4>)
800110e: 685b ldr r3, [r3, #4]
8001110: f423 62e0 bic.w r2, r3, #1792 ; 0x700
8001114: 687b ldr r3, [r7, #4]
8001116: 68db ldr r3, [r3, #12]
8001118: 4916 ldr r1, [pc, #88] ; (8001174 <HAL_RCC_ClockConfig+0x1c4>)
800111a: 4313 orrs r3, r2
800111c: 604b str r3, [r1, #4]
}
/*-------------------------- PCLK2 Configuration ---------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
800111e: 687b ldr r3, [r7, #4]
8001120: 681b ldr r3, [r3, #0]
8001122: f003 0308 and.w r3, r3, #8
8001126: 2b00 cmp r3, #0
8001128: d009 beq.n 800113e <HAL_RCC_ClockConfig+0x18e>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3));
800112a: 4b12 ldr r3, [pc, #72] ; (8001174 <HAL_RCC_ClockConfig+0x1c4>)
800112c: 685b ldr r3, [r3, #4]
800112e: f423 5260 bic.w r2, r3, #14336 ; 0x3800
8001132: 687b ldr r3, [r7, #4]
8001134: 691b ldr r3, [r3, #16]
8001136: 00db lsls r3, r3, #3
8001138: 490e ldr r1, [pc, #56] ; (8001174 <HAL_RCC_ClockConfig+0x1c4>)
800113a: 4313 orrs r3, r2
800113c: 604b str r3, [r1, #4]
}
/* Update the SystemCoreClock global variable */
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos];
800113e: f000 f821 bl 8001184 <HAL_RCC_GetSysClockFreq>
8001142: 4602 mov r2, r0
8001144: 4b0b ldr r3, [pc, #44] ; (8001174 <HAL_RCC_ClockConfig+0x1c4>)
8001146: 685b ldr r3, [r3, #4]
8001148: 091b lsrs r3, r3, #4
800114a: f003 030f and.w r3, r3, #15
800114e: 490a ldr r1, [pc, #40] ; (8001178 <HAL_RCC_ClockConfig+0x1c8>)
8001150: 5ccb ldrb r3, [r1, r3]
8001152: fa22 f303 lsr.w r3, r2, r3
8001156: 4a09 ldr r2, [pc, #36] ; (800117c <HAL_RCC_ClockConfig+0x1cc>)
8001158: 6013 str r3, [r2, #0]
/* Configure the source of time base considering new system clocks settings*/
HAL_InitTick(uwTickPrio);
800115a: 4b09 ldr r3, [pc, #36] ; (8001180 <HAL_RCC_ClockConfig+0x1d0>)
800115c: 681b ldr r3, [r3, #0]
800115e: 4618 mov r0, r3
8001160: f7ff f9cc bl 80004fc <HAL_InitTick>
return HAL_OK;
8001164: 2300 movs r3, #0
}
8001166: 4618 mov r0, r3
8001168: 3710 adds r7, #16
800116a: 46bd mov sp, r7
800116c: bd80 pop {r7, pc}
800116e: bf00 nop
8001170: 40022000 .word 0x40022000
8001174: 40021000 .word 0x40021000
8001178: 08001fe4 .word 0x08001fe4
800117c: 20000000 .word 0x20000000
8001180: 20000004 .word 0x20000004
08001184 <HAL_RCC_GetSysClockFreq>:
* right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
*
* @retval SYSCLK frequency
*/
uint32_t HAL_RCC_GetSysClockFreq(void)
{
8001184: b490 push {r4, r7}
8001186: b08a sub sp, #40 ; 0x28
8001188: af00 add r7, sp, #0
#if defined(RCC_CFGR2_PREDIV1SRC)
const uint8_t aPLLMULFactorTable[14] = {0, 0, 4, 5, 6, 7, 8, 9, 0, 0, 0, 0, 0, 13};
const uint8_t aPredivFactorTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16};
#else
const uint8_t aPLLMULFactorTable[16] = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16};
800118a: 4b29 ldr r3, [pc, #164] ; (8001230 <HAL_RCC_GetSysClockFreq+0xac>)
800118c: 1d3c adds r4, r7, #4
800118e: cb0f ldmia r3, {r0, r1, r2, r3}
8001190: e884 000f stmia.w r4, {r0, r1, r2, r3}
#if defined(RCC_CFGR2_PREDIV1)
const uint8_t aPredivFactorTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16};
#else
const uint8_t aPredivFactorTable[2] = {1, 2};
8001194: f240 2301 movw r3, #513 ; 0x201
8001198: 803b strh r3, [r7, #0]
#endif /*RCC_CFGR2_PREDIV1*/
#endif
uint32_t tmpreg = 0U, prediv = 0U, pllclk = 0U, pllmul = 0U;
800119a: 2300 movs r3, #0
800119c: 61fb str r3, [r7, #28]
800119e: 2300 movs r3, #0
80011a0: 61bb str r3, [r7, #24]
80011a2: 2300 movs r3, #0
80011a4: 627b str r3, [r7, #36] ; 0x24
80011a6: 2300 movs r3, #0
80011a8: 617b str r3, [r7, #20]
uint32_t sysclockfreq = 0U;
80011aa: 2300 movs r3, #0
80011ac: 623b str r3, [r7, #32]
#if defined(RCC_CFGR2_PREDIV1SRC)
uint32_t prediv2 = 0U, pll2mul = 0U;
#endif /*RCC_CFGR2_PREDIV1SRC*/
tmpreg = RCC->CFGR;
80011ae: 4b21 ldr r3, [pc, #132] ; (8001234 <HAL_RCC_GetSysClockFreq+0xb0>)
80011b0: 685b ldr r3, [r3, #4]
80011b2: 61fb str r3, [r7, #28]
/* Get SYSCLK source -------------------------------------------------------*/
switch (tmpreg & RCC_CFGR_SWS)
80011b4: 69fb ldr r3, [r7, #28]
80011b6: f003 030c and.w r3, r3, #12
80011ba: 2b04 cmp r3, #4
80011bc: d002 beq.n 80011c4 <HAL_RCC_GetSysClockFreq+0x40>
80011be: 2b08 cmp r3, #8
80011c0: d003 beq.n 80011ca <HAL_RCC_GetSysClockFreq+0x46>
80011c2: e02b b.n 800121c <HAL_RCC_GetSysClockFreq+0x98>
{
case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */
{
sysclockfreq = HSE_VALUE;
80011c4: 4b1c ldr r3, [pc, #112] ; (8001238 <HAL_RCC_GetSysClockFreq+0xb4>)
80011c6: 623b str r3, [r7, #32]
break;
80011c8: e02b b.n 8001222 <HAL_RCC_GetSysClockFreq+0x9e>
}
case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */
{
pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos];
80011ca: 69fb ldr r3, [r7, #28]
80011cc: 0c9b lsrs r3, r3, #18
80011ce: f003 030f and.w r3, r3, #15
80011d2: 3328 adds r3, #40 ; 0x28
80011d4: 443b add r3, r7
80011d6: f813 3c24 ldrb.w r3, [r3, #-36]
80011da: 617b str r3, [r7, #20]
if ((tmpreg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2)
80011dc: 69fb ldr r3, [r7, #28]
80011de: f403 3380 and.w r3, r3, #65536 ; 0x10000
80011e2: 2b00 cmp r3, #0
80011e4: d012 beq.n 800120c <HAL_RCC_GetSysClockFreq+0x88>
{
#if defined(RCC_CFGR2_PREDIV1)
prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> RCC_CFGR2_PREDIV1_Pos];
#else
prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos];
80011e6: 4b13 ldr r3, [pc, #76] ; (8001234 <HAL_RCC_GetSysClockFreq+0xb0>)
80011e8: 685b ldr r3, [r3, #4]
80011ea: 0c5b lsrs r3, r3, #17
80011ec: f003 0301 and.w r3, r3, #1
80011f0: 3328 adds r3, #40 ; 0x28
80011f2: 443b add r3, r7
80011f4: f813 3c28 ldrb.w r3, [r3, #-40]
80011f8: 61bb str r3, [r7, #24]
{
pllclk = pllclk / 2;
}
#else
/* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */
pllclk = (uint32_t)((HSE_VALUE * pllmul) / prediv);
80011fa: 697b ldr r3, [r7, #20]
80011fc: 4a0e ldr r2, [pc, #56] ; (8001238 <HAL_RCC_GetSysClockFreq+0xb4>)
80011fe: fb03 f202 mul.w r2, r3, r2
8001202: 69bb ldr r3, [r7, #24]
8001204: fbb2 f3f3 udiv r3, r2, r3
8001208: 627b str r3, [r7, #36] ; 0x24
800120a: e004 b.n 8001216 <HAL_RCC_GetSysClockFreq+0x92>
#endif /*RCC_CFGR2_PREDIV1SRC*/
}
else
{
/* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */
pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul);
800120c: 697b ldr r3, [r7, #20]
800120e: 4a0b ldr r2, [pc, #44] ; (800123c <HAL_RCC_GetSysClockFreq+0xb8>)
8001210: fb02 f303 mul.w r3, r2, r3
8001214: 627b str r3, [r7, #36] ; 0x24
}
sysclockfreq = pllclk;
8001216: 6a7b ldr r3, [r7, #36] ; 0x24
8001218: 623b str r3, [r7, #32]
break;
800121a: e002 b.n 8001222 <HAL_RCC_GetSysClockFreq+0x9e>
}
case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
default: /* HSI used as system clock */
{
sysclockfreq = HSI_VALUE;
800121c: 4b06 ldr r3, [pc, #24] ; (8001238 <HAL_RCC_GetSysClockFreq+0xb4>)
800121e: 623b str r3, [r7, #32]
break;
8001220: bf00 nop
}
}
return sysclockfreq;
8001222: 6a3b ldr r3, [r7, #32]
}
8001224: 4618 mov r0, r3
8001226: 3728 adds r7, #40 ; 0x28
8001228: 46bd mov sp, r7
800122a: bc90 pop {r4, r7}
800122c: 4770 bx lr
800122e: bf00 nop
8001230: 08001fd4 .word 0x08001fd4
8001234: 40021000 .word 0x40021000
8001238: 007a1200 .word 0x007a1200
800123c: 003d0900 .word 0x003d0900
08001240 <HAL_RCC_GetHCLKFreq>:
* @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
* and updated within this function
* @retval HCLK frequency
*/
uint32_t HAL_RCC_GetHCLKFreq(void)
{
8001240: b480 push {r7}
8001242: af00 add r7, sp, #0
return SystemCoreClock;
8001244: 4b02 ldr r3, [pc, #8] ; (8001250 <HAL_RCC_GetHCLKFreq+0x10>)
8001246: 681b ldr r3, [r3, #0]
}
8001248: 4618 mov r0, r3
800124a: 46bd mov sp, r7
800124c: bc80 pop {r7}
800124e: 4770 bx lr
8001250: 20000000 .word 0x20000000
08001254 <HAL_RCC_GetPCLK1Freq>:
* @note Each time PCLK1 changes, this function must be called to update the
* right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
* @retval PCLK1 frequency
*/
uint32_t HAL_RCC_GetPCLK1Freq(void)
{
8001254: b580 push {r7, lr}
8001256: af00 add r7, sp, #0
/* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]);
8001258: f7ff fff2 bl 8001240 <HAL_RCC_GetHCLKFreq>
800125c: 4602 mov r2, r0
800125e: 4b05 ldr r3, [pc, #20] ; (8001274 <HAL_RCC_GetPCLK1Freq+0x20>)
8001260: 685b ldr r3, [r3, #4]
8001262: 0a1b lsrs r3, r3, #8
8001264: f003 0307 and.w r3, r3, #7
8001268: 4903 ldr r1, [pc, #12] ; (8001278 <HAL_RCC_GetPCLK1Freq+0x24>)
800126a: 5ccb ldrb r3, [r1, r3]
800126c: fa22 f303 lsr.w r3, r2, r3
}
8001270: 4618 mov r0, r3
8001272: bd80 pop {r7, pc}
8001274: 40021000 .word 0x40021000
8001278: 08001ff4 .word 0x08001ff4
0800127c <HAL_RCC_GetPCLK2Freq>:
* @note Each time PCLK2 changes, this function must be called to update the
* right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
* @retval PCLK2 frequency
*/
uint32_t HAL_RCC_GetPCLK2Freq(void)
{
800127c: b580 push {r7, lr}
800127e: af00 add r7, sp, #0
/* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]);
8001280: f7ff ffde bl 8001240 <HAL_RCC_GetHCLKFreq>
8001284: 4602 mov r2, r0
8001286: 4b05 ldr r3, [pc, #20] ; (800129c <HAL_RCC_GetPCLK2Freq+0x20>)
8001288: 685b ldr r3, [r3, #4]
800128a: 0adb lsrs r3, r3, #11
800128c: f003 0307 and.w r3, r3, #7
8001290: 4903 ldr r1, [pc, #12] ; (80012a0 <HAL_RCC_GetPCLK2Freq+0x24>)
8001292: 5ccb ldrb r3, [r1, r3]
8001294: fa22 f303 lsr.w r3, r2, r3
}
8001298: 4618 mov r0, r3
800129a: bd80 pop {r7, pc}
800129c: 40021000 .word 0x40021000
80012a0: 08001ff4 .word 0x08001ff4
080012a4 <RCC_Delay>:
* @brief This function provides delay (in milliseconds) based on CPU cycles method.
* @param mdelay: specifies the delay time length, in milliseconds.
* @retval None
*/
static void RCC_Delay(uint32_t mdelay)
{
80012a4: b480 push {r7}
80012a6: b085 sub sp, #20
80012a8: af00 add r7, sp, #0
80012aa: 6078 str r0, [r7, #4]
__IO uint32_t Delay = mdelay * (SystemCoreClock / 8U / 1000U);
80012ac: 4b0a ldr r3, [pc, #40] ; (80012d8 <RCC_Delay+0x34>)
80012ae: 681b ldr r3, [r3, #0]
80012b0: 4a0a ldr r2, [pc, #40] ; (80012dc <RCC_Delay+0x38>)
80012b2: fba2 2303 umull r2, r3, r2, r3
80012b6: 0a5b lsrs r3, r3, #9
80012b8: 687a ldr r2, [r7, #4]
80012ba: fb02 f303 mul.w r3, r2, r3
80012be: 60fb str r3, [r7, #12]
do
{
__NOP();
80012c0: bf00 nop
}
while (Delay --);
80012c2: 68fb ldr r3, [r7, #12]
80012c4: 1e5a subs r2, r3, #1
80012c6: 60fa str r2, [r7, #12]
80012c8: 2b00 cmp r3, #0
80012ca: d1f9 bne.n 80012c0 <RCC_Delay+0x1c>
}
80012cc: bf00 nop
80012ce: bf00 nop
80012d0: 3714 adds r7, #20
80012d2: 46bd mov sp, r7
80012d4: bc80 pop {r7}
80012d6: 4770 bx lr
80012d8: 20000000 .word 0x20000000
80012dc: 10624dd3 .word 0x10624dd3
080012e0 <HAL_UART_Init>:
* @param huart Pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
{
80012e0: b580 push {r7, lr}
80012e2: b082 sub sp, #8
80012e4: af00 add r7, sp, #0
80012e6: 6078 str r0, [r7, #4]
/* Check the UART handle allocation */
if (huart == NULL)
80012e8: 687b ldr r3, [r7, #4]
80012ea: 2b00 cmp r3, #0
80012ec: d101 bne.n 80012f2 <HAL_UART_Init+0x12>
{
return HAL_ERROR;
80012ee: 2301 movs r3, #1
80012f0: e03f b.n 8001372 <HAL_UART_Init+0x92>
assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));
#if defined(USART_CR1_OVER8)
assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling));
#endif /* USART_CR1_OVER8 */
if (huart->gState == HAL_UART_STATE_RESET)
80012f2: 687b ldr r3, [r7, #4]
80012f4: f893 303d ldrb.w r3, [r3, #61] ; 0x3d
80012f8: b2db uxtb r3, r3
80012fa: 2b00 cmp r3, #0
80012fc: d106 bne.n 800130c <HAL_UART_Init+0x2c>
{
/* Allocate lock resource and initialize it */
huart->Lock = HAL_UNLOCKED;
80012fe: 687b ldr r3, [r7, #4]
8001300: 2200 movs r2, #0
8001302: f883 203c strb.w r2, [r3, #60] ; 0x3c
/* Init the low level hardware */
huart->MspInitCallback(huart);
#else
/* Init the low level hardware : GPIO, CLOCK */
HAL_UART_MspInit(huart);
8001306: 6878 ldr r0, [r7, #4]
8001308: f7ff f872 bl 80003f0 <HAL_UART_MspInit>
#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
}
huart->gState = HAL_UART_STATE_BUSY;
800130c: 687b ldr r3, [r7, #4]
800130e: 2224 movs r2, #36 ; 0x24
8001310: f883 203d strb.w r2, [r3, #61] ; 0x3d
/* Disable the peripheral */
__HAL_UART_DISABLE(huart);
8001314: 687b ldr r3, [r7, #4]
8001316: 681b ldr r3, [r3, #0]
8001318: 68da ldr r2, [r3, #12]
800131a: 687b ldr r3, [r7, #4]
800131c: 681b ldr r3, [r3, #0]
800131e: f422 5200 bic.w r2, r2, #8192 ; 0x2000
8001322: 60da str r2, [r3, #12]
/* Set the UART Communication parameters */
UART_SetConfig(huart);
8001324: 6878 ldr r0, [r7, #4]
8001326: f000 f905 bl 8001534 <UART_SetConfig>
/* In asynchronous mode, the following bits must be kept cleared:
- LINEN and CLKEN bits in the USART_CR2 register,
- SCEN, HDSEL and IREN bits in the USART_CR3 register.*/
CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
800132a: 687b ldr r3, [r7, #4]
800132c: 681b ldr r3, [r3, #0]
800132e: 691a ldr r2, [r3, #16]
8001330: 687b ldr r3, [r7, #4]
8001332: 681b ldr r3, [r3, #0]
8001334: f422 4290 bic.w r2, r2, #18432 ; 0x4800
8001338: 611a str r2, [r3, #16]
CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
800133a: 687b ldr r3, [r7, #4]
800133c: 681b ldr r3, [r3, #0]
800133e: 695a ldr r2, [r3, #20]
8001340: 687b ldr r3, [r7, #4]
8001342: 681b ldr r3, [r3, #0]
8001344: f022 022a bic.w r2, r2, #42 ; 0x2a
8001348: 615a str r2, [r3, #20]
/* Enable the peripheral */
__HAL_UART_ENABLE(huart);
800134a: 687b ldr r3, [r7, #4]
800134c: 681b ldr r3, [r3, #0]
800134e: 68da ldr r2, [r3, #12]
8001350: 687b ldr r3, [r7, #4]
8001352: 681b ldr r3, [r3, #0]
8001354: f442 5200 orr.w r2, r2, #8192 ; 0x2000
8001358: 60da str r2, [r3, #12]
/* Initialize the UART state */
huart->ErrorCode = HAL_UART_ERROR_NONE;
800135a: 687b ldr r3, [r7, #4]
800135c: 2200 movs r2, #0
800135e: 641a str r2, [r3, #64] ; 0x40
huart->gState = HAL_UART_STATE_READY;
8001360: 687b ldr r3, [r7, #4]
8001362: 2220 movs r2, #32
8001364: f883 203d strb.w r2, [r3, #61] ; 0x3d
huart->RxState = HAL_UART_STATE_READY;
8001368: 687b ldr r3, [r7, #4]
800136a: 2220 movs r2, #32
800136c: f883 203e strb.w r2, [r3, #62] ; 0x3e
return HAL_OK;
8001370: 2300 movs r3, #0
}
8001372: 4618 mov r0, r3
8001374: 3708 adds r7, #8
8001376: 46bd mov sp, r7
8001378: bd80 pop {r7, pc}
0800137a <HAL_UART_Transmit>:
* @param Size Amount of data elements (u8 or u16) to be sent
* @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
800137a: b580 push {r7, lr}
800137c: b08a sub sp, #40 ; 0x28
800137e: af02 add r7, sp, #8
8001380: 60f8 str r0, [r7, #12]
8001382: 60b9 str r1, [r7, #8]
8001384: 603b str r3, [r7, #0]
8001386: 4613 mov r3, r2
8001388: 80fb strh r3, [r7, #6]
uint8_t *pdata8bits;
uint16_t *pdata16bits;
uint32_t tickstart = 0U;
800138a: 2300 movs r3, #0
800138c: 617b str r3, [r7, #20]
/* Check that a Tx process is not already ongoing */
if (huart->gState == HAL_UART_STATE_READY)
800138e: 68fb ldr r3, [r7, #12]
8001390: f893 303d ldrb.w r3, [r3, #61] ; 0x3d
8001394: b2db uxtb r3, r3
8001396: 2b20 cmp r3, #32
8001398: d17c bne.n 8001494 <HAL_UART_Transmit+0x11a>
{
if ((pData == NULL) || (Size == 0U))
800139a: 68bb ldr r3, [r7, #8]
800139c: 2b00 cmp r3, #0
800139e: d002 beq.n 80013a6 <HAL_UART_Transmit+0x2c>
80013a0: 88fb ldrh r3, [r7, #6]
80013a2: 2b00 cmp r3, #0
80013a4: d101 bne.n 80013aa <HAL_UART_Transmit+0x30>
{
return HAL_ERROR;
80013a6: 2301 movs r3, #1
80013a8: e075 b.n 8001496 <HAL_UART_Transmit+0x11c>
}
/* Process Locked */
__HAL_LOCK(huart);
80013aa: 68fb ldr r3, [r7, #12]
80013ac: f893 303c ldrb.w r3, [r3, #60] ; 0x3c
80013b0: 2b01 cmp r3, #1
80013b2: d101 bne.n 80013b8 <HAL_UART_Transmit+0x3e>
80013b4: 2302 movs r3, #2
80013b6: e06e b.n 8001496 <HAL_UART_Transmit+0x11c>
80013b8: 68fb ldr r3, [r7, #12]
80013ba: 2201 movs r2, #1
80013bc: f883 203c strb.w r2, [r3, #60] ; 0x3c
huart->ErrorCode = HAL_UART_ERROR_NONE;
80013c0: 68fb ldr r3, [r7, #12]
80013c2: 2200 movs r2, #0
80013c4: 641a str r2, [r3, #64] ; 0x40
huart->gState = HAL_UART_STATE_BUSY_TX;
80013c6: 68fb ldr r3, [r7, #12]
80013c8: 2221 movs r2, #33 ; 0x21
80013ca: f883 203d strb.w r2, [r3, #61] ; 0x3d
/* Init tickstart for timeout management */
tickstart = HAL_GetTick();
80013ce: f7ff f8d7 bl 8000580 <HAL_GetTick>
80013d2: 6178 str r0, [r7, #20]
huart->TxXferSize = Size;
80013d4: 68fb ldr r3, [r7, #12]
80013d6: 88fa ldrh r2, [r7, #6]
80013d8: 849a strh r2, [r3, #36] ; 0x24
huart->TxXferCount = Size;
80013da: 68fb ldr r3, [r7, #12]
80013dc: 88fa ldrh r2, [r7, #6]
80013de: 84da strh r2, [r3, #38] ; 0x26
/* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
80013e0: 68fb ldr r3, [r7, #12]
80013e2: 689b ldr r3, [r3, #8]
80013e4: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
80013e8: d108 bne.n 80013fc <HAL_UART_Transmit+0x82>
80013ea: 68fb ldr r3, [r7, #12]
80013ec: 691b ldr r3, [r3, #16]
80013ee: 2b00 cmp r3, #0
80013f0: d104 bne.n 80013fc <HAL_UART_Transmit+0x82>
{
pdata8bits = NULL;
80013f2: 2300 movs r3, #0
80013f4: 61fb str r3, [r7, #28]
pdata16bits = (uint16_t *) pData;
80013f6: 68bb ldr r3, [r7, #8]
80013f8: 61bb str r3, [r7, #24]
80013fa: e003 b.n 8001404 <HAL_UART_Transmit+0x8a>
}
else
{
pdata8bits = pData;
80013fc: 68bb ldr r3, [r7, #8]
80013fe: 61fb str r3, [r7, #28]
pdata16bits = NULL;
8001400: 2300 movs r3, #0
8001402: 61bb str r3, [r7, #24]
}
/* Process Unlocked */
__HAL_UNLOCK(huart);
8001404: 68fb ldr r3, [r7, #12]
8001406: 2200 movs r2, #0
8001408: f883 203c strb.w r2, [r3, #60] ; 0x3c
while (huart->TxXferCount > 0U)
800140c: e02a b.n 8001464 <HAL_UART_Transmit+0xea>
{
if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
800140e: 683b ldr r3, [r7, #0]
8001410: 9300 str r3, [sp, #0]
8001412: 697b ldr r3, [r7, #20]
8001414: 2200 movs r2, #0
8001416: 2180 movs r1, #128 ; 0x80
8001418: 68f8 ldr r0, [r7, #12]
800141a: f000 f840 bl 800149e <UART_WaitOnFlagUntilTimeout>
800141e: 4603 mov r3, r0
8001420: 2b00 cmp r3, #0
8001422: d001 beq.n 8001428 <HAL_UART_Transmit+0xae>
{
return HAL_TIMEOUT;
8001424: 2303 movs r3, #3
8001426: e036 b.n 8001496 <HAL_UART_Transmit+0x11c>
}
if (pdata8bits == NULL)
8001428: 69fb ldr r3, [r7, #28]
800142a: 2b00 cmp r3, #0
800142c: d10b bne.n 8001446 <HAL_UART_Transmit+0xcc>
{
huart->Instance->DR = (uint16_t)(*pdata16bits & 0x01FFU);
800142e: 69bb ldr r3, [r7, #24]
8001430: 881b ldrh r3, [r3, #0]
8001432: 461a mov r2, r3
8001434: 68fb ldr r3, [r7, #12]
8001436: 681b ldr r3, [r3, #0]
8001438: f3c2 0208 ubfx r2, r2, #0, #9
800143c: 605a str r2, [r3, #4]
pdata16bits++;
800143e: 69bb ldr r3, [r7, #24]
8001440: 3302 adds r3, #2
8001442: 61bb str r3, [r7, #24]
8001444: e007 b.n 8001456 <HAL_UART_Transmit+0xdc>
}
else
{
huart->Instance->DR = (uint8_t)(*pdata8bits & 0xFFU);
8001446: 69fb ldr r3, [r7, #28]
8001448: 781a ldrb r2, [r3, #0]
800144a: 68fb ldr r3, [r7, #12]
800144c: 681b ldr r3, [r3, #0]
800144e: 605a str r2, [r3, #4]
pdata8bits++;
8001450: 69fb ldr r3, [r7, #28]
8001452: 3301 adds r3, #1
8001454: 61fb str r3, [r7, #28]
}
huart->TxXferCount--;
8001456: 68fb ldr r3, [r7, #12]
8001458: 8cdb ldrh r3, [r3, #38] ; 0x26
800145a: b29b uxth r3, r3
800145c: 3b01 subs r3, #1
800145e: b29a uxth r2, r3
8001460: 68fb ldr r3, [r7, #12]
8001462: 84da strh r2, [r3, #38] ; 0x26
while (huart->TxXferCount > 0U)
8001464: 68fb ldr r3, [r7, #12]
8001466: 8cdb ldrh r3, [r3, #38] ; 0x26
8001468: b29b uxth r3, r3
800146a: 2b00 cmp r3, #0
800146c: d1cf bne.n 800140e <HAL_UART_Transmit+0x94>
}
if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
800146e: 683b ldr r3, [r7, #0]
8001470: 9300 str r3, [sp, #0]
8001472: 697b ldr r3, [r7, #20]
8001474: 2200 movs r2, #0
8001476: 2140 movs r1, #64 ; 0x40
8001478: 68f8 ldr r0, [r7, #12]
800147a: f000 f810 bl 800149e <UART_WaitOnFlagUntilTimeout>
800147e: 4603 mov r3, r0
8001480: 2b00 cmp r3, #0
8001482: d001 beq.n 8001488 <HAL_UART_Transmit+0x10e>
{
return HAL_TIMEOUT;
8001484: 2303 movs r3, #3
8001486: e006 b.n 8001496 <HAL_UART_Transmit+0x11c>
}
/* At end of Tx process, restore huart->gState to Ready */
huart->gState = HAL_UART_STATE_READY;
8001488: 68fb ldr r3, [r7, #12]
800148a: 2220 movs r2, #32
800148c: f883 203d strb.w r2, [r3, #61] ; 0x3d
return HAL_OK;
8001490: 2300 movs r3, #0
8001492: e000 b.n 8001496 <HAL_UART_Transmit+0x11c>
}
else
{
return HAL_BUSY;
8001494: 2302 movs r3, #2
}
}
8001496: 4618 mov r0, r3
8001498: 3720 adds r7, #32
800149a: 46bd mov sp, r7
800149c: bd80 pop {r7, pc}
0800149e <UART_WaitOnFlagUntilTimeout>:
* @param Tickstart Tick start value
* @param Timeout Timeout duration
* @retval HAL status
*/
static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
{
800149e: b580 push {r7, lr}
80014a0: b084 sub sp, #16
80014a2: af00 add r7, sp, #0
80014a4: 60f8 str r0, [r7, #12]
80014a6: 60b9 str r1, [r7, #8]
80014a8: 603b str r3, [r7, #0]
80014aa: 4613 mov r3, r2
80014ac: 71fb strb r3, [r7, #7]
/* Wait until flag is set */
while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
80014ae: e02c b.n 800150a <UART_WaitOnFlagUntilTimeout+0x6c>
{
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
80014b0: 69bb ldr r3, [r7, #24]
80014b2: f1b3 3fff cmp.w r3, #4294967295
80014b6: d028 beq.n 800150a <UART_WaitOnFlagUntilTimeout+0x6c>
{
if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout))
80014b8: 69bb ldr r3, [r7, #24]
80014ba: 2b00 cmp r3, #0
80014bc: d007 beq.n 80014ce <UART_WaitOnFlagUntilTimeout+0x30>
80014be: f7ff f85f bl 8000580 <HAL_GetTick>
80014c2: 4602 mov r2, r0
80014c4: 683b ldr r3, [r7, #0]
80014c6: 1ad3 subs r3, r2, r3
80014c8: 69ba ldr r2, [r7, #24]
80014ca: 429a cmp r2, r3
80014cc: d21d bcs.n 800150a <UART_WaitOnFlagUntilTimeout+0x6c>
{
/* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
80014ce: 68fb ldr r3, [r7, #12]
80014d0: 681b ldr r3, [r3, #0]
80014d2: 68da ldr r2, [r3, #12]
80014d4: 68fb ldr r3, [r7, #12]
80014d6: 681b ldr r3, [r3, #0]
80014d8: f422 72d0 bic.w r2, r2, #416 ; 0x1a0
80014dc: 60da str r2, [r3, #12]
CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
80014de: 68fb ldr r3, [r7, #12]
80014e0: 681b ldr r3, [r3, #0]
80014e2: 695a ldr r2, [r3, #20]
80014e4: 68fb ldr r3, [r7, #12]
80014e6: 681b ldr r3, [r3, #0]
80014e8: f022 0201 bic.w r2, r2, #1
80014ec: 615a str r2, [r3, #20]
huart->gState = HAL_UART_STATE_READY;
80014ee: 68fb ldr r3, [r7, #12]
80014f0: 2220 movs r2, #32
80014f2: f883 203d strb.w r2, [r3, #61] ; 0x3d
huart->RxState = HAL_UART_STATE_READY;
80014f6: 68fb ldr r3, [r7, #12]
80014f8: 2220 movs r2, #32
80014fa: f883 203e strb.w r2, [r3, #62] ; 0x3e
/* Process Unlocked */
__HAL_UNLOCK(huart);
80014fe: 68fb ldr r3, [r7, #12]
8001500: 2200 movs r2, #0
8001502: f883 203c strb.w r2, [r3, #60] ; 0x3c
return HAL_TIMEOUT;
8001506: 2303 movs r3, #3
8001508: e00f b.n 800152a <UART_WaitOnFlagUntilTimeout+0x8c>
while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
800150a: 68fb ldr r3, [r7, #12]
800150c: 681b ldr r3, [r3, #0]
800150e: 681a ldr r2, [r3, #0]
8001510: 68bb ldr r3, [r7, #8]
8001512: 4013 ands r3, r2
8001514: 68ba ldr r2, [r7, #8]
8001516: 429a cmp r2, r3
8001518: bf0c ite eq
800151a: 2301 moveq r3, #1
800151c: 2300 movne r3, #0
800151e: b2db uxtb r3, r3
8001520: 461a mov r2, r3
8001522: 79fb ldrb r3, [r7, #7]
8001524: 429a cmp r2, r3
8001526: d0c3 beq.n 80014b0 <UART_WaitOnFlagUntilTimeout+0x12>
}
}
}
return HAL_OK;
8001528: 2300 movs r3, #0
}
800152a: 4618 mov r0, r3
800152c: 3710 adds r7, #16
800152e: 46bd mov sp, r7
8001530: bd80 pop {r7, pc}
...
08001534 <UART_SetConfig>:
* @param huart Pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval None
*/
static void UART_SetConfig(UART_HandleTypeDef *huart)
{
8001534: b580 push {r7, lr}
8001536: b084 sub sp, #16
8001538: af00 add r7, sp, #0
800153a: 6078 str r0, [r7, #4]
assert_param(IS_UART_MODE(huart->Init.Mode));
/*-------------------------- USART CR2 Configuration -----------------------*/
/* Configure the UART Stop Bits: Set STOP[13:12] bits
according to huart->Init.StopBits value */
MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
800153c: 687b ldr r3, [r7, #4]
800153e: 681b ldr r3, [r3, #0]
8001540: 691b ldr r3, [r3, #16]
8001542: f423 5140 bic.w r1, r3, #12288 ; 0x3000
8001546: 687b ldr r3, [r7, #4]
8001548: 68da ldr r2, [r3, #12]
800154a: 687b ldr r3, [r7, #4]
800154c: 681b ldr r3, [r3, #0]
800154e: 430a orrs r2, r1
8001550: 611a str r2, [r3, #16]
tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling;
MODIFY_REG(huart->Instance->CR1,
(uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8),
tmpreg);
#else
tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode;
8001552: 687b ldr r3, [r7, #4]
8001554: 689a ldr r2, [r3, #8]
8001556: 687b ldr r3, [r7, #4]
8001558: 691b ldr r3, [r3, #16]
800155a: 431a orrs r2, r3
800155c: 687b ldr r3, [r7, #4]
800155e: 695b ldr r3, [r3, #20]
8001560: 4313 orrs r3, r2
8001562: 60bb str r3, [r7, #8]
MODIFY_REG(huart->Instance->CR1,
8001564: 687b ldr r3, [r7, #4]
8001566: 681b ldr r3, [r3, #0]
8001568: 68db ldr r3, [r3, #12]
800156a: f423 53b0 bic.w r3, r3, #5632 ; 0x1600
800156e: f023 030c bic.w r3, r3, #12
8001572: 687a ldr r2, [r7, #4]
8001574: 6812 ldr r2, [r2, #0]
8001576: 68b9 ldr r1, [r7, #8]
8001578: 430b orrs r3, r1
800157a: 60d3 str r3, [r2, #12]
tmpreg);
#endif /* USART_CR1_OVER8 */
/*-------------------------- USART CR3 Configuration -----------------------*/
/* Configure the UART HFC: Set CTSE and RTSE bits according to huart->Init.HwFlowCtl value */
MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE), huart->Init.HwFlowCtl);
800157c: 687b ldr r3, [r7, #4]
800157e: 681b ldr r3, [r3, #0]
8001580: 695b ldr r3, [r3, #20]
8001582: f423 7140 bic.w r1, r3, #768 ; 0x300
8001586: 687b ldr r3, [r7, #4]
8001588: 699a ldr r2, [r3, #24]
800158a: 687b ldr r3, [r7, #4]
800158c: 681b ldr r3, [r3, #0]
800158e: 430a orrs r2, r1
8001590: 615a str r2, [r3, #20]
if(huart->Instance == USART1)
8001592: 687b ldr r3, [r7, #4]
8001594: 681b ldr r3, [r3, #0]
8001596: 4a2c ldr r2, [pc, #176] ; (8001648 <UART_SetConfig+0x114>)
8001598: 4293 cmp r3, r2
800159a: d103 bne.n 80015a4 <UART_SetConfig+0x70>
{
pclk = HAL_RCC_GetPCLK2Freq();
800159c: f7ff fe6e bl 800127c <HAL_RCC_GetPCLK2Freq>
80015a0: 60f8 str r0, [r7, #12]
80015a2: e002 b.n 80015aa <UART_SetConfig+0x76>
}
else
{
pclk = HAL_RCC_GetPCLK1Freq();
80015a4: f7ff fe56 bl 8001254 <HAL_RCC_GetPCLK1Freq>
80015a8: 60f8 str r0, [r7, #12]
else
{
huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate);
}
#else
huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate);
80015aa: 68fa ldr r2, [r7, #12]
80015ac: 4613 mov r3, r2
80015ae: 009b lsls r3, r3, #2
80015b0: 4413 add r3, r2
80015b2: 009a lsls r2, r3, #2
80015b4: 441a add r2, r3
80015b6: 687b ldr r3, [r7, #4]
80015b8: 685b ldr r3, [r3, #4]
80015ba: 009b lsls r3, r3, #2
80015bc: fbb2 f3f3 udiv r3, r2, r3
80015c0: 4a22 ldr r2, [pc, #136] ; (800164c <UART_SetConfig+0x118>)
80015c2: fba2 2303 umull r2, r3, r2, r3
80015c6: 095b lsrs r3, r3, #5
80015c8: 0119 lsls r1, r3, #4
80015ca: 68fa ldr r2, [r7, #12]
80015cc: 4613 mov r3, r2
80015ce: 009b lsls r3, r3, #2
80015d0: 4413 add r3, r2
80015d2: 009a lsls r2, r3, #2
80015d4: 441a add r2, r3
80015d6: 687b ldr r3, [r7, #4]
80015d8: 685b ldr r3, [r3, #4]
80015da: 009b lsls r3, r3, #2
80015dc: fbb2 f2f3 udiv r2, r2, r3
80015e0: 4b1a ldr r3, [pc, #104] ; (800164c <UART_SetConfig+0x118>)
80015e2: fba3 0302 umull r0, r3, r3, r2
80015e6: 095b lsrs r3, r3, #5
80015e8: 2064 movs r0, #100 ; 0x64
80015ea: fb00 f303 mul.w r3, r0, r3
80015ee: 1ad3 subs r3, r2, r3
80015f0: 011b lsls r3, r3, #4
80015f2: 3332 adds r3, #50 ; 0x32
80015f4: 4a15 ldr r2, [pc, #84] ; (800164c <UART_SetConfig+0x118>)
80015f6: fba2 2303 umull r2, r3, r2, r3
80015fa: 095b lsrs r3, r3, #5
80015fc: f003 03f0 and.w r3, r3, #240 ; 0xf0
8001600: 4419 add r1, r3
8001602: 68fa ldr r2, [r7, #12]
8001604: 4613 mov r3, r2
8001606: 009b lsls r3, r3, #2
8001608: 4413 add r3, r2
800160a: 009a lsls r2, r3, #2
800160c: 441a add r2, r3
800160e: 687b ldr r3, [r7, #4]
8001610: 685b ldr r3, [r3, #4]
8001612: 009b lsls r3, r3, #2
8001614: fbb2 f2f3 udiv r2, r2, r3
8001618: 4b0c ldr r3, [pc, #48] ; (800164c <UART_SetConfig+0x118>)
800161a: fba3 0302 umull r0, r3, r3, r2
800161e: 095b lsrs r3, r3, #5
8001620: 2064 movs r0, #100 ; 0x64
8001622: fb00 f303 mul.w r3, r0, r3
8001626: 1ad3 subs r3, r2, r3
8001628: 011b lsls r3, r3, #4
800162a: 3332 adds r3, #50 ; 0x32
800162c: 4a07 ldr r2, [pc, #28] ; (800164c <UART_SetConfig+0x118>)
800162e: fba2 2303 umull r2, r3, r2, r3
8001632: 095b lsrs r3, r3, #5
8001634: f003 020f and.w r2, r3, #15
8001638: 687b ldr r3, [r7, #4]
800163a: 681b ldr r3, [r3, #0]
800163c: 440a add r2, r1
800163e: 609a str r2, [r3, #8]
#endif /* USART_CR1_OVER8 */
}
8001640: bf00 nop
8001642: 3710 adds r7, #16
8001644: 46bd mov sp, r7
8001646: bd80 pop {r7, pc}
8001648: 40013800 .word 0x40013800
800164c: 51eb851f .word 0x51eb851f
08001650 <__errno>:
8001650: 4b01 ldr r3, [pc, #4] ; (8001658 <__errno+0x8>)
8001652: 6818 ldr r0, [r3, #0]
8001654: 4770 bx lr
8001656: bf00 nop
8001658: 2000000c .word 0x2000000c
0800165c <__libc_init_array>:
800165c: b570 push {r4, r5, r6, lr}
800165e: 2600 movs r6, #0
8001660: 4d0c ldr r5, [pc, #48] ; (8001694 <__libc_init_array+0x38>)
8001662: 4c0d ldr r4, [pc, #52] ; (8001698 <__libc_init_array+0x3c>)
8001664: 1b64 subs r4, r4, r5
8001666: 10a4 asrs r4, r4, #2
8001668: 42a6 cmp r6, r4
800166a: d109 bne.n 8001680 <__libc_init_array+0x24>
800166c: f000 fc9c bl 8001fa8 <_init>
8001670: 2600 movs r6, #0
8001672: 4d0a ldr r5, [pc, #40] ; (800169c <__libc_init_array+0x40>)
8001674: 4c0a ldr r4, [pc, #40] ; (80016a0 <__libc_init_array+0x44>)
8001676: 1b64 subs r4, r4, r5
8001678: 10a4 asrs r4, r4, #2
800167a: 42a6 cmp r6, r4
800167c: d105 bne.n 800168a <__libc_init_array+0x2e>
800167e: bd70 pop {r4, r5, r6, pc}
8001680: f855 3b04 ldr.w r3, [r5], #4
8001684: 4798 blx r3
8001686: 3601 adds r6, #1
8001688: e7ee b.n 8001668 <__libc_init_array+0xc>
800168a: f855 3b04 ldr.w r3, [r5], #4
800168e: 4798 blx r3
8001690: 3601 adds r6, #1
8001692: e7f2 b.n 800167a <__libc_init_array+0x1e>
8001694: 08002030 .word 0x08002030
8001698: 08002030 .word 0x08002030
800169c: 08002030 .word 0x08002030
80016a0: 08002034 .word 0x08002034
080016a4 <memset>:
80016a4: 4603 mov r3, r0
80016a6: 4402 add r2, r0
80016a8: 4293 cmp r3, r2
80016aa: d100 bne.n 80016ae <memset+0xa>
80016ac: 4770 bx lr
80016ae: f803 1b01 strb.w r1, [r3], #1
80016b2: e7f9 b.n 80016a8 <memset+0x4>
080016b4 <siprintf>:
80016b4: b40e push {r1, r2, r3}
80016b6: f06f 4100 mvn.w r1, #2147483648 ; 0x80000000
80016ba: b500 push {lr}
80016bc: b09c sub sp, #112 ; 0x70
80016be: ab1d add r3, sp, #116 ; 0x74
80016c0: 9002 str r0, [sp, #8]
80016c2: 9006 str r0, [sp, #24]
80016c4: 9107 str r1, [sp, #28]
80016c6: 9104 str r1, [sp, #16]
80016c8: 4808 ldr r0, [pc, #32] ; (80016ec <siprintf+0x38>)
80016ca: 4909 ldr r1, [pc, #36] ; (80016f0 <siprintf+0x3c>)
80016cc: f853 2b04 ldr.w r2, [r3], #4
80016d0: 9105 str r1, [sp, #20]
80016d2: 6800 ldr r0, [r0, #0]
80016d4: a902 add r1, sp, #8
80016d6: 9301 str r3, [sp, #4]
80016d8: f000 f868 bl 80017ac <_svfiprintf_r>
80016dc: 2200 movs r2, #0
80016de: 9b02 ldr r3, [sp, #8]
80016e0: 701a strb r2, [r3, #0]
80016e2: b01c add sp, #112 ; 0x70
80016e4: f85d eb04 ldr.w lr, [sp], #4
80016e8: b003 add sp, #12
80016ea: 4770 bx lr
80016ec: 2000000c .word 0x2000000c
80016f0: ffff0208 .word 0xffff0208
080016f4 <__ssputs_r>:
80016f4: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
80016f8: 688e ldr r6, [r1, #8]
80016fa: 4682 mov sl, r0
80016fc: 429e cmp r6, r3
80016fe: 460c mov r4, r1
8001700: 4690 mov r8, r2
8001702: 461f mov r7, r3
8001704: d838 bhi.n 8001778 <__ssputs_r+0x84>
8001706: 898a ldrh r2, [r1, #12]
8001708: f412 6f90 tst.w r2, #1152 ; 0x480
800170c: d032 beq.n 8001774 <__ssputs_r+0x80>
800170e: 6825 ldr r5, [r4, #0]
8001710: 6909 ldr r1, [r1, #16]
8001712: 3301 adds r3, #1
8001714: eba5 0901 sub.w r9, r5, r1
8001718: 6965 ldr r5, [r4, #20]
800171a: 444b add r3, r9
800171c: eb05 0545 add.w r5, r5, r5, lsl #1
8001720: eb05 75d5 add.w r5, r5, r5, lsr #31
8001724: 106d asrs r5, r5, #1
8001726: 429d cmp r5, r3
8001728: bf38 it cc
800172a: 461d movcc r5, r3
800172c: 0553 lsls r3, r2, #21
800172e: d531 bpl.n 8001794 <__ssputs_r+0xa0>
8001730: 4629 mov r1, r5
8001732: f000 fb6f bl 8001e14 <_malloc_r>
8001736: 4606 mov r6, r0
8001738: b950 cbnz r0, 8001750 <__ssputs_r+0x5c>
800173a: 230c movs r3, #12
800173c: f04f 30ff mov.w r0, #4294967295
8001740: f8ca 3000 str.w r3, [sl]
8001744: 89a3 ldrh r3, [r4, #12]
8001746: f043 0340 orr.w r3, r3, #64 ; 0x40
800174a: 81a3 strh r3, [r4, #12]
800174c: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
8001750: 464a mov r2, r9
8001752: 6921 ldr r1, [r4, #16]
8001754: f000 face bl 8001cf4 <memcpy>
8001758: 89a3 ldrh r3, [r4, #12]
800175a: f423 6390 bic.w r3, r3, #1152 ; 0x480
800175e: f043 0380 orr.w r3, r3, #128 ; 0x80
8001762: 81a3 strh r3, [r4, #12]
8001764: 6126 str r6, [r4, #16]
8001766: 444e add r6, r9
8001768: 6026 str r6, [r4, #0]
800176a: 463e mov r6, r7
800176c: 6165 str r5, [r4, #20]
800176e: eba5 0509 sub.w r5, r5, r9
8001772: 60a5 str r5, [r4, #8]
8001774: 42be cmp r6, r7
8001776: d900 bls.n 800177a <__ssputs_r+0x86>
8001778: 463e mov r6, r7
800177a: 4632 mov r2, r6
800177c: 4641 mov r1, r8
800177e: 6820 ldr r0, [r4, #0]
8001780: f000 fac6 bl 8001d10 <memmove>
8001784: 68a3 ldr r3, [r4, #8]
8001786: 2000 movs r0, #0
8001788: 1b9b subs r3, r3, r6
800178a: 60a3 str r3, [r4, #8]
800178c: 6823 ldr r3, [r4, #0]
800178e: 4433 add r3, r6
8001790: 6023 str r3, [r4, #0]
8001792: e7db b.n 800174c <__ssputs_r+0x58>
8001794: 462a mov r2, r5
8001796: f000 fbb1 bl 8001efc <_realloc_r>
800179a: 4606 mov r6, r0
800179c: 2800 cmp r0, #0
800179e: d1e1 bne.n 8001764 <__ssputs_r+0x70>
80017a0: 4650 mov r0, sl
80017a2: 6921 ldr r1, [r4, #16]
80017a4: f000 face bl 8001d44 <_free_r>
80017a8: e7c7 b.n 800173a <__ssputs_r+0x46>
...
080017ac <_svfiprintf_r>:
80017ac: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
80017b0: 4698 mov r8, r3
80017b2: 898b ldrh r3, [r1, #12]
80017b4: 4607 mov r7, r0
80017b6: 061b lsls r3, r3, #24
80017b8: 460d mov r5, r1
80017ba: 4614 mov r4, r2
80017bc: b09d sub sp, #116 ; 0x74
80017be: d50e bpl.n 80017de <_svfiprintf_r+0x32>
80017c0: 690b ldr r3, [r1, #16]
80017c2: b963 cbnz r3, 80017de <_svfiprintf_r+0x32>
80017c4: 2140 movs r1, #64 ; 0x40
80017c6: f000 fb25 bl 8001e14 <_malloc_r>
80017ca: 6028 str r0, [r5, #0]
80017cc: 6128 str r0, [r5, #16]
80017ce: b920 cbnz r0, 80017da <_svfiprintf_r+0x2e>
80017d0: 230c movs r3, #12
80017d2: 603b str r3, [r7, #0]
80017d4: f04f 30ff mov.w r0, #4294967295
80017d8: e0d1 b.n 800197e <_svfiprintf_r+0x1d2>
80017da: 2340 movs r3, #64 ; 0x40
80017dc: 616b str r3, [r5, #20]
80017de: 2300 movs r3, #0
80017e0: 9309 str r3, [sp, #36] ; 0x24
80017e2: 2320 movs r3, #32
80017e4: f88d 3029 strb.w r3, [sp, #41] ; 0x29
80017e8: 2330 movs r3, #48 ; 0x30
80017ea: f04f 0901 mov.w r9, #1
80017ee: f8cd 800c str.w r8, [sp, #12]
80017f2: f8df 81a4 ldr.w r8, [pc, #420] ; 8001998 <_svfiprintf_r+0x1ec>
80017f6: f88d 302a strb.w r3, [sp, #42] ; 0x2a
80017fa: 4623 mov r3, r4
80017fc: 469a mov sl, r3
80017fe: f813 2b01 ldrb.w r2, [r3], #1
8001802: b10a cbz r2, 8001808 <_svfiprintf_r+0x5c>
8001804: 2a25 cmp r2, #37 ; 0x25
8001806: d1f9 bne.n 80017fc <_svfiprintf_r+0x50>
8001808: ebba 0b04 subs.w fp, sl, r4
800180c: d00b beq.n 8001826 <_svfiprintf_r+0x7a>
800180e: 465b mov r3, fp
8001810: 4622 mov r2, r4
8001812: 4629 mov r1, r5
8001814: 4638 mov r0, r7
8001816: f7ff ff6d bl 80016f4 <__ssputs_r>
800181a: 3001 adds r0, #1
800181c: f000 80aa beq.w 8001974 <_svfiprintf_r+0x1c8>
8001820: 9a09 ldr r2, [sp, #36] ; 0x24
8001822: 445a add r2, fp
8001824: 9209 str r2, [sp, #36] ; 0x24
8001826: f89a 3000 ldrb.w r3, [sl]
800182a: 2b00 cmp r3, #0
800182c: f000 80a2 beq.w 8001974 <_svfiprintf_r+0x1c8>
8001830: 2300 movs r3, #0
8001832: f04f 32ff mov.w r2, #4294967295
8001836: e9cd 2305 strd r2, r3, [sp, #20]
800183a: f10a 0a01 add.w sl, sl, #1
800183e: 9304 str r3, [sp, #16]
8001840: 9307 str r3, [sp, #28]
8001842: f88d 3053 strb.w r3, [sp, #83] ; 0x53
8001846: 931a str r3, [sp, #104] ; 0x68
8001848: 4654 mov r4, sl
800184a: 2205 movs r2, #5
800184c: f814 1b01 ldrb.w r1, [r4], #1
8001850: 4851 ldr r0, [pc, #324] ; (8001998 <_svfiprintf_r+0x1ec>)
8001852: f000 fa41 bl 8001cd8 <memchr>
8001856: 9a04 ldr r2, [sp, #16]
8001858: b9d8 cbnz r0, 8001892 <_svfiprintf_r+0xe6>
800185a: 06d0 lsls r0, r2, #27
800185c: bf44 itt mi
800185e: 2320 movmi r3, #32
8001860: f88d 3053 strbmi.w r3, [sp, #83] ; 0x53
8001864: 0711 lsls r1, r2, #28
8001866: bf44 itt mi
8001868: 232b movmi r3, #43 ; 0x2b
800186a: f88d 3053 strbmi.w r3, [sp, #83] ; 0x53
800186e: f89a 3000 ldrb.w r3, [sl]
8001872: 2b2a cmp r3, #42 ; 0x2a
8001874: d015 beq.n 80018a2 <_svfiprintf_r+0xf6>
8001876: 4654 mov r4, sl
8001878: 2000 movs r0, #0
800187a: f04f 0c0a mov.w ip, #10
800187e: 9a07 ldr r2, [sp, #28]
8001880: 4621 mov r1, r4
8001882: f811 3b01 ldrb.w r3, [r1], #1
8001886: 3b30 subs r3, #48 ; 0x30
8001888: 2b09 cmp r3, #9
800188a: d94e bls.n 800192a <_svfiprintf_r+0x17e>
800188c: b1b0 cbz r0, 80018bc <_svfiprintf_r+0x110>
800188e: 9207 str r2, [sp, #28]
8001890: e014 b.n 80018bc <_svfiprintf_r+0x110>
8001892: eba0 0308 sub.w r3, r0, r8
8001896: fa09 f303 lsl.w r3, r9, r3
800189a: 4313 orrs r3, r2
800189c: 46a2 mov sl, r4
800189e: 9304 str r3, [sp, #16]
80018a0: e7d2 b.n 8001848 <_svfiprintf_r+0x9c>
80018a2: 9b03 ldr r3, [sp, #12]
80018a4: 1d19 adds r1, r3, #4
80018a6: 681b ldr r3, [r3, #0]
80018a8: 9103 str r1, [sp, #12]
80018aa: 2b00 cmp r3, #0
80018ac: bfbb ittet lt
80018ae: 425b neglt r3, r3
80018b0: f042 0202 orrlt.w r2, r2, #2
80018b4: 9307 strge r3, [sp, #28]
80018b6: 9307 strlt r3, [sp, #28]
80018b8: bfb8 it lt
80018ba: 9204 strlt r2, [sp, #16]
80018bc: 7823 ldrb r3, [r4, #0]
80018be: 2b2e cmp r3, #46 ; 0x2e
80018c0: d10c bne.n 80018dc <_svfiprintf_r+0x130>
80018c2: 7863 ldrb r3, [r4, #1]
80018c4: 2b2a cmp r3, #42 ; 0x2a
80018c6: d135 bne.n 8001934 <_svfiprintf_r+0x188>
80018c8: 9b03 ldr r3, [sp, #12]
80018ca: 3402 adds r4, #2
80018cc: 1d1a adds r2, r3, #4
80018ce: 681b ldr r3, [r3, #0]
80018d0: 9203 str r2, [sp, #12]
80018d2: 2b00 cmp r3, #0
80018d4: bfb8 it lt
80018d6: f04f 33ff movlt.w r3, #4294967295
80018da: 9305 str r3, [sp, #20]
80018dc: f8df a0bc ldr.w sl, [pc, #188] ; 800199c <_svfiprintf_r+0x1f0>
80018e0: 2203 movs r2, #3
80018e2: 4650 mov r0, sl
80018e4: 7821 ldrb r1, [r4, #0]
80018e6: f000 f9f7 bl 8001cd8 <memchr>
80018ea: b140 cbz r0, 80018fe <_svfiprintf_r+0x152>
80018ec: 2340 movs r3, #64 ; 0x40
80018ee: eba0 000a sub.w r0, r0, sl
80018f2: fa03 f000 lsl.w r0, r3, r0
80018f6: 9b04 ldr r3, [sp, #16]
80018f8: 3401 adds r4, #1
80018fa: 4303 orrs r3, r0
80018fc: 9304 str r3, [sp, #16]
80018fe: f814 1b01 ldrb.w r1, [r4], #1
8001902: 2206 movs r2, #6
8001904: 4826 ldr r0, [pc, #152] ; (80019a0 <_svfiprintf_r+0x1f4>)
8001906: f88d 1028 strb.w r1, [sp, #40] ; 0x28
800190a: f000 f9e5 bl 8001cd8 <memchr>
800190e: 2800 cmp r0, #0
8001910: d038 beq.n 8001984 <_svfiprintf_r+0x1d8>
8001912: 4b24 ldr r3, [pc, #144] ; (80019a4 <_svfiprintf_r+0x1f8>)
8001914: bb1b cbnz r3, 800195e <_svfiprintf_r+0x1b2>
8001916: 9b03 ldr r3, [sp, #12]
8001918: 3307 adds r3, #7
800191a: f023 0307 bic.w r3, r3, #7
800191e: 3308 adds r3, #8
8001920: 9303 str r3, [sp, #12]
8001922: 9b09 ldr r3, [sp, #36] ; 0x24
8001924: 4433 add r3, r6
8001926: 9309 str r3, [sp, #36] ; 0x24
8001928: e767 b.n 80017fa <_svfiprintf_r+0x4e>
800192a: 460c mov r4, r1
800192c: 2001 movs r0, #1
800192e: fb0c 3202 mla r2, ip, r2, r3
8001932: e7a5 b.n 8001880 <_svfiprintf_r+0xd4>
8001934: 2300 movs r3, #0
8001936: f04f 0c0a mov.w ip, #10
800193a: 4619 mov r1, r3
800193c: 3401 adds r4, #1
800193e: 9305 str r3, [sp, #20]
8001940: 4620 mov r0, r4
8001942: f810 2b01 ldrb.w r2, [r0], #1
8001946: 3a30 subs r2, #48 ; 0x30
8001948: 2a09 cmp r2, #9
800194a: d903 bls.n 8001954 <_svfiprintf_r+0x1a8>
800194c: 2b00 cmp r3, #0
800194e: d0c5 beq.n 80018dc <_svfiprintf_r+0x130>
8001950: 9105 str r1, [sp, #20]
8001952: e7c3 b.n 80018dc <_svfiprintf_r+0x130>
8001954: 4604 mov r4, r0
8001956: 2301 movs r3, #1
8001958: fb0c 2101 mla r1, ip, r1, r2
800195c: e7f0 b.n 8001940 <_svfiprintf_r+0x194>
800195e: ab03 add r3, sp, #12
8001960: 9300 str r3, [sp, #0]
8001962: 462a mov r2, r5
8001964: 4638 mov r0, r7
8001966: 4b10 ldr r3, [pc, #64] ; (80019a8 <_svfiprintf_r+0x1fc>)
8001968: a904 add r1, sp, #16
800196a: f3af 8000 nop.w
800196e: 1c42 adds r2, r0, #1
8001970: 4606 mov r6, r0
8001972: d1d6 bne.n 8001922 <_svfiprintf_r+0x176>
8001974: 89ab ldrh r3, [r5, #12]
8001976: 065b lsls r3, r3, #25
8001978: f53f af2c bmi.w 80017d4 <_svfiprintf_r+0x28>
800197c: 9809 ldr r0, [sp, #36] ; 0x24
800197e: b01d add sp, #116 ; 0x74
8001980: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
8001984: ab03 add r3, sp, #12
8001986: 9300 str r3, [sp, #0]
8001988: 462a mov r2, r5
800198a: 4638 mov r0, r7
800198c: 4b06 ldr r3, [pc, #24] ; (80019a8 <_svfiprintf_r+0x1fc>)
800198e: a904 add r1, sp, #16
8001990: f000 f87c bl 8001a8c <_printf_i>
8001994: e7eb b.n 800196e <_svfiprintf_r+0x1c2>
8001996: bf00 nop
8001998: 08001ffc .word 0x08001ffc
800199c: 08002002 .word 0x08002002
80019a0: 08002006 .word 0x08002006
80019a4: 00000000 .word 0x00000000
80019a8: 080016f5 .word 0x080016f5
080019ac <_printf_common>:
80019ac: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
80019b0: 4616 mov r6, r2
80019b2: 4699 mov r9, r3
80019b4: 688a ldr r2, [r1, #8]
80019b6: 690b ldr r3, [r1, #16]
80019b8: 4607 mov r7, r0
80019ba: 4293 cmp r3, r2
80019bc: bfb8 it lt
80019be: 4613 movlt r3, r2
80019c0: 6033 str r3, [r6, #0]
80019c2: f891 2043 ldrb.w r2, [r1, #67] ; 0x43
80019c6: 460c mov r4, r1
80019c8: f8dd 8020 ldr.w r8, [sp, #32]
80019cc: b10a cbz r2, 80019d2 <_printf_common+0x26>
80019ce: 3301 adds r3, #1
80019d0: 6033 str r3, [r6, #0]
80019d2: 6823 ldr r3, [r4, #0]
80019d4: 0699 lsls r1, r3, #26
80019d6: bf42 ittt mi
80019d8: 6833 ldrmi r3, [r6, #0]
80019da: 3302 addmi r3, #2
80019dc: 6033 strmi r3, [r6, #0]
80019de: 6825 ldr r5, [r4, #0]
80019e0: f015 0506 ands.w r5, r5, #6
80019e4: d106 bne.n 80019f4 <_printf_common+0x48>
80019e6: f104 0a19 add.w sl, r4, #25
80019ea: 68e3 ldr r3, [r4, #12]
80019ec: 6832 ldr r2, [r6, #0]
80019ee: 1a9b subs r3, r3, r2
80019f0: 42ab cmp r3, r5
80019f2: dc28 bgt.n 8001a46 <_printf_common+0x9a>
80019f4: f894 2043 ldrb.w r2, [r4, #67] ; 0x43
80019f8: 1e13 subs r3, r2, #0
80019fa: 6822 ldr r2, [r4, #0]
80019fc: bf18 it ne
80019fe: 2301 movne r3, #1
8001a00: 0692 lsls r2, r2, #26
8001a02: d42d bmi.n 8001a60 <_printf_common+0xb4>
8001a04: 4649 mov r1, r9
8001a06: 4638 mov r0, r7
8001a08: f104 0243 add.w r2, r4, #67 ; 0x43
8001a0c: 47c0 blx r8
8001a0e: 3001 adds r0, #1
8001a10: d020 beq.n 8001a54 <_printf_common+0xa8>
8001a12: 6823 ldr r3, [r4, #0]
8001a14: 68e5 ldr r5, [r4, #12]
8001a16: f003 0306 and.w r3, r3, #6
8001a1a: 2b04 cmp r3, #4
8001a1c: bf18 it ne
8001a1e: 2500 movne r5, #0
8001a20: 6832 ldr r2, [r6, #0]
8001a22: f04f 0600 mov.w r6, #0
8001a26: 68a3 ldr r3, [r4, #8]
8001a28: bf08 it eq
8001a2a: 1aad subeq r5, r5, r2
8001a2c: 6922 ldr r2, [r4, #16]
8001a2e: bf08 it eq
8001a30: ea25 75e5 biceq.w r5, r5, r5, asr #31
8001a34: 4293 cmp r3, r2
8001a36: bfc4 itt gt
8001a38: 1a9b subgt r3, r3, r2
8001a3a: 18ed addgt r5, r5, r3
8001a3c: 341a adds r4, #26
8001a3e: 42b5 cmp r5, r6
8001a40: d11a bne.n 8001a78 <_printf_common+0xcc>
8001a42: 2000 movs r0, #0
8001a44: e008 b.n 8001a58 <_printf_common+0xac>
8001a46: 2301 movs r3, #1
8001a48: 4652 mov r2, sl
8001a4a: 4649 mov r1, r9
8001a4c: 4638 mov r0, r7
8001a4e: 47c0 blx r8
8001a50: 3001 adds r0, #1
8001a52: d103 bne.n 8001a5c <_printf_common+0xb0>
8001a54: f04f 30ff mov.w r0, #4294967295
8001a58: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
8001a5c: 3501 adds r5, #1
8001a5e: e7c4 b.n 80019ea <_printf_common+0x3e>
8001a60: 2030 movs r0, #48 ; 0x30
8001a62: 18e1 adds r1, r4, r3
8001a64: f881 0043 strb.w r0, [r1, #67] ; 0x43
8001a68: 1c5a adds r2, r3, #1
8001a6a: f894 1045 ldrb.w r1, [r4, #69] ; 0x45
8001a6e: 4422 add r2, r4
8001a70: 3302 adds r3, #2
8001a72: f882 1043 strb.w r1, [r2, #67] ; 0x43
8001a76: e7c5 b.n 8001a04 <_printf_common+0x58>
8001a78: 2301 movs r3, #1
8001a7a: 4622 mov r2, r4
8001a7c: 4649 mov r1, r9
8001a7e: 4638 mov r0, r7
8001a80: 47c0 blx r8
8001a82: 3001 adds r0, #1
8001a84: d0e6 beq.n 8001a54 <_printf_common+0xa8>
8001a86: 3601 adds r6, #1
8001a88: e7d9 b.n 8001a3e <_printf_common+0x92>
...
08001a8c <_printf_i>:
8001a8c: e92d 47ff stmdb sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, lr}
8001a90: 7e0f ldrb r7, [r1, #24]
8001a92: 4691 mov r9, r2
8001a94: 2f78 cmp r7, #120 ; 0x78
8001a96: 4680 mov r8, r0
8001a98: 460c mov r4, r1
8001a9a: 469a mov sl, r3
8001a9c: 9d0c ldr r5, [sp, #48] ; 0x30
8001a9e: f101 0243 add.w r2, r1, #67 ; 0x43
8001aa2: d807 bhi.n 8001ab4 <_printf_i+0x28>
8001aa4: 2f62 cmp r7, #98 ; 0x62
8001aa6: d80a bhi.n 8001abe <_printf_i+0x32>
8001aa8: 2f00 cmp r7, #0
8001aaa: f000 80d9 beq.w 8001c60 <_printf_i+0x1d4>
8001aae: 2f58 cmp r7, #88 ; 0x58
8001ab0: f000 80a4 beq.w 8001bfc <_printf_i+0x170>
8001ab4: f104 0542 add.w r5, r4, #66 ; 0x42
8001ab8: f884 7042 strb.w r7, [r4, #66] ; 0x42
8001abc: e03a b.n 8001b34 <_printf_i+0xa8>
8001abe: f1a7 0363 sub.w r3, r7, #99 ; 0x63
8001ac2: 2b15 cmp r3, #21
8001ac4: d8f6 bhi.n 8001ab4 <_printf_i+0x28>
8001ac6: a101 add r1, pc, #4 ; (adr r1, 8001acc <_printf_i+0x40>)
8001ac8: f851 f023 ldr.w pc, [r1, r3, lsl #2]
8001acc: 08001b25 .word 0x08001b25
8001ad0: 08001b39 .word 0x08001b39
8001ad4: 08001ab5 .word 0x08001ab5
8001ad8: 08001ab5 .word 0x08001ab5
8001adc: 08001ab5 .word 0x08001ab5
8001ae0: 08001ab5 .word 0x08001ab5
8001ae4: 08001b39 .word 0x08001b39
8001ae8: 08001ab5 .word 0x08001ab5
8001aec: 08001ab5 .word 0x08001ab5
8001af0: 08001ab5 .word 0x08001ab5
8001af4: 08001ab5 .word 0x08001ab5
8001af8: 08001c47 .word 0x08001c47
8001afc: 08001b69 .word 0x08001b69
8001b00: 08001c29 .word 0x08001c29
8001b04: 08001ab5 .word 0x08001ab5
8001b08: 08001ab5 .word 0x08001ab5
8001b0c: 08001c69 .word 0x08001c69
8001b10: 08001ab5 .word 0x08001ab5
8001b14: 08001b69 .word 0x08001b69
8001b18: 08001ab5 .word 0x08001ab5
8001b1c: 08001ab5 .word 0x08001ab5
8001b20: 08001c31 .word 0x08001c31
8001b24: 682b ldr r3, [r5, #0]
8001b26: 1d1a adds r2, r3, #4
8001b28: 681b ldr r3, [r3, #0]
8001b2a: 602a str r2, [r5, #0]
8001b2c: f104 0542 add.w r5, r4, #66 ; 0x42
8001b30: f884 3042 strb.w r3, [r4, #66] ; 0x42
8001b34: 2301 movs r3, #1
8001b36: e0a4 b.n 8001c82 <_printf_i+0x1f6>
8001b38: 6820 ldr r0, [r4, #0]
8001b3a: 6829 ldr r1, [r5, #0]
8001b3c: 0606 lsls r6, r0, #24
8001b3e: f101 0304 add.w r3, r1, #4
8001b42: d50a bpl.n 8001b5a <_printf_i+0xce>
8001b44: 680e ldr r6, [r1, #0]
8001b46: 602b str r3, [r5, #0]
8001b48: 2e00 cmp r6, #0
8001b4a: da03 bge.n 8001b54 <_printf_i+0xc8>
8001b4c: 232d movs r3, #45 ; 0x2d
8001b4e: 4276 negs r6, r6
8001b50: f884 3043 strb.w r3, [r4, #67] ; 0x43
8001b54: 230a movs r3, #10
8001b56: 485e ldr r0, [pc, #376] ; (8001cd0 <_printf_i+0x244>)
8001b58: e019 b.n 8001b8e <_printf_i+0x102>
8001b5a: 680e ldr r6, [r1, #0]
8001b5c: f010 0f40 tst.w r0, #64 ; 0x40
8001b60: 602b str r3, [r5, #0]
8001b62: bf18 it ne
8001b64: b236 sxthne r6, r6
8001b66: e7ef b.n 8001b48 <_printf_i+0xbc>
8001b68: 682b ldr r3, [r5, #0]
8001b6a: 6820 ldr r0, [r4, #0]
8001b6c: 1d19 adds r1, r3, #4
8001b6e: 6029 str r1, [r5, #0]
8001b70: 0601 lsls r1, r0, #24
8001b72: d501 bpl.n 8001b78 <_printf_i+0xec>
8001b74: 681e ldr r6, [r3, #0]
8001b76: e002 b.n 8001b7e <_printf_i+0xf2>
8001b78: 0646 lsls r6, r0, #25
8001b7a: d5fb bpl.n 8001b74 <_printf_i+0xe8>
8001b7c: 881e ldrh r6, [r3, #0]
8001b7e: 2f6f cmp r7, #111 ; 0x6f
8001b80: bf0c ite eq
8001b82: 2308 moveq r3, #8
8001b84: 230a movne r3, #10
8001b86: 4852 ldr r0, [pc, #328] ; (8001cd0 <_printf_i+0x244>)
8001b88: 2100 movs r1, #0
8001b8a: f884 1043 strb.w r1, [r4, #67] ; 0x43
8001b8e: 6865 ldr r5, [r4, #4]
8001b90: 2d00 cmp r5, #0
8001b92: bfa8 it ge
8001b94: 6821 ldrge r1, [r4, #0]
8001b96: 60a5 str r5, [r4, #8]
8001b98: bfa4 itt ge
8001b9a: f021 0104 bicge.w r1, r1, #4
8001b9e: 6021 strge r1, [r4, #0]
8001ba0: b90e cbnz r6, 8001ba6 <_printf_i+0x11a>
8001ba2: 2d00 cmp r5, #0
8001ba4: d04d beq.n 8001c42 <_printf_i+0x1b6>
8001ba6: 4615 mov r5, r2
8001ba8: fbb6 f1f3 udiv r1, r6, r3
8001bac: fb03 6711 mls r7, r3, r1, r6
8001bb0: 5dc7 ldrb r7, [r0, r7]
8001bb2: f805 7d01 strb.w r7, [r5, #-1]!
8001bb6: 4637 mov r7, r6
8001bb8: 42bb cmp r3, r7
8001bba: 460e mov r6, r1
8001bbc: d9f4 bls.n 8001ba8 <_printf_i+0x11c>
8001bbe: 2b08 cmp r3, #8
8001bc0: d10b bne.n 8001bda <_printf_i+0x14e>
8001bc2: 6823 ldr r3, [r4, #0]
8001bc4: 07de lsls r6, r3, #31
8001bc6: d508 bpl.n 8001bda <_printf_i+0x14e>
8001bc8: 6923 ldr r3, [r4, #16]
8001bca: 6861 ldr r1, [r4, #4]
8001bcc: 4299 cmp r1, r3
8001bce: bfde ittt le
8001bd0: 2330 movle r3, #48 ; 0x30
8001bd2: f805 3c01 strble.w r3, [r5, #-1]
8001bd6: f105 35ff addle.w r5, r5, #4294967295
8001bda: 1b52 subs r2, r2, r5
8001bdc: 6122 str r2, [r4, #16]
8001bde: 464b mov r3, r9
8001be0: 4621 mov r1, r4
8001be2: 4640 mov r0, r8
8001be4: f8cd a000 str.w sl, [sp]
8001be8: aa03 add r2, sp, #12
8001bea: f7ff fedf bl 80019ac <_printf_common>
8001bee: 3001 adds r0, #1
8001bf0: d14c bne.n 8001c8c <_printf_i+0x200>
8001bf2: f04f 30ff mov.w r0, #4294967295
8001bf6: b004 add sp, #16
8001bf8: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
8001bfc: 4834 ldr r0, [pc, #208] ; (8001cd0 <_printf_i+0x244>)
8001bfe: f881 7045 strb.w r7, [r1, #69] ; 0x45
8001c02: 6829 ldr r1, [r5, #0]
8001c04: 6823 ldr r3, [r4, #0]
8001c06: f851 6b04 ldr.w r6, [r1], #4
8001c0a: 6029 str r1, [r5, #0]
8001c0c: 061d lsls r5, r3, #24
8001c0e: d514 bpl.n 8001c3a <_printf_i+0x1ae>
8001c10: 07df lsls r7, r3, #31
8001c12: bf44 itt mi
8001c14: f043 0320 orrmi.w r3, r3, #32
8001c18: 6023 strmi r3, [r4, #0]
8001c1a: b91e cbnz r6, 8001c24 <_printf_i+0x198>
8001c1c: 6823 ldr r3, [r4, #0]
8001c1e: f023 0320 bic.w r3, r3, #32
8001c22: 6023 str r3, [r4, #0]
8001c24: 2310 movs r3, #16
8001c26: e7af b.n 8001b88 <_printf_i+0xfc>
8001c28: 6823 ldr r3, [r4, #0]
8001c2a: f043 0320 orr.w r3, r3, #32
8001c2e: 6023 str r3, [r4, #0]
8001c30: 2378 movs r3, #120 ; 0x78
8001c32: 4828 ldr r0, [pc, #160] ; (8001cd4 <_printf_i+0x248>)
8001c34: f884 3045 strb.w r3, [r4, #69] ; 0x45
8001c38: e7e3 b.n 8001c02 <_printf_i+0x176>
8001c3a: 0659 lsls r1, r3, #25
8001c3c: bf48 it mi
8001c3e: b2b6 uxthmi r6, r6
8001c40: e7e6 b.n 8001c10 <_printf_i+0x184>
8001c42: 4615 mov r5, r2
8001c44: e7bb b.n 8001bbe <_printf_i+0x132>
8001c46: 682b ldr r3, [r5, #0]
8001c48: 6826 ldr r6, [r4, #0]
8001c4a: 1d18 adds r0, r3, #4
8001c4c: 6961 ldr r1, [r4, #20]
8001c4e: 6028 str r0, [r5, #0]
8001c50: 0635 lsls r5, r6, #24
8001c52: 681b ldr r3, [r3, #0]
8001c54: d501 bpl.n 8001c5a <_printf_i+0x1ce>
8001c56: 6019 str r1, [r3, #0]
8001c58: e002 b.n 8001c60 <_printf_i+0x1d4>
8001c5a: 0670 lsls r0, r6, #25
8001c5c: d5fb bpl.n 8001c56 <_printf_i+0x1ca>
8001c5e: 8019 strh r1, [r3, #0]
8001c60: 2300 movs r3, #0
8001c62: 4615 mov r5, r2
8001c64: 6123 str r3, [r4, #16]
8001c66: e7ba b.n 8001bde <_printf_i+0x152>
8001c68: 682b ldr r3, [r5, #0]
8001c6a: 2100 movs r1, #0
8001c6c: 1d1a adds r2, r3, #4
8001c6e: 602a str r2, [r5, #0]
8001c70: 681d ldr r5, [r3, #0]
8001c72: 6862 ldr r2, [r4, #4]
8001c74: 4628 mov r0, r5
8001c76: f000 f82f bl 8001cd8 <memchr>
8001c7a: b108 cbz r0, 8001c80 <_printf_i+0x1f4>
8001c7c: 1b40 subs r0, r0, r5
8001c7e: 6060 str r0, [r4, #4]
8001c80: 6863 ldr r3, [r4, #4]
8001c82: 6123 str r3, [r4, #16]
8001c84: 2300 movs r3, #0
8001c86: f884 3043 strb.w r3, [r4, #67] ; 0x43
8001c8a: e7a8 b.n 8001bde <_printf_i+0x152>
8001c8c: 462a mov r2, r5
8001c8e: 4649 mov r1, r9
8001c90: 4640 mov r0, r8
8001c92: 6923 ldr r3, [r4, #16]
8001c94: 47d0 blx sl
8001c96: 3001 adds r0, #1
8001c98: d0ab beq.n 8001bf2 <_printf_i+0x166>
8001c9a: 6823 ldr r3, [r4, #0]
8001c9c: 079b lsls r3, r3, #30
8001c9e: d413 bmi.n 8001cc8 <_printf_i+0x23c>
8001ca0: 68e0 ldr r0, [r4, #12]
8001ca2: 9b03 ldr r3, [sp, #12]
8001ca4: 4298 cmp r0, r3
8001ca6: bfb8 it lt
8001ca8: 4618 movlt r0, r3
8001caa: e7a4 b.n 8001bf6 <_printf_i+0x16a>
8001cac: 2301 movs r3, #1
8001cae: 4632 mov r2, r6
8001cb0: 4649 mov r1, r9
8001cb2: 4640 mov r0, r8
8001cb4: 47d0 blx sl
8001cb6: 3001 adds r0, #1
8001cb8: d09b beq.n 8001bf2 <_printf_i+0x166>
8001cba: 3501 adds r5, #1
8001cbc: 68e3 ldr r3, [r4, #12]
8001cbe: 9903 ldr r1, [sp, #12]
8001cc0: 1a5b subs r3, r3, r1
8001cc2: 42ab cmp r3, r5
8001cc4: dcf2 bgt.n 8001cac <_printf_i+0x220>
8001cc6: e7eb b.n 8001ca0 <_printf_i+0x214>
8001cc8: 2500 movs r5, #0
8001cca: f104 0619 add.w r6, r4, #25
8001cce: e7f5 b.n 8001cbc <_printf_i+0x230>
8001cd0: 0800200d .word 0x0800200d
8001cd4: 0800201e .word 0x0800201e
08001cd8 <memchr>:
8001cd8: 4603 mov r3, r0
8001cda: b510 push {r4, lr}
8001cdc: b2c9 uxtb r1, r1
8001cde: 4402 add r2, r0
8001ce0: 4293 cmp r3, r2
8001ce2: 4618 mov r0, r3
8001ce4: d101 bne.n 8001cea <memchr+0x12>
8001ce6: 2000 movs r0, #0
8001ce8: e003 b.n 8001cf2 <memchr+0x1a>
8001cea: 7804 ldrb r4, [r0, #0]
8001cec: 3301 adds r3, #1
8001cee: 428c cmp r4, r1
8001cf0: d1f6 bne.n 8001ce0 <memchr+0x8>
8001cf2: bd10 pop {r4, pc}
08001cf4 <memcpy>:
8001cf4: 440a add r2, r1
8001cf6: 4291 cmp r1, r2
8001cf8: f100 33ff add.w r3, r0, #4294967295
8001cfc: d100 bne.n 8001d00 <memcpy+0xc>
8001cfe: 4770 bx lr
8001d00: b510 push {r4, lr}
8001d02: f811 4b01 ldrb.w r4, [r1], #1
8001d06: 4291 cmp r1, r2
8001d08: f803 4f01 strb.w r4, [r3, #1]!
8001d0c: d1f9 bne.n 8001d02 <memcpy+0xe>
8001d0e: bd10 pop {r4, pc}
08001d10 <memmove>:
8001d10: 4288 cmp r0, r1
8001d12: b510 push {r4, lr}
8001d14: eb01 0402 add.w r4, r1, r2
8001d18: d902 bls.n 8001d20 <memmove+0x10>
8001d1a: 4284 cmp r4, r0
8001d1c: 4623 mov r3, r4
8001d1e: d807 bhi.n 8001d30 <memmove+0x20>
8001d20: 1e43 subs r3, r0, #1
8001d22: 42a1 cmp r1, r4
8001d24: d008 beq.n 8001d38 <memmove+0x28>
8001d26: f811 2b01 ldrb.w r2, [r1], #1
8001d2a: f803 2f01 strb.w r2, [r3, #1]!
8001d2e: e7f8 b.n 8001d22 <memmove+0x12>
8001d30: 4601 mov r1, r0
8001d32: 4402 add r2, r0
8001d34: 428a cmp r2, r1
8001d36: d100 bne.n 8001d3a <memmove+0x2a>
8001d38: bd10 pop {r4, pc}
8001d3a: f813 4d01 ldrb.w r4, [r3, #-1]!
8001d3e: f802 4d01 strb.w r4, [r2, #-1]!
8001d42: e7f7 b.n 8001d34 <memmove+0x24>
08001d44 <_free_r>:
8001d44: b538 push {r3, r4, r5, lr}
8001d46: 4605 mov r5, r0
8001d48: 2900 cmp r1, #0
8001d4a: d040 beq.n 8001dce <_free_r+0x8a>
8001d4c: f851 3c04 ldr.w r3, [r1, #-4]
8001d50: 1f0c subs r4, r1, #4
8001d52: 2b00 cmp r3, #0
8001d54: bfb8 it lt
8001d56: 18e4 addlt r4, r4, r3
8001d58: f000 f910 bl 8001f7c <__malloc_lock>
8001d5c: 4a1c ldr r2, [pc, #112] ; (8001dd0 <_free_r+0x8c>)
8001d5e: 6813 ldr r3, [r2, #0]
8001d60: b933 cbnz r3, 8001d70 <_free_r+0x2c>
8001d62: 6063 str r3, [r4, #4]
8001d64: 6014 str r4, [r2, #0]
8001d66: 4628 mov r0, r5
8001d68: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr}
8001d6c: f000 b90c b.w 8001f88 <__malloc_unlock>
8001d70: 42a3 cmp r3, r4
8001d72: d908 bls.n 8001d86 <_free_r+0x42>
8001d74: 6820 ldr r0, [r4, #0]
8001d76: 1821 adds r1, r4, r0
8001d78: 428b cmp r3, r1
8001d7a: bf01 itttt eq
8001d7c: 6819 ldreq r1, [r3, #0]
8001d7e: 685b ldreq r3, [r3, #4]
8001d80: 1809 addeq r1, r1, r0
8001d82: 6021 streq r1, [r4, #0]
8001d84: e7ed b.n 8001d62 <_free_r+0x1e>
8001d86: 461a mov r2, r3
8001d88: 685b ldr r3, [r3, #4]
8001d8a: b10b cbz r3, 8001d90 <_free_r+0x4c>
8001d8c: 42a3 cmp r3, r4
8001d8e: d9fa bls.n 8001d86 <_free_r+0x42>
8001d90: 6811 ldr r1, [r2, #0]
8001d92: 1850 adds r0, r2, r1
8001d94: 42a0 cmp r0, r4
8001d96: d10b bne.n 8001db0 <_free_r+0x6c>
8001d98: 6820 ldr r0, [r4, #0]
8001d9a: 4401 add r1, r0
8001d9c: 1850 adds r0, r2, r1
8001d9e: 4283 cmp r3, r0
8001da0: 6011 str r1, [r2, #0]
8001da2: d1e0 bne.n 8001d66 <_free_r+0x22>
8001da4: 6818 ldr r0, [r3, #0]
8001da6: 685b ldr r3, [r3, #4]
8001da8: 4401 add r1, r0
8001daa: 6011 str r1, [r2, #0]
8001dac: 6053 str r3, [r2, #4]
8001dae: e7da b.n 8001d66 <_free_r+0x22>
8001db0: d902 bls.n 8001db8 <_free_r+0x74>
8001db2: 230c movs r3, #12
8001db4: 602b str r3, [r5, #0]
8001db6: e7d6 b.n 8001d66 <_free_r+0x22>
8001db8: 6820 ldr r0, [r4, #0]
8001dba: 1821 adds r1, r4, r0
8001dbc: 428b cmp r3, r1
8001dbe: bf01 itttt eq
8001dc0: 6819 ldreq r1, [r3, #0]
8001dc2: 685b ldreq r3, [r3, #4]
8001dc4: 1809 addeq r1, r1, r0
8001dc6: 6021 streq r1, [r4, #0]
8001dc8: 6063 str r3, [r4, #4]
8001dca: 6054 str r4, [r2, #4]
8001dcc: e7cb b.n 8001d66 <_free_r+0x22>
8001dce: bd38 pop {r3, r4, r5, pc}
8001dd0: 200000d8 .word 0x200000d8
08001dd4 <sbrk_aligned>:
8001dd4: b570 push {r4, r5, r6, lr}
8001dd6: 4e0e ldr r6, [pc, #56] ; (8001e10 <sbrk_aligned+0x3c>)
8001dd8: 460c mov r4, r1
8001dda: 6831 ldr r1, [r6, #0]
8001ddc: 4605 mov r5, r0
8001dde: b911 cbnz r1, 8001de6 <sbrk_aligned+0x12>
8001de0: f000 f8bc bl 8001f5c <_sbrk_r>
8001de4: 6030 str r0, [r6, #0]
8001de6: 4621 mov r1, r4
8001de8: 4628 mov r0, r5
8001dea: f000 f8b7 bl 8001f5c <_sbrk_r>
8001dee: 1c43 adds r3, r0, #1
8001df0: d00a beq.n 8001e08 <sbrk_aligned+0x34>
8001df2: 1cc4 adds r4, r0, #3
8001df4: f024 0403 bic.w r4, r4, #3
8001df8: 42a0 cmp r0, r4
8001dfa: d007 beq.n 8001e0c <sbrk_aligned+0x38>
8001dfc: 1a21 subs r1, r4, r0
8001dfe: 4628 mov r0, r5
8001e00: f000 f8ac bl 8001f5c <_sbrk_r>
8001e04: 3001 adds r0, #1
8001e06: d101 bne.n 8001e0c <sbrk_aligned+0x38>
8001e08: f04f 34ff mov.w r4, #4294967295
8001e0c: 4620 mov r0, r4
8001e0e: bd70 pop {r4, r5, r6, pc}
8001e10: 200000dc .word 0x200000dc
08001e14 <_malloc_r>:
8001e14: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr}
8001e18: 1ccd adds r5, r1, #3
8001e1a: f025 0503 bic.w r5, r5, #3
8001e1e: 3508 adds r5, #8
8001e20: 2d0c cmp r5, #12
8001e22: bf38 it cc
8001e24: 250c movcc r5, #12
8001e26: 2d00 cmp r5, #0
8001e28: 4607 mov r7, r0
8001e2a: db01 blt.n 8001e30 <_malloc_r+0x1c>
8001e2c: 42a9 cmp r1, r5
8001e2e: d905 bls.n 8001e3c <_malloc_r+0x28>
8001e30: 230c movs r3, #12
8001e32: 2600 movs r6, #0
8001e34: 603b str r3, [r7, #0]
8001e36: 4630 mov r0, r6
8001e38: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc}
8001e3c: 4e2e ldr r6, [pc, #184] ; (8001ef8 <_malloc_r+0xe4>)
8001e3e: f000 f89d bl 8001f7c <__malloc_lock>
8001e42: 6833 ldr r3, [r6, #0]
8001e44: 461c mov r4, r3
8001e46: bb34 cbnz r4, 8001e96 <_malloc_r+0x82>
8001e48: 4629 mov r1, r5
8001e4a: 4638 mov r0, r7
8001e4c: f7ff ffc2 bl 8001dd4 <sbrk_aligned>
8001e50: 1c43 adds r3, r0, #1
8001e52: 4604 mov r4, r0
8001e54: d14d bne.n 8001ef2 <_malloc_r+0xde>
8001e56: 6834 ldr r4, [r6, #0]
8001e58: 4626 mov r6, r4
8001e5a: 2e00 cmp r6, #0
8001e5c: d140 bne.n 8001ee0 <_malloc_r+0xcc>
8001e5e: 6823 ldr r3, [r4, #0]
8001e60: 4631 mov r1, r6
8001e62: 4638 mov r0, r7
8001e64: eb04 0803 add.w r8, r4, r3
8001e68: f000 f878 bl 8001f5c <_sbrk_r>
8001e6c: 4580 cmp r8, r0
8001e6e: d13a bne.n 8001ee6 <_malloc_r+0xd2>
8001e70: 6821 ldr r1, [r4, #0]
8001e72: 3503 adds r5, #3
8001e74: 1a6d subs r5, r5, r1
8001e76: f025 0503 bic.w r5, r5, #3
8001e7a: 3508 adds r5, #8
8001e7c: 2d0c cmp r5, #12
8001e7e: bf38 it cc
8001e80: 250c movcc r5, #12
8001e82: 4638 mov r0, r7
8001e84: 4629 mov r1, r5
8001e86: f7ff ffa5 bl 8001dd4 <sbrk_aligned>
8001e8a: 3001 adds r0, #1
8001e8c: d02b beq.n 8001ee6 <_malloc_r+0xd2>
8001e8e: 6823 ldr r3, [r4, #0]
8001e90: 442b add r3, r5
8001e92: 6023 str r3, [r4, #0]
8001e94: e00e b.n 8001eb4 <_malloc_r+0xa0>
8001e96: 6822 ldr r2, [r4, #0]
8001e98: 1b52 subs r2, r2, r5
8001e9a: d41e bmi.n 8001eda <_malloc_r+0xc6>
8001e9c: 2a0b cmp r2, #11
8001e9e: d916 bls.n 8001ece <_malloc_r+0xba>
8001ea0: 1961 adds r1, r4, r5
8001ea2: 42a3 cmp r3, r4
8001ea4: 6025 str r5, [r4, #0]
8001ea6: bf18 it ne
8001ea8: 6059 strne r1, [r3, #4]
8001eaa: 6863 ldr r3, [r4, #4]
8001eac: bf08 it eq
8001eae: 6031 streq r1, [r6, #0]
8001eb0: 5162 str r2, [r4, r5]
8001eb2: 604b str r3, [r1, #4]
8001eb4: 4638 mov r0, r7
8001eb6: f104 060b add.w r6, r4, #11
8001eba: f000 f865 bl 8001f88 <__malloc_unlock>
8001ebe: f026 0607 bic.w r6, r6, #7
8001ec2: 1d23 adds r3, r4, #4
8001ec4: 1af2 subs r2, r6, r3
8001ec6: d0b6 beq.n 8001e36 <_malloc_r+0x22>
8001ec8: 1b9b subs r3, r3, r6
8001eca: 50a3 str r3, [r4, r2]
8001ecc: e7b3 b.n 8001e36 <_malloc_r+0x22>
8001ece: 6862 ldr r2, [r4, #4]
8001ed0: 42a3 cmp r3, r4
8001ed2: bf0c ite eq
8001ed4: 6032 streq r2, [r6, #0]
8001ed6: 605a strne r2, [r3, #4]
8001ed8: e7ec b.n 8001eb4 <_malloc_r+0xa0>
8001eda: 4623 mov r3, r4
8001edc: 6864 ldr r4, [r4, #4]
8001ede: e7b2 b.n 8001e46 <_malloc_r+0x32>
8001ee0: 4634 mov r4, r6
8001ee2: 6876 ldr r6, [r6, #4]
8001ee4: e7b9 b.n 8001e5a <_malloc_r+0x46>
8001ee6: 230c movs r3, #12
8001ee8: 4638 mov r0, r7
8001eea: 603b str r3, [r7, #0]
8001eec: f000 f84c bl 8001f88 <__malloc_unlock>
8001ef0: e7a1 b.n 8001e36 <_malloc_r+0x22>
8001ef2: 6025 str r5, [r4, #0]
8001ef4: e7de b.n 8001eb4 <_malloc_r+0xa0>
8001ef6: bf00 nop
8001ef8: 200000d8 .word 0x200000d8
08001efc <_realloc_r>:
8001efc: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr}
8001f00: 4680 mov r8, r0
8001f02: 4614 mov r4, r2
8001f04: 460e mov r6, r1
8001f06: b921 cbnz r1, 8001f12 <_realloc_r+0x16>
8001f08: 4611 mov r1, r2
8001f0a: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr}
8001f0e: f7ff bf81 b.w 8001e14 <_malloc_r>
8001f12: b92a cbnz r2, 8001f20 <_realloc_r+0x24>
8001f14: f7ff ff16 bl 8001d44 <_free_r>
8001f18: 4625 mov r5, r4
8001f1a: 4628 mov r0, r5
8001f1c: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc}
8001f20: f000 f838 bl 8001f94 <_malloc_usable_size_r>
8001f24: 4284 cmp r4, r0
8001f26: 4607 mov r7, r0
8001f28: d802 bhi.n 8001f30 <_realloc_r+0x34>
8001f2a: ebb4 0f50 cmp.w r4, r0, lsr #1
8001f2e: d812 bhi.n 8001f56 <_realloc_r+0x5a>
8001f30: 4621 mov r1, r4
8001f32: 4640 mov r0, r8
8001f34: f7ff ff6e bl 8001e14 <_malloc_r>
8001f38: 4605 mov r5, r0
8001f3a: 2800 cmp r0, #0
8001f3c: d0ed beq.n 8001f1a <_realloc_r+0x1e>
8001f3e: 42bc cmp r4, r7
8001f40: 4622 mov r2, r4
8001f42: 4631 mov r1, r6
8001f44: bf28 it cs
8001f46: 463a movcs r2, r7
8001f48: f7ff fed4 bl 8001cf4 <memcpy>
8001f4c: 4631 mov r1, r6
8001f4e: 4640 mov r0, r8
8001f50: f7ff fef8 bl 8001d44 <_free_r>
8001f54: e7e1 b.n 8001f1a <_realloc_r+0x1e>
8001f56: 4635 mov r5, r6
8001f58: e7df b.n 8001f1a <_realloc_r+0x1e>
...
08001f5c <_sbrk_r>:
8001f5c: b538 push {r3, r4, r5, lr}
8001f5e: 2300 movs r3, #0
8001f60: 4d05 ldr r5, [pc, #20] ; (8001f78 <_sbrk_r+0x1c>)
8001f62: 4604 mov r4, r0
8001f64: 4608 mov r0, r1
8001f66: 602b str r3, [r5, #0]
8001f68: f7fe f9dc bl 8000324 <_sbrk>
8001f6c: 1c43 adds r3, r0, #1
8001f6e: d102 bne.n 8001f76 <_sbrk_r+0x1a>
8001f70: 682b ldr r3, [r5, #0]
8001f72: b103 cbz r3, 8001f76 <_sbrk_r+0x1a>
8001f74: 6023 str r3, [r4, #0]
8001f76: bd38 pop {r3, r4, r5, pc}
8001f78: 200000e0 .word 0x200000e0
08001f7c <__malloc_lock>:
8001f7c: 4801 ldr r0, [pc, #4] ; (8001f84 <__malloc_lock+0x8>)
8001f7e: f000 b811 b.w 8001fa4 <__retarget_lock_acquire_recursive>
8001f82: bf00 nop
8001f84: 200000e4 .word 0x200000e4
08001f88 <__malloc_unlock>:
8001f88: 4801 ldr r0, [pc, #4] ; (8001f90 <__malloc_unlock+0x8>)
8001f8a: f000 b80c b.w 8001fa6 <__retarget_lock_release_recursive>
8001f8e: bf00 nop
8001f90: 200000e4 .word 0x200000e4
08001f94 <_malloc_usable_size_r>:
8001f94: f851 3c04 ldr.w r3, [r1, #-4]
8001f98: 1f18 subs r0, r3, #4
8001f9a: 2b00 cmp r3, #0
8001f9c: bfbc itt lt
8001f9e: 580b ldrlt r3, [r1, r0]
8001fa0: 18c0 addlt r0, r0, r3
8001fa2: 4770 bx lr
08001fa4 <__retarget_lock_acquire_recursive>:
8001fa4: 4770 bx lr
08001fa6 <__retarget_lock_release_recursive>:
8001fa6: 4770 bx lr
08001fa8 <_init>:
8001fa8: b5f8 push {r3, r4, r5, r6, r7, lr}
8001faa: bf00 nop
8001fac: bcf8 pop {r3, r4, r5, r6, r7}
8001fae: bc08 pop {r3}
8001fb0: 469e mov lr, r3
8001fb2: 4770 bx lr
08001fb4 <_fini>:
8001fb4: b5f8 push {r3, r4, r5, r6, r7, lr}
8001fb6: bf00 nop
8001fb8: bcf8 pop {r3, r4, r5, r6, r7}
8001fba: bc08 pop {r3}
8001fbc: 469e mov lr, r3
8001fbe: 4770 bx lr
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